| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_l2d_32kb_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_l2d_32kb_cust ( |
| 36 | waysel_c3, |
| 37 | waysel_err_c3, |
| 38 | set_c3, |
| 39 | coloff_c3, |
| 40 | coloff_c4_l, |
| 41 | coloff_c5, |
| 42 | rd_wr_c3, |
| 43 | readen_c5, |
| 44 | l2clk, |
| 45 | fuse_l2d_data_in_00, |
| 46 | fuse_l2d_rid_00, |
| 47 | fuse_l2d_wren_00, |
| 48 | fuse_l2d_reset_00_l, |
| 49 | sel_quad_00, |
| 50 | red_d_out_00, |
| 51 | fuse_l2d_data_in_01, |
| 52 | fuse_l2d_rid_01, |
| 53 | fuse_l2d_wren_01, |
| 54 | fuse_l2d_reset_01_l, |
| 55 | sel_quad_01, |
| 56 | red_d_out_01, |
| 57 | red_top_d_00, |
| 58 | red_top_d_01, |
| 59 | tcu_pce_ov, |
| 60 | tcu_pce, |
| 61 | se, |
| 62 | tcu_clk_stop, |
| 63 | wrd0lo_b_l, |
| 64 | wrd0hi_b_l, |
| 65 | wrd1lo_b_l, |
| 66 | wrd1hi_b_l, |
| 67 | ldin0lo_b, |
| 68 | ldin0hi_b, |
| 69 | ldin1lo_b, |
| 70 | ldin1hi_b, |
| 71 | worden_c3, |
| 72 | tstmodclk_l, |
| 73 | wee_l, |
| 74 | vnw_ary, |
| 75 | ldout0lo_b00, |
| 76 | ldout0hi_b00, |
| 77 | ldout1lo_b00, |
| 78 | ldout1hi_b00); |
| 79 | wire [7:0] waysel_top_c4; |
| 80 | wire [8:0] set_top_c3b; |
| 81 | wire coloff_top_c3b_l; |
| 82 | wire writeen_top_c3b; |
| 83 | wire [3:0] worden_top_c3b; |
| 84 | wire l1clk; |
| 85 | wire [9:0] red_addr_top_01; |
| 86 | wire [77:0] cred; |
| 87 | wire [19:0] sat_lo0_bc_l; |
| 88 | wire [19:0] sat_hi0_bc_l; |
| 89 | wire [18:0] sat_lo1_bc_l; |
| 90 | wire [18:0] sat_hi1_bc_l; |
| 91 | wire [7:0] waysel_bot_c4; |
| 92 | wire [8:0] set_bot_c3b; |
| 93 | wire coloff_bot_c3b_l; |
| 94 | wire writeen_bot_c3b; |
| 95 | wire [3:0] worden_bot_c3b; |
| 96 | wire [9:0] red_addr_bot_00; |
| 97 | wire [19:0] sab_lo0_bc_l; |
| 98 | wire [19:0] sab_hi0_bc_l; |
| 99 | wire [18:0] sab_lo1_bc_l; |
| 100 | wire [18:0] sab_hi1_bc_l; |
| 101 | |
| 102 | |
| 103 | |
| 104 | input [7:0] waysel_c3; |
| 105 | input waysel_err_c3; |
| 106 | input [8:0] set_c3; |
| 107 | input coloff_c3; |
| 108 | input coloff_c4_l; // check if 1 bit |
| 109 | input [1:0] coloff_c5; // check if 1 bit |
| 110 | input rd_wr_c3; |
| 111 | input readen_c5; |
| 112 | input l2clk; |
| 113 | |
| 114 | |
| 115 | input [9:0] fuse_l2d_data_in_00; |
| 116 | input [2:0] fuse_l2d_rid_00; |
| 117 | input fuse_l2d_wren_00; |
| 118 | input fuse_l2d_reset_00_l; |
| 119 | input sel_quad_00; |
| 120 | output [9:0] red_d_out_00; |
| 121 | |
| 122 | input [9:0] fuse_l2d_data_in_01; |
| 123 | input [2:0] fuse_l2d_rid_01; |
| 124 | input fuse_l2d_wren_01; |
| 125 | input fuse_l2d_reset_01_l; |
| 126 | input sel_quad_01; |
| 127 | output [9:0] red_d_out_01; |
| 128 | |
| 129 | input [9:0] red_top_d_00; |
| 130 | input [9:0] red_top_d_01; |
| 131 | |
| 132 | input tcu_pce_ov; |
| 133 | input tcu_pce; |
| 134 | input se; |
| 135 | input tcu_clk_stop; |
| 136 | input [19:0] wrd0lo_b_l; |
| 137 | input [19:0] wrd0hi_b_l; |
| 138 | input [18:0] wrd1lo_b_l; |
| 139 | input [18:0] wrd1hi_b_l; |
| 140 | input [19:0] ldin0lo_b; |
| 141 | input [19:0] ldin0hi_b; |
| 142 | input [18:0] ldin1lo_b; |
| 143 | input [18:0] ldin1hi_b; |
| 144 | input [3:0] worden_c3; |
| 145 | input tstmodclk_l; |
| 146 | input wee_l; |
| 147 | input vnw_ary; //NEW |
| 148 | |
| 149 | output [19:0] ldout0lo_b00; |
| 150 | output [19:0] ldout0hi_b00; |
| 151 | output [18:0] ldout1lo_b00; |
| 152 | output [18:0] ldout1hi_b00; |
| 153 | |
| 154 | |
| 155 | n2_l2d_16kb_cust set_top |
| 156 | ( |
| 157 | .waysel_c4 (waysel_top_c4[7:0]), |
| 158 | .waysel_err_c3 (waysel_err_c3), |
| 159 | .set_c3b (set_top_c3b[8:0]), |
| 160 | .coloff_c3b_l (coloff_top_c3b_l), |
| 161 | .coloff_c4_l (coloff_c4_l), |
| 162 | .coloff_c5 (coloff_c5[1:0]), |
| 163 | .wen_c3b (writeen_top_c3b), |
| 164 | .readen_c5 (readen_c5), |
| 165 | .worden_c3b (worden_top_c3b[3:0]), |
| 166 | .l1clk (l1clk), |
| 167 | .wrd_lo0_b_l (wrd0lo_b_l[19:0]), |
| 168 | .wrd_hi0_b_l (wrd0hi_b_l[19:0]), |
| 169 | .wrd_lo1_b_l (wrd1lo_b_l[18:0]), |
| 170 | .wrd_hi1_b_l (wrd1hi_b_l[18:0]), |
| 171 | // .bnken_lat (bnken_lat), |
| 172 | .red_adr (red_addr_top_01[9:0]), |
| 173 | .cred (cred[77:0]), |
| 174 | // .fuse_l2d_reset (fuse_l2d_reset_00_l_buf), |
| 175 | .saout_lo0_bc_l (sat_lo0_bc_l[19:0]), |
| 176 | .saout_hi0_bc_l (sat_hi0_bc_l[19:0]), |
| 177 | .saout_lo1_bc_l (sat_lo1_bc_l[18:0]), |
| 178 | .saout_hi1_bc_l (sat_hi1_bc_l[18:0]), |
| 179 | .tstmodclk_l (tstmodclk_l), //NEW |
| 180 | .wee_l (wee_l), //NEW |
| 181 | .vnw_ary (vnw_ary) //NEW |
| 182 | ); |
| 183 | |
| 184 | n2_l2d_16kb_cust set_bot |
| 185 | ( |
| 186 | .waysel_c4 (waysel_bot_c4[7:0]), |
| 187 | .waysel_err_c3 (waysel_err_c3), |
| 188 | .set_c3b (set_bot_c3b[8:0]), |
| 189 | .coloff_c3b_l (coloff_bot_c3b_l), |
| 190 | .coloff_c4_l (coloff_c4_l), |
| 191 | .coloff_c5 (coloff_c5[1:0]), |
| 192 | .wen_c3b (writeen_bot_c3b), |
| 193 | .readen_c5 (readen_c5), |
| 194 | .worden_c3b (worden_bot_c3b[3:0]), |
| 195 | .l1clk (l1clk), |
| 196 | .wrd_lo0_b_l (wrd0lo_b_l[19:0]), |
| 197 | .wrd_hi0_b_l (wrd0hi_b_l[19:0]), |
| 198 | .wrd_lo1_b_l (wrd1lo_b_l[18:0]), |
| 199 | .wrd_hi1_b_l (wrd1hi_b_l[18:0]), |
| 200 | .red_adr (red_addr_bot_00[9:0]), |
| 201 | // .bnken_lat (), |
| 202 | .cred (cred[77:0]), |
| 203 | // .fuse_l2d_reset (fuse_l2d_reset_01_l_buf), |
| 204 | .saout_lo0_bc_l (sab_lo0_bc_l[19:0]), |
| 205 | .saout_hi0_bc_l (sab_hi0_bc_l[19:0]), |
| 206 | .saout_lo1_bc_l (sab_lo1_bc_l[18:0]), |
| 207 | .saout_hi1_bc_l (sab_hi1_bc_l[18:0]), |
| 208 | .tstmodclk_l (tstmodclk_l), //NEW |
| 209 | .wee_l (wee_l), //NEW |
| 210 | .vnw_ary (vnw_ary) //NEW |
| 211 | ); |
| 212 | |
| 213 | |
| 214 | n2_l2d_dmux78_cust data_mux |
| 215 | ( |
| 216 | .waysel_c3 (waysel_c3[7:0]), // should be 15:0 |
| 217 | .set_c3 (set_c3[8:0]), |
| 218 | .coloff_c3 (coloff_c3), |
| 219 | // .coloff_c4_l (coloff_c4_l), |
| 220 | // .coloff_c5 (coloff_c5[1:0]), |
| 221 | .rd_wr_c3 (rd_wr_c3), |
| 222 | // .readen_c5 (readen_c5), |
| 223 | .worden_c3 (worden_c3[3:0]), |
| 224 | .l2clk (l2clk), |
| 225 | .tcu_pce_ov (tcu_pce_ov), |
| 226 | .tcu_pce (tcu_pce), |
| 227 | .se (se), |
| 228 | .tcu_clk_stop (tcu_clk_stop), |
| 229 | .waysel_top_c4 (waysel_top_c4[7:0]), |
| 230 | .waysel_bot_c4 (waysel_bot_c4[7:0]), |
| 231 | .set_top_c3b (set_top_c3b[8:0]), |
| 232 | .set_bot_c3b (set_bot_c3b[8:0]), |
| 233 | // .coloff_top_c3b_l (coloff_top_c3b_l), |
| 234 | // .coloff_bot_c3b_l (coloff_bot_c3b_l), |
| 235 | // .coloff_top_c4_l (coloff_top_c4_l), |
| 236 | // .coloff_bot_c4_l (coloff_bot_c4_l), |
| 237 | // .coloff_top_c5 (coloff_top_c5), |
| 238 | // .coloff_bot_c5 (coloff_bot_c5), |
| 239 | .writeen_top_c3b (writeen_top_c3b), |
| 240 | .writeen_bot_c3b (writeen_bot_c3b), |
| 241 | // .readen_top_c5 (readen_top_c5), |
| 242 | // .readen_bot_c5 (readen_bot_c5), |
| 243 | .l1clk (l1clk), |
| 244 | .worden_top_c3b (worden_top_c3b[3:0]), |
| 245 | .worden_bot_c3b (worden_bot_c3b[3:0]), |
| 246 | .sat_lo0_bc_l (sat_lo0_bc_l[19:0]), |
| 247 | .sat_hi0_bc_l (sat_hi0_bc_l[19:0]), |
| 248 | .sat_lo1_bc_l (sat_lo1_bc_l[18:0]), |
| 249 | .sat_hi1_bc_l (sat_hi1_bc_l[18:0]), |
| 250 | .sab_lo0_bc_l (sab_lo0_bc_l[19:0]), |
| 251 | .sab_hi0_bc_l (sab_hi0_bc_l[19:0]), |
| 252 | .sab_lo1_bc_l (sab_lo1_bc_l[18:0]), |
| 253 | .sab_hi1_bc_l (sab_hi1_bc_l[18:0]), |
| 254 | .ldin0lo_b (ldin0lo_b[19:0]), |
| 255 | .ldin0hi_b (ldin0hi_b[19:0]), |
| 256 | .ldin1lo_b (ldin1lo_b[18:0]), |
| 257 | .ldin1hi_b (ldin1hi_b[18:0]), |
| 258 | // .bnken_lat (bnken_lat), |
| 259 | .ldout0lo_b (ldout0lo_b00[19:0]), |
| 260 | .ldout1lo_b (ldout1lo_b00[18:0]), |
| 261 | .ldout0hi_b (ldout0hi_b00[19:0]), |
| 262 | .ldout1hi_b (ldout1hi_b00[18:0]), |
| 263 | .red_d_out_00 (red_d_out_00[9:0]), |
| 264 | .red_d_in_00 (fuse_l2d_data_in_00[9:0]), |
| 265 | .fuse_l2d_rid_00 (fuse_l2d_rid_00[2:0]), |
| 266 | .fuse_l2d_wren_00 (fuse_l2d_wren_00), |
| 267 | .fuse_l2d_reset_00_l (fuse_l2d_reset_00_l), |
| 268 | .sel_quad_00 (sel_quad_00), |
| 269 | .red_d_out_01 (red_d_out_01[9:0]), |
| 270 | .red_top_d_00 (red_top_d_00[9:0]), |
| 271 | .red_top_d_01 (red_top_d_01[9:0]), |
| 272 | .red_d_in_01 (fuse_l2d_data_in_01[9:0]), |
| 273 | .fuse_l2d_rid_01 (fuse_l2d_rid_01[2:0]), |
| 274 | .fuse_l2d_wren_01 (fuse_l2d_wren_01), |
| 275 | .fuse_l2d_reset_01_l (fuse_l2d_reset_01_l), |
| 276 | .sel_quad_01 (sel_quad_01), |
| 277 | .cred (cred[77:0]), |
| 278 | // .fuse_l2d_reset_00_l_buf (fuse_l2d_reset_00_l_buf), |
| 279 | // .fuse_l2d_reset_01_l_buf (fuse_l2d_reset_01_l_buf), |
| 280 | .red_addr_top (red_addr_top_01), |
| 281 | .red_addr_bot (red_addr_bot_00), |
| 282 | .coloff_c4_l(coloff_c4_l), |
| 283 | .coloff_top_c3b_l(coloff_top_c3b_l), |
| 284 | .coloff_bot_c3b_l(coloff_bot_c3b_l) |
| 285 | ); |
| 286 | |
| 287 | endmodule |
| 288 | |
| 289 | |
| 290 | |
| 291 | |
| 292 | module n2_l2d_16kb_cust ( |
| 293 | waysel_c4, |
| 294 | waysel_err_c3, |
| 295 | set_c3b, |
| 296 | coloff_c3b_l, |
| 297 | coloff_c4_l, |
| 298 | coloff_c5, |
| 299 | wen_c3b, |
| 300 | readen_c5, |
| 301 | worden_c3b, |
| 302 | l1clk, |
| 303 | wrd_lo0_b_l, |
| 304 | wrd_lo1_b_l, |
| 305 | wrd_hi0_b_l, |
| 306 | wrd_hi1_b_l, |
| 307 | red_adr, |
| 308 | cred, |
| 309 | tstmodclk_l, |
| 310 | wee_l, |
| 311 | vnw_ary, |
| 312 | saout_lo0_bc_l, |
| 313 | saout_lo1_bc_l, |
| 314 | saout_hi0_bc_l, |
| 315 | saout_hi1_bc_l); |
| 316 | wire coloff_c3b_l_unused; |
| 317 | wire bank_select; |
| 318 | wire coloff_c4; |
| 319 | wire [7:0] set_c4; |
| 320 | wire [1:0] spare_word_enable; |
| 321 | wire select_red_odd; |
| 322 | wire select_red_even; |
| 323 | |
| 324 | |
| 325 | |
| 326 | input [7:0] waysel_c4; |
| 327 | input waysel_err_c3; // Active when multiple way sel is on |
| 328 | input [8:0] set_c3b; // After b-latch |
| 329 | input coloff_c3b_l; // After b-latch+inv |
| 330 | input coloff_c4_l; // stage+inv |
| 331 | input [1:0] coloff_c5; // 2-stage |
| 332 | input wen_c3b; // Write-enable, after b-latch |
| 333 | input readen_c5; // |
| 334 | input [3:0] worden_c3b; // After b-latch |
| 335 | input l1clk; // After l1clk hdr |
| 336 | input [19:0] wrd_lo0_b_l; // |
| 337 | input [18:0] wrd_lo1_b_l; // |
| 338 | input [19:0] wrd_hi0_b_l; // |
| 339 | input [18:0] wrd_hi1_b_l; // |
| 340 | input [9:0] red_adr; // Redudancy address |
| 341 | input [77:0] cred; // Redudancy address |
| 342 | input tstmodclk_l; //NEW |
| 343 | input wee_l; //NEW |
| 344 | input vnw_ary; //NEW |
| 345 | |
| 346 | //output bnken_lat; // Address latch enable (1.5cycle) |
| 347 | output [19:0] saout_lo0_bc_l; // C5bc output from senseamp |
| 348 | output [18:0] saout_lo1_bc_l; // C5bc output from senseamp |
| 349 | output [19:0] saout_hi0_bc_l; // C5bc output from senseamp |
| 350 | output [18:0] saout_hi1_bc_l; // C5bc output from senseamp |
| 351 | |
| 352 | //reg rd_data_out_sel_c5b; |
| 353 | //reg select_read_data_c5b; |
| 354 | reg select_read_data_c5b_hi_rgt; |
| 355 | reg select_read_data_c5b_hi_lft; |
| 356 | reg select_read_data_c5b_lo_rgt; |
| 357 | reg select_read_data_c5b_lo_lft; |
| 358 | reg select_read_data_all_c5b; |
| 359 | reg select_read_red_all_c5b; |
| 360 | |
| 361 | //reg select_read_red_c5b; |
| 362 | reg select_read_red_c5b_hi_rgt; |
| 363 | reg select_read_red_c5b_hi_lft; |
| 364 | reg select_read_red_c5b_lo_rgt; |
| 365 | reg select_read_red_c5b_lo_lft; |
| 366 | |
| 367 | //reg bnken_lat; |
| 368 | |
| 369 | reg [19:0] saout_lo0_bc_l; // C5bc output from senseamp |
| 370 | reg [18:0] saout_lo1_bc_l; // C5bc output from senseamp |
| 371 | reg [19:0] saout_hi0_bc_l; // C5bc output from senseamp |
| 372 | reg [18:0] saout_hi1_bc_l; // C5bc output from senseamp |
| 373 | |
| 374 | reg [79:0] read_data; |
| 375 | wire [79:0] rd_data; |
| 376 | wire [79:0] wr_data; |
| 377 | reg rd_spare_0,rd_spare_1; |
| 378 | wire wr_spare_0,wr_spare_1; |
| 379 | |
| 380 | wire [19:0] saout_hi0_b_out_l, saout_lo0_b_out_l; |
| 381 | wire [18:0] saout_hi1_b_out_l, saout_lo1_b_out_l; |
| 382 | wire [19:0] red_lo0_b_out_l; |
| 383 | wire [18:0] red_lo1_b_out_l; |
| 384 | wire [19:0] red_hi0_b_out_l; |
| 385 | wire [18:0] red_hi1_b_out_l; |
| 386 | |
| 387 | wire [1:0] coloff_c5_rgt; |
| 388 | wire [1:0] coloff_c5_lft; |
| 389 | wire red_sel_rgt; |
| 390 | wire red_sel_lft; |
| 391 | |
| 392 | |
| 393 | |
| 394 | |
| 395 | reg [19:0] mem_lo0_way0 [255:0]; |
| 396 | reg [18:0] mem_lo1_way0 [255:0]; |
| 397 | reg [19:0] mem_hi0_way0 [255:0]; |
| 398 | reg [18:0] mem_hi1_way0 [255:0]; |
| 399 | reg [255:0] mem_way0_spare_0; |
| 400 | reg [255:0] mem_way0_spare_1; |
| 401 | |
| 402 | reg [19:0] mem_lo0_way1 [255:0]; |
| 403 | reg [18:0] mem_lo1_way1 [255:0]; |
| 404 | reg [19:0] mem_hi0_way1 [255:0]; |
| 405 | reg [18:0] mem_hi1_way1 [255:0]; |
| 406 | reg [255:0] mem_way1_spare_0; |
| 407 | reg [255:0] mem_way1_spare_1; |
| 408 | |
| 409 | reg [19:0] mem_lo0_way2 [255:0]; |
| 410 | reg [18:0] mem_lo1_way2 [255:0]; |
| 411 | reg [19:0] mem_hi0_way2 [255:0]; |
| 412 | reg [18:0] mem_hi1_way2 [255:0]; |
| 413 | reg [255:0] mem_way2_spare_0; |
| 414 | reg [255:0] mem_way2_spare_1; |
| 415 | |
| 416 | |
| 417 | reg [19:0] mem_lo0_way3 [255:0]; |
| 418 | reg [18:0] mem_lo1_way3 [255:0]; |
| 419 | reg [19:0] mem_hi0_way3 [255:0]; |
| 420 | reg [18:0] mem_hi1_way3 [255:0]; |
| 421 | reg [255:0] mem_way3_spare_0; |
| 422 | reg [255:0] mem_way3_spare_1; |
| 423 | |
| 424 | |
| 425 | reg [19:0] mem_lo0_way4 [255:0]; |
| 426 | reg [18:0] mem_lo1_way4 [255:0]; |
| 427 | reg [19:0] mem_hi0_way4 [255:0]; |
| 428 | reg [18:0] mem_hi1_way4 [255:0]; |
| 429 | reg [255:0] mem_way4_spare_0; |
| 430 | reg [255:0] mem_way4_spare_1; |
| 431 | |
| 432 | |
| 433 | reg [19:0] mem_lo0_way5 [255:0]; |
| 434 | reg [18:0] mem_lo1_way5 [255:0]; |
| 435 | reg [19:0] mem_hi0_way5 [255:0]; |
| 436 | reg [18:0] mem_hi1_way5 [255:0]; |
| 437 | reg [255:0] mem_way5_spare_0; |
| 438 | reg [255:0] mem_way5_spare_1; |
| 439 | |
| 440 | |
| 441 | reg [19:0] mem_lo0_way6 [255:0]; |
| 442 | reg [18:0] mem_lo1_way6 [255:0]; |
| 443 | reg [19:0] mem_hi0_way6 [255:0]; |
| 444 | reg [18:0] mem_hi1_way6 [255:0]; |
| 445 | reg [255:0] mem_way6_spare_0; |
| 446 | reg [255:0] mem_way6_spare_1; |
| 447 | |
| 448 | |
| 449 | reg [19:0] mem_lo0_way7 [255:0]; |
| 450 | reg [18:0] mem_lo1_way7 [255:0]; |
| 451 | reg [19:0] mem_hi0_way7 [255:0]; |
| 452 | reg [18:0] mem_hi1_way7 [255:0]; |
| 453 | reg [255:0] mem_way7_spare_0; |
| 454 | reg [255:0] mem_way7_spare_1; |
| 455 | |
| 456 | //reg bnken_lat_c52; |
| 457 | reg [19:0] saout_lo0_bc; // C5bc output from senseamp |
| 458 | reg [18:0] saout_lo1_bc; // C5bc output from senseamp |
| 459 | reg [19:0] saout_hi0_bc; // C5bc output from senseamp |
| 460 | reg [18:0] saout_hi1_bc; // C5bc output from senseamp |
| 461 | |
| 462 | |
| 463 | //reg [19:0] saout_lo0_bc_d; // C5bc output from senseamp |
| 464 | //reg [18:0] saout_lo1_bc_d; // C5bc output from senseamp |
| 465 | //reg [19:0] saout_hi0_bc_d; // C5bc output from senseamp |
| 466 | //reg [18:0] saout_hi1_bc_d; // C5bc output from senseamp |
| 467 | |
| 468 | //reg set_banken_lat, reset_banken_lat; |
| 469 | |
| 470 | reg [19:0] saout_lo0_bc_c5b_l; |
| 471 | reg [18:0] saout_lo1_bc_c5b_l; |
| 472 | reg [19:0] saout_hi0_bc_c5b_l; |
| 473 | reg [18:0] saout_hi1_bc_c5b_l; |
| 474 | |
| 475 | reg [19:0] saout_lo0_bc_d_l; |
| 476 | reg [18:0] saout_lo1_bc_d_l; |
| 477 | reg [19:0] saout_hi0_bc_d_l; |
| 478 | reg [18:0] saout_hi1_bc_d_l; |
| 479 | |
| 480 | |
| 481 | assign coloff_c3b_l_unused = coloff_c3b_l; |
| 482 | |
| 483 | |
| 484 | //always@(posedge l1clk) |
| 485 | //begin |
| 486 | // if(~coloff_c3b_l) |
| 487 | // set_banken_lat <= 1'b1; |
| 488 | // else set_banken_lat <= 1'b0; |
| 489 | //end |
| 490 | // |
| 491 | //always@(negedge l1clk) |
| 492 | //begin |
| 493 | // if(coloff_c4_l) |
| 494 | // reset_banken_lat <= 1'b1; |
| 495 | // else reset_banken_lat <= 1'b0; |
| 496 | //end |
| 497 | // |
| 498 | //always@(set_banken_lat or reset_banken_lat) |
| 499 | //begin |
| 500 | // if(set_banken_lat ) |
| 501 | // bnken_lat <= 1'b1; |
| 502 | // else if(reset_banken_lat ) |
| 503 | // bnken_lat <= 1'b0; |
| 504 | //end |
| 505 | |
| 506 | |
| 507 | reg [7:0] waysel_c5; |
| 508 | reg [8:0] index_c4; |
| 509 | reg [8:0] set_c5; |
| 510 | reg wen_c4; |
| 511 | reg [3:0] worden_c4; |
| 512 | |
| 513 | |
| 514 | |
| 515 | reg bank_select_c5; |
| 516 | reg waysel_err_c3b, waysel_err_c4,waysel_err_c5; |
| 517 | |
| 518 | always@(l1clk or coloff_c4_l) |
| 519 | begin |
| 520 | if(~l1clk & coloff_c4_l) |
| 521 | waysel_err_c3b <= waysel_err_c3; |
| 522 | end |
| 523 | |
| 524 | |
| 525 | |
| 526 | |
| 527 | |
| 528 | always@(posedge l1clk) |
| 529 | begin |
| 530 | waysel_err_c4 <= waysel_err_c3b; |
| 531 | waysel_err_c5 <= waysel_err_c4; |
| 532 | waysel_c5[7:0] <= waysel_c4[7:0]; |
| 533 | index_c4[8:0] <= set_c3b[8:0]; |
| 534 | set_c5[8:0] <= index_c4[8:0]; |
| 535 | worden_c4[3:0] <= worden_c3b[3:0]; |
| 536 | wen_c4 <= wen_c3b; |
| 537 | bank_select_c5 <= bank_select; |
| 538 | end |
| 539 | |
| 540 | |
| 541 | assign coloff_c4 = ~coloff_c4_l; |
| 542 | assign bank_select = index_c4[8]; |
| 543 | |
| 544 | //reg [19:0] saout_lo0_bc_c5b; |
| 545 | //reg [18:0] saout_lo1_bc_c5b; |
| 546 | //reg [19:0] saout_hi0_bc_c5b; |
| 547 | //reg [18:0] saout_hi1_bc_c5b; |
| 548 | |
| 549 | |
| 550 | |
| 551 | |
| 552 | |
| 553 | |
| 554 | assign set_c4[7:0] = index_c4[7:0]; |
| 555 | wire [19:0] wrd_lo0_a; |
| 556 | wire [19:0] wrd_hi0_a; |
| 557 | wire [18:0] wrd_lo1_a; |
| 558 | wire [18:0] wrd_hi1_a; |
| 559 | |
| 560 | reg [19:0] wrd_lo0_a_reg; |
| 561 | reg [19:0] wrd_hi0_a_reg; |
| 562 | reg [18:0] wrd_lo1_a_reg; |
| 563 | reg [18:0] wrd_hi1_a_reg; |
| 564 | |
| 565 | |
| 566 | always@(posedge l1clk) |
| 567 | begin |
| 568 | wrd_lo0_a_reg[19:0] <= ~wrd_lo0_b_l[19:0]; |
| 569 | wrd_hi0_a_reg[19:0] <= ~wrd_hi0_b_l[19:0]; |
| 570 | wrd_lo1_a_reg[18:0] <= ~wrd_lo1_b_l[18:0]; |
| 571 | wrd_hi1_a_reg[18:0] <= ~wrd_hi1_b_l[18:0]; |
| 572 | end |
| 573 | |
| 574 | |
| 575 | |
| 576 | // COL redudancy |
| 577 | |
| 578 | //reg [255:0] red_reg1; |
| 579 | //reg [255:0] red_reg2; |
| 580 | |
| 581 | wire [79:0] cred_mod; |
| 582 | |
| 583 | |
| 584 | assign cred_mod[79:0] = {cred[77:59],1'b0,cred[58:19],1'b0,cred[18:0]}; |
| 585 | |
| 586 | |
| 587 | //assign spare_word_enable[1] = cred_mod[19] ? worden_c4[3] : worden_c4[2]; |
| 588 | //assign spare_word_enable[0] = cred_mod[59] ? worden_c4[3] : worden_c4[2]; |
| 589 | |
| 590 | |
| 591 | assign wr_data[19:0] = |
| 592 | {wr_spare_0, wrd_lo1_a_reg[4], wrd_hi0_a_reg[4],wrd_lo0_a_reg[4], |
| 593 | wrd_hi1_a_reg[3], wrd_lo1_a_reg[3], wrd_hi0_a_reg[3],wrd_lo0_a_reg[3], |
| 594 | wrd_hi1_a_reg[2], wrd_lo1_a_reg[2], wrd_hi0_a_reg[2],wrd_lo0_a_reg[2], |
| 595 | wrd_hi1_a_reg[1], wrd_lo1_a_reg[1], wrd_hi0_a_reg[1],wrd_lo0_a_reg[1], |
| 596 | wrd_hi1_a_reg[0], wrd_lo1_a_reg[0], wrd_hi0_a_reg[0],wrd_lo0_a_reg[0]}; |
| 597 | |
| 598 | assign wr_data[39:20] = { |
| 599 | wrd_lo1_a_reg[9], wrd_hi0_a_reg[9],wrd_lo0_a_reg[9], |
| 600 | wrd_hi1_a_reg[8], wrd_lo1_a_reg[8], wrd_hi0_a_reg[8],wrd_lo0_a_reg[8], |
| 601 | wrd_hi1_a_reg[7], wrd_lo1_a_reg[7], wrd_hi0_a_reg[7],wrd_lo0_a_reg[7], |
| 602 | wrd_hi1_a_reg[6], wrd_lo1_a_reg[6], wrd_hi0_a_reg[6],wrd_lo0_a_reg[6], |
| 603 | wrd_hi1_a_reg[5], wrd_lo1_a_reg[5], wrd_hi0_a_reg[5],wrd_lo0_a_reg[5], wrd_hi1_a_reg[4]}; |
| 604 | |
| 605 | |
| 606 | assign wr_data[59:40] = { |
| 607 | wrd_lo1_a_reg[14], wrd_hi0_a_reg[14],wrd_lo0_a_reg[14], |
| 608 | wrd_hi1_a_reg[13], wrd_lo1_a_reg[13], wrd_hi0_a_reg[13],wrd_lo0_a_reg[13], |
| 609 | wrd_hi1_a_reg[12], wrd_lo1_a_reg[12], wrd_hi0_a_reg[12],wrd_lo0_a_reg[12], |
| 610 | wrd_hi1_a_reg[11], wrd_lo1_a_reg[11], wrd_hi0_a_reg[11],wrd_lo0_a_reg[11], |
| 611 | wrd_hi1_a_reg[10], wrd_lo1_a_reg[10], wrd_hi0_a_reg[10],wrd_lo0_a_reg[10], wrd_hi1_a_reg[9]}; |
| 612 | |
| 613 | assign wr_data[79:60] = { |
| 614 | wrd_hi0_a_reg[19], wrd_lo0_a_reg[19], |
| 615 | wrd_hi1_a_reg[18], wrd_lo1_a_reg[18], wrd_hi0_a_reg[18],wrd_lo0_a_reg[18], |
| 616 | wrd_hi1_a_reg[17], wrd_lo1_a_reg[17], wrd_hi0_a_reg[17],wrd_lo0_a_reg[17], |
| 617 | wrd_hi1_a_reg[16], wrd_lo1_a_reg[16], wrd_hi0_a_reg[16],wrd_lo0_a_reg[16], |
| 618 | wrd_hi1_a_reg[15], wrd_lo1_a_reg[15], wrd_hi0_a_reg[15],wrd_lo0_a_reg[15], wrd_hi1_a_reg[14],wr_spare_1}; |
| 619 | |
| 620 | |
| 621 | integer i; |
| 622 | reg [80:0] data; |
| 623 | |
| 624 | always@(cred_mod or wr_data) |
| 625 | begin |
| 626 | if (~cred_mod[0]) begin |
| 627 | data[0] = wr_data[0]; |
| 628 | end |
| 629 | |
| 630 | for(i=0; i<18; i=i+1) |
| 631 | begin |
| 632 | data[i+1] = cred_mod[i] ? wr_data[i] : wr_data[i+1]; |
| 633 | end |
| 634 | |
| 635 | data[19] = cred_mod[18] ? wr_data[18] : cred_mod[20] ? wr_data[20] : 1'b0; |
| 636 | |
| 637 | for(i=21;i<40;i=i+1) |
| 638 | begin |
| 639 | data[i-1] = cred_mod[i] ? wr_data[i] : wr_data[i-1]; |
| 640 | end |
| 641 | |
| 642 | |
| 643 | if (~cred_mod[39]) begin |
| 644 | data[39] = wr_data[39]; |
| 645 | end |
| 646 | |
| 647 | if (~cred_mod[40]) begin |
| 648 | data[40] = wr_data[40]; |
| 649 | end |
| 650 | |
| 651 | for(i=40;i<59;i=i+1) |
| 652 | begin |
| 653 | data[i+1] = cred_mod[i] ? wr_data[i] : wr_data[i+1]; |
| 654 | end |
| 655 | |
| 656 | data[60] = cred_mod[59] ? wr_data[59] : cred_mod[61] ? wr_data[61] : 1'b0; |
| 657 | |
| 658 | for(i=62;i<80;i=i+1) |
| 659 | begin |
| 660 | data[i-1] = cred_mod[i] ? wr_data[i] : wr_data[i-1]; |
| 661 | end |
| 662 | |
| 663 | if (~cred_mod[79]) begin |
| 664 | data[79] = wr_data[79]; |
| 665 | end |
| 666 | |
| 667 | end |
| 668 | |
| 669 | |
| 670 | assign { wrd_hi0_a[19], wrd_lo0_a[19], |
| 671 | wrd_hi1_a[18], wrd_lo1_a[18], wrd_hi0_a[18],wrd_lo0_a[18], |
| 672 | wrd_hi1_a[17], wrd_lo1_a[17], wrd_hi0_a[17],wrd_lo0_a[17], |
| 673 | wrd_hi1_a[16], wrd_lo1_a[16], wrd_hi0_a[16],wrd_lo0_a[16], |
| 674 | wrd_hi1_a[15], wrd_lo1_a[15], wrd_hi0_a[15],wrd_lo0_a[15], |
| 675 | wrd_hi1_a[14],wr_spare_1} = data[79:60]; |
| 676 | |
| 677 | assign { |
| 678 | wrd_lo1_a[14], wrd_hi0_a[14],wrd_lo0_a[14], |
| 679 | wrd_hi1_a[13], wrd_lo1_a[13], wrd_hi0_a[13],wrd_lo0_a[13], |
| 680 | wrd_hi1_a[12], wrd_lo1_a[12], wrd_hi0_a[12],wrd_lo0_a[12], |
| 681 | wrd_hi1_a[11], wrd_lo1_a[11], wrd_hi0_a[11],wrd_lo0_a[11], |
| 682 | wrd_hi1_a[10], wrd_lo1_a[10], wrd_hi0_a[10],wrd_lo0_a[10],wrd_hi1_a[9]} = data[59:40]; |
| 683 | |
| 684 | assign { |
| 685 | wrd_lo1_a[9], wrd_hi0_a[9],wrd_lo0_a[9], |
| 686 | wrd_hi1_a[8], wrd_lo1_a[8], wrd_hi0_a[8],wrd_lo0_a[8], |
| 687 | wrd_hi1_a[7], wrd_lo1_a[7], wrd_hi0_a[7],wrd_lo0_a[7], |
| 688 | wrd_hi1_a[6], wrd_lo1_a[6], wrd_hi0_a[6],wrd_lo0_a[6], |
| 689 | wrd_hi1_a[5], wrd_lo1_a[5], wrd_hi0_a[5],wrd_lo0_a[5], wrd_hi1_a[4]} = data[39:20]; |
| 690 | |
| 691 | assign { |
| 692 | wr_spare_0, wrd_lo1_a[4], wrd_hi0_a[4],wrd_lo0_a[4], |
| 693 | wrd_hi1_a[3], wrd_lo1_a[3], wrd_hi0_a[3],wrd_lo0_a[3], |
| 694 | wrd_hi1_a[2], wrd_lo1_a[2], wrd_hi0_a[2],wrd_lo0_a[2], |
| 695 | wrd_hi1_a[1], wrd_lo1_a[1], wrd_hi0_a[1],wrd_lo0_a[1], |
| 696 | wrd_hi1_a[0], wrd_lo1_a[0], wrd_hi0_a[0],wrd_lo0_a[0]} = data[19:0]; |
| 697 | |
| 698 | |
| 699 | |
| 700 | wire [79:0] worden_data; |
| 701 | wire [19:0] worden_lo0; |
| 702 | wire [19:0] worden_hi0; |
| 703 | wire [18:0] worden_lo1; |
| 704 | wire [18:0] worden_hi1; |
| 705 | |
| 706 | |
| 707 | assign worden_data[19:0] = |
| 708 | {spare_word_enable[0], worden_c4[2], worden_c4[1],worden_c4[0], |
| 709 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 710 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 711 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 712 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0]}; |
| 713 | |
| 714 | assign worden_data[39:20] = { |
| 715 | worden_c4[2], worden_c4[1],worden_c4[0], |
| 716 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 717 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 718 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 719 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3]}; |
| 720 | |
| 721 | |
| 722 | assign worden_data[59:40] = { |
| 723 | worden_c4[2], worden_c4[1],worden_c4[0], |
| 724 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 725 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 726 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 727 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3]}; |
| 728 | |
| 729 | assign worden_data[79:60] = { |
| 730 | worden_c4[1],worden_c4[0], |
| 731 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 732 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 733 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], |
| 734 | worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3],spare_word_enable[1]}; |
| 735 | |
| 736 | reg [79:0] worden_shift; |
| 737 | |
| 738 | |
| 739 | |
| 740 | always@(cred_mod or worden_data or wen_c4 or coloff_c4) |
| 741 | begin |
| 742 | if (wen_c4 & coloff_c4) |
| 743 | begin |
| 744 | if (~cred_mod[0]) begin |
| 745 | worden_shift[0] = worden_data[0]; |
| 746 | end |
| 747 | |
| 748 | for(i=0; i<18; i=i+1) |
| 749 | begin |
| 750 | worden_shift[i+1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i+1] ? worden_data[i+1] : 1'b0; |
| 751 | end |
| 752 | |
| 753 | worden_shift[19] = cred_mod[18] ? worden_data[18] : cred_mod[20] ? worden_data[20] : 1'b0; |
| 754 | |
| 755 | for(i=21;i<40;i=i+1) |
| 756 | begin |
| 757 | worden_shift[i-1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i-1] ? worden_data[i-1] : 1'b0; |
| 758 | end |
| 759 | |
| 760 | |
| 761 | if (~cred_mod[39]) begin |
| 762 | worden_shift[39] = worden_data[39]; |
| 763 | end |
| 764 | |
| 765 | if (~cred_mod[40]) begin |
| 766 | worden_shift[40] = worden_data[40]; |
| 767 | end |
| 768 | |
| 769 | for(i=40;i<59;i=i+1) |
| 770 | begin |
| 771 | worden_shift[i+1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i+1] ? worden_data[i+1] : 1'b0; |
| 772 | end |
| 773 | |
| 774 | worden_shift[60] = cred_mod[59] ? worden_data[59] : cred_mod[61] ? worden_data[61] : 1'b0; |
| 775 | |
| 776 | for(i=62;i<80;i=i+1) |
| 777 | begin |
| 778 | worden_shift[i-1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i-1] ? worden_data[i-1] : 1'b0; |
| 779 | end |
| 780 | |
| 781 | if (~cred_mod[79]) begin |
| 782 | worden_shift[79] = worden_data[79]; |
| 783 | end |
| 784 | |
| 785 | end |
| 786 | else worden_shift[79:0] = 80'b0; |
| 787 | |
| 788 | end |
| 789 | |
| 790 | |
| 791 | assign { worden_hi0[19], worden_lo0[19], |
| 792 | worden_hi1[18], worden_lo1[18], worden_hi0[18],worden_lo0[18], |
| 793 | worden_hi1[17], worden_lo1[17], worden_hi0[17],worden_lo0[17], |
| 794 | worden_hi1[16], worden_lo1[16], worden_hi0[16],worden_lo0[16], |
| 795 | worden_hi1[15], worden_lo1[15], worden_hi0[15],worden_lo0[15], |
| 796 | worden_hi1[14],spare_word_enable[1]} = worden_shift[79:60]; |
| 797 | |
| 798 | assign { |
| 799 | worden_lo1[14], worden_hi0[14],worden_lo0[14], |
| 800 | worden_hi1[13], worden_lo1[13], worden_hi0[13],worden_lo0[13], |
| 801 | worden_hi1[12], worden_lo1[12], worden_hi0[12],worden_lo0[12], |
| 802 | worden_hi1[11], worden_lo1[11], worden_hi0[11],worden_lo0[11], |
| 803 | worden_hi1[10], worden_lo1[10], worden_hi0[10],worden_lo0[10],worden_hi1[9]} = worden_shift[59:40]; |
| 804 | |
| 805 | assign { |
| 806 | worden_lo1[9], worden_hi0[9],worden_lo0[9], |
| 807 | worden_hi1[8], worden_lo1[8], worden_hi0[8],worden_lo0[8], |
| 808 | worden_hi1[7], worden_lo1[7], worden_hi0[7],worden_lo0[7], |
| 809 | worden_hi1[6], worden_lo1[6], worden_hi0[6],worden_lo0[6], |
| 810 | worden_hi1[5], worden_lo1[5], worden_hi0[5],worden_lo0[5], worden_hi1[4]} = worden_shift[39:20]; |
| 811 | |
| 812 | assign { |
| 813 | spare_word_enable[0], worden_lo1[4], worden_hi0[4],worden_lo0[4], |
| 814 | worden_hi1[3], worden_lo1[3], worden_hi0[3],worden_lo0[3], |
| 815 | worden_hi1[2], worden_lo1[2], worden_hi0[2],worden_lo0[2], |
| 816 | worden_hi1[1], worden_lo1[1], worden_hi0[1],worden_lo0[1], |
| 817 | worden_hi1[0], worden_lo1[0], worden_hi0[0],worden_lo0[0]} = worden_shift[19:0]; |
| 818 | |
| 819 | |
| 820 | |
| 821 | |
| 822 | |
| 823 | |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | always@(l1clk or wen_c4 or set_c4 or waysel_c4 or waysel_err_c4 or worden_c4 or wrd_lo0_a or |
| 837 | wrd_hi0_a or wrd_lo1_a or wrd_hi1_a or coloff_c4 or bank_select or wr_spare_0 or |
| 838 | wr_spare_1 or wee_l or worden_hi0 or worden_lo0 or worden_lo1 or worden_hi1 or spare_word_enable |
| 839 | or vnw_ary) |
| 840 | begin |
| 841 | |
| 842 | //////////////////////////////////////////////////////////////// |
| 843 | // Read all entries for a given set |
| 844 | //////////////////////////////////////////////////////////////// |
| 845 | |
| 846 | //////////////////////////////////////////////////////////////// |
| 847 | // Write data computation |
| 848 | //////////////////////////////////////////////////////////////// |
| 849 | |
| 850 | /////////////////////////////////////////////////////////////// |
| 851 | // Write to memory |
| 852 | ////////////////////////////////////////////////////////////// |
| 853 | |
| 854 | |
| 855 | |
| 856 | #0 |
| 857 | |
| 858 | |
| 859 | //if(wen_c4 & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4)) |
| 860 | if(~l1clk & wee_l & wen_c4 & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary) |
| 861 | begin |
| 862 | if(waysel_c4[0]) |
| 863 | begin |
| 864 | mem_lo0_way0[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way0[set_c4]); |
| 865 | mem_hi0_way0[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way0[set_c4]); |
| 866 | mem_lo1_way0[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way0[set_c4]); |
| 867 | mem_hi1_way0[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way0[set_c4]); |
| 868 | mem_way0_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way0_spare_0[set_c4]); |
| 869 | mem_way0_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way0_spare_1[set_c4]); |
| 870 | end |
| 871 | else if(waysel_c4[1]) |
| 872 | begin |
| 873 | mem_lo0_way1[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way1[set_c4]); |
| 874 | mem_hi0_way1[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way1[set_c4]); |
| 875 | mem_lo1_way1[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way1[set_c4]); |
| 876 | mem_hi1_way1[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way1[set_c4]); |
| 877 | mem_way1_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way1_spare_0[set_c4]); |
| 878 | mem_way1_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way1_spare_1[set_c4]); |
| 879 | end |
| 880 | else if(waysel_c4[2]) |
| 881 | begin |
| 882 | mem_lo0_way2[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way2[set_c4]); |
| 883 | mem_lo1_way2[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way2[set_c4]); |
| 884 | mem_hi0_way2[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way2[set_c4]); |
| 885 | mem_hi1_way2[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way2[set_c4]); |
| 886 | mem_way2_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way2_spare_0[set_c4]); |
| 887 | mem_way2_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way2_spare_1[set_c4]); |
| 888 | end |
| 889 | else if(waysel_c4[3]) |
| 890 | begin |
| 891 | mem_lo0_way3[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way3[set_c4]); |
| 892 | mem_lo1_way3[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way3[set_c4]); |
| 893 | mem_hi0_way3[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way3[set_c4]); |
| 894 | mem_hi1_way3[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way3[set_c4]); |
| 895 | mem_way3_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way3_spare_0[set_c4]); |
| 896 | mem_way3_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way3_spare_1[set_c4]); |
| 897 | end |
| 898 | else if(waysel_c4[4]) |
| 899 | begin |
| 900 | mem_lo0_way4[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way4[set_c4]); |
| 901 | mem_lo1_way4[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way4[set_c4]); |
| 902 | mem_hi0_way4[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way4[set_c4]); |
| 903 | mem_hi1_way4[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way4[set_c4]); |
| 904 | mem_way4_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way4_spare_0[set_c4]); |
| 905 | mem_way4_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way4_spare_1[set_c4]); |
| 906 | end |
| 907 | else if(waysel_c4[5]) |
| 908 | begin |
| 909 | mem_lo0_way5[set_c4] =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way5[set_c4]); |
| 910 | mem_lo1_way5[set_c4] =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way5[set_c4]); |
| 911 | mem_hi0_way5[set_c4] =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way5[set_c4]); |
| 912 | mem_hi1_way5[set_c4] =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way5[set_c4]); |
| 913 | mem_way5_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way5_spare_0[set_c4]); |
| 914 | mem_way5_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way5_spare_1[set_c4]); |
| 915 | end |
| 916 | else if(waysel_c4[6]) |
| 917 | begin |
| 918 | mem_lo0_way6[set_c4] =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way6[set_c4]); |
| 919 | mem_lo1_way6[set_c4] =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way6[set_c4]); |
| 920 | mem_hi0_way6[set_c4] =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way6[set_c4]); |
| 921 | mem_hi1_way6[set_c4] =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way6[set_c4]); |
| 922 | mem_way6_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way6_spare_0[set_c4]); |
| 923 | mem_way6_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way6_spare_1[set_c4]); |
| 924 | end |
| 925 | else if(waysel_c4[7]) |
| 926 | begin |
| 927 | mem_lo0_way7[set_c4] =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way7[set_c4]); |
| 928 | mem_lo1_way7[set_c4] =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way7[set_c4]); |
| 929 | mem_hi0_way7[set_c4] =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way7[set_c4]); |
| 930 | mem_hi1_way7[set_c4] =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way7[set_c4]); |
| 931 | mem_way7_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way7_spare_0[set_c4]); |
| 932 | mem_way7_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way7_spare_1[set_c4]); |
| 933 | end |
| 934 | end |
| 935 | end |
| 936 | |
| 937 | //always@(waysel_c4 or set_c4 or bnken_lat ) |
| 938 | always@(waysel_c4 or set_c4 or coloff_c4_l or vnw_ary) |
| 939 | |
| 940 | begin |
| 941 | |
| 942 | |
| 943 | #0 |
| 944 | |
| 945 | if(~coloff_c4_l & vnw_ary) |
| 946 | begin |
| 947 | if(waysel_c4[0]) |
| 948 | begin |
| 949 | saout_lo0_bc[19:0] <= mem_lo0_way0[set_c4]; |
| 950 | saout_lo1_bc[18:0] <= mem_lo1_way0[set_c4]; |
| 951 | saout_hi0_bc[19:0] <= mem_hi0_way0[set_c4]; |
| 952 | saout_hi1_bc[18:0] <= mem_hi1_way0[set_c4]; |
| 953 | rd_spare_0 <= mem_way0_spare_0[set_c4]; |
| 954 | rd_spare_1 <= mem_way0_spare_1[set_c4]; |
| 955 | end |
| 956 | else if(waysel_c4[1]) |
| 957 | begin |
| 958 | saout_lo0_bc[19:0] <= mem_lo0_way1[set_c4]; |
| 959 | saout_lo1_bc[18:0] <= mem_lo1_way1[set_c4]; |
| 960 | saout_hi0_bc[19:0] <= mem_hi0_way1[set_c4]; |
| 961 | saout_hi1_bc[18:0] <= mem_hi1_way1[set_c4]; |
| 962 | rd_spare_0 <= mem_way1_spare_0[set_c4]; |
| 963 | rd_spare_1 <= mem_way1_spare_1[set_c4]; |
| 964 | end |
| 965 | else if(waysel_c4[2]) |
| 966 | begin |
| 967 | saout_lo0_bc[19:0] <= mem_lo0_way2[set_c4]; |
| 968 | saout_lo1_bc[18:0] <= mem_lo1_way2[set_c4]; |
| 969 | saout_hi0_bc[19:0] <= mem_hi0_way2[set_c4]; |
| 970 | saout_hi1_bc[18:0] <= mem_hi1_way2[set_c4]; |
| 971 | rd_spare_0 <= mem_way2_spare_0[set_c4]; |
| 972 | rd_spare_1 <= mem_way2_spare_1[set_c4]; |
| 973 | end |
| 974 | else if(waysel_c4[3]) |
| 975 | begin |
| 976 | saout_lo0_bc[19:0] <= mem_lo0_way3[set_c4]; |
| 977 | saout_lo1_bc[18:0] <= mem_lo1_way3[set_c4]; |
| 978 | saout_hi0_bc[19:0] <= mem_hi0_way3[set_c4]; |
| 979 | saout_hi1_bc[18:0] <= mem_hi1_way3[set_c4]; |
| 980 | rd_spare_0 <= mem_way3_spare_0[set_c4]; |
| 981 | rd_spare_1 <= mem_way3_spare_1[set_c4]; |
| 982 | end |
| 983 | else if(waysel_c4[4]) |
| 984 | begin |
| 985 | saout_lo0_bc[19:0] <= mem_lo0_way4[set_c4]; |
| 986 | saout_lo1_bc[18:0] <= mem_lo1_way4[set_c4]; |
| 987 | saout_hi0_bc[19:0] <= mem_hi0_way4[set_c4]; |
| 988 | saout_hi1_bc[18:0] <= mem_hi1_way4[set_c4]; |
| 989 | rd_spare_0 <= mem_way4_spare_0[set_c4]; |
| 990 | rd_spare_1 <= mem_way4_spare_1[set_c4]; |
| 991 | end |
| 992 | else if(waysel_c4[5]) |
| 993 | begin |
| 994 | saout_lo0_bc[19:0] <= mem_lo0_way5[set_c4]; |
| 995 | saout_lo1_bc[18:0] <= mem_lo1_way5[set_c4]; |
| 996 | saout_hi0_bc[19:0] <= mem_hi0_way5[set_c4]; |
| 997 | saout_hi1_bc[18:0] <= mem_hi1_way5[set_c4]; |
| 998 | rd_spare_0 <= mem_way5_spare_0[set_c4]; |
| 999 | rd_spare_1 <= mem_way5_spare_1[set_c4]; |
| 1000 | end |
| 1001 | else if(waysel_c4[6]) |
| 1002 | begin |
| 1003 | saout_lo0_bc[19:0] <= mem_lo0_way6[set_c4]; |
| 1004 | saout_lo1_bc[18:0] <= mem_lo1_way6[set_c4]; |
| 1005 | saout_hi0_bc[19:0] <= mem_hi0_way6[set_c4]; |
| 1006 | saout_hi1_bc[18:0] <= mem_hi1_way6[set_c4]; |
| 1007 | rd_spare_0 <= mem_way6_spare_0[set_c4]; |
| 1008 | rd_spare_1 <= mem_way6_spare_1[set_c4]; |
| 1009 | end |
| 1010 | else if(waysel_c4[7]) |
| 1011 | begin |
| 1012 | saout_lo0_bc[19:0] <= mem_lo0_way7[set_c4]; |
| 1013 | saout_lo1_bc[18:0] <= mem_lo1_way7[set_c4]; |
| 1014 | saout_hi0_bc[19:0] <= mem_hi0_way7[set_c4]; |
| 1015 | saout_hi1_bc[18:0] <= mem_hi1_way7[set_c4]; |
| 1016 | rd_spare_0 <= mem_way7_spare_0[set_c4]; |
| 1017 | rd_spare_1 <= mem_way7_spare_1[set_c4]; |
| 1018 | end |
| 1019 | end |
| 1020 | end |
| 1021 | |
| 1022 | |
| 1023 | // READ |
| 1024 | // Data is read out of the above array in c4 and gets registered and latched |
| 1025 | // to become a c5b signal which gets muxed and goes to dmux |
| 1026 | |
| 1027 | |
| 1028 | reg rd_spare_0_d_l,rd_spare_1_d_l; |
| 1029 | reg rdd_spare_0,rdd_spare_1; |
| 1030 | reg tstmodclk_c3b_l; |
| 1031 | always@(posedge l1clk) |
| 1032 | begin |
| 1033 | saout_lo0_bc_d_l[19:0] <= ~saout_lo0_bc[19:0]; |
| 1034 | saout_lo1_bc_d_l[18:0] <= ~saout_lo1_bc[18:0]; |
| 1035 | saout_hi0_bc_d_l[19:0] <= ~saout_hi0_bc[19:0]; |
| 1036 | saout_hi1_bc_d_l[18:0] <= ~saout_hi1_bc[18:0]; |
| 1037 | rd_spare_0_d_l <= ~rd_spare_0; |
| 1038 | rd_spare_1_d_l <= ~rd_spare_1; |
| 1039 | end |
| 1040 | |
| 1041 | always@(negedge l1clk) |
| 1042 | begin |
| 1043 | saout_lo0_bc_c5b_l[19:0] <= saout_lo0_bc_d_l[19:0]; |
| 1044 | saout_lo1_bc_c5b_l[18:0] <= saout_lo1_bc_d_l[18:0]; |
| 1045 | saout_hi0_bc_c5b_l[19:0] <= saout_hi0_bc_d_l[19:0]; |
| 1046 | saout_hi1_bc_c5b_l[18:0] <= saout_hi1_bc_d_l[18:0]; |
| 1047 | rdd_spare_0 <= rd_spare_0_d_l; |
| 1048 | rdd_spare_1 <= rd_spare_1_d_l; |
| 1049 | tstmodclk_c3b_l <= tstmodclk_l; |
| 1050 | end |
| 1051 | |
| 1052 | |
| 1053 | assign rd_data[19:0] = |
| 1054 | {rdd_spare_0, saout_lo1_bc_c5b_l[4], saout_hi0_bc_c5b_l[4],saout_lo0_bc_c5b_l[4], |
| 1055 | saout_hi1_bc_c5b_l[3], saout_lo1_bc_c5b_l[3], saout_hi0_bc_c5b_l[3],saout_lo0_bc_c5b_l[3], |
| 1056 | saout_hi1_bc_c5b_l[2], saout_lo1_bc_c5b_l[2], saout_hi0_bc_c5b_l[2],saout_lo0_bc_c5b_l[2], |
| 1057 | saout_hi1_bc_c5b_l[1], saout_lo1_bc_c5b_l[1], saout_hi0_bc_c5b_l[1],saout_lo0_bc_c5b_l[1], |
| 1058 | saout_hi1_bc_c5b_l[0], saout_lo1_bc_c5b_l[0], saout_hi0_bc_c5b_l[0],saout_lo0_bc_c5b_l[0]}; |
| 1059 | |
| 1060 | assign rd_data[39:20] = { |
| 1061 | saout_lo1_bc_c5b_l[9], saout_hi0_bc_c5b_l[9],saout_lo0_bc_c5b_l[9], |
| 1062 | saout_hi1_bc_c5b_l[8], saout_lo1_bc_c5b_l[8], saout_hi0_bc_c5b_l[8],saout_lo0_bc_c5b_l[8], |
| 1063 | saout_hi1_bc_c5b_l[7], saout_lo1_bc_c5b_l[7], saout_hi0_bc_c5b_l[7],saout_lo0_bc_c5b_l[7], |
| 1064 | saout_hi1_bc_c5b_l[6], saout_lo1_bc_c5b_l[6], saout_hi0_bc_c5b_l[6],saout_lo0_bc_c5b_l[6], |
| 1065 | saout_hi1_bc_c5b_l[5], saout_lo1_bc_c5b_l[5], saout_hi0_bc_c5b_l[5],saout_lo0_bc_c5b_l[5], saout_hi1_bc_c5b_l[4]}; |
| 1066 | |
| 1067 | |
| 1068 | assign rd_data[59:40] = { |
| 1069 | saout_lo1_bc_c5b_l[14], saout_hi0_bc_c5b_l[14],saout_lo0_bc_c5b_l[14], |
| 1070 | saout_hi1_bc_c5b_l[13], saout_lo1_bc_c5b_l[13], saout_hi0_bc_c5b_l[13],saout_lo0_bc_c5b_l[13], |
| 1071 | saout_hi1_bc_c5b_l[12], saout_lo1_bc_c5b_l[12], saout_hi0_bc_c5b_l[12],saout_lo0_bc_c5b_l[12], |
| 1072 | saout_hi1_bc_c5b_l[11], saout_lo1_bc_c5b_l[11], saout_hi0_bc_c5b_l[11],saout_lo0_bc_c5b_l[11], |
| 1073 | saout_hi1_bc_c5b_l[10], saout_lo1_bc_c5b_l[10], saout_hi0_bc_c5b_l[10],saout_lo0_bc_c5b_l[10], saout_hi1_bc_c5b_l[9]}; |
| 1074 | |
| 1075 | assign rd_data[79:60] = { |
| 1076 | saout_hi0_bc_c5b_l[19], saout_lo0_bc_c5b_l[19], |
| 1077 | saout_hi1_bc_c5b_l[18], saout_lo1_bc_c5b_l[18], saout_hi0_bc_c5b_l[18],saout_lo0_bc_c5b_l[18], |
| 1078 | saout_hi1_bc_c5b_l[17], saout_lo1_bc_c5b_l[17], saout_hi0_bc_c5b_l[17],saout_lo0_bc_c5b_l[17], |
| 1079 | saout_hi1_bc_c5b_l[16], saout_lo1_bc_c5b_l[16], saout_hi0_bc_c5b_l[16],saout_lo0_bc_c5b_l[16], |
| 1080 | saout_hi1_bc_c5b_l[15], saout_lo1_bc_c5b_l[15], saout_hi0_bc_c5b_l[15],saout_lo0_bc_c5b_l[15], saout_hi1_bc_c5b_l[14],rdd_spare_1}; |
| 1081 | |
| 1082 | |
| 1083 | always@(cred_mod or rd_data) |
| 1084 | begin |
| 1085 | |
| 1086 | for(i=0;i<19;i=i+1) |
| 1087 | begin |
| 1088 | read_data[i] = cred_mod[i] ? rd_data[i+1] : rd_data[i]; |
| 1089 | end |
| 1090 | |
| 1091 | for(i=20;i<40;i=i+1) |
| 1092 | begin |
| 1093 | read_data[i] = cred_mod[i] ? rd_data[i-1] : rd_data[i]; |
| 1094 | end |
| 1095 | |
| 1096 | |
| 1097 | for(i=40;i<60;i=i+1) |
| 1098 | begin |
| 1099 | read_data[i] = cred_mod[i] ? rd_data[i+1] : rd_data[i]; |
| 1100 | end |
| 1101 | |
| 1102 | for(i=61;i<80;i=i+1) |
| 1103 | begin |
| 1104 | read_data[i] = cred_mod[i] ? rd_data[i-1] : rd_data[i]; |
| 1105 | end |
| 1106 | |
| 1107 | end |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | assign { saout_hi0_b_out_l[19], saout_lo0_b_out_l[19], |
| 1112 | saout_hi1_b_out_l[18], saout_lo1_b_out_l[18], saout_hi0_b_out_l[18],saout_lo0_b_out_l[18], |
| 1113 | saout_hi1_b_out_l[17], saout_lo1_b_out_l[17], saout_hi0_b_out_l[17],saout_lo0_b_out_l[17], |
| 1114 | saout_hi1_b_out_l[16], saout_lo1_b_out_l[16], saout_hi0_b_out_l[16],saout_lo0_b_out_l[16], |
| 1115 | saout_hi1_b_out_l[15], saout_lo1_b_out_l[15], saout_hi0_b_out_l[15],saout_lo0_b_out_l[15], |
| 1116 | saout_hi1_b_out_l[14]} = read_data[79:61]; |
| 1117 | |
| 1118 | assign {saout_lo1_b_out_l[14], saout_hi0_b_out_l[14],saout_lo0_b_out_l[14], |
| 1119 | saout_hi1_b_out_l[13], saout_lo1_b_out_l[13], saout_hi0_b_out_l[13],saout_lo0_b_out_l[13], |
| 1120 | saout_hi1_b_out_l[12], saout_lo1_b_out_l[12], saout_hi0_b_out_l[12],saout_lo0_b_out_l[12], |
| 1121 | saout_hi1_b_out_l[11], saout_lo1_b_out_l[11], saout_hi0_b_out_l[11],saout_lo0_b_out_l[11], |
| 1122 | saout_hi1_b_out_l[10], saout_lo1_b_out_l[10], saout_hi0_b_out_l[10],saout_lo0_b_out_l[10], |
| 1123 | saout_hi1_b_out_l[9]} = read_data[59:40]; |
| 1124 | |
| 1125 | assign { saout_lo1_b_out_l[9], saout_hi0_b_out_l[9],saout_lo0_b_out_l[9], |
| 1126 | saout_hi1_b_out_l[8], saout_lo1_b_out_l[8], saout_hi0_b_out_l[8],saout_lo0_b_out_l[8], |
| 1127 | saout_hi1_b_out_l[7], saout_lo1_b_out_l[7], saout_hi0_b_out_l[7],saout_lo0_b_out_l[7], |
| 1128 | saout_hi1_b_out_l[6], saout_lo1_b_out_l[6], saout_hi0_b_out_l[6],saout_lo0_b_out_l[6], |
| 1129 | saout_hi1_b_out_l[5], saout_lo1_b_out_l[5], saout_hi0_b_out_l[5],saout_lo0_b_out_l[5], |
| 1130 | saout_hi1_b_out_l[4]} = read_data[39:20]; |
| 1131 | |
| 1132 | assign {saout_lo1_b_out_l[4], saout_hi0_b_out_l[4],saout_lo0_b_out_l[4], |
| 1133 | saout_hi1_b_out_l[3], saout_lo1_b_out_l[3], saout_hi0_b_out_l[3],saout_lo0_b_out_l[3], |
| 1134 | saout_hi1_b_out_l[2], saout_lo1_b_out_l[2], saout_hi0_b_out_l[2],saout_lo0_b_out_l[2], |
| 1135 | saout_hi1_b_out_l[1], saout_lo1_b_out_l[1], saout_hi0_b_out_l[1],saout_lo0_b_out_l[1], |
| 1136 | saout_hi1_b_out_l[0], saout_lo1_b_out_l[0], saout_hi0_b_out_l[0],saout_lo0_b_out_l[0]} = read_data[18:0]; |
| 1137 | |
| 1138 | assign red_sel_rgt = |cred[19:18]; |
| 1139 | assign red_sel_lft = |cred[59:58]; |
| 1140 | |
| 1141 | assign coloff_c5_rgt[1] = coloff_c5[1] | red_sel_rgt & coloff_c5[0]; |
| 1142 | assign coloff_c5_rgt[0] = coloff_c5[0] | red_sel_rgt & coloff_c5[1]; |
| 1143 | assign coloff_c5_lft[1] = coloff_c5[1] | red_sel_lft & coloff_c5[0]; |
| 1144 | assign coloff_c5_lft[0] = coloff_c5[0] | red_sel_lft & coloff_c5[1]; |
| 1145 | |
| 1146 | |
| 1147 | |
| 1148 | |
| 1149 | |
| 1150 | |
| 1151 | |
| 1152 | |
| 1153 | |
| 1154 | |
| 1155 | |
| 1156 | always@(negedge l1clk) |
| 1157 | begin |
| 1158 | select_read_data_all_c5b <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & (|coloff_c5) & readen_c5 & wee_l & ~waysel_err_c4); |
| 1159 | select_read_red_all_c5b <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & (|coloff_c5) & readen_c5 & wee_l & ~waysel_err_c4); |
| 1160 | |
| 1161 | select_read_data_c5b_hi_rgt <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1162 | (readen_c5 & coloff_c5_rgt[1] & ~waysel_err_c5); |
| 1163 | select_read_data_c5b_hi_lft <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1164 | (readen_c5 & coloff_c5_lft[1] & ~waysel_err_c5); |
| 1165 | select_read_data_c5b_lo_rgt <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1166 | (readen_c5 & coloff_c5_rgt[0] & ~waysel_err_c5); |
| 1167 | select_read_data_c5b_lo_lft <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1168 | (readen_c5 & coloff_c5_lft[0] & ~waysel_err_c5); |
| 1169 | select_read_red_c5b_hi_rgt <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1170 | (readen_c5 & coloff_c5_rgt[1] & ~waysel_err_c5); |
| 1171 | select_read_red_c5b_hi_lft <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1172 | (readen_c5 & coloff_c5_lft[1] & ~waysel_err_c5); |
| 1173 | select_read_red_c5b_lo_rgt <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1174 | (readen_c5 & coloff_c5_rgt[0] & ~waysel_err_c5); |
| 1175 | select_read_red_c5b_lo_lft <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) & |
| 1176 | (readen_c5 & coloff_c5_lft[0] & ~waysel_err_c5); |
| 1177 | end |
| 1178 | |
| 1179 | |
| 1180 | //assign saout_lo0_bc_l[19:0] = select_read_data_c5b ? saout_lo0_bc_c5b_l[19:0] : |
| 1181 | // select_read_red_c5b ? red_lo0_out[19:0] : 20'hFFFFF; |
| 1182 | //assign saout_lo1_bc_l[18:0] = select_read_data_c5b ? saout_lo1_bc_c5b_l[18:0] : |
| 1183 | // select_read_red_c5b ? red_lo1_out[18:0] : 19'h7FFFF; |
| 1184 | //assign saout_hi0_bc_l[19:0] = select_read_data_c5b ? saout_hi0_bc_c5b_l[19:0] : |
| 1185 | // select_read_red_c5b ? red_hi0_out[19:0] : 20'hFFFFF; |
| 1186 | //assign saout_hi1_bc_l[18:0] = select_read_data_c5b ? saout_hi1_bc_c5b_l[18:0] : |
| 1187 | // select_read_red_c5b ? red_hi1_out[18:0] : 19'h7FFFF; |
| 1188 | // |
| 1189 | always@(select_read_red_c5b_lo_rgt or select_read_red_c5b_lo_lft or select_read_red_c5b_hi_rgt or select_read_red_c5b_hi_lft or |
| 1190 | select_read_data_c5b_lo_rgt or select_read_data_c5b_lo_lft or select_read_data_c5b_hi_rgt or select_read_data_c5b_hi_lft |
| 1191 | or red_lo0_b_out_l or red_hi0_b_out_l or red_lo1_b_out_l or saout_hi1_b_out_l |
| 1192 | or saout_lo0_b_out_l or red_hi0_b_out_l or saout_lo1_b_out_l or saout_hi1_b_out_l or tstmodclk_c3b_l or l1clk) |
| 1193 | begin |
| 1194 | |
| 1195 | if(tstmodclk_c3b_l) |
| 1196 | begin |
| 1197 | saout_lo0_bc_l[9:0] = select_read_red_c5b_lo_rgt ? red_lo0_b_out_l[9:0] : |
| 1198 | select_read_data_c5b_lo_rgt ? saout_lo0_b_out_l[9:0] : 10'h3FF; |
| 1199 | saout_lo0_bc_l[19:10] = select_read_red_c5b_lo_lft ? red_lo0_b_out_l[19:10] : |
| 1200 | select_read_data_c5b_lo_lft ? saout_lo0_b_out_l[19:10] : 10'h3FF; |
| 1201 | saout_hi0_bc_l[9:0] = select_read_red_c5b_lo_rgt ? red_hi0_b_out_l[9:0] : |
| 1202 | select_read_data_c5b_lo_rgt ? saout_hi0_b_out_l[9:0] : 10'h3FF; |
| 1203 | saout_hi0_bc_l[19:10] = select_read_red_c5b_lo_lft ? red_hi0_b_out_l[19:10] : |
| 1204 | select_read_data_c5b_lo_lft ? saout_hi0_b_out_l[19:10] : 10'h3FF; |
| 1205 | saout_lo1_bc_l[9:0] = select_read_red_c5b_hi_rgt ? red_lo1_b_out_l[9:0] : |
| 1206 | select_read_data_c5b_hi_rgt ? saout_lo1_b_out_l[9:0] : 10'h3FF; |
| 1207 | saout_lo1_bc_l[18:10] = select_read_red_c5b_hi_lft ? red_lo1_b_out_l[18:10] : |
| 1208 | select_read_data_c5b_hi_lft ? saout_lo1_b_out_l[18:10] : 9'h1FF; |
| 1209 | saout_hi1_bc_l[8:0] = select_read_red_c5b_hi_rgt ? red_hi1_b_out_l[8:0] : |
| 1210 | select_read_data_c5b_hi_rgt ? saout_hi1_b_out_l[8:0] : 9'h1FF; |
| 1211 | saout_hi1_bc_l[18:9] = select_read_red_c5b_hi_lft ? red_hi1_b_out_l[18:9] : |
| 1212 | select_read_data_c5b_hi_lft ? saout_hi1_b_out_l[18:9] : 10'h3FF; |
| 1213 | end |
| 1214 | else |
| 1215 | begin |
| 1216 | saout_lo0_bc_l[19:0] = select_read_red_all_c5b ? red_lo0_b_out_l[19:0] : |
| 1217 | select_read_data_all_c5b ? saout_lo0_b_out_l[19:0] : 20'bx; |
| 1218 | saout_hi0_bc_l[19:0] = select_read_red_all_c5b ? red_hi0_b_out_l[19:0] : |
| 1219 | select_read_data_all_c5b ? saout_hi0_b_out_l[19:0] : 20'bx; |
| 1220 | saout_lo1_bc_l[18:0] = select_read_red_all_c5b ? red_lo1_b_out_l[18:0] : |
| 1221 | select_read_data_all_c5b ? saout_lo1_b_out_l[18:0] : 19'bx; |
| 1222 | saout_hi1_bc_l[18:0] = select_read_red_all_c5b ? red_hi1_b_out_l[18:0] : |
| 1223 | select_read_data_all_c5b ? saout_hi1_b_out_l[18:0] : 19'bx; |
| 1224 | |
| 1225 | //saout_lo0_bc_l[19:0] = select_read_data_all_c5b ? saout_lo0_bc_c5b_l[19:0] : 20'hFFFFF; |
| 1226 | //saout_lo1_bc_l[18:0] = select_read_data_all_c5b ? saout_lo1_bc_c5b_l[18:0] : 19'hFFFFF; |
| 1227 | //saout_hi0_bc_l[19:0] = select_read_data_all_c5b ? saout_hi0_bc_c5b_l[19:0] : 20'hFFFFF; |
| 1228 | //saout_hi1_bc_l[18:0] = select_read_data_all_c5b ? saout_hi1_bc_c5b_l[18:0] : 19'hFFFFF; |
| 1229 | end |
| 1230 | end |
| 1231 | |
| 1232 | |
| 1233 | //assign repair_saout_lo0_bc_l[9:0] = |
| 1234 | //select_read_red_c5b_lo_rgt ? red_lo0_b_out_l[9:0] : select_read_data_c5b_lo_rgt ? saout_lo0_b_out_l[9:0] : 10'h3FF ; |
| 1235 | //assign repair_saout_lo0_bc_l[19:10] = |
| 1236 | //select_read_red_c5b_lo_lft ? red_lo0_b_out_l[19:10] : select_read_data_c5b_lo_lft ? saout_lo0_b_out_l[19:10] : 10'h3FF ; |
| 1237 | //assign repair_saout_hi0_bc_l[9:0] = |
| 1238 | //select_read_red_c5b_lo_rgt ? red_hi0_b_out_l[9:0] : select_read_data_c5b_lo_rgt ? saout_hi0_b_out_l[9:0] : 10'h3FF ; |
| 1239 | //assign repair_saout_hi0_bc_l[19:10] = |
| 1240 | //select_read_red_c5b_lo_lft ? red_hi0_b_out_l[19:10] : select_read_data_c5b_lo_lft ? saout_hi0_b_out_l[19:10] : 10'h3FF ; |
| 1241 | //assign repair_saout_lo1_bc_l[9:0] = |
| 1242 | //select_read_red_c5b_hi_rgt ? red_lo1_b_out_l[9:0] : select_read_data_c5b_hi_rgt ? saout_lo1_b_out_l[9:0] : 10'h3FF ; |
| 1243 | //assign repair_saout_lo1_bc_l[18:10] = |
| 1244 | //select_read_red_c5b_hi_lft ? red_lo1_b_out_l[18:10] : select_read_data_c5b_hi_lft ? saout_lo1_b_out_l[18:10] : 9'h1FF ; |
| 1245 | //assign repair_saout_hi1_bc_l[8:0] = |
| 1246 | //select_read_red_c5b_hi_rgt ? red_hi1_b_out_l[8:0] : select_read_data_c5b_hi_rgt ? saout_hi1_b_out_l[8:0] : 9'h1FF ; |
| 1247 | //assign repair_saout_hi1_bc_l[18:9] = |
| 1248 | //select_read_red_c5b_hi_lft ? red_hi1_b_out_l[18:9] : select_read_data_c5b_hi_lft ? saout_hi1_b_out_l[18:9] : 10'h3FF ; |
| 1249 | // |
| 1250 | // |
| 1251 | //assign norepair_saout_lo0_bc_l[19:0] = select_read_data_all_c5b ? saout_lo0_bc_c5b_l[19:0] : 20'hFFFFF; |
| 1252 | //assign norepair_saout_lo1_bc_l[18:0] = select_read_data_all_c5b ? saout_lo1_bc_c5b_l[18:0] : 19'hFFFFF; |
| 1253 | //assign norepair_saout_hi0_bc_l[19:0] = select_read_data_all_c5b ? saout_hi0_bc_c5b_l[19:0] : 20'hFFFFF; |
| 1254 | //assign norepair_saout_hi1_bc_l[18:0] = select_read_data_all_c5b ? saout_hi1_bc_c5b_l[18:0] : 19'hFFFFF; |
| 1255 | // |
| 1256 | //`endif |
| 1257 | // |
| 1258 | //`ifdef AXIS_SMEM |
| 1259 | // |
| 1260 | // always@(negedge l1clk) |
| 1261 | // begin |
| 1262 | // axis_saout_lo0_bc[19:0] = saout_lo0_bc[19:0]; |
| 1263 | // axis_saout_lo1_bc[18:0] = saout_lo1_bc[18:0]; |
| 1264 | // axis_saout_hi0_bc[19:0] = saout_hi0_bc[19:0]; |
| 1265 | // axis_saout_hi1_bc[18:0] = saout_hi1_bc[18:0]; |
| 1266 | // end |
| 1267 | // assign saout_lo0_bc_l[19:0] = axis_select_read_data_c5b ? axis_saout_lo0_bc[19:0] : 20'hFFFFF; |
| 1268 | // assign saout_lo1_bc_l[18:0] = axis_select_read_data_c5b ? axis_saout_lo1_bc[18:0] : 19'h7FFFF; |
| 1269 | // assign saout_hi0_bc_l[19:0] = axis_select_read_data_c5b ? axis_saout_hi0_bc[19:0] : 20'hFFFFF; |
| 1270 | // assign saout_hi1_bc_l[18:0] = axis_select_read_data_c5b ? axis_saout_hi1_bc[18:0] : 19'h7FFFF; |
| 1271 | // |
| 1272 | //`else |
| 1273 | //assign saout_lo0_bc_l[19:0] = ~tstmodclk_c3b_l ? repair_saout_lo0_bc_l[19:0] : norepair_saout_lo0_bc_l[19:0]; |
| 1274 | //assign saout_lo1_bc_l[18:0] = ~tstmodclk_c3b_l ? repair_saout_lo1_bc_l[18:0] : norepair_saout_lo1_bc_l[18:0]; |
| 1275 | //assign saout_hi0_bc_l[19:0] = ~tstmodclk_c3b_l ? repair_saout_hi0_bc_l[19:0] : norepair_saout_hi0_bc_l[19:0]; |
| 1276 | //assign saout_hi1_bc_l[18:0] = ~tstmodclk_c3b_l ? repair_saout_hi1_bc_l[18:0] : norepair_saout_hi1_bc_l[18:0]; |
| 1277 | |
| 1278 | /////////////////////////////////////////////////////////////////////////////////////////////// |
| 1279 | |
| 1280 | // REDUDANCY |
| 1281 | |
| 1282 | reg [19:0] red_lo0_odd_0; |
| 1283 | reg [18:0] red_lo1_odd_0; |
| 1284 | reg [19:0] red_hi0_odd_0; |
| 1285 | reg [18:0] red_hi1_odd_0; |
| 1286 | reg [19:0] red_lo0_even_0; |
| 1287 | reg [18:0] red_lo1_even_0; |
| 1288 | reg [19:0] red_hi0_even_0; |
| 1289 | reg [18:0] red_hi1_even_0; |
| 1290 | reg redrow_way0_spare_odd_0; |
| 1291 | reg redrow_way0_spare_even_0; |
| 1292 | reg redrow_way0_spare_odd_1; |
| 1293 | reg redrow_way0_spare_even_1; |
| 1294 | |
| 1295 | reg [19:0] red_lo0_odd_1; |
| 1296 | reg [18:0] red_lo1_odd_1; |
| 1297 | reg [19:0] red_hi0_odd_1; |
| 1298 | reg [18:0] red_hi1_odd_1; |
| 1299 | reg [19:0] red_lo0_even_1; |
| 1300 | reg [18:0] red_lo1_even_1; |
| 1301 | reg [19:0] red_hi0_even_1; |
| 1302 | reg [18:0] red_hi1_even_1; |
| 1303 | reg redrow_way1_spare_odd_0; |
| 1304 | reg redrow_way1_spare_even_0; |
| 1305 | reg redrow_way1_spare_odd_1; |
| 1306 | reg redrow_way1_spare_even_1; |
| 1307 | |
| 1308 | reg [19:0] red_lo0_odd_2; |
| 1309 | reg [18:0] red_lo1_odd_2; |
| 1310 | reg [19:0] red_hi0_odd_2; |
| 1311 | reg [18:0] red_hi1_odd_2; |
| 1312 | reg [19:0] red_lo0_even_2; |
| 1313 | reg [18:0] red_lo1_even_2; |
| 1314 | reg [19:0] red_hi0_even_2; |
| 1315 | reg [18:0] red_hi1_even_2; |
| 1316 | reg redrow_way2_spare_odd_0; |
| 1317 | reg redrow_way2_spare_even_0; |
| 1318 | reg redrow_way2_spare_odd_1; |
| 1319 | reg redrow_way2_spare_even_1; |
| 1320 | |
| 1321 | reg [19:0] red_lo0_odd_3; |
| 1322 | reg [18:0] red_lo1_odd_3; |
| 1323 | reg [19:0] red_hi0_odd_3; |
| 1324 | reg [18:0] red_hi1_odd_3; |
| 1325 | reg [19:0] red_lo0_even_3; |
| 1326 | reg [18:0] red_lo1_even_3; |
| 1327 | reg [19:0] red_hi0_even_3; |
| 1328 | reg [18:0] red_hi1_even_3; |
| 1329 | reg redrow_way3_spare_odd_0; |
| 1330 | reg redrow_way3_spare_even_0; |
| 1331 | reg redrow_way3_spare_odd_1; |
| 1332 | reg redrow_way3_spare_even_1; |
| 1333 | |
| 1334 | reg [19:0] red_lo0_odd_4; |
| 1335 | reg [18:0] red_lo1_odd_4; |
| 1336 | reg [19:0] red_hi0_odd_4; |
| 1337 | reg [18:0] red_hi1_odd_4; |
| 1338 | reg [19:0] red_lo0_even_4; |
| 1339 | reg [18:0] red_lo1_even_4; |
| 1340 | reg [19:0] red_hi0_even_4; |
| 1341 | reg [18:0] red_hi1_even_4; |
| 1342 | reg redrow_way4_spare_odd_0; |
| 1343 | reg redrow_way4_spare_even_0; |
| 1344 | reg redrow_way4_spare_odd_1; |
| 1345 | reg redrow_way4_spare_even_1; |
| 1346 | |
| 1347 | reg [19:0] red_lo0_odd_5; |
| 1348 | reg [18:0] red_lo1_odd_5; |
| 1349 | reg [19:0] red_hi0_odd_5; |
| 1350 | reg [18:0] red_hi1_odd_5; |
| 1351 | reg [19:0] red_lo0_even_5; |
| 1352 | reg [18:0] red_lo1_even_5; |
| 1353 | reg [19:0] red_hi0_even_5; |
| 1354 | reg [18:0] red_hi1_even_5; |
| 1355 | reg redrow_way5_spare_odd_0; |
| 1356 | reg redrow_way5_spare_even_0; |
| 1357 | reg redrow_way5_spare_odd_1; |
| 1358 | reg redrow_way5_spare_even_1; |
| 1359 | |
| 1360 | reg [19:0] red_lo0_odd_6; |
| 1361 | reg [18:0] red_lo1_odd_6; |
| 1362 | reg [19:0] red_hi0_odd_6; |
| 1363 | reg [18:0] red_hi1_odd_6; |
| 1364 | reg [19:0] red_lo0_even_6; |
| 1365 | reg [18:0] red_lo1_even_6; |
| 1366 | reg [19:0] red_hi0_even_6; |
| 1367 | reg [18:0] red_hi1_even_6; |
| 1368 | reg redrow_way6_spare_odd_0; |
| 1369 | reg redrow_way6_spare_even_0; |
| 1370 | reg redrow_way6_spare_odd_1; |
| 1371 | reg redrow_way6_spare_even_1; |
| 1372 | |
| 1373 | reg [19:0] red_lo0_odd_7; |
| 1374 | reg [18:0] red_lo1_odd_7; |
| 1375 | reg [19:0] red_hi0_odd_7; |
| 1376 | reg [18:0] red_hi1_odd_7; |
| 1377 | reg [19:0] red_lo0_even_7; |
| 1378 | reg [18:0] red_lo1_even_7; |
| 1379 | reg [19:0] red_hi0_even_7; |
| 1380 | reg [18:0] red_hi1_even_7; |
| 1381 | reg redrow_way7_spare_odd_0; |
| 1382 | reg redrow_way7_spare_even_0; |
| 1383 | reg redrow_way7_spare_odd_1; |
| 1384 | reg redrow_way7_spare_even_1; |
| 1385 | |
| 1386 | |
| 1387 | |
| 1388 | reg [19:0] red_lo0_out_bc; |
| 1389 | reg [18:0] red_lo1_out_bc; |
| 1390 | reg [19:0] red_hi0_out_bc; |
| 1391 | reg [18:0] red_hi1_out_bc; |
| 1392 | reg redrow_rd_spare_0; |
| 1393 | reg redrow_rd_spare_1; |
| 1394 | |
| 1395 | reg [19:0] red_lo0_out_bc_d_l; |
| 1396 | reg [18:0] red_lo1_out_bc_d_l; |
| 1397 | reg [19:0] red_hi0_out_bc_d_l; |
| 1398 | reg [18:0] red_hi1_out_bc_d_l; |
| 1399 | reg redrow_rd_spare_0_d_l; |
| 1400 | reg redrow_rd_spare_1_d_l; |
| 1401 | |
| 1402 | reg [19:0] red_lo0_bc_c5b_l; |
| 1403 | reg [19:0] red_hi0_bc_c5b_l; |
| 1404 | reg [18:0] red_lo1_bc_c5b_l; |
| 1405 | reg [18:0] red_hi1_bc_c5b_l; |
| 1406 | reg redrow_rdd_spare_0; |
| 1407 | reg redrow_rdd_spare_1; |
| 1408 | |
| 1409 | wire [79:0] red_rd_data; |
| 1410 | reg [79:0] red_read_data; |
| 1411 | |
| 1412 | // Folloing 2 assigns detects a red index to hit with incoming index |
| 1413 | // and assert. While writing and reading the way info is looked at |
| 1414 | |
| 1415 | assign select_red_odd = (red_adr[9:8] == 2'b11) & (red_adr[7:1] == set_c3b[7:1]) |
| 1416 | & set_c3b[0] & red_adr[0]; |
| 1417 | assign select_red_even = (red_adr[9:8] == 2'b11) & (red_adr[7:1] == set_c3b[7:1]) |
| 1418 | & ~set_c3b[0] & ~red_adr[0]; |
| 1419 | |
| 1420 | |
| 1421 | always@(wee_l or l1clk or wen_c4 or set_c4 or waysel_c4 or waysel_err_c4 or bank_select or coloff_c4 or worden_c4 or |
| 1422 | select_red_odd or select_red_even or worden_lo0 or worden_hi0 or worden_lo1 or worden_hi1 or wrd_lo0_a |
| 1423 | or wrd_hi0_a or wrd_lo1_a or wrd_hi1_a or wr_spare_0 or wr_spare_1 or spare_word_enable or vnw_ary) |
| 1424 | begin |
| 1425 | // Odd row to be written |
| 1426 | if(~l1clk & wee_l & wen_c4 & select_red_odd & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary) |
| 1427 | begin |
| 1428 | if(waysel_c4[0]) |
| 1429 | begin |
| 1430 | red_lo0_odd_0 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_0); |
| 1431 | red_hi0_odd_0 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_0); |
| 1432 | red_lo1_odd_0 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_0); |
| 1433 | red_hi1_odd_0 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_0); |
| 1434 | redrow_way0_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way0_spare_odd_0); |
| 1435 | redrow_way0_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way0_spare_odd_1); |
| 1436 | end |
| 1437 | else if(waysel_c4[1]) |
| 1438 | begin |
| 1439 | red_lo0_odd_1 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_1); |
| 1440 | red_hi0_odd_1 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_1); |
| 1441 | red_lo1_odd_1 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_1); |
| 1442 | red_hi1_odd_1 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_1); |
| 1443 | redrow_way1_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way1_spare_odd_0); |
| 1444 | redrow_way1_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way1_spare_odd_1); |
| 1445 | end |
| 1446 | else if(waysel_c4[2]) |
| 1447 | begin |
| 1448 | red_lo0_odd_2 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_2); |
| 1449 | red_hi0_odd_2 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_2); |
| 1450 | red_lo1_odd_2 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_2); |
| 1451 | red_hi1_odd_2 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_2); |
| 1452 | redrow_way2_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way2_spare_odd_0); |
| 1453 | redrow_way2_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way2_spare_odd_1); |
| 1454 | end |
| 1455 | else if(waysel_c4[3]) |
| 1456 | begin |
| 1457 | red_lo0_odd_3 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_3); |
| 1458 | red_hi0_odd_3 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_3); |
| 1459 | red_lo1_odd_3 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_3); |
| 1460 | red_hi1_odd_3 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_3); |
| 1461 | redrow_way3_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way3_spare_odd_0); |
| 1462 | redrow_way3_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way3_spare_odd_1); |
| 1463 | end |
| 1464 | else if(waysel_c4[4]) |
| 1465 | begin |
| 1466 | red_lo0_odd_4 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_4); |
| 1467 | red_hi0_odd_4 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_4); |
| 1468 | red_lo1_odd_4 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_4); |
| 1469 | red_hi1_odd_4 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_4); |
| 1470 | redrow_way4_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way4_spare_odd_0); |
| 1471 | redrow_way4_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way4_spare_odd_1); |
| 1472 | end |
| 1473 | else if(waysel_c4[5]) |
| 1474 | begin |
| 1475 | red_lo0_odd_5 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_5); |
| 1476 | red_hi0_odd_5 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_5); |
| 1477 | red_lo1_odd_5 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_5); |
| 1478 | red_hi1_odd_5 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_5); |
| 1479 | redrow_way5_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way5_spare_odd_0); |
| 1480 | redrow_way5_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way5_spare_odd_1); |
| 1481 | end |
| 1482 | else if(waysel_c4[6]) |
| 1483 | begin |
| 1484 | red_lo0_odd_6 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_6); |
| 1485 | red_hi0_odd_6 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_6); |
| 1486 | red_lo1_odd_6 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_6); |
| 1487 | red_hi1_odd_6 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_6); |
| 1488 | redrow_way6_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way6_spare_odd_0); |
| 1489 | redrow_way6_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way6_spare_odd_1); |
| 1490 | end |
| 1491 | else if(waysel_c4[7]) |
| 1492 | begin |
| 1493 | red_lo0_odd_7 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_7); |
| 1494 | red_hi0_odd_7 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_7); |
| 1495 | red_lo1_odd_7 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_7); |
| 1496 | red_hi1_odd_7 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_7); |
| 1497 | redrow_way7_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way7_spare_odd_0); |
| 1498 | redrow_way7_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way7_spare_odd_1); |
| 1499 | end |
| 1500 | end |
| 1501 | |
| 1502 | |
| 1503 | // Even rows to be written |
| 1504 | if(~l1clk & wee_l & wen_c4 & select_red_even & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary) |
| 1505 | begin |
| 1506 | if(waysel_c4[0]) |
| 1507 | begin |
| 1508 | red_lo0_even_0 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_0); |
| 1509 | red_hi0_even_0 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_0); |
| 1510 | red_lo1_even_0 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_0); |
| 1511 | red_hi1_even_0 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_0); |
| 1512 | redrow_way0_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way0_spare_even_0); |
| 1513 | redrow_way0_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way0_spare_even_1); |
| 1514 | end |
| 1515 | else if(waysel_c4[1]) |
| 1516 | begin |
| 1517 | red_lo0_even_1 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_1); |
| 1518 | red_hi0_even_1 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_1); |
| 1519 | red_lo1_even_1 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_1); |
| 1520 | red_hi1_even_1 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_1); |
| 1521 | redrow_way1_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way1_spare_even_0); |
| 1522 | redrow_way1_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way1_spare_even_1); |
| 1523 | end |
| 1524 | else if(waysel_c4[2]) |
| 1525 | begin |
| 1526 | red_lo0_even_2 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_2); |
| 1527 | red_hi0_even_2 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_2); |
| 1528 | red_lo1_even_2 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_2); |
| 1529 | red_hi1_even_2 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_2); |
| 1530 | redrow_way2_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way2_spare_even_0); |
| 1531 | redrow_way2_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way2_spare_even_1); |
| 1532 | end |
| 1533 | else if(waysel_c4[3]) |
| 1534 | begin |
| 1535 | red_lo0_even_3 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_3); |
| 1536 | red_hi0_even_3 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_3); |
| 1537 | red_lo1_even_3 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_3); |
| 1538 | red_hi1_even_3 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_3); |
| 1539 | redrow_way3_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way3_spare_even_0); |
| 1540 | redrow_way3_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way3_spare_even_1); |
| 1541 | end |
| 1542 | else if(waysel_c4[4]) |
| 1543 | begin |
| 1544 | red_lo0_even_4 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_4); |
| 1545 | red_hi0_even_4 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_4); |
| 1546 | red_lo1_even_4 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_4); |
| 1547 | red_hi1_even_4 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_4); |
| 1548 | redrow_way4_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way4_spare_even_0); |
| 1549 | redrow_way4_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way4_spare_even_1); |
| 1550 | end |
| 1551 | else if(waysel_c4[5]) |
| 1552 | begin |
| 1553 | red_lo0_even_5 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_5); |
| 1554 | red_hi0_even_5 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_5); |
| 1555 | red_lo1_even_5 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_5); |
| 1556 | red_hi1_even_5 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_5); |
| 1557 | redrow_way5_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way5_spare_even_0); |
| 1558 | redrow_way5_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way5_spare_even_1); |
| 1559 | end |
| 1560 | else if(waysel_c4[6]) |
| 1561 | begin |
| 1562 | red_lo0_even_6 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_6); |
| 1563 | red_hi0_even_6 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_6); |
| 1564 | red_lo1_even_6 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_6); |
| 1565 | red_hi1_even_6 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_6); |
| 1566 | redrow_way6_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way6_spare_even_0); |
| 1567 | redrow_way6_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way6_spare_even_1); |
| 1568 | end |
| 1569 | else if(waysel_c4[7]) |
| 1570 | begin |
| 1571 | red_lo0_even_7 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_7); |
| 1572 | red_hi0_even_7 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_7); |
| 1573 | red_lo1_even_7 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_7); |
| 1574 | red_hi1_even_7 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_7); |
| 1575 | redrow_way7_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way7_spare_even_0); |
| 1576 | redrow_way7_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way7_spare_even_1); |
| 1577 | end |
| 1578 | end |
| 1579 | end |
| 1580 | |
| 1581 | // read out |
| 1582 | always@(waysel_c4 or coloff_c4_l or set_c4 or vnw_ary) |
| 1583 | begin |
| 1584 | if(~coloff_c4_l & vnw_ary) |
| 1585 | begin |
| 1586 | if(waysel_c4[0]) |
| 1587 | begin |
| 1588 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_0 : red_lo0_even_0; |
| 1589 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_0 : red_lo1_even_0; |
| 1590 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_0 : red_hi0_even_0; |
| 1591 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_0 : red_hi1_even_0; |
| 1592 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way0_spare_odd_0 : redrow_way0_spare_even_0; |
| 1593 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way0_spare_odd_1 : redrow_way0_spare_even_1; |
| 1594 | end |
| 1595 | else if(waysel_c4[1]) |
| 1596 | begin |
| 1597 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_1 : red_lo0_even_1; |
| 1598 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_1 : red_lo1_even_1; |
| 1599 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_1 : red_hi0_even_1; |
| 1600 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_1 : red_hi1_even_1; |
| 1601 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way1_spare_odd_0 : redrow_way1_spare_even_0; |
| 1602 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way1_spare_odd_1 : redrow_way1_spare_even_1; |
| 1603 | end |
| 1604 | else if(waysel_c4[2]) |
| 1605 | begin |
| 1606 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_2 : red_lo0_even_2; |
| 1607 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_2 : red_lo1_even_2; |
| 1608 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_2 : red_hi0_even_2; |
| 1609 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_2 : red_hi1_even_2; |
| 1610 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way2_spare_odd_0 : redrow_way2_spare_even_0; |
| 1611 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way2_spare_odd_1 : redrow_way2_spare_even_1; |
| 1612 | end |
| 1613 | else if(waysel_c4[3]) |
| 1614 | begin |
| 1615 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_3 : red_lo0_even_3; |
| 1616 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_3 : red_lo1_even_3; |
| 1617 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_3 : red_hi0_even_3; |
| 1618 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_3 : red_hi1_even_3; |
| 1619 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way3_spare_odd_0 : redrow_way3_spare_even_0; |
| 1620 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way3_spare_odd_1 : redrow_way3_spare_even_1; |
| 1621 | end |
| 1622 | else if(waysel_c4[4]) |
| 1623 | begin |
| 1624 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_4 : red_lo0_even_4; |
| 1625 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_4 : red_lo1_even_4; |
| 1626 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_4 : red_hi0_even_4; |
| 1627 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_4 : red_hi1_even_4; |
| 1628 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way4_spare_odd_0 : redrow_way4_spare_even_0; |
| 1629 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way4_spare_odd_1 : redrow_way4_spare_even_1; |
| 1630 | end |
| 1631 | else if(waysel_c4[5]) |
| 1632 | begin |
| 1633 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_5 : red_lo0_even_5; |
| 1634 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_5 : red_lo1_even_5; |
| 1635 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_5 : red_hi0_even_5; |
| 1636 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_5 : red_hi1_even_5; |
| 1637 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way5_spare_odd_0 : redrow_way5_spare_even_0; |
| 1638 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way5_spare_odd_1 : redrow_way5_spare_even_1; |
| 1639 | end |
| 1640 | else if(waysel_c4[6]) |
| 1641 | begin |
| 1642 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_6 : red_lo0_even_6; |
| 1643 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_6 : red_lo1_even_6; |
| 1644 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_6 : red_hi0_even_6; |
| 1645 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_6 : red_hi1_even_6; |
| 1646 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way6_spare_odd_0 : redrow_way6_spare_even_0; |
| 1647 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way6_spare_odd_1 : redrow_way6_spare_even_1; |
| 1648 | end |
| 1649 | else if(waysel_c4[7]) |
| 1650 | begin |
| 1651 | red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_7 : red_lo0_even_7; |
| 1652 | red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_7 : red_lo1_even_7; |
| 1653 | red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_7 : red_hi0_even_7; |
| 1654 | red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_7 : red_hi1_even_7; |
| 1655 | redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way7_spare_odd_0 : redrow_way7_spare_even_0; |
| 1656 | redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way7_spare_odd_1 : redrow_way7_spare_even_1; |
| 1657 | end |
| 1658 | end |
| 1659 | end |
| 1660 | |
| 1661 | always@(negedge l1clk) |
| 1662 | begin |
| 1663 | red_lo0_out_bc_d_l <= ~red_lo0_out_bc; |
| 1664 | red_hi0_out_bc_d_l <= ~red_hi0_out_bc; |
| 1665 | red_lo1_out_bc_d_l <= ~red_lo1_out_bc; |
| 1666 | red_hi1_out_bc_d_l <= ~red_hi1_out_bc; |
| 1667 | redrow_rd_spare_0_d_l <= ~redrow_rd_spare_0; |
| 1668 | redrow_rd_spare_1_d_l <= ~redrow_rd_spare_1; |
| 1669 | end |
| 1670 | |
| 1671 | always@(posedge l1clk) |
| 1672 | begin |
| 1673 | red_lo0_bc_c5b_l <= red_lo0_out_bc_d_l; |
| 1674 | red_hi0_bc_c5b_l <= red_hi0_out_bc_d_l; |
| 1675 | red_lo1_bc_c5b_l <= red_lo1_out_bc_d_l; |
| 1676 | red_hi1_bc_c5b_l <= red_hi1_out_bc_d_l; |
| 1677 | redrow_rdd_spare_0 <= redrow_rd_spare_0_d_l; |
| 1678 | redrow_rdd_spare_1 <= redrow_rd_spare_1_d_l; |
| 1679 | end |
| 1680 | |
| 1681 | assign red_rd_data[19:0] = |
| 1682 | {redrow_rdd_spare_0, red_lo1_bc_c5b_l[4], red_hi0_bc_c5b_l[4],red_lo0_bc_c5b_l[4], |
| 1683 | red_hi1_bc_c5b_l[3], red_lo1_bc_c5b_l[3], red_hi0_bc_c5b_l[3],red_lo0_bc_c5b_l[3], |
| 1684 | red_hi1_bc_c5b_l[2], red_lo1_bc_c5b_l[2], red_hi0_bc_c5b_l[2],red_lo0_bc_c5b_l[2], |
| 1685 | red_hi1_bc_c5b_l[1], red_lo1_bc_c5b_l[1], red_hi0_bc_c5b_l[1],red_lo0_bc_c5b_l[1], |
| 1686 | red_hi1_bc_c5b_l[0], red_lo1_bc_c5b_l[0], red_hi0_bc_c5b_l[0],red_lo0_bc_c5b_l[0]}; |
| 1687 | |
| 1688 | assign red_rd_data[39:20] = { |
| 1689 | red_lo1_bc_c5b_l[9], red_hi0_bc_c5b_l[9],red_lo0_bc_c5b_l[9], |
| 1690 | red_hi1_bc_c5b_l[8], red_lo1_bc_c5b_l[8], red_hi0_bc_c5b_l[8],red_lo0_bc_c5b_l[8], |
| 1691 | red_hi1_bc_c5b_l[7], red_lo1_bc_c5b_l[7], red_hi0_bc_c5b_l[7],red_lo0_bc_c5b_l[7], |
| 1692 | red_hi1_bc_c5b_l[6], red_lo1_bc_c5b_l[6], red_hi0_bc_c5b_l[6],red_lo0_bc_c5b_l[6], |
| 1693 | red_hi1_bc_c5b_l[5], red_lo1_bc_c5b_l[5], red_hi0_bc_c5b_l[5],red_lo0_bc_c5b_l[5], red_hi1_bc_c5b_l[4]}; |
| 1694 | |
| 1695 | |
| 1696 | assign red_rd_data[59:40] = { |
| 1697 | red_lo1_bc_c5b_l[14], red_hi0_bc_c5b_l[14],red_lo0_bc_c5b_l[14], |
| 1698 | red_hi1_bc_c5b_l[13], red_lo1_bc_c5b_l[13], red_hi0_bc_c5b_l[13],red_lo0_bc_c5b_l[13], |
| 1699 | red_hi1_bc_c5b_l[12], red_lo1_bc_c5b_l[12], red_hi0_bc_c5b_l[12],red_lo0_bc_c5b_l[12], |
| 1700 | red_hi1_bc_c5b_l[11], red_lo1_bc_c5b_l[11], red_hi0_bc_c5b_l[11],red_lo0_bc_c5b_l[11], |
| 1701 | red_hi1_bc_c5b_l[10], red_lo1_bc_c5b_l[10], red_hi0_bc_c5b_l[10],red_lo0_bc_c5b_l[10], red_hi1_bc_c5b_l[9]}; |
| 1702 | |
| 1703 | assign red_rd_data[79:60] = { |
| 1704 | red_hi0_bc_c5b_l[19], red_lo0_bc_c5b_l[19], |
| 1705 | red_hi1_bc_c5b_l[18], red_lo1_bc_c5b_l[18], red_hi0_bc_c5b_l[18],red_lo0_bc_c5b_l[18], |
| 1706 | red_hi1_bc_c5b_l[17], red_lo1_bc_c5b_l[17], red_hi0_bc_c5b_l[17],red_lo0_bc_c5b_l[17], |
| 1707 | red_hi1_bc_c5b_l[16], red_lo1_bc_c5b_l[16], red_hi0_bc_c5b_l[16],red_lo0_bc_c5b_l[16], |
| 1708 | red_hi1_bc_c5b_l[15], red_lo1_bc_c5b_l[15], red_hi0_bc_c5b_l[15],red_lo0_bc_c5b_l[15], red_hi1_bc_c5b_l[14],redrow_rdd_spare_1}; |
| 1709 | |
| 1710 | |
| 1711 | always@(cred_mod or red_rd_data) |
| 1712 | begin |
| 1713 | |
| 1714 | for(i=0;i<19;i=i+1) |
| 1715 | begin |
| 1716 | red_read_data[i] = cred_mod[i] ? red_rd_data[i+1] : red_rd_data[i]; |
| 1717 | end |
| 1718 | |
| 1719 | for(i=20;i<40;i=i+1) |
| 1720 | begin |
| 1721 | red_read_data[i] = cred_mod[i] ? red_rd_data[i-1] : red_rd_data[i]; |
| 1722 | end |
| 1723 | |
| 1724 | |
| 1725 | for(i=40;i<60;i=i+1) |
| 1726 | begin |
| 1727 | red_read_data[i] = cred_mod[i] ? red_rd_data[i+1] : red_rd_data[i]; |
| 1728 | end |
| 1729 | |
| 1730 | for(i=61;i<80;i=i+1) |
| 1731 | begin |
| 1732 | red_read_data[i] = cred_mod[i] ? red_rd_data[i-1] : red_rd_data[i]; |
| 1733 | end |
| 1734 | |
| 1735 | end |
| 1736 | |
| 1737 | |
| 1738 | |
| 1739 | assign { red_hi0_b_out_l[19], red_lo0_b_out_l[19], |
| 1740 | red_hi1_b_out_l[18], red_lo1_b_out_l[18], red_hi0_b_out_l[18],red_lo0_b_out_l[18], |
| 1741 | red_hi1_b_out_l[17], red_lo1_b_out_l[17], red_hi0_b_out_l[17],red_lo0_b_out_l[17], |
| 1742 | red_hi1_b_out_l[16], red_lo1_b_out_l[16], red_hi0_b_out_l[16],red_lo0_b_out_l[16], |
| 1743 | red_hi1_b_out_l[15], red_lo1_b_out_l[15], red_hi0_b_out_l[15],red_lo0_b_out_l[15], |
| 1744 | red_hi1_b_out_l[14]} = red_read_data[79:61]; |
| 1745 | |
| 1746 | assign {red_lo1_b_out_l[14], red_hi0_b_out_l[14],red_lo0_b_out_l[14], |
| 1747 | red_hi1_b_out_l[13], red_lo1_b_out_l[13], red_hi0_b_out_l[13],red_lo0_b_out_l[13], |
| 1748 | red_hi1_b_out_l[12], red_lo1_b_out_l[12], red_hi0_b_out_l[12],red_lo0_b_out_l[12], |
| 1749 | red_hi1_b_out_l[11], red_lo1_b_out_l[11], red_hi0_b_out_l[11],red_lo0_b_out_l[11], |
| 1750 | red_hi1_b_out_l[10], red_lo1_b_out_l[10], red_hi0_b_out_l[10],red_lo0_b_out_l[10], |
| 1751 | red_hi1_b_out_l[9]} = red_read_data[59:40]; |
| 1752 | |
| 1753 | assign { red_lo1_b_out_l[9], red_hi0_b_out_l[9],red_lo0_b_out_l[9], |
| 1754 | red_hi1_b_out_l[8], red_lo1_b_out_l[8], red_hi0_b_out_l[8],red_lo0_b_out_l[8], |
| 1755 | red_hi1_b_out_l[7], red_lo1_b_out_l[7], red_hi0_b_out_l[7],red_lo0_b_out_l[7], |
| 1756 | red_hi1_b_out_l[6], red_lo1_b_out_l[6], red_hi0_b_out_l[6],red_lo0_b_out_l[6], |
| 1757 | red_hi1_b_out_l[5], red_lo1_b_out_l[5], red_hi0_b_out_l[5],red_lo0_b_out_l[5], |
| 1758 | red_hi1_b_out_l[4]} = red_read_data[39:20]; |
| 1759 | |
| 1760 | assign {red_lo1_b_out_l[4], red_hi0_b_out_l[4],red_lo0_b_out_l[4], |
| 1761 | red_hi1_b_out_l[3], red_lo1_b_out_l[3], red_hi0_b_out_l[3],red_lo0_b_out_l[3], |
| 1762 | red_hi1_b_out_l[2], red_lo1_b_out_l[2], red_hi0_b_out_l[2],red_lo0_b_out_l[2], |
| 1763 | red_hi1_b_out_l[1], red_lo1_b_out_l[1], red_hi0_b_out_l[1],red_lo0_b_out_l[1], |
| 1764 | red_hi1_b_out_l[0], red_lo1_b_out_l[0], red_hi0_b_out_l[0],red_lo0_b_out_l[0]} = red_read_data[18:0]; |
| 1765 | |
| 1766 | |
| 1767 | ////////////////////////////////////////////////////////////////////////////// |
| 1768 | // col redudancy |
| 1769 | // hi1, lo1, hi0, lo0 |
| 1770 | |
| 1771 | //assign cred_mod_lo0[18:0] = cred_mod[18:0]; |
| 1772 | //assign cred_mod_hi0[38:19] = cred_mod[38:19]; |
| 1773 | //assign cred_mod_lo1[58:39] = cred_mod[58:39]; |
| 1774 | //assign cred_mod_hi1[77:59] = cred_mod[77:59]; |
| 1775 | |
| 1776 | // mux 0+1 |
| 1777 | // mux 19 spare |
| 1778 | // mux 18 and spare |
| 1779 | // mux 38 and 37 |
| 1780 | // mux 77 |
| 1781 | |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | endmodule |
| 1786 | |
| 1787 | |
| 1788 | module n2_l2d_dmux78_cust ( |
| 1789 | waysel_c3, |
| 1790 | set_c3, |
| 1791 | coloff_c3, |
| 1792 | coloff_c4_l, |
| 1793 | rd_wr_c3, |
| 1794 | worden_c3, |
| 1795 | l2clk, |
| 1796 | tcu_pce_ov, |
| 1797 | tcu_pce, |
| 1798 | se, |
| 1799 | tcu_clk_stop, |
| 1800 | waysel_top_c4, |
| 1801 | waysel_bot_c4, |
| 1802 | set_top_c3b, |
| 1803 | set_bot_c3b, |
| 1804 | coloff_top_c3b_l, |
| 1805 | coloff_bot_c3b_l, |
| 1806 | writeen_top_c3b, |
| 1807 | writeen_bot_c3b, |
| 1808 | l1clk, |
| 1809 | worden_top_c3b, |
| 1810 | worden_bot_c3b, |
| 1811 | sat_lo0_bc_l, |
| 1812 | sat_hi0_bc_l, |
| 1813 | sat_lo1_bc_l, |
| 1814 | sat_hi1_bc_l, |
| 1815 | sab_lo0_bc_l, |
| 1816 | sab_hi0_bc_l, |
| 1817 | sab_lo1_bc_l, |
| 1818 | sab_hi1_bc_l, |
| 1819 | ldin0lo_b, |
| 1820 | ldin0hi_b, |
| 1821 | ldin1lo_b, |
| 1822 | ldin1hi_b, |
| 1823 | ldout0lo_b, |
| 1824 | ldout0hi_b, |
| 1825 | ldout1lo_b, |
| 1826 | ldout1hi_b, |
| 1827 | red_d_in_00, |
| 1828 | red_d_out_00, |
| 1829 | fuse_l2d_rid_00, |
| 1830 | fuse_l2d_wren_00, |
| 1831 | fuse_l2d_reset_00_l, |
| 1832 | sel_quad_00, |
| 1833 | red_d_in_01, |
| 1834 | red_d_out_01, |
| 1835 | fuse_l2d_rid_01, |
| 1836 | fuse_l2d_wren_01, |
| 1837 | fuse_l2d_reset_01_l, |
| 1838 | sel_quad_01, |
| 1839 | red_addr_top, |
| 1840 | red_addr_bot, |
| 1841 | red_top_d_00, |
| 1842 | red_top_d_01, |
| 1843 | cred); |
| 1844 | |
| 1845 | input [7:0] waysel_c3; |
| 1846 | input [8:0] set_c3; |
| 1847 | input coloff_c3; |
| 1848 | input coloff_c4_l; |
| 1849 | //input [1:0] coloff_c5; |
| 1850 | input rd_wr_c3; |
| 1851 | //input readen_c5; |
| 1852 | input [3:0] worden_c3; |
| 1853 | input l2clk; |
| 1854 | input tcu_pce_ov; |
| 1855 | input tcu_pce; |
| 1856 | input se; |
| 1857 | input tcu_clk_stop; |
| 1858 | |
| 1859 | output [7:0] waysel_top_c4; |
| 1860 | output [7:0] waysel_bot_c4; |
| 1861 | output [8:0] set_top_c3b; // Set 8 will be inverted for top/bot |
| 1862 | output [8:0] set_bot_c3b; // Set 8 will be inverted for top/bot |
| 1863 | output coloff_top_c3b_l; |
| 1864 | output coloff_bot_c3b_l; |
| 1865 | //output coloff_top_c4_l ; |
| 1866 | //output coloff_bot_c4_l; |
| 1867 | //output [1:0] coloff_top_c5; |
| 1868 | //output [1:0] coloff_bot_c5; |
| 1869 | output writeen_top_c3b; |
| 1870 | output writeen_bot_c3b; |
| 1871 | //output readen_top_c5; |
| 1872 | //output readen_bot_c5; |
| 1873 | output l1clk; |
| 1874 | output [3:0] worden_top_c3b; |
| 1875 | output [3:0] worden_bot_c3b; |
| 1876 | |
| 1877 | |
| 1878 | input [19:0] sat_lo0_bc_l; // Senseamp out from top-16kb |
| 1879 | input [19:0] sat_hi0_bc_l; // Senseamp out from top-16kb |
| 1880 | input [18:0] sat_lo1_bc_l; // Senseamp out from top-16kb |
| 1881 | input [18:0] sat_hi1_bc_l; // Senseamp out from top-16kb |
| 1882 | input [19:0] sab_lo0_bc_l; // Senseamp out from bot-16kb |
| 1883 | input [19:0] sab_hi0_bc_l; // Senseamp out from bot-16kb |
| 1884 | input [18:0] sab_lo1_bc_l; // Senseamp out from bot-16kb |
| 1885 | input [18:0] sab_hi1_bc_l; // Senseamp out from bot-16kb |
| 1886 | input [19:0] ldin0lo_b; |
| 1887 | input [19:0] ldin0hi_b; |
| 1888 | input [18:0] ldin1lo_b; |
| 1889 | input [18:0] ldin1hi_b; |
| 1890 | //input bnken_lat; // Address latch enable (1.5cycle) |
| 1891 | output [19:0] ldout0lo_b; |
| 1892 | output [19:0] ldout0hi_b; |
| 1893 | output [18:0] ldout1lo_b; |
| 1894 | output [18:0] ldout1hi_b; |
| 1895 | |
| 1896 | |
| 1897 | input [9:0] red_d_in_00; |
| 1898 | output [9:0] red_d_out_00; |
| 1899 | input [2:0] fuse_l2d_rid_00; |
| 1900 | input fuse_l2d_wren_00; |
| 1901 | input fuse_l2d_reset_00_l; |
| 1902 | input sel_quad_00; |
| 1903 | |
| 1904 | input [9:0] red_d_in_01; |
| 1905 | output [9:0] red_d_out_01; |
| 1906 | input [2:0] fuse_l2d_rid_01; |
| 1907 | input fuse_l2d_wren_01; |
| 1908 | input fuse_l2d_reset_01_l; |
| 1909 | input sel_quad_01; |
| 1910 | |
| 1911 | output [9:0] red_addr_top; |
| 1912 | output [9:0] red_addr_bot; |
| 1913 | // forwarded |
| 1914 | input [9:0] red_top_d_00; |
| 1915 | input [9:0] red_top_d_01; |
| 1916 | |
| 1917 | output [77:0] cred; |
| 1918 | //output fuse_l2d_reset_00_l_buf; |
| 1919 | //output fuse_l2d_reset_01_l_buf; |
| 1920 | |
| 1921 | reg [7:0] waysel_top_c4; |
| 1922 | reg [7:0] waysel_bot_c4; |
| 1923 | reg [8:0] set_top_c3b; |
| 1924 | reg [8:0] set_bot_c3b; |
| 1925 | reg writeen_top_c3b; |
| 1926 | reg writeen_bot_c3b; |
| 1927 | reg [3:0] worden_top_c3b; |
| 1928 | reg [3:0] worden_bot_c3b; |
| 1929 | reg coloff_top_c3b_l; |
| 1930 | reg coloff_bot_c3b_l; |
| 1931 | reg [7:0] waysel_top_c3b; |
| 1932 | reg [7:0] waysel_bot_c3b; |
| 1933 | //always@(posedge l2clk) |
| 1934 | always@(negedge l2clk) |
| 1935 | begin |
| 1936 | coloff_top_c3b_l <= ~coloff_c3; |
| 1937 | coloff_bot_c3b_l <= ~coloff_c3; |
| 1938 | worden_top_c3b[3:0] <= worden_c3[3:0]; |
| 1939 | worden_bot_c3b[3:0] <= worden_c3[3:0]; |
| 1940 | writeen_top_c3b <= ~rd_wr_c3; |
| 1941 | writeen_bot_c3b <= ~rd_wr_c3; |
| 1942 | end |
| 1943 | |
| 1944 | //always@(negedge l2clk) |
| 1945 | //always@(l2clk or bnken_lat) |
| 1946 | always@(l2clk or coloff_c4_l) |
| 1947 | begin |
| 1948 | // if(~bnken_lat) |
| 1949 | if(~l2clk & coloff_c4_l) |
| 1950 | begin |
| 1951 | waysel_top_c3b[7:0] <= waysel_c3[7:0]; |
| 1952 | waysel_bot_c3b[7:0] <= waysel_c3[7:0]; |
| 1953 | set_bot_c3b[8:0] <= set_c3[8:0]; |
| 1954 | set_top_c3b[8:0] <= {~set_c3[8],set_c3[7:0]}; |
| 1955 | |
| 1956 | end |
| 1957 | end |
| 1958 | |
| 1959 | always@(posedge l2clk ) |
| 1960 | begin |
| 1961 | waysel_top_c4[7:0] <= waysel_top_c3b[7:0]; |
| 1962 | waysel_bot_c4[7:0] <= waysel_bot_c3b[7:0]; |
| 1963 | end |
| 1964 | //assign readen_top_c5 = readen_c5; |
| 1965 | //assign readen_bot_c5 = readen_c5; |
| 1966 | //assign coloff_top_c5 = coloff_c5[1:0]; |
| 1967 | //assign coloff_bot_c5 = coloff_c5[1:0]; |
| 1968 | //assign coloff_top_c4_l = coloff_c4_l; |
| 1969 | //assign coloff_bot_c4_l = coloff_c4_l; |
| 1970 | |
| 1971 | |
| 1972 | wire [19:0] sat_lo0_bc; |
| 1973 | wire [19:0] sab_lo0_bc; |
| 1974 | wire [19:0] sat_hi0_bc; |
| 1975 | wire [19:0] sab_hi0_bc; |
| 1976 | |
| 1977 | wire [18:0] sat_lo1_bc; |
| 1978 | wire [18:0] sab_lo1_bc; |
| 1979 | wire [18:0] sat_hi1_bc; |
| 1980 | wire [18:0] sab_hi1_bc; |
| 1981 | |
| 1982 | |
| 1983 | //always@(posedge l1clk) |
| 1984 | //begin |
| 1985 | assign sat_lo0_bc[19:0] = ~sat_lo0_bc_l[19:0]; |
| 1986 | assign sab_lo0_bc[19:0] = ~sab_lo0_bc_l[19:0]; |
| 1987 | assign sat_hi0_bc[19:0] = ~sat_hi0_bc_l[19:0]; |
| 1988 | assign sab_hi0_bc[19:0] = ~sab_hi0_bc_l[19:0]; |
| 1989 | |
| 1990 | assign sat_lo1_bc[18:0] = ~sat_lo1_bc_l[18:0]; |
| 1991 | assign sab_lo1_bc[18:0] = ~sab_lo1_bc_l[18:0]; |
| 1992 | assign sat_hi1_bc[18:0] = ~sat_hi1_bc_l[18:0]; |
| 1993 | assign sab_hi1_bc[18:0] = ~sab_hi1_bc_l[18:0]; |
| 1994 | //end |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | n2_l2d_32kb_cust_or_macro__ports_3__width_20 or_ldout0lo_b |
| 1999 | ( |
| 2000 | .dout (ldout0lo_b[19:0]), |
| 2001 | .din0 (sat_lo0_bc[19:0]), |
| 2002 | .din1 (sab_lo0_bc[19:0]), |
| 2003 | .din2 (ldin0lo_b[19:0]) |
| 2004 | ); |
| 2005 | |
| 2006 | n2_l2d_32kb_cust_or_macro__ports_3__width_20 or_ldout0hi_b |
| 2007 | ( |
| 2008 | .dout (ldout0hi_b[19:0]), |
| 2009 | .din0 (sat_hi0_bc[19:0]), |
| 2010 | .din1 (sab_hi0_bc[19:0]), |
| 2011 | .din2 (ldin0hi_b[19:0]) |
| 2012 | ); |
| 2013 | |
| 2014 | n2_l2d_32kb_cust_or_macro__ports_3__width_19 or_ldout1lo_b |
| 2015 | ( |
| 2016 | .dout (ldout1lo_b[18:0]), |
| 2017 | .din0 (sat_lo1_bc[18:0]), |
| 2018 | .din1 (sab_lo1_bc[18:0]), |
| 2019 | .din2 (ldin1lo_b[18:0]) |
| 2020 | ); |
| 2021 | |
| 2022 | |
| 2023 | n2_l2d_32kb_cust_or_macro__ports_3__width_19 or_ldout1hi_b |
| 2024 | ( |
| 2025 | .dout (ldout1hi_b[18:0]), |
| 2026 | .din0 (sat_hi1_bc[18:0]), |
| 2027 | .din1 (sab_hi1_bc[18:0]), |
| 2028 | .din2 (ldin1hi_b[18:0]) |
| 2029 | ); |
| 2030 | |
| 2031 | |
| 2032 | cl_sc1_l1hdr_12x clk_hdr ( |
| 2033 | .l2clk (l2clk), |
| 2034 | .se (se), |
| 2035 | .pce (tcu_pce), |
| 2036 | .pce_ov (tcu_pce_ov), |
| 2037 | .stop (tcu_clk_stop), |
| 2038 | .l1clk (l1clk) |
| 2039 | ); |
| 2040 | |
| 2041 | |
| 2042 | // Redudant row modelling |
| 2043 | |
| 2044 | |
| 2045 | |
| 2046 | reg [9:0] red_odd_0; |
| 2047 | reg [9:0] red_odd_1; |
| 2048 | reg [9:0] red_even_0; |
| 2049 | reg [9:0] red_even_1; |
| 2050 | reg [7:0] red_col_0; |
| 2051 | reg [7:0] red_col_1; |
| 2052 | //reg [9:0] red_d_out_00; |
| 2053 | //reg [9:0] red_d_out_01; |
| 2054 | |
| 2055 | wire red_reg_clk_even_0; |
| 2056 | wire red_reg_clk_even_1; |
| 2057 | wire red_reg_clk_odd_0; |
| 2058 | wire red_reg_clk_odd_1; |
| 2059 | wire red_reg_clk_col_0; |
| 2060 | wire red_reg_clk_col_1; |
| 2061 | wire [9:0] red_data_00; |
| 2062 | wire [9:0] red_data_01; |
| 2063 | |
| 2064 | // Initialize the register. |
| 2065 | initial begin |
| 2066 | |
| 2067 | red_odd_0[9:0] = 10'b0; |
| 2068 | red_odd_1[9:0] = 10'b0; |
| 2069 | red_even_0[9:0]= 10'b0; |
| 2070 | red_even_1[9:0]= 10'b0; |
| 2071 | red_col_0[7:0] = 8'b0; |
| 2072 | red_col_1[7:0] = 8'b0; |
| 2073 | end |
| 2074 | |
| 2075 | assign red_reg_clk_even_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b000) & sel_quad_00) | ~fuse_l2d_reset_00_l); |
| 2076 | assign red_reg_clk_even_1 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b010) & sel_quad_00) | ~fuse_l2d_reset_00_l); |
| 2077 | assign red_reg_clk_col_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b100) & sel_quad_00) | ~fuse_l2d_reset_00_l); |
| 2078 | |
| 2079 | assign red_reg_clk_odd_0 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b001) & sel_quad_01) | ~fuse_l2d_reset_01_l); |
| 2080 | assign red_reg_clk_odd_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b011) & sel_quad_01) | ~fuse_l2d_reset_01_l); |
| 2081 | assign red_reg_clk_col_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b101) & sel_quad_01) | ~fuse_l2d_reset_01_l); |
| 2082 | |
| 2083 | assign red_data_00[9:0] = red_d_in_00[9:0] & {10{fuse_l2d_reset_00_l}}; |
| 2084 | assign red_data_01[9:0] = red_d_in_01[9:0] & {10{fuse_l2d_reset_01_l}}; |
| 2085 | |
| 2086 | always @(red_reg_clk_even_0 or red_reg_clk_even_1 or red_reg_clk_col_0 or red_reg_clk_odd_0 or red_reg_clk_odd_1 or red_reg_clk_col_1 or red_d_in_00 or red_d_in_01) begin |
| 2087 | if (~red_reg_clk_even_0) begin |
| 2088 | red_even_0[9:0] <= red_data_00[9:0]; |
| 2089 | end |
| 2090 | |
| 2091 | if (~red_reg_clk_even_1) begin |
| 2092 | red_even_1[9:0] <= red_data_00[9:0]; |
| 2093 | end |
| 2094 | |
| 2095 | if (~red_reg_clk_col_0) begin |
| 2096 | red_col_0[7:0] <= {red_data_00[9:8],red_data_00[5:0]}; |
| 2097 | end |
| 2098 | |
| 2099 | if (~red_reg_clk_odd_0) begin |
| 2100 | red_odd_0[9:0] <= red_data_01[9:0]; |
| 2101 | end |
| 2102 | |
| 2103 | if (~red_reg_clk_odd_1) begin |
| 2104 | red_odd_1[9:0] <= red_data_01[9:0]; |
| 2105 | end |
| 2106 | |
| 2107 | if (~red_reg_clk_col_1) begin |
| 2108 | red_col_1[7:0] <= {red_data_01[9:8],red_data_01[5:0]}; |
| 2109 | end |
| 2110 | end |
| 2111 | |
| 2112 | |
| 2113 | // 00 = bot and 01 = top |
| 2114 | |
| 2115 | //always@(fuse_l2d_wren_00 or fuse_l2d_wren_01 or fuse_l2d_rid_01 or fuse_l2d_rid_00 |
| 2116 | // or red_d_in_00 or red_d_in_01 or sel_quad_00 or sel_quad_01) |
| 2117 | //begin |
| 2118 | // if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_bot_c3b[8] & (fuse_l2d_rid_00[2:1]==2'b00) & sel_quad_00) |
| 2119 | // red_even_0 <= red_d_in_00; |
| 2120 | // else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_00) |
| 2121 | // red_even_1 <= red_d_in_00; |
| 2122 | // else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_00) |
| 2123 | // red_col_0 <= red_d_in_00[7:0]; |
| 2124 | // |
| 2125 | // if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b00) & sel_quad_01) |
| 2126 | // red_odd_0 <= red_d_in_01; |
| 2127 | // else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_bot_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_01) |
| 2128 | // red_odd_1 <= red_d_in_01; |
| 2129 | // else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_01) |
| 2130 | // red_col_1 <= red_d_in_01[7:0]; |
| 2131 | //end |
| 2132 | // |
| 2133 | |
| 2134 | //assign red_addr_top = set_top_c3b[0] ? red_odd_0 : red_even_0; |
| 2135 | //assign red_addr_bot = set_top_c3b[0] ? red_odd_1 : red_even_1; |
| 2136 | assign red_addr_top = set_top_c3b[0] ? red_odd_1 : red_even_1; |
| 2137 | assign red_addr_bot = set_top_c3b[0] ? red_odd_0 : red_even_0; |
| 2138 | |
| 2139 | assign red_d_out_00[7:0] = (red_even_0[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b000}}) | |
| 2140 | (red_even_1[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b010}}) | |
| 2141 | ({2'b0,(red_col_0[5:0] & {6{fuse_l2d_rid_00[2:0]==3'b100}})}) | |
| 2142 | (red_top_d_00[7:0] & {8{~sel_quad_00}}); |
| 2143 | |
| 2144 | assign red_d_out_00[9:8] = (red_even_0[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b000}}) | |
| 2145 | (red_even_1[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b010}}) | |
| 2146 | (red_col_0[7:6] & {2{fuse_l2d_rid_00[2:0]==3'b100}}) | |
| 2147 | (red_top_d_00[9:8] & {2{~sel_quad_00}}); |
| 2148 | |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | assign red_d_out_01[7:0] = (red_odd_0[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b001}}) | |
| 2153 | (red_odd_1[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b011}}) | |
| 2154 | ({2'b0,(red_col_1[5:0] & {6{fuse_l2d_rid_01[2:0]==3'b101}})}) | |
| 2155 | (red_top_d_01[7:0] & {8{~sel_quad_01}}); |
| 2156 | |
| 2157 | assign red_d_out_01[9:8] = (red_odd_0[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b001}}) | |
| 2158 | (red_odd_1[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b011}}) | |
| 2159 | (red_col_1[7:6] & {2{fuse_l2d_rid_01[2:0]==3'b101}}) | |
| 2160 | (red_top_d_01[9:8] & {2{~sel_quad_01}}); |
| 2161 | |
| 2162 | |
| 2163 | |
| 2164 | //always@(fuse_l2d_rid_00) |
| 2165 | //begin |
| 2166 | //case(fuse_l2d_rid_00) |
| 2167 | //3'b000 : begin |
| 2168 | // red_d_out_00 = red_even_0; |
| 2169 | // red_d_out_01 = 10'b0; |
| 2170 | // end |
| 2171 | //3'b010 : begin |
| 2172 | // red_d_out_00 = red_even_1; |
| 2173 | // red_d_out_01 = 10'b0; |
| 2174 | // end |
| 2175 | //3'b100 : begin |
| 2176 | // red_d_out_00 = {2'b0,red_col_0}; |
| 2177 | // red_d_out_01 = 10'b0; |
| 2178 | // end |
| 2179 | // |
| 2180 | //3'b001 : begin |
| 2181 | // red_d_out_01 = red_odd_0; |
| 2182 | // red_d_out_00 = 10'b0; |
| 2183 | // end |
| 2184 | //3'b011 : begin |
| 2185 | // red_d_out_01 = red_odd_1; |
| 2186 | // red_d_out_00 = 10'b0; |
| 2187 | // end |
| 2188 | //3'b101 : begin |
| 2189 | // red_d_out_01 = {2'b0,red_col_1}; |
| 2190 | // red_d_out_00 = 10'b0; |
| 2191 | // end |
| 2192 | // |
| 2193 | //default : begin |
| 2194 | // red_d_out_00 = red_top_d_00; |
| 2195 | // red_d_out_01 = red_top_d_01; |
| 2196 | // end |
| 2197 | //endcase |
| 2198 | //end |
| 2199 | |
| 2200 | // Col redudancy |
| 2201 | |
| 2202 | //reg [7:0] red_col_0; |
| 2203 | //reg [7:0] red_col_1; |
| 2204 | |
| 2205 | reg [38:0] cred0; |
| 2206 | reg [38:0] cred1; |
| 2207 | |
| 2208 | // Initialize cred0, cred1 |
| 2209 | initial begin |
| 2210 | cred0[38:0] = 39'b0; |
| 2211 | cred1[38:0] = 39'b0; |
| 2212 | end |
| 2213 | |
| 2214 | always@(red_col_0) |
| 2215 | if(red_col_0[7] & red_col_0[6] & ~red_col_0[5]) |
| 2216 | case(red_col_0) |
| 2217 | 8'b11_0_00000 : cred0[18:0] = 19'b111_1111_1111_1111_1111; //0 |
| 2218 | 8'b11_0_00001 : cred0[18:0] = 19'b111_1111_1111_1111_1110; //1 |
| 2219 | 8'b11_0_00010 : cred0[18:0] = 19'b111_1111_1111_1111_1100; //2 |
| 2220 | 8'b11_0_00011 : cred0[18:0] = 19'b111_1111_1111_1111_1000; //3 |
| 2221 | 8'b11_0_00100 : cred0[18:0] = 19'b111_1111_1111_1111_0000; //4 |
| 2222 | 8'b11_0_00101 : cred0[18:0] = 19'b111_1111_1111_1110_0000; //5 |
| 2223 | 8'b11_0_00110 : cred0[18:0] = 19'b111_1111_1111_1100_0000; //6 |
| 2224 | 8'b11_0_00111 : cred0[18:0] = 19'b111_1111_1111_1000_0000; //7 |
| 2225 | 8'b11_0_01000 : cred0[18:0] = 19'b111_1111_1111_0000_0000; //8 |
| 2226 | 8'b11_0_01001 : cred0[18:0] = 19'b111_1111_1110_0000_0000; //9 |
| 2227 | 8'b11_0_01010 : cred0[18:0] = 19'b111_1111_1100_0000_0000; //10 |
| 2228 | 8'b11_0_01011 : cred0[18:0] = 19'b111_1111_1000_0000_0000; //11 |
| 2229 | 8'b11_0_01100 : cred0[18:0] = 19'b111_1111_0000_0000_0000; //12 |
| 2230 | 8'b11_0_01101 : cred0[18:0] = 19'b111_1110_0000_0000_0000; //13 |
| 2231 | 8'b11_0_01110 : cred0[18:0] = 19'b111_1100_0000_0000_0000; //14 |
| 2232 | 8'b11_0_01111 : cred0[18:0] = 19'b111_1000_0000_0000_0000; //15 |
| 2233 | 8'b11_0_10000 : cred0[18:0] = 19'b111_0000_0000_0000_0000; //16 |
| 2234 | 8'b11_0_10001 : cred0[18:0] = 19'b110_0000_0000_0000_0000; //17 |
| 2235 | 8'b11_0_10010 : cred0[18:0] = 19'b100_0000_0000_0000_0000; //18 |
| 2236 | default : cred0[18:0] = 19'b0; |
| 2237 | endcase |
| 2238 | else cred0[18:0] = 19'b0; |
| 2239 | |
| 2240 | always@(red_col_0) |
| 2241 | if(red_col_0[7] & red_col_0[6] & red_col_0[5]) |
| 2242 | case(red_col_0) |
| 2243 | 8'b11_1_00000 : cred0[38:19] = 20'b1111_1111_1111_1111_1111;//0 |
| 2244 | 8'b11_1_00001 : cred0[38:19] = 20'b0111_1111_1111_1111_1111;//1 |
| 2245 | 8'b11_1_00010 : cred0[38:19] = 20'b0011_1111_1111_1111_1111;//2 |
| 2246 | 8'b11_1_00011 : cred0[38:19] = 20'b0001_1111_1111_1111_1111;//3 |
| 2247 | 8'b11_1_00100 : cred0[38:19] = 20'b0000_1111_1111_1111_1111;//4 |
| 2248 | 8'b11_1_00101 : cred0[38:19] = 20'b0000_0111_1111_1111_1111;//5 |
| 2249 | 8'b11_1_00110 : cred0[38:19] = 20'b0000_0011_1111_1111_1111;//6 |
| 2250 | 8'b11_1_00111 : cred0[38:19] = 20'b0000_0001_1111_1111_1111;//7 |
| 2251 | 8'b11_1_01000 : cred0[38:19] = 20'b0000_0000_1111_1111_1111;//8 |
| 2252 | 8'b11_1_01001 : cred0[38:19] = 20'b0000_0000_0111_1111_1111;//9 |
| 2253 | 8'b11_1_01010 : cred0[38:19] = 20'b0000_0000_0011_1111_1111;//10 |
| 2254 | 8'b11_1_01011 : cred0[38:19] = 20'b0000_0000_0001_1111_1111;//11 |
| 2255 | 8'b11_1_01100 : cred0[38:19] = 20'b0000_0000_0000_1111_1111;//12 |
| 2256 | 8'b11_1_01101 : cred0[38:19] = 20'b0000_0000_0000_0111_1111;//13 |
| 2257 | 8'b11_1_01110 : cred0[38:19] = 20'b0000_0000_0000_0011_1111;//14 |
| 2258 | 8'b11_1_01111 : cred0[38:19] = 20'b0000_0000_0000_0001_1111;//15 |
| 2259 | 8'b11_1_10000 : cred0[38:19] = 20'b0000_0000_0000_0000_1111;//16 |
| 2260 | 8'b11_1_10001 : cred0[38:19] = 20'b0000_0000_0000_0000_0111;//17 |
| 2261 | 8'b11_1_10010 : cred0[38:19] = 20'b0000_0000_0000_0000_0011;//18 |
| 2262 | 8'b11_1_10011 : cred0[38:19] = 20'b0000_0000_0000_0000_0001;//19 |
| 2263 | default : cred0[38:19] = 20'b0; |
| 2264 | endcase |
| 2265 | else cred0[38:19] = 20'b0; |
| 2266 | |
| 2267 | always@(red_col_1) |
| 2268 | if(red_col_1[7] & red_col_1[6] & red_col_1[5]) |
| 2269 | case(red_col_1) |
| 2270 | 8'b11_1_00000 : cred1[19:0] = 20'b1111_1111_1111_1111_1111; //0 |
| 2271 | 8'b11_1_00001 : cred1[19:0] = 20'b1111_1111_1111_1111_1110; //1 |
| 2272 | 8'b11_1_00010 : cred1[19:0] = 20'b1111_1111_1111_1111_1100; //2 |
| 2273 | 8'b11_1_00011 : cred1[19:0] = 20'b1111_1111_1111_1111_1000; //3 |
| 2274 | 8'b11_1_00100 : cred1[19:0] = 20'b1111_1111_1111_1111_0000; //4 |
| 2275 | 8'b11_1_00101 : cred1[19:0] = 20'b1111_1111_1111_1110_0000; //5 |
| 2276 | 8'b11_1_00110 : cred1[19:0] = 20'b1111_1111_1111_1100_0000; //6 |
| 2277 | 8'b11_1_00111 : cred1[19:0] = 20'b1111_1111_1111_1000_0000; //7 |
| 2278 | 8'b11_1_01000 : cred1[19:0] = 20'b1111_1111_1111_0000_0000; //8 |
| 2279 | 8'b11_1_01001 : cred1[19:0] = 20'b1111_1111_1110_0000_0000; //9 |
| 2280 | 8'b11_1_01010 : cred1[19:0] = 20'b1111_1111_1100_0000_0000; //10 |
| 2281 | 8'b11_1_01011 : cred1[19:0] = 20'b1111_1111_1000_0000_0000; //11 |
| 2282 | 8'b11_1_01100 : cred1[19:0] = 20'b1111_1111_0000_0000_0000; //12 |
| 2283 | 8'b11_1_01101 : cred1[19:0] = 20'b1111_1110_0000_0000_0000; //13 |
| 2284 | 8'b11_1_01110 : cred1[19:0] = 20'b1111_1100_0000_0000_0000; //14 |
| 2285 | 8'b11_1_01111 : cred1[19:0] = 20'b1111_1000_0000_0000_0000; //15 |
| 2286 | 8'b11_1_10000 : cred1[19:0] = 20'b1111_0000_0000_0000_0000; //16 |
| 2287 | 8'b11_1_10001 : cred1[19:0] = 20'b1110_0000_0000_0000_0000; //17 |
| 2288 | 8'b11_1_10010 : cred1[19:0] = 20'b1100_0000_0000_0000_0000; //18 |
| 2289 | 8'b11_1_10011 : cred1[19:0] = 20'b1000_0000_0000_0000_0000; //19 |
| 2290 | default : cred1[19:0] = 20'b0; |
| 2291 | endcase |
| 2292 | else cred1[19:0] = 20'b0; |
| 2293 | |
| 2294 | always@(red_col_1) |
| 2295 | if(red_col_1[7] & red_col_1[6] & ~red_col_1[5]) |
| 2296 | case(red_col_1) |
| 2297 | 8'b11_0_00000 : cred1[38:20] = 19'b111_1111_1111_1111_1111;//0 |
| 2298 | 8'b11_0_00001 : cred1[38:20] = 19'b011_1111_1111_1111_1111;//1 |
| 2299 | 8'b11_0_00010 : cred1[38:20] = 19'b001_1111_1111_1111_1111;//2 |
| 2300 | 8'b11_0_00011 : cred1[38:20] = 19'b000_1111_1111_1111_1111;//3 |
| 2301 | 8'b11_0_00100 : cred1[38:20] = 19'b000_0111_1111_1111_1111;//4 |
| 2302 | 8'b11_0_00101 : cred1[38:20] = 19'b000_0011_1111_1111_1111;//5 |
| 2303 | 8'b11_0_00110 : cred1[38:20] = 19'b000_0001_1111_1111_1111;//6 |
| 2304 | 8'b11_0_00111 : cred1[38:20] = 19'b000_0000_1111_1111_1111;//7 |
| 2305 | 8'b11_0_01000 : cred1[38:20] = 19'b000_0000_0111_1111_1111;//8 |
| 2306 | 8'b11_0_01001 : cred1[38:20] = 19'b000_0000_0011_1111_1111;//9 |
| 2307 | 8'b11_0_01010 : cred1[38:20] = 19'b000_0000_0001_1111_1111;//10 |
| 2308 | 8'b11_0_01011 : cred1[38:20] = 19'b000_0000_0000_1111_1111;//11 |
| 2309 | 8'b11_0_01100 : cred1[38:20] = 19'b000_0000_0000_0111_1111;//12 |
| 2310 | 8'b11_0_01101 : cred1[38:20] = 19'b000_0000_0000_0011_1111;//13 |
| 2311 | 8'b11_0_01110 : cred1[38:20] = 19'b000_0000_0000_0001_1111;//14 |
| 2312 | 8'b11_0_01111 : cred1[38:20] = 19'b000_0000_0000_0000_1111;//15 |
| 2313 | 8'b11_0_10000 : cred1[38:20] = 19'b000_0000_0000_0000_0111;//16 |
| 2314 | 8'b11_0_10001 : cred1[38:20] = 19'b000_0000_0000_0000_0011;//17 |
| 2315 | 8'b11_0_10010 : cred1[38:20] = 19'b000_0000_0000_0000_0001;//18 |
| 2316 | default : cred1[38:20] = 19'b0; |
| 2317 | endcase |
| 2318 | else cred1[38:20] = 19'b0; |
| 2319 | |
| 2320 | assign cred[77:0] = {cred1[38:0], cred0[38:0]}; |
| 2321 | //assign cred[77:0] = 78'b0; |
| 2322 | |
| 2323 | |
| 2324 | //assign fuse_l2d_reset_00_buf = fuse_l2d_reset_00; |
| 2325 | //assign fuse_l2d_reset_01_buf = fuse_l2d_reset_01; |
| 2326 | |
| 2327 | |
| 2328 | |
| 2329 | |
| 2330 | endmodule |
| 2331 | |
| 2332 | |
| 2333 | // |
| 2334 | // or macro for ports = 2,3 |
| 2335 | // |
| 2336 | // |
| 2337 | |
| 2338 | |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | module n2_l2d_32kb_cust_or_macro__ports_3__width_20 ( |
| 2343 | din0, |
| 2344 | din1, |
| 2345 | din2, |
| 2346 | dout); |
| 2347 | input [19:0] din0; |
| 2348 | input [19:0] din1; |
| 2349 | input [19:0] din2; |
| 2350 | output [19:0] dout; |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | |
| 2356 | |
| 2357 | or3 #(20) d0_0 ( |
| 2358 | .in0(din0[19:0]), |
| 2359 | .in1(din1[19:0]), |
| 2360 | .in2(din2[19:0]), |
| 2361 | .out(dout[19:0]) |
| 2362 | ); |
| 2363 | |
| 2364 | |
| 2365 | |
| 2366 | |
| 2367 | |
| 2368 | |
| 2369 | |
| 2370 | |
| 2371 | |
| 2372 | endmodule |
| 2373 | |
| 2374 | |
| 2375 | |
| 2376 | |
| 2377 | |
| 2378 | // |
| 2379 | // or macro for ports = 2,3 |
| 2380 | // |
| 2381 | // |
| 2382 | |
| 2383 | |
| 2384 | |
| 2385 | |
| 2386 | |
| 2387 | module n2_l2d_32kb_cust_or_macro__ports_3__width_19 ( |
| 2388 | din0, |
| 2389 | din1, |
| 2390 | din2, |
| 2391 | dout); |
| 2392 | input [18:0] din0; |
| 2393 | input [18:0] din1; |
| 2394 | input [18:0] din2; |
| 2395 | output [18:0] dout; |
| 2396 | |
| 2397 | |
| 2398 | |
| 2399 | |
| 2400 | |
| 2401 | |
| 2402 | or3 #(19) d0_0 ( |
| 2403 | .in0(din0[18:0]), |
| 2404 | .in1(din1[18:0]), |
| 2405 | .in2(din2[18:0]), |
| 2406 | .out(dout[18:0]) |
| 2407 | ); |
| 2408 | |
| 2409 | |
| 2410 | |
| 2411 | |
| 2412 | |
| 2413 | |
| 2414 | |
| 2415 | |
| 2416 | |
| 2417 | endmodule |
| 2418 | |
| 2419 | |
| 2420 | |
| 2421 | |