| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_l2d_dmux78_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_l2d_dmux78_cust ( |
| 36 | waysel_c3, |
| 37 | set_c3, |
| 38 | coloff_c3, |
| 39 | coloff_c4_l, |
| 40 | rd_wr_c3, |
| 41 | worden_c3, |
| 42 | l2clk, |
| 43 | tcu_pce_ov, |
| 44 | tcu_pce, |
| 45 | se, |
| 46 | tcu_clk_stop, |
| 47 | waysel_top_c4, |
| 48 | waysel_bot_c4, |
| 49 | set_top_c3b, |
| 50 | set_bot_c3b, |
| 51 | coloff_top_c3b_l, |
| 52 | coloff_bot_c3b_l, |
| 53 | writeen_top_c3b, |
| 54 | writeen_bot_c3b, |
| 55 | l1clk, |
| 56 | worden_top_c3b, |
| 57 | worden_bot_c3b, |
| 58 | sat_lo0_bc_l, |
| 59 | sat_hi0_bc_l, |
| 60 | sat_lo1_bc_l, |
| 61 | sat_hi1_bc_l, |
| 62 | sab_lo0_bc_l, |
| 63 | sab_hi0_bc_l, |
| 64 | sab_lo1_bc_l, |
| 65 | sab_hi1_bc_l, |
| 66 | ldin0lo_b, |
| 67 | ldin0hi_b, |
| 68 | ldin1lo_b, |
| 69 | ldin1hi_b, |
| 70 | ldout0lo_b, |
| 71 | ldout0hi_b, |
| 72 | ldout1lo_b, |
| 73 | ldout1hi_b, |
| 74 | red_d_in_00, |
| 75 | red_d_out_00, |
| 76 | fuse_l2d_rid_00, |
| 77 | fuse_l2d_wren_00, |
| 78 | fuse_l2d_reset_00_l, |
| 79 | sel_quad_00, |
| 80 | red_d_in_01, |
| 81 | red_d_out_01, |
| 82 | fuse_l2d_rid_01, |
| 83 | fuse_l2d_wren_01, |
| 84 | fuse_l2d_reset_01_l, |
| 85 | sel_quad_01, |
| 86 | red_addr_top, |
| 87 | red_addr_bot, |
| 88 | red_top_d_00, |
| 89 | red_top_d_01, |
| 90 | cred); |
| 91 | |
| 92 | input [7:0] waysel_c3; |
| 93 | input [8:0] set_c3; |
| 94 | input coloff_c3; |
| 95 | input coloff_c4_l; |
| 96 | //input [1:0] coloff_c5; |
| 97 | input rd_wr_c3; |
| 98 | //input readen_c5; |
| 99 | input [3:0] worden_c3; |
| 100 | input l2clk; |
| 101 | input tcu_pce_ov; |
| 102 | input tcu_pce; |
| 103 | input se; |
| 104 | input tcu_clk_stop; |
| 105 | |
| 106 | output [7:0] waysel_top_c4; |
| 107 | output [7:0] waysel_bot_c4; |
| 108 | output [8:0] set_top_c3b; // Set 8 will be inverted for top/bot |
| 109 | output [8:0] set_bot_c3b; // Set 8 will be inverted for top/bot |
| 110 | output coloff_top_c3b_l; |
| 111 | output coloff_bot_c3b_l; |
| 112 | //output coloff_top_c4_l ; |
| 113 | //output coloff_bot_c4_l; |
| 114 | //output [1:0] coloff_top_c5; |
| 115 | //output [1:0] coloff_bot_c5; |
| 116 | output writeen_top_c3b; |
| 117 | output writeen_bot_c3b; |
| 118 | //output readen_top_c5; |
| 119 | //output readen_bot_c5; |
| 120 | output l1clk; |
| 121 | output [3:0] worden_top_c3b; |
| 122 | output [3:0] worden_bot_c3b; |
| 123 | |
| 124 | |
| 125 | input [19:0] sat_lo0_bc_l; // Senseamp out from top-16kb |
| 126 | input [19:0] sat_hi0_bc_l; // Senseamp out from top-16kb |
| 127 | input [18:0] sat_lo1_bc_l; // Senseamp out from top-16kb |
| 128 | input [18:0] sat_hi1_bc_l; // Senseamp out from top-16kb |
| 129 | input [19:0] sab_lo0_bc_l; // Senseamp out from bot-16kb |
| 130 | input [19:0] sab_hi0_bc_l; // Senseamp out from bot-16kb |
| 131 | input [18:0] sab_lo1_bc_l; // Senseamp out from bot-16kb |
| 132 | input [18:0] sab_hi1_bc_l; // Senseamp out from bot-16kb |
| 133 | input [19:0] ldin0lo_b; |
| 134 | input [19:0] ldin0hi_b; |
| 135 | input [18:0] ldin1lo_b; |
| 136 | input [18:0] ldin1hi_b; |
| 137 | //input bnken_lat; // Address latch enable (1.5cycle) |
| 138 | output [19:0] ldout0lo_b; |
| 139 | output [19:0] ldout0hi_b; |
| 140 | output [18:0] ldout1lo_b; |
| 141 | output [18:0] ldout1hi_b; |
| 142 | |
| 143 | |
| 144 | input [9:0] red_d_in_00; |
| 145 | output [9:0] red_d_out_00; |
| 146 | input [2:0] fuse_l2d_rid_00; |
| 147 | input fuse_l2d_wren_00; |
| 148 | input fuse_l2d_reset_00_l; |
| 149 | input sel_quad_00; |
| 150 | |
| 151 | input [9:0] red_d_in_01; |
| 152 | output [9:0] red_d_out_01; |
| 153 | input [2:0] fuse_l2d_rid_01; |
| 154 | input fuse_l2d_wren_01; |
| 155 | input fuse_l2d_reset_01_l; |
| 156 | input sel_quad_01; |
| 157 | |
| 158 | output [9:0] red_addr_top; |
| 159 | output [9:0] red_addr_bot; |
| 160 | // forwarded |
| 161 | input [9:0] red_top_d_00; |
| 162 | input [9:0] red_top_d_01; |
| 163 | |
| 164 | output [77:0] cred; |
| 165 | //output fuse_l2d_reset_00_l_buf; |
| 166 | //output fuse_l2d_reset_01_l_buf; |
| 167 | |
| 168 | reg [7:0] waysel_top_c4; |
| 169 | reg [7:0] waysel_bot_c4; |
| 170 | reg [8:0] set_top_c3b; |
| 171 | reg [8:0] set_bot_c3b; |
| 172 | reg writeen_top_c3b; |
| 173 | reg writeen_bot_c3b; |
| 174 | reg [3:0] worden_top_c3b; |
| 175 | reg [3:0] worden_bot_c3b; |
| 176 | reg coloff_top_c3b_l; |
| 177 | reg coloff_bot_c3b_l; |
| 178 | reg [7:0] waysel_top_c3b; |
| 179 | reg [7:0] waysel_bot_c3b; |
| 180 | //always@(posedge l2clk) |
| 181 | always@(negedge l2clk) |
| 182 | begin |
| 183 | coloff_top_c3b_l <= ~coloff_c3; |
| 184 | coloff_bot_c3b_l <= ~coloff_c3; |
| 185 | worden_top_c3b[3:0] <= worden_c3[3:0]; |
| 186 | worden_bot_c3b[3:0] <= worden_c3[3:0]; |
| 187 | writeen_top_c3b <= ~rd_wr_c3; |
| 188 | writeen_bot_c3b <= ~rd_wr_c3; |
| 189 | end |
| 190 | |
| 191 | //always@(negedge l2clk) |
| 192 | //always@(l2clk or bnken_lat) |
| 193 | always@(l2clk or coloff_c4_l) |
| 194 | begin |
| 195 | // if(~bnken_lat) |
| 196 | if(~l2clk & coloff_c4_l) |
| 197 | begin |
| 198 | waysel_top_c3b[7:0] <= waysel_c3[7:0]; |
| 199 | waysel_bot_c3b[7:0] <= waysel_c3[7:0]; |
| 200 | set_bot_c3b[8:0] <= set_c3[8:0]; |
| 201 | set_top_c3b[8:0] <= {~set_c3[8],set_c3[7:0]}; |
| 202 | |
| 203 | end |
| 204 | end |
| 205 | |
| 206 | always@(posedge l2clk ) |
| 207 | begin |
| 208 | waysel_top_c4[7:0] <= waysel_top_c3b[7:0]; |
| 209 | waysel_bot_c4[7:0] <= waysel_bot_c3b[7:0]; |
| 210 | end |
| 211 | //assign readen_top_c5 = readen_c5; |
| 212 | //assign readen_bot_c5 = readen_c5; |
| 213 | //assign coloff_top_c5 = coloff_c5[1:0]; |
| 214 | //assign coloff_bot_c5 = coloff_c5[1:0]; |
| 215 | //assign coloff_top_c4_l = coloff_c4_l; |
| 216 | //assign coloff_bot_c4_l = coloff_c4_l; |
| 217 | |
| 218 | |
| 219 | wire [19:0] sat_lo0_bc; |
| 220 | wire [19:0] sab_lo0_bc; |
| 221 | wire [19:0] sat_hi0_bc; |
| 222 | wire [19:0] sab_hi0_bc; |
| 223 | |
| 224 | wire [18:0] sat_lo1_bc; |
| 225 | wire [18:0] sab_lo1_bc; |
| 226 | wire [18:0] sat_hi1_bc; |
| 227 | wire [18:0] sab_hi1_bc; |
| 228 | |
| 229 | |
| 230 | //always@(posedge l1clk) |
| 231 | //begin |
| 232 | assign sat_lo0_bc[19:0] = ~sat_lo0_bc_l[19:0]; |
| 233 | assign sab_lo0_bc[19:0] = ~sab_lo0_bc_l[19:0]; |
| 234 | assign sat_hi0_bc[19:0] = ~sat_hi0_bc_l[19:0]; |
| 235 | assign sab_hi0_bc[19:0] = ~sab_hi0_bc_l[19:0]; |
| 236 | |
| 237 | assign sat_lo1_bc[18:0] = ~sat_lo1_bc_l[18:0]; |
| 238 | assign sab_lo1_bc[18:0] = ~sab_lo1_bc_l[18:0]; |
| 239 | assign sat_hi1_bc[18:0] = ~sat_hi1_bc_l[18:0]; |
| 240 | assign sab_hi1_bc[18:0] = ~sab_hi1_bc_l[18:0]; |
| 241 | //end |
| 242 | |
| 243 | |
| 244 | |
| 245 | n2_l2d_dmux78_cust_or_macro__ports_3__width_20 or_ldout0lo_b |
| 246 | ( |
| 247 | .dout (ldout0lo_b[19:0]), |
| 248 | .din0 (sat_lo0_bc[19:0]), |
| 249 | .din1 (sab_lo0_bc[19:0]), |
| 250 | .din2 (ldin0lo_b[19:0]) |
| 251 | ); |
| 252 | |
| 253 | n2_l2d_dmux78_cust_or_macro__ports_3__width_20 or_ldout0hi_b |
| 254 | ( |
| 255 | .dout (ldout0hi_b[19:0]), |
| 256 | .din0 (sat_hi0_bc[19:0]), |
| 257 | .din1 (sab_hi0_bc[19:0]), |
| 258 | .din2 (ldin0hi_b[19:0]) |
| 259 | ); |
| 260 | |
| 261 | n2_l2d_dmux78_cust_or_macro__ports_3__width_19 or_ldout1lo_b |
| 262 | ( |
| 263 | .dout (ldout1lo_b[18:0]), |
| 264 | .din0 (sat_lo1_bc[18:0]), |
| 265 | .din1 (sab_lo1_bc[18:0]), |
| 266 | .din2 (ldin1lo_b[18:0]) |
| 267 | ); |
| 268 | |
| 269 | |
| 270 | n2_l2d_dmux78_cust_or_macro__ports_3__width_19 or_ldout1hi_b |
| 271 | ( |
| 272 | .dout (ldout1hi_b[18:0]), |
| 273 | .din0 (sat_hi1_bc[18:0]), |
| 274 | .din1 (sab_hi1_bc[18:0]), |
| 275 | .din2 (ldin1hi_b[18:0]) |
| 276 | ); |
| 277 | |
| 278 | |
| 279 | cl_sc1_l1hdr_12x clk_hdr ( |
| 280 | .l2clk (l2clk), |
| 281 | .se (se), |
| 282 | .pce (tcu_pce), |
| 283 | .pce_ov (tcu_pce_ov), |
| 284 | .stop (tcu_clk_stop), |
| 285 | .l1clk (l1clk) |
| 286 | ); |
| 287 | |
| 288 | |
| 289 | // Redudant row modelling |
| 290 | |
| 291 | |
| 292 | |
| 293 | reg [9:0] red_odd_0; |
| 294 | reg [9:0] red_odd_1; |
| 295 | reg [9:0] red_even_0; |
| 296 | reg [9:0] red_even_1; |
| 297 | reg [7:0] red_col_0; |
| 298 | reg [7:0] red_col_1; |
| 299 | //reg [9:0] red_d_out_00; |
| 300 | //reg [9:0] red_d_out_01; |
| 301 | |
| 302 | wire red_reg_clk_even_0; |
| 303 | wire red_reg_clk_even_1; |
| 304 | wire red_reg_clk_odd_0; |
| 305 | wire red_reg_clk_odd_1; |
| 306 | wire red_reg_clk_col_0; |
| 307 | wire red_reg_clk_col_1; |
| 308 | wire [9:0] red_data_00; |
| 309 | wire [9:0] red_data_01; |
| 310 | |
| 311 | // Initialize the register. |
| 312 | initial begin |
| 313 | |
| 314 | red_odd_0[9:0] = 10'b0; |
| 315 | red_odd_1[9:0] = 10'b0; |
| 316 | red_even_0[9:0]= 10'b0; |
| 317 | red_even_1[9:0]= 10'b0; |
| 318 | red_col_0[7:0] = 8'b0; |
| 319 | red_col_1[7:0] = 8'b0; |
| 320 | end |
| 321 | |
| 322 | assign red_reg_clk_even_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b000) & sel_quad_00) | ~fuse_l2d_reset_00_l); |
| 323 | assign red_reg_clk_even_1 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b010) & sel_quad_00) | ~fuse_l2d_reset_00_l); |
| 324 | assign red_reg_clk_col_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b100) & sel_quad_00) | ~fuse_l2d_reset_00_l); |
| 325 | |
| 326 | assign red_reg_clk_odd_0 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b001) & sel_quad_01) | ~fuse_l2d_reset_01_l); |
| 327 | assign red_reg_clk_odd_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b011) & sel_quad_01) | ~fuse_l2d_reset_01_l); |
| 328 | assign red_reg_clk_col_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b101) & sel_quad_01) | ~fuse_l2d_reset_01_l); |
| 329 | |
| 330 | assign red_data_00[9:0] = red_d_in_00[9:0] & {10{fuse_l2d_reset_00_l}}; |
| 331 | assign red_data_01[9:0] = red_d_in_01[9:0] & {10{fuse_l2d_reset_01_l}}; |
| 332 | |
| 333 | always @(red_reg_clk_even_0 or red_reg_clk_even_1 or red_reg_clk_col_0 or red_reg_clk_odd_0 or red_reg_clk_odd_1 or red_reg_clk_col_1 or red_d_in_00 or red_d_in_01) begin |
| 334 | if (~red_reg_clk_even_0) begin |
| 335 | red_even_0[9:0] <= red_data_00[9:0]; |
| 336 | end |
| 337 | |
| 338 | if (~red_reg_clk_even_1) begin |
| 339 | red_even_1[9:0] <= red_data_00[9:0]; |
| 340 | end |
| 341 | |
| 342 | if (~red_reg_clk_col_0) begin |
| 343 | red_col_0[7:0] <= {red_data_00[9:8],red_data_00[5:0]}; |
| 344 | end |
| 345 | |
| 346 | if (~red_reg_clk_odd_0) begin |
| 347 | red_odd_0[9:0] <= red_data_01[9:0]; |
| 348 | end |
| 349 | |
| 350 | if (~red_reg_clk_odd_1) begin |
| 351 | red_odd_1[9:0] <= red_data_01[9:0]; |
| 352 | end |
| 353 | |
| 354 | if (~red_reg_clk_col_1) begin |
| 355 | red_col_1[7:0] <= {red_data_01[9:8],red_data_01[5:0]}; |
| 356 | end |
| 357 | end |
| 358 | |
| 359 | |
| 360 | // 00 = bot and 01 = top |
| 361 | |
| 362 | //always@(fuse_l2d_wren_00 or fuse_l2d_wren_01 or fuse_l2d_rid_01 or fuse_l2d_rid_00 |
| 363 | // or red_d_in_00 or red_d_in_01 or sel_quad_00 or sel_quad_01) |
| 364 | //begin |
| 365 | // if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_bot_c3b[8] & (fuse_l2d_rid_00[2:1]==2'b00) & sel_quad_00) |
| 366 | // red_even_0 <= red_d_in_00; |
| 367 | // else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_00) |
| 368 | // red_even_1 <= red_d_in_00; |
| 369 | // else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_00) |
| 370 | // red_col_0 <= red_d_in_00[7:0]; |
| 371 | // |
| 372 | // if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b00) & sel_quad_01) |
| 373 | // red_odd_0 <= red_d_in_01; |
| 374 | // else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_bot_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_01) |
| 375 | // red_odd_1 <= red_d_in_01; |
| 376 | // else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_01) |
| 377 | // red_col_1 <= red_d_in_01[7:0]; |
| 378 | //end |
| 379 | // |
| 380 | |
| 381 | //assign red_addr_top = set_top_c3b[0] ? red_odd_0 : red_even_0; |
| 382 | //assign red_addr_bot = set_top_c3b[0] ? red_odd_1 : red_even_1; |
| 383 | assign red_addr_top = set_top_c3b[0] ? red_odd_1 : red_even_1; |
| 384 | assign red_addr_bot = set_top_c3b[0] ? red_odd_0 : red_even_0; |
| 385 | |
| 386 | assign red_d_out_00[7:0] = (red_even_0[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b000}}) | |
| 387 | (red_even_1[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b010}}) | |
| 388 | ({2'b0,(red_col_0[5:0] & {6{fuse_l2d_rid_00[2:0]==3'b100}})}) | |
| 389 | (red_top_d_00[7:0] & {8{~sel_quad_00}}); |
| 390 | |
| 391 | assign red_d_out_00[9:8] = (red_even_0[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b000}}) | |
| 392 | (red_even_1[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b010}}) | |
| 393 | (red_col_0[7:6] & {2{fuse_l2d_rid_00[2:0]==3'b100}}) | |
| 394 | (red_top_d_00[9:8] & {2{~sel_quad_00}}); |
| 395 | |
| 396 | |
| 397 | |
| 398 | |
| 399 | assign red_d_out_01[7:0] = (red_odd_0[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b001}}) | |
| 400 | (red_odd_1[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b011}}) | |
| 401 | ({2'b0,(red_col_1[5:0] & {6{fuse_l2d_rid_01[2:0]==3'b101}})}) | |
| 402 | (red_top_d_01[7:0] & {8{~sel_quad_01}}); |
| 403 | |
| 404 | assign red_d_out_01[9:8] = (red_odd_0[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b001}}) | |
| 405 | (red_odd_1[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b011}}) | |
| 406 | (red_col_1[7:6] & {2{fuse_l2d_rid_01[2:0]==3'b101}}) | |
| 407 | (red_top_d_01[9:8] & {2{~sel_quad_01}}); |
| 408 | |
| 409 | |
| 410 | |
| 411 | //always@(fuse_l2d_rid_00) |
| 412 | //begin |
| 413 | //case(fuse_l2d_rid_00) |
| 414 | //3'b000 : begin |
| 415 | // red_d_out_00 = red_even_0; |
| 416 | // red_d_out_01 = 10'b0; |
| 417 | // end |
| 418 | //3'b010 : begin |
| 419 | // red_d_out_00 = red_even_1; |
| 420 | // red_d_out_01 = 10'b0; |
| 421 | // end |
| 422 | //3'b100 : begin |
| 423 | // red_d_out_00 = {2'b0,red_col_0}; |
| 424 | // red_d_out_01 = 10'b0; |
| 425 | // end |
| 426 | // |
| 427 | //3'b001 : begin |
| 428 | // red_d_out_01 = red_odd_0; |
| 429 | // red_d_out_00 = 10'b0; |
| 430 | // end |
| 431 | //3'b011 : begin |
| 432 | // red_d_out_01 = red_odd_1; |
| 433 | // red_d_out_00 = 10'b0; |
| 434 | // end |
| 435 | //3'b101 : begin |
| 436 | // red_d_out_01 = {2'b0,red_col_1}; |
| 437 | // red_d_out_00 = 10'b0; |
| 438 | // end |
| 439 | // |
| 440 | //default : begin |
| 441 | // red_d_out_00 = red_top_d_00; |
| 442 | // red_d_out_01 = red_top_d_01; |
| 443 | // end |
| 444 | //endcase |
| 445 | //end |
| 446 | |
| 447 | // Col redudancy |
| 448 | |
| 449 | //reg [7:0] red_col_0; |
| 450 | //reg [7:0] red_col_1; |
| 451 | |
| 452 | reg [38:0] cred0; |
| 453 | reg [38:0] cred1; |
| 454 | |
| 455 | // Initialize cred0, cred1 |
| 456 | initial begin |
| 457 | cred0[38:0] = 39'b0; |
| 458 | cred1[38:0] = 39'b0; |
| 459 | end |
| 460 | |
| 461 | always@(red_col_0) |
| 462 | if(red_col_0[7] & red_col_0[6] & ~red_col_0[5]) |
| 463 | case(red_col_0) |
| 464 | 8'b11_0_00000 : cred0[18:0] = 19'b111_1111_1111_1111_1111; //0 |
| 465 | 8'b11_0_00001 : cred0[18:0] = 19'b111_1111_1111_1111_1110; //1 |
| 466 | 8'b11_0_00010 : cred0[18:0] = 19'b111_1111_1111_1111_1100; //2 |
| 467 | 8'b11_0_00011 : cred0[18:0] = 19'b111_1111_1111_1111_1000; //3 |
| 468 | 8'b11_0_00100 : cred0[18:0] = 19'b111_1111_1111_1111_0000; //4 |
| 469 | 8'b11_0_00101 : cred0[18:0] = 19'b111_1111_1111_1110_0000; //5 |
| 470 | 8'b11_0_00110 : cred0[18:0] = 19'b111_1111_1111_1100_0000; //6 |
| 471 | 8'b11_0_00111 : cred0[18:0] = 19'b111_1111_1111_1000_0000; //7 |
| 472 | 8'b11_0_01000 : cred0[18:0] = 19'b111_1111_1111_0000_0000; //8 |
| 473 | 8'b11_0_01001 : cred0[18:0] = 19'b111_1111_1110_0000_0000; //9 |
| 474 | 8'b11_0_01010 : cred0[18:0] = 19'b111_1111_1100_0000_0000; //10 |
| 475 | 8'b11_0_01011 : cred0[18:0] = 19'b111_1111_1000_0000_0000; //11 |
| 476 | 8'b11_0_01100 : cred0[18:0] = 19'b111_1111_0000_0000_0000; //12 |
| 477 | 8'b11_0_01101 : cred0[18:0] = 19'b111_1110_0000_0000_0000; //13 |
| 478 | 8'b11_0_01110 : cred0[18:0] = 19'b111_1100_0000_0000_0000; //14 |
| 479 | 8'b11_0_01111 : cred0[18:0] = 19'b111_1000_0000_0000_0000; //15 |
| 480 | 8'b11_0_10000 : cred0[18:0] = 19'b111_0000_0000_0000_0000; //16 |
| 481 | 8'b11_0_10001 : cred0[18:0] = 19'b110_0000_0000_0000_0000; //17 |
| 482 | 8'b11_0_10010 : cred0[18:0] = 19'b100_0000_0000_0000_0000; //18 |
| 483 | default : cred0[18:0] = 19'b0; |
| 484 | endcase |
| 485 | else cred0[18:0] = 19'b0; |
| 486 | |
| 487 | always@(red_col_0) |
| 488 | if(red_col_0[7] & red_col_0[6] & red_col_0[5]) |
| 489 | case(red_col_0) |
| 490 | 8'b11_1_00000 : cred0[38:19] = 20'b1111_1111_1111_1111_1111;//0 |
| 491 | 8'b11_1_00001 : cred0[38:19] = 20'b0111_1111_1111_1111_1111;//1 |
| 492 | 8'b11_1_00010 : cred0[38:19] = 20'b0011_1111_1111_1111_1111;//2 |
| 493 | 8'b11_1_00011 : cred0[38:19] = 20'b0001_1111_1111_1111_1111;//3 |
| 494 | 8'b11_1_00100 : cred0[38:19] = 20'b0000_1111_1111_1111_1111;//4 |
| 495 | 8'b11_1_00101 : cred0[38:19] = 20'b0000_0111_1111_1111_1111;//5 |
| 496 | 8'b11_1_00110 : cred0[38:19] = 20'b0000_0011_1111_1111_1111;//6 |
| 497 | 8'b11_1_00111 : cred0[38:19] = 20'b0000_0001_1111_1111_1111;//7 |
| 498 | 8'b11_1_01000 : cred0[38:19] = 20'b0000_0000_1111_1111_1111;//8 |
| 499 | 8'b11_1_01001 : cred0[38:19] = 20'b0000_0000_0111_1111_1111;//9 |
| 500 | 8'b11_1_01010 : cred0[38:19] = 20'b0000_0000_0011_1111_1111;//10 |
| 501 | 8'b11_1_01011 : cred0[38:19] = 20'b0000_0000_0001_1111_1111;//11 |
| 502 | 8'b11_1_01100 : cred0[38:19] = 20'b0000_0000_0000_1111_1111;//12 |
| 503 | 8'b11_1_01101 : cred0[38:19] = 20'b0000_0000_0000_0111_1111;//13 |
| 504 | 8'b11_1_01110 : cred0[38:19] = 20'b0000_0000_0000_0011_1111;//14 |
| 505 | 8'b11_1_01111 : cred0[38:19] = 20'b0000_0000_0000_0001_1111;//15 |
| 506 | 8'b11_1_10000 : cred0[38:19] = 20'b0000_0000_0000_0000_1111;//16 |
| 507 | 8'b11_1_10001 : cred0[38:19] = 20'b0000_0000_0000_0000_0111;//17 |
| 508 | 8'b11_1_10010 : cred0[38:19] = 20'b0000_0000_0000_0000_0011;//18 |
| 509 | 8'b11_1_10011 : cred0[38:19] = 20'b0000_0000_0000_0000_0001;//19 |
| 510 | default : cred0[38:19] = 20'b0; |
| 511 | endcase |
| 512 | else cred0[38:19] = 20'b0; |
| 513 | |
| 514 | always@(red_col_1) |
| 515 | if(red_col_1[7] & red_col_1[6] & red_col_1[5]) |
| 516 | case(red_col_1) |
| 517 | 8'b11_1_00000 : cred1[19:0] = 20'b1111_1111_1111_1111_1111; //0 |
| 518 | 8'b11_1_00001 : cred1[19:0] = 20'b1111_1111_1111_1111_1110; //1 |
| 519 | 8'b11_1_00010 : cred1[19:0] = 20'b1111_1111_1111_1111_1100; //2 |
| 520 | 8'b11_1_00011 : cred1[19:0] = 20'b1111_1111_1111_1111_1000; //3 |
| 521 | 8'b11_1_00100 : cred1[19:0] = 20'b1111_1111_1111_1111_0000; //4 |
| 522 | 8'b11_1_00101 : cred1[19:0] = 20'b1111_1111_1111_1110_0000; //5 |
| 523 | 8'b11_1_00110 : cred1[19:0] = 20'b1111_1111_1111_1100_0000; //6 |
| 524 | 8'b11_1_00111 : cred1[19:0] = 20'b1111_1111_1111_1000_0000; //7 |
| 525 | 8'b11_1_01000 : cred1[19:0] = 20'b1111_1111_1111_0000_0000; //8 |
| 526 | 8'b11_1_01001 : cred1[19:0] = 20'b1111_1111_1110_0000_0000; //9 |
| 527 | 8'b11_1_01010 : cred1[19:0] = 20'b1111_1111_1100_0000_0000; //10 |
| 528 | 8'b11_1_01011 : cred1[19:0] = 20'b1111_1111_1000_0000_0000; //11 |
| 529 | 8'b11_1_01100 : cred1[19:0] = 20'b1111_1111_0000_0000_0000; //12 |
| 530 | 8'b11_1_01101 : cred1[19:0] = 20'b1111_1110_0000_0000_0000; //13 |
| 531 | 8'b11_1_01110 : cred1[19:0] = 20'b1111_1100_0000_0000_0000; //14 |
| 532 | 8'b11_1_01111 : cred1[19:0] = 20'b1111_1000_0000_0000_0000; //15 |
| 533 | 8'b11_1_10000 : cred1[19:0] = 20'b1111_0000_0000_0000_0000; //16 |
| 534 | 8'b11_1_10001 : cred1[19:0] = 20'b1110_0000_0000_0000_0000; //17 |
| 535 | 8'b11_1_10010 : cred1[19:0] = 20'b1100_0000_0000_0000_0000; //18 |
| 536 | 8'b11_1_10011 : cred1[19:0] = 20'b1000_0000_0000_0000_0000; //19 |
| 537 | default : cred1[19:0] = 20'b0; |
| 538 | endcase |
| 539 | else cred1[19:0] = 20'b0; |
| 540 | |
| 541 | always@(red_col_1) |
| 542 | if(red_col_1[7] & red_col_1[6] & ~red_col_1[5]) |
| 543 | case(red_col_1) |
| 544 | 8'b11_0_00000 : cred1[38:20] = 19'b111_1111_1111_1111_1111;//0 |
| 545 | 8'b11_0_00001 : cred1[38:20] = 19'b011_1111_1111_1111_1111;//1 |
| 546 | 8'b11_0_00010 : cred1[38:20] = 19'b001_1111_1111_1111_1111;//2 |
| 547 | 8'b11_0_00011 : cred1[38:20] = 19'b000_1111_1111_1111_1111;//3 |
| 548 | 8'b11_0_00100 : cred1[38:20] = 19'b000_0111_1111_1111_1111;//4 |
| 549 | 8'b11_0_00101 : cred1[38:20] = 19'b000_0011_1111_1111_1111;//5 |
| 550 | 8'b11_0_00110 : cred1[38:20] = 19'b000_0001_1111_1111_1111;//6 |
| 551 | 8'b11_0_00111 : cred1[38:20] = 19'b000_0000_1111_1111_1111;//7 |
| 552 | 8'b11_0_01000 : cred1[38:20] = 19'b000_0000_0111_1111_1111;//8 |
| 553 | 8'b11_0_01001 : cred1[38:20] = 19'b000_0000_0011_1111_1111;//9 |
| 554 | 8'b11_0_01010 : cred1[38:20] = 19'b000_0000_0001_1111_1111;//10 |
| 555 | 8'b11_0_01011 : cred1[38:20] = 19'b000_0000_0000_1111_1111;//11 |
| 556 | 8'b11_0_01100 : cred1[38:20] = 19'b000_0000_0000_0111_1111;//12 |
| 557 | 8'b11_0_01101 : cred1[38:20] = 19'b000_0000_0000_0011_1111;//13 |
| 558 | 8'b11_0_01110 : cred1[38:20] = 19'b000_0000_0000_0001_1111;//14 |
| 559 | 8'b11_0_01111 : cred1[38:20] = 19'b000_0000_0000_0000_1111;//15 |
| 560 | 8'b11_0_10000 : cred1[38:20] = 19'b000_0000_0000_0000_0111;//16 |
| 561 | 8'b11_0_10001 : cred1[38:20] = 19'b000_0000_0000_0000_0011;//17 |
| 562 | 8'b11_0_10010 : cred1[38:20] = 19'b000_0000_0000_0000_0001;//18 |
| 563 | default : cred1[38:20] = 19'b0; |
| 564 | endcase |
| 565 | else cred1[38:20] = 19'b0; |
| 566 | |
| 567 | assign cred[77:0] = {cred1[38:0], cred0[38:0]}; |
| 568 | //assign cred[77:0] = 78'b0; |
| 569 | |
| 570 | |
| 571 | //assign fuse_l2d_reset_00_buf = fuse_l2d_reset_00; |
| 572 | //assign fuse_l2d_reset_01_buf = fuse_l2d_reset_01; |
| 573 | |
| 574 | |
| 575 | |
| 576 | |
| 577 | endmodule |
| 578 | |
| 579 | |
| 580 | // |
| 581 | // or macro for ports = 2,3 |
| 582 | // |
| 583 | // |
| 584 | |
| 585 | |
| 586 | |
| 587 | |
| 588 | |
| 589 | module n2_l2d_dmux78_cust_or_macro__ports_3__width_20 ( |
| 590 | din0, |
| 591 | din1, |
| 592 | din2, |
| 593 | dout); |
| 594 | input [19:0] din0; |
| 595 | input [19:0] din1; |
| 596 | input [19:0] din2; |
| 597 | output [19:0] dout; |
| 598 | |
| 599 | |
| 600 | |
| 601 | |
| 602 | |
| 603 | |
| 604 | or3 #(20) d0_0 ( |
| 605 | .in0(din0[19:0]), |
| 606 | .in1(din1[19:0]), |
| 607 | .in2(din2[19:0]), |
| 608 | .out(dout[19:0]) |
| 609 | ); |
| 610 | |
| 611 | |
| 612 | |
| 613 | |
| 614 | |
| 615 | |
| 616 | |
| 617 | |
| 618 | |
| 619 | endmodule |
| 620 | |
| 621 | |
| 622 | |
| 623 | |
| 624 | |
| 625 | // |
| 626 | // or macro for ports = 2,3 |
| 627 | // |
| 628 | // |
| 629 | |
| 630 | |
| 631 | |
| 632 | |
| 633 | |
| 634 | module n2_l2d_dmux78_cust_or_macro__ports_3__width_19 ( |
| 635 | din0, |
| 636 | din1, |
| 637 | din2, |
| 638 | dout); |
| 639 | input [18:0] din0; |
| 640 | input [18:0] din1; |
| 641 | input [18:0] din2; |
| 642 | output [18:0] dout; |
| 643 | |
| 644 | |
| 645 | |
| 646 | |
| 647 | |
| 648 | |
| 649 | or3 #(19) d0_0 ( |
| 650 | .in0(din0[18:0]), |
| 651 | .in1(din1[18:0]), |
| 652 | .in2(din2[18:0]), |
| 653 | .out(dout[18:0]) |
| 654 | ); |
| 655 | |
| 656 | |
| 657 | |
| 658 | |
| 659 | |
| 660 | |
| 661 | |
| 662 | |
| 663 | |
| 664 | endmodule |
| 665 | |
| 666 | |
| 667 | |
| 668 | |