| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_adv_ncupiowr_32bit.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define ENABLE_PCIE_LINK_TRAINING |
| 39 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ |
| 40 | #define MAIN_PAGE_HV_ALSO |
| 41 | |
| 42 | #include "err_defines.h" |
| 43 | #include "hboot.s" |
| 44 | #include "peu_defines.h" |
| 45 | |
| 46 | !#define IO_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) |
| 47 | #define IO_WR_ADDR mpeval((N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) | IO_ACCESS_PA) |
| 48 | |
| 49 | /************************************************************************ |
| 50 | Test case code start |
| 51 | ************************************************************************/ |
| 52 | .text |
| 53 | .global main |
| 54 | |
| 55 | main: |
| 56 | ta T_CHANGE_HPRIV |
| 57 | nop |
| 58 | |
| 59 | clear_esr_first: |
| 60 | setx SOC_ESR_REG, %l7, %i0 |
| 61 | stx %g0, [%i0] |
| 62 | |
| 63 | first_st_ld: |
| 64 | setx IO_WR_ADDR, %g1, %g2 |
| 65 | setx 0x55555555, %g1, %l0 |
| 66 | st %l0, [%g2] |
| 67 | ld [%g2], %i5 |
| 68 | |
| 69 | set_ejr: |
| 70 | set 0x1, %i1 |
| 71 | sllx %i1, ERR_FIELD, %i2 |
| 72 | setx SOC_EJR_REG, %l7, %i3 |
| 73 | stx %i2, [%i3] |
| 74 | membar 0x40 |
| 75 | |
| 76 | ! select a CFG address in PCI address range and transmit the command to NCU |
| 77 | setx IO_WR_ADDR, %g1, %g2 |
| 78 | setx 0xaaaaaaaa, %g1, %l0 |
| 79 | stw %l0, [%g2] |
| 80 | |
| 81 | setx 0x40, %l1, %g4 |
| 82 | delay_loop: |
| 83 | nop |
| 84 | nop |
| 85 | nop |
| 86 | nop |
| 87 | dec %g4 |
| 88 | brnz %g4, delay_loop |
| 89 | nop |
| 90 | nop |
| 91 | |
| 92 | check_esr: |
| 93 | setx SOC_ESR_REG, %l7, %i0 |
| 94 | ldx [%i0], %i1 |
| 95 | nop |
| 96 | |
| 97 | setx 0x8000000000000000, %l7, %o3 !valid bit |
| 98 | set 0x1, %i2 |
| 99 | sllx %i2, ERR_FIELD, %i3 |
| 100 | or %i3, %o3, %i4 |
| 101 | sub %i1, %i4, %i5 |
| 102 | brnz %i5, test_failed |
| 103 | nop |
| 104 | |
| 105 | clear_esr_ejr: |
| 106 | setx SOC_EJR_REG, %l7, %i0 |
| 107 | stx %g0, [%i0] |
| 108 | |
| 109 | setx SOC_ESR_REG, %l7, %i0 |
| 110 | stx %g0, [%i0] |
| 111 | |
| 112 | read_again: |
| 113 | setx IO_WR_ADDR, %g1, %g2 |
| 114 | ld [%g2], %i5 |
| 115 | |
| 116 | setx 0x10, %l1, %g4 |
| 117 | delay_loop_2: |
| 118 | nop |
| 119 | nop |
| 120 | nop |
| 121 | nop |
| 122 | dec %g4 |
| 123 | brnz %g4, delay_loop_2 |
| 124 | nop |
| 125 | nop |
| 126 | |
| 127 | check_esr_again: |
| 128 | setx SOC_ESR_REG, %l7, %i0 |
| 129 | ld [%i0], %i1 |
| 130 | nop |
| 131 | |
| 132 | test_passed: |
| 133 | EXIT_GOOD |
| 134 | |
| 135 | test_failed: |
| 136 | EXIT_BAD |
| 137 | |
| 138 | |
| 139 | /************************************************************************ |
| 140 | Test case data start |
| 141 | ************************************************************************/ |
| 142 | |
| 143 | SECTION .DATA DATA_VA=IO_WR_ADDR |
| 144 | attr_data { |
| 145 | Name = .DATA, |
| 146 | hypervisor, |
| 147 | compressimage |
| 148 | } |
| 149 | |
| 150 | .data |
| 151 | .global PCIAddr9 |
| 152 | |
| 153 | data0: .word 0xccccdddd |
| 154 | data1: .word 0xeeeeffff |
| 155 | /************************************************************************/ |