| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_L2_LDWC_cecc.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | #define L2_ENTRY_PA 0x517590000 |
| 41 | #define TEST_DATA 0x555555555555555 |
| 42 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 43 | |
| 44 | |
| 45 | #include "hboot.s" |
| 46 | #include "asi_s.h" |
| 47 | #include "err_defines.h" |
| 48 | |
| 49 | .text |
| 50 | .global main |
| 51 | |
| 52 | |
| 53 | main: |
| 54 | |
| 55 | |
| 56 | ! Boot code does not provide TLB translation for IO address space |
| 57 | ta T_CHANGE_HPRIV |
| 58 | |
| 59 | setx L2_ES_W1C_VALUE, %l0, %g4 |
| 60 | |
| 61 | ! Now access L2 control and status registers |
| 62 | disable_l1: |
| 63 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 64 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 65 | andn %l0, 0x3, %l0 |
| 66 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 67 | |
| 68 | |
| 69 | ! Write 1 to clear L2 Error status registers |
| 70 | |
| 71 | clear_l2_ESR: |
| 72 | setx L2ES_PA0, %l3, %l4 |
| 73 | stx %g4, [%l4] |
| 74 | nop |
| 75 | |
| 76 | |
| 77 | set_L2_Directly_Mapped_Mode: |
| 78 | setx L2CS_PA0, %l6, %g1 |
| 79 | mov 0x2, %l0 |
| 80 | stx %l0, [%g1] |
| 81 | |
| 82 | |
| 83 | store_to_L2_way0: |
| 84 | setx TEST_DATA, %l0, %g5 |
| 85 | setx 0x202000aa00, %l0, %g1 |
| 86 | stx %g5, [%g1] |
| 87 | stx %g5, [%g1+8] |
| 88 | membar #Sync |
| 89 | |
| 90 | |
| 91 | generate_VD_addr: |
| 92 | ! Generate L2 VD Diag read address |
| 93 | ! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [7:6] bank, [2:0] = 0 |
| 94 | setx 0x3ffc0, %l0, %l2 ! Mask for extracting [17:6] |
| 95 | and %g1, %l2, %l7 |
| 96 | |
| 97 | mov 0xb6, %l0 |
| 98 | sllx %l0, 32, %l0 ! Bits [39:32] |
| 99 | or %l7, %l0, %l7 |
| 100 | |
| 101 | mov 0x1, %l0 |
| 102 | sllx %l0, 22, %l0 ! Bit [22] |
| 103 | or %l7, %l0, %l7 |
| 104 | |
| 105 | read_l2_VD_diag: |
| 106 | ! ldx [%l7], %l6 |
| 107 | |
| 108 | ! Now find out which way it is being stored |
| 109 | setx 0xffff, %l0, %l2 ! Mask for [16:0] |
| 110 | and %l6, %l2, %l6 ! Valid bits at [31:16] |
| 111 | |
| 112 | clr %g2 ! %g2 will store the "way" |
| 113 | |
| 114 | ! Direct comparison - avoid loops to save run time |
| 115 | ! cmp %l6, 0x1 |
| 116 | ! bne test_fail |
| 117 | ! nop |
| 118 | |
| 119 | way_found: |
| 120 | ! Read L2 Data Diag - %g2 has the "way" |
| 121 | ! Addressing: [39:32] See PRM, [22] odd/even word, [21:18] way, [17:8] set, [7:6] bank, [5:3] D-word, [2:0] = 0 |
| 122 | setx 0x3fff8, %l0, %l2 ! Mask for extracting [17:3] |
| 123 | and %g1, %l2, %g5 |
| 124 | |
| 125 | sllx %g2, 18, %l0 ! Position Way |
| 126 | or %g5, %l0, %g5 |
| 127 | |
| 128 | mov 0xa3, %l0 |
| 129 | sllx %l0, 32, %l0 ! Bits [39:32] |
| 130 | or %g5, %l0, %g5 ! %g5 has L2 Data Diag addressing |
| 131 | |
| 132 | |
| 133 | read_l2_data_diag: |
| 134 | ldx [%g5], %g6 |
| 135 | |
| 136 | ! Flip one bit from the data field |
| 137 | xor %g6, 0x80, %g6 ! save on %g6 for future reference |
| 138 | write_back_with_error: |
| 139 | stx %g6, [%g5] |
| 140 | |
| 141 | ! Now set allocate bits for all other 15 ways (to ensure a write-back later) |
| 142 | set_allocate: |
| 143 | mov 0x1, %l0 |
| 144 | sllx %l0, 22, %l1 ! L2_VD and L2_UA addressing differ on bit 22 |
| 145 | xor %l7, %l1, %l7 ! change %l7 from L2_VD to L2_UA address |
| 146 | |
| 147 | read_l2_UA_diag: |
| 148 | ! ldx [%l7], %l6 |
| 149 | |
| 150 | sllx %l0, %g2, %l1 ! Shift "way" into its bit position |
| 151 | not %l1 |
| 152 | setx 0xffff,%l5, %g2 |
| 153 | and %l1, %g2 , %l1 ! Allocate bits on [15:0] |
| 154 | or %l6, %l1, %l6 ! Write 1 to all other 15 ways' allocate bits |
| 155 | |
| 156 | ! also need to set ECC bits for Allocate bits (Bits [38:32]) |
| 157 | set_ECC_Allocate: |
| 158 | mov 0x7f, %l0 |
| 159 | sllx %l0, 32, %l0 |
| 160 | xor %l6, %l0, %l1 |
| 161 | or %l6, %l1, %l6 |
| 162 | |
| 163 | write_l2_UA_diag: |
| 164 | ! stx %l6, [%l7] |
| 165 | |
| 166 | |
| 167 | ! Now do another store with the same index but different tag - to force a Write-Back |
| 168 | error_address: |
| 169 | mov 0x1, %l0 |
| 170 | sllx %l0, 28, %l0 |
| 171 | xor %g1, %l0, %l1 ! Flip bit 28 of previous L2 entry PA |
| 172 | |
| 173 | ! This should cause L2 LDWC (bit 51) |
| 174 | store_to_L2_with_error: |
| 175 | st %g5, [%l1] |
| 176 | membar #Sync |
| 177 | |
| 178 | |
| 179 | enable_l1: |
| 180 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 181 | or %l0, 0x3, %l0 |
| 182 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 183 | |
| 184 | |
| 185 | ! Compute expected value of L2 error status register |
| 186 | compute_expected_L2_ESR: |
| 187 | mov 0x1, %l1 |
| 188 | sllx %l1, L2ES_LDWC, %l0 |
| 189 | sllx %l1, L2ES_VEC, %l3 ! VEC bit |
| 190 | or %l0, %l3, %l0 |
| 191 | ! No RW bit or Syndrome field for LDWC - %l0 has expected value |
| 192 | |
| 193 | setx L2ES_PA0, %l2, %l3 |
| 194 | |
| 195 | |
| 196 | check_l2_ESR: |
| 197 | ldx [%l3], %l4 |
| 198 | |
| 199 | cmp %l4, %l0 |
| 200 | bne test_fail |
| 201 | nop |
| 202 | |
| 203 | setx L2EA_PA0, %l2, %l3 |
| 204 | check_l2_EAR: |
| 205 | ldx [%l3], %l4 |
| 206 | |
| 207 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 208 | andn %g1, 0x3f, %l1 |
| 209 | cmp %l4, %l1 |
| 210 | bne test_fail |
| 211 | nop |
| 212 | |
| 213 | ba test_pass |
| 214 | nop |
| 215 | |
| 216 | /******************************************************* |
| 217 | * Exit code |
| 218 | *******************************************************/ |
| 219 | |
| 220 | test_pass: |
| 221 | ta T_GOOD_TRAP |
| 222 | |
| 223 | test_fail: |
| 224 | ta T_BAD_TRAP |
| 225 | |