| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_L2_NotData_NDDM_shadow.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define ENABLE_PCIE_LINK_TRAINING |
| 39 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 40 | #define MAIN_PAGE_HV_ALSO |
| 41 | |
| 42 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 43 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 44 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 45 | #define L2_ERR_ADDR_REG 0xAC00000000 |
| 46 | #define L2_NDDM_REG 0xAE00000000 |
| 47 | |
| 48 | #define TT_SW_Error 0x40 |
| 49 | |
| 50 | |
| 51 | #define ERROR_ADDR 0x20200000 |
| 52 | #define TEST_DATA0 0x1000100081c3e008 |
| 53 | #define TEST_DATA1 0x2000200081c3e008 |
| 54 | #define TEST_DATA2 0x3000300081c3e008 |
| 55 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 56 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 57 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000aa00 |
| 58 | |
| 59 | #include "hboot.s" |
| 60 | #include "asi_s.h" |
| 61 | #include "err_defines.h" |
| 62 | #include "peu_defines.h" |
| 63 | #include "nmacros.h" |
| 64 | #include "cmp_macros.h" |
| 65 | |
| 66 | #ifdef SSI_CLK_8_3 |
| 67 | #define CLK_RATIO_VAL 0x03 |
| 68 | #else |
| 69 | #ifdef SSI_CLK_8_2 |
| 70 | #define CLK_RATIO_VAL 0x02 |
| 71 | #else |
| 72 | #ifdef SSI_CLK_4 |
| 73 | #define CLK_RATIO_VAL 0x01 |
| 74 | #else |
| 75 | #define CLK_RATIO_VAL 0x00 |
| 76 | #endif |
| 77 | #endif |
| 78 | #endif |
| 79 | |
| 80 | |
| 81 | .text |
| 82 | .global main |
| 83 | |
| 84 | |
| 85 | |
| 86 | main: |
| 87 | ta T_CHANGE_HPRIV |
| 88 | nop |
| 89 | |
| 90 | ! Determine thread running on |
| 91 | |
| 92 | ta T_RD_THID |
| 93 | cmp %o1, 0 |
| 94 | be main_t0 |
| 95 | nop |
| 96 | ba main_t1_to_t63 |
| 97 | nop |
| 98 | |
| 99 | |
| 100 | main_t0: |
| 101 | |
| 102 | ta T_CHANGE_HPRIV |
| 103 | |
| 104 | |
| 105 | |
| 106 | |
| 107 | disable_l1: |
| 108 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 109 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 110 | andn %l0, 0x3, %l0 |
| 111 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 112 | |
| 113 | setx 0x20040000, %l0, %g6 |
| 114 | |
| 115 | |
| 116 | clear_dram_esr_0: |
| 117 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 118 | setx DRAM_ES_W1C_VALUE, %l0, %g4 |
| 119 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 120 | stx %g4, [%g5] |
| 121 | |
| 122 | set_DRAM_error_inject_ch0: |
| 123 | mov 0x602, %l1 ! ECC Mask (2-bit error) |
| 124 | mov 0x1, %l2 |
| 125 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 126 | Or %l1, %l3, %l1 ! Set single shot ; |
| 127 | mov 0x1, %l2 |
| 128 | sllx %l2, DRAM_EI_ENB, %l3 |
| 129 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 130 | setx DRAM_ERR_INJ_REG, %l3, %g5 |
| 131 | stx %l1, [%g5] |
| 132 | membar 0x40 |
| 133 | |
| 134 | !enable_err_reporting: |
| 135 | ! setx L2EE_PA0, %l0, %l1 |
| 136 | ! ldx [%l1], %l2 |
| 137 | ! mov 0x3, %l0 |
| 138 | ! or %l2, %l0, %l2 |
| 139 | ! stx %l2, [%l1] |
| 140 | |
| 141 | ! Write 1 to clear L2 Error status registers |
| 142 | clear_l2_ESR: |
| 143 | setx L2ES_PA0, %l3, %l4 |
| 144 | stx %g4, [%l4] |
| 145 | nop |
| 146 | |
| 147 | store_to_L2: |
| 148 | setx TEST_DATA1, %l0, %g5 |
| 149 | |
| 150 | |
| 151 | set_L2_Directly_Mapped_Mode: |
| 152 | setx L2CS_PA0, %l6, %g1 |
| 153 | mov 0x2, %l0 |
| 154 | stx %l0, [%g1] |
| 155 | |
| 156 | |
| 157 | store_to_L2_way0: |
| 158 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way |
| 159 | stx %g5, [%g2] |
| 160 | stx %g5, [%g2+8] |
| 161 | membar #Sync |
| 162 | |
| 163 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 164 | write_mcu_channel_0: |
| 165 | setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way |
| 166 | stx %g5, [%g3] |
| 167 | stx %g5, [%g3+8] |
| 168 | membar #Sync |
| 169 | |
| 170 | read_error_address_ch0: |
| 171 | stx %g5, [%g2] |
| 172 | membar #Sync |
| 173 | |
| 174 | Wr_Evnt: nop; |
| 175 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) |
| 176 | |
| 177 | clr %i7 |
| 178 | set 0x20,%l7 |
| 179 | loop: |
| 180 | inc %i7 |
| 181 | cmp %i7,%l7 |
| 182 | bne loop |
| 183 | nop |
| 184 | |
| 185 | Wr_Evnt1: nop; |
| 186 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt1) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) |
| 187 | |
| 188 | clr %i7 |
| 189 | set 0x20,%l7 |
| 190 | loop_wr: |
| 191 | inc %i7 |
| 192 | cmp %i7,%l7 |
| 193 | bne loop_wr |
| 194 | nop |
| 195 | |
| 196 | |
| 197 | |
| 198 | check_DRAM_ESR_0: |
| 199 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 200 | ldx [%g5], %l6 |
| 201 | |
| 202 | compute_dram_ESR: |
| 203 | setx 0xffffffffffff0000, %l0,%o2 |
| 204 | and %l6,%o2,%l6 |
| 205 | mov 0x1, %l1 |
| 206 | sllx %l1, DRAM_ES_DAU, %l0 |
| 207 | |
| 208 | verify_dram_ESR: |
| 209 | cmp %l0, %l6 |
| 210 | bne %xcc, test_fail |
| 211 | nop |
| 212 | |
| 213 | check_L2_ESR_0: |
| 214 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 215 | ldx [%g5], %l6 |
| 216 | |
| 217 | compute_L2_ESR: |
| 218 | setx 0xfffffffff0000000, %l3, %l0 |
| 219 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits |
| 220 | mov 0x1, %l1 |
| 221 | sllx %l1, L2ES_DAU, %l0 |
| 222 | mov 0x1, %l1 |
| 223 | sllx %l1, L2ES_VEU, %l2 |
| 224 | or %l0, %l2, %l3 |
| 225 | |
| 226 | verify_L2_ESR: |
| 227 | cmp %l6, %l3 |
| 228 | bne %xcc, test_fail |
| 229 | nop |
| 230 | |
| 231 | check_notData_reg: |
| 232 | setx L2_NDDM_REG, %l3, %g5 |
| 233 | ldx [%g5], %l6 |
| 234 | |
| 235 | compute_notData_reg: |
| 236 | setx 0x900002000aa00, %l0, %l1 ! bits [21:18] select way |
| 237 | setx 0xfffffffffffc0, %l0,%o2 |
| 238 | and %l6, %o2, %l6 |
| 239 | cmp %l6, %l1 |
| 240 | bne %xcc, test_fail |
| 241 | nop |
| 242 | |
| 243 | setx L2EA_PA0, %l2, %l3 |
| 244 | check_l2_EAR: |
| 245 | ldx [%l3], %l4 |
| 246 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 247 | setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way |
| 248 | setx 0xffffffffc0, %l0,%o2 |
| 249 | and %l4, %o2, %l4 |
| 250 | cmp %l4, %l1 |
| 251 | bne %xcc, test_fail |
| 252 | nop |
| 253 | |
| 254 | |
| 255 | ba test_pass |
| 256 | nop |
| 257 | |
| 258 | |
| 259 | /************************************************************************ |
| 260 | Thread 1 to 63 code |
| 261 | ************************************************************************/ |
| 262 | |
| 263 | main_t1_to_t63: |
| 264 | |
| 265 | ! Sync up all the treads. |
| 266 | |
| 267 | |
| 268 | test: |
| 269 | !Verify clock ratio counter value |
| 270 | wr %g0,ASI_CMP_CORE,%asi |
| 271 | setx 0x8000003040,%g7,%g1 |
| 272 | ldx [%g1],%g2 |
| 273 | setx CLK_RATIO_VAL,%g7,%g1 |
| 274 | cmp %g2,%g1 |
| 275 | bne test_fail |
| 276 | nop |
| 277 | |
| 278 | !Read words from the SSI interface |
| 279 | setx 0x000000fff0000000,%g7,%g1 |
| 280 | set 0x3,%g2 |
| 281 | loop1: |
| 282 | lduw [%g1],%g3 |
| 283 | add %g1,4,%g1 |
| 284 | sub %g2,1,%g2 |
| 285 | cmp %g2,%g0 |
| 286 | bne loop1 |
| 287 | nop |
| 288 | |
| 289 | ba test_pass |
| 290 | nop |
| 291 | |
| 292 | /******************************************************* |
| 293 | * Exit code |
| 294 | *******************************************************/ |
| 295 | |
| 296 | test_pass: |
| 297 | ta T_GOOD_TRAP |
| 298 | |
| 299 | |
| 300 | test_fail: |
| 301 | ta T_BAD_TRAP |
| 302 | |
| 303 | |
| 304 | /************************************************************************ |
| 305 | * Test case data start |
| 306 | ************************************************************************/ |