| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_l2_LDRU_Rd_uecc.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | |
| 41 | #define L2_ENTRY_PA 0xa000000000 |
| 42 | #define TEST_DATA1 0x5555555555555555 |
| 43 | #define L2_ENTRY_PA0 0x2020000008 |
| 44 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 45 | #define SPARC_ES_W1C_VALUE 0xefffffff |
| 46 | #define TT_SW_Error 0x40 |
| 47 | |
| 48 | #include "hboot.s" |
| 49 | #include "asi_s.h" |
| 50 | #include "err_defines.h" |
| 51 | |
| 52 | .text |
| 53 | .global main |
| 54 | |
| 55 | main: |
| 56 | |
| 57 | |
| 58 | ! Boot code does not provide TLB translation for IO address space |
| 59 | ta T_CHANGE_HPRIV |
| 60 | |
| 61 | |
| 62 | disable_l1_DCache: |
| 63 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 64 | ! Remove bit 2 |
| 65 | andn %l0, 0x2, %l0 |
| 66 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 67 | |
| 68 | |
| 69 | clear_l2_ESR: |
| 70 | setx L2_ES_W1C_VALUE, %l0, %l1 |
| 71 | setx L2ES_PA0, %l6, %g1 |
| 72 | stx %l1, [%g1] |
| 73 | |
| 74 | |
| 75 | set_L2_Directly_Mapped_Mode: |
| 76 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register |
| 77 | mov 0x2, %l0 |
| 78 | stx %l0, [%g1] |
| 79 | |
| 80 | store_to_L2: |
| 81 | setx TEST_DATA1, %l0, %g5 |
| 82 | |
| 83 | store_to_L2_way0: |
| 84 | setx 0x202000aa00, %l0, %g2 ! bits [21:18] select way |
| 85 | stx %g5, [%g2] |
| 86 | stx %g5, [%g2+8] |
| 87 | membar #Sync |
| 88 | |
| 89 | L2_diag_load: |
| 90 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] |
| 91 | setx L2_ENTRY_PA, %l0, %g4 |
| 92 | and %g2, %l2, %g5 !g2 has L2 PA, |
| 93 | or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address |
| 94 | ldx [%g5], %g6 |
| 95 | membar #Sync |
| 96 | |
| 97 | ! Flip two bits to inject error |
| 98 | xor %g6, 0x300, %g6 |
| 99 | stx %g6, [%g5] |
| 100 | membar #Sync |
| 101 | |
| 102 | /* |
| 103 | reading_back_0: !Load to L2 again to get the error |
| 104 | setx 0x202000aa00, %l0, %g2 |
| 105 | ldx [%g2], %l6 |
| 106 | membar #Sync |
| 107 | */ |
| 108 | |
| 109 | ldsw: |
| 110 | nop; !$EV trig_pc_d(0,@VA(.MAIN.ldsw)) -> siuDmaRd(202000aa00,2,0) |
| 111 | |
| 112 | |
| 113 | enable_l1_DCache: |
| 114 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 115 | or %l0, 0x2, %l0 |
| 116 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 117 | |
| 118 | |
| 119 | compute_error: |
| 120 | mov 0x1, %l1 |
| 121 | sllx %l1, L2ES_LDRU, %l7 |
| 122 | sllx %l1, L2ES_VEU, %l3 |
| 123 | or %l7, %l3, %l7 |
| 124 | membar #Sync |
| 125 | |
| 126 | |
| 127 | check_l2_ESR: |
| 128 | setx L2ES_PA0, %l6, %g1 |
| 129 | ldx [%g1], %l4 |
| 130 | membar #Sync |
| 131 | |
| 132 | verify_ESR: |
| 133 | cmp %l7, %l4 ! l7 has expected value, l4 has actual value |
| 134 | bne test_fail |
| 135 | |
| 136 | |
| 137 | check_l2_EAR: |
| 138 | setx L2EA_PA0, %l6, %l3 |
| 139 | ldx [%l3], %l4 |
| 140 | membar #Sync |
| 141 | |
| 142 | verify_EAR: |
| 143 | setx 0x202000aa00, %l0, %g2 ! bits [21:18] select way |
| 144 | cmp %g2, %l4 ! g2 has expected value, l4 has actual value |
| 145 | bne test_fail |
| 146 | nop |
| 147 | |
| 148 | |
| 149 | ba test_pass |
| 150 | nop |
| 151 | |
| 152 | |
| 153 | |
| 154 | /******************************************************* |
| 155 | * Exit code |
| 156 | *******************************************************/ |
| 157 | |
| 158 | test_pass: |
| 159 | ta T_GOOD_TRAP |
| 160 | |
| 161 | test_fail: |
| 162 | ta T_BAD_TRAP |