| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_l2_LRU.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | |
| 42 | #include "hboot.s" |
| 43 | #include "asi_s.h" |
| 44 | #include "err_defines.h" |
| 45 | |
| 46 | .text |
| 47 | .global main |
| 48 | |
| 49 | #define L2_ENTRY_PA 0x400500000 |
| 50 | #define L2_BANK_ADDR 0x80 |
| 51 | #define DRAM_CHANNEL_ADDR 0x2000 |
| 52 | #define TEST_DATA0 0x5555555555555555 |
| 53 | #define TEST_DATA1 0xaaaaaaaaaaaaaaaa |
| 54 | #define TEST_DATA2 0x3000300081c3e008 |
| 55 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 56 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 57 | |
| 58 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 59 | |
| 60 | #define L2_ENTRY_PA0 0x20200000 |
| 61 | #define L2_ENTRY_PA1 0x21200000 |
| 62 | #define L2_ENTRY_PA2 0x22200000 |
| 63 | #define L2_ENTRY_PA3 0x23200000 |
| 64 | #define L2_ENTRY_PA4 0x24200000 |
| 65 | #define L2_ENTRY_PA5 0x25200000 |
| 66 | #define L2_ENTRY_PA6 0x26200000 |
| 67 | #define L2_ENTRY_PA7 0x27200000 |
| 68 | #define L2_ENTRY_PA8 0x28200000 |
| 69 | #define L2_ENTRY_PA9 0x29200000 |
| 70 | #define L2_ENTRY_PAa 0x2a200000 |
| 71 | #define L2_ENTRY_PAb 0x2b200000 |
| 72 | #define L2_ENTRY_PAc 0x2c200000 |
| 73 | #define L2_ENTRY_PAd 0x2d200000 |
| 74 | #define L2_ENTRY_PAe 0x2e200000 |
| 75 | #define L2_ENTRY_PAf 0x2f200000 |
| 76 | #define L2_ENTRY_PA10 0x30200000 |
| 77 | #define L2_ENTRY_PA11 0x31200000 |
| 78 | #define L2_ENTRY_PA12 0x32200000 |
| 79 | |
| 80 | #define DC_ENTRY_PA0 0x20200000 |
| 81 | #define DC_ENTRY_PA1 0x20200800 |
| 82 | #define DC_ENTRY_PA2 0x20201000 |
| 83 | #define DC_ENTRY_PA3 0x20201800 |
| 84 | #define DC_ENTRY_PA4 0x20202000 |
| 85 | #define DC_ENTRY_PA5 0x20202800 |
| 86 | #define DC_ENTRY_PA6 0x20203000 |
| 87 | #define DC_ENTRY_PA7 0x20203800 |
| 88 | #define DC_ENTRY_PA8 0x20204000 |
| 89 | #define DC_ENTRY_PA9 0x20204800 |
| 90 | #define DC_ENTRY_PAa 0x20205000 |
| 91 | #define DC_ENTRY_PAb 0x20205800 |
| 92 | |
| 93 | |
| 94 | main: |
| 95 | ta T_CHANGE_HPRIV |
| 96 | |
| 97 | |
| 98 | clear_l2_ESR: |
| 99 | ! Write 1 to clear L2 Error status registers |
| 100 | setx L2ES_PA0, %l3, %l4 |
| 101 | setx L2_ES_W1C_VALUE, %l0, %l1 |
| 102 | stx %l1, [%l4] |
| 103 | nop |
| 104 | |
| 105 | create_entry: |
| 106 | setx TEST_DATA0, %l2, %l1 |
| 107 | |
| 108 | setx DC_ENTRY_PA0, %l0, %g1 |
| 109 | stx %l1, [%g1] |
| 110 | |
| 111 | setx DC_ENTRY_PA1, %l0, %g1 |
| 112 | stx %l1, [%g1] |
| 113 | |
| 114 | setx DC_ENTRY_PA2, %l0, %g1 |
| 115 | stx %l1, [%g1] |
| 116 | |
| 117 | setx DC_ENTRY_PA3, %l0, %g1 |
| 118 | stx %l1, [%g1] |
| 119 | |
| 120 | |
| 121 | Enable_err_inj_reg: |
| 122 | setx L2EI_PA0, %l3, %l4 |
| 123 | set 0x3, %l1 |
| 124 | stx %l1, [%l4] |
| 125 | nop |
| 126 | ldx [%l4], %o1 |
| 127 | |
| 128 | update_directory: |
| 129 | setx TEST_DATA0, %l2, %l1 |
| 130 | |
| 131 | setx DC_ENTRY_PA4, %l0, %g1 |
| 132 | stx %l1, [%g1] |
| 133 | |
| 134 | setx DC_ENTRY_PA5, %l0, %g1 |
| 135 | stx %l1, [%g1] |
| 136 | |
| 137 | setx DC_ENTRY_PA6, %l0, %g1 |
| 138 | stx %l1, [%g1] |
| 139 | |
| 140 | setx DC_ENTRY_PA7, %l0, %g1 |
| 141 | stx %l1, [%g1] |
| 142 | |
| 143 | membar 0x40 |
| 144 | |
| 145 | write_mcu_channel_0: |
| 146 | setx L2_ENTRY_PA0, %l0, %g1 |
| 147 | setx TEST_DATA1, %l2, %l1 |
| 148 | stx %l1, [%g1] |
| 149 | setx L2_ENTRY_PA1, %l0, %g1 |
| 150 | setx TEST_DATA1, %l2, %l1 |
| 151 | stx %l1, [%g1] |
| 152 | setx L2_ENTRY_PA2, %l0, %g1 |
| 153 | setx TEST_DATA1, %l2, %l1 |
| 154 | stx %l1, [%g1] |
| 155 | setx L2_ENTRY_PA3, %l0, %g1 |
| 156 | setx TEST_DATA1, %l2, %l1 |
| 157 | stx %l1, [%g1] |
| 158 | setx L2_ENTRY_PA4, %l0, %g1 |
| 159 | setx TEST_DATA1, %l2, %l1 |
| 160 | stx %l1, [%g1] |
| 161 | setx L2_ENTRY_PA5, %l0, %g1 |
| 162 | setx TEST_DATA1, %l2, %l1 |
| 163 | stx %l1, [%g1] |
| 164 | setx L2_ENTRY_PA6, %l0, %g1 |
| 165 | setx TEST_DATA1, %l2, %l1 |
| 166 | stx %l1, [%g1] |
| 167 | setx L2_ENTRY_PA7, %l0, %g1 |
| 168 | setx TEST_DATA1, %l2, %l1 |
| 169 | stx %l1, [%g1] |
| 170 | setx L2_ENTRY_PA8, %l0, %g1 |
| 171 | setx TEST_DATA1, %l2, %l1 |
| 172 | stx %l1, [%g1] |
| 173 | setx L2_ENTRY_PA9, %l0, %g1 |
| 174 | setx TEST_DATA1, %l2, %l1 |
| 175 | stx %l1, [%g1] |
| 176 | setx L2_ENTRY_PAa, %l0, %g1 |
| 177 | setx TEST_DATA1, %l2, %l1 |
| 178 | stx %l1, [%g1] |
| 179 | setx L2_ENTRY_PAb, %l0, %g1 |
| 180 | setx TEST_DATA1, %l2, %l1 |
| 181 | stx %l1, [%g1] |
| 182 | setx L2_ENTRY_PAc, %l0, %g1 |
| 183 | setx TEST_DATA1, %l2, %l1 |
| 184 | stx %l1, [%g1] |
| 185 | setx L2_ENTRY_PAd, %l0, %g1 |
| 186 | setx TEST_DATA1, %l2, %l1 |
| 187 | stx %l1, [%g1] |
| 188 | setx L2_ENTRY_PAe, %l0, %g1 |
| 189 | setx TEST_DATA1, %l2, %l1 |
| 190 | stx %l1, [%g1] |
| 191 | setx L2_ENTRY_PAf, %l0, %g1 |
| 192 | setx TEST_DATA1, %l2, %l1 |
| 193 | stx %l1, [%g1] |
| 194 | setx L2_ENTRY_PA10, %l0, %g1 |
| 195 | setx TEST_DATA1, %l2, %l1 |
| 196 | stx %l1, [%g1] |
| 197 | membar 0x40 |
| 198 | |
| 199 | |
| 200 | compute_error: |
| 201 | mov 0x1, %l1 |
| 202 | sllx %l1, L2ES_LRU, %l7 |
| 203 | sllx %l1, L2ES_VEU, %l3 |
| 204 | or %l7, %l3, %l7 |
| 205 | |
| 206 | check_L2_ESR_0: |
| 207 | setx L2ES_PA0, %l3, %g5 |
| 208 | ldx [%g5], %l6 |
| 209 | membar #Sync |
| 210 | |
| 211 | verify_error: |
| 212 | cmp %l7, %l6 |
| 213 | bne %xcc, test_fail |
| 214 | nop |
| 215 | nop |
| 216 | |
| 217 | ch_L2_addr_ch0: |
| 218 | setx L2EA_PA0, %l3, %g5 |
| 219 | ldx [%g5], %l1 |
| 220 | membar 0x40 |
| 221 | |
| 222 | ba test_pass |
| 223 | nop |
| 224 | |
| 225 | |
| 226 | /******************************************************* |
| 227 | * Exit code |
| 228 | *******************************************************/ |
| 229 | |
| 230 | test_pass: |
| 231 | EXIT_GOOD |
| 232 | |
| 233 | test_fail: |
| 234 | EXIT_BAD |
| 235 | |
| 236 | |