| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_adv_mcu_4_CRC_MULTI_ECC.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 42 | #define L2_ERR_ADDR_REG 0xAC00000000 |
| 43 | |
| 44 | #define TEST_DATA1 0x1000100081c3e008 |
| 45 | #define TEST_DATA2 0x2000200081c3e008 |
| 46 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 47 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 48 | |
| 49 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 50 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 51 | #define ERROR_ADDR 0x20200000 |
| 52 | |
| 53 | #define DRAM_SCRUB_FREQ_REG 0x8400000018 |
| 54 | #define DRAM_SCRUB_ENB_REG 0x8400000040 |
| 55 | |
| 56 | #include "hboot.s" |
| 57 | #include "asi_s.h" |
| 58 | #include "err_defines.h" |
| 59 | |
| 60 | |
| 61 | .text |
| 62 | .global main |
| 63 | |
| 64 | |
| 65 | main: |
| 66 | ta T_CHANGE_HPRIV |
| 67 | |
| 68 | ! begin |
| 69 | get_th_id_o0: |
| 70 | ta T_RD_THID |
| 71 | cmp %o1, 0x0 |
| 72 | be main_t0 |
| 73 | nop |
| 74 | cmp %o1, 0x1 |
| 75 | be main_t1 |
| 76 | nop |
| 77 | |
| 78 | main_t0: |
| 79 | ba L2B0_Init |
| 80 | nop |
| 81 | |
| 82 | L2B0_Init: |
| 83 | disable_l1: |
| 84 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 85 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 86 | andn %l0, 0x3, %l0 |
| 87 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 88 | |
| 89 | clear_DRAM_ESR_MCU0_B0: |
| 90 | clr %l0 |
| 91 | clr %l1 |
| 92 | setx DRAM_ES_W1C_VALUE, %l0, %g2 |
| 93 | setx 0x8400000280, %l1, %g6 |
| 94 | stx %g2, [%g6] |
| 95 | clear_L2_ESR_BANK_0: |
| 96 | clr %l0 |
| 97 | clr %l1 |
| 98 | setx L2_ES_W1C_VALUE, %l0, %g4 |
| 99 | setx 0xbb00000000, %l1, %g7 |
| 100 | stx %g4, [%g7] |
| 101 | |
| 102 | set_DRAM_error_inject_mcu0_l2bank0: |
| 103 | mov 0x2, %l1 |
| 104 | !mov 0x1, %l2 |
| 105 | !sllx %l2, DRAM_EI_SSHOT, %l2 |
| 106 | !or %l1, %l2, %l1 |
| 107 | mov 0x1, %l3 |
| 108 | sllx %l3, 31, %l3 |
| 109 | or %l1, %l3, %l1 |
| 110 | setx 0x8400000290, %l0, %g4 |
| 111 | stx %l1, [%g4] |
| 112 | membar 0x40 |
| 113 | |
| 114 | set_L2_Direct_Mapped_Mode_bank0: |
| 115 | clr %l0 |
| 116 | clr %g1 |
| 117 | setx 0xa900000000, %l0, %g1 |
| 118 | clr %l0 |
| 119 | mov 0x2, %l0 |
| 120 | stx %l0, [%g1] |
| 121 | membar 0x40 |
| 122 | |
| 123 | clr %g1 |
| 124 | clr %g2 |
| 125 | clr %l1 |
| 126 | setx 0x0123456789abcdef, %l1, %g2 |
| 127 | clr %l2 |
| 128 | mov 0x1, %l2 |
| 129 | sllx %l2, 22, %l2 |
| 130 | clr %l3 |
| 131 | mov 100, %l3 |
| 132 | st_to_L2_way0_and_MCU0: |
| 133 | stx %g2, [%g1] |
| 134 | membar 0x40 |
| 135 | clr %l4 |
| 136 | add %g1, %l2, %l4 |
| 137 | stx %g2, [%l4] |
| 138 | membar 0x40 |
| 139 | add %g1, 0x200, %g1 |
| 140 | sub %l3, 1, %l3 |
| 141 | brnz %l3,st_to_L2_way0_and_MCU0 |
| 142 | nop |
| 143 | |
| 144 | clr %g1 |
| 145 | clr %l2 |
| 146 | mov 200, %l2 |
| 147 | ld_from_error_and_nonerror_address_b0: |
| 148 | ld [%g1], %l1 |
| 149 | membar 0x40 |
| 150 | add %g1, 0x100, %g1 |
| 151 | sub %l2, 1, %l2 |
| 152 | brnz %l2,ld_from_error_and_nonerror_address_b0 |
| 153 | nop |
| 154 | |
| 155 | clr %g1 |
| 156 | mov 0x1, %g1 |
| 157 | sllx %g1, 32, %g1 |
| 158 | clr %g2 |
| 159 | mov 0x1, %g2 |
| 160 | sllx %g2, 22, %g2 |
| 161 | clr %g3 |
| 162 | mov 100, %g3 |
| 163 | |
| 164 | ld_from_L2_bank0_for_CRC: |
| 165 | ldx [%g1], %l1 |
| 166 | membar 0x40 |
| 167 | add %g1, %g2, %g1 |
| 168 | sub %g3, 1, %g3 |
| 169 | brnz %g3,ld_from_L2_bank0_for_CRC |
| 170 | nop |
| 171 | |
| 172 | check_DRAM_ESR_MCU0_L2BANK0_FBR: |
| 173 | !clr %l1 |
| 174 | !mov 0x1, %l1 |
| 175 | !sllx %l1, 54, %l1 |
| 176 | !clr %l2 |
| 177 | !mov 0x3, %l2 |
| 178 | !sllx %l2, 61, %l2 |
| 179 | !or %l1, %l2, %l1 |
| 180 | ldx [%g6], %l0 |
| 181 | clr %l4 |
| 182 | set 0xffff, %l4 |
| 183 | andn %l0, %l4, %l0 |
| 184 | !cmp %l0, %l1 |
| 185 | !bne %xcc, test_fail |
| 186 | !nop |
| 187 | |
| 188 | check_L2_ESR_Bank_0_DSC: |
| 189 | !clr %l1 |
| 190 | !mov 0x1, %l1 |
| 191 | !sllx %l1, 38, %l1 |
| 192 | !clr %l2 |
| 193 | !mov 0x1, %l2 |
| 194 | !sllx %l2, 42, %l2 |
| 195 | !or %l1, %l2, %l1 |
| 196 | !clr %l3 |
| 197 | !mov 0x1, %l3 |
| 198 | !sllx %l3, 36, %l3 |
| 199 | !or %l1, %l3, %l1 |
| 200 | !clr %l4 |
| 201 | !mov 0x1, %l4 |
| 202 | !sllx %l4, 62, %l4 |
| 203 | !or %l1, %l4, %l1 |
| 204 | ldx [%g7], %l0 |
| 205 | clr %l2 |
| 206 | clr %l3 |
| 207 | setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54] |
| 208 | and %l0, %l3, %l0 |
| 209 | !cmp %l0, %l1 |
| 210 | !bne %xcc, test_fail |
| 211 | !nop |
| 212 | |
| 213 | ba test_pass |
| 214 | nop |
| 215 | |
| 216 | main_t1: |
| 217 | ba L2B1_Init |
| 218 | nop |
| 219 | |
| 220 | L2B1_Init: |
| 221 | |
| 222 | clear_DRAM_ESR_MCU0_B1: |
| 223 | clr %l0 |
| 224 | clr %l1 |
| 225 | setx DRAM_ES_W1C_VALUE, %l0, %g2 |
| 226 | setx 0x8400000280, %l1, %g6 |
| 227 | stx %g2, [%g6] |
| 228 | clear_L2_ESR_BANK_1: |
| 229 | clr %l0 |
| 230 | clr %l1 |
| 231 | setx L2_ES_W1C_VALUE, %l0, %g4 |
| 232 | setx 0xbb00000040, %l1, %g7 |
| 233 | stx %g4, [%g7] |
| 234 | |
| 235 | set_DRAM_error_inject_mcu0_l2bank1: |
| 236 | mov 0x2, %l1 |
| 237 | !mov 0x1, %l2 |
| 238 | !sllx %l2, DRAM_EI_SSHOT, %l2 |
| 239 | !or %l1, %l2, %l1 |
| 240 | mov 0x1, %l3 |
| 241 | sllx %l3, 31, %l3 |
| 242 | or %l1, %l3, %l1 |
| 243 | setx 0x8400000290, %l0, %g4 |
| 244 | stx %l1, [%g4] |
| 245 | membar 0x40 |
| 246 | |
| 247 | set_L2_Direct_Mapped_Mode_bank1: |
| 248 | clr %l0 |
| 249 | clr %g1 |
| 250 | setx 0xa900000040, %l0, %g1 |
| 251 | clr %l0 |
| 252 | mov 0x2, %l0 |
| 253 | stx %l0, [%g1] |
| 254 | membar 0x40 |
| 255 | |
| 256 | clr %g1 |
| 257 | add %g1, 0x40, %g1 |
| 258 | clr %g2 |
| 259 | clr %l1 |
| 260 | setx 0x0123456789abcdef, %l1, %g2 |
| 261 | clr %l2 |
| 262 | mov 0x1, %l2 |
| 263 | sllx %l2, 22, %l2 |
| 264 | clr %l3 |
| 265 | mov 100, %l3 |
| 266 | st_to_L2_way1_and_MCU0: |
| 267 | stx %g2, [%g1] |
| 268 | membar 0x40 |
| 269 | clr %l4 |
| 270 | add %g1, %l2, %l4 |
| 271 | stx %g2, [%l4] |
| 272 | membar 0x40 |
| 273 | add %g1, 0x200, %g1 |
| 274 | sub %l3, 1, %l3 |
| 275 | brnz %l3,st_to_L2_way1_and_MCU0 |
| 276 | nop |
| 277 | |
| 278 | clr %g1 |
| 279 | add %g1, 0x40, %g1 |
| 280 | clr %l2 |
| 281 | mov 200, %l2 |
| 282 | ld_from_error_and_nonerror_address_b1: |
| 283 | ld [%g1], %l1 |
| 284 | membar 0x40 |
| 285 | add %g1, 0x100, %g1 |
| 286 | sub %l2, 1, %l2 |
| 287 | brnz %l2,ld_from_error_and_nonerror_address_b1 |
| 288 | nop |
| 289 | |
| 290 | clr %g1 |
| 291 | mov 0x1, %g1 |
| 292 | sllx %g1, 32, %g1 |
| 293 | add %g1, 0x40, %g1 |
| 294 | clr %g2 |
| 295 | mov 0x1, %g2 |
| 296 | sllx %g2, 22, %g2 |
| 297 | clr %g3 |
| 298 | mov 100, %g3 |
| 299 | |
| 300 | ld_from_L2_bank1_for_CRC: |
| 301 | ldx [%g1], %l1 |
| 302 | membar 0x40 |
| 303 | add %g1, %g2, %g1 |
| 304 | sub %g3, 1, %g3 |
| 305 | brnz %g3,ld_from_L2_bank1_for_CRC |
| 306 | nop |
| 307 | |
| 308 | check_DRAM_ESR_MCU0_L2BANK1_FBR: |
| 309 | !clr %l1 |
| 310 | !mov 0x1, %l1 |
| 311 | !sllx %l1, 54, %l1 |
| 312 | !clr %l2 |
| 313 | !mov 0x3, %l2 |
| 314 | !sllx %l2, 61, %l2 |
| 315 | !or %l1, %l2, %l1 |
| 316 | ldx [%g6], %l0 |
| 317 | clr %l4 |
| 318 | set 0xffff, %l4 |
| 319 | andn %l0, %l4, %l0 |
| 320 | !cmp %l0, %l1 |
| 321 | !bne %xcc, test_fail |
| 322 | !nop |
| 323 | |
| 324 | check_L2_ESR_Bank_1_DSC: |
| 325 | !clr %l1 |
| 326 | !mov 0x1, %l1 |
| 327 | !sllx %l1, 38, %l1 |
| 328 | !clr %l2 |
| 329 | !mov 0x1, %l2 |
| 330 | !sllx %l2, 42, %l2 |
| 331 | !or %l1, %l2, %l1 |
| 332 | !clr %l3 |
| 333 | !mov 0x1, %l3 |
| 334 | !sllx %l3, 36, %l3 |
| 335 | !or %l1, %l3, %l1 |
| 336 | !clr %l4 |
| 337 | !mov 0x1, %l4 |
| 338 | !sllx %l4, 62, %l4 |
| 339 | !or %l1, %l4, %l1 |
| 340 | ldx [%g7], %l0 |
| 341 | clr %l2 |
| 342 | clr %l3 |
| 343 | setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54] |
| 344 | and %l0, %l3, %l0 |
| 345 | !cmp %l0, %l1 |
| 346 | !bne %xcc, test_fail |
| 347 | !nop |
| 348 | |
| 349 | ba test_pass |
| 350 | nop |
| 351 | |
| 352 | /******************************************************* |
| 353 | * Exit code |
| 354 | *******************************************************/ |
| 355 | |
| 356 | test_pass: |
| 357 | ta T_GOOD_TRAP |
| 358 | |
| 359 | test_fail: |
| 360 | ta T_BAD_TRAP |
| 361 | |