| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_all_4_mcu.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap |
| 39 | |
| 40 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 41 | #define MAIN_PAGE_HV_ALSO |
| 42 | |
| 43 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 44 | #define L2_ERR_ADDR_REG 0xAC00000000 |
| 45 | |
| 46 | #define TEST_DATA0 0x1000100081c3e008 |
| 47 | #define TEST_DATA1 0x2000200081c3e008 |
| 48 | #define TEST_DATA2 0x3000300081c3e008 |
| 49 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 50 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 51 | |
| 52 | #define L2_BANK_ADDR0 0x0 |
| 53 | #define MCU_BANK_ADDR0 0x0 |
| 54 | #define DRAM_ERR_INJ_REG0 0x8400000290 |
| 55 | #define DRAM_ERR_STAT_REG0 0x8400000280 |
| 56 | #define ERROR_ADDR0 0x20200000 |
| 57 | |
| 58 | #define L2_BANK_ADDR1 0x80 |
| 59 | #define MCU_BANK_ADDR1 0x80 |
| 60 | #define DRAM_ERR_INJ_REG1 0x8400001290 |
| 61 | #define DRAM_ERR_STAT_REG1 0x8400001280 |
| 62 | #define ERROR_ADDR1 0x20200000 |
| 63 | |
| 64 | |
| 65 | #define L2_BANK_ADDR2 0x100 |
| 66 | #define MCU_BANK_ADDR2 0x100 |
| 67 | #define DRAM_ERR_INJ_REG2 0x8400002290 |
| 68 | #define DRAM_ERR_STAT_REG2 0x8400002280 |
| 69 | #define ERROR_ADDR2 0x20200100 |
| 70 | |
| 71 | #define L2_BANK_ADDR3 0x180 |
| 72 | #define MCU_BANK_ADDR3 0x180 |
| 73 | #define DRAM_ERR_INJ_REG3 0x8400003290 |
| 74 | #define DRAM_ERR_STAT_REG3 0x8400003280 |
| 75 | #define ERROR_ADDR3 0x20200000 |
| 76 | |
| 77 | |
| 78 | #include "hboot.s" |
| 79 | #include "asi_s.h" |
| 80 | #include "err_defines.h" |
| 81 | |
| 82 | |
| 83 | .text |
| 84 | .global main |
| 85 | .global My_Corrected_ECC_error_trap |
| 86 | |
| 87 | main: |
| 88 | |
| 89 | |
| 90 | ! Boot code does not provide TLB translation for IO address space |
| 91 | ta T_CHANGE_HPRIV |
| 92 | |
| 93 | |
| 94 | |
| 95 | |
| 96 | get_th_id_o0: |
| 97 | ta T_RD_THID |
| 98 | |
| 99 | cmp %o1, 0x0 |
| 100 | be main_t0 |
| 101 | nop |
| 102 | |
| 103 | cmp %o1, 0x1 |
| 104 | be main_t1 |
| 105 | nop |
| 106 | |
| 107 | cmp %o1, 0x2 |
| 108 | be main_t2 |
| 109 | nop |
| 110 | |
| 111 | cmp %o1, 0x3 |
| 112 | be main_t3 |
| 113 | nop |
| 114 | |
| 115 | |
| 116 | main_t0: |
| 117 | ba MCU0_Init |
| 118 | nop |
| 119 | |
| 120 | |
| 121 | main_t1: |
| 122 | ba MCU1_Init |
| 123 | nop |
| 124 | |
| 125 | main_t2: |
| 126 | ba MCU2_Init |
| 127 | nop |
| 128 | |
| 129 | main_t3: |
| 130 | ba MCU3_Init |
| 131 | nop |
| 132 | |
| 133 | |
| 134 | |
| 135 | /******************* |
| 136 | DIMM 0,1 |
| 137 | *******************/ |
| 138 | chk_core_running_status_reg: |
| 139 | wr %g0, ASI_CMP_CORE, %asi |
| 140 | ldxa [ASI_CMP_CORE_RUNNING_STATUS]%asi, %l0 |
| 141 | |
| 142 | !Code for Thread1 |
| 143 | MCU1_Init: |
| 144 | |
| 145 | |
| 146 | |
| 147 | disable_l11: |
| 148 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 149 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 150 | andn %l0, 0x3, %l0 |
| 151 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 152 | |
| 153 | |
| 154 | clear_dram_esr_01: |
| 155 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 156 | setx DRAM_ES_W1C_VALUE, %l0, %l5 |
| 157 | setx DRAM_ERR_STAT_REG1, %l3, %g5 |
| 158 | ! add %g5, MCU_BANK_ADDR1, %g5 |
| 159 | stx %l5, [%g5] |
| 160 | |
| 161 | set_DRAM_error_inject_ch01: |
| 162 | mov 0x2, %l1 ! ECC Mask (1-bit error) |
| 163 | mov 0x1, %l2 |
| 164 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 165 | Or %l1, %l3, %l1 ! Set single shot ; |
| 166 | mov 0x1, %l2 |
| 167 | sllx %l2, DRAM_EI_ENB, %l3 |
| 168 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 169 | setx DRAM_ERR_INJ_REG1, %l3, %g6 |
| 170 | ! add %g6, MCU_BANK_ADDR, %g6 |
| 171 | stx %l1, [%g6] |
| 172 | membar 0x40 |
| 173 | |
| 174 | enable_err_reporting1: |
| 175 | setx L2EE_PA0, %l0, %l1 |
| 176 | add %l1, L2_BANK_ADDR1, %l1 |
| 177 | ldx [%l1], %l2 |
| 178 | mov 0x3, %l0 |
| 179 | or %l2, %l0, %l2 |
| 180 | stx %l2, [%l1] |
| 181 | |
| 182 | |
| 183 | ! Write 1 to clear L2 Error status registers |
| 184 | clear_l2_ESR1: |
| 185 | setx L2ES_PA0, %l3, %l4 |
| 186 | add %l4, L2_BANK_ADDR1, %l4 |
| 187 | stx %l5, [%l4] |
| 188 | nop |
| 189 | |
| 190 | store_to_L21: |
| 191 | setx TEST_DATA1, %l0, %g5 |
| 192 | |
| 193 | |
| 194 | set_L2_Directly_Mapped_Mode1: |
| 195 | setx L2CS_PA0, %l6, %g1 |
| 196 | add %g1, L2_BANK_ADDR1, %g1 |
| 197 | mov 0x2, %l0 |
| 198 | stx %l0, [%g1] |
| 199 | |
| 200 | |
| 201 | store_to_L2_way01: |
| 202 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 203 | add %g2, L2_BANK_ADDR1, %g2 |
| 204 | stx %g5, [%g2] |
| 205 | stx %g5, [%g2+8] |
| 206 | membar #Sync |
| 207 | |
| 208 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 209 | write_mcu_channel_01: |
| 210 | setx 0x20210aa00, %l0, %g3 ! bits [21:18] select way |
| 211 | add %g3, L2_BANK_ADDR1, %g3 |
| 212 | stx %g5, [%g3] |
| 213 | stx %g5, [%g3+8] |
| 214 | membar #Sync |
| 215 | |
| 216 | |
| 217 | read_error_address_ch01: |
| 218 | ldx [%g2], %l1 |
| 219 | membar #Sync |
| 220 | ! ldx [%g3], %l2 |
| 221 | ! membar #Sync |
| 222 | |
| 223 | |
| 224 | check_DRAM_ESR_01: |
| 225 | setx DRAM_ERR_STAT_REG1, %l3, %g5 |
| 226 | ! add %g5, MCU_BANK_ADDR1, %g5 |
| 227 | ldx [%g5], %l6 |
| 228 | |
| 229 | compute_dram_ESR1: |
| 230 | mov 0x1, %l1 |
| 231 | sllx %l1, DRAM_ES_DAC, %l0 |
| 232 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed |
| 233 | or %l0, %l3, %l0 ! %l0 has expected value |
| 234 | |
| 235 | verify_dram_ESR1: |
| 236 | cmp %l0, %l6 |
| 237 | !bne %xcc, test_fail |
| 238 | nop |
| 239 | |
| 240 | check_L2_ESR_01: |
| 241 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 242 | add %g5, L2_BANK_ADDR1, %g5 |
| 243 | ldx [%g5], %l6 |
| 244 | |
| 245 | compute_L2_ESR1: |
| 246 | setx 0xfffffffff0000000, %l3, %l0 |
| 247 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits |
| 248 | mov 0x1, %l1 |
| 249 | sllx %l1, L2ES_DAC, %l0 |
| 250 | mov 0x1, %l1 |
| 251 | sllx %l1, L2ES_VEC, %l2 |
| 252 | or %l0, %l2, %l3 |
| 253 | |
| 254 | verify_L2_ESR1: |
| 255 | cmp %l6, %l3 |
| 256 | !bne %xcc, test_fail |
| 257 | nop |
| 258 | |
| 259 | |
| 260 | setx L2EA_PA0, %l2, %l3 |
| 261 | add %l3, L2_BANK_ADDR1, %l3 |
| 262 | check_l2_EAR1: |
| 263 | ldx [%l3], %l4 |
| 264 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 265 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 266 | add %g2, L2_BANK_ADDR1, %g2 |
| 267 | |
| 268 | setx 0xffffffffc0, %l0,%o2 |
| 269 | and %l4, %o2, %l4 |
| 270 | cmp %l4, %g2 |
| 271 | !bne %xcc, test_fail |
| 272 | nop |
| 273 | |
| 274 | check_Corr_err_trap1: |
| 275 | ! Check if a Corrected ECC Error Trap happened |
| 276 | set EXECUTED, %l0 |
| 277 | cmp %o0, %l0 |
| 278 | !bne test_fail |
| 279 | nop |
| 280 | mov TT_Corrected_ECC, %l0 |
| 281 | ! mov TT_SW_Error, %l0 |
| 282 | cmp %o1, %l0 |
| 283 | !bne test_fail |
| 284 | nop |
| 285 | |
| 286 | ba test_pass |
| 287 | nop |
| 288 | |
| 289 | !Code for Thread1 |
| 290 | MCU0_Init: |
| 291 | |
| 292 | |
| 293 | disable_l1: |
| 294 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 295 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 296 | andn %l0, 0x3, %l0 |
| 297 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 298 | |
| 299 | |
| 300 | clear_dram_esr_0: |
| 301 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 302 | setx DRAM_ES_W1C_VALUE, %l0, %l5 |
| 303 | setx DRAM_ERR_STAT_REG0, %l3, %g5 |
| 304 | ! add %g5, MCU_BANK_ADDR0, %g5 |
| 305 | stx %l5, [%g5] |
| 306 | |
| 307 | set_DRAM_error_inject_ch0: |
| 308 | mov 0x2, %l1 ! ECC Mask (1-bit error) |
| 309 | mov 0x1, %l2 |
| 310 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 311 | Or %l1, %l3, %l1 ! Set single shot ; |
| 312 | mov 0x1, %l2 |
| 313 | sllx %l2, DRAM_EI_ENB, %l3 |
| 314 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 315 | setx DRAM_ERR_INJ_REG0, %l3, %g6 |
| 316 | ! add %g6, MCU_BANK_ADDR, %g6 |
| 317 | stx %l1, [%g6] |
| 318 | membar 0x40 |
| 319 | |
| 320 | enable_err_reporting: |
| 321 | setx L2EE_PA0, %l0, %l1 |
| 322 | add %l1, L2_BANK_ADDR0, %l1 |
| 323 | ldx [%l1], %l2 |
| 324 | mov 0x3, %l0 |
| 325 | or %l2, %l0, %l2 |
| 326 | stx %l2, [%l1] |
| 327 | |
| 328 | |
| 329 | ! Write 1 to clear L2 Error status registers |
| 330 | clear_l2_ESR: |
| 331 | setx L2ES_PA0, %l3, %l4 |
| 332 | add %l4, L2_BANK_ADDR0, %l4 |
| 333 | stx %l5, [%l4] |
| 334 | nop |
| 335 | |
| 336 | store_to_L2: |
| 337 | setx TEST_DATA1, %l0, %g5 |
| 338 | |
| 339 | |
| 340 | set_L2_Directly_Mapped_Mode: |
| 341 | setx L2CS_PA0, %l6, %g1 |
| 342 | add %g1, L2_BANK_ADDR0, %g1 |
| 343 | mov 0x2, %l0 |
| 344 | stx %l0, [%g1] |
| 345 | |
| 346 | store_to_L2_way0: |
| 347 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 348 | add %g2, L2_BANK_ADDR0, %g2 |
| 349 | stx %g5, [%g2] |
| 350 | stx %g5, [%g2+8] |
| 351 | membar #Sync |
| 352 | |
| 353 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 354 | write_mcu_channel_0: |
| 355 | setx 0x20210aa00, %l0, %g3 ! bits [21:18] select way |
| 356 | add %g3, L2_BANK_ADDR0, %g3 |
| 357 | stx %g5, [%g3] |
| 358 | stx %g5, [%g3+8] |
| 359 | membar #Sync |
| 360 | |
| 361 | |
| 362 | read_error_address_ch0: |
| 363 | ldx [%g2], %l1 |
| 364 | membar #Sync |
| 365 | ! ldx [%g3], %l2 |
| 366 | ! membar #Sync |
| 367 | |
| 368 | |
| 369 | check_DRAM_ESR_0: |
| 370 | setx DRAM_ERR_STAT_REG0, %l3, %g5 |
| 371 | ! add %g5, MCU_BANK_ADDR0, %g5 |
| 372 | ldx [%g5], %l6 |
| 373 | |
| 374 | compute_dram_ESR: |
| 375 | mov 0x1, %l1 |
| 376 | sllx %l1, DRAM_ES_DAC, %l0 |
| 377 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed |
| 378 | or %l0, %l3, %l0 ! %l0 has expected value |
| 379 | |
| 380 | verify_dram_ESR: |
| 381 | cmp %l0, %l6 |
| 382 | !bne %xcc, test_fail |
| 383 | nop |
| 384 | |
| 385 | check_L2_ESR_0: |
| 386 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 387 | add %g5, L2_BANK_ADDR0, %g5 |
| 388 | ldx [%g5], %l6 |
| 389 | |
| 390 | compute_L2_ESR: |
| 391 | setx 0xfffffffff0000000, %l3, %l0 |
| 392 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits |
| 393 | mov 0x1, %l1 |
| 394 | sllx %l1, L2ES_DAC, %l0 |
| 395 | mov 0x1, %l1 |
| 396 | sllx %l1, L2ES_VEC, %l2 |
| 397 | or %l0, %l2, %l3 |
| 398 | |
| 399 | verify_L2_ESR: |
| 400 | cmp %l6, %l3 |
| 401 | !bne %xcc, test_fail |
| 402 | nop |
| 403 | |
| 404 | |
| 405 | setx L2EA_PA0, %l2, %l3 |
| 406 | add %l3, L2_BANK_ADDR0, %l3 |
| 407 | check_l2_EAR: |
| 408 | ldx [%l3], %l4 |
| 409 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 410 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 411 | add %g2, L2_BANK_ADDR0, %g2 |
| 412 | |
| 413 | setx 0xffffffffc0, %l0,%o2 |
| 414 | and %l4, %o2, %l4 |
| 415 | cmp %l4, %g2 |
| 416 | !bne %xcc, test_fail |
| 417 | nop |
| 418 | |
| 419 | check_Corr_err_trap: |
| 420 | ! Check if a Corrected ECC Error Trap happened |
| 421 | set EXECUTED, %l0 |
| 422 | cmp %o0, %l0 |
| 423 | !bne test_fail |
| 424 | nop |
| 425 | mov TT_Corrected_ECC, %l0 |
| 426 | ! mov TT_SW_Error, %l0 |
| 427 | cmp %o1, %l0 |
| 428 | !bne test_fail |
| 429 | nop |
| 430 | |
| 431 | |
| 432 | ba test_pass |
| 433 | nop |
| 434 | |
| 435 | !Code for Thread2 |
| 436 | MCU2_Init: |
| 437 | |
| 438 | disable_l12: |
| 439 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 440 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 441 | andn %l0, 0x3, %l0 |
| 442 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 443 | |
| 444 | |
| 445 | clear_dram_esr_02: |
| 446 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 447 | setx DRAM_ES_W1C_VALUE, %l0, %l5 |
| 448 | setx DRAM_ERR_STAT_REG2, %l3, %g5 |
| 449 | ! add %g5, MCU_BANK_ADDR, %g5 |
| 450 | stx %l5, [%g5] |
| 451 | |
| 452 | set_DRAM_error_inject_ch02: |
| 453 | mov 0x2, %l1 ! ECC Mask (1-bit error) |
| 454 | mov 0x1, %l2 |
| 455 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 456 | Or %l1, %l3, %l1 ! Set single shot ; |
| 457 | mov 0x1, %l2 |
| 458 | sllx %l2, DRAM_EI_ENB, %l3 |
| 459 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 460 | setx DRAM_ERR_INJ_REG2, %l3, %g6 |
| 461 | ! add %g6, MCU_BANK_ADDR, %g6 |
| 462 | stx %l1, [%g6] |
| 463 | membar 0x40 |
| 464 | |
| 465 | enable_err_reporting2: |
| 466 | setx L2EE_PA0, %l0, %l1 |
| 467 | add %l1, L2_BANK_ADDR2, %l1 |
| 468 | ldx [%l1], %l2 |
| 469 | mov 0x3, %l0 |
| 470 | or %l2, %l0, %l2 |
| 471 | stx %l2, [%l1] |
| 472 | |
| 473 | |
| 474 | ! Write 1 to clear L2 Error status registers |
| 475 | clear_l2_ESR2: |
| 476 | setx L2ES_PA0, %l3, %l4 |
| 477 | add %l4, L2_BANK_ADDR2, %l4 |
| 478 | stx %l5, [%l4] |
| 479 | nop |
| 480 | |
| 481 | store_to_L22: |
| 482 | setx TEST_DATA1, %l0, %g5 |
| 483 | |
| 484 | |
| 485 | set_L2_Directly_Mapped_Mode2: |
| 486 | setx L2CS_PA0, %l6, %g1 |
| 487 | add %g1, L2_BANK_ADDR2, %g1 |
| 488 | mov 0x2, %l0 |
| 489 | stx %l0, [%g1] |
| 490 | |
| 491 | store_to_L2_way02: |
| 492 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 493 | add %g2, L2_BANK_ADDR2, %g2 |
| 494 | stx %g5, [%g2] |
| 495 | stx %g5, [%g2+8] |
| 496 | membar #Sync |
| 497 | |
| 498 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 499 | write_mcu_channel_02: |
| 500 | setx 0x20210aa00, %l0, %g3 ! bits [21:18] select way |
| 501 | add %g3, L2_BANK_ADDR2, %g3 |
| 502 | stx %g5, [%g3] |
| 503 | stx %g5, [%g3+8] |
| 504 | membar #Sync |
| 505 | |
| 506 | |
| 507 | read_error_address_ch02: |
| 508 | ldx [%g2], %l1 |
| 509 | membar #Sync |
| 510 | ! ldx [%g3], %l2 |
| 511 | ! membar #Sync |
| 512 | |
| 513 | |
| 514 | check_DRAM_ESR_02: |
| 515 | setx DRAM_ERR_STAT_REG2, %l3, %g5 |
| 516 | ! add %g5, MCU_BANK_ADDR2, %g5 |
| 517 | ldx [%g5], %l6 |
| 518 | |
| 519 | compute_dram_ESR2: |
| 520 | mov 0x1, %l1 |
| 521 | sllx %l1, DRAM_ES_DAC, %l0 |
| 522 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed |
| 523 | or %l0, %l3, %l0 ! %l0 has expected value |
| 524 | |
| 525 | verify_dram_ESR2: |
| 526 | cmp %l0, %l6 |
| 527 | !bne %xcc, test_fail |
| 528 | nop |
| 529 | |
| 530 | check_L2_ESR_02: |
| 531 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 532 | add %g5, L2_BANK_ADDR2, %g5 |
| 533 | ldx [%g5], %l6 |
| 534 | |
| 535 | compute_L2_ESR2: |
| 536 | setx 0xfffffffff0000000, %l3, %l0 |
| 537 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits |
| 538 | mov 0x1, %l1 |
| 539 | sllx %l1, L2ES_DAC, %l0 |
| 540 | mov 0x1, %l1 |
| 541 | sllx %l1, L2ES_VEC, %l2 |
| 542 | or %l0, %l2, %l3 |
| 543 | |
| 544 | verify_L2_ESR2: |
| 545 | cmp %l6, %l3 |
| 546 | !bne %xcc, test_fail |
| 547 | nop |
| 548 | |
| 549 | |
| 550 | setx L2EA_PA0, %l2, %l3 |
| 551 | add %l3, L2_BANK_ADDR2, %l3 |
| 552 | |
| 553 | check_l2_EAR2: |
| 554 | ldx [%l3], %l4 |
| 555 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 556 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 557 | add %g2, L2_BANK_ADDR2, %g2 |
| 558 | |
| 559 | setx 0xffffffffc0, %l0,%o2 |
| 560 | and %l4, %o2, %l4 |
| 561 | cmp %l4, %g2 |
| 562 | !bne %xcc, test_fail |
| 563 | nop |
| 564 | |
| 565 | check_Corr_err_trap2: |
| 566 | ! Check if a Corrected ECC Error Trap happened |
| 567 | set EXECUTED, %l0 |
| 568 | cmp %o0, %l0 |
| 569 | !bne test_fail |
| 570 | nop |
| 571 | mov TT_Corrected_ECC, %l0 |
| 572 | ! mov TT_SW_Error, %l0 |
| 573 | cmp %o1, %l0 |
| 574 | !bne test_fail |
| 575 | nop |
| 576 | |
| 577 | |
| 578 | ba test_pass |
| 579 | nop |
| 580 | |
| 581 | |
| 582 | |
| 583 | |
| 584 | !Code for Thread3 |
| 585 | MCU3_Init: |
| 586 | |
| 587 | disable_l13: |
| 588 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 589 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 590 | andn %l0, 0x3, %l0 |
| 591 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 592 | |
| 593 | |
| 594 | clear_dram_esr_03: |
| 595 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 596 | setx DRAM_ES_W1C_VALUE, %l0, %l5 |
| 597 | setx DRAM_ERR_STAT_REG3, %l3, %g5 |
| 598 | ! add %g5, MCU_BANK_ADDR3, %g5 |
| 599 | stx %l5, [%g5] |
| 600 | |
| 601 | set_DRAM_error_inject_ch03: |
| 602 | mov 0x2, %l1 ! ECC Mask (1-bit error) |
| 603 | mov 0x1, %l2 |
| 604 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 605 | Or %l1, %l3, %l1 ! Set single shot ; |
| 606 | mov 0x1, %l2 |
| 607 | sllx %l2, DRAM_EI_ENB, %l3 |
| 608 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 609 | setx DRAM_ERR_INJ_REG3, %l3, %g6 |
| 610 | ! add %g6, MCU_BANK_ADDR, %g6 |
| 611 | stx %l1, [%g6] |
| 612 | membar 0x40 |
| 613 | |
| 614 | enable_err_reporting3: |
| 615 | setx L2EE_PA0, %l0, %l1 |
| 616 | add %l1, L2_BANK_ADDR3, %l1 |
| 617 | ldx [%l1], %l2 |
| 618 | mov 0x3, %l0 |
| 619 | or %l2, %l0, %l2 |
| 620 | stx %l2, [%l1] |
| 621 | |
| 622 | |
| 623 | ! Write 1 to clear L2 Error status registers |
| 624 | clear_l2_ESR3: |
| 625 | setx L2ES_PA0, %l3, %l4 |
| 626 | add %l4, L2_BANK_ADDR3, %l4 |
| 627 | stx %l5, [%l4] |
| 628 | nop |
| 629 | |
| 630 | store_to_L23: |
| 631 | setx TEST_DATA1, %l0, %g5 |
| 632 | |
| 633 | |
| 634 | set_L2_Directly_Mapped_Mode3: |
| 635 | setx L2CS_PA0, %l6, %g1 |
| 636 | add %g1, L2_BANK_ADDR3, %g1 |
| 637 | mov 0x2, %l0 |
| 638 | stx %l0, [%g1] |
| 639 | |
| 640 | store_to_L2_way03: |
| 641 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 642 | add %g2, L2_BANK_ADDR3, %g2 |
| 643 | stx %g5, [%g2] |
| 644 | stx %g5, [%g2+8] |
| 645 | membar #Sync |
| 646 | |
| 647 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 648 | write_mcu_channel_03: |
| 649 | setx 0x20210aa00, %l0, %g3 ! bits [21:18] select way |
| 650 | add %g3, L2_BANK_ADDR3, %g3 |
| 651 | stx %g5, [%g3] |
| 652 | stx %g5, [%g3+8] |
| 653 | membar #Sync |
| 654 | |
| 655 | |
| 656 | read_error_address_ch03: |
| 657 | ldx [%g2], %l1 |
| 658 | membar #Sync |
| 659 | ! ldx [%g3], %l2 |
| 660 | ! membar #Sync |
| 661 | |
| 662 | |
| 663 | check_DRAM_ESR_03: |
| 664 | setx DRAM_ERR_STAT_REG3, %l3, %g5 |
| 665 | ! add %g5, MCU_BANK_ADDR3, %g5 |
| 666 | ldx [%g5], %l6 |
| 667 | |
| 668 | compute_dram_ESR3: |
| 669 | mov 0x1, %l1 |
| 670 | sllx %l1, DRAM_ES_DAC, %l0 |
| 671 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed |
| 672 | or %l0, %l3, %l0 ! %l0 has expected value |
| 673 | |
| 674 | verify_dram_ESR3: |
| 675 | cmp %l0, %l6 |
| 676 | !bne %xcc, test_fail |
| 677 | nop |
| 678 | |
| 679 | check_L2_ESR_03: |
| 680 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 681 | add %g5, L2_BANK_ADDR3, %g5 |
| 682 | ldx [%g5], %l6 |
| 683 | |
| 684 | compute_L2_ESR3: |
| 685 | setx 0xfffffffff0000000, %l3, %l0 |
| 686 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits |
| 687 | mov 0x1, %l1 |
| 688 | sllx %l1, L2ES_DAC, %l0 |
| 689 | mov 0x1, %l1 |
| 690 | sllx %l1, L2ES_VEC, %l2 |
| 691 | or %l0, %l2, %l3 |
| 692 | |
| 693 | verify_L2_ESR3: |
| 694 | cmp %l6, %l3 |
| 695 | !bne %xcc, test_fail |
| 696 | nop |
| 697 | |
| 698 | |
| 699 | setx L2EA_PA0, %l2, %l3 |
| 700 | add %l3, L2_BANK_ADDR3, %l3 |
| 701 | |
| 702 | |
| 703 | |
| 704 | check_l2_EAR3: |
| 705 | ldx [%l3], %l4 |
| 706 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 707 | setx 0x20220aa00, %l0, %g2 ! bits [21:18] select way |
| 708 | add %g2, L2_BANK_ADDR3, %g2 |
| 709 | |
| 710 | setx 0xffffffffc0, %l0,%o2 |
| 711 | and %l4, %o2, %l4 |
| 712 | cmp %l4, %g2 |
| 713 | !bne %xcc, test_fail |
| 714 | nop |
| 715 | |
| 716 | check_Corr_err_trap3: |
| 717 | ! Check if a Corrected ECC Error Trap happened |
| 718 | set EXECUTED, %l0 |
| 719 | cmp %o0, %l0 |
| 720 | !bne test_fail |
| 721 | nop |
| 722 | mov TT_Corrected_ECC, %l0 |
| 723 | ! mov TT_SW_Error, %l0 |
| 724 | cmp %o1, %l0 |
| 725 | !bne test_fail |
| 726 | nop |
| 727 | |
| 728 | |
| 729 | ba test_pass |
| 730 | nop |
| 731 | |
| 732 | My_Corrected_ECC_error_trap: |
| 733 | |
| 734 | !My_Recoverable_Sw_error_trap: |
| 735 | ! Signal trap taken |
| 736 | setx EXECUTED, %l0, %o0 |
| 737 | ! save trap type value |
| 738 | rdpr %tt, %o1 |
| 739 | retry |
| 740 | nop |
| 741 | |
| 742 | |
| 743 | /******************************************************* |
| 744 | * Exit code |
| 745 | *******************************************************/ |
| 746 | |
| 747 | test_pass: |
| 748 | ta T_GOOD_TRAP |
| 749 | |
| 750 | |
| 751 | test_fail: |
| 752 | ta T_BAD_TRAP |
| 753 | |
| 754 | |
| 755 | |