| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_err_dram_1b_cont_notrap.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #ifdef MCU0 |
| 42 | #define L2_ENTRY_PA0 0x20200000 |
| 43 | #define L2_ENTRY_PA1 0x21200000 |
| 44 | #define L2_ENTRY_PA2 0x22200000 |
| 45 | #define L2_ENTRY_PA3 0x23200000 |
| 46 | #define L2_ENTRY_PA4 0x24200000 |
| 47 | #define L2_ENTRY_PA5 0x25200000 |
| 48 | #define L2_ENTRY_PA6 0x26200000 |
| 49 | #define L2_ENTRY_PA7 0x27200000 |
| 50 | #define L2_ENTRY_PA8 0x28200000 |
| 51 | #define L2_ENTRY_PA9 0x29200000 |
| 52 | #define L2_ENTRY_PAa 0x2a200000 |
| 53 | #define L2_ENTRY_PAb 0x2b200000 |
| 54 | #define L2_ENTRY_PAc 0x2c200000 |
| 55 | #define L2_ENTRY_PAd 0x2d200000 |
| 56 | #define L2_ENTRY_PAe 0x2e200000 |
| 57 | #define L2_ENTRY_PAf 0x2f200000 |
| 58 | #define L2_ENTRY_PA10 0x30200000 |
| 59 | #define L2_ENTRY_PA11 0x31200000 |
| 60 | #define L2_ENTRY_PA12 0x32200000 |
| 61 | |
| 62 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 63 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 64 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 65 | #define L2_ERR_ADDR_REG 0xAC00000000 |
| 66 | |
| 67 | #define ERROR_ADDR 0x20200000 |
| 68 | #endif |
| 69 | |
| 70 | |
| 71 | #ifdef MCU1 |
| 72 | #define L2_ENTRY_PA0 0x20200080 |
| 73 | #define L2_ENTRY_PA1 0x21200080 |
| 74 | #define L2_ENTRY_PA2 0x22200080 |
| 75 | #define L2_ENTRY_PA3 0x23200080 |
| 76 | #define L2_ENTRY_PA4 0x24200080 |
| 77 | #define L2_ENTRY_PA5 0x25200080 |
| 78 | #define L2_ENTRY_PA6 0x26200080 |
| 79 | #define L2_ENTRY_PA7 0x27200080 |
| 80 | #define L2_ENTRY_PA8 0x28200080 |
| 81 | #define L2_ENTRY_PA9 0x29200080 |
| 82 | #define L2_ENTRY_PAa 0x2a200080 |
| 83 | #define L2_ENTRY_PAb 0x2b200080 |
| 84 | #define L2_ENTRY_PAc 0x2c200080 |
| 85 | #define L2_ENTRY_PAd 0x2d200080 |
| 86 | #define L2_ENTRY_PAe 0x2e200080 |
| 87 | #define L2_ENTRY_PAf 0x2f200080 |
| 88 | #define L2_ENTRY_PA10 0x30200080 |
| 89 | #define L2_ENTRY_PA11 0x31200080 |
| 90 | #define L2_ENTRY_PA12 0x32200080 |
| 91 | |
| 92 | #define DRAM_ERR_INJ_REG 0x8400001290 |
| 93 | #define DRAM_ERR_STAT_REG 0x8400001280 |
| 94 | #define L2_ERR_STAT_REG 0xAB00000080 |
| 95 | #define L2_ERR_ADDR_REG 0xAC00000080 |
| 96 | |
| 97 | #define ERROR_ADDR 0x20200080 |
| 98 | |
| 99 | #endif |
| 100 | |
| 101 | |
| 102 | #ifdef MCU2 |
| 103 | #define L2_ENTRY_PA0 0x20200100 |
| 104 | #define L2_ENTRY_PA1 0x21200100 |
| 105 | #define L2_ENTRY_PA2 0x22200100 |
| 106 | #define L2_ENTRY_PA3 0x23200100 |
| 107 | #define L2_ENTRY_PA4 0x24200100 |
| 108 | #define L2_ENTRY_PA5 0x25200100 |
| 109 | #define L2_ENTRY_PA6 0x26200100 |
| 110 | #define L2_ENTRY_PA7 0x27200100 |
| 111 | #define L2_ENTRY_PA8 0x28200100 |
| 112 | #define L2_ENTRY_PA9 0x29200100 |
| 113 | #define L2_ENTRY_PAa 0x2a200100 |
| 114 | #define L2_ENTRY_PAb 0x2b200100 |
| 115 | #define L2_ENTRY_PAc 0x2c200100 |
| 116 | #define L2_ENTRY_PAd 0x2d200100 |
| 117 | #define L2_ENTRY_PAe 0x2e200100 |
| 118 | #define L2_ENTRY_PAf 0x2f200100 |
| 119 | #define L2_ENTRY_PA10 0x30200100 |
| 120 | #define L2_ENTRY_PA11 0x31200100 |
| 121 | #define L2_ENTRY_PA12 0x32200100 |
| 122 | |
| 123 | #define DRAM_ERR_INJ_REG 0x8400002290 |
| 124 | #define DRAM_ERR_STAT_REG 0x8400002280 |
| 125 | #define L2_ERR_STAT_REG 0xAB00000100 |
| 126 | #define L2_ERR_ADDR_REG 0xAC00000100 |
| 127 | |
| 128 | #define ERROR_ADDR 0x20200100 |
| 129 | |
| 130 | #endif |
| 131 | |
| 132 | #ifdef MCU3 |
| 133 | #define L2_ENTRY_PA0 0x20200180 |
| 134 | #define L2_ENTRY_PA1 0x21200180 |
| 135 | #define L2_ENTRY_PA2 0x22200180 |
| 136 | #define L2_ENTRY_PA3 0x23200180 |
| 137 | #define L2_ENTRY_PA4 0x24200180 |
| 138 | #define L2_ENTRY_PA5 0x25200180 |
| 139 | #define L2_ENTRY_PA6 0x26200180 |
| 140 | #define L2_ENTRY_PA7 0x27200180 |
| 141 | #define L2_ENTRY_PA8 0x28200180 |
| 142 | #define L2_ENTRY_PA9 0x29200180 |
| 143 | #define L2_ENTRY_PAa 0x2a200180 |
| 144 | #define L2_ENTRY_PAb 0x2b200180 |
| 145 | #define L2_ENTRY_PAc 0x2c200180 |
| 146 | #define L2_ENTRY_PAd 0x2d200180 |
| 147 | #define L2_ENTRY_PAe 0x2e200180 |
| 148 | #define L2_ENTRY_PAf 0x2f200180 |
| 149 | #define L2_ENTRY_PA10 0x30200180 |
| 150 | #define L2_ENTRY_PA11 0x31200180 |
| 151 | #define L2_ENTRY_PA12 0x32200180 |
| 152 | |
| 153 | #define DRAM_ERR_INJ_REG 0x8400003290 |
| 154 | #define DRAM_ERR_STAT_REG 0x8400003280 |
| 155 | #define L2_ERR_STAT_REG 0xAB00000180 |
| 156 | #define L2_ERR_ADDR_REG 0xAC00000180 |
| 157 | |
| 158 | #define ERROR_ADDR 0x20200180 |
| 159 | |
| 160 | #endif |
| 161 | |
| 162 | |
| 163 | #define TEST_DATA0 0x1000100081c3e008 |
| 164 | #define TEST_DATA1 0x2000200081c3e008 |
| 165 | #define TEST_DATA2 0x3000300081c3e008 |
| 166 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 167 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 168 | |
| 169 | #include "hboot.s" |
| 170 | #include "asi_s.h" |
| 171 | #include "err_defines.h" |
| 172 | |
| 173 | |
| 174 | .text |
| 175 | .global main |
| 176 | |
| 177 | |
| 178 | main: |
| 179 | ta T_CHANGE_HPRIV |
| 180 | |
| 181 | clr %o7 |
| 182 | |
| 183 | #ifdef RUN_TH1 |
| 184 | mov 0x1, %o7 |
| 185 | #endif |
| 186 | #ifdef RUN_TH2 |
| 187 | mov 0x2, %o7 |
| 188 | #endif |
| 189 | #ifdef RUN_TH3 |
| 190 | mov 0x3, %o7 |
| 191 | #endif |
| 192 | |
| 193 | ta %icc, T_RD_THID |
| 194 | cmp %o1, %o7 |
| 195 | bne test_pass |
| 196 | nop |
| 197 | |
| 198 | |
| 199 | clear_dram_esr_0: |
| 200 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 201 | setx DRAM_ES_W1C_VALUE, %l0, %g4 |
| 202 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 203 | stx %g4, [%g5] |
| 204 | |
| 205 | clear_l2_ESR: |
| 206 | ! Write 1 to clear L2 Error status registers |
| 207 | setx L2_ERR_STAT_REG, %l3, %l4 |
| 208 | setx L2_ES_W1C_VALUE, %l0, %l1 |
| 209 | stx %l1, [%l4] |
| 210 | nop |
| 211 | |
| 212 | read_l2_ESR: |
| 213 | ldx [%l4], %i6 |
| 214 | |
| 215 | |
| 216 | store_first_8_bytes: |
| 217 | setx L2_ENTRY_PA0, %l0, %g1 |
| 218 | setx TEST_DATA0, %l0, %g3 |
| 219 | stx %g3, [%g1] |
| 220 | |
| 221 | set_DRAM_error_inject_ch0: |
| 222 | mov 0x2, %l1 ! ECC Mask (1-bit error) |
| 223 | mov 0x0, %l2 ! contineous ; |
| 224 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 225 | Or %l1, %l3, %l1 ! Set single shot ; : cont |
| 226 | mov 0x1, %l2 |
| 227 | sllx %l2, DRAM_EI_ENB, %l3 |
| 228 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 229 | setx DRAM_ERR_INJ_REG, %l3, %g6 |
| 230 | stx %l1, [%g6] |
| 231 | membar 0x40 |
| 232 | |
| 233 | |
| 234 | write_mcu_channel_0: |
| 235 | setx L2_ENTRY_PA0, %l0, %g1 |
| 236 | setx TEST_DATA1, %l2, %l1 |
| 237 | stx %l1, [%g1] |
| 238 | setx L2_ENTRY_PA1, %l0, %g1 |
| 239 | setx TEST_DATA1, %l2, %l1 |
| 240 | stx %l1, [%g1] |
| 241 | setx L2_ENTRY_PA2, %l0, %g1 |
| 242 | setx TEST_DATA1, %l2, %l1 |
| 243 | stx %l1, [%g1] |
| 244 | setx L2_ENTRY_PA3, %l0, %g1 |
| 245 | setx TEST_DATA1, %l2, %l1 |
| 246 | stx %l1, [%g1] |
| 247 | setx L2_ENTRY_PA4, %l0, %g1 |
| 248 | setx TEST_DATA1, %l2, %l1 |
| 249 | stx %l1, [%g1] |
| 250 | setx L2_ENTRY_PA5, %l0, %g1 |
| 251 | setx TEST_DATA1, %l2, %l1 |
| 252 | stx %l1, [%g1] |
| 253 | setx L2_ENTRY_PA6, %l0, %g1 |
| 254 | setx TEST_DATA1, %l2, %l1 |
| 255 | stx %l1, [%g1] |
| 256 | setx L2_ENTRY_PA7, %l0, %g1 |
| 257 | setx TEST_DATA1, %l2, %l1 |
| 258 | stx %l1, [%g1] |
| 259 | setx L2_ENTRY_PA8, %l0, %g1 |
| 260 | setx TEST_DATA1, %l2, %l1 |
| 261 | stx %l1, [%g1] |
| 262 | setx L2_ENTRY_PA9, %l0, %g1 |
| 263 | setx TEST_DATA1, %l2, %l1 |
| 264 | stx %l1, [%g1] |
| 265 | setx L2_ENTRY_PAa, %l0, %g1 |
| 266 | setx TEST_DATA1, %l2, %l1 |
| 267 | stx %l1, [%g1] |
| 268 | setx L2_ENTRY_PAb, %l0, %g1 |
| 269 | setx TEST_DATA1, %l2, %l1 |
| 270 | stx %l1, [%g1] |
| 271 | setx L2_ENTRY_PAc, %l0, %g1 |
| 272 | setx TEST_DATA1, %l2, %l1 |
| 273 | stx %l1, [%g1] |
| 274 | setx L2_ENTRY_PAd, %l0, %g1 |
| 275 | setx TEST_DATA1, %l2, %l1 |
| 276 | stx %l1, [%g1] |
| 277 | setx L2_ENTRY_PAe, %l0, %g1 |
| 278 | setx TEST_DATA1, %l2, %l1 |
| 279 | stx %l1, [%g1] |
| 280 | setx L2_ENTRY_PAf, %l0, %g1 |
| 281 | setx TEST_DATA1, %l2, %l1 |
| 282 | stx %l1, [%g1] |
| 283 | setx L2_ENTRY_PA10, %l0, %g1 |
| 284 | setx TEST_DATA1, %l2, %l1 |
| 285 | stx %l1, [%g1] |
| 286 | membar 0x40 |
| 287 | |
| 288 | read_error_address_ch0: |
| 289 | setx L2_ENTRY_PA0, %l0, %g1 |
| 290 | ldx [%g1], %l1 |
| 291 | |
| 292 | check_DRAM_ESR_0: |
| 293 | mov 0x1, %l1 |
| 294 | sllx %l1, DRAM_ES_DAC, %l0 |
| 295 | sllx %l1, DRAM_ES_MEC, %l3 |
| 296 | or %l0, %l3, %l4 |
| 297 | |
| 298 | set 0x2000, %l3 !16-bit Syndrome- for SECC, it's the mask nibble-reversed |
| 299 | or %l4, %l3, %l0 !%l0 has expected value |
| 300 | |
| 301 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 302 | ldx [%g5], %l1 |
| 303 | cmp %l0, %l1 |
| 304 | bne %xcc, test_fail |
| 305 | nop |
| 306 | |
| 307 | check_L2_ESR_0: |
| 308 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 309 | ldx [%g5], %l6 |
| 310 | |
| 311 | setx 0xfffffffff0000000, %l3, %l0 |
| 312 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits |
| 313 | |
| 314 | |
| 315 | mov 0x1, %l1 |
| 316 | sllx %l1, L2ES_DAC, %l0 |
| 317 | mov 0x1, %l1 |
| 318 | sllx %l1, L2ES_VEC, %l2 |
| 319 | or %l0, %l2, %l3 |
| 320 | |
| 321 | ! cmp %l5, %l3 |
| 322 | ! bne %xcc, test_fail |
| 323 | ! nop |
| 324 | |
| 325 | ch_L2_addr_ch0: |
| 326 | setx L2_ERR_ADDR_REG, %l3, %g5 |
| 327 | ldx [%g5], %l1 |
| 328 | set ERROR_ADDR, %l5 |
| 329 | ! cmp %l5, %l1 |
| 330 | ! bne %xcc, test_fail |
| 331 | ! nop |
| 332 | |
| 333 | |
| 334 | ba test_pass |
| 335 | nop |
| 336 | |
| 337 | /******************************************************* |
| 338 | * Exit code |
| 339 | *******************************************************/ |
| 340 | |
| 341 | test_pass: |
| 342 | ta T_GOOD_TRAP |
| 343 | |
| 344 | |
| 345 | test_fail: |
| 346 | ta T_BAD_TRAP |
| 347 | |
| 348 | |
| 349 | |