| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: ncu_ios.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | |
| 42 | #define FFLP_CONFIG 0x00100 |
| 43 | #define FZC_FFLP_BASE_OFFSET 0x020000 |
| 44 | #define FZC_FFLP_BASE_ADDRESS 0x380000 |
| 45 | |
| 46 | #include "hboot.s" |
| 47 | !#include "asi_s.h" |
| 48 | |
| 49 | .text |
| 50 | .global main |
| 51 | |
| 52 | |
| 53 | main: |
| 54 | ta T_CHANGE_HPRIV |
| 55 | |
| 56 | get_th_id: |
| 57 | ta %icc, T_RD_THID |
| 58 | |
| 59 | // cmp %o1,0x0 |
| 60 | // bne test_pass |
| 61 | nop |
| 62 | |
| 63 | acc_ssi_timeout: |
| 64 | !Write then read data of INT_VEC_REG of NCU |
| 65 | setx 0x000000ff00010088,%g7,%g1 |
| 66 | setx ssi_timeout, %g7,%g2 |
| 67 | |
| 68 | ldx [%g2],%g4 |
| 69 | stx %g4,[%g1] |
| 70 | |
| 71 | ldx [%g1], %g5 |
| 72 | cmp %g4, %g5 |
| 73 | |
| 74 | bne %xcc, test_fail |
| 75 | |
| 76 | nop |
| 77 | |
| 78 | |
| 79 | acc_debug_cnt_in_tcu: |
| 80 | !Write then read data of DEBUG counter enbalbe REG of TCU block |
| 81 | setx 0x00850000f8, %g7,%g1 |
| 82 | setx debug_cnt_en,%g7,%g2 |
| 83 | |
| 84 | ldx [%g2],%g4 |
| 85 | stx %g4,[%g1] |
| 86 | |
| 87 | ldx [%g1], %g5 |
| 88 | ! cmp %g4, %g5 |
| 89 | |
| 90 | ! bne %xcc, test_fail |
| 91 | |
| 92 | nop |
| 93 | |
| 94 | |
| 95 | |
| 96 | acc_int_vec_in_ncu: |
| 97 | !Write then read data of INT_VEC_REG of NCU |
| 98 | setx 0x0000008000000a00,%g7,%g1 |
| 99 | setx int_vec_data,%g7,%g2 |
| 100 | |
| 101 | ldx [%g2],%g4 |
| 102 | stx %g4,[%g1] |
| 103 | |
| 104 | ldx [%g1], %g5 |
| 105 | cmp %g4, %g5 |
| 106 | |
| 107 | bne %xcc, test_fail |
| 108 | |
| 109 | nop |
| 110 | |
| 111 | acc_reset_fee_in_rst: |
| 112 | !Write then read data of RESET_FEE of RST block |
| 113 | setx 0x0000008900000820,%g7,%g1 |
| 114 | setx reset_fee,%g7,%g2 |
| 115 | |
| 116 | ldx [%g2],%g4 |
| 117 | stx %g4,[%g1] |
| 118 | |
| 119 | ldx [%g1], %g5 |
| 120 | |
| 121 | cmp %g4, %g5 |
| 122 | |
| 123 | bne %xcc, test_fail |
| 124 | |
| 125 | nop |
| 126 | |
| 127 | acc_serdes_test_cfg_in_mcu0: |
| 128 | !Write then read data of SERDES Test Configuration Bus Register of MCU0 block |
| 129 | setx 0x00000084000008e0,%g7,%g1 |
| 130 | setx mcu_cfg_data,%g7,%g2 |
| 131 | |
| 132 | ldx [%g2],%g4 |
| 133 | stx %g4,[%g1] |
| 134 | |
| 135 | ldx [%g1], %g5 |
| 136 | |
| 137 | cmp %g4, %g5 |
| 138 | |
| 139 | bne %xcc, test_fail |
| 140 | |
| 141 | nop |
| 142 | acc_serdes_test_cfg_in_mcu1: |
| 143 | !Write then read data of SERDES Test Configuration Bus Register of MCU1 block |
| 144 | setx 0x00000084000018e0,%g7,%g1 |
| 145 | setx mcu_cfg_data,%g7,%g2 |
| 146 | |
| 147 | ldx [%g2],%g4 |
| 148 | stx %g4,[%g1] |
| 149 | |
| 150 | ldx [%g1], %g5 |
| 151 | |
| 152 | cmp %g4, %g5 |
| 153 | |
| 154 | bne %xcc, test_fail |
| 155 | |
| 156 | nop |
| 157 | acc_serdes_test_cfg_in_mcu2: |
| 158 | !Write then read data of SERDES Test Configuration Bus Register of MCU2 block |
| 159 | setx 0x00000084000028e0,%g7,%g1 |
| 160 | setx mcu_cfg_data,%g7,%g2 |
| 161 | |
| 162 | ldx [%g2],%g4 |
| 163 | stx %g4,[%g1] |
| 164 | |
| 165 | ldx [%g1], %g5 |
| 166 | cmp %g4, %g5 |
| 167 | |
| 168 | bne %xcc, test_fail |
| 169 | |
| 170 | |
| 171 | nop |
| 172 | acc_serdes_test_cfg_in_mcu3: |
| 173 | !Write then read data of SERDES Test Configuration Bus Register of MCU3 block |
| 174 | setx 0x00000084000038e0,%g7,%g1 |
| 175 | setx mcu_cfg_data,%g7,%g2 |
| 176 | |
| 177 | ldx [%g2],%g4 |
| 178 | stx %g4,[%g1] |
| 179 | |
| 180 | ldx [%g1], %g5 |
| 181 | cmp %g4, %g5 |
| 182 | |
| 183 | bne %xcc, test_fail |
| 184 | |
| 185 | nop |
| 186 | acc_pll_ctl_in_ccu: |
| 187 | !Write then read data of PLL_CTL Register of CCU block |
| 188 | setx 0x0000008300000000,%g7,%g1 |
| 189 | setx pll_ctl_data,%g7,%g2 |
| 190 | |
| 191 | ldx [%g2],%g4 |
| 192 | stx %g4,[%g1] |
| 193 | |
| 194 | ldx [%g1], %g5 |
| 195 | cmp %g4, %g5 |
| 196 | |
| 197 | bne %xcc, test_fail |
| 198 | |
| 199 | nop |
| 200 | |
| 201 | #ifndef VECTOR |
| 202 | acc_config_in_niu: |
| 203 | !Write then read data of PLL_CTL Register of NIU block |
| 204 | setx config,%g7,%g1 |
| 205 | setx config_data,%g7,%g2 |
| 206 | |
| 207 | ldx [%g2],%g4 |
| 208 | stxa %g4,[%g1]ASI_PRIMARY_LITTLE |
| 209 | nop |
| 210 | nop |
| 211 | |
| 212 | ldxa [%g1]ASI_PRIMARY_LITTLE, %g5 |
| 213 | cmp %g4, %g5 |
| 214 | |
| 215 | bne %xcc, test_fail |
| 216 | |
| 217 | nop |
| 218 | #endif |
| 219 | |
| 220 | acc_int_en_in_dmu: |
| 221 | !Write then read data of INT_EN Register of DMUCSR block |
| 222 | setx 0x8800631008, %g7,%g1 |
| 223 | setx int_en_data,%g7,%g2 |
| 224 | |
| 225 | ldx [%g2],%g4 |
| 226 | stx %g4,[%g1] |
| 227 | |
| 228 | ldx [%g1], %g5 |
| 229 | cmp %g4, %g5 |
| 230 | |
| 231 | bne %xcc, test_fail |
| 232 | |
| 233 | nop |
| 234 | |
| 235 | |
| 236 | |
| 237 | acc_debug_port_cfg_in_dbug1: |
| 238 | !Write then read data of DEBUG_PORT_CONFIG of DBG1 block |
| 239 | setx 0x8600000000, %g7,%g1 |
| 240 | setx dbg1_cfg,%g7,%g2 |
| 241 | |
| 242 | ldx [%g2],%g4 |
| 243 | stx %g4,[%g1] |
| 244 | |
| 245 | ldx [%g1], %g5 |
| 246 | #ifndef VECTOR |
| 247 | cmp %g4, %g5 |
| 248 | |
| 249 | bne %xcc, test_fail |
| 250 | #endif |
| 251 | nop |
| 252 | |
| 253 | |
| 254 | |
| 255 | ****************************************************** |
| 256 | * Exit code |
| 257 | *******************************************************/ |
| 258 | |
| 259 | test_pass: |
| 260 | EXIT_GOOD |
| 261 | |
| 262 | test_fail: |
| 263 | EXIT_BAD |
| 264 | |
| 265 | |
| 266 | .data |
| 267 | .align 0x100 |
| 268 | int_vec_data: |
| 269 | .xword 0x000000000000002a |
| 270 | .xword 0x000000000000003f |
| 271 | .xword 0x0000000000000015 |
| 272 | .xword 0x0000000000000001 |
| 273 | .xword 0x0000000000000002 |
| 274 | .xword 0x0000000000000004 |
| 275 | .xword 0x0000000000000008 |
| 276 | .xword 0x0000000000000010 |
| 277 | .xword 0x0000000000000020 |
| 278 | |
| 279 | |
| 280 | .align 0x100 |
| 281 | reset_fee: |
| 282 | .xword 0x000000000000ff00 |
| 283 | .xword 0x000000000000aa00 |
| 284 | .xword 0x0000000000005500 |
| 285 | .xword 0x0000000000000000 |
| 286 | .xword 0x0000000000008800 |
| 287 | .xword 0x0000000000002200 |
| 288 | |
| 289 | .align 0x100 |
| 290 | mcu_cfg_data: |
| 291 | .xword 0x000000000000ff00 |
| 292 | .xword 0x000000000000aa00 |
| 293 | .xword 0x0000000000005500 |
| 294 | .xword 0x0000000000000000 |
| 295 | .xword 0x0000000000000000 |
| 296 | .xword 0x0000000000000000 |
| 297 | |
| 298 | .align 0x100 |
| 299 | ssi_timeout: |
| 300 | .xword 0x0000000000ffffff |
| 301 | .xword 0x0000000000aaaaaa |
| 302 | .xword 0x0000000000555555 |
| 303 | .xword 0x000000000056789a |
| 304 | .xword 0x0000000000df0123 |
| 305 | .xword 0x0000000000789abc |
| 306 | |
| 307 | .align 0x100 |
| 308 | pll_ctl_data: |
| 309 | .xword 0x0000001fffffffff |
| 310 | .xword 0x0000001aaaaaaaaa |
| 311 | .xword 0x0000000555555555 |
| 312 | .xword 0x000000123456789a |
| 313 | .xword 0x0000000bcedf0123 |
| 314 | .xword 0x0000001456789abc |
| 315 | |
| 316 | .align 0x100 |
| 317 | int_en_data: |
| 318 | .xword 0x0000000000000fff |
| 319 | .xword 0x0000000000000aaa |
| 320 | .xword 0x0000000000000555 |
| 321 | .xword 0x000000000000089a |
| 322 | .xword 0x0000000000000123 |
| 323 | .xword 0x0000000000000abc |
| 324 | |
| 325 | .align 0x100 |
| 326 | config_data: |
| 327 | .xword 0x0000000000ffffff |
| 328 | .xword 0x0000000000aaaaaa |
| 329 | .xword 0x0000000000555555 |
| 330 | .xword 0x000000000056789a |
| 331 | .xword 0x0000000000df0123 |
| 332 | .xword 0x0000000000789abc |
| 333 | |
| 334 | |
| 335 | .align 0x100 |
| 336 | wdata: |
| 337 | .xword 0xffffffffffffffff |
| 338 | .xword 0xaaaaaaaaaaaaaaaa |
| 339 | .xword 0x0000000000000000 |
| 340 | .xword 0x5555555555555555 |
| 341 | .xword 0x0123456789abcdef |
| 342 | |
| 343 | .align 0x100 |
| 344 | dbg1_cfg: |
| 345 | .xword 0x00000000000000ff |
| 346 | .xword 0x00000000000000aa |
| 347 | .xword 0x0000000000000000 |
| 348 | .xword 0x0000000000000055 |
| 349 | |
| 350 | .align 0x100 |
| 351 | debug_cnt_en: |
| 352 | .xword 0x000000000000000f |
| 353 | .xword 0x0000000000000000 |
| 354 | .xword 0x000000000000000a |
| 355 | .xword 0x0000000000000005 |
| 356 | .xword 0x0000000000000002 |
| 357 | .xword 0x0000000000000004 |
| 358 | .align 0x100 |
| 359 | bit_1_data: |
| 360 | .xword 0x0000000000000001 |
| 361 | .xword 0x0000000000000000 |
| 362 | .xword 0x0000000000000001 |
| 363 | .xword 0x0000000000000000 |
| 364 | |
| 365 | busy_data: |
| 366 | .xword 0x0000000000000040 |
| 367 | .xword 0x0000000000000000 |
| 368 | .xword 0x0000000000000040 |
| 369 | .xword 0x0000000000000000 |
| 370 | |
| 371 | .align 0x100 |
| 372 | data_xword: |
| 373 | .xword 0x000000faaa000000 |
| 374 | .xword 0x000000fcad000000 |
| 375 | .xword 0x000000f555000000 |
| 376 | .xword 0x000000fabc000000 |
| 377 | |
| 378 | .end |
| 379 | |