| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: interrupt_INT_VEC_DIS_all.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define H_HT0_Interrupt_0x60 |
| 42 | #define My_HT0_Interrupt_0x60 \ |
| 43 | call my_trap_code; \ |
| 44 | nop; \ |
| 45 | retry; \ |
| 46 | nop; |
| 47 | |
| 48 | #include "hboot.s" |
| 49 | #include "ncu_defines.h" |
| 50 | #include "asi_s.h" |
| 51 | #include "cmp_macros.h" |
| 52 | |
| 53 | |
| 54 | /************************************************************************ |
| 55 | Test case code start |
| 56 | ************************************************************************/ |
| 57 | |
| 58 | .text |
| 59 | .global main |
| 60 | |
| 61 | main: |
| 62 | ! Switch to hypervisor mode. |
| 63 | |
| 64 | ta T_CHANGE_HPRIV |
| 65 | nop |
| 66 | |
| 67 | wr %g0, INT_VEC_DIS, %asi |
| 68 | |
| 69 | ! Initialize the global registers. |
| 70 | mov %g0, %g1 |
| 71 | mov %g0, %g2 |
| 72 | mov %g0, %g3 |
| 73 | mov %g0, %g4 |
| 74 | mov %g0, %g5 |
| 75 | mov %g0, %g6 |
| 76 | mov %g0, %g7 |
| 77 | |
| 78 | ta T_RD_THID |
| 79 | mov %o1, %g6 ! %o1, %g6 = thread ID |
| 80 | set 8, %l7 |
| 81 | umul %g6, %l7, %l7 |
| 82 | setx user_data_start, %g1, %g3 |
| 83 | add %l7, %g3, %g7 ! %g7 = pointer to thread's data area |
| 84 | |
| 85 | cmp %g6, 0x0 |
| 86 | be main_t0 ! branch if tread 0 |
| 87 | nop |
| 88 | ba main_t1_to_t63 ! branch if not thread 0 |
| 89 | nop |
| 90 | |
| 91 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 92 | ! |
| 93 | ! Thread 0 Start Here |
| 94 | ! |
| 95 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 96 | |
| 97 | ! Sync up all the treads. |
| 98 | |
| 99 | main_t0: |
| 100 | #ifndef PORTABLE_CORE |
| 101 | SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 ) |
| 102 | |
| 103 | ! For each of the 64 threads generate an interrupt to that thread |
| 104 | |
| 105 | mov %g0, %l7 ! destination thread number |
| 106 | |
| 107 | t0_send_loop_top: |
| 108 | sllx %l7, 8, %l6 ! send interrupt with vector number |
| 109 | or %l6, %l7, %l6 ! set to destination thread number |
| 110 | stxa %l6, [%g0]%asi |
| 111 | membar #Sync |
| 112 | |
| 113 | cmp %l7, 63 |
| 114 | blt t0_send_loop_top |
| 115 | add %l7, 1, %l7 ! increment destination thread number |
| 116 | |
| 117 | ! Wait until interrupt occurs in this thread, 0. |
| 118 | t0_1: |
| 119 | set 4000, %l4 ! l4 = timeout counter |
| 120 | mov %g7, %l2 ! l2 = interrupt count |
| 121 | |
| 122 | t0_wait_loop_top: |
| 123 | cmp %l4, 0 |
| 124 | be test_failed ! branch if no interrupt occured |
| 125 | add %l4, -1, %l4 ! decrement wait count |
| 126 | |
| 127 | ld [%l2], %l1 |
| 128 | cmp %l1, 1 |
| 129 | bne t0_wait_loop_top |
| 130 | nop |
| 131 | |
| 132 | ! Done |
| 133 | t0_2: |
| 134 | ba test_passed |
| 135 | nop |
| 136 | #else |
| 137 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 138 | ! |
| 139 | ! Core portable version for thread 0 |
| 140 | ! Needs run arg -midas_args=-DSYNC_THREADS |
| 141 | ! |
| 142 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 143 | |
| 144 | ! Generate an interrupt to each thread in this core |
| 145 | |
| 146 | ldxa [%g0]ASI_INTR_ID, %l7 ! get full thread ID |
| 147 | |
| 148 | t0_send_loop_top: |
| 149 | sllx %l7, 8, %l6 ! send interrupt with vector number |
| 150 | or %l6, %l7, %l6 ! set to destination thread number |
| 151 | stxa %l6, [%g0]%asi |
| 152 | membar #Sync |
| 153 | |
| 154 | and %l7, 7, %l5 |
| 155 | cmp %l5, 7 |
| 156 | blt t0_send_loop_top |
| 157 | add %l7, 1, %l7 ! increment destination thread number |
| 158 | |
| 159 | ! Wait until interrupt occurs in this thread, 0. |
| 160 | t0_1: |
| 161 | set 4000, %l4 ! l4 = timeout counter |
| 162 | mov %g7, %l2 ! l2 = interrupt count |
| 163 | |
| 164 | t0_wait_loop_top: |
| 165 | cmp %l4, 0 |
| 166 | be test_failed ! branch if no interrupt occured |
| 167 | add %l4, -1, %l4 ! decrement wait count |
| 168 | |
| 169 | ld [%l2], %l1 |
| 170 | cmp %l1, 1 |
| 171 | bne t0_wait_loop_top |
| 172 | nop |
| 173 | |
| 174 | ! Done |
| 175 | t0_2: |
| 176 | ba test_passed |
| 177 | nop |
| 178 | #endif |
| 179 | |
| 180 | |
| 181 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 182 | ! |
| 183 | ! All Threads Except 0 Start Here |
| 184 | ! |
| 185 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 186 | |
| 187 | main_t1_to_t63: |
| 188 | #ifndef PORTABLE_CORE |
| 189 | ! Sync up all the treads. |
| 190 | |
| 191 | SYNC_THREAD_OTHER( %g6,%g1,%g2 ) |
| 192 | #endif |
| 193 | |
| 194 | ! Wait for interrupt to arrive to this thread. |
| 195 | |
| 196 | setx 8000, %i6, %i5 ! i5 = timeout counter |
| 197 | mov %g7, %i2 ! i2 = interrupt count address |
| 198 | |
| 199 | wait_loop_top: |
| 200 | cmp %i5, 0 |
| 201 | be test_failed ! branch if no interrupt occured |
| 202 | add %i5, -1, %i5 |
| 203 | |
| 204 | ld [%i2], %i1 |
| 205 | cmp %i1, 1 |
| 206 | bne wait_loop_top |
| 207 | nop |
| 208 | |
| 209 | ! Done |
| 210 | finished: |
| 211 | ba test_passed |
| 212 | nop |
| 213 | |
| 214 | /********************************************************************** |
| 215 | Interrupt trap handler. Same interrupt handler for all threads. |
| 216 | **********************************************************************/ |
| 217 | |
| 218 | .global my_trap_code |
| 219 | |
| 220 | my_trap_code: |
| 221 | |
| 222 | ! Get the thread ID & find data area |
| 223 | |
| 224 | #ifndef PORTABLE_CORE |
| 225 | ta T_RD_THID ! %o1 = thread id |
| 226 | #else |
| 227 | ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID |
| 228 | #endif |
| 229 | set 8, %l0 |
| 230 | umul %o1, %l0, %l1 |
| 231 | setx user_data_start, %l2, %l3 |
| 232 | add %l3, %l1, %l6 |
| 233 | |
| 234 | ! Increment the interrupt count |
| 235 | trap1: |
| 236 | ld [%l6], %g5 |
| 237 | add %g5, 1, %g5 |
| 238 | st %g5, [%l6] |
| 239 | membar #Sync |
| 240 | |
| 241 | ! Check the core interrupt receive and incoming vector registers. |
| 242 | trap2: |
| 243 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 |
| 244 | set 1, %g1 |
| 245 | #ifndef PORTABLE_CORE |
| 246 | sllx %g1, %o1, %g1 |
| 247 | #else |
| 248 | sllx %g1, %o2, %g1 |
| 249 | #endif |
| 250 | cmp %g4, %g1 ! vector bit # should = thread ID |
| 251 | bne test_failed |
| 252 | nop |
| 253 | |
| 254 | ! Clear the interrupt |
| 255 | trap3: |
| 256 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 |
| 257 | |
| 258 | #ifndef PORTABLE_CORE |
| 259 | cmp %g3, %o1 ! vector # should = thread ID |
| 260 | #else |
| 261 | cmp %g3, %o2 ! vector # should = thread ID |
| 262 | #endif |
| 263 | bne test_failed |
| 264 | nop |
| 265 | trap4: |
| 266 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 |
| 267 | cmp %g4, 0 ! now should be 0 |
| 268 | bne test_failed |
| 269 | nop |
| 270 | trap5: |
| 271 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 |
| 272 | cmp %g3, 0x0 ! should also now be 0 |
| 273 | bne test_failed |
| 274 | nop |
| 275 | trap6: |
| 276 | jmpl %o7+0x8, %g0 |
| 277 | nop |
| 278 | |
| 279 | |
| 280 | test_passed: |
| 281 | EXIT_GOOD |
| 282 | |
| 283 | test_failed: |
| 284 | EXIT_BAD |
| 285 | |
| 286 | |
| 287 | /************************************************************************ |
| 288 | Test case data start |
| 289 | ************************************************************************/ |
| 290 | .data |
| 291 | user_data_start: |
| 292 | .word 0x0 ! Thread 0 interrupt count |
| 293 | .word 0x0 |
| 294 | .word 0x0 ! Thread 1 interrupt count |
| 295 | .word 0x0 |
| 296 | .word 0x0 ! etc. ... |
| 297 | .word 0x0 |
| 298 | .word 0x0 |
| 299 | .word 0x0 |
| 300 | .word 0x0 |
| 301 | .word 0x0 |
| 302 | .word 0x0 |
| 303 | .word 0x0 |
| 304 | .word 0x0 |
| 305 | .word 0x0 |
| 306 | .word 0x0 |
| 307 | .word 0x0 |
| 308 | .word 0x0 |
| 309 | .word 0x0 |
| 310 | .word 0x0 |
| 311 | .word 0x0 |
| 312 | .word 0x0 |
| 313 | .word 0x0 |
| 314 | .word 0x0 |
| 315 | .word 0x0 |
| 316 | .word 0x0 |
| 317 | .word 0x0 |
| 318 | .word 0x0 |
| 319 | .word 0x0 |
| 320 | .word 0x0 |
| 321 | .word 0x0 |
| 322 | .word 0x0 |
| 323 | .word 0x0 |
| 324 | .word 0x0 |
| 325 | .word 0x0 |
| 326 | .word 0x0 |
| 327 | .word 0x0 |
| 328 | .word 0x0 |
| 329 | .word 0x0 |
| 330 | .word 0x0 |
| 331 | .word 0x0 |
| 332 | .word 0x0 |
| 333 | .word 0x0 |
| 334 | .word 0x0 |
| 335 | .word 0x0 |
| 336 | .word 0x0 |
| 337 | .word 0x0 |
| 338 | .word 0x0 |
| 339 | .word 0x0 |
| 340 | .word 0x0 |
| 341 | .word 0x0 |
| 342 | .word 0x0 |
| 343 | .word 0x0 |
| 344 | .word 0x0 |
| 345 | .word 0x0 |
| 346 | .word 0x0 |
| 347 | .word 0x0 |
| 348 | .word 0x0 |
| 349 | .word 0x0 |
| 350 | .word 0x0 |
| 351 | .word 0x0 |
| 352 | .word 0x0 |
| 353 | .word 0x0 |
| 354 | .word 0x0 |
| 355 | .word 0x0 |
| 356 | .word 0x0 |
| 357 | .word 0x0 |
| 358 | .word 0x0 |
| 359 | .word 0x0 |
| 360 | .word 0x0 |
| 361 | .word 0x0 |
| 362 | .word 0x0 |
| 363 | .word 0x0 |
| 364 | .word 0x0 |
| 365 | .word 0x0 |
| 366 | .word 0x0 |
| 367 | .word 0x0 |
| 368 | .word 0x0 |
| 369 | .word 0x0 |
| 370 | .word 0x0 |
| 371 | .word 0x0 |
| 372 | .word 0x0 |
| 373 | .word 0x0 |
| 374 | .word 0x0 |
| 375 | .word 0x0 |
| 376 | .word 0x0 |
| 377 | .word 0x0 |
| 378 | .word 0x0 |
| 379 | .word 0x0 |
| 380 | .word 0x0 |
| 381 | .word 0x0 |
| 382 | .word 0x0 |
| 383 | .word 0x0 |
| 384 | .word 0x0 |
| 385 | .word 0x0 |
| 386 | .word 0x0 |
| 387 | .word 0x0 |
| 388 | .word 0x0 |
| 389 | .word 0x0 |
| 390 | .word 0x0 |
| 391 | .word 0x0 |
| 392 | .word 0x0 |
| 393 | .word 0x0 |
| 394 | .word 0x0 |
| 395 | .word 0x0 |
| 396 | .word 0x0 |
| 397 | .word 0x0 |
| 398 | .word 0x0 |
| 399 | .word 0x0 |
| 400 | .word 0x0 |
| 401 | .word 0x0 |
| 402 | .word 0x0 |
| 403 | .word 0x0 |
| 404 | .word 0x0 |
| 405 | .word 0x0 |
| 406 | .word 0x0 |
| 407 | .word 0x0 |
| 408 | .word 0x0 |
| 409 | .word 0x0 |
| 410 | .word 0x0 |
| 411 | .word 0x0 |
| 412 | .word 0x0 |
| 413 | .word 0x0 |
| 414 | .word 0x0 |
| 415 | .word 0x0 |
| 416 | .word 0x0 |
| 417 | .word 0x0 |
| 418 | .word 0x0 |
| 419 | .word 0x0 |
| 420 | .word 0x0 |
| 421 | .word 0x0 |
| 422 | .word 0x0 |
| 423 | .word 0x0 |
| 424 | .word 0x0 |
| 425 | .word 0x0 |
| 426 | .word 0x0 |
| 427 | .word 0x0 |
| 428 | .word 0x0 |
| 429 | .word 0x0 |
| 430 | .end |
| 431 | |
| 432 | |
| 433 | |
| 434 | |