| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: interrupt_INT_VEC_DIS_all2.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define H_HT0_Interrupt_0x60 |
| 42 | #define My_HT0_Interrupt_0x60 \ |
| 43 | call my_trap_code; \ |
| 44 | nop; \ |
| 45 | retry; \ |
| 46 | nop; |
| 47 | |
| 48 | #include "hboot.s" |
| 49 | |
| 50 | #include "ncu_defines.h" |
| 51 | |
| 52 | /************************************************************************ |
| 53 | Test case code start |
| 54 | ************************************************************************/ |
| 55 | |
| 56 | .text |
| 57 | .global main |
| 58 | |
| 59 | main: |
| 60 | |
| 61 | ! Switch to hypervisor mode. |
| 62 | |
| 63 | ta T_CHANGE_HPRIV |
| 64 | nop |
| 65 | |
| 66 | wr %g0, INT_VEC_DIS, %asi |
| 67 | |
| 68 | ! Generate a cross thread interrupt to this thread, 0. |
| 69 | label0: |
| 70 | #ifndef PORTABLE_CORE |
| 71 | stxa %g0, [%g0]%asi ! start with vector number 0 |
| 72 | #else |
| 73 | ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID |
| 74 | sllx %o2, 8, %o2 |
| 75 | stxa %o2, [%g0]%asi ! start with vector number 0 |
| 76 | #endif |
| 77 | membar #Sync |
| 78 | |
| 79 | ! Wait until interrupt occurs. |
| 80 | label1: |
| 81 | #ifdef DTM_ENABLED |
| 82 | set 400, %g4 ! g4 = timeout counter |
| 83 | #else |
| 84 | setx 1600, %g1, %g4 ! g4 = DTM timeout counter |
| 85 | #endif |
| 86 | mov %g0, %g3 ! g3 = interrupt count |
| 87 | setx my_trap_count, %g1, %g2 |
| 88 | |
| 89 | wait_loop_top: |
| 90 | ld [%g2], %g1 |
| 91 | cmp %g1, %g3 |
| 92 | be wait_loop_bottom ! no interrupt yet |
| 93 | nop |
| 94 | |
| 95 | ! When an interrupt occurs, check if done enough |
| 96 | wait_loop_2: |
| 97 | inc %g3 |
| 98 | cmp %g3, 32 |
| 99 | be test_passed |
| 100 | nop |
| 101 | |
| 102 | ! Then kick off another interrupt, with new vector number |
| 103 | wait_loop_3: |
| 104 | #ifndef PORTABLE_CORE |
| 105 | stxa %g3, [%g0]%asi ! INT_VEC_DIS |
| 106 | #else |
| 107 | or %o2, %g3, %o3 ! get the vector & thread to use |
| 108 | stxa %o3, [%g0]%asi ! INT_VEC_DIS |
| 109 | #endif |
| 110 | ba wait_loop_top |
| 111 | nop |
| 112 | |
| 113 | ! When no interrupt check for timeout |
| 114 | wait_loop_bottom: |
| 115 | cmp %g4, 0 |
| 116 | be test_failed |
| 117 | nop |
| 118 | ba wait_loop_top |
| 119 | dec %g4 |
| 120 | |
| 121 | |
| 122 | /********************************************************************** |
| 123 | Interrupt trap handler. |
| 124 | **********************************************************************/ |
| 125 | |
| 126 | .global my_trap_code |
| 127 | |
| 128 | my_trap_code: |
| 129 | ! Increment the count |
| 130 | |
| 131 | setx my_trap_count, %g6, %g7 |
| 132 | ld [%g7], %g5 |
| 133 | add %g5, 1, %g6 |
| 134 | st %g6, [%g7] |
| 135 | membar #Sync |
| 136 | |
| 137 | ! Check the core interrupt receive and incoming vector registers. |
| 138 | |
| 139 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 |
| 140 | set 1, %g7 |
| 141 | sllx %g7, %g5, %g7 |
| 142 | cmp %g4, %g7 ! vector bit # should = old trap count |
| 143 | bne test_failed |
| 144 | nop |
| 145 | |
| 146 | ! Clear the interrupt |
| 147 | |
| 148 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 |
| 149 | cmp %g3, %g5 ! vector # should = old trap count |
| 150 | bne test_failed |
| 151 | nop |
| 152 | |
| 153 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 |
| 154 | cmp %g4, 0 ! now should be 0 |
| 155 | bne test_failed |
| 156 | nop |
| 157 | |
| 158 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 |
| 159 | cmp %g3, 0x0 ! should also now be 0 |
| 160 | bne test_failed |
| 161 | nop |
| 162 | |
| 163 | jmpl %o7+0x8, %g0 |
| 164 | nop |
| 165 | |
| 166 | |
| 167 | test_passed: |
| 168 | EXIT_GOOD |
| 169 | |
| 170 | test_failed: |
| 171 | EXIT_BAD |
| 172 | |
| 173 | |
| 174 | /************************************************************************ |
| 175 | Test case data start |
| 176 | ************************************************************************/ |
| 177 | .data |
| 178 | user_data_start: |
| 179 | my_trap_count: |
| 180 | .word 0x0 |
| 181 | .word 0x0 |
| 182 | .end |
| 183 | |
| 184 | |
| 185 | |