| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: interrupt_QUEUE_DEV_MONDO_trap.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define H_T0_Dev_Mondo_Trap_0x7d |
| 42 | #define My_T0_Dev_Mondo_Trap_0x7d \ |
| 43 | call my_Dev_Mondo_trap; \ |
| 44 | nop; \ |
| 45 | done; \ |
| 46 | nop; |
| 47 | |
| 48 | #define H_HT0_DAE_invalid_asi_0x14 my_H_T0_DAE_invalid_asi_0x14 |
| 49 | |
| 50 | #include "hboot.s" |
| 51 | #include "asi_s.h" |
| 52 | |
| 53 | /************************************************************************ |
| 54 | Test case code start |
| 55 | ************************************************************************/ |
| 56 | |
| 57 | .text |
| 58 | .global main |
| 59 | |
| 60 | main: |
| 61 | |
| 62 | ! Switch to Hypervisor mode. |
| 63 | go_hyper1: |
| 64 | ta T_CHANGE_HPRIV |
| 65 | nop |
| 66 | |
| 67 | ! Enable interrupts in the Pstate reg. |
| 68 | rdpr %pstate, %g5 |
| 69 | wrpr %g5, 1, %pstate |
| 70 | |
| 71 | ! Initialize the queue head and tail pointers to same location. |
| 72 | init_dev_queue: |
| 73 | set ASI_QUEUE, %g1 |
| 74 | wr %g1, %g0, %asi |
| 75 | setx queue_start, %g1, %g2 |
| 76 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_HEAD]%asi |
| 77 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_TAIL]%asi |
| 78 | |
| 79 | ! Switch to supervisor mode. |
| 80 | go_super: |
| 81 | ta T_CHANGE_PRIV |
| 82 | nop |
| 83 | ta T_CHANGE_NONHPRIV |
| 84 | nop |
| 85 | |
| 86 | ! Change the queue head != queue tail to generate trap |
| 87 | gen_mondo_trap: |
| 88 | setx queue_end, %g1, %g2 |
| 89 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_HEAD]%asi |
| 90 | membar #Sync |
| 91 | |
| 92 | ! Wait for mondo trap |
| 93 | mondo_wait: |
| 94 | setx 400, %g1, %g7 ! g7 = timeout count |
| 95 | setx dev_mondo_trap_count, %g1, %g3 |
| 96 | mondo_loop: |
| 97 | brz %g7, test_failed |
| 98 | nop |
| 99 | ld [%g3], %g4 |
| 100 | brz %g4, mondo_loop |
| 101 | sub %g7, 1, %g7 |
| 102 | |
| 103 | ! Change queue head == queue tail, no trap expected |
| 104 | no_mondo_trap: |
| 105 | setx queue_start, %g1, %g2 |
| 106 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_HEAD]%asi |
| 107 | membar #Sync |
| 108 | |
| 109 | ! Try to write queue tail register, expect a |
| 110 | ! DAE_invalid trap |
| 111 | dae_inv_trap: |
| 112 | setx queue_end, %g1, %g2 |
| 113 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_TAIL]%asi |
| 114 | membar #Sync |
| 115 | |
| 116 | ! Switch to Hypervisor mode. |
| 117 | go_hyper2: |
| 118 | ta T_CHANGE_HPRIV |
| 119 | nop |
| 120 | |
| 121 | ! Change queue tail != queue head, no trap expected. |
| 122 | hyper_no_trap: |
| 123 | setx queue_end, %g1, %g2 |
| 124 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_TAIL]%asi |
| 125 | membar #Sync |
| 126 | |
| 127 | ! Wait a bit |
| 128 | wait: |
| 129 | setx 100, %g1, %g7 ! Loop count |
| 130 | loop: |
| 131 | brz %g7, go_super2 |
| 132 | sub %g7, 1, %g7 |
| 133 | |
| 134 | ! Go back to supervisor mode, trap should occur now. |
| 135 | go_super2: |
| 136 | ta T_CHANGE_NONHPRIV |
| 137 | nop |
| 138 | |
| 139 | ! Wait a bit more |
| 140 | wait_more: |
| 141 | setx 400, %g1, %g7 ! Loop count |
| 142 | loop_more: |
| 143 | brz %g7, check_trap_counts |
| 144 | sub %g7, 1, %g7 |
| 145 | |
| 146 | check_trap_counts: |
| 147 | setx dev_mondo_trap_count, %g1, %g3 |
| 148 | ld [%g3], %g4 |
| 149 | cmp %g4, 2 |
| 150 | bne test_failed |
| 151 | nop |
| 152 | |
| 153 | ta T_CHANGE_HPRIV |
| 154 | nop |
| 155 | |
| 156 | setx dae_invalid_trap_count, %g1, %g3 |
| 157 | ld [%g3], %g4 |
| 158 | cmp %g4, 1 |
| 159 | bne test_failed |
| 160 | nop |
| 161 | |
| 162 | ! Done |
| 163 | |
| 164 | ba test_passed |
| 165 | nop |
| 166 | |
| 167 | |
| 168 | test_passed: |
| 169 | EXIT_GOOD |
| 170 | |
| 171 | test_failed: |
| 172 | EXIT_BAD |
| 173 | |
| 174 | |
| 175 | /********************************************************************** |
| 176 | Trap handlers. |
| 177 | **********************************************************************/ |
| 178 | |
| 179 | .global my_Dev_Mondo_trap |
| 180 | .global my_H_T0_DAE_invalid_asi_0x14 |
| 181 | |
| 182 | my_Dev_Mondo_trap: |
| 183 | ! Increment the count |
| 184 | |
| 185 | setx dev_mondo_trap_count, %g6, %g7 |
| 186 | ld [%g7], %g5 |
| 187 | add %g5, 1, %g5 |
| 188 | st %g5, [%g7] |
| 189 | membar #Sync |
| 190 | |
| 191 | ! Clear the interrupt |
| 192 | |
| 193 | ldxa [%g0 + ASI_DEVICE_QUEUE_TAIL]%asi, %g2 |
| 194 | stxa %g2, [%g0 + ASI_DEVICE_QUEUE_HEAD]%asi |
| 195 | membar #Sync |
| 196 | |
| 197 | jmpl %o7+0x8, %g0 |
| 198 | nop |
| 199 | |
| 200 | |
| 201 | my_H_T0_DAE_invalid_asi_0x14: |
| 202 | ! Increment the count |
| 203 | |
| 204 | setx dae_invalid_trap_count, %g6, %g7 |
| 205 | ld [%g7], %g5 |
| 206 | add %g5, 1, %g5 |
| 207 | st %g5, [%g7] |
| 208 | membar #Sync |
| 209 | |
| 210 | done |
| 211 | nop |
| 212 | |
| 213 | |
| 214 | /************************************************************************ |
| 215 | Test case data start |
| 216 | ************************************************************************/ |
| 217 | .data |
| 218 | user_data_start: |
| 219 | dev_mondo_trap_count: |
| 220 | .word 0x0 |
| 221 | .word 0x0 |
| 222 | dae_invalid_trap_count: |
| 223 | .word 0x0 |
| 224 | .word 0x0 |
| 225 | queue_start: |
| 226 | .word 0x0 |
| 227 | .word 0x0 |
| 228 | .word 0x0 |
| 229 | .word 0x0 |
| 230 | .word 0x0 |
| 231 | .word 0x0 |
| 232 | .word 0x0 |
| 233 | .word 0x0 |
| 234 | .word 0x0 |
| 235 | .word 0x0 |
| 236 | .word 0x0 |
| 237 | .word 0x0 |
| 238 | .word 0x0 |
| 239 | .word 0x0 |
| 240 | .word 0x0 |
| 241 | .word 0x0 |
| 242 | queue_end: |
| 243 | .word 0x0 |
| 244 | .word 0x0 |
| 245 | .word 0x0 |
| 246 | .word 0x0 |
| 247 | .end |
| 248 | |
| 249 | |
| 250 | |