| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: interrupt_send_cc_all_thr.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | #define SYNC_THREADS 0xffffffffffffffff |
| 41 | |
| 42 | #define H_HT0_Interrupt_0x60 |
| 43 | #define My_HT0_Interrupt_0x60 \ |
| 44 | call my_trap_code; \ |
| 45 | nop; \ |
| 46 | retry; \ |
| 47 | nop; |
| 48 | |
| 49 | #include "hboot.s" |
| 50 | |
| 51 | #include "ncu_defines.h" |
| 52 | #include "cmp_macros.h" |
| 53 | |
| 54 | /************************************************************************ |
| 55 | Test case code start |
| 56 | ************************************************************************/ |
| 57 | |
| 58 | .text |
| 59 | .global main |
| 60 | |
| 61 | main: |
| 62 | |
| 63 | ! Switch to hypervisor mode. |
| 64 | |
| 65 | ta T_CHANGE_HPRIV |
| 66 | nop |
| 67 | |
| 68 | ta T_RD_THID |
| 69 | cmp %o1, 0 |
| 70 | be main_t0 ! branch if tread 0 |
| 71 | nop |
| 72 | ba main_t1_to_t63 ! branch if not thread 0 |
| 73 | nop |
| 74 | |
| 75 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 76 | ! |
| 77 | ! Thread 0 Start Here |
| 78 | ! |
| 79 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 80 | |
| 81 | main_t0: |
| 82 | mov %g0, %g7 ! %g7 = loop count |
| 83 | mov %o1, %g6 ! %g6 = data for INT_VEC_DIS reg. |
| 84 | wr %g0, INT_VEC_DIS, %asi |
| 85 | |
| 86 | /* Turn off interrupts. */ |
| 87 | |
| 88 | t0_intr_off: |
| 89 | rdpr %pstate, %g1 |
| 90 | set 0x2, %g2 |
| 91 | andn %g1, %g2,%g1 |
| 92 | wrpr %g1, %g0, %pstate |
| 93 | |
| 94 | /* Sync up all the treads. */ |
| 95 | |
| 96 | sync_t0: |
| 97 | SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 ) |
| 98 | |
| 99 | /* Send 1 interrupt, done twice, first is to fill Icache */ |
| 100 | |
| 101 | t0_send_1_intr: |
| 102 | |
| 103 | stxa %g6, [%g0]%asi |
| 104 | inc %g7 |
| 105 | cmp %g7, 1 |
| 106 | beq sync_t0 |
| 107 | nop |
| 108 | |
| 109 | /* Turn on interrupts and handle the traps */ |
| 110 | |
| 111 | t0_get_intr_1: |
| 112 | rdpr %pstate, %g1 |
| 113 | set 0x2, %g2 |
| 114 | or %g1, %g2,%g1 |
| 115 | wrpr %g1, %g0, %pstate |
| 116 | |
| 117 | /* Wait for 64 interrupts to be taken. */ |
| 118 | |
| 119 | t0_intr_wait_1: |
| 120 | setx 0x1000, %g1, %g2 ! %g2 = timeout value |
| 121 | setx my_trap_count, %g1, %g3 |
| 122 | |
| 123 | t0_intr_wait_loop_1: |
| 124 | ld [%g3], %g4 |
| 125 | cmp %g4, 64 |
| 126 | beq t0_more |
| 127 | dec %g2 |
| 128 | |
| 129 | cmp %g2, 0 |
| 130 | beq test_failed |
| 131 | nop |
| 132 | |
| 133 | ba t0_intr_wait_loop_1 |
| 134 | nop |
| 135 | |
| 136 | |
| 137 | /* Set up to do 4 interrupts in at a time. */ |
| 138 | |
| 139 | t0_more: |
| 140 | st %g0, [%g3] ! Zero the interrupt count |
| 141 | mov %g0, %g7 ! %g7 = loop count |
| 142 | mov %o1, %g6 ! %g6 = data for INT_VEC_DIS reg. |
| 143 | |
| 144 | /* Turn off interrupts. */ |
| 145 | t0_intr_off_again: |
| 146 | rdpr %pstate, %g1 |
| 147 | set 0x2, %g2 |
| 148 | andn %g1, %g2,%g1 |
| 149 | wrpr %g1, %g0, %pstate |
| 150 | |
| 151 | /* Sync up all the treads. */ |
| 152 | |
| 153 | sync_t0_again: |
| 154 | SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 ) |
| 155 | |
| 156 | /* Send 4 interrupts, done twice, first is to fill Icache */ |
| 157 | |
| 158 | t0_send_4_intr: |
| 159 | stxa %g6, [%g0]%asi |
| 160 | stxa %g6, [%g0]%asi |
| 161 | stxa %g6, [%g0]%asi |
| 162 | stxa %g6, [%g0]%asi |
| 163 | inc %g7 |
| 164 | cmp %g7, 1 |
| 165 | beq sync_t0_again |
| 166 | nop |
| 167 | |
| 168 | /* Turn on interrupts and handle the traps */ |
| 169 | |
| 170 | t0_get_intr_2: |
| 171 | rdpr %pstate, %g1 |
| 172 | set 0x2, %g2 |
| 173 | or %g1, %g2,%g1 |
| 174 | wrpr %g1, %g0, %pstate |
| 175 | |
| 176 | /* Wait for 64 interrupts to be taken. */ |
| 177 | |
| 178 | t0_intr_wait_2: |
| 179 | setx 0x1000, %g1, %g2 ! %g2 = timeout value |
| 180 | setx my_trap_count, %g1, %g3 |
| 181 | |
| 182 | t0_intr_wait_loop_2: |
| 183 | ld [%g3], %g4 |
| 184 | cmp %g4, 64 |
| 185 | beq t0_done |
| 186 | dec %g2 |
| 187 | |
| 188 | cmp %g2, 0 |
| 189 | beq test_failed |
| 190 | nop |
| 191 | |
| 192 | ba t0_intr_wait_loop_2 |
| 193 | nop |
| 194 | |
| 195 | /* T0 Done */ |
| 196 | |
| 197 | t0_done: |
| 198 | ba test_passed |
| 199 | nop |
| 200 | |
| 201 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 202 | ! |
| 203 | ! All Threads Except 0 Start Here |
| 204 | ! |
| 205 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 206 | |
| 207 | |
| 208 | main_t1_to_t63: |
| 209 | mov %g0, %g7 ! %g7 = loop count |
| 210 | mov %o1, %g6 ! %g6 = data for INT_VEC_DIS reg. |
| 211 | wr %g0, INT_VEC_DIS, %asi |
| 212 | |
| 213 | /* Sync up all the treads. */ |
| 214 | |
| 215 | sync_t1_t63: |
| 216 | SYNC_THREAD_OTHER( %g6,%g1,%g2 ) |
| 217 | |
| 218 | /* Send 1 interrupt, done twice, first is to fill Icache */ |
| 219 | |
| 220 | t1_t63_send_1_intr: |
| 221 | |
| 222 | stxa %g6, [%g0]%asi |
| 223 | inc %g7 |
| 224 | cmp %g7, 1 |
| 225 | beq sync_t1_t63 |
| 226 | nop |
| 227 | |
| 228 | /* Set up to do 4 interrupts in at a time. */ |
| 229 | |
| 230 | t1_t63_more: |
| 231 | st %g0, [%g3] ! Zero the interrupt count |
| 232 | mov %g0, %g7 ! %g7 = loop count |
| 233 | mov %o1, %g6 ! %g6 = data for INT_VEC_DIS reg. |
| 234 | |
| 235 | /* Sync up all the treads. */ |
| 236 | |
| 237 | sync_t1_t63_again: |
| 238 | SYNC_THREAD_OTHER( %g6,%g1,%g2 ) |
| 239 | |
| 240 | /* Send 4 interrupts, done twice, first is to fill Icache */ |
| 241 | |
| 242 | t1_t63_send_4_intr: |
| 243 | stxa %g6, [%g0]%asi |
| 244 | stxa %g6, [%g0]%asi |
| 245 | stxa %g6, [%g0]%asi |
| 246 | stxa %g6, [%g0]%asi |
| 247 | inc %g7 |
| 248 | cmp %g7, 1 |
| 249 | beq sync_t1_t63_again |
| 250 | nop |
| 251 | |
| 252 | /* T1_T63 Done */ |
| 253 | |
| 254 | t1_t63_done: |
| 255 | ba test_passed |
| 256 | nop |
| 257 | |
| 258 | |
| 259 | /********************************************************************** |
| 260 | Interrupt trap handler. |
| 261 | **********************************************************************/ |
| 262 | |
| 263 | .global my_trap_code |
| 264 | |
| 265 | my_trap_code: |
| 266 | |
| 267 | ! Only T1_T63 should get interrupts |
| 268 | |
| 269 | ta T_RD_THID |
| 270 | cmp %o1, 0 |
| 271 | bne test_failed |
| 272 | nop |
| 273 | |
| 274 | ! Increment the count |
| 275 | trap0: |
| 276 | setx my_trap_count, %g6, %g7 |
| 277 | ld [%g7], %g5 |
| 278 | add %g5, 1, %g5 |
| 279 | st %g5, [%g7] |
| 280 | membar #Sync |
| 281 | |
| 282 | ! Read the core interrupt receive reg. |
| 283 | trap1: |
| 284 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 |
| 285 | |
| 286 | ! Check the incomming vector register to make sure highest priority |
| 287 | ! interrupt was done first. |
| 288 | trap2: |
| 289 | ldxa [%g0]ASI_SWVR_INTR_R, %g5 |
| 290 | orn %g0, %g0, %g1 |
| 291 | inc %g5 |
| 292 | cmp %g5, 64 |
| 293 | be trap3 ! skip check since this is highest possible priority |
| 294 | nop |
| 295 | |
| 296 | sllx %g1, %g5, %g1 |
| 297 | and %g1, %g4, %g4 |
| 298 | brnz %g4, test_failed |
| 299 | nop |
| 300 | |
| 301 | ! Done |
| 302 | trap3: |
| 303 | |
| 304 | jmpl %o7+0x8, %g0 |
| 305 | nop |
| 306 | |
| 307 | |
| 308 | test_passed: |
| 309 | EXIT_GOOD |
| 310 | |
| 311 | test_failed: |
| 312 | EXIT_BAD |
| 313 | |
| 314 | |
| 315 | /************************************************************************ |
| 316 | Test case data start |
| 317 | ************************************************************************/ |
| 318 | .data |
| 319 | user_data_start: |
| 320 | my_trap_count: |
| 321 | .word 0x0 |
| 322 | .word 0x0 |
| 323 | .end |
| 324 | |
| 325 | |
| 326 | |