| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: allbanks_allcores.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | |
| 41 | #define TEST_DATA1 0x5555555555555555 |
| 42 | #define L2_ENTRY_PA0 0x2020000008 |
| 43 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 44 | #define SPARC_ES_W1C_VALUE 0xefffffff |
| 45 | #define TT_SW_Error 0x40 |
| 46 | |
| 47 | #include "hboot.s" |
| 48 | #include "asi_s.h" |
| 49 | #include "err_defines.h" |
| 50 | |
| 51 | |
| 52 | |
| 53 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 54 | |
| 55 | |
| 56 | /************************************************************************ |
| 57 | Test case code start |
| 58 | ************************************************************************/ |
| 59 | |
| 60 | .text |
| 61 | .global main |
| 62 | |
| 63 | main: |
| 64 | ta T_CHANGE_HPRIV |
| 65 | |
| 66 | get_th_id_o0: |
| 67 | ta T_RD_THID |
| 68 | |
| 69 | cmp %o1, 0x0 |
| 70 | be main_t0 |
| 71 | nop |
| 72 | |
| 73 | cmp %o1, 0x1 |
| 74 | be main_t1 |
| 75 | nop |
| 76 | |
| 77 | cmp %o1, 0x2 |
| 78 | be main_t2 |
| 79 | nop |
| 80 | |
| 81 | |
| 82 | cmp %o1, 0x3 |
| 83 | be main_t3 |
| 84 | nop |
| 85 | |
| 86 | |
| 87 | cmp %o1, 0x4 |
| 88 | be main_t4 |
| 89 | nop |
| 90 | |
| 91 | cmp %o1, 0x5 |
| 92 | be main_t5 |
| 93 | nop |
| 94 | |
| 95 | cmp %o1, 0x6 |
| 96 | be main_t6 |
| 97 | nop |
| 98 | |
| 99 | |
| 100 | cmp %o1, 0x7 |
| 101 | be main_t7 |
| 102 | nop |
| 103 | |
| 104 | main_t0: |
| 105 | ba L20_Init |
| 106 | nop |
| 107 | |
| 108 | |
| 109 | main_t1: |
| 110 | nop |
| 111 | nop |
| 112 | nop |
| 113 | ba L21_Init |
| 114 | nop |
| 115 | |
| 116 | main_t2: |
| 117 | nop |
| 118 | nop |
| 119 | nop |
| 120 | ba L22_Init |
| 121 | nop |
| 122 | main_t3: |
| 123 | nop |
| 124 | nop |
| 125 | nop |
| 126 | ba L23_Init |
| 127 | nop |
| 128 | main_t4: |
| 129 | nop |
| 130 | nop |
| 131 | nop |
| 132 | ba L24_Init |
| 133 | nop |
| 134 | main_t5: |
| 135 | nop |
| 136 | nop |
| 137 | nop |
| 138 | ba L25_Init |
| 139 | nop |
| 140 | main_t6: |
| 141 | nop |
| 142 | nop |
| 143 | nop |
| 144 | ba L26_Init |
| 145 | nop |
| 146 | main_t7: |
| 147 | nop |
| 148 | nop |
| 149 | nop |
| 150 | ba L27_Init |
| 151 | nop |
| 152 | |
| 153 | |
| 154 | |
| 155 | L20_Init: |
| 156 | |
| 157 | disable_l1_DCache: |
| 158 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 159 | ! Remove bit 2 |
| 160 | andn %l0, 0x2, %l0 |
| 161 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 162 | |
| 163 | |
| 164 | clear_l2_ESR: |
| 165 | setx L2_ES_W1C_VALUE, %l0, %l1 |
| 166 | setx L2ES_PA0, %l6, %g1 |
| 167 | stx %l1, [%g1] |
| 168 | |
| 169 | |
| 170 | set_L2_Directly_Mapped_Mode: |
| 171 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register |
| 172 | mov 0x2, %l0 |
| 173 | stx %l0, [%g1] |
| 174 | |
| 175 | store_to_L2: |
| 176 | setx TEST_DATA1, %l0, %g5 |
| 177 | |
| 178 | store_to_L2_Bank0: |
| 179 | setx 0xaf000000, %l0, %g2 ! bits [8:6] select Bank |
| 180 | setx 0x53000000, %l0, %g3 |
| 181 | setx 0x49000000, %l0, %g4 |
| 182 | setx 0xaa000000, %l0, %g6 |
| 183 | setx 0xa3000000, %l0, %g7 |
| 184 | setx 0xa3000000, %l0, %g1 |
| 185 | setx 0xa3000000, %l0, %l7 |
| 186 | setx 0xa3000000, %l0, %l6 |
| 187 | stx %g5, [%g2] |
| 188 | stx %g5, [%g3] |
| 189 | stx %g5, [%g4] |
| 190 | stx %g5, [%g6] |
| 191 | stx %g5, [%g7] |
| 192 | stx %g5, [%g1] |
| 193 | stx %g5, [%l7] |
| 194 | stx %g5, [%l6] |
| 195 | ldx [%g2], %l0 |
| 196 | ldx [%g3], %l1 |
| 197 | ldx [%g4], %l2 |
| 198 | ldx [%g6], %l3 |
| 199 | ldx [%g7], %l4 |
| 200 | ldx [%g1], %l5 |
| 201 | ldx [%l7], %i1 |
| 202 | ldx [%l6], %i2 |
| 203 | |
| 204 | ba test_pass |
| 205 | nop |
| 206 | |
| 207 | |
| 208 | L21_Init: |
| 209 | setx TEST_DATA1, %l0, %g5 |
| 210 | |
| 211 | |
| 212 | |
| 213 | |
| 214 | |
| 215 | |
| 216 | store_to_L2_Bank1: |
| 217 | setx 0xaf000040, %l0, %i1 ! bits [8:6] select Bank |
| 218 | setx 0xaa000040, %l0, %i2 |
| 219 | setx 0x56000040, %l0, %i3 |
| 220 | setx 0x44000040, %l0, %i4 |
| 221 | setx 0x33000040, %l0, %i5 |
| 222 | setx 0x33000040, %l0, %i6 |
| 223 | setx 0x33000040, %l0, %i7 |
| 224 | setx 0x33000040, %l0, %l1 |
| 225 | stx %g5, [%i2] |
| 226 | stx %g5, [%i3] |
| 227 | stx %g5, [%i4] |
| 228 | stx %g5, [%i5] |
| 229 | stx %g5, [%i1] |
| 230 | stx %g5, [%i6] |
| 231 | stx %g5, [%i7] |
| 232 | stx %g5, [%l1] |
| 233 | |
| 234 | ldx [%i2], %o1 |
| 235 | ldx [%i3], %o2 |
| 236 | ldx [%i4], %o3 |
| 237 | ldx [%i5], %o4 |
| 238 | ldx [%i1], %g6 |
| 239 | ldx [%i6], %g1 |
| 240 | ldx [%i7], %g2 |
| 241 | ldx [%l1], %g3 |
| 242 | |
| 243 | ba test_pass |
| 244 | nop |
| 245 | |
| 246 | L22_Init: |
| 247 | setx TEST_DATA1, %l0, %g5 |
| 248 | |
| 249 | |
| 250 | |
| 251 | |
| 252 | store_to_L2_Bank2: |
| 253 | setx 0xaf000080, %l0, %g2 ! bits [8:6] select Bank |
| 254 | setx 0x53000080, %l0, %g3 |
| 255 | setx 0x49000080, %l0, %g4 |
| 256 | setx 0xaa000080, %l0, %g6 |
| 257 | setx 0xa3000080, %l0, %g7 |
| 258 | setx 0xa3000080, %l0, %g1 |
| 259 | setx 0xa3000080, %l0, %l7 |
| 260 | setx 0xa3000080, %l0, %l6 |
| 261 | stx %g5, [%g2] |
| 262 | stx %g5, [%g3] |
| 263 | stx %g5, [%g4] |
| 264 | stx %g5, [%g6] |
| 265 | stx %g5, [%g7] |
| 266 | stx %g5, [%g1] |
| 267 | stx %g5, [%l7] |
| 268 | stx %g5, [%l6] |
| 269 | ldx [%g2], %l0 |
| 270 | ldx [%g3], %l1 |
| 271 | ldx [%g4], %l2 |
| 272 | ldx [%g6], %l3 |
| 273 | ldx [%g7], %l4 |
| 274 | ldx [%g1], %l5 |
| 275 | ldx [%l7], %i1 |
| 276 | ldx [%l6], %i2 |
| 277 | |
| 278 | |
| 279 | ba test_pass |
| 280 | nop |
| 281 | |
| 282 | L23_Init: |
| 283 | setx TEST_DATA1, %l0, %g5 |
| 284 | |
| 285 | |
| 286 | |
| 287 | |
| 288 | store_to_L2_Bank3: |
| 289 | setx 0xaf0000c0, %l0, %i1 ! bits [8:6] select Bank |
| 290 | setx 0xaa0000c0, %l0, %i2 |
| 291 | setx 0x560000c0, %l0, %i3 |
| 292 | setx 0x440000c0, %l0, %i4 |
| 293 | setx 0x330000c0, %l0, %i5 |
| 294 | setx 0x330000c0, %l0, %i6 |
| 295 | setx 0x330000c0, %l0, %i7 |
| 296 | setx 0x330000c0, %l0, %l1 |
| 297 | stx %g5, [%i2] |
| 298 | stx %g5, [%i3] |
| 299 | stx %g5, [%i4] |
| 300 | stx %g5, [%i5] |
| 301 | stx %g5, [%i1] |
| 302 | stx %g5, [%i6] |
| 303 | stx %g5, [%i7] |
| 304 | stx %g5, [%l1] |
| 305 | |
| 306 | ldx [%i2], %o1 |
| 307 | ldx [%i3], %o2 |
| 308 | ldx [%i4], %o3 |
| 309 | ldx [%i5], %o4 |
| 310 | ldx [%i1], %g6 |
| 311 | ldx [%i6], %g1 |
| 312 | ldx [%i7], %g2 |
| 313 | ldx [%l1], %g3 |
| 314 | |
| 315 | ba test_pass |
| 316 | nop |
| 317 | |
| 318 | L24_Init: |
| 319 | setx TEST_DATA1, %l0, %g5 |
| 320 | |
| 321 | |
| 322 | |
| 323 | |
| 324 | |
| 325 | store_to_L2_Bank4: |
| 326 | setx 0xaf000100, %l0, %g2 ! bits [8:6] select Bank |
| 327 | setx 0x53000100, %l0, %g3 |
| 328 | setx 0x49000100, %l0, %g4 |
| 329 | setx 0xaa000100, %l0, %g6 |
| 330 | setx 0xa3000100, %l0, %g7 |
| 331 | setx 0xa3000100, %l0, %g1 |
| 332 | setx 0xa3000100, %l0, %l7 |
| 333 | setx 0xa3000100, %l0, %l6 |
| 334 | stx %g5, [%g2] |
| 335 | stx %g5, [%g3] |
| 336 | stx %g5, [%g4] |
| 337 | stx %g5, [%g6] |
| 338 | stx %g5, [%g7] |
| 339 | stx %g5, [%g1] |
| 340 | stx %g5, [%l7] |
| 341 | stx %g5, [%l6] |
| 342 | ldx [%g2], %l0 |
| 343 | ldx [%g3], %l1 |
| 344 | ldx [%g4], %l2 |
| 345 | ldx [%g6], %l3 |
| 346 | ldx [%g7], %l4 |
| 347 | ldx [%g1], %l5 |
| 348 | ldx [%l7], %i1 |
| 349 | ldx [%l6], %i2 |
| 350 | |
| 351 | ba test_pass |
| 352 | nop |
| 353 | |
| 354 | L25_Init: |
| 355 | setx TEST_DATA1, %l0, %g5 |
| 356 | |
| 357 | |
| 358 | |
| 359 | |
| 360 | store_to_L2_Bank5: |
| 361 | setx 0xaf000140, %l0, %i1 ! bits [8:6] select Bank |
| 362 | setx 0xaa000140, %l0, %i2 |
| 363 | setx 0x56000140, %l0, %i3 |
| 364 | setx 0x44000140, %l0, %i4 |
| 365 | setx 0x33000140, %l0, %i5 |
| 366 | setx 0x33000140, %l0, %i6 |
| 367 | setx 0x33000140, %l0, %i7 |
| 368 | setx 0x33000140, %l0, %l1 |
| 369 | stx %g5, [%i2] |
| 370 | stx %g5, [%i3] |
| 371 | stx %g5, [%i4] |
| 372 | stx %g5, [%i5] |
| 373 | stx %g5, [%i1] |
| 374 | stx %g5, [%i6] |
| 375 | stx %g5, [%i7] |
| 376 | stx %g5, [%l1] |
| 377 | |
| 378 | ldx [%i2], %o1 |
| 379 | ldx [%i3], %o2 |
| 380 | ldx [%i4], %o3 |
| 381 | ldx [%i5], %o4 |
| 382 | ldx [%i1], %g6 |
| 383 | ldx [%i6], %g1 |
| 384 | ldx [%i7], %g2 |
| 385 | ldx [%l1], %g3 |
| 386 | |
| 387 | ba test_pass |
| 388 | nop |
| 389 | |
| 390 | L26_Init: |
| 391 | setx TEST_DATA1, %l0, %g5 |
| 392 | |
| 393 | store_to_L2_Bank6: |
| 394 | setx 0xaf000180, %l0, %i1 ! bits [8:6] select Bank |
| 395 | setx 0xaa000180, %l0, %i2 |
| 396 | setx 0x56000180, %l0, %i3 |
| 397 | setx 0x44000180, %l0, %i4 |
| 398 | setx 0x33000180, %l0, %i5 |
| 399 | setx 0x33000180, %l0, %i6 |
| 400 | setx 0x33000180, %l0, %i7 |
| 401 | setx 0x33000180, %l0, %l1 |
| 402 | stx %g5, [%i2] |
| 403 | stx %g5, [%i3] |
| 404 | stx %g5, [%i4] |
| 405 | stx %g5, [%i5] |
| 406 | stx %g5, [%i1] |
| 407 | stx %g5, [%i6] |
| 408 | stx %g5, [%i7] |
| 409 | stx %g5, [%l1] |
| 410 | |
| 411 | ldx [%i2], %o1 |
| 412 | ldx [%i3], %o2 |
| 413 | ldx [%i4], %o3 |
| 414 | ldx [%i5], %o4 |
| 415 | ldx [%i1], %g6 |
| 416 | ldx [%i6], %g1 |
| 417 | ldx [%i7], %g2 |
| 418 | ldx [%l1], %g3 |
| 419 | |
| 420 | ba test_pass |
| 421 | nop |
| 422 | |
| 423 | L27_Init: |
| 424 | setx TEST_DATA1, %l0, %g5 |
| 425 | |
| 426 | |
| 427 | |
| 428 | |
| 429 | |
| 430 | store_to_L2_Bank7: |
| 431 | setx 0xaf0001c0, %l0, %i1 ! bits [8:6] select Bank |
| 432 | setx 0xaa0001c0, %l0, %i2 |
| 433 | setx 0x560001c0, %l0, %i3 |
| 434 | setx 0x440001c0, %l0, %i4 |
| 435 | setx 0x330001c0, %l0, %i5 |
| 436 | setx 0x330001c0, %l0, %i6 |
| 437 | setx 0x330001c0, %l0, %i7 |
| 438 | setx 0x330001c0, %l0, %l1 |
| 439 | stx %g5, [%i2] |
| 440 | stx %g5, [%i3] |
| 441 | stx %g5, [%i4] |
| 442 | stx %g5, [%i5] |
| 443 | stx %g5, [%i1] |
| 444 | stx %g5, [%i6] |
| 445 | stx %g5, [%i7] |
| 446 | stx %g5, [%l1] |
| 447 | |
| 448 | ldx [%i2], %o1 |
| 449 | ldx [%i3], %o2 |
| 450 | ldx [%i4], %o3 |
| 451 | ldx [%i5], %o4 |
| 452 | ldx [%i1], %g6 |
| 453 | ldx [%i6], %g1 |
| 454 | ldx [%i7], %g2 |
| 455 | ldx [%l1], %g3 |
| 456 | |
| 457 | |
| 458 | |
| 459 | ba test_pass |
| 460 | nop |
| 461 | |
| 462 | |
| 463 | |
| 464 | /******************************************************* |
| 465 | * Exit code |
| 466 | *******************************************************/ |
| 467 | |
| 468 | test_pass: |
| 469 | ta T_GOOD_TRAP |
| 470 | |
| 471 | test_fail: |
| 472 | ta T_BAD_TRAP |
| 473 | nop |
| 474 | |
| 475 | |
| 476 | user_text_end: |
| 477 | |
| 478 | |
| 479 | /************************************************************************ |
| 480 | * Test case data start |
| 481 | ************************************************************************/ |
| 482 | |
| 483 | SECTION .DATA DATA_VA=0x70000000 |
| 484 | attr_data { |
| 485 | Name = .DATA, |
| 486 | hypervisor, |
| 487 | compressimage |
| 488 | } |
| 489 | |
| 490 | .data |
| 491 | .global result_area |
| 492 | .global alias1 |
| 493 | .global alias2 |
| 494 | .global alias3 |
| 495 | .global alias4 |
| 496 | .global alias5 |
| 497 | .global alias6 |
| 498 | .global alias7 |
| 499 | .global alias8 |
| 500 | .global alias9 |
| 501 | .global alias10 |
| 502 | .global alias11 |
| 503 | .global alias12 |
| 504 | .global alias13 |
| 505 | .global alias14 |
| 506 | .global alias15 |
| 507 | .global alias16 |
| 508 | |
| 509 | user_data_start: |
| 510 | result_area: |
| 511 | .skip 512 ! 64 bytes per core |
| 512 | |
| 513 | .align 0x40000 ! each 246kb, 0x40000, aliases to same L2$ line |
| 514 | alias1: |
| 515 | .skip 1024 |
| 516 | .align 0x40000 |
| 517 | alias2: |
| 518 | .skip 1024 |
| 519 | .align 0x40000 |
| 520 | alias3: |
| 521 | .skip 1024 |
| 522 | .align 0x40000 |
| 523 | alias4: |
| 524 | .skip 1024 |
| 525 | .align 0x40000 |
| 526 | alias5: |
| 527 | .skip 1024 |
| 528 | .align 0x40000 |
| 529 | alias6: |
| 530 | .skip 1024 |
| 531 | .align 0x40000 |
| 532 | alias7: |
| 533 | .skip 1024 |
| 534 | .align 0x40000 |
| 535 | alias8: |
| 536 | .skip 1024 |
| 537 | .align 0x40000 |
| 538 | alias9: |
| 539 | .skip 1024 |
| 540 | .align 0x40000 |
| 541 | alias10: |
| 542 | .skip 1024 |
| 543 | .align 0x40000 |
| 544 | alias11: |
| 545 | .skip 1024 |
| 546 | .align 0x40000 |
| 547 | alias12: |
| 548 | .skip 1024 |
| 549 | .align 0x40000 |
| 550 | alias13: |
| 551 | .skip 1024 |
| 552 | .align 0x40000 |
| 553 | alias14: |
| 554 | .skip 1024 |
| 555 | .align 0x40000 |
| 556 | alias15: |
| 557 | .skip 1024 |
| 558 | .align 0x40000 |
| 559 | alias16: |
| 560 | .skip 1024 |
| 561 | |
| 562 | user_data_end: |
| 563 | .end |