| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_pm_all_dimm_rdwr_4.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | |
| 42 | #include "hboot.s" |
| 43 | #include "asi_s.h" |
| 44 | |
| 45 | #ifdef PM_8BANK |
| 46 | #define L20_MCU_DM0_BK0 0x0000134000 |
| 47 | #define L20_MCU_DM0_BK2 0x0000134200 |
| 48 | #define L20_MCU_DM0_BK4 0x0000134400 |
| 49 | #define L20_MCU_DM0_BK6 0x0000134600 |
| 50 | |
| 51 | #define L20_MCU_DM1_BK0 0x0800134000 |
| 52 | #define L20_MCU_DM1_BK2 0x0800134200 |
| 53 | #define L20_MCU_DM1_BK4 0x0800134400 |
| 54 | #define L20_MCU_DM1_BK6 0x0800134600 |
| 55 | |
| 56 | #define L20_MCU_DM2_BK0 0x1000134000 |
| 57 | #define L20_MCU_DM2_BK2 0x1000134200 |
| 58 | #define L20_MCU_DM2_BK4 0x1000134400 |
| 59 | #define L20_MCU_DM2_BK6 0x1000134600 |
| 60 | |
| 61 | #define L20_MCU_DM3_BK0 0x1800134000 |
| 62 | #define L20_MCU_DM3_BK2 0x1800134200 |
| 63 | #define L20_MCU_DM3_BK4 0x1800134400 |
| 64 | #define L20_MCU_DM3_BK6 0x1800134600 |
| 65 | |
| 66 | #define L20_MCU_DM4_BK0 0x2000134000 |
| 67 | #define L20_MCU_DM4_BK2 0x2000134200 |
| 68 | #define L20_MCU_DM4_BK4 0x2000134400 |
| 69 | #define L20_MCU_DM4_BK6 0x2000134600 |
| 70 | |
| 71 | #define L20_MCU_DM5_BK0 0x2800134000 |
| 72 | #define L20_MCU_DM5_BK2 0x2800134200 |
| 73 | #define L20_MCU_DM5_BK4 0x2800134400 |
| 74 | #define L20_MCU_DM5_BK6 0x2800134600 |
| 75 | |
| 76 | #define L20_MCU_DM6_BK0 0x3000134000 |
| 77 | #define L20_MCU_DM6_BK2 0x3000134200 |
| 78 | #define L20_MCU_DM6_BK4 0x3000134400 |
| 79 | #define L20_MCU_DM6_BK6 0x3000134600 |
| 80 | |
| 81 | #define L20_MCU_DM7_BK0 0x3800134000 |
| 82 | #define L20_MCU_DM7_BK2 0x3800134200 |
| 83 | #define L20_MCU_DM7_BK4 0x3800134400 |
| 84 | #define L20_MCU_DM7_BK6 0x3800134600 |
| 85 | |
| 86 | #define L2_1_MCU_DM0_BK1 0x0000134040 |
| 87 | #define L2_1_MCU_DM0_BK3 0x0000134240 |
| 88 | #define L2_1_MCU_DM0_BK5 0x0000134440 |
| 89 | #define L2_1_MCU_DM0_BK7 0x0000134640 |
| 90 | |
| 91 | #define L2_1_MCU_DM1_BK1 0x0800134040 |
| 92 | #define L2_1_MCU_DM1_BK3 0x0800134240 |
| 93 | #define L2_1_MCU_DM1_BK5 0x0800134440 |
| 94 | #define L2_1_MCU_DM1_BK7 0x0800134640 |
| 95 | |
| 96 | #define L2_1_MCU_DM2_BK1 0x1000134040 |
| 97 | #define L2_1_MCU_DM2_BK3 0x1000134240 |
| 98 | #define L2_1_MCU_DM2_BK5 0x1000134440 |
| 99 | #define L2_1_MCU_DM2_BK7 0x1000134640 |
| 100 | |
| 101 | #define L2_1_MCU_DM3_BK1 0x1800134040 |
| 102 | #define L2_1_MCU_DM3_BK3 0x1800134240 |
| 103 | #define L2_1_MCU_DM3_BK5 0x1800134440 |
| 104 | #define L2_1_MCU_DM3_BK7 0x1800134640 |
| 105 | |
| 106 | #define L2_1_MCU_DM4_BK1 0x2000134040 |
| 107 | #define L2_1_MCU_DM4_BK3 0x2000134240 |
| 108 | #define L2_1_MCU_DM4_BK5 0x2000134440 |
| 109 | #define L2_1_MCU_DM4_BK7 0x2000134640 |
| 110 | |
| 111 | #define L2_1_MCU_DM5_BK1 0x2800134040 |
| 112 | #define L2_1_MCU_DM5_BK3 0x2800134240 |
| 113 | #define L2_1_MCU_DM5_BK5 0x2800134440 |
| 114 | #define L2_1_MCU_DM5_BK7 0x2800134640 |
| 115 | |
| 116 | #define L2_1_MCU_DM6_BK1 0x3000134040 |
| 117 | #define L2_1_MCU_DM6_BK3 0x3000134240 |
| 118 | #define L2_1_MCU_DM6_BK5 0x3000134440 |
| 119 | #define L2_1_MCU_DM6_BK7 0x3000134640 |
| 120 | |
| 121 | #define L2_1_MCU_DM7_BK1 0x3800134040 |
| 122 | #define L2_1_MCU_DM7_BK3 0x3800134240 |
| 123 | #define L2_1_MCU_DM7_BK5 0x3800134440 |
| 124 | #define L2_1_MCU_DM7_BK7 0x3800134640 |
| 125 | #endif |
| 126 | |
| 127 | #ifdef PM_4BANK |
| 128 | #define L20_MCU_DM0_BK0 0x0000134000 |
| 129 | #define L20_MCU_DM0_BK2 0x0000134100 |
| 130 | #define L20_MCU_DM0_BK4 0x0000134200 |
| 131 | #define L20_MCU_DM0_BK6 0x0000134300 |
| 132 | |
| 133 | #define L20_MCU_DM1_BK0 0x0400134000 |
| 134 | #define L20_MCU_DM1_BK2 0x0400134100 |
| 135 | #define L20_MCU_DM1_BK4 0x0400134200 |
| 136 | #define L20_MCU_DM1_BK6 0x0400134300 |
| 137 | |
| 138 | #define L20_MCU_DM2_BK0 0x0800134000 |
| 139 | #define L20_MCU_DM2_BK2 0x0800134100 |
| 140 | #define L20_MCU_DM2_BK4 0x0800134200 |
| 141 | #define L20_MCU_DM2_BK6 0x0800134300 |
| 142 | |
| 143 | #define L20_MCU_DM3_BK0 0x0c00134000 |
| 144 | #define L20_MCU_DM3_BK2 0x0c00134100 |
| 145 | #define L20_MCU_DM3_BK4 0x0c00134200 |
| 146 | #define L20_MCU_DM3_BK6 0x0c00134300 |
| 147 | |
| 148 | #define L20_MCU_DM4_BK0 0x1000134000 |
| 149 | #define L20_MCU_DM4_BK2 0x1000134100 |
| 150 | #define L20_MCU_DM4_BK4 0x1000134200 |
| 151 | #define L20_MCU_DM4_BK6 0x1000134300 |
| 152 | |
| 153 | #define L20_MCU_DM5_BK0 0x1400134000 |
| 154 | #define L20_MCU_DM5_BK2 0x1400134100 |
| 155 | #define L20_MCU_DM5_BK4 0x1400134200 |
| 156 | #define L20_MCU_DM5_BK6 0x1400134300 |
| 157 | |
| 158 | #define L20_MCU_DM6_BK0 0x1800134000 |
| 159 | #define L20_MCU_DM6_BK2 0x1800134100 |
| 160 | #define L20_MCU_DM6_BK4 0x1800134200 |
| 161 | #define L20_MCU_DM6_BK6 0x1800134300 |
| 162 | |
| 163 | #define L20_MCU_DM7_BK0 0x1c00134000 |
| 164 | #define L20_MCU_DM7_BK2 0x1c00134100 |
| 165 | #define L20_MCU_DM7_BK4 0x1c00134200 |
| 166 | #define L20_MCU_DM7_BK6 0x1c00134300 |
| 167 | |
| 168 | #define L2_1_MCU_DM0_BK1 0x0000134040 |
| 169 | #define L2_1_MCU_DM0_BK3 0x0000134140 |
| 170 | #define L2_1_MCU_DM0_BK5 0x0000134240 |
| 171 | #define L2_1_MCU_DM0_BK7 0x0000134340 |
| 172 | |
| 173 | #define L2_1_MCU_DM1_BK1 0x0400134040 |
| 174 | #define L2_1_MCU_DM1_BK3 0x0400134140 |
| 175 | #define L2_1_MCU_DM1_BK5 0x0400134240 |
| 176 | #define L2_1_MCU_DM1_BK7 0x0400134340 |
| 177 | |
| 178 | #define L2_1_MCU_DM2_BK1 0x0800134040 |
| 179 | #define L2_1_MCU_DM2_BK3 0x0800134140 |
| 180 | #define L2_1_MCU_DM2_BK5 0x0800134240 |
| 181 | #define L2_1_MCU_DM2_BK7 0x0800134340 |
| 182 | |
| 183 | #define L2_1_MCU_DM3_BK1 0x0c00134040 |
| 184 | #define L2_1_MCU_DM3_BK3 0x0c00134140 |
| 185 | #define L2_1_MCU_DM3_BK5 0x0c00134240 |
| 186 | #define L2_1_MCU_DM3_BK7 0x0c00134340 |
| 187 | |
| 188 | #define L2_1_MCU_DM4_BK1 0x1000134040 |
| 189 | #define L2_1_MCU_DM4_BK3 0x1000134140 |
| 190 | #define L2_1_MCU_DM4_BK5 0x1000134240 |
| 191 | #define L2_1_MCU_DM4_BK7 0x1000134340 |
| 192 | |
| 193 | #define L2_1_MCU_DM5_BK1 0x1400134040 |
| 194 | #define L2_1_MCU_DM5_BK3 0x1400134140 |
| 195 | #define L2_1_MCU_DM5_BK5 0x1400134240 |
| 196 | #define L2_1_MCU_DM5_BK7 0x1400134340 |
| 197 | |
| 198 | #define L2_1_MCU_DM6_BK1 0x1800134040 |
| 199 | #define L2_1_MCU_DM6_BK3 0x1800134140 |
| 200 | #define L2_1_MCU_DM6_BK5 0x1800134240 |
| 201 | #define L2_1_MCU_DM6_BK7 0x1800134340 |
| 202 | |
| 203 | #define L2_1_MCU_DM7_BK1 0x1c00134040 |
| 204 | #define L2_1_MCU_DM7_BK3 0x1c00134140 |
| 205 | #define L2_1_MCU_DM7_BK5 0x1c00134240 |
| 206 | #define L2_1_MCU_DM7_BK7 0x1c00134340 |
| 207 | #endif |
| 208 | |
| 209 | |
| 210 | |
| 211 | #ifdef PM_2BANK |
| 212 | #define L20_MCU_DM0_BK0 0x0000134000 |
| 213 | #define L20_MCU_DM0_BK2 0x0000134080 |
| 214 | #define L20_MCU_DM0_BK4 0x0000134100 |
| 215 | #define L20_MCU_DM0_BK6 0x0000134180 |
| 216 | |
| 217 | #define L20_MCU_DM1_BK0 0x0200134000 |
| 218 | #define L20_MCU_DM1_BK2 0x0200134080 |
| 219 | #define L20_MCU_DM1_BK4 0x0200134100 |
| 220 | #define L20_MCU_DM1_BK6 0x0200134180 |
| 221 | |
| 222 | #define L20_MCU_DM2_BK0 0x0400134000 |
| 223 | #define L20_MCU_DM2_BK2 0x0400134080 |
| 224 | #define L20_MCU_DM2_BK4 0x0400134100 |
| 225 | #define L20_MCU_DM2_BK6 0x0400134180 |
| 226 | |
| 227 | #define L20_MCU_DM3_BK0 0x0600134000 |
| 228 | #define L20_MCU_DM3_BK2 0x0600134080 |
| 229 | #define L20_MCU_DM3_BK4 0x0600134100 |
| 230 | #define L20_MCU_DM3_BK6 0x0600134180 |
| 231 | |
| 232 | #define L20_MCU_DM4_BK0 0x0800134000 |
| 233 | #define L20_MCU_DM4_BK2 0x0800134080 |
| 234 | #define L20_MCU_DM4_BK4 0x0800134100 |
| 235 | #define L20_MCU_DM4_BK6 0x0800134180 |
| 236 | |
| 237 | #define L20_MCU_DM5_BK0 0x0a00134000 |
| 238 | #define L20_MCU_DM5_BK2 0x0a00134080 |
| 239 | #define L20_MCU_DM5_BK4 0x0a00134100 |
| 240 | #define L20_MCU_DM5_BK6 0x0a00134180 |
| 241 | |
| 242 | #define L20_MCU_DM6_BK0 0x0c00134000 |
| 243 | #define L20_MCU_DM6_BK2 0x0c00134080 |
| 244 | #define L20_MCU_DM6_BK4 0x0c00134100 |
| 245 | #define L20_MCU_DM6_BK6 0x0c00134180 |
| 246 | |
| 247 | #define L20_MCU_DM7_BK0 0x0e00134000 |
| 248 | #define L20_MCU_DM7_BK2 0x0e00134080 |
| 249 | #define L20_MCU_DM7_BK4 0x0e00134100 |
| 250 | #define L20_MCU_DM7_BK6 0x0e00134180 |
| 251 | |
| 252 | |
| 253 | #define L2_1_MCU_DM0_BK1 0x0000134040 |
| 254 | #define L2_1_MCU_DM0_BK3 0x00001340c0 |
| 255 | #define L2_1_MCU_DM0_BK5 0x0000134140 |
| 256 | #define L2_1_MCU_DM0_BK7 0x00001341c0 |
| 257 | |
| 258 | #define L2_1_MCU_DM1_BK1 0x0200134040 |
| 259 | #define L2_1_MCU_DM1_BK3 0x02001340c0 |
| 260 | #define L2_1_MCU_DM1_BK5 0x0200134140 |
| 261 | #define L2_1_MCU_DM1_BK7 0x02001341c0 |
| 262 | |
| 263 | #define L2_1_MCU_DM2_BK1 0x0400134040 |
| 264 | #define L2_1_MCU_DM2_BK3 0x04001340c0 |
| 265 | #define L2_1_MCU_DM2_BK5 0x0400134140 |
| 266 | #define L2_1_MCU_DM2_BK7 0x04001341c0 |
| 267 | |
| 268 | #define L2_1_MCU_DM3_BK1 0x0600134040 |
| 269 | #define L2_1_MCU_DM3_BK3 0x06001340c0 |
| 270 | #define L2_1_MCU_DM3_BK5 0x0600134140 |
| 271 | #define L2_1_MCU_DM3_BK7 0x06001341c0 |
| 272 | |
| 273 | #define L2_1_MCU_DM4_BK1 0x0800134040 |
| 274 | #define L2_1_MCU_DM4_BK3 0x08001340c0 |
| 275 | #define L2_1_MCU_DM4_BK5 0x0800134140 |
| 276 | #define L2_1_MCU_DM4_BK7 0x08001341c0 |
| 277 | |
| 278 | #define L2_1_MCU_DM5_BK1 0x0a00134040 |
| 279 | #define L2_1_MCU_DM5_BK3 0x0a001340c0 |
| 280 | #define L2_1_MCU_DM5_BK5 0x0a00134140 |
| 281 | #define L2_1_MCU_DM5_BK7 0x0a001341c0 |
| 282 | |
| 283 | #define L2_1_MCU_DM6_BK1 0x0c00134040 |
| 284 | #define L2_1_MCU_DM6_BK3 0x0c001340c0 |
| 285 | #define L2_1_MCU_DM6_BK5 0x0c00134140 |
| 286 | #define L2_1_MCU_DM6_BK7 0x0c001341c0 |
| 287 | |
| 288 | #define L2_1_MCU_DM7_BK1 0x0e00134040 |
| 289 | #define L2_1_MCU_DM7_BK3 0x0e001340c0 |
| 290 | #define L2_1_MCU_DM7_BK5 0x0e00134140 |
| 291 | #define L2_1_MCU_DM7_BK7 0x0e001341c0 |
| 292 | #endif |
| 293 | |
| 294 | #ifdef L2_OFF |
| 295 | #define L2_ON_OFF_DM 0x1 |
| 296 | #else |
| 297 | #define L2_ON_OFF_DM 0x0 |
| 298 | #endif |
| 299 | |
| 300 | |
| 301 | .text |
| 302 | .global main |
| 303 | |
| 304 | |
| 305 | main: |
| 306 | ta T_CHANGE_HPRIV |
| 307 | nop |
| 308 | |
| 309 | membar #Sync |
| 310 | |
| 311 | ta T_RD_THID |
| 312 | |
| 313 | ! Preserve Thread id in %g4 left shifted 28 bits |
| 314 | sllx %o1, 24, %g4 |
| 315 | nop |
| 316 | |
| 317 | branch_th: |
| 318 | ! Core0 |
| 319 | cmp %o1, 0x0 |
| 320 | be main_bank0 |
| 321 | nop |
| 322 | |
| 323 | cmp %o1, 0x1 |
| 324 | be main_bank1 |
| 325 | nop |
| 326 | |
| 327 | cmp %o1, 0x2 |
| 328 | be main_bank0 |
| 329 | nop |
| 330 | |
| 331 | cmp %o1, 0x3 |
| 332 | be main_bank1 |
| 333 | nop |
| 334 | |
| 335 | cmp %o1, 0x4 |
| 336 | be main_bank0 |
| 337 | nop |
| 338 | |
| 339 | cmp %o1, 0x5 |
| 340 | be main_bank1 |
| 341 | nop |
| 342 | |
| 343 | cmp %o1, 0x6 |
| 344 | be main_bank0 |
| 345 | nop |
| 346 | |
| 347 | cmp %o1, 0x7 |
| 348 | be main_bank1 |
| 349 | nop |
| 350 | |
| 351 | ! Core1 |
| 352 | cmp %o1, 0x8 |
| 353 | be main_bank0 |
| 354 | nop |
| 355 | |
| 356 | cmp %o1, 0x9 |
| 357 | be main_bank1 |
| 358 | nop |
| 359 | |
| 360 | cmp %o1, 0xa |
| 361 | be main_bank0 |
| 362 | nop |
| 363 | |
| 364 | cmp %o1, 0xb |
| 365 | be main_bank1 |
| 366 | nop |
| 367 | |
| 368 | cmp %o1, 0xc |
| 369 | be main_bank0 |
| 370 | nop |
| 371 | |
| 372 | cmp %o1, 0xd |
| 373 | be main_bank1 |
| 374 | nop |
| 375 | |
| 376 | cmp %o1, 0xe |
| 377 | be main_bank0 |
| 378 | nop |
| 379 | |
| 380 | cmp %o1, 0xf |
| 381 | be main_bank1 |
| 382 | nop |
| 383 | |
| 384 | ! Core2 |
| 385 | cmp %o1, 0x10 |
| 386 | be main_bank0 |
| 387 | nop |
| 388 | |
| 389 | cmp %o1, 0x11 |
| 390 | be main_bank1 |
| 391 | nop |
| 392 | |
| 393 | cmp %o1, 0x12 |
| 394 | be main_bank0 |
| 395 | nop |
| 396 | |
| 397 | cmp %o1, 0x13 |
| 398 | be main_bank1 |
| 399 | nop |
| 400 | |
| 401 | cmp %o1, 0x14 |
| 402 | be main_bank0 |
| 403 | nop |
| 404 | |
| 405 | cmp %o1, 0x15 |
| 406 | be main_bank1 |
| 407 | nop |
| 408 | |
| 409 | cmp %o1, 0x16 |
| 410 | be main_bank0 |
| 411 | nop |
| 412 | |
| 413 | cmp %o1, 0x17 |
| 414 | be main_bank1 |
| 415 | nop |
| 416 | |
| 417 | |
| 418 | ! Core3 |
| 419 | cmp %o1, 0x18 |
| 420 | be main_bank0 |
| 421 | nop |
| 422 | |
| 423 | cmp %o1, 0x19 |
| 424 | be main_bank1 |
| 425 | nop |
| 426 | |
| 427 | cmp %o1, 0x1a |
| 428 | be main_bank0 |
| 429 | nop |
| 430 | |
| 431 | cmp %o1, 0x1b |
| 432 | be main_bank1 |
| 433 | nop |
| 434 | |
| 435 | cmp %o1, 0x1c |
| 436 | be main_bank0 |
| 437 | nop |
| 438 | |
| 439 | cmp %o1, 0x1d |
| 440 | be main_bank1 |
| 441 | nop |
| 442 | |
| 443 | cmp %o1, 0x1e |
| 444 | be main_bank0 |
| 445 | nop |
| 446 | |
| 447 | cmp %o1, 0x1f |
| 448 | be main_bank1 |
| 449 | nop |
| 450 | |
| 451 | ! Core4 |
| 452 | cmp %o1, 0x20 |
| 453 | be main_bank0 |
| 454 | nop |
| 455 | |
| 456 | cmp %o1, 0x21 |
| 457 | be main_bank1 |
| 458 | nop |
| 459 | |
| 460 | cmp %o1, 0x22 |
| 461 | be main_bank0 |
| 462 | nop |
| 463 | |
| 464 | cmp %o1, 0x23 |
| 465 | be main_bank1 |
| 466 | nop |
| 467 | |
| 468 | cmp %o1, 0x24 |
| 469 | be main_bank0 |
| 470 | nop |
| 471 | |
| 472 | cmp %o1, 0x25 |
| 473 | be main_bank1 |
| 474 | nop |
| 475 | |
| 476 | cmp %o1, 0x26 |
| 477 | be main_bank0 |
| 478 | nop |
| 479 | |
| 480 | cmp %o1, 0x27 |
| 481 | be main_bank1 |
| 482 | nop |
| 483 | |
| 484 | ! Core5 |
| 485 | cmp %o1, 0x28 |
| 486 | be main_bank0 |
| 487 | nop |
| 488 | |
| 489 | cmp %o1, 0x29 |
| 490 | be main_bank1 |
| 491 | nop |
| 492 | |
| 493 | cmp %o1, 0x2a |
| 494 | be main_bank0 |
| 495 | nop |
| 496 | |
| 497 | cmp %o1, 0x2b |
| 498 | be main_bank1 |
| 499 | nop |
| 500 | |
| 501 | cmp %o1, 0x2c |
| 502 | be main_bank0 |
| 503 | nop |
| 504 | |
| 505 | cmp %o1, 0x2d |
| 506 | be main_bank1 |
| 507 | nop |
| 508 | |
| 509 | cmp %o1, 0x2e |
| 510 | be main_bank0 |
| 511 | nop |
| 512 | |
| 513 | cmp %o1, 0x2f |
| 514 | be main_bank1 |
| 515 | nop |
| 516 | |
| 517 | ! Core6 |
| 518 | cmp %o1, 0x30 |
| 519 | be main_bank0 |
| 520 | nop |
| 521 | |
| 522 | cmp %o1, 0x31 |
| 523 | be main_bank1 |
| 524 | nop |
| 525 | |
| 526 | cmp %o1, 0x32 |
| 527 | be main_bank0 |
| 528 | nop |
| 529 | |
| 530 | cmp %o1, 0x33 |
| 531 | be main_bank1 |
| 532 | nop |
| 533 | |
| 534 | cmp %o1, 0x34 |
| 535 | be main_bank0 |
| 536 | nop |
| 537 | |
| 538 | cmp %o1, 0x35 |
| 539 | be main_bank1 |
| 540 | nop |
| 541 | |
| 542 | cmp %o1, 0x36 |
| 543 | be main_bank0 |
| 544 | nop |
| 545 | |
| 546 | cmp %o1, 0x37 |
| 547 | be main_bank1 |
| 548 | nop |
| 549 | |
| 550 | ! Core7 |
| 551 | cmp %o1, 0x38 |
| 552 | be main_bank0 |
| 553 | nop |
| 554 | |
| 555 | cmp %o1, 0x39 |
| 556 | be main_bank1 |
| 557 | nop |
| 558 | |
| 559 | cmp %o1, 0x3a |
| 560 | be main_bank0 |
| 561 | nop |
| 562 | |
| 563 | cmp %o1, 0x3b |
| 564 | be main_bank1 |
| 565 | nop |
| 566 | |
| 567 | cmp %o1, 0x3c |
| 568 | be main_bank0 |
| 569 | nop |
| 570 | |
| 571 | cmp %o1, 0x3d |
| 572 | be main_bank1 |
| 573 | nop |
| 574 | |
| 575 | cmp %o1, 0x3e |
| 576 | be main_bank0 |
| 577 | nop |
| 578 | |
| 579 | cmp %o1, 0x3f |
| 580 | be main_bank1 |
| 581 | nop |
| 582 | |
| 583 | |
| 584 | ba test_failed |
| 585 | nop |
| 586 | |
| 587 | /********************** |
| 588 | L2 Bank 0 |
| 589 | **********************/ |
| 590 | main_bank0: |
| 591 | nop |
| 592 | nop |
| 593 | /******************* |
| 594 | DIMM 0,1 |
| 595 | *******************/ |
| 596 | L20_dimm01_init: |
| 597 | setx 0x1111111111110000, %g7, %g5 |
| 598 | |
| 599 | setx L20_MCU_DM0_BK0, %g7, %o0 |
| 600 | setx L20_MCU_DM0_BK2, %g7, %o1 |
| 601 | setx L20_MCU_DM0_BK4, %g7, %o2 |
| 602 | setx L20_MCU_DM0_BK6, %g7, %o3 |
| 603 | |
| 604 | setx L20_MCU_DM1_BK0, %g7, %o4 |
| 605 | setx L20_MCU_DM1_BK2, %g7, %o5 |
| 606 | setx L20_MCU_DM1_BK4, %g7, %o6 |
| 607 | setx L20_MCU_DM1_BK6, %g7, %o7 |
| 608 | |
| 609 | ! to make the addr unique for each thread in PA[28] and up |
| 610 | add %o0, %g4, %l0 |
| 611 | add %o1, %g4, %l1 |
| 612 | add %o2, %g4, %l2 |
| 613 | add %o3, %g4, %l3 |
| 614 | add %o4, %g4, %l4 |
| 615 | add %o5, %g4, %l5 |
| 616 | add %o6, %g4, %l6 |
| 617 | add %o7, %g4, %l7 |
| 618 | |
| 619 | setx 0xabcdef1234, %g7, %g2 |
| 620 | mov 0x1, %g1 |
| 621 | sllx %g1, 24, %g6 |
| 622 | |
| 623 | mov 0x1, %g7 |
| 624 | sllx %g7, 14, %g1 |
| 625 | set 0x4, %g3 |
| 626 | L20_dimm01_rd_wr: |
| 627 | !DIMM0,1 |
| 628 | stx %g5, [%l0] |
| 629 | stx %g5, [%l1] |
| 630 | stx %g5, [%l2] |
| 631 | stx %g5, [%l3] |
| 632 | stx %g5, [%l4] |
| 633 | stx %g5, [%l5] |
| 634 | stx %g5, [%l6] |
| 635 | stx %g5, [%l7] |
| 636 | |
| 637 | add %l0, %g6, %o0 |
| 638 | add %l1, %g6, %o1 |
| 639 | add %l2, %g6, %o2 |
| 640 | add %l3, %g6, %o3 |
| 641 | add %l4, %g6, %o4 |
| 642 | add %l5, %g6, %o5 |
| 643 | add %l6, %g6, %o6 |
| 644 | add %l7, %g6, %o7 |
| 645 | |
| 646 | ! cause wrb |
| 647 | stx %g2, [%o0] |
| 648 | stx %g2, [%o1] |
| 649 | stx %g2, [%o2] |
| 650 | stx %g2, [%o3] |
| 651 | stx %g2, [%o4] |
| 652 | stx %g2, [%o5] |
| 653 | stx %g2, [%o6] |
| 654 | stx %g2, [%o7] |
| 655 | |
| 656 | add %l0, %g1, %l0 |
| 657 | add %l1, %g1, %l1 |
| 658 | add %l2, %g1, %l2 |
| 659 | add %l3, %g1, %l3 |
| 660 | add %l4, %g1, %l4 |
| 661 | add %l5, %g1, %l5 |
| 662 | add %l6, %g1, %l6 |
| 663 | add %l7, %g1, %l7 |
| 664 | |
| 665 | add %o0, %g1, %o0 |
| 666 | add %o1, %g1, %o1 |
| 667 | add %o2, %g1, %o2 |
| 668 | add %o3, %g1, %o3 |
| 669 | add %o4, %g1, %o4 |
| 670 | add %o5, %g1, %o5 |
| 671 | add %o6, %g1, %o6 |
| 672 | add %o7, %g1, %o7 |
| 673 | |
| 674 | dec %g3 |
| 675 | brnz %g3, L20_dimm01_rd_wr |
| 676 | nop |
| 677 | |
| 678 | /******************* |
| 679 | DIMM2,3 |
| 680 | *******************/ |
| 681 | L20_dimm23_init: |
| 682 | setx 0x1111111111110000, %g7, %g5 |
| 683 | |
| 684 | setx L20_MCU_DM2_BK0, %g7, %o0 |
| 685 | setx L20_MCU_DM2_BK2, %g7, %o1 |
| 686 | setx L20_MCU_DM2_BK4, %g7, %o2 |
| 687 | setx L20_MCU_DM2_BK6, %g7, %o3 |
| 688 | |
| 689 | setx L20_MCU_DM3_BK0, %g7, %o4 |
| 690 | setx L20_MCU_DM3_BK2, %g7, %o5 |
| 691 | setx L20_MCU_DM3_BK4, %g7, %o6 |
| 692 | setx L20_MCU_DM3_BK6, %g7, %o7 |
| 693 | |
| 694 | ! to make the addr unique for each thread in PA[28] and up |
| 695 | add %o0, %g4, %l0 |
| 696 | add %o1, %g4, %l1 |
| 697 | add %o2, %g4, %l2 |
| 698 | add %o3, %g4, %l3 |
| 699 | add %o4, %g4, %l4 |
| 700 | add %o5, %g4, %l5 |
| 701 | add %o6, %g4, %l6 |
| 702 | add %o7, %g4, %l7 |
| 703 | |
| 704 | setx 0xabcdef1234, %g7, %g2 |
| 705 | mov 0x1, %g1 |
| 706 | sllx %g1, 22, %g6 |
| 707 | |
| 708 | mov 0x1, %g7 |
| 709 | sllx %g7, 14, %g1 |
| 710 | set 0x4, %g3 |
| 711 | |
| 712 | L20_dimm23_rd_wr: |
| 713 | stx %g5, [%l0] |
| 714 | stx %g5, [%l1] |
| 715 | stx %g5, [%l2] |
| 716 | stx %g5, [%l3] |
| 717 | stx %g5, [%l4] |
| 718 | stx %g5, [%l5] |
| 719 | stx %g5, [%l6] |
| 720 | stx %g5, [%l7] |
| 721 | |
| 722 | add %l0, %g6, %o0 |
| 723 | add %l1, %g6, %o1 |
| 724 | add %l2, %g6, %o2 |
| 725 | add %l3, %g6, %o3 |
| 726 | add %l4, %g6, %o4 |
| 727 | add %l5, %g6, %o5 |
| 728 | add %l6, %g6, %o6 |
| 729 | add %l7, %g6, %o7 |
| 730 | |
| 731 | ! cause wrb |
| 732 | stx %g2, [%o0] |
| 733 | stx %g2, [%o1] |
| 734 | stx %g2, [%o2] |
| 735 | stx %g2, [%o3] |
| 736 | stx %g2, [%o4] |
| 737 | stx %g2, [%o5] |
| 738 | stx %g2, [%o6] |
| 739 | stx %g2, [%o7] |
| 740 | |
| 741 | add %l0, %g1, %l0 |
| 742 | add %l1, %g1, %l1 |
| 743 | add %l2, %g1, %l2 |
| 744 | add %l3, %g1, %l3 |
| 745 | add %l4, %g1, %l4 |
| 746 | add %l5, %g1, %l5 |
| 747 | add %l6, %g1, %l6 |
| 748 | add %l7, %g1, %l7 |
| 749 | |
| 750 | add %o0, %g1, %o0 |
| 751 | add %o1, %g1, %o1 |
| 752 | add %o2, %g1, %o2 |
| 753 | add %o3, %g1, %o3 |
| 754 | add %o4, %g1, %o4 |
| 755 | add %o5, %g1, %o5 |
| 756 | add %o6, %g1, %o6 |
| 757 | add %o7, %g1, %o7 |
| 758 | |
| 759 | dec %g3 |
| 760 | brnz %g3, L20_dimm23_rd_wr |
| 761 | nop |
| 762 | |
| 763 | /******************************** |
| 764 | * DIMM 4, 5 |
| 765 | *********************************/ |
| 766 | L20_dimm45_init: |
| 767 | setx 0x1111111111110000, %g7, %g5 |
| 768 | |
| 769 | setx L20_MCU_DM4_BK0, %g7, %o0 |
| 770 | setx L20_MCU_DM4_BK2, %g7, %o1 |
| 771 | setx L20_MCU_DM4_BK4, %g7, %o2 |
| 772 | setx L20_MCU_DM4_BK6, %g7, %o3 |
| 773 | |
| 774 | setx L20_MCU_DM5_BK0, %g7, %o4 |
| 775 | setx L20_MCU_DM5_BK2, %g7, %o5 |
| 776 | setx L20_MCU_DM5_BK4, %g7, %o6 |
| 777 | setx L20_MCU_DM5_BK6, %g7, %o7 |
| 778 | |
| 779 | ! to make the addr unique for each thread in PA[28] and up |
| 780 | add %o0, %g4, %l0 |
| 781 | add %o1, %g4, %l1 |
| 782 | add %o2, %g4, %l2 |
| 783 | add %o3, %g4, %l3 |
| 784 | add %o4, %g4, %l4 |
| 785 | add %o5, %g4, %l5 |
| 786 | add %o6, %g4, %l6 |
| 787 | add %o7, %g4, %l7 |
| 788 | |
| 789 | setx 0xabcdef1234, %g7, %g2 |
| 790 | mov 0x1, %g1 |
| 791 | sllx %g1, 22, %g6 |
| 792 | |
| 793 | mov 0x1, %g7 |
| 794 | sllx %g7, 14, %g1 |
| 795 | set 0x4, %g3 |
| 796 | |
| 797 | L20_dimm45_rd_wr: |
| 798 | stx %g5, [%l0] |
| 799 | stx %g5, [%l1] |
| 800 | stx %g5, [%l2] |
| 801 | stx %g5, [%l3] |
| 802 | stx %g5, [%l4] |
| 803 | stx %g5, [%l5] |
| 804 | stx %g5, [%l6] |
| 805 | stx %g5, [%l7] |
| 806 | |
| 807 | add %l0, %g6, %o0 |
| 808 | add %l1, %g6, %o1 |
| 809 | add %l2, %g6, %o2 |
| 810 | add %l3, %g6, %o3 |
| 811 | add %l4, %g6, %o4 |
| 812 | add %l5, %g6, %o5 |
| 813 | add %l6, %g6, %o6 |
| 814 | add %l7, %g6, %o7 |
| 815 | |
| 816 | ! cause wrb |
| 817 | stx %g2, [%o0] |
| 818 | stx %g2, [%o1] |
| 819 | stx %g2, [%o2] |
| 820 | stx %g2, [%o3] |
| 821 | stx %g2, [%o4] |
| 822 | stx %g2, [%o5] |
| 823 | stx %g2, [%o6] |
| 824 | stx %g2, [%o7] |
| 825 | |
| 826 | add %l0, %g1, %l0 |
| 827 | add %l1, %g1, %l1 |
| 828 | add %l2, %g1, %l2 |
| 829 | add %l3, %g1, %l3 |
| 830 | add %l4, %g1, %l4 |
| 831 | add %l5, %g1, %l5 |
| 832 | add %l6, %g1, %l6 |
| 833 | add %l7, %g1, %l7 |
| 834 | |
| 835 | add %o0, %g1, %o0 |
| 836 | add %o1, %g1, %o1 |
| 837 | add %o2, %g1, %o2 |
| 838 | add %o3, %g1, %o3 |
| 839 | add %o4, %g1, %o4 |
| 840 | add %o5, %g1, %o5 |
| 841 | add %o6, %g1, %o6 |
| 842 | add %o7, %g1, %o7 |
| 843 | |
| 844 | dec %g3 |
| 845 | brnz %g3, L20_dimm45_rd_wr |
| 846 | nop |
| 847 | |
| 848 | /******************************** |
| 849 | * DIMM 6, 7 |
| 850 | *********************************/ |
| 851 | L20_dimm67_init: |
| 852 | setx 0x1111111111110000, %g7, %g5 |
| 853 | |
| 854 | setx L20_MCU_DM6_BK0, %g7, %o0 |
| 855 | setx L20_MCU_DM6_BK2, %g7, %o1 |
| 856 | setx L20_MCU_DM6_BK4, %g7, %o2 |
| 857 | setx L20_MCU_DM6_BK6, %g7, %o3 |
| 858 | |
| 859 | setx L20_MCU_DM7_BK0, %g7, %o4 |
| 860 | setx L20_MCU_DM7_BK2, %g7, %o5 |
| 861 | setx L20_MCU_DM7_BK4, %g7, %o6 |
| 862 | setx L20_MCU_DM7_BK6, %g7, %o7 |
| 863 | |
| 864 | ! to make the addr unique for each thread in PA[28] and up |
| 865 | add %o0, %g4, %l0 |
| 866 | add %o1, %g4, %l1 |
| 867 | add %o2, %g4, %l2 |
| 868 | add %o3, %g4, %l3 |
| 869 | add %o4, %g4, %l4 |
| 870 | add %o5, %g4, %l5 |
| 871 | add %o6, %g4, %l6 |
| 872 | add %o7, %g4, %l7 |
| 873 | |
| 874 | setx 0xabcdef1234, %g7, %g2 |
| 875 | mov 0x1, %g1 |
| 876 | sllx %g1, 22, %g6 |
| 877 | |
| 878 | mov 0x1, %g7 |
| 879 | sllx %g7, 14, %g1 |
| 880 | set 0x4, %g3 |
| 881 | |
| 882 | L20_dimm67_rd_wr: |
| 883 | stx %g5, [%l0] |
| 884 | stx %g5, [%l1] |
| 885 | stx %g5, [%l2] |
| 886 | stx %g5, [%l3] |
| 887 | stx %g5, [%l4] |
| 888 | stx %g5, [%l5] |
| 889 | stx %g5, [%l6] |
| 890 | stx %g5, [%l7] |
| 891 | |
| 892 | add %l0, %g6, %o0 |
| 893 | add %l1, %g6, %o1 |
| 894 | add %l2, %g6, %o2 |
| 895 | add %l3, %g6, %o3 |
| 896 | add %l4, %g6, %o4 |
| 897 | add %l5, %g6, %o5 |
| 898 | add %l6, %g6, %o6 |
| 899 | add %l7, %g6, %o7 |
| 900 | |
| 901 | ! cause wrb |
| 902 | stx %g2, [%o0] |
| 903 | stx %g2, [%o1] |
| 904 | stx %g2, [%o2] |
| 905 | stx %g2, [%o3] |
| 906 | stx %g2, [%o4] |
| 907 | stx %g2, [%o5] |
| 908 | stx %g2, [%o6] |
| 909 | stx %g2, [%o7] |
| 910 | |
| 911 | add %l0, %g1, %l0 |
| 912 | add %l1, %g1, %l1 |
| 913 | add %l2, %g1, %l2 |
| 914 | add %l3, %g1, %l3 |
| 915 | add %l4, %g1, %l4 |
| 916 | add %l5, %g1, %l5 |
| 917 | add %l6, %g1, %l6 |
| 918 | add %l7, %g1, %l7 |
| 919 | |
| 920 | add %o0, %g1, %o0 |
| 921 | add %o1, %g1, %o1 |
| 922 | add %o2, %g1, %o2 |
| 923 | add %o3, %g1, %o3 |
| 924 | add %o4, %g1, %o4 |
| 925 | add %o5, %g1, %o5 |
| 926 | add %o6, %g1, %o6 |
| 927 | add %o7, %g1, %o7 |
| 928 | |
| 929 | dec %g3 |
| 930 | brnz %g3, L20_dimm67_rd_wr |
| 931 | nop |
| 932 | |
| 933 | /*********************************** |
| 934 | L2 Bank 1 |
| 935 | ***********************************/ |
| 936 | main_bank1: |
| 937 | nop |
| 938 | nop |
| 939 | |
| 940 | /******************************** |
| 941 | * DIMM 0, 1 |
| 942 | *********************************/ |
| 943 | L2_1_dimm01_init: |
| 944 | setx 0x1111111111110000, %g7, %g5 |
| 945 | |
| 946 | setx L2_1_MCU_DM0_BK1, %g7, %o0 |
| 947 | setx L2_1_MCU_DM0_BK3, %g7, %o1 |
| 948 | setx L2_1_MCU_DM0_BK5, %g7, %o2 |
| 949 | setx L2_1_MCU_DM0_BK7, %g7, %o3 |
| 950 | |
| 951 | setx L2_1_MCU_DM1_BK1, %g7, %o4 |
| 952 | setx L2_1_MCU_DM1_BK3, %g7, %o5 |
| 953 | setx L2_1_MCU_DM1_BK5, %g7, %o6 |
| 954 | setx L2_1_MCU_DM1_BK7, %g7, %o7 |
| 955 | |
| 956 | ! to make the addr unique for each thread in PA[28] and up |
| 957 | add %o0, %g4, %l0 |
| 958 | add %o1, %g4, %l1 |
| 959 | add %o2, %g4, %l2 |
| 960 | add %o3, %g4, %l3 |
| 961 | add %o4, %g4, %l4 |
| 962 | add %o5, %g4, %l5 |
| 963 | add %o6, %g4, %l6 |
| 964 | add %o7, %g4, %l7 |
| 965 | |
| 966 | setx 0xabcdef1234, %g7, %g2 |
| 967 | mov 0x1, %g1 |
| 968 | sllx %g1, 22, %g6 |
| 969 | |
| 970 | mov 0x1, %g7 |
| 971 | sllx %g7, 14, %g1 |
| 972 | set 0x4, %g3 |
| 973 | |
| 974 | L2_1_dimm01_rd_wr: |
| 975 | stx %g5, [%l0] |
| 976 | stx %g5, [%l1] |
| 977 | stx %g5, [%l2] |
| 978 | stx %g5, [%l3] |
| 979 | stx %g5, [%l4] |
| 980 | stx %g5, [%l5] |
| 981 | stx %g5, [%l6] |
| 982 | stx %g5, [%l7] |
| 983 | |
| 984 | add %l0, %g6, %o0 |
| 985 | add %l1, %g6, %o1 |
| 986 | add %l2, %g6, %o2 |
| 987 | add %l3, %g6, %o3 |
| 988 | add %l4, %g6, %o4 |
| 989 | add %l5, %g6, %o5 |
| 990 | add %l6, %g6, %o6 |
| 991 | add %l7, %g6, %o7 |
| 992 | |
| 993 | ! cause wrb |
| 994 | stx %g2, [%o0] |
| 995 | stx %g2, [%o1] |
| 996 | stx %g2, [%o2] |
| 997 | stx %g2, [%o3] |
| 998 | stx %g2, [%o4] |
| 999 | stx %g2, [%o5] |
| 1000 | stx %g2, [%o6] |
| 1001 | stx %g2, [%o7] |
| 1002 | |
| 1003 | add %l0, %g1, %l0 |
| 1004 | add %l1, %g1, %l1 |
| 1005 | add %l2, %g1, %l2 |
| 1006 | add %l3, %g1, %l3 |
| 1007 | add %l4, %g1, %l4 |
| 1008 | add %l5, %g1, %l5 |
| 1009 | add %l6, %g1, %l6 |
| 1010 | add %l7, %g1, %l7 |
| 1011 | |
| 1012 | add %o0, %g1, %o0 |
| 1013 | add %o1, %g1, %o1 |
| 1014 | add %o2, %g1, %o2 |
| 1015 | add %o3, %g1, %o3 |
| 1016 | add %o4, %g1, %o4 |
| 1017 | add %o5, %g1, %o5 |
| 1018 | add %o6, %g1, %o6 |
| 1019 | add %o7, %g1, %o7 |
| 1020 | |
| 1021 | dec %g3 |
| 1022 | brnz %g3, L2_1_dimm01_rd_wr |
| 1023 | nop |
| 1024 | |
| 1025 | /******************************** |
| 1026 | * DIMM 2, 3 |
| 1027 | *********************************/ |
| 1028 | L2_1_dimm23_init: |
| 1029 | setx 0x1111111111110000, %g7, %g5 |
| 1030 | |
| 1031 | setx L2_1_MCU_DM0_BK1, %g7, %o0 |
| 1032 | setx L2_1_MCU_DM0_BK3, %g7, %o1 |
| 1033 | setx L2_1_MCU_DM0_BK5, %g7, %o2 |
| 1034 | setx L2_1_MCU_DM0_BK7, %g7, %o3 |
| 1035 | |
| 1036 | setx L2_1_MCU_DM1_BK1, %g7, %o4 |
| 1037 | setx L2_1_MCU_DM1_BK3, %g7, %o5 |
| 1038 | setx L2_1_MCU_DM1_BK5, %g7, %o6 |
| 1039 | setx L2_1_MCU_DM1_BK7, %g7, %o7 |
| 1040 | |
| 1041 | ! to make the addr unique for each thread in PA[28] and up |
| 1042 | add %o0, %g4, %l0 |
| 1043 | add %o1, %g4, %l1 |
| 1044 | add %o2, %g4, %l2 |
| 1045 | add %o3, %g4, %l3 |
| 1046 | add %o4, %g4, %l4 |
| 1047 | add %o5, %g4, %l5 |
| 1048 | add %o6, %g4, %l6 |
| 1049 | add %o7, %g4, %l7 |
| 1050 | |
| 1051 | setx 0xabcdef1234, %g7, %g2 |
| 1052 | mov 0x1, %g1 |
| 1053 | sllx %g1, 22, %g6 |
| 1054 | |
| 1055 | mov 0x1, %g7 |
| 1056 | sllx %g7, 14, %g1 |
| 1057 | set 0x4, %g3 |
| 1058 | |
| 1059 | L2_1_dimm23_rd_wr: |
| 1060 | stx %g5, [%l0] |
| 1061 | stx %g5, [%l1] |
| 1062 | stx %g5, [%l2] |
| 1063 | stx %g5, [%l3] |
| 1064 | stx %g5, [%l4] |
| 1065 | stx %g5, [%l5] |
| 1066 | stx %g5, [%l6] |
| 1067 | stx %g5, [%l7] |
| 1068 | |
| 1069 | add %l0, %g6, %o0 |
| 1070 | add %l1, %g6, %o1 |
| 1071 | add %l2, %g6, %o2 |
| 1072 | add %l3, %g6, %o3 |
| 1073 | add %l4, %g6, %o4 |
| 1074 | add %l5, %g6, %o5 |
| 1075 | add %l6, %g6, %o6 |
| 1076 | add %l7, %g6, %o7 |
| 1077 | |
| 1078 | ! cause wrb |
| 1079 | stx %g2, [%o0] |
| 1080 | stx %g2, [%o1] |
| 1081 | stx %g2, [%o2] |
| 1082 | stx %g2, [%o3] |
| 1083 | stx %g2, [%o4] |
| 1084 | stx %g2, [%o5] |
| 1085 | stx %g2, [%o6] |
| 1086 | stx %g2, [%o7] |
| 1087 | |
| 1088 | add %l0, %g1, %l0 |
| 1089 | add %l1, %g1, %l1 |
| 1090 | add %l2, %g1, %l2 |
| 1091 | add %l3, %g1, %l3 |
| 1092 | add %l4, %g1, %l4 |
| 1093 | add %l5, %g1, %l5 |
| 1094 | add %l6, %g1, %l6 |
| 1095 | add %l7, %g1, %l7 |
| 1096 | |
| 1097 | add %o0, %g1, %o0 |
| 1098 | add %o1, %g1, %o1 |
| 1099 | add %o2, %g1, %o2 |
| 1100 | add %o3, %g1, %o3 |
| 1101 | add %o4, %g1, %o4 |
| 1102 | add %o5, %g1, %o5 |
| 1103 | add %o6, %g1, %o6 |
| 1104 | add %o7, %g1, %o7 |
| 1105 | |
| 1106 | dec %g3 |
| 1107 | brnz %g3, L2_1_dimm23_rd_wr |
| 1108 | nop |
| 1109 | |
| 1110 | /******************************** |
| 1111 | * DIMM4, 5 |
| 1112 | *********************************/ |
| 1113 | L2_1_dimm45_init: |
| 1114 | setx 0x1111111111110000, %g7, %g5 |
| 1115 | |
| 1116 | setx L2_1_MCU_DM0_BK1, %g7, %o0 |
| 1117 | setx L2_1_MCU_DM0_BK3, %g7, %o1 |
| 1118 | setx L2_1_MCU_DM0_BK5, %g7, %o2 |
| 1119 | setx L2_1_MCU_DM0_BK7, %g7, %o3 |
| 1120 | |
| 1121 | setx L2_1_MCU_DM1_BK1, %g7, %o4 |
| 1122 | setx L2_1_MCU_DM1_BK3, %g7, %o5 |
| 1123 | setx L2_1_MCU_DM1_BK5, %g7, %o6 |
| 1124 | setx L2_1_MCU_DM1_BK7, %g7, %o7 |
| 1125 | |
| 1126 | ! to make the addr unique for each thread in PA[28] and up |
| 1127 | add %o0, %g4, %l0 |
| 1128 | add %o1, %g4, %l1 |
| 1129 | add %o2, %g4, %l2 |
| 1130 | add %o3, %g4, %l3 |
| 1131 | add %o4, %g4, %l4 |
| 1132 | add %o5, %g4, %l5 |
| 1133 | add %o6, %g4, %l6 |
| 1134 | add %o7, %g4, %l7 |
| 1135 | |
| 1136 | setx 0xabcdef1234, %g7, %g2 |
| 1137 | mov 0x1, %g1 |
| 1138 | sllx %g1, 22, %g6 |
| 1139 | |
| 1140 | mov 0x1, %g7 |
| 1141 | sllx %g7, 14, %g1 |
| 1142 | set 0x4, %g3 |
| 1143 | |
| 1144 | L2_1_dimm45_rd_wr: |
| 1145 | stx %g5, [%l0] |
| 1146 | stx %g5, [%l1] |
| 1147 | stx %g5, [%l2] |
| 1148 | stx %g5, [%l3] |
| 1149 | stx %g5, [%l4] |
| 1150 | stx %g5, [%l5] |
| 1151 | stx %g5, [%l6] |
| 1152 | stx %g5, [%l7] |
| 1153 | |
| 1154 | add %l0, %g6, %o0 |
| 1155 | add %l1, %g6, %o1 |
| 1156 | add %l2, %g6, %o2 |
| 1157 | add %l3, %g6, %o3 |
| 1158 | add %l4, %g6, %o4 |
| 1159 | add %l5, %g6, %o5 |
| 1160 | add %l6, %g6, %o6 |
| 1161 | add %l7, %g6, %o7 |
| 1162 | |
| 1163 | ! cause wrb |
| 1164 | stx %g2, [%o0] |
| 1165 | stx %g2, [%o1] |
| 1166 | stx %g2, [%o2] |
| 1167 | stx %g2, [%o3] |
| 1168 | stx %g2, [%o4] |
| 1169 | stx %g2, [%o5] |
| 1170 | stx %g2, [%o6] |
| 1171 | stx %g2, [%o7] |
| 1172 | |
| 1173 | add %l0, %g1, %l0 |
| 1174 | add %l1, %g1, %l1 |
| 1175 | add %l2, %g1, %l2 |
| 1176 | add %l3, %g1, %l3 |
| 1177 | add %l4, %g1, %l4 |
| 1178 | add %l5, %g1, %l5 |
| 1179 | add %l6, %g1, %l6 |
| 1180 | add %l7, %g1, %l7 |
| 1181 | |
| 1182 | add %o0, %g1, %o0 |
| 1183 | add %o1, %g1, %o1 |
| 1184 | add %o2, %g1, %o2 |
| 1185 | add %o3, %g1, %o3 |
| 1186 | add %o4, %g1, %o4 |
| 1187 | add %o5, %g1, %o5 |
| 1188 | add %o6, %g1, %o6 |
| 1189 | add %o7, %g1, %o7 |
| 1190 | |
| 1191 | dec %g3 |
| 1192 | brnz %g3, L2_1_dimm45_rd_wr |
| 1193 | nop |
| 1194 | |
| 1195 | /******************************** |
| 1196 | * DIMM 6, 7 |
| 1197 | *********************************/ |
| 1198 | L2_1_dimm67_init: |
| 1199 | setx 0x1111111111110000, %g7, %g5 |
| 1200 | |
| 1201 | setx L2_1_MCU_DM0_BK1, %g7, %o0 |
| 1202 | setx L2_1_MCU_DM0_BK3, %g7, %o1 |
| 1203 | setx L2_1_MCU_DM0_BK5, %g7, %o2 |
| 1204 | setx L2_1_MCU_DM0_BK7, %g7, %o3 |
| 1205 | |
| 1206 | setx L2_1_MCU_DM1_BK1, %g7, %o4 |
| 1207 | setx L2_1_MCU_DM1_BK3, %g7, %o5 |
| 1208 | setx L2_1_MCU_DM1_BK5, %g7, %o6 |
| 1209 | setx L2_1_MCU_DM1_BK7, %g7, %o7 |
| 1210 | |
| 1211 | ! to make the addr unique for each thread in PA[28] and up |
| 1212 | add %o0, %g4, %l0 |
| 1213 | add %o1, %g4, %l1 |
| 1214 | add %o2, %g4, %l2 |
| 1215 | add %o3, %g4, %l3 |
| 1216 | add %o4, %g4, %l4 |
| 1217 | add %o5, %g4, %l5 |
| 1218 | add %o6, %g4, %l6 |
| 1219 | add %o7, %g4, %l7 |
| 1220 | |
| 1221 | setx 0xabcdef1234, %g7, %g2 |
| 1222 | mov 0x1, %g1 |
| 1223 | sllx %g1, 22, %g6 |
| 1224 | |
| 1225 | mov 0x1, %g7 |
| 1226 | sllx %g7, 14, %g1 |
| 1227 | set 0x4, %g3 |
| 1228 | |
| 1229 | L2_1_dimm67_rd_wr: |
| 1230 | stx %g5, [%l0] |
| 1231 | stx %g5, [%l1] |
| 1232 | stx %g5, [%l2] |
| 1233 | stx %g5, [%l3] |
| 1234 | stx %g5, [%l4] |
| 1235 | stx %g5, [%l5] |
| 1236 | stx %g5, [%l6] |
| 1237 | stx %g5, [%l7] |
| 1238 | |
| 1239 | add %l0, %g6, %o0 |
| 1240 | add %l1, %g6, %o1 |
| 1241 | add %l2, %g6, %o2 |
| 1242 | add %l3, %g6, %o3 |
| 1243 | add %l4, %g6, %o4 |
| 1244 | add %l5, %g6, %o5 |
| 1245 | add %l6, %g6, %o6 |
| 1246 | add %l7, %g6, %o7 |
| 1247 | |
| 1248 | ! cause wrb |
| 1249 | stx %g2, [%o0] |
| 1250 | stx %g2, [%o1] |
| 1251 | stx %g2, [%o2] |
| 1252 | stx %g2, [%o3] |
| 1253 | stx %g2, [%o4] |
| 1254 | stx %g2, [%o5] |
| 1255 | stx %g2, [%o6] |
| 1256 | stx %g2, [%o7] |
| 1257 | |
| 1258 | |
| 1259 | add %l0, %g1, %l0 |
| 1260 | add %l1, %g1, %l1 |
| 1261 | add %l2, %g1, %l2 |
| 1262 | add %l3, %g1, %l3 |
| 1263 | add %l4, %g1, %l4 |
| 1264 | add %l5, %g1, %l5 |
| 1265 | add %l6, %g1, %l6 |
| 1266 | add %l7, %g1, %l7 |
| 1267 | |
| 1268 | add %o0, %g1, %o0 |
| 1269 | add %o1, %g1, %o1 |
| 1270 | add %o2, %g1, %o2 |
| 1271 | add %o3, %g1, %o3 |
| 1272 | add %o4, %g1, %o4 |
| 1273 | add %o5, %g1, %o5 |
| 1274 | add %o6, %g1, %o6 |
| 1275 | add %o7, %g1, %o7 |
| 1276 | |
| 1277 | dec %g3 |
| 1278 | brnz %g3, L2_1_dimm67_rd_wr |
| 1279 | nop |
| 1280 | |
| 1281 | /****************************************************** |
| 1282 | * Exit code |
| 1283 | *******************************************************/ |
| 1284 | |
| 1285 | test_passed: |
| 1286 | EXIT_GOOD |
| 1287 | |
| 1288 | test_failed: |
| 1289 | EXIT_BAD |
| 1290 | |