| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: memop_l2_disable.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | #define L2_CONTROL_REG_ADDR 0xa900000000 |
| 41 | |
| 42 | #include "hboot.s" |
| 43 | #include "asi_s.h" |
| 44 | |
| 45 | /************************************************************************ |
| 46 | Test case code start |
| 47 | ************************************************************************/ |
| 48 | |
| 49 | .text |
| 50 | .global main |
| 51 | |
| 52 | main: |
| 53 | ta T_CHANGE_HPRIV |
| 54 | |
| 55 | ! Disable the L1 caches. |
| 56 | |
| 57 | ldxa [%g0]ASI_LSU_CONTROL, %g5 |
| 58 | xor %g5, 0x3, %g5 ! 0 the D$ & L$ enable bits |
| 59 | stxa %g5, [%g0]ASI_LSU_CONTROL |
| 60 | membar #Sync |
| 61 | |
| 62 | ! Disable the L2 cache. |
| 63 | l2_disable: |
| 64 | ! setx L2_CONTROL_REG_ADDR, %g1, %g4 |
| 65 | ! ldx [%g4], %g6 |
| 66 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 67 | ! stx %g6, [%g4] |
| 68 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 69 | ! ldx [%g4], %g6 |
| 70 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 71 | ! stx %g6, [%g4] |
| 72 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 73 | ! ldx [%g4], %g6 |
| 74 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 75 | ! stx %g6, [%g4] |
| 76 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 77 | ! ldx [%g4], %g6 |
| 78 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 79 | ! stx %g6, [%g4] |
| 80 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 81 | ! ldx [%g4], %g6 |
| 82 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 83 | ! stx %g6, [%g4] |
| 84 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 85 | ! ldx [%g4], %g6 |
| 86 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 87 | ! stx %g6, [%g4] |
| 88 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 89 | ! ldx [%g4], %g6 |
| 90 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 91 | ! stx %g6, [%g4] |
| 92 | ! add %g4, 0x40, %g4 ! point to next L2_CONTROL_REG |
| 93 | ! ldx [%g4], %g6 |
| 94 | ! or %g6, 1, %g6 ! Disable 1st L2 bank |
| 95 | ! stx %g6, [%g4] |
| 96 | |
| 97 | ! Set up data to use. |
| 98 | |
| 99 | mov %g0, %l0 ! l0 = data to use |
| 100 | setx 0x0001000100010001, %g1, %g7 ! value to increment data by |
| 101 | |
| 102 | ! For L2$ bank 0 address space, addr[8:6] = 0x0 |
| 103 | ! 8 stores, 8 loads and check data |
| 104 | bank0_store: |
| 105 | setx data1, %g1, %g2 |
| 106 | mov %l0, %l1 |
| 107 | stx %l1, [%g2] |
| 108 | add %l1, %g7, %l1 |
| 109 | stx %l1, [%g2 + 0x8] |
| 110 | add %l1, %g7, %l1 |
| 111 | stx %l1, [%g2 + 0x10] |
| 112 | add %l1, %g7, %l1 |
| 113 | stx %l1, [%g2 + 0x18] |
| 114 | add %l1, %g7, %l1 |
| 115 | stx %l1, [%g2 + 0x20] |
| 116 | add %l1, %g7, %l1 |
| 117 | stx %l1, [%g2 + 0x28] |
| 118 | add %l1, %g7, %l1 |
| 119 | stx %l1, [%g2 + 0x30] |
| 120 | add %l1, %g7, %l1 |
| 121 | stx %l1, [%g2 + 0x38] |
| 122 | add %l1, %g7, %l1 |
| 123 | bank0_load: |
| 124 | ldx [%g2], %l2 |
| 125 | cmp %l0, %l2 |
| 126 | bne test_failed |
| 127 | add %l0, %g7, %l0 |
| 128 | ldx [%g2 + 0x8], %l2 |
| 129 | cmp %l0, %l2 |
| 130 | bne test_failed |
| 131 | add %l0, %g7, %l0 |
| 132 | ldx [%g2 + 0x10], %l2 |
| 133 | cmp %l0, %l2 |
| 134 | bne test_failed |
| 135 | add %l0, %g7, %l0 |
| 136 | ldx [%g2 + 0x18], %l2 |
| 137 | cmp %l0, %l2 |
| 138 | bne test_failed |
| 139 | add %l0, %g7, %l0 |
| 140 | ldx [%g2 + 0x20], %l2 |
| 141 | cmp %l0, %l2 |
| 142 | bne test_failed |
| 143 | add %l0, %g7, %l0 |
| 144 | ldx [%g2 + 0x28], %l2 |
| 145 | cmp %l0, %l2 |
| 146 | bne test_failed |
| 147 | add %l0, %g7, %l0 |
| 148 | ldx [%g2 + 0x30], %l2 |
| 149 | cmp %l0, %l2 |
| 150 | bne test_failed |
| 151 | add %l0, %g7, %l0 |
| 152 | ldx [%g2 + 0x38], %l2 |
| 153 | cmp %l0, %l2 |
| 154 | bne test_failed |
| 155 | add %l0, %g7, %l0 |
| 156 | |
| 157 | ! For L2$ bank 1 address space, addr[8:6] = 0x0 |
| 158 | ! 8 stores, 8 loads and check data |
| 159 | bank1_store: |
| 160 | setx data2, %g1, %g2 |
| 161 | mov %l0, %l1 |
| 162 | stx %l1, [%g2] |
| 163 | add %l1, %g7, %l1 |
| 164 | stx %l1, [%g2 + 0x8] |
| 165 | add %l1, %g7, %l1 |
| 166 | stx %l1, [%g2 + 0x10] |
| 167 | add %l1, %g7, %l1 |
| 168 | stx %l1, [%g2 + 0x18] |
| 169 | add %l1, %g7, %l1 |
| 170 | stx %l1, [%g2 + 0x20] |
| 171 | add %l1, %g7, %l1 |
| 172 | stx %l1, [%g2 + 0x28] |
| 173 | add %l1, %g7, %l1 |
| 174 | stx %l1, [%g2 + 0x30] |
| 175 | add %l1, %g7, %l1 |
| 176 | stx %l1, [%g2 + 0x38] |
| 177 | add %l1, %g7, %l1 |
| 178 | bank1_load: |
| 179 | ldx [%g2], %l2 |
| 180 | cmp %l0, %l2 |
| 181 | bne test_failed |
| 182 | add %l0, %g7, %l0 |
| 183 | ldx [%g2 + 0x8], %l2 |
| 184 | cmp %l0, %l2 |
| 185 | bne test_failed |
| 186 | add %l0, %g7, %l0 |
| 187 | ldx [%g2 + 0x10], %l2 |
| 188 | cmp %l0, %l2 |
| 189 | bne test_failed |
| 190 | add %l0, %g7, %l0 |
| 191 | ldx [%g2 + 0x18], %l2 |
| 192 | cmp %l0, %l2 |
| 193 | bne test_failed |
| 194 | add %l0, %g7, %l0 |
| 195 | ldx [%g2 + 0x20], %l2 |
| 196 | cmp %l0, %l2 |
| 197 | bne test_failed |
| 198 | add %l0, %g7, %l0 |
| 199 | ldx [%g2 + 0x28], %l2 |
| 200 | cmp %l0, %l2 |
| 201 | bne test_failed |
| 202 | add %l0, %g7, %l0 |
| 203 | ldx [%g2 + 0x30], %l2 |
| 204 | cmp %l0, %l2 |
| 205 | bne test_failed |
| 206 | add %l0, %g7, %l0 |
| 207 | ldx [%g2 + 0x38], %l2 |
| 208 | cmp %l0, %l2 |
| 209 | bne test_failed |
| 210 | add %l0, %g7, %l0 |
| 211 | |
| 212 | ! For L2$ bank 2 address space, addr[8:6] = 0x0 |
| 213 | ! 8 stores, 8 loads and check data |
| 214 | bank2_store: |
| 215 | setx data3, %g1, %g2 |
| 216 | mov %l0, %l1 |
| 217 | stx %l1, [%g2] |
| 218 | add %l1, %g7, %l1 |
| 219 | stx %l1, [%g2 + 0x8] |
| 220 | add %l1, %g7, %l1 |
| 221 | stx %l1, [%g2 + 0x10] |
| 222 | add %l1, %g7, %l1 |
| 223 | stx %l1, [%g2 + 0x18] |
| 224 | add %l1, %g7, %l1 |
| 225 | stx %l1, [%g2 + 0x20] |
| 226 | add %l1, %g7, %l1 |
| 227 | stx %l1, [%g2 + 0x28] |
| 228 | add %l1, %g7, %l1 |
| 229 | stx %l1, [%g2 + 0x30] |
| 230 | add %l1, %g7, %l1 |
| 231 | stx %l1, [%g2 + 0x38] |
| 232 | add %l1, %g7, %l1 |
| 233 | bank2_load: |
| 234 | ldx [%g2], %l2 |
| 235 | cmp %l0, %l2 |
| 236 | bne test_failed |
| 237 | add %l0, %g7, %l0 |
| 238 | ldx [%g2 + 0x8], %l2 |
| 239 | cmp %l0, %l2 |
| 240 | bne test_failed |
| 241 | add %l0, %g7, %l0 |
| 242 | ldx [%g2 + 0x10], %l2 |
| 243 | cmp %l0, %l2 |
| 244 | bne test_failed |
| 245 | add %l0, %g7, %l0 |
| 246 | ldx [%g2 + 0x18], %l2 |
| 247 | cmp %l0, %l2 |
| 248 | bne test_failed |
| 249 | add %l0, %g7, %l0 |
| 250 | ldx [%g2 + 0x20], %l2 |
| 251 | cmp %l0, %l2 |
| 252 | bne test_failed |
| 253 | add %l0, %g7, %l0 |
| 254 | ldx [%g2 + 0x28], %l2 |
| 255 | cmp %l0, %l2 |
| 256 | bne test_failed |
| 257 | add %l0, %g7, %l0 |
| 258 | ldx [%g2 + 0x30], %l2 |
| 259 | cmp %l0, %l2 |
| 260 | bne test_failed |
| 261 | add %l0, %g7, %l0 |
| 262 | ldx [%g2 + 0x38], %l2 |
| 263 | cmp %l0, %l2 |
| 264 | bne test_failed |
| 265 | add %l0, %g7, %l0 |
| 266 | |
| 267 | ! For L2$ bank 3 address space, addr[8:6] = 0x0 |
| 268 | ! 8 stores, 8 loads and check data |
| 269 | bank3_store: |
| 270 | setx data4, %g1, %g2 |
| 271 | mov %l0, %l1 |
| 272 | stx %l1, [%g2] |
| 273 | add %l1, %g7, %l1 |
| 274 | stx %l1, [%g2 + 0x8] |
| 275 | add %l1, %g7, %l1 |
| 276 | stx %l1, [%g2 + 0x10] |
| 277 | add %l1, %g7, %l1 |
| 278 | stx %l1, [%g2 + 0x18] |
| 279 | add %l1, %g7, %l1 |
| 280 | stx %l1, [%g2 + 0x20] |
| 281 | add %l1, %g7, %l1 |
| 282 | stx %l1, [%g2 + 0x28] |
| 283 | add %l1, %g7, %l1 |
| 284 | stx %l1, [%g2 + 0x30] |
| 285 | add %l1, %g7, %l1 |
| 286 | stx %l1, [%g2 + 0x38] |
| 287 | add %l1, %g7, %l1 |
| 288 | bank3_load: |
| 289 | ldx [%g2], %l2 |
| 290 | cmp %l0, %l2 |
| 291 | bne test_failed |
| 292 | add %l0, %g7, %l0 |
| 293 | ldx [%g2 + 0x8], %l2 |
| 294 | cmp %l0, %l2 |
| 295 | bne test_failed |
| 296 | add %l0, %g7, %l0 |
| 297 | ldx [%g2 + 0x10], %l2 |
| 298 | cmp %l0, %l2 |
| 299 | bne test_failed |
| 300 | add %l0, %g7, %l0 |
| 301 | ldx [%g2 + 0x18], %l2 |
| 302 | cmp %l0, %l2 |
| 303 | bne test_failed |
| 304 | add %l0, %g7, %l0 |
| 305 | ldx [%g2 + 0x20], %l2 |
| 306 | cmp %l0, %l2 |
| 307 | bne test_failed |
| 308 | add %l0, %g7, %l0 |
| 309 | ldx [%g2 + 0x28], %l2 |
| 310 | cmp %l0, %l2 |
| 311 | bne test_failed |
| 312 | add %l0, %g7, %l0 |
| 313 | ldx [%g2 + 0x30], %l2 |
| 314 | cmp %l0, %l2 |
| 315 | bne test_failed |
| 316 | add %l0, %g7, %l0 |
| 317 | ldx [%g2 + 0x38], %l2 |
| 318 | cmp %l0, %l2 |
| 319 | bne test_failed |
| 320 | add %l0, %g7, %l0 |
| 321 | |
| 322 | ! For L2$ bank 4 address space, addr[8:6] = 0x0 |
| 323 | ! 8 stores, 8 loads and check data |
| 324 | bank4_store: |
| 325 | setx data5, %g1, %g2 |
| 326 | mov %l0, %l1 |
| 327 | stx %l1, [%g2] |
| 328 | add %l1, %g7, %l1 |
| 329 | stx %l1, [%g2 + 0x8] |
| 330 | add %l1, %g7, %l1 |
| 331 | stx %l1, [%g2 + 0x10] |
| 332 | add %l1, %g7, %l1 |
| 333 | stx %l1, [%g2 + 0x18] |
| 334 | add %l1, %g7, %l1 |
| 335 | stx %l1, [%g2 + 0x20] |
| 336 | add %l1, %g7, %l1 |
| 337 | stx %l1, [%g2 + 0x28] |
| 338 | add %l1, %g7, %l1 |
| 339 | stx %l1, [%g2 + 0x30] |
| 340 | add %l1, %g7, %l1 |
| 341 | stx %l1, [%g2 + 0x38] |
| 342 | add %l1, %g7, %l1 |
| 343 | bank4_load: |
| 344 | ldx [%g2], %l2 |
| 345 | cmp %l0, %l2 |
| 346 | bne test_failed |
| 347 | add %l0, %g7, %l0 |
| 348 | ldx [%g2 + 0x8], %l2 |
| 349 | cmp %l0, %l2 |
| 350 | bne test_failed |
| 351 | add %l0, %g7, %l0 |
| 352 | ldx [%g2 + 0x10], %l2 |
| 353 | cmp %l0, %l2 |
| 354 | bne test_failed |
| 355 | add %l0, %g7, %l0 |
| 356 | ldx [%g2 + 0x18], %l2 |
| 357 | cmp %l0, %l2 |
| 358 | bne test_failed |
| 359 | add %l0, %g7, %l0 |
| 360 | ldx [%g2 + 0x20], %l2 |
| 361 | cmp %l0, %l2 |
| 362 | bne test_failed |
| 363 | add %l0, %g7, %l0 |
| 364 | ldx [%g2 + 0x28], %l2 |
| 365 | cmp %l0, %l2 |
| 366 | bne test_failed |
| 367 | add %l0, %g7, %l0 |
| 368 | ldx [%g2 + 0x30], %l2 |
| 369 | cmp %l0, %l2 |
| 370 | bne test_failed |
| 371 | add %l0, %g7, %l0 |
| 372 | ldx [%g2 + 0x38], %l2 |
| 373 | cmp %l0, %l2 |
| 374 | bne test_failed |
| 375 | add %l0, %g7, %l0 |
| 376 | |
| 377 | ! For L2$ bank 5 address space, addr[8:6] = 0x0 |
| 378 | ! 8 stores, 8 loads and check data |
| 379 | bank5_store: |
| 380 | setx data6, %g1, %g2 |
| 381 | mov %l0, %l1 |
| 382 | stx %l1, [%g2] |
| 383 | add %l1, %g7, %l1 |
| 384 | stx %l1, [%g2 + 0x8] |
| 385 | add %l1, %g7, %l1 |
| 386 | stx %l1, [%g2 + 0x10] |
| 387 | add %l1, %g7, %l1 |
| 388 | stx %l1, [%g2 + 0x18] |
| 389 | add %l1, %g7, %l1 |
| 390 | stx %l1, [%g2 + 0x20] |
| 391 | add %l1, %g7, %l1 |
| 392 | stx %l1, [%g2 + 0x28] |
| 393 | add %l1, %g7, %l1 |
| 394 | stx %l1, [%g2 + 0x30] |
| 395 | add %l1, %g7, %l1 |
| 396 | stx %l1, [%g2 + 0x38] |
| 397 | add %l1, %g7, %l1 |
| 398 | bank5_load: |
| 399 | ldx [%g2], %l2 |
| 400 | cmp %l0, %l2 |
| 401 | bne test_failed |
| 402 | add %l0, %g7, %l0 |
| 403 | ldx [%g2 + 0x8], %l2 |
| 404 | cmp %l0, %l2 |
| 405 | bne test_failed |
| 406 | add %l0, %g7, %l0 |
| 407 | ldx [%g2 + 0x10], %l2 |
| 408 | cmp %l0, %l2 |
| 409 | bne test_failed |
| 410 | add %l0, %g7, %l0 |
| 411 | ldx [%g2 + 0x18], %l2 |
| 412 | cmp %l0, %l2 |
| 413 | bne test_failed |
| 414 | add %l0, %g7, %l0 |
| 415 | ldx [%g2 + 0x20], %l2 |
| 416 | cmp %l0, %l2 |
| 417 | bne test_failed |
| 418 | add %l0, %g7, %l0 |
| 419 | ldx [%g2 + 0x28], %l2 |
| 420 | cmp %l0, %l2 |
| 421 | bne test_failed |
| 422 | add %l0, %g7, %l0 |
| 423 | ldx [%g2 + 0x30], %l2 |
| 424 | cmp %l0, %l2 |
| 425 | bne test_failed |
| 426 | add %l0, %g7, %l0 |
| 427 | ldx [%g2 + 0x38], %l2 |
| 428 | cmp %l0, %l2 |
| 429 | bne test_failed |
| 430 | add %l0, %g7, %l0 |
| 431 | |
| 432 | ! For L2$ bank 6 address space, addr[8:6] = 0x0 |
| 433 | ! 8 stores, 8 loads and check data |
| 434 | bank6_store: |
| 435 | setx data7, %g1, %g2 |
| 436 | mov %l0, %l1 |
| 437 | stx %l1, [%g2] |
| 438 | add %l1, %g7, %l1 |
| 439 | stx %l1, [%g2 + 0x8] |
| 440 | add %l1, %g7, %l1 |
| 441 | stx %l1, [%g2 + 0x10] |
| 442 | add %l1, %g7, %l1 |
| 443 | stx %l1, [%g2 + 0x18] |
| 444 | add %l1, %g7, %l1 |
| 445 | stx %l1, [%g2 + 0x20] |
| 446 | add %l1, %g7, %l1 |
| 447 | stx %l1, [%g2 + 0x28] |
| 448 | add %l1, %g7, %l1 |
| 449 | stx %l1, [%g2 + 0x30] |
| 450 | add %l1, %g7, %l1 |
| 451 | stx %l1, [%g2 + 0x38] |
| 452 | add %l1, %g7, %l1 |
| 453 | bank6_load: |
| 454 | ldx [%g2], %l2 |
| 455 | cmp %l0, %l2 |
| 456 | bne test_failed |
| 457 | add %l0, %g7, %l0 |
| 458 | ldx [%g2 + 0x8], %l2 |
| 459 | cmp %l0, %l2 |
| 460 | bne test_failed |
| 461 | add %l0, %g7, %l0 |
| 462 | ldx [%g2 + 0x10], %l2 |
| 463 | cmp %l0, %l2 |
| 464 | bne test_failed |
| 465 | add %l0, %g7, %l0 |
| 466 | ldx [%g2 + 0x18], %l2 |
| 467 | cmp %l0, %l2 |
| 468 | bne test_failed |
| 469 | add %l0, %g7, %l0 |
| 470 | ldx [%g2 + 0x20], %l2 |
| 471 | cmp %l0, %l2 |
| 472 | bne test_failed |
| 473 | add %l0, %g7, %l0 |
| 474 | ldx [%g2 + 0x28], %l2 |
| 475 | cmp %l0, %l2 |
| 476 | bne test_failed |
| 477 | add %l0, %g7, %l0 |
| 478 | ldx [%g2 + 0x30], %l2 |
| 479 | cmp %l0, %l2 |
| 480 | bne test_failed |
| 481 | add %l0, %g7, %l0 |
| 482 | ldx [%g2 + 0x38], %l2 |
| 483 | cmp %l0, %l2 |
| 484 | bne test_failed |
| 485 | add %l0, %g7, %l0 |
| 486 | |
| 487 | ! For L2$ bank 7 address space, addr[8:6] = 0x0 |
| 488 | ! 8 stores, 8 loads and check data |
| 489 | bank7_store: |
| 490 | setx data8, %g1, %g2 |
| 491 | mov %l0, %l1 |
| 492 | stx %l1, [%g2] |
| 493 | add %l1, %g7, %l1 |
| 494 | stx %l1, [%g2 + 0x8] |
| 495 | add %l1, %g7, %l1 |
| 496 | stx %l1, [%g2 + 0x10] |
| 497 | add %l1, %g7, %l1 |
| 498 | stx %l1, [%g2 + 0x18] |
| 499 | add %l1, %g7, %l1 |
| 500 | stx %l1, [%g2 + 0x20] |
| 501 | add %l1, %g7, %l1 |
| 502 | stx %l1, [%g2 + 0x28] |
| 503 | add %l1, %g7, %l1 |
| 504 | stx %l1, [%g2 + 0x30] |
| 505 | add %l1, %g7, %l1 |
| 506 | stx %l1, [%g2 + 0x38] |
| 507 | add %l1, %g7, %l1 |
| 508 | bank7_load: |
| 509 | ldx [%g2], %l2 |
| 510 | cmp %l0, %l2 |
| 511 | bne test_failed |
| 512 | add %l0, %g7, %l0 |
| 513 | ldx [%g2 + 0x8], %l2 |
| 514 | cmp %l0, %l2 |
| 515 | bne test_failed |
| 516 | add %l0, %g7, %l0 |
| 517 | ldx [%g2 + 0x10], %l2 |
| 518 | cmp %l0, %l2 |
| 519 | bne test_failed |
| 520 | add %l0, %g7, %l0 |
| 521 | ldx [%g2 + 0x18], %l2 |
| 522 | cmp %l0, %l2 |
| 523 | bne test_failed |
| 524 | add %l0, %g7, %l0 |
| 525 | ldx [%g2 + 0x20], %l2 |
| 526 | cmp %l0, %l2 |
| 527 | bne test_failed |
| 528 | add %l0, %g7, %l0 |
| 529 | ldx [%g2 + 0x28], %l2 |
| 530 | cmp %l0, %l2 |
| 531 | bne test_failed |
| 532 | add %l0, %g7, %l0 |
| 533 | ldx [%g2 + 0x30], %l2 |
| 534 | cmp %l0, %l2 |
| 535 | bne test_failed |
| 536 | add %l0, %g7, %l0 |
| 537 | ldx [%g2 + 0x38], %l2 |
| 538 | cmp %l0, %l2 |
| 539 | bne test_failed |
| 540 | add %l0, %g7, %l0 |
| 541 | |
| 542 | ! DONE |
| 543 | |
| 544 | ba test_passed |
| 545 | nop |
| 546 | |
| 547 | |
| 548 | /********************************************************************** |
| 549 | * Common code. |
| 550 | *********************************************************************/ |
| 551 | |
| 552 | test_passed: |
| 553 | EXIT_GOOD |
| 554 | |
| 555 | test_failed: |
| 556 | EXIT_BAD |
| 557 | |
| 558 | |
| 559 | /************************************************************************ |
| 560 | Test case data start |
| 561 | ************************************************************************/ |
| 562 | .data |
| 563 | user_data_start: |
| 564 | .align 0x40000 |
| 565 | data1: |
| 566 | .xword 0xa5a5a5a5a5a5a5a5 |
| 567 | .xword 0xa5a5a5a5a5a5a5a5 |
| 568 | .xword 0xa5a5a5a5a5a5a5a5 |
| 569 | .xword 0xa5a5a5a5a5a5a5a5 |
| 570 | .xword 0xa5a5a5a5a5a5a5a5 |
| 571 | .xword 0xa5a5a5a5a5a5a5a5 |
| 572 | .xword 0xa5a5a5a5a5a5a5a5 |
| 573 | .xword 0xa5a5a5a5a5a5a5a5 |
| 574 | data2: |
| 575 | .xword 0xa5a5a5a5a5a5a5a5 |
| 576 | .xword 0xa5a5a5a5a5a5a5a5 |
| 577 | .xword 0xa5a5a5a5a5a5a5a5 |
| 578 | .xword 0xa5a5a5a5a5a5a5a5 |
| 579 | .xword 0xa5a5a5a5a5a5a5a5 |
| 580 | .xword 0xa5a5a5a5a5a5a5a5 |
| 581 | .xword 0xa5a5a5a5a5a5a5a5 |
| 582 | .xword 0xa5a5a5a5a5a5a5a5 |
| 583 | data3: |
| 584 | .xword 0xa5a5a5a5a5a5a5a5 |
| 585 | .xword 0xa5a5a5a5a5a5a5a5 |
| 586 | .xword 0xa5a5a5a5a5a5a5a5 |
| 587 | .xword 0xa5a5a5a5a5a5a5a5 |
| 588 | .xword 0xa5a5a5a5a5a5a5a5 |
| 589 | .xword 0xa5a5a5a5a5a5a5a5 |
| 590 | .xword 0xa5a5a5a5a5a5a5a5 |
| 591 | .xword 0xa5a5a5a5a5a5a5a5 |
| 592 | data4: |
| 593 | .xword 0xa5a5a5a5a5a5a5a5 |
| 594 | .xword 0xa5a5a5a5a5a5a5a5 |
| 595 | .xword 0xa5a5a5a5a5a5a5a5 |
| 596 | .xword 0xa5a5a5a5a5a5a5a5 |
| 597 | .xword 0xa5a5a5a5a5a5a5a5 |
| 598 | .xword 0xa5a5a5a5a5a5a5a5 |
| 599 | .xword 0xa5a5a5a5a5a5a5a5 |
| 600 | .xword 0xa5a5a5a5a5a5a5a5 |
| 601 | data5: |
| 602 | .xword 0xa5a5a5a5a5a5a5a5 |
| 603 | .xword 0xa5a5a5a5a5a5a5a5 |
| 604 | .xword 0xa5a5a5a5a5a5a5a5 |
| 605 | .xword 0xa5a5a5a5a5a5a5a5 |
| 606 | .xword 0xa5a5a5a5a5a5a5a5 |
| 607 | .xword 0xa5a5a5a5a5a5a5a5 |
| 608 | .xword 0xa5a5a5a5a5a5a5a5 |
| 609 | .xword 0xa5a5a5a5a5a5a5a5 |
| 610 | data6: |
| 611 | .xword 0xa5a5a5a5a5a5a5a5 |
| 612 | .xword 0xa5a5a5a5a5a5a5a5 |
| 613 | .xword 0xa5a5a5a5a5a5a5a5 |
| 614 | .xword 0xa5a5a5a5a5a5a5a5 |
| 615 | .xword 0xa5a5a5a5a5a5a5a5 |
| 616 | .xword 0xa5a5a5a5a5a5a5a5 |
| 617 | .xword 0xa5a5a5a5a5a5a5a5 |
| 618 | .xword 0xa5a5a5a5a5a5a5a5 |
| 619 | data7: |
| 620 | .xword 0xa5a5a5a5a5a5a5a5 |
| 621 | .xword 0xa5a5a5a5a5a5a5a5 |
| 622 | .xword 0xa5a5a5a5a5a5a5a5 |
| 623 | .xword 0xa5a5a5a5a5a5a5a5 |
| 624 | .xword 0xa5a5a5a5a5a5a5a5 |
| 625 | .xword 0xa5a5a5a5a5a5a5a5 |
| 626 | .xword 0xa5a5a5a5a5a5a5a5 |
| 627 | .xword 0xa5a5a5a5a5a5a5a5 |
| 628 | data8: |
| 629 | .xword 0xa5a5a5a5a5a5a5a5 |
| 630 | .xword 0xa5a5a5a5a5a5a5a5 |
| 631 | .xword 0xa5a5a5a5a5a5a5a5 |
| 632 | .xword 0xa5a5a5a5a5a5a5a5 |
| 633 | .xword 0xa5a5a5a5a5a5a5a5 |
| 634 | .xword 0xa5a5a5a5a5a5a5a5 |
| 635 | .xword 0xa5a5a5a5a5a5a5a5 |
| 636 | .xword 0xa5a5a5a5a5a5a5a5 |
| 637 | |
| 638 | user_data_end: |
| 639 | |
| 640 | .end |
| 641 | |
| 642 | |