| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: tcu_asm_ucb_accesses_fc_a.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | |
| 41 | #define L2_ENTRY_PA 0xa000000000 |
| 42 | #define TEST_DATA0 0x5555555555555555 |
| 43 | #define TEST_DATA1 0xaaaaaaaaaaaaaaaa |
| 44 | #define TEST_DATA2 0x4c3fdead4c3fbeef |
| 45 | #define TEST_DATA3 0xdead4c3fbeef4c3f |
| 46 | #define L2_ENTRY_PA0 0x2020000008 |
| 47 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 48 | #define SPARC_ES_W1C_VALUE 0xefffffff |
| 49 | #define TT_SW_Error 0x40 |
| 50 | |
| 51 | #include "hboot.s" |
| 52 | #include "asi_s.h" |
| 53 | #include "err_defines.h" |
| 54 | |
| 55 | .text |
| 56 | .global main |
| 57 | |
| 58 | main: |
| 59 | |
| 60 | ! Boot code does not provide TLB translation for IO address space |
| 61 | ta T_CHANGE_HPRIV |
| 62 | |
| 63 | disable_l1_DCache: |
| 64 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 65 | ! Remove bit 2 |
| 66 | andn %l0, 0x2, %l0 |
| 67 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 68 | |
| 69 | set_L2_Directly_Mapped_Mode: |
| 70 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register |
| 71 | mov 0x2, %l0 |
| 72 | stx %l0, [%g1] |
| 73 | |
| 74 | |
| 75 | store_to_L2_bank0: |
| 76 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way |
| 77 | setx TEST_DATA0, %l0, %g3 |
| 78 | stx %g3, [%g2] |
| 79 | membar #Sync |
| 80 | nop |
| 81 | |
| 82 | setx 0x302000c0, %l0, %g4 ! Mask for extracting [21:3] |
| 83 | stx %g0, [%g4] ! initialize mem addr where JTAG writes back |
| 84 | membar #Sync |
| 85 | nop |
| 86 | start_jtag_rd_bank0: |
| 87 | nop !$EV trig_pc_d(1, @VA(.MAIN.start_jtag_rd_bank0)) -> jtagRdWrL2(0x002000aa00, TEST_DATA0, 0x00302000c0, 0) |
| 88 | |
| 89 | nop |
| 90 | membar #Sync |
| 91 | ! from this point down to chkJtagWrBank0, added to diag, from copy of l2 diag |
| 92 | setx 0x8500000000, %g1, %g2 ! bits [3:0] RW |
| 93 | membar #Sync |
| 94 | |
| 95 | mov 0xf, %g5 !added to test regress sim item with '%g5 unexp range change message' |
| 96 | mov 0xf, %l0 |
| 97 | stx %l0, [%g2] |
| 98 | nop |
| 99 | nop |
| 100 | ldx [%g2], %g5 |
| 101 | membar #Sync |
| 102 | cmp %g5, %l0 |
| 103 | nop |
| 104 | bne test_fail |
| 105 | nop |
| 106 | membar #Sync |
| 107 | |
| 108 | mov 0xa, %l0 |
| 109 | stx %l0, [%g2] |
| 110 | nop |
| 111 | nop |
| 112 | ldx [%g2], %g5 |
| 113 | membar #Sync |
| 114 | cmp %g5, %l0 |
| 115 | nop |
| 116 | bne test_fail |
| 117 | nop |
| 118 | membar #Sync |
| 119 | |
| 120 | mov 0x5, %l0 |
| 121 | stx %l0, [%g2] |
| 122 | nop |
| 123 | nop |
| 124 | ldx [%g2], %g5 |
| 125 | membar #Sync |
| 126 | cmp %g5, %l0 |
| 127 | nop |
| 128 | bne test_fail |
| 129 | nop |
| 130 | membar #Sync |
| 131 | |
| 132 | mov 0x0, %l0 |
| 133 | stx %l0, [%g2] |
| 134 | nop |
| 135 | nop |
| 136 | ldx [%g2], %g5 |
| 137 | membar #Sync |
| 138 | cmp %g5, %l0 |
| 139 | nop |
| 140 | bne test_fail |
| 141 | nop |
| 142 | membar #Sync |
| 143 | |
| 144 | mov 0x2, %l0 |
| 145 | stx %l0, [%g2] |
| 146 | nop |
| 147 | nop |
| 148 | ldx [%g2], %g5 |
| 149 | membar #Sync |
| 150 | cmp %g5, %l0 |
| 151 | nop |
| 152 | bne test_fail |
| 153 | nop |
| 154 | membar #Sync |
| 155 | |
| 156 | mov 0x3, %l0 |
| 157 | stx %l0, [%g2] |
| 158 | nop |
| 159 | nop |
| 160 | ldx [%g2], %g5 |
| 161 | membar #Sync |
| 162 | cmp %g5, %l0 |
| 163 | nop |
| 164 | bne test_fail |
| 165 | nop |
| 166 | membar #Sync |
| 167 | |
| 168 | |
| 169 | ! These ldx do asm accesses to 0x85 MBIST mode csr |
| 170 | ! These accesses occur during jtag tcu creg rds of DMU csr |
| 171 | ! This tests simultaneous access across ucb between tcu & ncu |
| 172 | |
| 173 | chkJtagWrBank0: |
| 174 | nop |
| 175 | ldx [%g4], %g6 |
| 176 | membar #Sync |
| 177 | cmp %g6, %g0 |
| 178 | nop |
| 179 | nop |
| 180 | nop |
| 181 | membar #Sync |
| 182 | nop |
| 183 | beq chkJtagWrBank0 |
| 184 | nop |
| 185 | membar #Sync |
| 186 | nop |
| 187 | |
| 188 | |
| 189 | enable_l1_DCache: |
| 190 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 191 | or %l0, 0x2, %l0 |
| 192 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 193 | |
| 194 | ba test_pass |
| 195 | nop |
| 196 | |
| 197 | |
| 198 | /******************************************************* |
| 199 | * Exit code |
| 200 | *******************************************************/ |
| 201 | |
| 202 | test_pass: |
| 203 | ta T_GOOD_TRAP |
| 204 | |
| 205 | test_fail: |
| 206 | ta T_BAD_TRAP |
| 207 | |
| 208 | |