| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: Debug_CoreSoc_Soc.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap |
| 39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap |
| 40 | |
| 41 | #define ENABLE_PCIE_LINK_TRAINING |
| 42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ |
| 43 | #define MAIN_PAGE_HV_ALSO |
| 44 | |
| 45 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 46 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 47 | |
| 48 | #include "err_defines.h" |
| 49 | #include "hboot.s" |
| 50 | #include "peu_defines.h" |
| 51 | |
| 52 | #define DMA_DATA_ADDR 0x0000000123456700 |
| 53 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456700 |
| 54 | #define DMA_DATA_BYP_ADDR2 0xfffc000123456780 |
| 55 | #define DMA_DATA_BYP_ADDR3 0xfffc000123456800 |
| 56 | |
| 57 | #define DMA_DATA_ADDR 0x0000000123456700 |
| 58 | #define DMA_DATA_BYP_SADDR 0xfffc000123456700 |
| 59 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 |
| 60 | |
| 61 | #define ADDR1 0xfffc00002000aa00 |
| 62 | #define TEST_DATA1 0xaaaaaaaaaaaaaaaa |
| 63 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 64 | |
| 65 | #define ERR_BITS 0x2 |
| 66 | #define ERR_BITS_EXPECT 0x8000000000000002 |
| 67 | |
| 68 | /**************/ |
| 69 | #define DBG_ERR_PA 0xAA00000000 |
| 70 | #define DBG_ERR_VAL 0x7 |
| 71 | |
| 72 | /***Following will enable the MCU Debug Events in case of an Error*****/ |
| 73 | |
| 74 | #define Soc_Decr_Pa 0x8600000010 |
| 75 | #define Soc_Decr_Val 0x00000000030000 |
| 76 | |
| 77 | //enable the coresoc mode diag |
| 78 | |
| 79 | #define Dbg_Config_Pa 0x8600000000 |
| 80 | #define Dbg_Config_Val 0x8000000000000007 |
| 81 | |
| 82 | |
| 83 | |
| 84 | /************************************************************************ |
| 85 | Test case code start |
| 86 | ************************************************************************/ |
| 87 | .text |
| 88 | .global main |
| 89 | .global My_Corrected_ECC_error_trap |
| 90 | .global My_Recoverable_Sw_error_trap |
| 91 | |
| 92 | main: |
| 93 | ta T_CHANGE_HPRIV |
| 94 | nop |
| 95 | setx Dbg_Config_Pa,%l1,%g3 |
| 96 | setx Dbg_Config_Val,%l4,%g7 |
| 97 | stx %g7,[%g3] |
| 98 | membar #Sync |
| 99 | nop |
| 100 | nop |
| 101 | |
| 102 | |
| 103 | clr %i7 |
| 104 | clr %o6 |
| 105 | clr %o7 |
| 106 | clr %i0 |
| 107 | setup_soc_decr_reg: |
| 108 | setx Soc_Decr_Pa,%l1,%g3 |
| 109 | setx Soc_Decr_Val,%l4,%g7 |
| 110 | stx %g7,[%g3] |
| 111 | nop |
| 112 | nop |
| 113 | |
| 114 | setup_dram_dbg: |
| 115 | setx DBG_ERR_PA,%l0,%g1 |
| 116 | setx DBG_ERR_VAL,%l3,%g5 |
| 117 | stx %g5,[%g1] |
| 118 | nop |
| 119 | nop |
| 120 | clr %i7 |
| 121 | clr %o6 |
| 122 | clr %o7 |
| 123 | clr %i0 |
| 124 | |
| 125 | disable_l1: |
| 126 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 127 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 128 | andn %l0, 0x3, %l0 |
| 129 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 130 | |
| 131 | set_DRAM_error_inject_ch0: |
| 132 | mov 0x606, %l1 ! ECC Mask (2-bit error) |
| 133 | mov 0x1, %l2 |
| 134 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 135 | Or %l1, %l3, %l1 ! Set single shot ; |
| 136 | mov 0x1, %l2 |
| 137 | sllx %l2, DRAM_EI_ENB, %l3 |
| 138 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 139 | setx DRAM_ERR_INJ_REG, %l3, %g6 |
| 140 | stx %l1, [%g6] |
| 141 | membar 0x40 |
| 142 | |
| 143 | L2_err_enable: |
| 144 | set 0x3, %l1 |
| 145 | mov 0xaa, %g2 |
| 146 | sllx %g2, 32, %g2 |
| 147 | stx %l1, [%g2] |
| 148 | stx %l1, [%g2 + 0x40] |
| 149 | stx %l1, [%g2 + 0x80] |
| 150 | stx %l1, [%g2 + 0xc0] |
| 151 | stx %l1, [%g2 + 0x100] |
| 152 | stx %l1, [%g2 + 0x140] |
| 153 | stx %l1, [%g2 + 0x180] |
| 154 | stx %l1, [%g2 + 0x1c0] |
| 155 | |
| 156 | set_L2_Directly_Mapped_Mode: |
| 157 | setx L2CS_PA0, %l6, %g1 |
| 158 | mov 0x2, %l0 |
| 159 | stx %l0, [%g1] |
| 160 | |
| 161 | store_to_L2_way0: |
| 162 | setx TEST_DATA1, %l0, %g5 |
| 163 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way |
| 164 | stx %g5, [%g2] |
| 165 | membar #Sync |
| 166 | |
| 167 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 168 | write_mcu_channel_0: |
| 169 | setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way |
| 170 | stx %g5, [%g3] |
| 171 | membar #Sync |
| 172 | |
| 173 | piu_iommu: |
| 174 | ! enable bypass in IOMMU |
| 175 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 |
| 176 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 |
| 177 | stx %g3, [%g2] |
| 178 | ldx [%g2], %g3 |
| 179 | |
| 180 | /******************************************************* |
| 181 | RDD from DMU |
| 182 | ********************************************************/ |
| 183 | |
| 184 | dma_rdd: |
| 185 | nop |
| 186 | UsrEvnt_rdd: |
| 187 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * ) |
| 188 | |
| 189 | ldx [%g2], %g3 |
| 190 | ldx [%g2], %g3 |
| 191 | ldx [%g2], %g3 |
| 192 | ldx [%g2], %g3 |
| 193 | |
| 194 | l2_esr: |
| 195 | mov 0x1, %g1 |
| 196 | sllx %g1, L2ES_DRU, %g2 |
| 197 | |
| 198 | mov 0x1, %g1 |
| 199 | sllx %g1, L2ES_VEU, %g3 |
| 200 | |
| 201 | or %g2, %g3, %g4 |
| 202 | |
| 203 | setx 0x7ffffffff0000000, %g7, %g5 |
| 204 | setx 0x30, %g7, %g6 |
| 205 | check_l2_esr: |
| 206 | cmp %g6, %g0 |
| 207 | be %xcc, test_failed |
| 208 | nop |
| 209 | dec %g6 |
| 210 | |
| 211 | setx L2_ERR_STAT_REG, %g7, %g1 |
| 212 | ldx [%g1], %g2 |
| 213 | andcc %g2, %g5, %g3 ! Donot check L2ESR SYND bits and MEC |
| 214 | |
| 215 | cmp %g3, %g4 |
| 216 | bne %xcc, check_l2_esr |
| 217 | nop |
| 218 | |
| 219 | cause_trap: |
| 220 | setx 0x2000a000, %g3, %g1 |
| 221 | stx %g0, [%g1] |
| 222 | setx 0x800bb00, %g3, %g1 |
| 223 | ldx [%g1], %g2 |
| 224 | |
| 225 | setx 0x8300b000, %g3, %g1 |
| 226 | setx 0x2222222222222222, %g3, %g2 |
| 227 | stx %g2, [%g1] |
| 228 | setx 0x6300b000, %g3, %g1 |
| 229 | ldx [%g1], %g2 |
| 230 | |
| 231 | eie_reg_ones_rdd: |
| 232 | setx SOC_EIE_REG, %g3, %g2 |
| 233 | setx 0xffffffffffffffff, %g3, %g1 |
| 234 | stx %g1, [%g2] |
| 235 | membar 0x40 |
| 236 | |
| 237 | set 0x1, %g1 |
| 238 | setx 0x30, %g7, %g6 |
| 239 | err_trap_loop_rdd: |
| 240 | cmp %g6, %g0 |
| 241 | be %xcc, test_failed |
| 242 | nop |
| 243 | |
| 244 | cmp %g1, %i7 |
| 245 | be %xcc, check_tt_rdd |
| 246 | nop |
| 247 | |
| 248 | ba err_trap_loop_rdd |
| 249 | nop |
| 250 | |
| 251 | check_tt_rdd: |
| 252 | mov 0x40, %l0 |
| 253 | cmp %o7, %l0 |
| 254 | bne %xcc, test_failed |
| 255 | nop |
| 256 | |
| 257 | |
| 258 | check_l2_trap_cnt: |
| 259 | set 0x1, %l0 |
| 260 | cmp %i0, %l0 |
| 261 | bne test_failed |
| 262 | nop |
| 263 | |
| 264 | test_passed: |
| 265 | EXIT_GOOD |
| 266 | |
| 267 | test_failed: |
| 268 | EXIT_BAD |
| 269 | |
| 270 | |
| 271 | /************************************************************************ |
| 272 | RAS |
| 273 | Trap Handlers |
| 274 | ************************************************************************/ |
| 275 | My_Recoverable_Sw_error_trap: |
| 276 | ! Signal trap taken |
| 277 | setx EXECUTED, %l0, %o6 |
| 278 | ! save trap type value |
| 279 | rdpr %tt, %o7 |
| 280 | |
| 281 | inc %i7 |
| 282 | |
| 283 | check_desr_NcuTrap_tt40: |
| 284 | ldxa [%g0]0x4c, %g2 |
| 285 | nop |
| 286 | |
| 287 | setx 0xb300000000000000, %l0, %g3 |
| 288 | subcc %g2, %g3, %g4 |
| 289 | brnz %g4, l2_trap |
| 290 | nop |
| 291 | |
| 292 | check_per_tt40: |
| 293 | ba test_failed |
| 294 | nop |
| 295 | |
| 296 | |
| 297 | l2_trap: |
| 298 | nop |
| 299 | inc %i0 |
| 300 | |
| 301 | check_desr_L2Trap_tt40: |
| 302 | setx 0xb000000000000000, %l0, %g3 |
| 303 | subcc %g2, %g3, %g4 |
| 304 | brnz %g4, test_failed |
| 305 | nop |
| 306 | |
| 307 | check_mcu2_esr_L2Trap_tt40: |
| 308 | mov 0x1, %l1 |
| 309 | sllx %l1, DRAM_ES_DAU, %l0 |
| 310 | |
| 311 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 312 | ldx [%g5], %l3 |
| 313 | |
| 314 | setx 0xffffffffffff0000, %l2, %l1 |
| 315 | andcc %l1, %l3, %l4 ! Donot check SYND bits |
| 316 | |
| 317 | sub %l0, %l4, %i4 |
| 318 | brnz %i4, test_failed |
| 319 | nop |
| 320 | |
| 321 | clear_mcu_esr_L2Trap_tt40: |
| 322 | stx %g0, [%g5] |
| 323 | |
| 324 | |
| 325 | check_L2_4_ESR_L2Trap_tt40: |
| 326 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 327 | ldx [%g5], %l6 |
| 328 | |
| 329 | setx 0x7ffffffff0000000, %l3, %l0 |
| 330 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU |
| 331 | |
| 332 | mov 0x1, %l1 |
| 333 | sllx %l1, L2ES_DRU, %l0 |
| 334 | |
| 335 | mov 0x1, %l1 |
| 336 | sllx %l1, L2ES_VEU, %l2 |
| 337 | |
| 338 | or %l0, %l2, %i4 |
| 339 | |
| 340 | cmp %l5, %i4 |
| 341 | bne %xcc, test_failed |
| 342 | nop |
| 343 | |
| 344 | clear_l2_esr_L2Trap_tt40: |
| 345 | stx %g0, [%g5] |
| 346 | |
| 347 | trap_done_tt40: |
| 348 | retry |
| 349 | nop |
| 350 | |
| 351 | |
| 352 | |
| 353 | My_Corrected_ECC_error_trap: |
| 354 | ba test_failed |
| 355 | nop |
| 356 | |
| 357 | |
| 358 | /************************************************************************ |
| 359 | Test case data start |
| 360 | ************************************************************************/ |
| 361 | |
| 362 | SECTION .DATA DATA_VA=DMA_DATA_ADDR |
| 363 | attr_data { |
| 364 | Name = .DATA, |
| 365 | hypervisor, |
| 366 | compressimage |
| 367 | } |
| 368 | |
| 369 | .data |
| 370 | .global PCIAddr9 |
| 371 | .xword 0x0001020304050607 |
| 372 | .xword 0x08090a0b0c0d0e0f |
| 373 | .xword 0x1011121314151617 |
| 374 | .xword 0x18191a1b1c1d1e1f |
| 375 | .xword 0x2021222324252627 |
| 376 | .xword 0x28292a2b2c2d2e2f |
| 377 | .xword 0x3031323334353637 |
| 378 | .xword 0x38393a3b3c3d3e3f |
| 379 | |
| 380 | .xword 0x4041424344454647 |
| 381 | .xword 0x48494a4b4c4d4e4f |
| 382 | .xword 0x5051525354555657 |
| 383 | .xword 0x58595a5b5c5d5e5f |
| 384 | .xword 0x6061626364656667 |
| 385 | .xword 0x68696a6b6c6d6e6f |
| 386 | .xword 0x7071727374757677 |
| 387 | .xword 0x78797a7b7c7d7e7f |
| 388 | |
| 389 | .xword 0x8081828384858687 |
| 390 | .xword 0x88898a8b8c8d8e8f |
| 391 | .xword 0x9091929394959697 |
| 392 | .xword 0x98999a9b9c9d9e9f |
| 393 | .xword 0xa0a1a2a3a4a5a6a7 |
| 394 | .xword 0xa8a9aaabacadaeaf |
| 395 | .xword 0xb0b1b2b3b4b5b6b7 |
| 396 | .xword 0xb8b9babbbcbdbebf |
| 397 | |
| 398 | .xword 0xc0c1c2c3c4c5c6c7 |
| 399 | .xword 0xc8c9cacbcccdcecf |
| 400 | .xword 0xd0d1d2d3d4d5d6d7 |
| 401 | .xword 0xd8d9dadbdcdddedf |
| 402 | .xword 0xe0e1e2e3e4e5e6e7 |
| 403 | .xword 0xe8e9eaebecedeeef |
| 404 | .xword 0xf0f1f2f3f4f5f6f7 |
| 405 | .xword 0xf8f9fafbfcfdfeff |
| 406 | |
| 407 | .xword 0x0001020304050607 |
| 408 | .xword 0x08090a0b0c0d0e0f |
| 409 | .xword 0x1011121314151617 |
| 410 | .xword 0x18191a1b1c1d1e1f |
| 411 | .xword 0x2021222324252627 |
| 412 | .xword 0x28292a2b2c2d2e2f |
| 413 | .xword 0x3031323334353637 |
| 414 | .xword 0x38393a3b3c3d3e3f |
| 415 | |
| 416 | .xword 0x4041424344454647 |
| 417 | .xword 0x48494a4b4c4d4e4f |
| 418 | .xword 0x5051525354555657 |
| 419 | .xword 0x58595a5b5c5d5e5f |
| 420 | .xword 0x6061626364656667 |
| 421 | .xword 0x68696a6b6c6d6e6f |
| 422 | .xword 0x7071727374757677 |
| 423 | .xword 0x78797a7b7c7d7e7f |
| 424 | |
| 425 | .xword 0x8081828384858687 |
| 426 | .xword 0x88898a8b8c8d8e8f |
| 427 | .xword 0x9091929394959697 |
| 428 | .xword 0x98999a9b9c9d9e9f |
| 429 | .xword 0xa0a1a2a3a4a5a6a7 |
| 430 | .xword 0xa8a9aaabacadaeaf |
| 431 | .xword 0xb0b1b2b3b4b5b6b7 |
| 432 | .xword 0xb8b9babbbcbdbebf |
| 433 | |
| 434 | .xword 0xc0c1c2c3c4c5c6c7 |
| 435 | .xword 0xc8c9cacbcccdcecf |
| 436 | .xword 0xd0d1d2d3d4d5d6d7 |
| 437 | .xword 0xd8d9dadbdcdddedf |
| 438 | .xword 0xe0e1e2e3e4e5e6e7 |
| 439 | .xword 0xe8e9eaebecedeeef |
| 440 | .xword 0xf0f1f2f3f4f5f6f7 |
| 441 | .xword 0xf8f9fafbfcfdfeff |
| 442 | |
| 443 | /************************************************************************/ |
| 444 | |