| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: Debug_Dmu_Quiscen.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define ENABLE_PCIE_LINK_TRAINING |
| 39 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ |
| 40 | #define MAIN_PAGE_HV_ALSO |
| 41 | ////////////////////////////////// |
| 42 | #define DBG_CONFIG_PA 0x8600000000 |
| 43 | #define DBG_REPEAT_VAL 0x8000000000000005 |
| 44 | #define DBG_IO_QUISCE 0x8600000008 |
| 45 | #define DBG_IOQ_VAL 0x1 |
| 46 | #define DBG_IOQ_DMUStall 0x1 |
| 47 | #define DBG_IOQ_DmuStallDone 0x4 |
| 48 | #define DBG_IOQ_DmuStallRst 0x1 |
| 49 | |
| 50 | //////////////////////////////////// |
| 51 | #define DBG_CONFIG_PA 0x8600000000 |
| 52 | #define DBG_PCIEX_VAL 0x800000000000000B |
| 53 | |
| 54 | #define DBG_PEUA_PA 0x8800683000 |
| 55 | #define DBG_PEUA_VAL 0x40 |
| 56 | #define DBG_PEUB_PA 0x8800683008 |
| 57 | #define DBG_PEUB_VAL 0x40 |
| 58 | |
| 59 | #define DBG_DMUA_PA 0x8800653000 |
| 60 | #define DBG_DMUA_VAL 0x140 |
| 61 | #define DBG_DMUB_PA 0x8800653008 |
| 62 | #define DBG_DMUB_VAL 0x140 |
| 63 | |
| 64 | |
| 65 | #include "hboot.s" |
| 66 | #include "peu_defines.h" |
| 67 | |
| 68 | #define MEM64_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA) |
| 69 | #define MEM64_WR_ADDR0 mpeval(MEM64_WR_ADDR + 0x0000000000) |
| 70 | #define MEM64_WR_ADDR1 mpeval(MEM64_WR_ADDR + 0x0100000000) |
| 71 | #define MEM64_WR_ADDR2 mpeval(MEM64_WR_ADDR + 0x0200000000) |
| 72 | #define MEM64_WR_ADDR4 mpeval(MEM64_WR_ADDR + 0x0400000000) |
| 73 | |
| 74 | #ifndef NO_SELF_CHECK |
| 75 | #define BNE_TEST_FAIL bne test_failed |
| 76 | #else |
| 77 | #define BNE_TEST_FAIL nop |
| 78 | #endif |
| 79 | |
| 80 | /************************************************************************ |
| 81 | Test case code start |
| 82 | ************************************************************************/ |
| 83 | .text |
| 84 | .global main |
| 85 | |
| 86 | main: |
| 87 | ta T_CHANGE_HPRIV |
| 88 | nop |
| 89 | setx DBG_CONFIG_PA,%g1,%g2 |
| 90 | setx DBG_PCIEX_VAL,%g3,%g4 |
| 91 | stx %g4,[%g2] |
| 92 | membar #Sync |
| 93 | setx DBG_PEUA_PA,%g1,%g2 |
| 94 | setx DBG_PEUA_VAL,%g3,%g4 |
| 95 | stx %g4,[%g2] |
| 96 | membar #Sync |
| 97 | setx DBG_PEUB_PA,%g1,%g2 |
| 98 | setx DBG_PEUB_VAL,%g3,%g4 |
| 99 | stx %g4,[%g2] |
| 100 | membar #Sync |
| 101 | setx DBG_DMUA_PA,%g1,%g2 |
| 102 | setx DBG_DMUA_VAL,%g3,%g4 |
| 103 | stx %g4,[%g2] |
| 104 | membar #Sync |
| 105 | setx DBG_DMUB_PA,%g1,%g2 |
| 106 | setx DBG_DMUB_VAL,%g3,%g4 |
| 107 | stx %g4,[%g2] |
| 108 | membar #Sync |
| 109 | |
| 110 | setx DBG_IO_QUISCE,%l0,%l2 |
| 111 | setx DBG_IOQ_VAL,%l3,%l4 |
| 112 | stx %l4,[%l2] |
| 113 | nop |
| 114 | membar #Sync |
| 115 | setx 0xf,%g1,%g3 |
| 116 | loop_resume: |
| 117 | nop |
| 118 | dec %g3 |
| 119 | brnz %g3,loop_resume |
| 120 | nop |
| 121 | ! setx 0x0,%g2,%l1 |
| 122 | setx DBG_IO_QUISCE,%l0,%l2 |
| 123 | stx %l1,[%l2] !reset the dmu stall bit. |
| 124 | nop |
| 125 | membar #Sync |
| 126 | |
| 127 | /////// |
| 128 | ! select a Mem address in PCI address range and transmit the command to NCU |
| 129 | setx MEM64_WR_ADDR1, %g1, %g2 |
| 130 | |
| 131 | ! store byte to a few offsets |
| 132 | setx 0x10, %g1, %l0 |
| 133 | stb %l0, [%g2 + 0] |
| 134 | mov %l0, %l1 |
| 135 | ldub [%g2 + 0], %l0 |
| 136 | cmp %l0, %l1 |
| 137 | BNE_TEST_FAIL |
| 138 | nop |
| 139 | |
| 140 | setx 0x20, %g1, %l0 |
| 141 | stb %l0, [%g2 + 1] |
| 142 | mov %l0, %l1 |
| 143 | ldub [%g2 + 1], %l0 |
| 144 | cmp %l0, %l1 |
| 145 | BNE_TEST_FAIL |
| 146 | nop |
| 147 | |
| 148 | setx 0x30, %g1, %l0 |
| 149 | stb %l0, [%g2 + 2] |
| 150 | mov %l0, %l1 |
| 151 | ldub [%g2 + 2], %l0 |
| 152 | cmp %l0, %l1 |
| 153 | BNE_TEST_FAIL |
| 154 | nop |
| 155 | |
| 156 | setx 0x40, %g1, %l0 |
| 157 | stb %l0, [%g2 + 3] |
| 158 | mov %l0, %l1 |
| 159 | ldub [%g2 + 3], %l0 |
| 160 | cmp %l0, %l1 |
| 161 | BNE_TEST_FAIL |
| 162 | nop |
| 163 | |
| 164 | setx 0x50, %g1, %l0 |
| 165 | stb %l0, [%g2 + 4] |
| 166 | mov %l0, %l1 |
| 167 | ldub [%g2 + 4], %l0 |
| 168 | cmp %l0, %l1 |
| 169 | BNE_TEST_FAIL |
| 170 | nop |
| 171 | |
| 172 | setx 0x60, %g1, %l0 |
| 173 | stb %l0, [%g2 + 5] |
| 174 | mov %l0, %l1 |
| 175 | ldub [%g2 + 5], %l0 |
| 176 | cmp %l0, %l1 |
| 177 | BNE_TEST_FAIL |
| 178 | nop |
| 179 | |
| 180 | setx 0x70, %g1, %l0 |
| 181 | stb %l0, [%g2 + 6] |
| 182 | mov %l0, %l1 |
| 183 | ldub [%g2 + 6], %l0 |
| 184 | cmp %l0, %l1 |
| 185 | BNE_TEST_FAIL |
| 186 | nop |
| 187 | |
| 188 | setx 0x80, %g1, %l0 |
| 189 | stb %l0, [%g2 + 7] |
| 190 | mov %l0, %l1 |
| 191 | ldub [%g2 + 7], %l0 |
| 192 | cmp %l0, %l1 |
| 193 | BNE_TEST_FAIL |
| 194 | nop |
| 195 | |
| 196 | ! store half-word to a few offsets |
| 197 | setx 0x9190, %g1, %l0 |
| 198 | sth %l0, [%g2 + 8] |
| 199 | mov %l0, %l1 |
| 200 | lduh [%g2 + 8], %l0 |
| 201 | cmp %l0, %l1 |
| 202 | BNE_TEST_FAIL |
| 203 | nop |
| 204 | |
| 205 | setx 0xa1a0, %g1, %l0 |
| 206 | sth %l0, [%g2 + 10] |
| 207 | mov %l0, %l1 |
| 208 | lduh [%g2 + 10], %l0 |
| 209 | cmp %l0, %l1 |
| 210 | BNE_TEST_FAIL |
| 211 | nop |
| 212 | |
| 213 | setx 0xb1b0, %g1, %l0 |
| 214 | sth %l0, [%g2 + 12] |
| 215 | mov %l0, %l1 |
| 216 | lduh [%g2 + 12], %l0 |
| 217 | cmp %l0, %l1 |
| 218 | BNE_TEST_FAIL |
| 219 | nop |
| 220 | |
| 221 | setx 0xc1c0, %g1, %l0 |
| 222 | sth %l0, [%g2 + 14] |
| 223 | mov %l0, %l1 |
| 224 | lduh [%g2 + 14], %l0 |
| 225 | cmp %l0, %l1 |
| 226 | BNE_TEST_FAIL |
| 227 | nop |
| 228 | |
| 229 | ! store word |
| 230 | setx 0xd3d2d1d0, %g1, %l0 |
| 231 | stw %l0, [%g2 + 16] |
| 232 | mov %l0, %l1 |
| 233 | lduw [%g2 + 16], %l0 |
| 234 | cmp %l0, %l1 |
| 235 | BNE_TEST_FAIL |
| 236 | nop |
| 237 | |
| 238 | setx 0xe3e2e1e0, %g1, %l0 |
| 239 | stw %l0, [%g2 + 20] |
| 240 | mov %l0, %l1 |
| 241 | lduw [%g2 + 20], %l0 |
| 242 | cmp %l0, %l1 |
| 243 | BNE_TEST_FAIL |
| 244 | nop |
| 245 | |
| 246 | setx 0xf3f2f1f0, %g1, %l0 |
| 247 | stw %l0, [%g2 + 24] |
| 248 | mov %l0, %l1 |
| 249 | lduw [%g2 + 24], %l0 |
| 250 | cmp %l0, %l1 |
| 251 | BNE_TEST_FAIL |
| 252 | nop |
| 253 | |
| 254 | setx 0x03020100, %g1, %l0 |
| 255 | stw %l0, [%g2 + 28] |
| 256 | mov %l0, %l1 |
| 257 | lduw [%g2 + 28], %l0 |
| 258 | cmp %l0, %l1 |
| 259 | BNE_TEST_FAIL |
| 260 | nop |
| 261 | |
| 262 | ! store dword |
| 263 | setx 0x1716151413121110, %g1, %l0 |
| 264 | stx %l0, [%g2 + 32] |
| 265 | mov %l0, %l1 |
| 266 | ldx [%g2 + 32], %l0 |
| 267 | cmp %l0, %l1 |
| 268 | BNE_TEST_FAIL |
| 269 | nop |
| 270 | |
| 271 | setx 0x2726252423222120, %g1, %l0 |
| 272 | stx %l0, [%g2 + 40] |
| 273 | mov %l0, %l1 |
| 274 | ldx [%g2 + 40], %l0 |
| 275 | cmp %l0, %l1 |
| 276 | BNE_TEST_FAIL |
| 277 | nop |
| 278 | nop |
| 279 | |
| 280 | test_passed: |
| 281 | EXIT_GOOD |
| 282 | |
| 283 | test_failed: |
| 284 | EXIT_BAD |
| 285 | |
| 286 | |
| 287 | /************************************************************************ |
| 288 | Test case data start |
| 289 | ************************************************************************/ |
| 290 | |
| 291 | SECTION .DATA DATA_VA=MEM64_WR_ADDR1 |
| 292 | attr_data { |
| 293 | Name = .DATA, |
| 294 | hypervisor, |
| 295 | compressimage |
| 296 | } |
| 297 | |
| 298 | .data |
| 299 | .global PCIAddr9 |
| 300 | |
| 301 | data0: .xword 0x1111111111111111 |
| 302 | .xword 0x2222222222222222 |
| 303 | .xword 0x3333333333333333 |
| 304 | .xword 0x4444444444444444 |
| 305 | .xword 0x5555555555555555 |
| 306 | .xword 0x6666666666666666 |
| 307 | .xword 0x7777777777777777 |
| 308 | .xword 0x8888888888888888 |
| 309 | |
| 310 | /************************************************************************/ |
| 311 | |