| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: Debug_Event_L2.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define Soc_Decr_Pa 0x8600000010 |
| 42 | #define Soc_Decr_Val 0x00000000030000 |
| 43 | |
| 44 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 45 | #define L2_ERR_ADDR_REG 0xAC00000000 |
| 46 | |
| 47 | #define TEST_DATA0 0x1000100081c3e008 |
| 48 | #define TEST_DATA1 0x2000200081c3e008 |
| 49 | #define TEST_DATA2 0x3000300081c3e008 |
| 50 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 |
| 51 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 52 | |
| 53 | #ifdef MCU0 |
| 54 | #define L2_BANK_ADDR 0x0 |
| 55 | #define MCU_BANK_ADDR 0x0 |
| 56 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 57 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 58 | #define ERROR_ADDR 0x20200000 |
| 59 | #define DBG_ERR_PA 0xAA00000000 |
| 60 | #define DBG_ERR_VAL 0x4 |
| 61 | #endif |
| 62 | |
| 63 | #ifdef MCU1 |
| 64 | #define L2_BANK_ADDR 0x80 |
| 65 | #define MCU_BANK_ADDR 0x80 |
| 66 | #define DRAM_ERR_INJ_REG 0x8400001290 |
| 67 | #define DRAM_ERR_STAT_REG 0x8400001280 |
| 68 | #define DBG_ERR_PA 0xAA00000080 |
| 69 | #define DBG_ERR_VAL 0x4 |
| 70 | #endif |
| 71 | |
| 72 | #ifdef MCU2 |
| 73 | #define L2_BANK_ADDR 0x100 |
| 74 | #define MCU_BANK_ADDR 0x100 |
| 75 | #define DRAM_ERR_INJ_REG 0x8400002290 |
| 76 | #define DRAM_ERR_STAT_REG 0x8400002280 |
| 77 | #define ERROR_ADDR 0x20200100 |
| 78 | #define DBG_ERR_PA 0xAA00000100 |
| 79 | #define DBG_ERR_VAL 0x4 |
| 80 | #endif |
| 81 | |
| 82 | #ifdef MCU3 |
| 83 | #define L2_BANK_ADDR 0x180 |
| 84 | #define MCU_BANK_ADDR 0x180 |
| 85 | #define DRAM_ERR_INJ_REG 0x8400003290 |
| 86 | #define DRAM_ERR_STAT_REG 0x8400003280 |
| 87 | #define DBG_ERR_PA 0xAA00000180 |
| 88 | #define DBG_ERR_VAL 0x4 |
| 89 | #endif |
| 90 | |
| 91 | |
| 92 | #include "hboot.s" |
| 93 | #include "asi_s.h" |
| 94 | #include "err_defines.h" |
| 95 | |
| 96 | |
| 97 | .text |
| 98 | .global main |
| 99 | .global My_Corrected_ECC_error_trap |
| 100 | |
| 101 | |
| 102 | |
| 103 | main: |
| 104 | ta T_CHANGE_HPRIV |
| 105 | nop |
| 106 | setx Soc_Decr_Pa,%l1,%g4 |
| 107 | setx Soc_Decr_Val,%l7,%g5 |
| 108 | stx %g5,[%g4] |
| 109 | nop |
| 110 | setx DBG_ERR_PA,%l0,%g2 |
| 111 | setx DBG_ERR_VAL,%l2,%g4 |
| 112 | stx %g4,[%g2] |
| 113 | nop |
| 114 | membar 0x40 |
| 115 | |
| 116 | |
| 117 | disable_l1: |
| 118 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 119 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 120 | andn %l0, 0x3, %l0 |
| 121 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 122 | |
| 123 | |
| 124 | clear_dram_esr_0: |
| 125 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) |
| 126 | setx DRAM_ES_W1C_VALUE, %l0, %l5 |
| 127 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 128 | ! add %g5, MCU_BANK_ADDR, %g5 |
| 129 | stx %l5, [%g5] |
| 130 | |
| 131 | set_DRAM_error_inject_ch0: |
| 132 | mov 0x606, %l1 ! ECC Mask (Multi-bit error) |
| 133 | mov 0x1, %l2 |
| 134 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 135 | Or %l1, %l3, %l1 ! Set single shot ; |
| 136 | mov 0x1, %l2 |
| 137 | sllx %l2, DRAM_EI_ENB, %l3 |
| 138 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 139 | setx DRAM_ERR_INJ_REG, %l3, %g6 |
| 140 | ! add %g6, MCU_BANK_ADDR, %g6 |
| 141 | stx %l1, [%g6] |
| 142 | membar 0x40 |
| 143 | |
| 144 | enable_err_reporting: |
| 145 | setx L2EE_PA0, %l0, %l1 |
| 146 | add %l1, L2_BANK_ADDR, %l1 |
| 147 | ldx [%l1], %l2 |
| 148 | mov 0x3, %l0 |
| 149 | or %l2, %l0, %l2 |
| 150 | stx %l2, [%l1] |
| 151 | |
| 152 | |
| 153 | ! Write 1 to clear L2 Error status registers |
| 154 | clear_l2_ESR: |
| 155 | setx L2ES_PA0, %l3, %l4 |
| 156 | add %l4, L2_BANK_ADDR, %l4 |
| 157 | stx %l5, [%l4] |
| 158 | nop |
| 159 | |
| 160 | set_L2_Off_Mode: |
| 161 | setx L2CS_PA0, %l6, %g1 |
| 162 | add %g1, L2_BANK_ADDR, %g1 |
| 163 | mov 0x1, %l0 |
| 164 | stx %l0, [%g1] |
| 165 | |
| 166 | |
| 167 | store_to_L2_way0: |
| 168 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way |
| 169 | add %g2, L2_BANK_ADDR, %g2 |
| 170 | stx %g5, [%g2] |
| 171 | membar #Sync |
| 172 | read_error_address_ch0: |
| 173 | ldx [%g2], %l1 |
| 174 | membar #Sync |
| 175 | |
| 176 | |
| 177 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 178 | write_mcu_channel_0: |
| 179 | setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way |
| 180 | add %g3, L2_BANK_ADDR, %g3 |
| 181 | stx %g5, [%g3] |
| 182 | membar #Sync |
| 183 | |
| 184 | /** |
| 185 | *read_error_address_ch0: |
| 186 | * ldx [%g2], %l1 |
| 187 | * membar #Sync |
| 188 | *! ldx [%g3], %l2 |
| 189 | *! membar #Sync |
| 190 | **/ |
| 191 | |
| 192 | |
| 193 | check_DRAM_ESR_0: |
| 194 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 195 | ! add %g5, MCU_BANK_ADDR, %g5 |
| 196 | ldx [%g5], %l6 |
| 197 | setx 0xffc0000000000000, %l0,%o2 |
| 198 | and %l6,%o2,%l6 |
| 199 | |
| 200 | |
| 201 | compute_dram_ESR: |
| 202 | mov 0x1, %l1 |
| 203 | sllx %l1, DRAM_ES_DAU, %l0 |
| 204 | |
| 205 | |
| 206 | verify_dram_ESR: |
| 207 | cmp %l0, %l6 |
| 208 | // bne %xcc, test_fail |
| 209 | nop |
| 210 | |
| 211 | check_L2_ESR_0: |
| 212 | setx L2_ERR_STAT_REG, %l3, %g5 |
| 213 | add %g5, L2_BANK_ADDR, %g5 |
| 214 | ldx [%g5], %l6 |
| 215 | |
| 216 | compute_L2_ESR: |
| 217 | setx 0xfffffffff0000000, %l3, %l0 |
| 218 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits |
| 219 | mov 0x1, %l1 |
| 220 | sllx %l1, L2ES_DAU, %l0 |
| 221 | mov 0x1, %l1 |
| 222 | sllx %l1, L2ES_VEU, %l2 |
| 223 | or %l0, %l2, %l3 |
| 224 | |
| 225 | verify_L2_ESR: |
| 226 | cmp %l6, %l3 |
| 227 | bne %xcc, test_fail |
| 228 | nop |
| 229 | |
| 230 | |
| 231 | setx L2EA_PA0, %l2, %l3 |
| 232 | add %l3, L2_BANK_ADDR, %l3 |
| 233 | check_l2_EAR: |
| 234 | ldx [%l3], %l4 |
| 235 | ! Error address is the physical address of the cache line (PA[5:0] 0) |
| 236 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way |
| 237 | add %g2, L2_BANK_ADDR, %g2 |
| 238 | |
| 239 | setx 0xffffffffc0, %l0,%o2 |
| 240 | and %l4, %o2, %l4 |
| 241 | cmp %l4, %g2 |
| 242 | // bne %xcc, test_fail |
| 243 | nop |
| 244 | |
| 245 | check_Corr_err_trap: |
| 246 | ! Check if a Corrected ECC Error Trap happened |
| 247 | set EXECUTED, %l0 |
| 248 | cmp %o0, %l0 |
| 249 | // bne test_fail |
| 250 | nop |
| 251 | mov TT_Data_Access_Error, %l0 |
| 252 | cmp %o1, %l0 |
| 253 | // bne test_fail |
| 254 | nop |
| 255 | |
| 256 | |
| 257 | ba test_pass |
| 258 | nop |
| 259 | |
| 260 | My_Corrected_ECC_error_trap: |
| 261 | |
| 262 | !My_Recoverable_Sw_error_trap: |
| 263 | ! Signal trap taken |
| 264 | setx EXECUTED, %l0, %o0 |
| 265 | ! save trap type value |
| 266 | rdpr %tt, %o1 |
| 267 | retry |
| 268 | nop |
| 269 | |
| 270 | |
| 271 | /******************************************************* |
| 272 | * Exit code |
| 273 | *******************************************************/ |
| 274 | |
| 275 | test_pass: |
| 276 | ta T_GOOD_TRAP |
| 277 | |
| 278 | |
| 279 | test_fail: |
| 280 | ta T_BAD_TRAP |
| 281 | |
| 282 | |
| 283 | |