| 1 | #ifndef THR_0_PARTID |
| 2 | #define THR_0_PARTID 0 |
| 3 | #endif |
| 4 | |
| 5 | #ifndef THR_1_PARTID |
| 6 | #define THR_1_PARTID 0 |
| 7 | #endif |
| 8 | |
| 9 | #ifndef THR_2_PARTID |
| 10 | #define THR_2_PARTID 0 |
| 11 | #endif |
| 12 | |
| 13 | #ifndef THR_3_PARTID |
| 14 | #define THR_3_PARTID 0 |
| 15 | #endif |
| 16 | |
| 17 | #ifndef THR_4_PARTID |
| 18 | #define THR_4_PARTID 0 |
| 19 | #endif |
| 20 | |
| 21 | #ifndef THR_5_PARTID |
| 22 | #define THR_5_PARTID 0 |
| 23 | #endif |
| 24 | |
| 25 | #ifndef THR_6_PARTID |
| 26 | #define THR_6_PARTID 0 |
| 27 | #endif |
| 28 | |
| 29 | #ifndef THR_7_PARTID |
| 30 | #define THR_7_PARTID 0 |
| 31 | #endif |
| 32 | |
| 33 | #ifndef THR_8_PARTID |
| 34 | #define THR_8_PARTID 0 |
| 35 | #endif |
| 36 | |
| 37 | #ifndef THR_9_PARTID |
| 38 | #define THR_9_PARTID 0 |
| 39 | #endif |
| 40 | |
| 41 | #ifndef THR_10_PARTID |
| 42 | #define THR_10_PARTID 0 |
| 43 | #endif |
| 44 | |
| 45 | #ifndef THR_11_PARTID |
| 46 | #define THR_11_PARTID 0 |
| 47 | #endif |
| 48 | |
| 49 | #ifndef THR_12_PARTID |
| 50 | #define THR_12_PARTID 0 |
| 51 | #endif |
| 52 | |
| 53 | #ifndef THR_13_PARTID |
| 54 | #define THR_13_PARTID 0 |
| 55 | #endif |
| 56 | |
| 57 | #ifndef THR_14_PARTID |
| 58 | #define THR_14_PARTID 0 |
| 59 | #endif |
| 60 | |
| 61 | #ifndef THR_15_PARTID |
| 62 | #define THR_15_PARTID 0 |
| 63 | #endif |
| 64 | |
| 65 | #ifndef THR_16_PARTID |
| 66 | #define THR_16_PARTID 0 |
| 67 | #endif |
| 68 | |
| 69 | #ifndef THR_17_PARTID |
| 70 | #define THR_17_PARTID 0 |
| 71 | #endif |
| 72 | |
| 73 | #ifndef THR_18_PARTID |
| 74 | #define THR_18_PARTID 0 |
| 75 | #endif |
| 76 | |
| 77 | #ifndef THR_19_PARTID |
| 78 | #define THR_19_PARTID 0 |
| 79 | #endif |
| 80 | |
| 81 | #ifndef THR_20_PARTID |
| 82 | #define THR_20_PARTID 0 |
| 83 | #endif |
| 84 | |
| 85 | #ifndef THR_21_PARTID |
| 86 | #define THR_21_PARTID 0 |
| 87 | #endif |
| 88 | |
| 89 | #ifndef THR_22_PARTID |
| 90 | #define THR_22_PARTID 0 |
| 91 | #endif |
| 92 | |
| 93 | #ifndef THR_23_PARTID |
| 94 | #define THR_23_PARTID 0 |
| 95 | #endif |
| 96 | |
| 97 | #ifndef THR_24_PARTID |
| 98 | #define THR_24_PARTID 0 |
| 99 | #endif |
| 100 | |
| 101 | #ifndef THR_25_PARTID |
| 102 | #define THR_25_PARTID 0 |
| 103 | #endif |
| 104 | |
| 105 | #ifndef THR_26_PARTID |
| 106 | #define THR_26_PARTID 0 |
| 107 | #endif |
| 108 | |
| 109 | #ifndef THR_27_PARTID |
| 110 | #define THR_27_PARTID 0 |
| 111 | #endif |
| 112 | |
| 113 | #ifndef THR_28_PARTID |
| 114 | #define THR_28_PARTID 0 |
| 115 | #endif |
| 116 | |
| 117 | #ifndef THR_29_PARTID |
| 118 | #define THR_29_PARTID 0 |
| 119 | #endif |
| 120 | |
| 121 | #ifndef THR_30_PARTID |
| 122 | #define THR_30_PARTID 0 |
| 123 | #endif |
| 124 | |
| 125 | #ifndef THR_31_PARTID |
| 126 | #define THR_31_PARTID 0 |
| 127 | #endif |
| 128 | |
| 129 | #ifndef THR_32_PARTID |
| 130 | #define THR_32_PARTID 0 |
| 131 | #endif |
| 132 | |
| 133 | #ifndef THR_33_PARTID |
| 134 | #define THR_33_PARTID 0 |
| 135 | #endif |
| 136 | |
| 137 | #ifndef THR_34_PARTID |
| 138 | #define THR_34_PARTID 0 |
| 139 | #endif |
| 140 | |
| 141 | #ifndef THR_35_PARTID |
| 142 | #define THR_35_PARTID 0 |
| 143 | #endif |
| 144 | |
| 145 | #ifndef THR_36_PARTID |
| 146 | #define THR_36_PARTID 0 |
| 147 | #endif |
| 148 | |
| 149 | #ifndef THR_37_PARTID |
| 150 | #define THR_37_PARTID 0 |
| 151 | #endif |
| 152 | |
| 153 | #ifndef THR_38_PARTID |
| 154 | #define THR_38_PARTID 0 |
| 155 | #endif |
| 156 | |
| 157 | #ifndef THR_39_PARTID |
| 158 | #define THR_39_PARTID 0 |
| 159 | #endif |
| 160 | |
| 161 | #ifndef THR_40_PARTID |
| 162 | #define THR_40_PARTID 0 |
| 163 | #endif |
| 164 | |
| 165 | #ifndef THR_41_PARTID |
| 166 | #define THR_41_PARTID 0 |
| 167 | #endif |
| 168 | |
| 169 | #ifndef THR_42_PARTID |
| 170 | #define THR_42_PARTID 0 |
| 171 | #endif |
| 172 | |
| 173 | #ifndef THR_43_PARTID |
| 174 | #define THR_43_PARTID 0 |
| 175 | #endif |
| 176 | |
| 177 | #ifndef THR_44_PARTID |
| 178 | #define THR_44_PARTID 0 |
| 179 | #endif |
| 180 | |
| 181 | #ifndef THR_45_PARTID |
| 182 | #define THR_45_PARTID 0 |
| 183 | #endif |
| 184 | |
| 185 | #ifndef THR_46_PARTID |
| 186 | #define THR_46_PARTID 0 |
| 187 | #endif |
| 188 | |
| 189 | #ifndef THR_47_PARTID |
| 190 | #define THR_47_PARTID 0 |
| 191 | #endif |
| 192 | |
| 193 | #ifndef THR_48_PARTID |
| 194 | #define THR_48_PARTID 0 |
| 195 | #endif |
| 196 | |
| 197 | #ifndef THR_49_PARTID |
| 198 | #define THR_49_PARTID 0 |
| 199 | #endif |
| 200 | |
| 201 | #ifndef THR_50_PARTID |
| 202 | #define THR_50_PARTID 0 |
| 203 | #endif |
| 204 | |
| 205 | #ifndef THR_51_PARTID |
| 206 | #define THR_51_PARTID 0 |
| 207 | #endif |
| 208 | |
| 209 | #ifndef THR_52_PARTID |
| 210 | #define THR_52_PARTID 0 |
| 211 | #endif |
| 212 | |
| 213 | #ifndef THR_53_PARTID |
| 214 | #define THR_53_PARTID 0 |
| 215 | #endif |
| 216 | |
| 217 | #ifndef THR_54_PARTID |
| 218 | #define THR_54_PARTID 0 |
| 219 | #endif |
| 220 | |
| 221 | #ifndef THR_55_PARTID |
| 222 | #define THR_55_PARTID 0 |
| 223 | #endif |
| 224 | |
| 225 | #ifndef THR_56_PARTID |
| 226 | #define THR_56_PARTID 0 |
| 227 | #endif |
| 228 | |
| 229 | #ifndef THR_57_PARTID |
| 230 | #define THR_57_PARTID 0 |
| 231 | #endif |
| 232 | |
| 233 | #ifndef THR_58_PARTID |
| 234 | #define THR_58_PARTID 0 |
| 235 | #endif |
| 236 | |
| 237 | #ifndef THR_59_PARTID |
| 238 | #define THR_59_PARTID 0 |
| 239 | #endif |
| 240 | |
| 241 | #ifndef THR_60_PARTID |
| 242 | #define THR_60_PARTID 0 |
| 243 | #endif |
| 244 | |
| 245 | #ifndef THR_61_PARTID |
| 246 | #define THR_61_PARTID 0 |
| 247 | #endif |
| 248 | |
| 249 | #ifndef THR_62_PARTID |
| 250 | #define THR_62_PARTID 0 |
| 251 | #endif |
| 252 | |
| 253 | #ifndef THR_63_PARTID |
| 254 | #define THR_63_PARTID 0 |
| 255 | #endif |
| 256 | |
| 257 | #if (THR_0_PARTID == 0) || \ |
| 258 | (THR_1_PARTID == 0) || \ |
| 259 | (THR_2_PARTID == 0) || \ |
| 260 | (THR_3_PARTID == 0) || \ |
| 261 | (THR_4_PARTID == 0) || \ |
| 262 | (THR_5_PARTID == 0) || \ |
| 263 | (THR_6_PARTID == 0) || \ |
| 264 | (THR_7_PARTID == 0) || \ |
| 265 | (THR_8_PARTID == 0) || \ |
| 266 | (THR_9_PARTID == 0) || \ |
| 267 | (THR_10_PARTID == 0) || \ |
| 268 | (THR_11_PARTID == 0) || \ |
| 269 | (THR_12_PARTID == 0) || \ |
| 270 | (THR_13_PARTID == 0) || \ |
| 271 | (THR_14_PARTID == 0) || \ |
| 272 | (THR_15_PARTID == 0) || \ |
| 273 | (THR_16_PARTID == 0) || \ |
| 274 | (THR_17_PARTID == 0) || \ |
| 275 | (THR_18_PARTID == 0) || \ |
| 276 | (THR_19_PARTID == 0) || \ |
| 277 | (THR_20_PARTID == 0) || \ |
| 278 | (THR_21_PARTID == 0) || \ |
| 279 | (THR_22_PARTID == 0) || \ |
| 280 | (THR_23_PARTID == 0) || \ |
| 281 | (THR_24_PARTID == 0) || \ |
| 282 | (THR_25_PARTID == 0) || \ |
| 283 | (THR_26_PARTID == 0) || \ |
| 284 | (THR_27_PARTID == 0) || \ |
| 285 | (THR_28_PARTID == 0) || \ |
| 286 | (THR_29_PARTID == 0) || \ |
| 287 | (THR_30_PARTID == 0) || \ |
| 288 | (THR_31_PARTID == 0) || \ |
| 289 | (THR_32_PARTID == 0) || \ |
| 290 | (THR_33_PARTID == 0) || \ |
| 291 | (THR_34_PARTID == 0) || \ |
| 292 | (THR_35_PARTID == 0) || \ |
| 293 | (THR_36_PARTID == 0) || \ |
| 294 | (THR_37_PARTID == 0) || \ |
| 295 | (THR_38_PARTID == 0) || \ |
| 296 | (THR_39_PARTID == 0) || \ |
| 297 | (THR_40_PARTID == 0) || \ |
| 298 | (THR_41_PARTID == 0) || \ |
| 299 | (THR_42_PARTID == 0) || \ |
| 300 | (THR_43_PARTID == 0) || \ |
| 301 | (THR_44_PARTID == 0) || \ |
| 302 | (THR_45_PARTID == 0) || \ |
| 303 | (THR_46_PARTID == 0) || \ |
| 304 | (THR_47_PARTID == 0) || \ |
| 305 | (THR_48_PARTID == 0) || \ |
| 306 | (THR_49_PARTID == 0) || \ |
| 307 | (THR_50_PARTID == 0) || \ |
| 308 | (THR_51_PARTID == 0) || \ |
| 309 | (THR_52_PARTID == 0) || \ |
| 310 | (THR_53_PARTID == 0) || \ |
| 311 | (THR_54_PARTID == 0) || \ |
| 312 | (THR_55_PARTID == 0) || \ |
| 313 | (THR_56_PARTID == 0) || \ |
| 314 | (THR_57_PARTID == 0) || \ |
| 315 | (THR_58_PARTID == 0) || \ |
| 316 | (THR_59_PARTID == 0) || \ |
| 317 | (THR_60_PARTID == 0) || \ |
| 318 | (THR_61_PARTID == 0) || \ |
| 319 | (THR_62_PARTID == 0) || \ |
| 320 | (THR_63_PARTID == 0) |
| 321 | #define PART_0_USED 1 |
| 322 | define(part_0_used, 1) |
| 323 | #endif |
| 324 | |
| 325 | #if (THR_0_PARTID == 1) || \ |
| 326 | (THR_1_PARTID == 1) || \ |
| 327 | (THR_2_PARTID == 1) || \ |
| 328 | (THR_3_PARTID == 1) || \ |
| 329 | (THR_4_PARTID == 1) || \ |
| 330 | (THR_5_PARTID == 1) || \ |
| 331 | (THR_6_PARTID == 1) || \ |
| 332 | (THR_7_PARTID == 1) || \ |
| 333 | (THR_8_PARTID == 1) || \ |
| 334 | (THR_9_PARTID == 1) || \ |
| 335 | (THR_10_PARTID == 1) || \ |
| 336 | (THR_11_PARTID == 1) || \ |
| 337 | (THR_12_PARTID == 1) || \ |
| 338 | (THR_13_PARTID == 1) || \ |
| 339 | (THR_14_PARTID == 1) || \ |
| 340 | (THR_15_PARTID == 1) || \ |
| 341 | (THR_16_PARTID == 1) || \ |
| 342 | (THR_17_PARTID == 1) || \ |
| 343 | (THR_18_PARTID == 1) || \ |
| 344 | (THR_19_PARTID == 1) || \ |
| 345 | (THR_20_PARTID == 1) || \ |
| 346 | (THR_21_PARTID == 1) || \ |
| 347 | (THR_22_PARTID == 1) || \ |
| 348 | (THR_23_PARTID == 1) || \ |
| 349 | (THR_24_PARTID == 1) || \ |
| 350 | (THR_25_PARTID == 1) || \ |
| 351 | (THR_26_PARTID == 1) || \ |
| 352 | (THR_27_PARTID == 1) || \ |
| 353 | (THR_28_PARTID == 1) || \ |
| 354 | (THR_29_PARTID == 1) || \ |
| 355 | (THR_30_PARTID == 1) || \ |
| 356 | (THR_31_PARTID == 1) || \ |
| 357 | (THR_32_PARTID == 1) || \ |
| 358 | (THR_33_PARTID == 1) || \ |
| 359 | (THR_34_PARTID == 1) || \ |
| 360 | (THR_35_PARTID == 1) || \ |
| 361 | (THR_36_PARTID == 1) || \ |
| 362 | (THR_37_PARTID == 1) || \ |
| 363 | (THR_38_PARTID == 1) || \ |
| 364 | (THR_39_PARTID == 1) || \ |
| 365 | (THR_40_PARTID == 1) || \ |
| 366 | (THR_41_PARTID == 1) || \ |
| 367 | (THR_42_PARTID == 1) || \ |
| 368 | (THR_43_PARTID == 1) || \ |
| 369 | (THR_44_PARTID == 1) || \ |
| 370 | (THR_45_PARTID == 1) || \ |
| 371 | (THR_46_PARTID == 1) || \ |
| 372 | (THR_47_PARTID == 1) || \ |
| 373 | (THR_48_PARTID == 1) || \ |
| 374 | (THR_49_PARTID == 1) || \ |
| 375 | (THR_50_PARTID == 1) || \ |
| 376 | (THR_51_PARTID == 1) || \ |
| 377 | (THR_52_PARTID == 1) || \ |
| 378 | (THR_53_PARTID == 1) || \ |
| 379 | (THR_54_PARTID == 1) || \ |
| 380 | (THR_55_PARTID == 1) || \ |
| 381 | (THR_56_PARTID == 1) || \ |
| 382 | (THR_57_PARTID == 1) || \ |
| 383 | (THR_58_PARTID == 1) || \ |
| 384 | (THR_59_PARTID == 1) || \ |
| 385 | (THR_60_PARTID == 1) || \ |
| 386 | (THR_61_PARTID == 1) || \ |
| 387 | (THR_62_PARTID == 1) || \ |
| 388 | (THR_63_PARTID == 1) |
| 389 | #define PART_1_USED 1 |
| 390 | define(part_1_used, 1) |
| 391 | #endif |
| 392 | |
| 393 | #if (THR_0_PARTID == 2) || \ |
| 394 | (THR_1_PARTID == 2) || \ |
| 395 | (THR_2_PARTID == 2) || \ |
| 396 | (THR_3_PARTID == 2) || \ |
| 397 | (THR_4_PARTID == 2) || \ |
| 398 | (THR_5_PARTID == 2) || \ |
| 399 | (THR_6_PARTID == 2) || \ |
| 400 | (THR_7_PARTID == 2) || \ |
| 401 | (THR_8_PARTID == 2) || \ |
| 402 | (THR_9_PARTID == 2) || \ |
| 403 | (THR_10_PARTID == 2) || \ |
| 404 | (THR_11_PARTID == 2) || \ |
| 405 | (THR_12_PARTID == 2) || \ |
| 406 | (THR_13_PARTID == 2) || \ |
| 407 | (THR_14_PARTID == 2) || \ |
| 408 | (THR_15_PARTID == 2) || \ |
| 409 | (THR_16_PARTID == 2) || \ |
| 410 | (THR_17_PARTID == 2) || \ |
| 411 | (THR_18_PARTID == 2) || \ |
| 412 | (THR_19_PARTID == 2) || \ |
| 413 | (THR_20_PARTID == 2) || \ |
| 414 | (THR_21_PARTID == 2) || \ |
| 415 | (THR_22_PARTID == 2) || \ |
| 416 | (THR_23_PARTID == 2) || \ |
| 417 | (THR_24_PARTID == 2) || \ |
| 418 | (THR_25_PARTID == 2) || \ |
| 419 | (THR_26_PARTID == 2) || \ |
| 420 | (THR_27_PARTID == 2) || \ |
| 421 | (THR_28_PARTID == 2) || \ |
| 422 | (THR_29_PARTID == 2) || \ |
| 423 | (THR_30_PARTID == 2) || \ |
| 424 | (THR_31_PARTID == 2) || \ |
| 425 | (THR_32_PARTID == 2) || \ |
| 426 | (THR_33_PARTID == 2) || \ |
| 427 | (THR_34_PARTID == 2) || \ |
| 428 | (THR_35_PARTID == 2) || \ |
| 429 | (THR_36_PARTID == 2) || \ |
| 430 | (THR_37_PARTID == 2) || \ |
| 431 | (THR_38_PARTID == 2) || \ |
| 432 | (THR_39_PARTID == 2) || \ |
| 433 | (THR_40_PARTID == 2) || \ |
| 434 | (THR_41_PARTID == 2) || \ |
| 435 | (THR_42_PARTID == 2) || \ |
| 436 | (THR_43_PARTID == 2) || \ |
| 437 | (THR_44_PARTID == 2) || \ |
| 438 | (THR_45_PARTID == 2) || \ |
| 439 | (THR_46_PARTID == 2) || \ |
| 440 | (THR_47_PARTID == 2) || \ |
| 441 | (THR_48_PARTID == 2) || \ |
| 442 | (THR_49_PARTID == 2) || \ |
| 443 | (THR_50_PARTID == 2) || \ |
| 444 | (THR_51_PARTID == 2) || \ |
| 445 | (THR_52_PARTID == 2) || \ |
| 446 | (THR_53_PARTID == 2) || \ |
| 447 | (THR_54_PARTID == 2) || \ |
| 448 | (THR_55_PARTID == 2) || \ |
| 449 | (THR_56_PARTID == 2) || \ |
| 450 | (THR_57_PARTID == 2) || \ |
| 451 | (THR_58_PARTID == 2) || \ |
| 452 | (THR_59_PARTID == 2) || \ |
| 453 | (THR_60_PARTID == 2) || \ |
| 454 | (THR_61_PARTID == 2) || \ |
| 455 | (THR_62_PARTID == 2) || \ |
| 456 | (THR_63_PARTID == 2) |
| 457 | #define PART_2_USED 1 |
| 458 | define(part_2_used, 1) |
| 459 | #endif |
| 460 | |
| 461 | #if (THR_0_PARTID == 3) || \ |
| 462 | (THR_1_PARTID == 3) || \ |
| 463 | (THR_2_PARTID == 3) || \ |
| 464 | (THR_3_PARTID == 3) || \ |
| 465 | (THR_4_PARTID == 3) || \ |
| 466 | (THR_5_PARTID == 3) || \ |
| 467 | (THR_6_PARTID == 3) || \ |
| 468 | (THR_7_PARTID == 3) || \ |
| 469 | (THR_8_PARTID == 3) || \ |
| 470 | (THR_9_PARTID == 3) || \ |
| 471 | (THR_10_PARTID == 3) || \ |
| 472 | (THR_11_PARTID == 3) || \ |
| 473 | (THR_12_PARTID == 3) || \ |
| 474 | (THR_13_PARTID == 3) || \ |
| 475 | (THR_14_PARTID == 3) || \ |
| 476 | (THR_15_PARTID == 3) || \ |
| 477 | (THR_16_PARTID == 3) || \ |
| 478 | (THR_17_PARTID == 3) || \ |
| 479 | (THR_18_PARTID == 3) || \ |
| 480 | (THR_19_PARTID == 3) || \ |
| 481 | (THR_20_PARTID == 3) || \ |
| 482 | (THR_21_PARTID == 3) || \ |
| 483 | (THR_22_PARTID == 3) || \ |
| 484 | (THR_23_PARTID == 3) || \ |
| 485 | (THR_24_PARTID == 3) || \ |
| 486 | (THR_25_PARTID == 3) || \ |
| 487 | (THR_26_PARTID == 3) || \ |
| 488 | (THR_27_PARTID == 3) || \ |
| 489 | (THR_28_PARTID == 3) || \ |
| 490 | (THR_29_PARTID == 3) || \ |
| 491 | (THR_30_PARTID == 3) || \ |
| 492 | (THR_31_PARTID == 3) || \ |
| 493 | (THR_32_PARTID == 3) || \ |
| 494 | (THR_33_PARTID == 3) || \ |
| 495 | (THR_34_PARTID == 3) || \ |
| 496 | (THR_35_PARTID == 3) || \ |
| 497 | (THR_36_PARTID == 3) || \ |
| 498 | (THR_37_PARTID == 3) || \ |
| 499 | (THR_38_PARTID == 3) || \ |
| 500 | (THR_39_PARTID == 3) || \ |
| 501 | (THR_40_PARTID == 3) || \ |
| 502 | (THR_41_PARTID == 3) || \ |
| 503 | (THR_42_PARTID == 3) || \ |
| 504 | (THR_43_PARTID == 3) || \ |
| 505 | (THR_44_PARTID == 3) || \ |
| 506 | (THR_45_PARTID == 3) || \ |
| 507 | (THR_46_PARTID == 3) || \ |
| 508 | (THR_47_PARTID == 3) || \ |
| 509 | (THR_48_PARTID == 3) || \ |
| 510 | (THR_49_PARTID == 3) || \ |
| 511 | (THR_50_PARTID == 3) || \ |
| 512 | (THR_51_PARTID == 3) || \ |
| 513 | (THR_52_PARTID == 3) || \ |
| 514 | (THR_53_PARTID == 3) || \ |
| 515 | (THR_54_PARTID == 3) || \ |
| 516 | (THR_55_PARTID == 3) || \ |
| 517 | (THR_56_PARTID == 3) || \ |
| 518 | (THR_57_PARTID == 3) || \ |
| 519 | (THR_58_PARTID == 3) || \ |
| 520 | (THR_59_PARTID == 3) || \ |
| 521 | (THR_60_PARTID == 3) || \ |
| 522 | (THR_61_PARTID == 3) || \ |
| 523 | (THR_62_PARTID == 3) || \ |
| 524 | (THR_63_PARTID == 3) |
| 525 | #define PART_3_USED 1 |
| 526 | define(part_3_used, 1) |
| 527 | #endif |
| 528 | |
| 529 | #if (THR_0_PARTID == 4) || \ |
| 530 | (THR_1_PARTID == 4) || \ |
| 531 | (THR_2_PARTID == 4) || \ |
| 532 | (THR_3_PARTID == 4) || \ |
| 533 | (THR_4_PARTID == 4) || \ |
| 534 | (THR_5_PARTID == 4) || \ |
| 535 | (THR_6_PARTID == 4) || \ |
| 536 | (THR_7_PARTID == 4) || \ |
| 537 | (THR_8_PARTID == 4) || \ |
| 538 | (THR_9_PARTID == 4) || \ |
| 539 | (THR_10_PARTID == 4) || \ |
| 540 | (THR_11_PARTID == 4) || \ |
| 541 | (THR_12_PARTID == 4) || \ |
| 542 | (THR_13_PARTID == 4) || \ |
| 543 | (THR_14_PARTID == 4) || \ |
| 544 | (THR_15_PARTID == 4) || \ |
| 545 | (THR_16_PARTID == 4) || \ |
| 546 | (THR_17_PARTID == 4) || \ |
| 547 | (THR_18_PARTID == 4) || \ |
| 548 | (THR_19_PARTID == 4) || \ |
| 549 | (THR_20_PARTID == 4) || \ |
| 550 | (THR_21_PARTID == 4) || \ |
| 551 | (THR_22_PARTID == 4) || \ |
| 552 | (THR_23_PARTID == 4) || \ |
| 553 | (THR_24_PARTID == 4) || \ |
| 554 | (THR_25_PARTID == 4) || \ |
| 555 | (THR_26_PARTID == 4) || \ |
| 556 | (THR_27_PARTID == 4) || \ |
| 557 | (THR_28_PARTID == 4) || \ |
| 558 | (THR_29_PARTID == 4) || \ |
| 559 | (THR_30_PARTID == 4) || \ |
| 560 | (THR_31_PARTID == 4) || \ |
| 561 | (THR_32_PARTID == 4) || \ |
| 562 | (THR_33_PARTID == 4) || \ |
| 563 | (THR_34_PARTID == 4) || \ |
| 564 | (THR_35_PARTID == 4) || \ |
| 565 | (THR_36_PARTID == 4) || \ |
| 566 | (THR_37_PARTID == 4) || \ |
| 567 | (THR_38_PARTID == 4) || \ |
| 568 | (THR_39_PARTID == 4) || \ |
| 569 | (THR_40_PARTID == 4) || \ |
| 570 | (THR_41_PARTID == 4) || \ |
| 571 | (THR_42_PARTID == 4) || \ |
| 572 | (THR_43_PARTID == 4) || \ |
| 573 | (THR_44_PARTID == 4) || \ |
| 574 | (THR_45_PARTID == 4) || \ |
| 575 | (THR_46_PARTID == 4) || \ |
| 576 | (THR_47_PARTID == 4) || \ |
| 577 | (THR_48_PARTID == 4) || \ |
| 578 | (THR_49_PARTID == 4) || \ |
| 579 | (THR_50_PARTID == 4) || \ |
| 580 | (THR_51_PARTID == 4) || \ |
| 581 | (THR_52_PARTID == 4) || \ |
| 582 | (THR_53_PARTID == 4) || \ |
| 583 | (THR_54_PARTID == 4) || \ |
| 584 | (THR_55_PARTID == 4) || \ |
| 585 | (THR_56_PARTID == 4) || \ |
| 586 | (THR_57_PARTID == 4) || \ |
| 587 | (THR_58_PARTID == 4) || \ |
| 588 | (THR_59_PARTID == 4) || \ |
| 589 | (THR_60_PARTID == 4) || \ |
| 590 | (THR_61_PARTID == 4) || \ |
| 591 | (THR_62_PARTID == 4) || \ |
| 592 | (THR_63_PARTID == 4) |
| 593 | #define PART_4_USED 1 |
| 594 | define(part_4_used, 1) |
| 595 | #endif |
| 596 | |
| 597 | #if (THR_0_PARTID == 5) || \ |
| 598 | (THR_1_PARTID == 5) || \ |
| 599 | (THR_2_PARTID == 5) || \ |
| 600 | (THR_3_PARTID == 5) || \ |
| 601 | (THR_4_PARTID == 5) || \ |
| 602 | (THR_5_PARTID == 5) || \ |
| 603 | (THR_6_PARTID == 5) || \ |
| 604 | (THR_7_PARTID == 5) || \ |
| 605 | (THR_8_PARTID == 5) || \ |
| 606 | (THR_9_PARTID == 5) || \ |
| 607 | (THR_10_PARTID == 5) || \ |
| 608 | (THR_11_PARTID == 5) || \ |
| 609 | (THR_12_PARTID == 5) || \ |
| 610 | (THR_13_PARTID == 5) || \ |
| 611 | (THR_14_PARTID == 5) || \ |
| 612 | (THR_15_PARTID == 5) || \ |
| 613 | (THR_16_PARTID == 5) || \ |
| 614 | (THR_17_PARTID == 5) || \ |
| 615 | (THR_18_PARTID == 5) || \ |
| 616 | (THR_19_PARTID == 5) || \ |
| 617 | (THR_20_PARTID == 5) || \ |
| 618 | (THR_21_PARTID == 5) || \ |
| 619 | (THR_22_PARTID == 5) || \ |
| 620 | (THR_23_PARTID == 5) || \ |
| 621 | (THR_24_PARTID == 5) || \ |
| 622 | (THR_25_PARTID == 5) || \ |
| 623 | (THR_26_PARTID == 5) || \ |
| 624 | (THR_27_PARTID == 5) || \ |
| 625 | (THR_28_PARTID == 5) || \ |
| 626 | (THR_29_PARTID == 5) || \ |
| 627 | (THR_30_PARTID == 5) || \ |
| 628 | (THR_31_PARTID == 5) || \ |
| 629 | (THR_32_PARTID == 5) || \ |
| 630 | (THR_33_PARTID == 5) || \ |
| 631 | (THR_34_PARTID == 5) || \ |
| 632 | (THR_35_PARTID == 5) || \ |
| 633 | (THR_36_PARTID == 5) || \ |
| 634 | (THR_37_PARTID == 5) || \ |
| 635 | (THR_38_PARTID == 5) || \ |
| 636 | (THR_39_PARTID == 5) || \ |
| 637 | (THR_40_PARTID == 5) || \ |
| 638 | (THR_41_PARTID == 5) || \ |
| 639 | (THR_42_PARTID == 5) || \ |
| 640 | (THR_43_PARTID == 5) || \ |
| 641 | (THR_44_PARTID == 5) || \ |
| 642 | (THR_45_PARTID == 5) || \ |
| 643 | (THR_46_PARTID == 5) || \ |
| 644 | (THR_47_PARTID == 5) || \ |
| 645 | (THR_48_PARTID == 5) || \ |
| 646 | (THR_49_PARTID == 5) || \ |
| 647 | (THR_50_PARTID == 5) || \ |
| 648 | (THR_51_PARTID == 5) || \ |
| 649 | (THR_52_PARTID == 5) || \ |
| 650 | (THR_53_PARTID == 5) || \ |
| 651 | (THR_54_PARTID == 5) || \ |
| 652 | (THR_55_PARTID == 5) || \ |
| 653 | (THR_56_PARTID == 5) || \ |
| 654 | (THR_57_PARTID == 5) || \ |
| 655 | (THR_58_PARTID == 5) || \ |
| 656 | (THR_59_PARTID == 5) || \ |
| 657 | (THR_60_PARTID == 5) || \ |
| 658 | (THR_61_PARTID == 5) || \ |
| 659 | (THR_62_PARTID == 5) || \ |
| 660 | (THR_63_PARTID == 5) |
| 661 | #define PART_5_USED 1 |
| 662 | define(part_5_used, 1) |
| 663 | #endif |
| 664 | |
| 665 | #if (THR_0_PARTID == 6) || \ |
| 666 | (THR_1_PARTID == 6) || \ |
| 667 | (THR_2_PARTID == 6) || \ |
| 668 | (THR_3_PARTID == 6) || \ |
| 669 | (THR_4_PARTID == 6) || \ |
| 670 | (THR_5_PARTID == 6) || \ |
| 671 | (THR_6_PARTID == 6) || \ |
| 672 | (THR_7_PARTID == 6) || \ |
| 673 | (THR_8_PARTID == 6) || \ |
| 674 | (THR_9_PARTID == 6) || \ |
| 675 | (THR_10_PARTID == 6) || \ |
| 676 | (THR_11_PARTID == 6) || \ |
| 677 | (THR_12_PARTID == 6) || \ |
| 678 | (THR_13_PARTID == 6) || \ |
| 679 | (THR_14_PARTID == 6) || \ |
| 680 | (THR_15_PARTID == 6) || \ |
| 681 | (THR_16_PARTID == 6) || \ |
| 682 | (THR_17_PARTID == 6) || \ |
| 683 | (THR_18_PARTID == 6) || \ |
| 684 | (THR_19_PARTID == 6) || \ |
| 685 | (THR_20_PARTID == 6) || \ |
| 686 | (THR_21_PARTID == 6) || \ |
| 687 | (THR_22_PARTID == 6) || \ |
| 688 | (THR_23_PARTID == 6) || \ |
| 689 | (THR_24_PARTID == 6) || \ |
| 690 | (THR_25_PARTID == 6) || \ |
| 691 | (THR_26_PARTID == 6) || \ |
| 692 | (THR_27_PARTID == 6) || \ |
| 693 | (THR_28_PARTID == 6) || \ |
| 694 | (THR_29_PARTID == 6) || \ |
| 695 | (THR_30_PARTID == 6) || \ |
| 696 | (THR_31_PARTID == 6) || \ |
| 697 | (THR_32_PARTID == 6) || \ |
| 698 | (THR_33_PARTID == 6) || \ |
| 699 | (THR_34_PARTID == 6) || \ |
| 700 | (THR_35_PARTID == 6) || \ |
| 701 | (THR_36_PARTID == 6) || \ |
| 702 | (THR_37_PARTID == 6) || \ |
| 703 | (THR_38_PARTID == 6) || \ |
| 704 | (THR_39_PARTID == 6) || \ |
| 705 | (THR_40_PARTID == 6) || \ |
| 706 | (THR_41_PARTID == 6) || \ |
| 707 | (THR_42_PARTID == 6) || \ |
| 708 | (THR_43_PARTID == 6) || \ |
| 709 | (THR_44_PARTID == 6) || \ |
| 710 | (THR_45_PARTID == 6) || \ |
| 711 | (THR_46_PARTID == 6) || \ |
| 712 | (THR_47_PARTID == 6) || \ |
| 713 | (THR_48_PARTID == 6) || \ |
| 714 | (THR_49_PARTID == 6) || \ |
| 715 | (THR_50_PARTID == 6) || \ |
| 716 | (THR_51_PARTID == 6) || \ |
| 717 | (THR_52_PARTID == 6) || \ |
| 718 | (THR_53_PARTID == 6) || \ |
| 719 | (THR_54_PARTID == 6) || \ |
| 720 | (THR_55_PARTID == 6) || \ |
| 721 | (THR_56_PARTID == 6) || \ |
| 722 | (THR_57_PARTID == 6) || \ |
| 723 | (THR_58_PARTID == 6) || \ |
| 724 | (THR_59_PARTID == 6) || \ |
| 725 | (THR_60_PARTID == 6) || \ |
| 726 | (THR_61_PARTID == 6) || \ |
| 727 | (THR_62_PARTID == 6) || \ |
| 728 | (THR_63_PARTID == 6) |
| 729 | #define PART_6_USED 1 |
| 730 | define(part_6_used, 1) |
| 731 | #endif |
| 732 | |
| 733 | #if (THR_0_PARTID == 7) || \ |
| 734 | (THR_1_PARTID == 7) || \ |
| 735 | (THR_2_PARTID == 7) || \ |
| 736 | (THR_3_PARTID == 7) || \ |
| 737 | (THR_4_PARTID == 7) || \ |
| 738 | (THR_5_PARTID == 7) || \ |
| 739 | (THR_6_PARTID == 7) || \ |
| 740 | (THR_7_PARTID == 7) || \ |
| 741 | (THR_8_PARTID == 7) || \ |
| 742 | (THR_9_PARTID == 7) || \ |
| 743 | (THR_10_PARTID == 7) || \ |
| 744 | (THR_11_PARTID == 7) || \ |
| 745 | (THR_12_PARTID == 7) || \ |
| 746 | (THR_13_PARTID == 7) || \ |
| 747 | (THR_14_PARTID == 7) || \ |
| 748 | (THR_15_PARTID == 7) || \ |
| 749 | (THR_16_PARTID == 7) || \ |
| 750 | (THR_17_PARTID == 7) || \ |
| 751 | (THR_18_PARTID == 7) || \ |
| 752 | (THR_19_PARTID == 7) || \ |
| 753 | (THR_20_PARTID == 7) || \ |
| 754 | (THR_21_PARTID == 7) || \ |
| 755 | (THR_22_PARTID == 7) || \ |
| 756 | (THR_23_PARTID == 7) || \ |
| 757 | (THR_24_PARTID == 7) || \ |
| 758 | (THR_25_PARTID == 7) || \ |
| 759 | (THR_26_PARTID == 7) || \ |
| 760 | (THR_27_PARTID == 7) || \ |
| 761 | (THR_28_PARTID == 7) || \ |
| 762 | (THR_29_PARTID == 7) || \ |
| 763 | (THR_30_PARTID == 7) || \ |
| 764 | (THR_31_PARTID == 7) || \ |
| 765 | (THR_32_PARTID == 7) || \ |
| 766 | (THR_33_PARTID == 7) || \ |
| 767 | (THR_34_PARTID == 7) || \ |
| 768 | (THR_35_PARTID == 7) || \ |
| 769 | (THR_36_PARTID == 7) || \ |
| 770 | (THR_37_PARTID == 7) || \ |
| 771 | (THR_38_PARTID == 7) || \ |
| 772 | (THR_39_PARTID == 7) || \ |
| 773 | (THR_40_PARTID == 7) || \ |
| 774 | (THR_41_PARTID == 7) || \ |
| 775 | (THR_42_PARTID == 7) || \ |
| 776 | (THR_43_PARTID == 7) || \ |
| 777 | (THR_44_PARTID == 7) || \ |
| 778 | (THR_45_PARTID == 7) || \ |
| 779 | (THR_46_PARTID == 7) || \ |
| 780 | (THR_47_PARTID == 7) || \ |
| 781 | (THR_48_PARTID == 7) || \ |
| 782 | (THR_49_PARTID == 7) || \ |
| 783 | (THR_50_PARTID == 7) || \ |
| 784 | (THR_51_PARTID == 7) || \ |
| 785 | (THR_52_PARTID == 7) || \ |
| 786 | (THR_53_PARTID == 7) || \ |
| 787 | (THR_54_PARTID == 7) || \ |
| 788 | (THR_55_PARTID == 7) || \ |
| 789 | (THR_56_PARTID == 7) || \ |
| 790 | (THR_57_PARTID == 7) || \ |
| 791 | (THR_58_PARTID == 7) || \ |
| 792 | (THR_59_PARTID == 7) || \ |
| 793 | (THR_60_PARTID == 7) || \ |
| 794 | (THR_61_PARTID == 7) || \ |
| 795 | (THR_62_PARTID == 7) || \ |
| 796 | (THR_63_PARTID == 7) |
| 797 | #define PART_7_USED 1 |
| 798 | define(part_7_used, 1) |
| 799 | #endif |
| 800 | |
| 801 | dnl Macro for translating Thread ID to Partition ID |
| 802 | dnl usage: tid2pid(THR_ID,PART_ID) |
| 803 | define(tid2pid,`ifelse( $1, 0, THR_0_PARTID, |
| 804 | $1, 1, THR_1_PARTID, |
| 805 | $1, 2, THR_2_PARTID, |
| 806 | $1, 3, THR_3_PARTID, |
| 807 | $1, 4, THR_4_PARTID, |
| 808 | $1, 5, THR_5_PARTID, |
| 809 | $1, 6, THR_6_PARTID, |
| 810 | $1, 7, THR_7_PARTID, |
| 811 | $1, 8, THR_8_PARTID, |
| 812 | $1, 9, THR_9_PARTID, |
| 813 | $1, 10, THR_10_PARTID, |
| 814 | $1, 11, THR_11_PARTID, |
| 815 | $1, 12, THR_12_PARTID, |
| 816 | $1, 13, THR_13_PARTID, |
| 817 | $1, 14, THR_14_PARTID, |
| 818 | $1, 15, THR_15_PARTID, |
| 819 | $1, 16, THR_16_PARTID, |
| 820 | $1, 17, THR_17_PARTID, |
| 821 | $1, 18, THR_18_PARTID, |
| 822 | $1, 19, THR_19_PARTID, |
| 823 | $1, 20, THR_20_PARTID, |
| 824 | $1, 21, THR_21_PARTID, |
| 825 | $1, 22, THR_22_PARTID, |
| 826 | $1, 23, THR_23_PARTID, |
| 827 | $1, 24, THR_24_PARTID, |
| 828 | $1, 25, THR_25_PARTID, |
| 829 | $1, 26, THR_26_PARTID, |
| 830 | $1, 27, THR_27_PARTID, |
| 831 | $1, 28, THR_28_PARTID, |
| 832 | $1, 29, THR_29_PARTID, |
| 833 | $1, 30, THR_30_PARTID, |
| 834 | $1, 31, THR_31_PARTID, |
| 835 | $1, 32, THR_32_PARTID, |
| 836 | $1, 33, THR_33_PARTID, |
| 837 | $1, 34, THR_34_PARTID, |
| 838 | $1, 35, THR_35_PARTID, |
| 839 | $1, 36, THR_36_PARTID, |
| 840 | $1, 37, THR_37_PARTID, |
| 841 | $1, 38, THR_38_PARTID, |
| 842 | $1, 39, THR_39_PARTID, |
| 843 | $1, 40, THR_40_PARTID, |
| 844 | $1, 41, THR_41_PARTID, |
| 845 | $1, 42, THR_42_PARTID, |
| 846 | $1, 43, THR_43_PARTID, |
| 847 | $1, 44, THR_44_PARTID, |
| 848 | $1, 45, THR_45_PARTID, |
| 849 | $1, 46, THR_46_PARTID, |
| 850 | $1, 47, THR_47_PARTID, |
| 851 | $1, 48, THR_48_PARTID, |
| 852 | $1, 49, THR_49_PARTID, |
| 853 | $1, 50, THR_50_PARTID, |
| 854 | $1, 51, THR_51_PARTID, |
| 855 | $1, 52, THR_52_PARTID, |
| 856 | $1, 53, THR_53_PARTID, |
| 857 | $1, 54, THR_54_PARTID, |
| 858 | $1, 55, THR_55_PARTID, |
| 859 | $1, 56, THR_56_PARTID, |
| 860 | $1, 57, THR_57_PARTID, |
| 861 | $1, 58, THR_58_PARTID, |
| 862 | $1, 59, THR_59_PARTID, |
| 863 | $1, 60, THR_60_PARTID, |
| 864 | $1, 61, THR_61_PARTID, |
| 865 | $1, 62, THR_62_PARTID, |
| 866 | $1, 63, THR_63_PARTID)') |
| 867 | |
| 868 | #ifndef PART_0_BASE |
| 869 | #define PART_0_BASE 0x1000000000 |
| 870 | #endif |
| 871 | #ifndef PART_0_LIMIT |
| 872 | #define PART_0_LIMIT 0x01ffffffff |
| 873 | #endif |
| 874 | |
| 875 | #ifndef PART_1_BASE |
| 876 | #define PART_1_BASE 0x1200000000 |
| 877 | #endif |
| 878 | #ifndef PART_1_LIMIT |
| 879 | #define PART_1_LIMIT 0x01ffffffff |
| 880 | #endif |
| 881 | |
| 882 | #ifndef PART_2_BASE |
| 883 | #define PART_2_BASE 0x1400000000 |
| 884 | #endif |
| 885 | #ifndef PART_2_LIMIT |
| 886 | #define PART_2_LIMIT 0x01ffffffff |
| 887 | #endif |
| 888 | |
| 889 | #ifndef PART_3_BASE |
| 890 | #define PART_3_BASE 0x1600000000 |
| 891 | #endif |
| 892 | #ifndef PART_3_LIMIT |
| 893 | #define PART_3_LIMIT 0x01ffffffff |
| 894 | #endif |
| 895 | |
| 896 | #ifndef PART_4_BASE |
| 897 | #define PART_4_BASE 0x1800000000 |
| 898 | #endif |
| 899 | #ifndef PART_4_LIMIT |
| 900 | #define PART_4_LIMIT 0x01ffffffff |
| 901 | #endif |
| 902 | |
| 903 | #ifndef PART_5_BASE |
| 904 | #define PART_5_BASE 0x1a00000000 |
| 905 | #endif |
| 906 | #ifndef PART_5_LIMIT |
| 907 | #define PART_5_LIMIT 0x01ffffffff |
| 908 | #endif |
| 909 | |
| 910 | #ifndef PART_6_BASE |
| 911 | #define PART_6_BASE 0x1c00000000 |
| 912 | #endif |
| 913 | #ifndef PART_6_LIMIT |
| 914 | #define PART_6_LIMIT 0x01ffffffff |
| 915 | #endif |
| 916 | |
| 917 | #ifndef PART_7_BASE |
| 918 | #define PART_7_BASE 0x1e00000000 |
| 919 | #endif |
| 920 | #ifndef PART_7_LIMIT |
| 921 | #define PART_7_LIMIT 0x01ffffffff |
| 922 | #endif |
| 923 | |
| 924 | dnl Macro for translating RA to PA |
| 925 | dnl usage: ra2pa(RA,PART_ID) |
| 926 | define(ra2pa,``0x'mpeval($1 + |
| 927 | ifelse( $2, 0, PART_0_BASE, |
| 928 | $2, 1, PART_1_BASE, |
| 929 | $2, 2, PART_2_BASE, |
| 930 | $2, 3, PART_3_BASE, |
| 931 | $2, 4, PART_4_BASE, |
| 932 | $2, 5, PART_5_BASE, |
| 933 | $2, 6, PART_6_BASE, |
| 934 | $2, 7, PART_7_BASE),16)') |
| 935 | |
| 936 | dnl Macro for translating RA to PA |
| 937 | dnl Used after change quote to [ ] |
| 938 | dnl usage: ra2pa2(RA,PART_ID) |
| 939 | define(ra2pa2,`[0x]mpeval($1 + |
| 940 | ifelse( $2, 0, PART_0_BASE, |
| 941 | $2, 1, PART_1_BASE, |
| 942 | $2, 2, PART_2_BASE, |
| 943 | $2, 3, PART_3_BASE, |
| 944 | $2, 4, PART_4_BASE, |
| 945 | $2, 5, PART_5_BASE, |
| 946 | $2, 6, PART_6_BASE, |
| 947 | $2, 7, PART_7_BASE),16)') |
| 948 | |
| 949 | define(part_0_base, PART_0_BASE) |
| 950 | define(part_1_base, PART_1_BASE) |
| 951 | define(part_2_base, PART_2_BASE) |
| 952 | define(part_3_base, PART_3_BASE) |
| 953 | define(part_4_base, PART_4_BASE) |
| 954 | define(part_5_base, PART_5_BASE) |
| 955 | define(part_6_base, PART_6_BASE) |
| 956 | define(part_7_base, PART_7_BASE) |
| 957 | |
| 958 | define(th00_part_limit, PART_0_LIMIT) |
| 959 | |
| 960 | #ifndef PART_0_LINK_AREA_BASE_ADDR |
| 961 | #define PART_0_LINK_AREA_BASE_ADDR 0x41000000 |
| 962 | #endif |
| 963 | #ifndef PART_1_LINK_AREA_BASE_ADDR |
| 964 | #define PART_1_LINK_AREA_BASE_ADDR 0x41100000 |
| 965 | #endif |
| 966 | #ifndef PART_2_LINK_AREA_BASE_ADDR |
| 967 | #define PART_2_LINK_AREA_BASE_ADDR 0x41200000 |
| 968 | #endif |
| 969 | #ifndef PART_3_LINK_AREA_BASE_ADDR |
| 970 | #define PART_3_LINK_AREA_BASE_ADDR 0x41300000 |
| 971 | #endif |
| 972 | #ifndef PART_4_LINK_AREA_BASE_ADDR |
| 973 | #define PART_4_LINK_AREA_BASE_ADDR 0x41400000 |
| 974 | #endif |
| 975 | #ifndef PART_5_LINK_AREA_BASE_ADDR |
| 976 | #define PART_5_LINK_AREA_BASE_ADDR 0x41500000 |
| 977 | #endif |
| 978 | #ifndef PART_6_LINK_AREA_BASE_ADDR |
| 979 | #define PART_6_LINK_AREA_BASE_ADDR 0x41600000 |
| 980 | #endif |
| 981 | #ifndef PART_7_LINK_AREA_BASE_ADDR |
| 982 | #define PART_7_LINK_AREA_BASE_ADDR 0x41700000 |
| 983 | #endif |
| 984 | |
| 985 | #if 0 |
| 986 | part_0_base PART_0_BASE |
| 987 | part_1_base PART_1_BASE |
| 988 | part_2_base PART_2_BASE |
| 989 | part_3_base PART_3_BASE |
| 990 | part_4_base PART_4_BASE |
| 991 | part_5_base PART_5_BASE |
| 992 | part_6_base PART_6_BASE |
| 993 | part_7_base PART_7_BASE |
| 994 | |
| 995 | part_0_limit PART_0_LIMIT |
| 996 | part_1_limit PART_1_LIMIT |
| 997 | part_2_limit PART_2_LIMIT |
| 998 | part_3_limit PART_3_LIMIT |
| 999 | part_4_limit PART_4_LIMIT |
| 1000 | part_5_limit PART_5_LIMIT |
| 1001 | part_6_limit PART_6_LIMIT |
| 1002 | part_7_limit PART_7_LIMIT |
| 1003 | |
| 1004 | #endif |
| 1005 | |
| 1006 | dnl // If TSB_SIZE is large (>11), PARTn_Z_ADDR_n will have to be moved apart |
| 1007 | dnl // and then might encroach on MAIN_BASE_TEXT_VA, which will have to |
| 1008 | dnl // moved higher in memory too. |
| 1009 | |
| 1010 | dnl // If NOHWTW is defined then define HWTEN to 0 |
| 1011 | |
| 1012 | #ifdef NOHWTW |
| 1013 | #define PART0_Z_HWTEN_0 0 |
| 1014 | #define PART0_Z_HWTEN_1 0 |
| 1015 | #define PART0_Z_HWTEN_2 0 |
| 1016 | #define PART0_Z_HWTEN_3 0 |
| 1017 | #define PART0_NZ_HWTEN_0 0 |
| 1018 | #define PART0_NZ_HWTEN_1 0 |
| 1019 | #define PART0_NZ_HWTEN_2 0 |
| 1020 | #define PART0_NZ_HWTEN_3 0 |
| 1021 | |
| 1022 | #define PART1_Z_HWTEN_0 0 |
| 1023 | #define PART1_Z_HWTEN_1 0 |
| 1024 | #define PART1_Z_HWTEN_2 0 |
| 1025 | #define PART1_Z_HWTEN_3 0 |
| 1026 | #define PART1_NZ_HWTEN_0 0 |
| 1027 | #define PART1_NZ_HWTEN_1 0 |
| 1028 | #define PART1_NZ_HWTEN_2 0 |
| 1029 | #define PART1_NZ_HWTEN_3 0 |
| 1030 | |
| 1031 | #define PART2_Z_HWTEN_0 0 |
| 1032 | #define PART2_Z_HWTEN_1 0 |
| 1033 | #define PART2_Z_HWTEN_2 0 |
| 1034 | #define PART2_Z_HWTEN_3 0 |
| 1035 | #define PART2_NZ_HWTEN_0 0 |
| 1036 | #define PART2_NZ_HWTEN_1 0 |
| 1037 | #define PART2_NZ_HWTEN_2 0 |
| 1038 | #define PART2_NZ_HWTEN_3 0 |
| 1039 | |
| 1040 | #define PART3_Z_HWTEN_0 0 |
| 1041 | #define PART3_Z_HWTEN_1 0 |
| 1042 | #define PART3_Z_HWTEN_2 0 |
| 1043 | #define PART3_Z_HWTEN_3 0 |
| 1044 | #define PART3_NZ_HWTEN_0 0 |
| 1045 | #define PART3_NZ_HWTEN_1 0 |
| 1046 | #define PART3_NZ_HWTEN_2 0 |
| 1047 | #define PART3_NZ_HWTEN_3 0 |
| 1048 | |
| 1049 | #define PART4_Z_HWTEN_0 0 |
| 1050 | #define PART4_Z_HWTEN_1 0 |
| 1051 | #define PART4_Z_HWTEN_2 0 |
| 1052 | #define PART4_Z_HWTEN_3 0 |
| 1053 | #define PART4_NZ_HWTEN_0 0 |
| 1054 | #define PART4_NZ_HWTEN_1 0 |
| 1055 | #define PART4_NZ_HWTEN_2 0 |
| 1056 | #define PART4_NZ_HWTEN_3 0 |
| 1057 | |
| 1058 | #define PART5_Z_HWTEN_0 0 |
| 1059 | #define PART5_Z_HWTEN_1 0 |
| 1060 | #define PART5_Z_HWTEN_2 0 |
| 1061 | #define PART5_Z_HWTEN_3 0 |
| 1062 | #define PART5_NZ_HWTEN_0 0 |
| 1063 | #define PART5_NZ_HWTEN_1 0 |
| 1064 | #define PART5_NZ_HWTEN_2 0 |
| 1065 | #define PART5_NZ_HWTEN_3 0 |
| 1066 | |
| 1067 | #define PART6_Z_HWTEN_0 0 |
| 1068 | #define PART6_Z_HWTEN_1 0 |
| 1069 | #define PART6_Z_HWTEN_2 0 |
| 1070 | #define PART6_Z_HWTEN_3 0 |
| 1071 | #define PART6_NZ_HWTEN_0 0 |
| 1072 | #define PART6_NZ_HWTEN_1 0 |
| 1073 | #define PART6_NZ_HWTEN_2 0 |
| 1074 | #define PART6_NZ_HWTEN_3 0 |
| 1075 | |
| 1076 | #define PART7_Z_HWTEN_0 0 |
| 1077 | #define PART7_Z_HWTEN_1 0 |
| 1078 | #define PART7_Z_HWTEN_2 0 |
| 1079 | #define PART7_Z_HWTEN_3 0 |
| 1080 | #define PART7_NZ_HWTEN_0 0 |
| 1081 | #define PART7_NZ_HWTEN_1 0 |
| 1082 | #define PART7_NZ_HWTEN_2 0 |
| 1083 | #define PART7_NZ_HWTEN_3 0 |
| 1084 | #endif |
| 1085 | |
| 1086 | dnl 0 //////////////////////// |
| 1087 | |
| 1088 | #ifndef PART0_Z_HWTEN_0 |
| 1089 | #define PART0_Z_HWTEN_0 1 |
| 1090 | #endif |
| 1091 | #ifndef PART0_Z_USECTX0_0 |
| 1092 | #define PART0_Z_USECTX0_0 0 |
| 1093 | #endif |
| 1094 | #ifndef PART0_Z_USECTX1_0 |
| 1095 | #define PART0_Z_USECTX1_0 0 |
| 1096 | #endif |
| 1097 | #ifndef PART0_Z_RANOTPA_0 |
| 1098 | #define PART0_Z_RANOTPA_0 1 |
| 1099 | #endif |
| 1100 | #ifndef SUN4V |
| 1101 | #define PART0_Z_SUN4V_0 0 |
| 1102 | #else |
| 1103 | #define PART0_Z_SUN4V_0 1 |
| 1104 | #endif |
| 1105 | #ifndef PART0_Z_ADDR_0 |
| 1106 | #define PART0_Z_ADDR_0 0x1000000 |
| 1107 | #endif |
| 1108 | #ifndef PART0_Z_TSB_SIZE_0 |
| 1109 | #define PART0_Z_TSB_SIZE_0 1 |
| 1110 | #endif |
| 1111 | #ifndef PART0_Z_PAGE_SIZE_0 |
| 1112 | #define PART0_Z_PAGE_SIZE_0 0 |
| 1113 | #endif |
| 1114 | #ifndef PART0_Z_TSB_CONFIG_0 |
| 1115 | #define PART0_Z_TSB_CONFIG_0 ((PART0_Z_HWTEN_0 << 63) | (PART0_Z_USECTX0_0 << 62) | (PART0_Z_USECTX1_0 << 61) | (PART0_Z_ADDR_0 & 0xffffffe000) | (PART0_Z_RANOTPA_0 << 8) | (PART0_Z_PAGE_SIZE_0 << 4) | (PART0_Z_TSB_SIZE_0)) |
| 1116 | #endif |
| 1117 | define(part_0_z_tsb_config_0, `0x'dnl' |
| 1118 | mpeval(PART0_Z_TSB_CONFIG_0,16))dnl |
| 1119 | |
| 1120 | #ifndef PART0_NZ_HWTEN_0 |
| 1121 | #define PART0_NZ_HWTEN_0 1 |
| 1122 | #endif |
| 1123 | #ifndef PART0_NZ_USECTX0_0 |
| 1124 | #define PART0_NZ_USECTX0_0 0 |
| 1125 | #endif |
| 1126 | #ifndef PART0_NZ_USECTX1_0 |
| 1127 | #define PART0_NZ_USECTX1_0 0 |
| 1128 | #endif |
| 1129 | #ifndef PART0_NZ_RANOTPA_0 |
| 1130 | #define PART0_NZ_RANOTPA_0 1 |
| 1131 | #endif |
| 1132 | #ifndef SUN4V |
| 1133 | #define PART0_NZ_SUN4V_0 0 |
| 1134 | #else |
| 1135 | #define PART0_NZ_SUN4V_0 1 |
| 1136 | #endif |
| 1137 | #ifndef PART0_NZ_ADDR_0 |
| 1138 | #define PART0_NZ_ADDR_0 0x2000000 |
| 1139 | #endif |
| 1140 | #ifndef PART0_NZ_TSB_SIZE_0 |
| 1141 | #define PART0_NZ_TSB_SIZE_0 1 |
| 1142 | #endif |
| 1143 | #ifndef PART0_NZ_PAGE_SIZE_0 |
| 1144 | #define PART0_NZ_PAGE_SIZE_0 0 |
| 1145 | #endif |
| 1146 | #ifndef PART0_NZ_TSB_CONFIG_0 |
| 1147 | #define PART0_NZ_TSB_CONFIG_0 ((PART0_NZ_HWTEN_0 << 63) | (PART0_NZ_USECTX0_0 << 62) | (PART0_NZ_USECTX1_0 << 61) | (PART0_NZ_ADDR_0 & 0xffffffe000) | (PART0_NZ_RANOTPA_0 << 8) | (PART0_NZ_PAGE_SIZE_0 << 4) | (PART0_NZ_TSB_SIZE_0)) |
| 1148 | #endif |
| 1149 | define(part_0_nz_tsb_config_0, `0x'dnl' |
| 1150 | mpeval(PART0_NZ_TSB_CONFIG_0,16))dnl |
| 1151 | |
| 1152 | #ifndef PART0_Z_HWTEN_1 |
| 1153 | #define PART0_Z_HWTEN_1 1 |
| 1154 | #endif |
| 1155 | #ifndef PART0_Z_USECTX0_1 |
| 1156 | #define PART0_Z_USECTX0_1 0 |
| 1157 | #endif |
| 1158 | #ifndef PART0_Z_USECTX1_1 |
| 1159 | #define PART0_Z_USECTX1_1 0 |
| 1160 | #endif |
| 1161 | #ifndef PART0_Z_RANOTPA_1 |
| 1162 | #define PART0_Z_RANOTPA_1 1 |
| 1163 | #endif |
| 1164 | #ifndef SUN4V |
| 1165 | #define PART0_Z_SUN4V_1 0 |
| 1166 | #else |
| 1167 | #define PART0_Z_SUN4V_1 1 |
| 1168 | #endif |
| 1169 | #ifndef PART0_Z_ADDR_1 |
| 1170 | #define PART0_Z_ADDR_1 0x3000000 |
| 1171 | #endif |
| 1172 | #ifndef PART0_Z_TSB_SIZE_1 |
| 1173 | #define PART0_Z_TSB_SIZE_1 1 |
| 1174 | #endif |
| 1175 | #ifndef PART0_Z_PAGE_SIZE_1 |
| 1176 | #define PART0_Z_PAGE_SIZE_1 0 |
| 1177 | #endif |
| 1178 | #ifndef PART0_Z_TSB_CONFIG_1 |
| 1179 | #define PART0_Z_TSB_CONFIG_1 ((PART0_Z_HWTEN_1 << 63) | (PART0_Z_USECTX0_1 << 62) | (PART0_Z_USECTX1_1 << 61) | (PART0_Z_ADDR_1 & 0xffffffe000) | (PART0_Z_RANOTPA_1 << 8) | (PART0_Z_PAGE_SIZE_1 << 4) | (PART0_Z_TSB_SIZE_1)) |
| 1180 | #endif |
| 1181 | define(part_0_z_tsb_config_1, `0x'dnl' |
| 1182 | mpeval(PART0_Z_TSB_CONFIG_1,16))dnl |
| 1183 | |
| 1184 | #ifndef PART0_NZ_HWTEN_1 |
| 1185 | #define PART0_NZ_HWTEN_1 1 |
| 1186 | #endif |
| 1187 | #ifndef PART0_NZ_USECTX0_1 |
| 1188 | #define PART0_NZ_USECTX0_1 0 |
| 1189 | #endif |
| 1190 | #ifndef PART0_NZ_USECTX1_1 |
| 1191 | #define PART0_NZ_USECTX1_1 0 |
| 1192 | #endif |
| 1193 | #ifndef PART0_NZ_RANOTPA_1 |
| 1194 | #define PART0_NZ_RANOTPA_1 1 |
| 1195 | #endif |
| 1196 | #ifndef SUN4V |
| 1197 | #define PART0_NZ_SUN4V_1 0 |
| 1198 | #else |
| 1199 | #define PART0_NZ_SUN4V_1 1 |
| 1200 | #endif |
| 1201 | #ifndef PART0_NZ_ADDR_1 |
| 1202 | #define PART0_NZ_ADDR_1 0x4000000 |
| 1203 | #endif |
| 1204 | #ifndef PART0_NZ_TSB_SIZE_1 |
| 1205 | #define PART0_NZ_TSB_SIZE_1 1 |
| 1206 | #endif |
| 1207 | #ifndef PART0_NZ_PAGE_SIZE_1 |
| 1208 | #define PART0_NZ_PAGE_SIZE_1 0 |
| 1209 | #endif |
| 1210 | #ifndef PART0_NZ_TSB_CONFIG_1 |
| 1211 | #define PART0_NZ_TSB_CONFIG_1 ((PART0_NZ_HWTEN_1 << 63) | (PART0_NZ_USECTX0_1 << 62) | (PART0_NZ_USECTX1_1 << 61) | (PART0_NZ_ADDR_1 & 0xffffffe000) | (PART0_NZ_RANOTPA_1 << 8) | (PART0_NZ_PAGE_SIZE_1 << 4) | (PART0_NZ_TSB_SIZE_1)) |
| 1212 | #endif |
| 1213 | define(part_0_nz_tsb_config_1, `0x'dnl' |
| 1214 | mpeval(PART0_NZ_TSB_CONFIG_1,16))dnl |
| 1215 | |
| 1216 | #ifndef PART0_Z_HWTEN_2 |
| 1217 | #define PART0_Z_HWTEN_2 1 |
| 1218 | #endif |
| 1219 | #ifndef PART0_Z_USECTX0_2 |
| 1220 | #define PART0_Z_USECTX0_2 0 |
| 1221 | #endif |
| 1222 | #ifndef PART0_Z_USECTX1_2 |
| 1223 | #define PART0_Z_USECTX1_2 0 |
| 1224 | #endif |
| 1225 | #ifndef PART0_Z_RANOTPA_2 |
| 1226 | #define PART0_Z_RANOTPA_2 1 |
| 1227 | #endif |
| 1228 | #ifndef SUN4V |
| 1229 | #define PART0_Z_SUN4V_2 0 |
| 1230 | #else |
| 1231 | #define PART0_Z_SUN4V_2 1 |
| 1232 | #endif |
| 1233 | #ifndef PART0_Z_ADDR_2 |
| 1234 | #define PART0_Z_ADDR_2 0x5000000 |
| 1235 | #endif |
| 1236 | #ifndef PART0_Z_TSB_SIZE_2 |
| 1237 | #define PART0_Z_TSB_SIZE_2 1 |
| 1238 | #endif |
| 1239 | #ifndef PART0_Z_PAGE_SIZE_2 |
| 1240 | #define PART0_Z_PAGE_SIZE_2 0 |
| 1241 | #endif |
| 1242 | #ifndef PART0_Z_TSB_CONFIG_2 |
| 1243 | #define PART0_Z_TSB_CONFIG_2 ((PART0_Z_HWTEN_2 << 63) | (PART0_Z_USECTX0_2 << 62) | (PART0_Z_USECTX1_2 << 61) | (PART0_Z_ADDR_2 & 0xffffffe000) | (PART0_Z_RANOTPA_2 << 8) | (PART0_Z_PAGE_SIZE_2 << 4) | (PART0_Z_TSB_SIZE_2)) |
| 1244 | #endif |
| 1245 | define(part_0_z_tsb_config_2, `0x'dnl' |
| 1246 | mpeval(PART0_Z_TSB_CONFIG_2,16))dnl |
| 1247 | |
| 1248 | #ifndef PART0_NZ_HWTEN_2 |
| 1249 | #define PART0_NZ_HWTEN_2 1 |
| 1250 | #endif |
| 1251 | #ifndef PART0_NZ_USECTX0_2 |
| 1252 | #define PART0_NZ_USECTX0_2 0 |
| 1253 | #endif |
| 1254 | #ifndef PART0_NZ_USECTX1_2 |
| 1255 | #define PART0_NZ_USECTX1_2 0 |
| 1256 | #endif |
| 1257 | #ifndef PART0_NZ_RANOTPA_2 |
| 1258 | #define PART0_NZ_RANOTPA_2 1 |
| 1259 | #endif |
| 1260 | #ifndef SUN4V |
| 1261 | #define PART0_NZ_SUN4V_2 0 |
| 1262 | #else |
| 1263 | #define PART0_NZ_SUN4V_2 1 |
| 1264 | #endif |
| 1265 | #ifndef PART0_NZ_ADDR_2 |
| 1266 | #define PART0_NZ_ADDR_2 0x6000000 |
| 1267 | #endif |
| 1268 | #ifndef PART0_NZ_TSB_SIZE_2 |
| 1269 | #define PART0_NZ_TSB_SIZE_2 1 |
| 1270 | #endif |
| 1271 | #ifndef PART0_NZ_PAGE_SIZE_2 |
| 1272 | #define PART0_NZ_PAGE_SIZE_2 0 |
| 1273 | #endif |
| 1274 | #ifndef PART0_NZ_TSB_CONFIG_2 |
| 1275 | #define PART0_NZ_TSB_CONFIG_2 ((PART0_NZ_HWTEN_2 << 63) | (PART0_NZ_USECTX0_2 << 62) | (PART0_NZ_USECTX1_2 << 61) | (PART0_NZ_ADDR_2 & 0xffffffe000) | (PART0_NZ_RANOTPA_2 << 8) | (PART0_NZ_PAGE_SIZE_2 << 4) | (PART0_NZ_TSB_SIZE_2)) |
| 1276 | #endif |
| 1277 | define(part_0_nz_tsb_config_2, `0x'dnl' |
| 1278 | mpeval(PART0_NZ_TSB_CONFIG_2,16))dnl |
| 1279 | |
| 1280 | #ifndef PART0_Z_HWTEN_3 |
| 1281 | #define PART0_Z_HWTEN_3 1 |
| 1282 | #endif |
| 1283 | #ifndef PART0_Z_USECTX0_3 |
| 1284 | #define PART0_Z_USECTX0_3 0 |
| 1285 | #endif |
| 1286 | #ifndef PART0_Z_USECTX1_3 |
| 1287 | #define PART0_Z_USECTX1_3 0 |
| 1288 | #endif |
| 1289 | #ifndef PART0_Z_RANOTPA_3 |
| 1290 | #define PART0_Z_RANOTPA_3 1 |
| 1291 | #endif |
| 1292 | #ifndef SUN4V |
| 1293 | #define PART0_Z_SUN4V_3 0 |
| 1294 | #else |
| 1295 | #define PART0_Z_SUN4V_3 1 |
| 1296 | #endif |
| 1297 | #ifndef PART0_Z_ADDR_3 |
| 1298 | #define PART0_Z_ADDR_3 0x7000000 |
| 1299 | #endif |
| 1300 | #ifndef PART0_Z_TSB_SIZE_3 |
| 1301 | #define PART0_Z_TSB_SIZE_3 1 |
| 1302 | #endif |
| 1303 | #ifndef PART0_Z_PAGE_SIZE_3 |
| 1304 | #define PART0_Z_PAGE_SIZE_3 0 |
| 1305 | #endif |
| 1306 | #ifndef PART0_Z_TSB_CONFIG_3 |
| 1307 | #define PART0_Z_TSB_CONFIG_3 ((PART0_Z_HWTEN_3 << 63) | (PART0_Z_USECTX0_3 << 62) | (PART0_Z_USECTX1_3 << 61) | (PART0_Z_ADDR_3 & 0xffffffe000) | (PART0_Z_RANOTPA_3 << 8) | (PART0_Z_PAGE_SIZE_3 << 4) | (PART0_Z_TSB_SIZE_3)) |
| 1308 | #endif |
| 1309 | define(part_0_z_tsb_config_3, `0x'dnl' |
| 1310 | mpeval(PART0_Z_TSB_CONFIG_3,16))dnl |
| 1311 | |
| 1312 | #ifndef PART0_NZ_HWTEN_3 |
| 1313 | #define PART0_NZ_HWTEN_3 1 |
| 1314 | #endif |
| 1315 | #ifndef PART0_NZ_USECTX0_3 |
| 1316 | #define PART0_NZ_USECTX0_3 0 |
| 1317 | #endif |
| 1318 | #ifndef PART0_NZ_USECTX1_3 |
| 1319 | #define PART0_NZ_USECTX1_3 0 |
| 1320 | #endif |
| 1321 | #ifndef PART0_NZ_RANOTPA_3 |
| 1322 | #define PART0_NZ_RANOTPA_3 1 |
| 1323 | #endif |
| 1324 | #ifndef SUN4V |
| 1325 | #define PART0_NZ_SUN4V_3 0 |
| 1326 | #else |
| 1327 | #define PART0_NZ_SUN4V_3 1 |
| 1328 | #endif |
| 1329 | #ifndef PART0_NZ_ADDR_3 |
| 1330 | #define PART0_NZ_ADDR_3 0x8000000 |
| 1331 | #endif |
| 1332 | #ifndef PART0_NZ_TSB_SIZE_3 |
| 1333 | #define PART0_NZ_TSB_SIZE_3 1 |
| 1334 | #endif |
| 1335 | #ifndef PART0_NZ_PAGE_SIZE_3 |
| 1336 | #define PART0_NZ_PAGE_SIZE_3 0 |
| 1337 | #endif |
| 1338 | #ifndef PART0_NZ_TSB_CONFIG_3 |
| 1339 | #define PART0_NZ_TSB_CONFIG_3 ((PART0_NZ_HWTEN_3 << 63) | (PART0_NZ_USECTX0_3 << 62) | (PART0_NZ_USECTX1_3 << 61) | (PART0_NZ_ADDR_3 & 0xffffffe000) | (PART0_NZ_RANOTPA_3 << 8) | (PART0_NZ_PAGE_SIZE_3 << 4) | (PART0_NZ_TSB_SIZE_3)) |
| 1340 | #endif |
| 1341 | define(part_0_nz_tsb_config_3, `0x'dnl' |
| 1342 | mpeval(PART0_NZ_TSB_CONFIG_3,16))dnl |
| 1343 | |
| 1344 | #ifndef PART0_PHY_OFF_X_0 |
| 1345 | #define PART0_PHY_OFF_X_0 1 |
| 1346 | #endif |
| 1347 | #ifndef PART0_PHY_OFF_P_0 |
| 1348 | #define PART0_PHY_OFF_P_0 0 |
| 1349 | #endif |
| 1350 | #ifndef PART0_PHY_OFF_W_0 |
| 1351 | #define PART0_PHY_OFF_W_0 0 |
| 1352 | #endif |
| 1353 | #ifndef PART0_PHY_OFF_0 |
| 1354 | #define PART0_PHY_OFF_0 ((PART_0_BASE) | (PART0_PHY_OFF_X_1 << 12) | (PART0_PHY_OFF_P_1 << 11) | (PART0_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 1355 | #endif |
| 1356 | |
| 1357 | #ifndef PART0_PHY_OFF_X_1 |
| 1358 | #define PART0_PHY_OFF_X_1 1 |
| 1359 | #endif |
| 1360 | #ifndef PART0_PHY_OFF_P_1 |
| 1361 | #define PART0_PHY_OFF_P_1 0 |
| 1362 | #endif |
| 1363 | #ifndef PART0_PHY_OFF_W_1 |
| 1364 | #define PART0_PHY_OFF_W_1 0 |
| 1365 | #endif |
| 1366 | #ifndef PART0_PHY_OFF_1 |
| 1367 | #define PART0_PHY_OFF_1 ((PART_0_BASE) | (PART0_PHY_OFF_X_1 << 12) | (PART0_PHY_OFF_P_1 << 11) | (PART0_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 1368 | #endif |
| 1369 | |
| 1370 | #ifndef PART0_PHY_OFF_X_2 |
| 1371 | #define PART0_PHY_OFF_X_2 1 |
| 1372 | #endif |
| 1373 | #ifndef PART0_PHY_OFF_P_2 |
| 1374 | #define PART0_PHY_OFF_P_2 0 |
| 1375 | #endif |
| 1376 | #ifndef PART0_PHY_OFF_W_2 |
| 1377 | #define PART0_PHY_OFF_W_2 0 |
| 1378 | #endif |
| 1379 | #ifndef PART0_PHY_OFF_2 |
| 1380 | #define PART0_PHY_OFF_2 ((PART_0_BASE) | (PART0_PHY_OFF_X_2 << 12) | (PART0_PHY_OFF_P_2 << 11) | (PART0_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 1381 | #endif |
| 1382 | |
| 1383 | #ifndef PART0_PHY_OFF_X_3 |
| 1384 | #define PART0_PHY_OFF_X_3 1 |
| 1385 | #endif |
| 1386 | #ifndef PART0_PHY_OFF_P_3 |
| 1387 | #define PART0_PHY_OFF_P_3 0 |
| 1388 | #endif |
| 1389 | #ifndef PART0_PHY_OFF_W_3 |
| 1390 | #define PART0_PHY_OFF_W_3 0 |
| 1391 | #endif |
| 1392 | #ifndef PART0_PHY_OFF_3 |
| 1393 | #define PART0_PHY_OFF_3 ((PART_0_BASE) | (PART0_PHY_OFF_X_3 << 12) | (PART0_PHY_OFF_P_3 << 11) | (PART0_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 1394 | #endif |
| 1395 | |
| 1396 | dnl 1 //////////////////////// |
| 1397 | |
| 1398 | #ifndef PART1_Z_HWTEN_0 |
| 1399 | #define PART1_Z_HWTEN_0 1 |
| 1400 | #endif |
| 1401 | #ifndef PART1_Z_USECTX0_0 |
| 1402 | #define PART1_Z_USECTX0_0 0 |
| 1403 | #endif |
| 1404 | #ifndef PART1_Z_USECTX1_0 |
| 1405 | #define PART1_Z_USECTX1_0 0 |
| 1406 | #endif |
| 1407 | #ifndef PART1_Z_RANOTPA_0 |
| 1408 | #define PART1_Z_RANOTPA_0 1 |
| 1409 | #endif |
| 1410 | #ifndef SUN4V |
| 1411 | #define PART1_Z_SUN4V_0 0 |
| 1412 | #else |
| 1413 | #define PART1_Z_SUN4V_0 1 |
| 1414 | #endif |
| 1415 | #ifndef PART1_Z_ADDR_0 |
| 1416 | #define PART1_Z_ADDR_0 0x9000000 |
| 1417 | #endif |
| 1418 | #ifndef PART1_Z_TSB_SIZE_0 |
| 1419 | #define PART1_Z_TSB_SIZE_0 1 |
| 1420 | #endif |
| 1421 | #ifndef PART1_Z_PAGE_SIZE_0 |
| 1422 | #define PART1_Z_PAGE_SIZE_0 0 |
| 1423 | #endif |
| 1424 | #ifndef PART1_Z_TSB_CONFIG_0 |
| 1425 | #define PART1_Z_TSB_CONFIG_0 ((PART1_Z_HWTEN_0 << 63) | (PART1_Z_USECTX0_0 << 62) | (PART1_Z_USECTX1_0 << 61) | (PART1_Z_ADDR_0 & 0xffffffe000) | (PART1_Z_RANOTPA_0 << 8) | (PART1_Z_PAGE_SIZE_0 << 4) | (PART1_Z_TSB_SIZE_0)) |
| 1426 | #endif |
| 1427 | define(part_1_z_tsb_config_0, `0x'dnl' |
| 1428 | mpeval(PART1_Z_TSB_CONFIG_0,16))dnl |
| 1429 | |
| 1430 | #ifndef PART1_NZ_HWTEN_0 |
| 1431 | #define PART1_NZ_HWTEN_0 1 |
| 1432 | #endif |
| 1433 | #ifndef PART1_NZ_USECTX0_0 |
| 1434 | #define PART1_NZ_USECTX0_0 0 |
| 1435 | #endif |
| 1436 | #ifndef PART1_NZ_USECTX1_0 |
| 1437 | #define PART1_NZ_USECTX1_0 0 |
| 1438 | #endif |
| 1439 | #ifndef PART1_NZ_RANOTPA_0 |
| 1440 | #define PART1_NZ_RANOTPA_0 1 |
| 1441 | #endif |
| 1442 | #ifndef SUN4V |
| 1443 | #define PART1_NZ_SUN4V_0 0 |
| 1444 | #else |
| 1445 | #define PART1_NZ_SUN4V_0 1 |
| 1446 | #endif |
| 1447 | #ifndef PART1_NZ_ADDR_0 |
| 1448 | #define PART1_NZ_ADDR_0 0xa000000 |
| 1449 | #endif |
| 1450 | #ifndef PART1_NZ_TSB_SIZE_0 |
| 1451 | #define PART1_NZ_TSB_SIZE_0 1 |
| 1452 | #endif |
| 1453 | #ifndef PART1_NZ_PAGE_SIZE_0 |
| 1454 | #define PART1_NZ_PAGE_SIZE_0 0 |
| 1455 | #endif |
| 1456 | #ifndef PART1_NZ_TSB_CONFIG_0 |
| 1457 | #define PART1_NZ_TSB_CONFIG_0 ((PART1_NZ_HWTEN_0 << 63) | (PART1_NZ_USECTX0_0 << 62) | (PART1_NZ_USECTX1_0 << 61) | (PART1_NZ_ADDR_0 & 0xffffffe000) | (PART1_NZ_RANOTPA_0 << 8) | (PART1_NZ_PAGE_SIZE_0 << 4) | (PART1_NZ_TSB_SIZE_0)) |
| 1458 | #endif |
| 1459 | define(part_1_nz_tsb_config_0, `0x'dnl' |
| 1460 | mpeval(PART1_NZ_TSB_CONFIG_0,16))dnl |
| 1461 | |
| 1462 | #ifndef PART1_Z_HWTEN_1 |
| 1463 | #define PART1_Z_HWTEN_1 1 |
| 1464 | #endif |
| 1465 | #ifndef PART1_Z_USECTX0_1 |
| 1466 | #define PART1_Z_USECTX0_1 0 |
| 1467 | #endif |
| 1468 | #ifndef PART1_Z_USECTX1_1 |
| 1469 | #define PART1_Z_USECTX1_1 0 |
| 1470 | #endif |
| 1471 | #ifndef PART1_Z_RANOTPA_1 |
| 1472 | #define PART1_Z_RANOTPA_1 1 |
| 1473 | #endif |
| 1474 | #ifndef SUN4V |
| 1475 | #define PART1_Z_SUN4V_1 0 |
| 1476 | #else |
| 1477 | #define PART1_Z_SUN4V_1 1 |
| 1478 | #endif |
| 1479 | #ifndef PART1_Z_ADDR_1 |
| 1480 | #define PART1_Z_ADDR_1 0xb000000 |
| 1481 | #endif |
| 1482 | #ifndef PART1_Z_TSB_SIZE_1 |
| 1483 | #define PART1_Z_TSB_SIZE_1 1 |
| 1484 | #endif |
| 1485 | #ifndef PART1_Z_PAGE_SIZE_1 |
| 1486 | #define PART1_Z_PAGE_SIZE_1 0 |
| 1487 | #endif |
| 1488 | #ifndef PART1_Z_TSB_CONFIG_1 |
| 1489 | #define PART1_Z_TSB_CONFIG_1 ((PART1_Z_HWTEN_1 << 63) | (PART1_Z_USECTX0_1 << 62) | (PART1_Z_USECTX1_1 << 61) | (PART1_Z_ADDR_1 & 0xffffffe000) | (PART1_Z_RANOTPA_1 << 8) | (PART1_Z_PAGE_SIZE_1 << 4) | (PART1_Z_TSB_SIZE_1)) |
| 1490 | #endif |
| 1491 | define(part_1_z_tsb_config_1, `0x'dnl' |
| 1492 | mpeval(PART1_Z_TSB_CONFIG_1,16))dnl |
| 1493 | |
| 1494 | #ifndef PART1_NZ_HWTEN_1 |
| 1495 | #define PART1_NZ_HWTEN_1 1 |
| 1496 | #endif |
| 1497 | #ifndef PART1_NZ_USECTX0_1 |
| 1498 | #define PART1_NZ_USECTX0_1 0 |
| 1499 | #endif |
| 1500 | #ifndef PART1_NZ_USECTX1_1 |
| 1501 | #define PART1_NZ_USECTX1_1 0 |
| 1502 | #endif |
| 1503 | #ifndef PART1_NZ_RANOTPA_1 |
| 1504 | #define PART1_NZ_RANOTPA_1 1 |
| 1505 | #endif |
| 1506 | #ifndef SUN4V |
| 1507 | #define PART1_NZ_SUN4V_1 0 |
| 1508 | #else |
| 1509 | #define PART1_NZ_SUN4V_1 1 |
| 1510 | #endif |
| 1511 | #ifndef PART1_NZ_ADDR_1 |
| 1512 | #define PART1_NZ_ADDR_1 0xc000000 |
| 1513 | #endif |
| 1514 | #ifndef PART1_NZ_TSB_SIZE_1 |
| 1515 | #define PART1_NZ_TSB_SIZE_1 1 |
| 1516 | #endif |
| 1517 | #ifndef PART1_NZ_PAGE_SIZE_1 |
| 1518 | #define PART1_NZ_PAGE_SIZE_1 0 |
| 1519 | #endif |
| 1520 | #ifndef PART1_NZ_TSB_CONFIG_1 |
| 1521 | #define PART1_NZ_TSB_CONFIG_1 ((PART1_NZ_HWTEN_1 << 63) | (PART1_NZ_USECTX0_1 << 62) | (PART1_NZ_USECTX1_1 << 61) | (PART1_NZ_ADDR_1 & 0xffffffe000) | (PART1_NZ_RANOTPA_1 << 8) | (PART1_NZ_PAGE_SIZE_1 << 4) | (PART1_NZ_TSB_SIZE_1)) |
| 1522 | #endif |
| 1523 | define(part_1_nz_tsb_config_1, `0x'dnl' |
| 1524 | mpeval(PART1_NZ_TSB_CONFIG_1,16))dnl |
| 1525 | |
| 1526 | #ifndef PART1_Z_HWTEN_2 |
| 1527 | #define PART1_Z_HWTEN_2 1 |
| 1528 | #endif |
| 1529 | #ifndef PART1_Z_USECTX0_2 |
| 1530 | #define PART1_Z_USECTX0_2 0 |
| 1531 | #endif |
| 1532 | #ifndef PART1_Z_USECTX1_2 |
| 1533 | #define PART1_Z_USECTX1_2 0 |
| 1534 | #endif |
| 1535 | #ifndef PART1_Z_RANOTPA_2 |
| 1536 | #define PART1_Z_RANOTPA_2 1 |
| 1537 | #endif |
| 1538 | #ifndef SUN4V |
| 1539 | #define PART1_Z_SUN4V_2 0 |
| 1540 | #else |
| 1541 | #define PART1_Z_SUN4V_2 1 |
| 1542 | #endif |
| 1543 | #ifndef PART1_Z_ADDR_2 |
| 1544 | #define PART1_Z_ADDR_2 0xd000000 |
| 1545 | #endif |
| 1546 | #ifndef PART1_Z_TSB_SIZE_2 |
| 1547 | #define PART1_Z_TSB_SIZE_2 1 |
| 1548 | #endif |
| 1549 | #ifndef PART1_Z_PAGE_SIZE_2 |
| 1550 | #define PART1_Z_PAGE_SIZE_2 0 |
| 1551 | #endif |
| 1552 | #ifndef PART1_Z_TSB_CONFIG_2 |
| 1553 | #define PART1_Z_TSB_CONFIG_2 ((PART1_Z_HWTEN_2 << 63) | (PART1_Z_USECTX0_2 << 62) | (PART1_Z_USECTX1_2 << 61) | (PART1_Z_ADDR_2 & 0xffffffe000) | (PART1_Z_RANOTPA_2 << 8) |(PART1_Z_PAGE_SIZE_2 << 4) | (PART1_Z_TSB_SIZE_2)) |
| 1554 | #endif |
| 1555 | define(part_1_z_tsb_config_2, `0x'dnl' |
| 1556 | mpeval(PART1_Z_TSB_CONFIG_2,16))dnl |
| 1557 | |
| 1558 | #ifndef PART1_NZ_HWTEN_2 |
| 1559 | #define PART1_NZ_HWTEN_2 1 |
| 1560 | #endif |
| 1561 | #ifndef PART1_NZ_USECTX0_2 |
| 1562 | #define PART1_NZ_USECTX0_2 0 |
| 1563 | #endif |
| 1564 | #ifndef PART1_NZ_USECTX1_2 |
| 1565 | #define PART1_NZ_USECTX1_2 0 |
| 1566 | #endif |
| 1567 | #ifndef PART1_NZ_RANOTPA_2 |
| 1568 | #define PART1_NZ_RANOTPA_2 1 |
| 1569 | #endif |
| 1570 | #ifndef SUN4V |
| 1571 | #define PART1_NZ_SUN4V_2 0 |
| 1572 | #else |
| 1573 | #define PART1_NZ_SUN4V_2 1 |
| 1574 | #endif |
| 1575 | #ifndef PART1_NZ_ADDR_2 |
| 1576 | #define PART1_NZ_ADDR_2 0xe000000 |
| 1577 | #endif |
| 1578 | #ifndef PART1_NZ_TSB_SIZE_2 |
| 1579 | #define PART1_NZ_TSB_SIZE_2 1 |
| 1580 | #endif |
| 1581 | #ifndef PART1_NZ_PAGE_SIZE_2 |
| 1582 | #define PART1_NZ_PAGE_SIZE_2 0 |
| 1583 | #endif |
| 1584 | #ifndef PART1_NZ_TSB_CONFIG_2 |
| 1585 | #define PART1_NZ_TSB_CONFIG_2 ((PART1_NZ_HWTEN_2 << 63) | (PART1_NZ_USECTX0_2 << 62) | (PART1_NZ_USECTX1_2 << 61) | (PART1_NZ_ADDR_2 & 0xffffffe000) | (PART1_NZ_RANOTPA_2 << 8) | (PART1_NZ_PAGE_SIZE_2 << 4) | (PART1_NZ_TSB_SIZE_2)) |
| 1586 | #endif |
| 1587 | define(part_1_nz_tsb_config_2, `0x'dnl' |
| 1588 | mpeval(PART1_NZ_TSB_CONFIG_2,16))dnl |
| 1589 | |
| 1590 | #ifndef PART1_Z_HWTEN_3 |
| 1591 | #define PART1_Z_HWTEN_3 1 |
| 1592 | #endif |
| 1593 | #ifndef PART1_Z_USECTX0_3 |
| 1594 | #define PART1_Z_USECTX0_3 0 |
| 1595 | #endif |
| 1596 | #ifndef PART1_Z_USECTX1_3 |
| 1597 | #define PART1_Z_USECTX1_3 0 |
| 1598 | #endif |
| 1599 | #ifndef PART1_Z_RANOTPA_3 |
| 1600 | #define PART1_Z_RANOTPA_3 1 |
| 1601 | #endif |
| 1602 | #ifndef SUN4V |
| 1603 | #define PART1_Z_SUN4V_3 0 |
| 1604 | #else |
| 1605 | #define PART1_Z_SUN4V_3 1 |
| 1606 | #endif |
| 1607 | #ifndef PART1_Z_ADDR_3 |
| 1608 | #define PART1_Z_ADDR_3 0xf000000 |
| 1609 | #endif |
| 1610 | #ifndef PART1_Z_TSB_SIZE_3 |
| 1611 | #define PART1_Z_TSB_SIZE_3 1 |
| 1612 | #endif |
| 1613 | #ifndef PART1_Z_PAGE_SIZE_3 |
| 1614 | #define PART1_Z_PAGE_SIZE_3 0 |
| 1615 | #endif |
| 1616 | #ifndef PART1_Z_TSB_CONFIG_3 |
| 1617 | #define PART1_Z_TSB_CONFIG_3 ((PART1_Z_HWTEN_3 << 63) | (PART1_Z_USECTX0_3 << 62) | (PART1_Z_USECTX1_3 << 61) | (PART1_Z_ADDR_3 & 0xffffffe000) | (PART1_Z_RANOTPA_3 << 8) | (PART1_Z_PAGE_SIZE_3 << 4) | (PART1_Z_TSB_SIZE_3)) |
| 1618 | #endif |
| 1619 | define(part_1_z_tsb_config_3, `0x'dnl' |
| 1620 | mpeval(PART1_Z_TSB_CONFIG_3,16))dnl |
| 1621 | |
| 1622 | #ifndef PART1_NZ_HWTEN_3 |
| 1623 | #define PART1_NZ_HWTEN_3 1 |
| 1624 | #endif |
| 1625 | #ifndef PART1_NZ_USECTX0_3 |
| 1626 | #define PART1_NZ_USECTX0_3 0 |
| 1627 | #endif |
| 1628 | #ifndef PART1_NZ_USECTX1_3 |
| 1629 | #define PART1_NZ_USECTX1_3 0 |
| 1630 | #endif |
| 1631 | #ifndef PART1_NZ_RANOTPA_3 |
| 1632 | #define PART1_NZ_RANOTPA_3 1 |
| 1633 | #endif |
| 1634 | #ifndef SUN4V |
| 1635 | #define PART1_NZ_SUN4V_3 0 |
| 1636 | #else |
| 1637 | #define PART1_NZ_SUN4V_3 1 |
| 1638 | #endif |
| 1639 | #ifndef PART1_NZ_ADDR_3 |
| 1640 | #define PART1_NZ_ADDR_3 0x10000000 |
| 1641 | #endif |
| 1642 | #ifndef PART1_NZ_TSB_SIZE_3 |
| 1643 | #define PART1_NZ_TSB_SIZE_3 1 |
| 1644 | #endif |
| 1645 | #ifndef PART1_NZ_PAGE_SIZE_3 |
| 1646 | #define PART1_NZ_PAGE_SIZE_3 0 |
| 1647 | #endif |
| 1648 | #ifndef PART1_NZ_TSB_CONFIG_3 |
| 1649 | #define PART1_NZ_TSB_CONFIG_3 ((PART1_NZ_HWTEN_3 << 63) | (PART1_NZ_USECTX0_3 << 62) | (PART1_NZ_USECTX1_3 << 61) | (PART1_NZ_ADDR_3 & 0xffffffe000) | (PART1_NZ_RANOTPA_3 << 8) | (PART1_NZ_PAGE_SIZE_3 << 4) | (PART1_NZ_TSB_SIZE_3)) |
| 1650 | #endif |
| 1651 | define(part_1_nz_tsb_config_3, `0x'dnl' |
| 1652 | mpeval(PART1_NZ_TSB_CONFIG_3,16))dnl |
| 1653 | |
| 1654 | |
| 1655 | #ifndef PART1_PHY_OFF_X_0 |
| 1656 | #define PART1_PHY_OFF_X_0 1 |
| 1657 | #endif |
| 1658 | #ifndef PART1_PHY_OFF_P_0 |
| 1659 | #define PART1_PHY_OFF_P_0 0 |
| 1660 | #endif |
| 1661 | #ifndef PART1_PHY_OFF_W_0 |
| 1662 | #define PART1_PHY_OFF_W_0 0 |
| 1663 | #endif |
| 1664 | #ifndef PART1_PHY_OFF_0 |
| 1665 | #define PART1_PHY_OFF_0 ((PART_1_BASE) | (PART1_PHY_OFF_X_1 << 12) | (PART1_PHY_OFF_P_1 << 11) | (PART1_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 1666 | #endif |
| 1667 | |
| 1668 | #ifndef PART1_PHY_OFF_X_1 |
| 1669 | #define PART1_PHY_OFF_X_1 1 |
| 1670 | #endif |
| 1671 | #ifndef PART1_PHY_OFF_P_1 |
| 1672 | #define PART1_PHY_OFF_P_1 0 |
| 1673 | #endif |
| 1674 | #ifndef PART1_PHY_OFF_W_1 |
| 1675 | #define PART1_PHY_OFF_W_1 0 |
| 1676 | #endif |
| 1677 | #ifndef PART1_PHY_OFF_1 |
| 1678 | #define PART1_PHY_OFF_1 ((PART_1_BASE) | (PART1_PHY_OFF_X_1 << 12) | (PART1_PHY_OFF_P_1 << 11) | (PART1_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 1679 | #endif |
| 1680 | |
| 1681 | #ifndef PART1_PHY_OFF_X_2 |
| 1682 | #define PART1_PHY_OFF_X_2 1 |
| 1683 | #endif |
| 1684 | #ifndef PART1_PHY_OFF_P_2 |
| 1685 | #define PART1_PHY_OFF_P_2 0 |
| 1686 | #endif |
| 1687 | #ifndef PART1_PHY_OFF_W_2 |
| 1688 | #define PART1_PHY_OFF_W_2 0 |
| 1689 | #endif |
| 1690 | #ifndef PART1_PHY_OFF_2 |
| 1691 | #define PART1_PHY_OFF_2 ((PART_1_BASE) | (PART1_PHY_OFF_X_2 << 12) | (PART1_PHY_OFF_P_2 << 11) | (PART1_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 1692 | #endif |
| 1693 | |
| 1694 | #ifndef PART1_PHY_OFF_X_3 |
| 1695 | #define PART1_PHY_OFF_X_3 1 |
| 1696 | #endif |
| 1697 | #ifndef PART1_PHY_OFF_P_3 |
| 1698 | #define PART1_PHY_OFF_P_3 0 |
| 1699 | #endif |
| 1700 | #ifndef PART1_PHY_OFF_W_3 |
| 1701 | #define PART1_PHY_OFF_W_3 0 |
| 1702 | #endif |
| 1703 | #ifndef PART1_PHY_OFF_3 |
| 1704 | #define PART1_PHY_OFF_3 ((PART_1_BASE) | (PART1_PHY_OFF_X_3 << 12) | (PART1_PHY_OFF_P_3 << 11) | (PART1_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 1705 | #endif |
| 1706 | |
| 1707 | dnl 2 //////////////////////// |
| 1708 | |
| 1709 | #ifndef PART2_Z_HWTEN_0 |
| 1710 | #define PART2_Z_HWTEN_0 1 |
| 1711 | #endif |
| 1712 | #ifndef PART2_Z_USECTX0_0 |
| 1713 | #define PART2_Z_USECTX0_0 0 |
| 1714 | #endif |
| 1715 | #ifndef PART2_Z_USECTX1_0 |
| 1716 | #define PART2_Z_USECTX1_0 0 |
| 1717 | #endif |
| 1718 | #ifndef PART2_Z_RANOTPA_0 |
| 1719 | #define PART2_Z_RANOTPA_0 1 |
| 1720 | #endif |
| 1721 | #ifndef SUN4V |
| 1722 | #define PART2_Z_SUN4V_0 0 |
| 1723 | #else |
| 1724 | #define PART2_Z_SUN4V_0 1 |
| 1725 | #endif |
| 1726 | #ifndef PART2_Z_ADDR_0 |
| 1727 | #define PART2_Z_ADDR_0 0x11000000 |
| 1728 | #endif |
| 1729 | #ifndef PART2_Z_TSB_SIZE_0 |
| 1730 | #define PART2_Z_TSB_SIZE_0 1 |
| 1731 | #endif |
| 1732 | #ifndef PART2_Z_PAGE_SIZE_0 |
| 1733 | #define PART2_Z_PAGE_SIZE_0 0 |
| 1734 | #endif |
| 1735 | #ifndef PART2_Z_TSB_CONFIG_0 |
| 1736 | #define PART2_Z_TSB_CONFIG_0 ((PART2_Z_HWTEN_0 << 63) | (PART2_Z_USECTX0_0 << 62) | (PART2_Z_USECTX1_0 << 61) | (PART2_Z_ADDR_0 & 0xffffffe000) | (PART2_Z_RANOTPA_0 << 8) | (PART2_Z_PAGE_SIZE_0 << 4) | (PART2_Z_TSB_SIZE_0)) |
| 1737 | #endif |
| 1738 | define(part_2_z_tsb_config_0, `0x'dnl' |
| 1739 | mpeval(PART2_Z_TSB_CONFIG_0,16))dnl |
| 1740 | |
| 1741 | #ifndef PART2_NZ_HWTEN_0 |
| 1742 | #define PART2_NZ_HWTEN_0 1 |
| 1743 | #endif |
| 1744 | #ifndef PART2_NZ_USECTX0_0 |
| 1745 | #define PART2_NZ_USECTX0_0 0 |
| 1746 | #endif |
| 1747 | #ifndef PART2_NZ_USECTX1_0 |
| 1748 | #define PART2_NZ_USECTX1_0 0 |
| 1749 | #endif |
| 1750 | #ifndef PART2_NZ_RANOTPA_0 |
| 1751 | #define PART2_NZ_RANOTPA_0 1 |
| 1752 | #endif |
| 1753 | #ifndef SUN4V |
| 1754 | #define PART2_NZ_SUN4V_0 0 |
| 1755 | #else |
| 1756 | #define PART2_NZ_SUN4V_0 1 |
| 1757 | #endif |
| 1758 | #ifndef PART2_NZ_ADDR_0 |
| 1759 | #define PART2_NZ_ADDR_0 0x12000000 |
| 1760 | #endif |
| 1761 | #ifndef PART2_NZ_TSB_SIZE_0 |
| 1762 | #define PART2_NZ_TSB_SIZE_0 1 |
| 1763 | #endif |
| 1764 | #ifndef PART2_NZ_PAGE_SIZE_0 |
| 1765 | #define PART2_NZ_PAGE_SIZE_0 0 |
| 1766 | #endif |
| 1767 | #ifndef PART2_NZ_TSB_CONFIG_0 |
| 1768 | #define PART2_NZ_TSB_CONFIG_0 ((PART2_NZ_HWTEN_0 << 63) | (PART2_NZ_USECTX0_0 << 62) | (PART2_NZ_USECTX1_0 << 61) | (PART2_NZ_ADDR_0 & 0xffffffe000) | (PART2_NZ_RANOTPA_0 << 8) | (PART2_NZ_PAGE_SIZE_0 << 4) | (PART2_NZ_TSB_SIZE_0)) |
| 1769 | #endif |
| 1770 | define(part_2_nz_tsb_config_0, `0x'dnl' |
| 1771 | mpeval(PART2_NZ_TSB_CONFIG_0,16))dnl |
| 1772 | |
| 1773 | #ifndef PART2_Z_HWTEN_1 |
| 1774 | #define PART2_Z_HWTEN_1 1 |
| 1775 | #endif |
| 1776 | #ifndef PART2_Z_USECTX0_1 |
| 1777 | #define PART2_Z_USECTX0_1 0 |
| 1778 | #endif |
| 1779 | #ifndef PART2_Z_USECTX1_1 |
| 1780 | #define PART2_Z_USECTX1_1 0 |
| 1781 | #endif |
| 1782 | #ifndef PART2_Z_RANOTPA_1 |
| 1783 | #define PART2_Z_RANOTPA_1 1 |
| 1784 | #endif |
| 1785 | #ifndef SUN4V |
| 1786 | #define PART2_Z_SUN4V_1 0 |
| 1787 | #else |
| 1788 | #define PART2_Z_SUN4V_1 1 |
| 1789 | #endif |
| 1790 | #ifndef PART2_Z_ADDR_1 |
| 1791 | #define PART2_Z_ADDR_1 0x13000000 |
| 1792 | #endif |
| 1793 | #ifndef PART2_Z_TSB_SIZE_1 |
| 1794 | #define PART2_Z_TSB_SIZE_1 1 |
| 1795 | #endif |
| 1796 | #ifndef PART2_Z_PAGE_SIZE_1 |
| 1797 | #define PART2_Z_PAGE_SIZE_1 0 |
| 1798 | #endif |
| 1799 | #ifndef PART2_Z_TSB_CONFIG_1 |
| 1800 | #define PART2_Z_TSB_CONFIG_1 ((PART2_Z_HWTEN_1 << 63) | (PART2_Z_USECTX0_1 << 62) | (PART2_Z_USECTX1_1 << 61) | (PART2_Z_ADDR_1 & 0xffffffe000) | (PART2_Z_RANOTPA_1 << 8) | (PART2_Z_PAGE_SIZE_1 << 4) | (PART2_Z_TSB_SIZE_1)) |
| 1801 | #endif |
| 1802 | define(part_2_z_tsb_config_1, `0x'dnl' |
| 1803 | mpeval(PART2_Z_TSB_CONFIG_1,16))dnl |
| 1804 | |
| 1805 | #ifndef PART2_NZ_HWTEN_1 |
| 1806 | #define PART2_NZ_HWTEN_1 1 |
| 1807 | #endif |
| 1808 | #ifndef PART2_NZ_USECTX0_1 |
| 1809 | #define PART2_NZ_USECTX0_1 0 |
| 1810 | #endif |
| 1811 | #ifndef PART2_NZ_USECTX1_1 |
| 1812 | #define PART2_NZ_USECTX1_1 0 |
| 1813 | #endif |
| 1814 | #ifndef PART2_NZ_RANOTPA_1 |
| 1815 | #define PART2_NZ_RANOTPA_1 1 |
| 1816 | #endif |
| 1817 | #ifndef SUN4V |
| 1818 | #define PART2_NZ_SUN4V_1 0 |
| 1819 | #else |
| 1820 | #define PART2_NZ_SUN4V_1 1 |
| 1821 | #endif |
| 1822 | #ifndef PART2_NZ_ADDR_1 |
| 1823 | #define PART2_NZ_ADDR_1 0x14000000 |
| 1824 | #endif |
| 1825 | #ifndef PART2_NZ_TSB_SIZE_1 |
| 1826 | #define PART2_NZ_TSB_SIZE_1 1 |
| 1827 | #endif |
| 1828 | #ifndef PART2_NZ_PAGE_SIZE_1 |
| 1829 | #define PART2_NZ_PAGE_SIZE_1 0 |
| 1830 | #endif |
| 1831 | #ifndef PART2_NZ_TSB_CONFIG_1 |
| 1832 | #define PART2_NZ_TSB_CONFIG_1 ((PART2_NZ_HWTEN_1 << 63) | (PART2_NZ_USECTX0_1 << 62) | (PART2_NZ_USECTX1_1 << 61) | (PART2_NZ_ADDR_1 & 0xffffffe000) | (PART2_NZ_RANOTPA_1 << 8) | (PART2_NZ_PAGE_SIZE_1 << 4) | (PART2_NZ_TSB_SIZE_1)) |
| 1833 | #endif |
| 1834 | define(part_2_nz_tsb_config_1, `0x'dnl' |
| 1835 | mpeval(PART2_NZ_TSB_CONFIG_1,16))dnl |
| 1836 | |
| 1837 | #ifndef PART2_Z_HWTEN_2 |
| 1838 | #define PART2_Z_HWTEN_2 1 |
| 1839 | #endif |
| 1840 | #ifndef PART2_Z_USECTX0_2 |
| 1841 | #define PART2_Z_USECTX0_2 0 |
| 1842 | #endif |
| 1843 | #ifndef PART2_Z_USECTX1_2 |
| 1844 | #define PART2_Z_USECTX1_2 0 |
| 1845 | #endif |
| 1846 | #ifndef PART2_Z_RANOTPA_2 |
| 1847 | #define PART2_Z_RANOTPA_2 1 |
| 1848 | #endif |
| 1849 | #ifndef SUN4V |
| 1850 | #define PART2_Z_SUN4V_2 0 |
| 1851 | #else |
| 1852 | #define PART2_Z_SUN4V_2 1 |
| 1853 | #endif |
| 1854 | #ifndef PART2_Z_ADDR_2 |
| 1855 | #define PART2_Z_ADDR_2 0x15000000 |
| 1856 | #endif |
| 1857 | #ifndef PART2_Z_TSB_SIZE_2 |
| 1858 | #define PART2_Z_TSB_SIZE_2 1 |
| 1859 | #endif |
| 1860 | #ifndef PART2_Z_PAGE_SIZE_2 |
| 1861 | #define PART2_Z_PAGE_SIZE_2 0 |
| 1862 | #endif |
| 1863 | #ifndef PART2_Z_TSB_CONFIG_2 |
| 1864 | #define PART2_Z_TSB_CONFIG_2 ((PART2_Z_HWTEN_2 << 63) | (PART2_Z_USECTX0_2 << 62) | (PART2_Z_USECTX1_2 << 61) | (PART2_Z_ADDR_2 & 0xffffffe000) | (PART2_Z_RANOTPA_2 << 8) | (PART2_Z_PAGE_SIZE_2 << 4) | (PART2_Z_TSB_SIZE_2)) |
| 1865 | #endif |
| 1866 | define(part_2_z_tsb_config_2, `0x'dnl' |
| 1867 | mpeval(PART2_Z_TSB_CONFIG_2,16))dnl |
| 1868 | |
| 1869 | #ifndef PART2_NZ_HWTEN_2 |
| 1870 | #define PART2_NZ_HWTEN_2 1 |
| 1871 | #endif |
| 1872 | #ifndef PART2_NZ_USECTX0_2 |
| 1873 | #define PART2_NZ_USECTX0_2 0 |
| 1874 | #endif |
| 1875 | #ifndef PART2_NZ_USECTX1_2 |
| 1876 | #define PART2_NZ_USECTX1_2 0 |
| 1877 | #endif |
| 1878 | #ifndef PART2_NZ_RANOTPA_2 |
| 1879 | #define PART2_NZ_RANOTPA_2 1 |
| 1880 | #endif |
| 1881 | #ifndef SUN4V |
| 1882 | #define PART2_NZ_SUN4V_2 0 |
| 1883 | #else |
| 1884 | #define PART2_NZ_SUN4V_2 1 |
| 1885 | #endif |
| 1886 | #ifndef PART2_NZ_ADDR_2 |
| 1887 | #define PART2_NZ_ADDR_2 0x16000000 |
| 1888 | #endif |
| 1889 | #ifndef PART2_NZ_TSB_SIZE_2 |
| 1890 | #define PART2_NZ_TSB_SIZE_2 1 |
| 1891 | #endif |
| 1892 | #ifndef PART2_NZ_PAGE_SIZE_2 |
| 1893 | #define PART2_NZ_PAGE_SIZE_2 0 |
| 1894 | #endif |
| 1895 | #ifndef PART2_NZ_TSB_CONFIG_2 |
| 1896 | #define PART2_NZ_TSB_CONFIG_2 ((PART2_NZ_HWTEN_2 << 63) | (PART2_NZ_USECTX0_2 << 62) | (PART2_NZ_USECTX1_2 << 61) | (PART2_NZ_ADDR_2 & 0xffffffe000) | (PART2_NZ_RANOTPA_2 << 8) | (PART2_NZ_PAGE_SIZE_2 << 4) | (PART2_NZ_TSB_SIZE_2)) |
| 1897 | #endif |
| 1898 | define(part_2_nz_tsb_config_2, `0x'dnl' |
| 1899 | mpeval(PART2_NZ_TSB_CONFIG_2,16))dnl |
| 1900 | |
| 1901 | #ifndef PART2_Z_HWTEN_3 |
| 1902 | #define PART2_Z_HWTEN_3 1 |
| 1903 | #endif |
| 1904 | #ifndef PART2_Z_USECTX0_3 |
| 1905 | #define PART2_Z_USECTX0_3 0 |
| 1906 | #endif |
| 1907 | #ifndef PART2_Z_USECTX1_3 |
| 1908 | #define PART2_Z_USECTX1_3 0 |
| 1909 | #endif |
| 1910 | #ifndef PART2_Z_RANOTPA_3 |
| 1911 | #define PART2_Z_RANOTPA_3 1 |
| 1912 | #endif |
| 1913 | #ifndef SUN4V |
| 1914 | #define PART2_Z_SUN4V_3 0 |
| 1915 | #else |
| 1916 | #define PART2_Z_SUN4V_3 1 |
| 1917 | #endif |
| 1918 | #ifndef PART2_Z_ADDR_3 |
| 1919 | #define PART2_Z_ADDR_3 0x17000000 |
| 1920 | #endif |
| 1921 | #ifndef PART2_Z_TSB_SIZE_3 |
| 1922 | #define PART2_Z_TSB_SIZE_3 1 |
| 1923 | #endif |
| 1924 | #ifndef PART2_Z_PAGE_SIZE_3 |
| 1925 | #define PART2_Z_PAGE_SIZE_3 0 |
| 1926 | #endif |
| 1927 | #ifndef PART2_Z_TSB_CONFIG_3 |
| 1928 | #define PART2_Z_TSB_CONFIG_3 ((PART2_Z_HWTEN_3 << 63) | (PART2_Z_USECTX0_3 << 62) | (PART2_Z_USECTX1_3 << 61) | (PART2_Z_ADDR_3 & 0xffffffe000) | (PART2_Z_RANOTPA_3 << 8) | (PART2_Z_PAGE_SIZE_3 << 4) | (PART2_Z_TSB_SIZE_3)) |
| 1929 | #endif |
| 1930 | define(part_2_z_tsb_config_3, `0x'dnl' |
| 1931 | mpeval(PART2_Z_TSB_CONFIG_3,16))dnl |
| 1932 | |
| 1933 | #ifndef PART2_NZ_HWTEN_3 |
| 1934 | #define PART2_NZ_HWTEN_3 1 |
| 1935 | #endif |
| 1936 | #ifndef PART2_NZ_USECTX0_3 |
| 1937 | #define PART2_NZ_USECTX0_3 0 |
| 1938 | #endif |
| 1939 | #ifndef PART2_NZ_USECTX1_3 |
| 1940 | #define PART2_NZ_USECTX1_3 0 |
| 1941 | #endif |
| 1942 | #ifndef PART2_NZ_RANOTPA_3 |
| 1943 | #define PART2_NZ_RANOTPA_3 1 |
| 1944 | #endif |
| 1945 | #ifndef SUN4V |
| 1946 | #define PART2_NZ_SUN4V_3 0 |
| 1947 | #else |
| 1948 | #define PART2_NZ_SUN4V_3 1 |
| 1949 | #endif |
| 1950 | #ifndef PART2_NZ_ADDR_3 |
| 1951 | #define PART2_NZ_ADDR_3 0x18000000 |
| 1952 | #endif |
| 1953 | #ifndef PART2_NZ_TSB_SIZE_3 |
| 1954 | #define PART2_NZ_TSB_SIZE_3 1 |
| 1955 | #endif |
| 1956 | #ifndef PART2_NZ_PAGE_SIZE_3 |
| 1957 | #define PART2_NZ_PAGE_SIZE_3 0 |
| 1958 | #endif |
| 1959 | #ifndef PART2_NZ_TSB_CONFIG_3 |
| 1960 | #define PART2_NZ_TSB_CONFIG_3 ((PART2_NZ_HWTEN_3 << 63) | (PART2_NZ_USECTX0_3 << 62) | (PART2_NZ_USECTX1_3 << 61) | (PART2_NZ_ADDR_3 & 0xffffffe000) | (PART2_NZ_RANOTPA_3 << 8) | (PART2_NZ_PAGE_SIZE_3 << 4) | (PART2_NZ_TSB_SIZE_3)) |
| 1961 | #endif |
| 1962 | define(part_2_nz_tsb_config_3, `0x'dnl' |
| 1963 | mpeval(PART2_NZ_TSB_CONFIG_3,16))dnl |
| 1964 | |
| 1965 | |
| 1966 | #ifndef PART2_PHY_OFF_X_0 |
| 1967 | #define PART2_PHY_OFF_X_0 1 |
| 1968 | #endif |
| 1969 | #ifndef PART2_PHY_OFF_P_0 |
| 1970 | #define PART2_PHY_OFF_P_0 0 |
| 1971 | #endif |
| 1972 | #ifndef PART2_PHY_OFF_W_0 |
| 1973 | #define PART2_PHY_OFF_W_0 0 |
| 1974 | #endif |
| 1975 | #ifndef PART2_PHY_OFF_0 |
| 1976 | #define PART2_PHY_OFF_0 ((PART_2_BASE) | (PART2_PHY_OFF_X_1 << 12) | (PART2_PHY_OFF_P_1 << 11) | (PART2_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 1977 | #endif |
| 1978 | |
| 1979 | #ifndef PART2_PHY_OFF_X_1 |
| 1980 | #define PART2_PHY_OFF_X_1 1 |
| 1981 | #endif |
| 1982 | #ifndef PART2_PHY_OFF_P_1 |
| 1983 | #define PART2_PHY_OFF_P_1 0 |
| 1984 | #endif |
| 1985 | #ifndef PART2_PHY_OFF_W_1 |
| 1986 | #define PART2_PHY_OFF_W_1 0 |
| 1987 | #endif |
| 1988 | #ifndef PART2_PHY_OFF_1 |
| 1989 | #define PART2_PHY_OFF_1 ((PART_2_BASE) | (PART2_PHY_OFF_X_1 << 12) | (PART2_PHY_OFF_P_1 << 11) | (PART2_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 1990 | #endif |
| 1991 | |
| 1992 | #ifndef PART2_PHY_OFF_X_2 |
| 1993 | #define PART2_PHY_OFF_X_2 1 |
| 1994 | #endif |
| 1995 | #ifndef PART2_PHY_OFF_P_2 |
| 1996 | #define PART2_PHY_OFF_P_2 0 |
| 1997 | #endif |
| 1998 | #ifndef PART2_PHY_OFF_W_2 |
| 1999 | #define PART2_PHY_OFF_W_2 0 |
| 2000 | #endif |
| 2001 | #ifndef PART2_PHY_OFF_2 |
| 2002 | #define PART2_PHY_OFF_2 ((PART_2_BASE) | (PART2_PHY_OFF_X_2 << 12) | (PART2_PHY_OFF_P_2 << 11) | (PART2_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 2003 | #endif |
| 2004 | |
| 2005 | #ifndef PART2_PHY_OFF_X_3 |
| 2006 | #define PART2_PHY_OFF_X_3 1 |
| 2007 | #endif |
| 2008 | #ifndef PART2_PHY_OFF_P_3 |
| 2009 | #define PART2_PHY_OFF_P_3 0 |
| 2010 | #endif |
| 2011 | #ifndef PART2_PHY_OFF_W_3 |
| 2012 | #define PART2_PHY_OFF_W_3 0 |
| 2013 | #endif |
| 2014 | #ifndef PART2_PHY_OFF_3 |
| 2015 | #define PART2_PHY_OFF_3 ((PART_2_BASE) | (PART2_PHY_OFF_X_3 << 12) | (PART2_PHY_OFF_P_3 << 11) | (PART2_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 2016 | #endif |
| 2017 | |
| 2018 | dnl 3 //////////////////////// |
| 2019 | |
| 2020 | #ifndef PART3_Z_HWTEN_0 |
| 2021 | #define PART3_Z_HWTEN_0 1 |
| 2022 | #endif |
| 2023 | #ifndef PART3_Z_USECTX0_0 |
| 2024 | #define PART3_Z_USECTX0_0 0 |
| 2025 | #endif |
| 2026 | #ifndef PART3_Z_USECTX1_0 |
| 2027 | #define PART3_Z_USECTX1_0 0 |
| 2028 | #endif |
| 2029 | #ifndef PART3_Z_RANOTPA_0 |
| 2030 | #define PART3_Z_RANOTPA_0 1 |
| 2031 | #endif |
| 2032 | #ifndef SUN4V |
| 2033 | #define PART3_Z_SUN4V_0 0 |
| 2034 | #else |
| 2035 | #define PART3_Z_SUN4V_0 1 |
| 2036 | #endif |
| 2037 | #ifndef PART3_Z_ADDR_0 |
| 2038 | #define PART3_Z_ADDR_0 0x19000000 |
| 2039 | #endif |
| 2040 | #ifndef PART3_Z_TSB_SIZE_0 |
| 2041 | #define PART3_Z_TSB_SIZE_0 1 |
| 2042 | #endif |
| 2043 | #ifndef PART3_Z_PAGE_SIZE_0 |
| 2044 | #define PART3_Z_PAGE_SIZE_0 0 |
| 2045 | #endif |
| 2046 | #ifndef PART3_Z_TSB_CONFIG_0 |
| 2047 | #define PART3_Z_TSB_CONFIG_0 ((PART3_Z_HWTEN_0 << 63) | (PART3_Z_USECTX0_0 << 62) | (PART3_Z_USECTX1_0 << 61) | (PART3_Z_ADDR_0 & 0xffffffe000) | (PART3_Z_RANOTPA_0 << 8) | (PART3_Z_PAGE_SIZE_0 << 4) | (PART3_Z_TSB_SIZE_0)) |
| 2048 | #endif |
| 2049 | define(part_3_z_tsb_config_0, `0x'dnl' |
| 2050 | mpeval(PART3_Z_TSB_CONFIG_0,16))dnl |
| 2051 | |
| 2052 | #ifndef PART3_NZ_HWTEN_0 |
| 2053 | #define PART3_NZ_HWTEN_0 1 |
| 2054 | #endif |
| 2055 | #ifndef PART3_NZ_USECTX0_0 |
| 2056 | #define PART3_NZ_USECTX0_0 0 |
| 2057 | #endif |
| 2058 | #ifndef PART3_NZ_USECTX1_0 |
| 2059 | #define PART3_NZ_USECTX1_0 0 |
| 2060 | #endif |
| 2061 | #ifndef PART3_NZ_RANOTPA_0 |
| 2062 | #define PART3_NZ_RANOTPA_0 1 |
| 2063 | #endif |
| 2064 | #ifndef SUN4V |
| 2065 | #define PART3_NZ_SUN4V_0 0 |
| 2066 | #else |
| 2067 | #define PART3_NZ_SUN4V_0 1 |
| 2068 | #endif |
| 2069 | #ifndef PART3_NZ_ADDR_0 |
| 2070 | #define PART3_NZ_ADDR_0 0x1a000000 |
| 2071 | #endif |
| 2072 | #ifndef PART3_NZ_TSB_SIZE_0 |
| 2073 | #define PART3_NZ_TSB_SIZE_0 1 |
| 2074 | #endif |
| 2075 | #ifndef PART3_NZ_PAGE_SIZE_0 |
| 2076 | #define PART3_NZ_PAGE_SIZE_0 0 |
| 2077 | #endif |
| 2078 | #ifndef PART3_NZ_TSB_CONFIG_0 |
| 2079 | #define PART3_NZ_TSB_CONFIG_0 ((PART3_NZ_HWTEN_0 << 63) | (PART3_NZ_USECTX0_0 << 62) | (PART3_NZ_USECTX1_0 << 61) | (PART3_NZ_ADDR_0 & 0xffffffe000) | (PART3_NZ_RANOTPA_0 << 8) | (PART3_NZ_PAGE_SIZE_0 << 4) | (PART3_NZ_TSB_SIZE_0)) |
| 2080 | #endif |
| 2081 | define(part_3_nz_tsb_config_0, `0x'dnl' |
| 2082 | mpeval(PART3_NZ_TSB_CONFIG_0,16))dnl |
| 2083 | |
| 2084 | #ifndef PART3_Z_HWTEN_1 |
| 2085 | #define PART3_Z_HWTEN_1 1 |
| 2086 | #endif |
| 2087 | #ifndef PART3_Z_USECTX0_1 |
| 2088 | #define PART3_Z_USECTX0_1 0 |
| 2089 | #endif |
| 2090 | #ifndef PART3_Z_USECTX1_1 |
| 2091 | #define PART3_Z_USECTX1_1 0 |
| 2092 | #endif |
| 2093 | #ifndef PART3_Z_RANOTPA_1 |
| 2094 | #define PART3_Z_RANOTPA_1 1 |
| 2095 | #endif |
| 2096 | #ifndef SUN4V |
| 2097 | #define PART3_Z_SUN4V_1 0 |
| 2098 | #else |
| 2099 | #define PART3_Z_SUN4V_1 1 |
| 2100 | #endif |
| 2101 | #ifndef PART3_Z_ADDR_1 |
| 2102 | #define PART3_Z_ADDR_1 0x1b000000 |
| 2103 | #endif |
| 2104 | #ifndef PART3_Z_TSB_SIZE_1 |
| 2105 | #define PART3_Z_TSB_SIZE_1 1 |
| 2106 | #endif |
| 2107 | #ifndef PART3_Z_PAGE_SIZE_1 |
| 2108 | #define PART3_Z_PAGE_SIZE_1 0 |
| 2109 | #endif |
| 2110 | #ifndef PART3_Z_TSB_CONFIG_1 |
| 2111 | #define PART3_Z_TSB_CONFIG_1 ((PART3_Z_HWTEN_1 << 63) | (PART3_Z_USECTX0_1 << 62) | (PART3_Z_USECTX1_1 << 61) | (PART3_Z_ADDR_1 & 0xffffffe000) | (PART3_Z_RANOTPA_1 << 8) | (PART3_Z_PAGE_SIZE_1 << 4) | (PART3_Z_TSB_SIZE_1)) |
| 2112 | #endif |
| 2113 | define(part_3_z_tsb_config_1, `0x'dnl' |
| 2114 | mpeval(PART3_Z_TSB_CONFIG_1,16))dnl |
| 2115 | |
| 2116 | #ifndef PART3_NZ_HWTEN_1 |
| 2117 | #define PART3_NZ_HWTEN_1 1 |
| 2118 | #endif |
| 2119 | #ifndef PART3_NZ_USECTX0_1 |
| 2120 | #define PART3_NZ_USECTX0_1 0 |
| 2121 | #endif |
| 2122 | #ifndef PART3_NZ_USECTX1_1 |
| 2123 | #define PART3_NZ_USECTX1_1 0 |
| 2124 | #endif |
| 2125 | #ifndef PART3_NZ_RANOTPA_1 |
| 2126 | #define PART3_NZ_RANOTPA_1 1 |
| 2127 | #endif |
| 2128 | #ifndef SUN4V |
| 2129 | #define PART3_NZ_SUN4V_1 0 |
| 2130 | #else |
| 2131 | #define PART3_NZ_SUN4V_1 1 |
| 2132 | #endif |
| 2133 | #ifndef PART3_NZ_ADDR_1 |
| 2134 | #define PART3_NZ_ADDR_1 0x1c000000 |
| 2135 | #endif |
| 2136 | #ifndef PART3_NZ_TSB_SIZE_1 |
| 2137 | #define PART3_NZ_TSB_SIZE_1 1 |
| 2138 | #endif |
| 2139 | #ifndef PART3_NZ_PAGE_SIZE_1 |
| 2140 | #define PART3_NZ_PAGE_SIZE_1 0 |
| 2141 | #endif |
| 2142 | #ifndef PART3_NZ_TSB_CONFIG_1 |
| 2143 | #define PART3_NZ_TSB_CONFIG_1 ((PART3_NZ_HWTEN_1 << 63) | (PART3_NZ_USECTX0_1 << 62) | (PART3_NZ_USECTX1_1 << 61) | (PART3_NZ_ADDR_1 & 0xffffffe000) | (PART3_NZ_RANOTPA_1 << 8) | (PART3_NZ_PAGE_SIZE_1 << 4) | (PART3_NZ_TSB_SIZE_1)) |
| 2144 | #endif |
| 2145 | define(part_3_nz_tsb_config_1, `0x'dnl' |
| 2146 | mpeval(PART3_NZ_TSB_CONFIG_1,16))dnl |
| 2147 | |
| 2148 | #ifndef PART3_Z_HWTEN_2 |
| 2149 | #define PART3_Z_HWTEN_2 1 |
| 2150 | #endif |
| 2151 | #ifndef PART3_Z_USECTX0_2 |
| 2152 | #define PART3_Z_USECTX0_2 0 |
| 2153 | #endif |
| 2154 | #ifndef PART3_Z_USECTX1_2 |
| 2155 | #define PART3_Z_USECTX1_2 0 |
| 2156 | #endif |
| 2157 | #ifndef PART3_Z_RANOTPA_2 |
| 2158 | #define PART3_Z_RANOTPA_2 1 |
| 2159 | #endif |
| 2160 | #ifndef SUN4V |
| 2161 | #define PART3_Z_SUN4V_2 0 |
| 2162 | #else |
| 2163 | #define PART3_Z_SUN4V_2 1 |
| 2164 | #endif |
| 2165 | #ifndef PART3_Z_ADDR_2 |
| 2166 | #define PART3_Z_ADDR_2 0x1d000000 |
| 2167 | #endif |
| 2168 | #ifndef PART3_Z_TSB_SIZE_2 |
| 2169 | #define PART3_Z_TSB_SIZE_2 1 |
| 2170 | #endif |
| 2171 | #ifndef PART3_Z_PAGE_SIZE_2 |
| 2172 | #define PART3_Z_PAGE_SIZE_2 0 |
| 2173 | #endif |
| 2174 | #ifndef PART3_Z_TSB_CONFIG_2 |
| 2175 | #define PART3_Z_TSB_CONFIG_2 ((PART3_Z_HWTEN_2 << 63) | (PART3_Z_USECTX0_2 << 62) | (PART3_Z_USECTX1_2 << 61) | (PART3_Z_ADDR_2 & 0xffffffe000) | (PART3_Z_RANOTPA_2 << 8) | (PART3_Z_PAGE_SIZE_2 << 4) | (PART3_Z_TSB_SIZE_2)) |
| 2176 | #endif |
| 2177 | define(part_3_z_tsb_config_2, `0x'dnl' |
| 2178 | mpeval(PART3_Z_TSB_CONFIG_2,16))dnl |
| 2179 | |
| 2180 | #ifndef PART3_NZ_HWTEN_2 |
| 2181 | #define PART3_NZ_HWTEN_2 1 |
| 2182 | #endif |
| 2183 | #ifndef PART3_NZ_USECTX0_2 |
| 2184 | #define PART3_NZ_USECTX0_2 0 |
| 2185 | #endif |
| 2186 | #ifndef PART3_NZ_USECTX1_2 |
| 2187 | #define PART3_NZ_USECTX1_2 0 |
| 2188 | #endif |
| 2189 | #ifndef PART3_NZ_RANOTPA_2 |
| 2190 | #define PART3_NZ_RANOTPA_2 1 |
| 2191 | #endif |
| 2192 | #ifndef SUN4V |
| 2193 | #define PART3_NZ_SUN4V_2 0 |
| 2194 | #else |
| 2195 | #define PART3_NZ_SUN4V_2 1 |
| 2196 | #endif |
| 2197 | #ifndef PART3_NZ_ADDR_2 |
| 2198 | #define PART3_NZ_ADDR_2 0x1e000000 |
| 2199 | #endif |
| 2200 | #ifndef PART3_NZ_TSB_SIZE_2 |
| 2201 | #define PART3_NZ_TSB_SIZE_2 1 |
| 2202 | #endif |
| 2203 | #ifndef PART3_NZ_PAGE_SIZE_2 |
| 2204 | #define PART3_NZ_PAGE_SIZE_2 0 |
| 2205 | #endif |
| 2206 | #ifndef PART3_NZ_TSB_CONFIG_2 |
| 2207 | #define PART3_NZ_TSB_CONFIG_2 ((PART3_NZ_HWTEN_2 << 63) | (PART3_NZ_USECTX0_2 << 62) | (PART3_NZ_USECTX1_2 << 61) | (PART3_NZ_ADDR_2 & 0xffffffe000) | (PART3_NZ_RANOTPA_2 << 8) | (PART3_NZ_PAGE_SIZE_2 << 4) | (PART3_NZ_TSB_SIZE_2)) |
| 2208 | #endif |
| 2209 | define(part_3_nz_tsb_config_2, `0x'dnl' |
| 2210 | mpeval(PART3_NZ_TSB_CONFIG_2,16))dnl |
| 2211 | |
| 2212 | #ifndef PART3_Z_HWTEN_3 |
| 2213 | #define PART3_Z_HWTEN_3 1 |
| 2214 | #endif |
| 2215 | #ifndef PART3_Z_USECTX0_3 |
| 2216 | #define PART3_Z_USECTX0_3 0 |
| 2217 | #endif |
| 2218 | #ifndef PART3_Z_USECTX1_3 |
| 2219 | #define PART3_Z_USECTX1_3 0 |
| 2220 | #endif |
| 2221 | #ifndef PART3_Z_RANOTPA_3 |
| 2222 | #define PART3_Z_RANOTPA_3 1 |
| 2223 | #endif |
| 2224 | #ifndef SUN4V |
| 2225 | #define PART3_Z_SUN4V_3 0 |
| 2226 | #else |
| 2227 | #define PART3_Z_SUN4V_3 1 |
| 2228 | #endif |
| 2229 | #ifndef PART3_Z_ADDR_3 |
| 2230 | #define PART3_Z_ADDR_3 0x1f000000 |
| 2231 | #endif |
| 2232 | #ifndef PART3_Z_TSB_SIZE_3 |
| 2233 | #define PART3_Z_TSB_SIZE_3 1 |
| 2234 | #endif |
| 2235 | #ifndef PART3_Z_PAGE_SIZE_3 |
| 2236 | #define PART3_Z_PAGE_SIZE_3 0 |
| 2237 | #endif |
| 2238 | #ifndef PART3_Z_TSB_CONFIG_3 |
| 2239 | #define PART3_Z_TSB_CONFIG_3 ((PART3_Z_HWTEN_3 << 63) | (PART3_Z_USECTX0_3 << 62) | (PART3_Z_USECTX1_3 << 61) | (PART3_Z_ADDR_3 & 0xffffffe000) | (PART3_Z_RANOTPA_3 << 8) | (PART3_Z_PAGE_SIZE_3 << 4) | (PART3_Z_TSB_SIZE_3)) |
| 2240 | #endif |
| 2241 | define(part_3_z_tsb_config_3, `0x'dnl' |
| 2242 | mpeval(PART3_Z_TSB_CONFIG_3,16))dnl |
| 2243 | |
| 2244 | #ifndef PART3_NZ_HWTEN_3 |
| 2245 | #define PART3_NZ_HWTEN_3 1 |
| 2246 | #endif |
| 2247 | #ifndef PART3_NZ_USECTX0_3 |
| 2248 | #define PART3_NZ_USECTX0_3 0 |
| 2249 | #endif |
| 2250 | #ifndef PART3_NZ_USECTX1_3 |
| 2251 | #define PART3_NZ_USECTX1_3 0 |
| 2252 | #endif |
| 2253 | #ifndef PART3_NZ_RANOTPA_3 |
| 2254 | #define PART3_NZ_RANOTPA_3 1 |
| 2255 | #endif |
| 2256 | #ifndef SUN4V |
| 2257 | #define PART3_NZ_SUN4V_3 0 |
| 2258 | #else |
| 2259 | #define PART3_NZ_SUN4V_3 1 |
| 2260 | #endif |
| 2261 | #ifndef PART3_NZ_ADDR_3 |
| 2262 | #define PART3_NZ_ADDR_3 0x20000000 |
| 2263 | #endif |
| 2264 | #ifndef PART3_NZ_TSB_SIZE_3 |
| 2265 | #define PART3_NZ_TSB_SIZE_3 1 |
| 2266 | #endif |
| 2267 | #ifndef PART3_NZ_PAGE_SIZE_3 |
| 2268 | #define PART3_NZ_PAGE_SIZE_3 0 |
| 2269 | #endif |
| 2270 | #ifndef PART3_NZ_TSB_CONFIG_3 |
| 2271 | #define PART3_NZ_TSB_CONFIG_3 ((PART3_NZ_HWTEN_3 << 63) | (PART3_NZ_USECTX0_3 << 62) | (PART3_NZ_USECTX1_3 << 61) | (PART3_NZ_ADDR_3 & 0xffffffe000) | (PART3_NZ_RANOTPA_3 << 8) | (PART3_NZ_PAGE_SIZE_3 << 4) | (PART3_NZ_TSB_SIZE_3)) |
| 2272 | #endif |
| 2273 | define(part_3_nz_tsb_config_3, `0x'dnl' |
| 2274 | mpeval(PART3_NZ_TSB_CONFIG_3,16))dnl |
| 2275 | |
| 2276 | |
| 2277 | #ifndef PART3_PHY_OFF_X_0 |
| 2278 | #define PART3_PHY_OFF_X_0 1 |
| 2279 | #endif |
| 2280 | #ifndef PART3_PHY_OFF_P_0 |
| 2281 | #define PART3_PHY_OFF_P_0 0 |
| 2282 | #endif |
| 2283 | #ifndef PART3_PHY_OFF_W_0 |
| 2284 | #define PART3_PHY_OFF_W_0 0 |
| 2285 | #endif |
| 2286 | #ifndef PART3_PHY_OFF_0 |
| 2287 | #define PART3_PHY_OFF_0 ((PART_3_BASE) | (PART3_PHY_OFF_X_1 << 12) | (PART3_PHY_OFF_P_1 << 11) | (PART3_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 2288 | #endif |
| 2289 | |
| 2290 | #ifndef PART3_PHY_OFF_X_1 |
| 2291 | #define PART3_PHY_OFF_X_1 1 |
| 2292 | #endif |
| 2293 | #ifndef PART3_PHY_OFF_P_1 |
| 2294 | #define PART3_PHY_OFF_P_1 0 |
| 2295 | #endif |
| 2296 | #ifndef PART3_PHY_OFF_W_1 |
| 2297 | #define PART3_PHY_OFF_W_1 0 |
| 2298 | #endif |
| 2299 | #ifndef PART3_PHY_OFF_1 |
| 2300 | #define PART3_PHY_OFF_1 ((PART_3_BASE) | (PART3_PHY_OFF_X_1 << 12) | (PART3_PHY_OFF_P_1 << 11) | (PART3_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 2301 | #endif |
| 2302 | |
| 2303 | #ifndef PART3_PHY_OFF_X_2 |
| 2304 | #define PART3_PHY_OFF_X_2 1 |
| 2305 | #endif |
| 2306 | #ifndef PART3_PHY_OFF_P_2 |
| 2307 | #define PART3_PHY_OFF_P_2 0 |
| 2308 | #endif |
| 2309 | #ifndef PART3_PHY_OFF_W_2 |
| 2310 | #define PART3_PHY_OFF_W_2 0 |
| 2311 | #endif |
| 2312 | #ifndef PART3_PHY_OFF_2 |
| 2313 | #define PART3_PHY_OFF_2 ((PART_3_BASE) | (PART3_PHY_OFF_X_2 << 12) | (PART3_PHY_OFF_P_2 << 11) | (PART3_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 2314 | #endif |
| 2315 | |
| 2316 | #ifndef PART3_PHY_OFF_X_3 |
| 2317 | #define PART3_PHY_OFF_X_3 1 |
| 2318 | #endif |
| 2319 | #ifndef PART3_PHY_OFF_P_3 |
| 2320 | #define PART3_PHY_OFF_P_3 0 |
| 2321 | #endif |
| 2322 | #ifndef PART3_PHY_OFF_W_3 |
| 2323 | #define PART3_PHY_OFF_W_3 0 |
| 2324 | #endif |
| 2325 | #ifndef PART3_PHY_OFF_3 |
| 2326 | #define PART3_PHY_OFF_3 ((PART_3_BASE) | (PART3_PHY_OFF_X_3 << 12) | (PART3_PHY_OFF_P_3 << 11) | (PART3_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 2327 | #endif |
| 2328 | |
| 2329 | dnl 4 //////////////////////// |
| 2330 | |
| 2331 | #ifndef PART4_Z_HWTEN_0 |
| 2332 | #define PART4_Z_HWTEN_0 1 |
| 2333 | #endif |
| 2334 | #ifndef PART4_Z_USECTX0_0 |
| 2335 | #define PART4_Z_USECTX0_0 0 |
| 2336 | #endif |
| 2337 | #ifndef PART4_Z_USECTX1_0 |
| 2338 | #define PART4_Z_USECTX1_0 0 |
| 2339 | #endif |
| 2340 | #ifndef PART4_Z_RANOTPA_0 |
| 2341 | #define PART4_Z_RANOTPA_0 1 |
| 2342 | #endif |
| 2343 | #ifndef SUN4V |
| 2344 | #define PART4_Z_SUN4V_0 0 |
| 2345 | #else |
| 2346 | #define PART4_Z_SUN4V_0 1 |
| 2347 | #endif |
| 2348 | #ifndef PART4_Z_ADDR_0 |
| 2349 | #define PART4_Z_ADDR_0 0x21000000 |
| 2350 | #endif |
| 2351 | #ifndef PART4_Z_TSB_SIZE_0 |
| 2352 | #define PART4_Z_TSB_SIZE_0 1 |
| 2353 | #endif |
| 2354 | #ifndef PART4_Z_PAGE_SIZE_0 |
| 2355 | #define PART4_Z_PAGE_SIZE_0 0 |
| 2356 | #endif |
| 2357 | #ifndef PART4_Z_TSB_CONFIG_0 |
| 2358 | #define PART4_Z_TSB_CONFIG_0 ((PART4_Z_HWTEN_0 << 63) | (PART4_Z_USECTX0_0 << 62) | (PART4_Z_USECTX1_0 << 61) | (PART4_Z_ADDR_0 & 0xffffffe000) | (PART4_Z_RANOTPA_0 << 8) | (PART4_Z_PAGE_SIZE_0 << 4) | (PART4_Z_TSB_SIZE_0)) |
| 2359 | #endif |
| 2360 | define(part_4_z_tsb_config_0, `0x'dnl' |
| 2361 | mpeval(PART4_Z_TSB_CONFIG_0,16))dnl |
| 2362 | |
| 2363 | #ifndef PART4_NZ_HWTEN_0 |
| 2364 | #define PART4_NZ_HWTEN_0 1 |
| 2365 | #endif |
| 2366 | #ifndef PART4_NZ_USECTX0_0 |
| 2367 | #define PART4_NZ_USECTX0_0 0 |
| 2368 | #endif |
| 2369 | #ifndef PART4_NZ_USECTX1_0 |
| 2370 | #define PART4_NZ_USECTX1_0 0 |
| 2371 | #endif |
| 2372 | #ifndef PART4_NZ_RANOTPA_0 |
| 2373 | #define PART4_NZ_RANOTPA_0 1 |
| 2374 | #endif |
| 2375 | #ifndef SUN4V |
| 2376 | #define PART4_NZ_SUN4V_0 0 |
| 2377 | #else |
| 2378 | #define PART4_NZ_SUN4V_0 1 |
| 2379 | #endif |
| 2380 | #ifndef PART4_NZ_ADDR_0 |
| 2381 | #define PART4_NZ_ADDR_0 0x22000000 |
| 2382 | #endif |
| 2383 | #ifndef PART4_NZ_TSB_SIZE_0 |
| 2384 | #define PART4_NZ_TSB_SIZE_0 1 |
| 2385 | #endif |
| 2386 | #ifndef PART4_NZ_PAGE_SIZE_0 |
| 2387 | #define PART4_NZ_PAGE_SIZE_0 0 |
| 2388 | #endif |
| 2389 | #ifndef PART4_NZ_TSB_CONFIG_0 |
| 2390 | #define PART4_NZ_TSB_CONFIG_0 ((PART4_NZ_HWTEN_0 << 63) | (PART4_NZ_USECTX0_0 << 62) | (PART4_NZ_USECTX1_0 << 61) | (PART4_NZ_ADDR_0 & 0xffffffe000) | (PART4_NZ_RANOTPA_0 << 8) | (PART4_NZ_PAGE_SIZE_0 << 4) | (PART4_NZ_TSB_SIZE_0)) |
| 2391 | #endif |
| 2392 | define(part_4_nz_tsb_config_0, `0x'dnl' |
| 2393 | mpeval(PART4_NZ_TSB_CONFIG_0,16))dnl |
| 2394 | |
| 2395 | #ifndef PART4_Z_HWTEN_1 |
| 2396 | #define PART4_Z_HWTEN_1 1 |
| 2397 | #endif |
| 2398 | #ifndef PART4_Z_USECTX0_1 |
| 2399 | #define PART4_Z_USECTX0_1 0 |
| 2400 | #endif |
| 2401 | #ifndef PART4_Z_USECTX1_1 |
| 2402 | #define PART4_Z_USECTX1_1 0 |
| 2403 | #endif |
| 2404 | #ifndef PART4_Z_RANOTPA_1 |
| 2405 | #define PART4_Z_RANOTPA_1 1 |
| 2406 | #endif |
| 2407 | #ifndef SUN4V |
| 2408 | #define PART4_Z_SUN4V_1 0 |
| 2409 | #else |
| 2410 | #define PART4_Z_SUN4V_1 1 |
| 2411 | #endif |
| 2412 | #ifndef PART4_Z_ADDR_1 |
| 2413 | #define PART4_Z_ADDR_1 0x23000000 |
| 2414 | #endif |
| 2415 | #ifndef PART4_Z_TSB_SIZE_1 |
| 2416 | #define PART4_Z_TSB_SIZE_1 1 |
| 2417 | #endif |
| 2418 | #ifndef PART4_Z_PAGE_SIZE_1 |
| 2419 | #define PART4_Z_PAGE_SIZE_1 0 |
| 2420 | #endif |
| 2421 | #ifndef PART4_Z_TSB_CONFIG_1 |
| 2422 | #define PART4_Z_TSB_CONFIG_1 ((PART4_Z_HWTEN_1 << 63) | (PART4_Z_USECTX0_1 << 62) | (PART4_Z_USECTX1_1 << 61) | (PART4_Z_ADDR_1 & 0xffffffe000) | (PART4_Z_RANOTPA_1 << 8) | (PART4_Z_PAGE_SIZE_1 << 4) | (PART4_Z_TSB_SIZE_1)) |
| 2423 | #endif |
| 2424 | define(part_4_z_tsb_config_1, `0x'dnl' |
| 2425 | mpeval(PART4_Z_TSB_CONFIG_1,16))dnl |
| 2426 | |
| 2427 | #ifndef PART4_NZ_HWTEN_1 |
| 2428 | #define PART4_NZ_HWTEN_1 1 |
| 2429 | #endif |
| 2430 | #ifndef PART4_NZ_USECTX0_1 |
| 2431 | #define PART4_NZ_USECTX0_1 0 |
| 2432 | #endif |
| 2433 | #ifndef PART4_NZ_USECTX1_1 |
| 2434 | #define PART4_NZ_USECTX1_1 0 |
| 2435 | #endif |
| 2436 | #ifndef PART4_NZ_RANOTPA_1 |
| 2437 | #define PART4_NZ_RANOTPA_1 1 |
| 2438 | #endif |
| 2439 | #ifndef SUN4V |
| 2440 | #define PART4_NZ_SUN4V_1 0 |
| 2441 | #else |
| 2442 | #define PART4_NZ_SUN4V_1 1 |
| 2443 | #endif |
| 2444 | #ifndef PART4_NZ_ADDR_1 |
| 2445 | #define PART4_NZ_ADDR_1 0x24000000 |
| 2446 | #endif |
| 2447 | #ifndef PART4_NZ_TSB_SIZE_1 |
| 2448 | #define PART4_NZ_TSB_SIZE_1 1 |
| 2449 | #endif |
| 2450 | #ifndef PART4_NZ_PAGE_SIZE_1 |
| 2451 | #define PART4_NZ_PAGE_SIZE_1 0 |
| 2452 | #endif |
| 2453 | #ifndef PART4_NZ_TSB_CONFIG_1 |
| 2454 | #define PART4_NZ_TSB_CONFIG_1 ((PART4_NZ_HWTEN_1 << 63) | (PART4_NZ_USECTX0_1 << 62) | (PART4_NZ_USECTX1_1 << 61) | (PART4_NZ_ADDR_1 & 0xffffffe000) | (PART4_NZ_RANOTPA_1 << 8) | (PART4_NZ_PAGE_SIZE_1 << 4) | (PART4_NZ_TSB_SIZE_1)) |
| 2455 | #endif |
| 2456 | define(part_4_nz_tsb_config_1, `0x'dnl' |
| 2457 | mpeval(PART4_NZ_TSB_CONFIG_1,16))dnl |
| 2458 | |
| 2459 | #ifndef PART4_Z_HWTEN_2 |
| 2460 | #define PART4_Z_HWTEN_2 1 |
| 2461 | #endif |
| 2462 | #ifndef PART4_Z_USECTX0_2 |
| 2463 | #define PART4_Z_USECTX0_2 0 |
| 2464 | #endif |
| 2465 | #ifndef PART4_Z_USECTX1_2 |
| 2466 | #define PART4_Z_USECTX1_2 0 |
| 2467 | #endif |
| 2468 | #ifndef PART4_Z_RANOTPA_2 |
| 2469 | #define PART4_Z_RANOTPA_2 1 |
| 2470 | #endif |
| 2471 | #ifndef SUN4V |
| 2472 | #define PART4_Z_SUN4V_2 0 |
| 2473 | #else |
| 2474 | #define PART4_Z_SUN4V_2 1 |
| 2475 | #endif |
| 2476 | #ifndef PART4_Z_ADDR_2 |
| 2477 | #define PART4_Z_ADDR_2 0x25000000 |
| 2478 | #endif |
| 2479 | #ifndef PART4_Z_TSB_SIZE_2 |
| 2480 | #define PART4_Z_TSB_SIZE_2 1 |
| 2481 | #endif |
| 2482 | #ifndef PART4_Z_PAGE_SIZE_2 |
| 2483 | #define PART4_Z_PAGE_SIZE_2 0 |
| 2484 | #endif |
| 2485 | #ifndef PART4_Z_TSB_CONFIG_2 |
| 2486 | #define PART4_Z_TSB_CONFIG_2 ((PART4_Z_HWTEN_2 << 63) | (PART4_Z_USECTX0_2 << 62) | (PART4_Z_USECTX1_2 << 61) | (PART4_Z_ADDR_2 & 0xffffffe000) | (PART4_Z_RANOTPA_2 << 8) | (PART4_Z_PAGE_SIZE_2 << 4) | (PART4_Z_TSB_SIZE_2)) |
| 2487 | #endif |
| 2488 | define(part_4_z_tsb_config_2, `0x'dnl' |
| 2489 | mpeval(PART4_Z_TSB_CONFIG_2,16))dnl |
| 2490 | |
| 2491 | #ifndef PART4_NZ_HWTEN_2 |
| 2492 | #define PART4_NZ_HWTEN_2 1 |
| 2493 | #endif |
| 2494 | #ifndef PART4_NZ_USECTX0_2 |
| 2495 | #define PART4_NZ_USECTX0_2 0 |
| 2496 | #endif |
| 2497 | #ifndef PART4_NZ_USECTX1_2 |
| 2498 | #define PART4_NZ_USECTX1_2 0 |
| 2499 | #endif |
| 2500 | #ifndef PART4_NZ_RANOTPA_2 |
| 2501 | #define PART4_NZ_RANOTPA_2 1 |
| 2502 | #endif |
| 2503 | #ifndef SUN4V |
| 2504 | #define PART4_NZ_SUN4V_2 0 |
| 2505 | #else |
| 2506 | #define PART4_NZ_SUN4V_2 1 |
| 2507 | #endif |
| 2508 | #ifndef PART4_NZ_ADDR_2 |
| 2509 | #define PART4_NZ_ADDR_2 0x26000000 |
| 2510 | #endif |
| 2511 | #ifndef PART4_NZ_TSB_SIZE_2 |
| 2512 | #define PART4_NZ_TSB_SIZE_2 1 |
| 2513 | #endif |
| 2514 | #ifndef PART4_NZ_PAGE_SIZE_2 |
| 2515 | #define PART4_NZ_PAGE_SIZE_2 0 |
| 2516 | #endif |
| 2517 | #ifndef PART4_NZ_TSB_CONFIG_2 |
| 2518 | #define PART4_NZ_TSB_CONFIG_2 ((PART4_NZ_HWTEN_2 << 63) | (PART4_NZ_USECTX0_2 << 62) | (PART4_NZ_USECTX1_2 << 61) | (PART4_NZ_ADDR_2 & 0xffffffe000) | (PART4_NZ_RANOTPA_2 << 8) | (PART4_NZ_PAGE_SIZE_2 << 4) | (PART4_NZ_TSB_SIZE_2)) |
| 2519 | #endif |
| 2520 | define(part_4_nz_tsb_config_2, `0x'dnl' |
| 2521 | mpeval(PART4_NZ_TSB_CONFIG_2,16))dnl |
| 2522 | |
| 2523 | #ifndef PART4_Z_HWTEN_3 |
| 2524 | #define PART4_Z_HWTEN_3 1 |
| 2525 | #endif |
| 2526 | #ifndef PART4_Z_USECTX0_3 |
| 2527 | #define PART4_Z_USECTX0_3 0 |
| 2528 | #endif |
| 2529 | #ifndef PART4_Z_USECTX1_3 |
| 2530 | #define PART4_Z_USECTX1_3 0 |
| 2531 | #endif |
| 2532 | #ifndef PART4_Z_RANOTPA_3 |
| 2533 | #define PART4_Z_RANOTPA_3 1 |
| 2534 | #endif |
| 2535 | #ifndef SUN4V |
| 2536 | #define PART4_Z_SUN4V_3 0 |
| 2537 | #else |
| 2538 | #define PART4_Z_SUN4V_3 1 |
| 2539 | #endif |
| 2540 | #ifndef PART4_Z_ADDR_3 |
| 2541 | #define PART4_Z_ADDR_3 0x27000000 |
| 2542 | #endif |
| 2543 | #ifndef PART4_Z_TSB_SIZE_3 |
| 2544 | #define PART4_Z_TSB_SIZE_3 1 |
| 2545 | #endif |
| 2546 | #ifndef PART4_Z_PAGE_SIZE_3 |
| 2547 | #define PART4_Z_PAGE_SIZE_3 0 |
| 2548 | #endif |
| 2549 | #ifndef PART4_Z_TSB_CONFIG_3 |
| 2550 | #define PART4_Z_TSB_CONFIG_3 ((PART4_Z_HWTEN_3 << 63) | (PART4_Z_USECTX0_3 << 62) | (PART4_Z_USECTX1_3 << 61) | (PART4_Z_ADDR_3 & 0xffffffe000) | (PART4_Z_RANOTPA_3 << 8) | (PART4_Z_PAGE_SIZE_3 << 4) | (PART4_Z_TSB_SIZE_3)) |
| 2551 | #endif |
| 2552 | define(part_4_z_tsb_config_3, `0x'dnl' |
| 2553 | mpeval(PART4_Z_TSB_CONFIG_3,16))dnl |
| 2554 | |
| 2555 | #ifndef PART4_NZ_HWTEN_3 |
| 2556 | #define PART4_NZ_HWTEN_3 1 |
| 2557 | #endif |
| 2558 | #ifndef PART4_NZ_USECTX0_3 |
| 2559 | #define PART4_NZ_USECTX0_3 0 |
| 2560 | #endif |
| 2561 | #ifndef PART4_NZ_USECTX1_3 |
| 2562 | #define PART4_NZ_USECTX1_3 0 |
| 2563 | #endif |
| 2564 | #ifndef PART4_NZ_RANOTPA_3 |
| 2565 | #define PART4_NZ_RANOTPA_3 1 |
| 2566 | #endif |
| 2567 | #ifndef SUN4V |
| 2568 | #define PART4_NZ_SUN4V_3 0 |
| 2569 | #else |
| 2570 | #define PART4_NZ_SUN4V_3 1 |
| 2571 | #endif |
| 2572 | #ifndef PART4_NZ_ADDR_3 |
| 2573 | #define PART4_NZ_ADDR_3 0x28000000 |
| 2574 | #endif |
| 2575 | #ifndef PART4_NZ_TSB_SIZE_3 |
| 2576 | #define PART4_NZ_TSB_SIZE_3 1 |
| 2577 | #endif |
| 2578 | #ifndef PART4_NZ_PAGE_SIZE_3 |
| 2579 | #define PART4_NZ_PAGE_SIZE_3 0 |
| 2580 | #endif |
| 2581 | #ifndef PART4_NZ_TSB_CONFIG_3 |
| 2582 | #define PART4_NZ_TSB_CONFIG_3 ((PART4_NZ_HWTEN_3 << 63) | (PART4_NZ_USECTX0_3 << 62) | (PART4_NZ_USECTX1_3 << 61) | (PART4_NZ_ADDR_3 & 0xffffffe000) | (PART4_NZ_RANOTPA_3 << 8) | (PART4_NZ_PAGE_SIZE_3 << 4) | (PART4_NZ_TSB_SIZE_3)) |
| 2583 | #endif |
| 2584 | define(part_4_nz_tsb_config_3, `0x'dnl' |
| 2585 | mpeval(PART4_NZ_TSB_CONFIG_3,16))dnl |
| 2586 | |
| 2587 | |
| 2588 | #ifndef PART4_PHY_OFF_X_0 |
| 2589 | #define PART4_PHY_OFF_X_0 1 |
| 2590 | #endif |
| 2591 | #ifndef PART4_PHY_OFF_P_0 |
| 2592 | #define PART4_PHY_OFF_P_0 0 |
| 2593 | #endif |
| 2594 | #ifndef PART4_PHY_OFF_W_0 |
| 2595 | #define PART4_PHY_OFF_W_0 0 |
| 2596 | #endif |
| 2597 | #ifndef PART4_PHY_OFF_0 |
| 2598 | #define PART4_PHY_OFF_0 ((PART_4_BASE) | (PART4_PHY_OFF_X_1 << 12) | (PART4_PHY_OFF_P_1 << 11) | (PART4_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 2599 | #endif |
| 2600 | |
| 2601 | #ifndef PART4_PHY_OFF_X_1 |
| 2602 | #define PART4_PHY_OFF_X_1 1 |
| 2603 | #endif |
| 2604 | #ifndef PART4_PHY_OFF_P_1 |
| 2605 | #define PART4_PHY_OFF_P_1 0 |
| 2606 | #endif |
| 2607 | #ifndef PART4_PHY_OFF_W_1 |
| 2608 | #define PART4_PHY_OFF_W_1 0 |
| 2609 | #endif |
| 2610 | #ifndef PART4_PHY_OFF_1 |
| 2611 | #define PART4_PHY_OFF_1 ((PART_4_BASE) | (PART4_PHY_OFF_X_1 << 12) | (PART4_PHY_OFF_P_1 << 11) | (PART4_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 2612 | #endif |
| 2613 | |
| 2614 | #ifndef PART4_PHY_OFF_X_2 |
| 2615 | #define PART4_PHY_OFF_X_2 1 |
| 2616 | #endif |
| 2617 | #ifndef PART4_PHY_OFF_P_2 |
| 2618 | #define PART4_PHY_OFF_P_2 0 |
| 2619 | #endif |
| 2620 | #ifndef PART4_PHY_OFF_W_2 |
| 2621 | #define PART4_PHY_OFF_W_2 0 |
| 2622 | #endif |
| 2623 | #ifndef PART4_PHY_OFF_2 |
| 2624 | #define PART4_PHY_OFF_2 ((PART_4_BASE) | (PART4_PHY_OFF_X_2 << 12) | (PART4_PHY_OFF_P_2 << 11) | (PART4_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 2625 | #endif |
| 2626 | |
| 2627 | #ifndef PART4_PHY_OFF_X_3 |
| 2628 | #define PART4_PHY_OFF_X_3 1 |
| 2629 | #endif |
| 2630 | #ifndef PART4_PHY_OFF_P_3 |
| 2631 | #define PART4_PHY_OFF_P_3 0 |
| 2632 | #endif |
| 2633 | #ifndef PART4_PHY_OFF_W_3 |
| 2634 | #define PART4_PHY_OFF_W_3 0 |
| 2635 | #endif |
| 2636 | #ifndef PART4_PHY_OFF_3 |
| 2637 | #define PART4_PHY_OFF_3 ((PART_4_BASE) | (PART4_PHY_OFF_X_3 << 12) | (PART4_PHY_OFF_P_3 << 11) | (PART4_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 2638 | #endif |
| 2639 | |
| 2640 | dnl 5 //////////////////////// |
| 2641 | |
| 2642 | #ifndef PART5_Z_HWTEN_0 |
| 2643 | #define PART5_Z_HWTEN_0 1 |
| 2644 | #endif |
| 2645 | #ifndef PART5_Z_USECTX0_0 |
| 2646 | #define PART5_Z_USECTX0_0 0 |
| 2647 | #endif |
| 2648 | #ifndef PART5_Z_USECTX1_0 |
| 2649 | #define PART5_Z_USECTX1_0 0 |
| 2650 | #endif |
| 2651 | #ifndef PART5_Z_RANOTPA_0 |
| 2652 | #define PART5_Z_RANOTPA_0 1 |
| 2653 | #endif |
| 2654 | #ifndef SUN4V |
| 2655 | #define PART5_Z_SUN4V_0 0 |
| 2656 | #else |
| 2657 | #define PART5_Z_SUN4V_0 1 |
| 2658 | #endif |
| 2659 | #ifndef PART5_Z_ADDR_0 |
| 2660 | #define PART5_Z_ADDR_0 0x29000000 |
| 2661 | #endif |
| 2662 | #ifndef PART5_Z_TSB_SIZE_0 |
| 2663 | #define PART5_Z_TSB_SIZE_0 1 |
| 2664 | #endif |
| 2665 | #ifndef PART5_Z_PAGE_SIZE_0 |
| 2666 | #define PART5_Z_PAGE_SIZE_0 0 |
| 2667 | #endif |
| 2668 | #ifndef PART5_Z_TSB_CONFIG_0 |
| 2669 | #define PART5_Z_TSB_CONFIG_0 ((PART5_Z_HWTEN_0 << 63) | (PART5_Z_USECTX0_0 << 62) | (PART5_Z_USECTX1_0 << 61) | (PART5_Z_ADDR_0 & 0xffffffe000) | (PART5_Z_RANOTPA_0 << 8) | (PART5_Z_PAGE_SIZE_0 << 4) | (PART5_Z_TSB_SIZE_0)) |
| 2670 | #endif |
| 2671 | define(part_5_z_tsb_config_0, `0x'dnl' |
| 2672 | mpeval(PART5_Z_TSB_CONFIG_0,16))dnl |
| 2673 | |
| 2674 | #ifndef PART5_NZ_HWTEN_0 |
| 2675 | #define PART5_NZ_HWTEN_0 1 |
| 2676 | #endif |
| 2677 | #ifndef PART5_NZ_USECTX0_0 |
| 2678 | #define PART5_NZ_USECTX0_0 0 |
| 2679 | #endif |
| 2680 | #ifndef PART5_NZ_USECTX1_0 |
| 2681 | #define PART5_NZ_USECTX1_0 0 |
| 2682 | #endif |
| 2683 | #ifndef PART5_NZ_RANOTPA_0 |
| 2684 | #define PART5_NZ_RANOTPA_0 1 |
| 2685 | #endif |
| 2686 | #ifndef SUN4V |
| 2687 | #define PART5_NZ_SUN4V_0 0 |
| 2688 | #else |
| 2689 | #define PART5_NZ_SUN4V_0 1 |
| 2690 | #endif |
| 2691 | #ifndef PART5_NZ_ADDR_0 |
| 2692 | #define PART5_NZ_ADDR_0 0x2a000000 |
| 2693 | #endif |
| 2694 | #ifndef PART5_NZ_TSB_SIZE_0 |
| 2695 | #define PART5_NZ_TSB_SIZE_0 1 |
| 2696 | #endif |
| 2697 | #ifndef PART5_NZ_PAGE_SIZE_0 |
| 2698 | #define PART5_NZ_PAGE_SIZE_0 0 |
| 2699 | #endif |
| 2700 | #ifndef PART5_NZ_TSB_CONFIG_0 |
| 2701 | #define PART5_NZ_TSB_CONFIG_0 ((PART5_NZ_HWTEN_0 << 63) | (PART5_NZ_USECTX0_0 << 62) | (PART5_NZ_USECTX1_0 << 61) | (PART5_NZ_ADDR_0 & 0xffffffe000) | (PART5_NZ_RANOTPA_0 << 8) | (PART5_NZ_PAGE_SIZE_0 << 4) | (PART5_NZ_TSB_SIZE_0)) |
| 2702 | #endif |
| 2703 | define(part_5_nz_tsb_config_0, `0x'dnl' |
| 2704 | mpeval(PART5_NZ_TSB_CONFIG_0,16))dnl |
| 2705 | |
| 2706 | #ifndef PART5_Z_HWTEN_1 |
| 2707 | #define PART5_Z_HWTEN_1 1 |
| 2708 | #endif |
| 2709 | #ifndef PART5_Z_USECTX0_1 |
| 2710 | #define PART5_Z_USECTX0_1 0 |
| 2711 | #endif |
| 2712 | #ifndef PART5_Z_USECTX1_1 |
| 2713 | #define PART5_Z_USECTX1_1 0 |
| 2714 | #endif |
| 2715 | #ifndef PART5_Z_RANOTPA_1 |
| 2716 | #define PART5_Z_RANOTPA_1 1 |
| 2717 | #endif |
| 2718 | #ifndef SUN4V |
| 2719 | #define PART5_Z_SUN4V_1 0 |
| 2720 | #else |
| 2721 | #define PART5_Z_SUN4V_1 1 |
| 2722 | #endif |
| 2723 | #ifndef PART5_Z_ADDR_1 |
| 2724 | #define PART5_Z_ADDR_1 0x2b000000 |
| 2725 | #endif |
| 2726 | #ifndef PART5_Z_TSB_SIZE_1 |
| 2727 | #define PART5_Z_TSB_SIZE_1 1 |
| 2728 | #endif |
| 2729 | #ifndef PART5_Z_PAGE_SIZE_1 |
| 2730 | #define PART5_Z_PAGE_SIZE_1 0 |
| 2731 | #endif |
| 2732 | #ifndef PART5_Z_TSB_CONFIG_1 |
| 2733 | #define PART5_Z_TSB_CONFIG_1 ((PART5_Z_HWTEN_1 << 63) | (PART5_Z_USECTX0_1 << 62) | (PART5_Z_USECTX1_1 << 61) | (PART5_Z_ADDR_1 & 0xffffffe000) | (PART5_Z_RANOTPA_1 << 8) | (PART5_Z_PAGE_SIZE_1 << 4) | (PART5_Z_TSB_SIZE_1)) |
| 2734 | #endif |
| 2735 | define(part_5_z_tsb_config_1, `0x'dnl' |
| 2736 | mpeval(PART5_Z_TSB_CONFIG_1,16))dnl |
| 2737 | |
| 2738 | #ifndef PART5_NZ_HWTEN_1 |
| 2739 | #define PART5_NZ_HWTEN_1 1 |
| 2740 | #endif |
| 2741 | #ifndef PART5_NZ_USECTX0_1 |
| 2742 | #define PART5_NZ_USECTX0_1 0 |
| 2743 | #endif |
| 2744 | #ifndef PART5_NZ_USECTX1_1 |
| 2745 | #define PART5_NZ_USECTX1_1 0 |
| 2746 | #endif |
| 2747 | #ifndef PART5_NZ_RANOTPA_1 |
| 2748 | #define PART5_NZ_RANOTPA_1 1 |
| 2749 | #endif |
| 2750 | #ifndef SUN4V |
| 2751 | #define PART5_NZ_SUN4V_1 0 |
| 2752 | #else |
| 2753 | #define PART5_NZ_SUN4V_1 1 |
| 2754 | #endif |
| 2755 | #ifndef PART5_NZ_ADDR_1 |
| 2756 | #define PART5_NZ_ADDR_1 0x2c000000 |
| 2757 | #endif |
| 2758 | #ifndef PART5_NZ_TSB_SIZE_1 |
| 2759 | #define PART5_NZ_TSB_SIZE_1 1 |
| 2760 | #endif |
| 2761 | #ifndef PART5_NZ_PAGE_SIZE_1 |
| 2762 | #define PART5_NZ_PAGE_SIZE_1 0 |
| 2763 | #endif |
| 2764 | #ifndef PART5_NZ_TSB_CONFIG_1 |
| 2765 | #define PART5_NZ_TSB_CONFIG_1 ((PART5_NZ_HWTEN_1 << 63) | (PART5_NZ_USECTX0_1 << 62) | (PART5_NZ_USECTX1_1 << 61) | (PART5_NZ_ADDR_1 & 0xffffffe000) | (PART5_NZ_RANOTPA_1 << 8) | (PART5_NZ_PAGE_SIZE_1 << 4) | (PART5_NZ_TSB_SIZE_1)) |
| 2766 | #endif |
| 2767 | define(part_5_nz_tsb_config_1, `0x'dnl' |
| 2768 | mpeval(PART5_NZ_TSB_CONFIG_1,16))dnl |
| 2769 | |
| 2770 | #ifndef PART5_Z_HWTEN_2 |
| 2771 | #define PART5_Z_HWTEN_2 1 |
| 2772 | #endif |
| 2773 | #ifndef PART5_Z_USECTX0_2 |
| 2774 | #define PART5_Z_USECTX0_2 0 |
| 2775 | #endif |
| 2776 | #ifndef PART5_Z_USECTX1_2 |
| 2777 | #define PART5_Z_USECTX1_2 0 |
| 2778 | #endif |
| 2779 | #ifndef PART5_Z_RANOTPA_2 |
| 2780 | #define PART5_Z_RANOTPA_2 1 |
| 2781 | #endif |
| 2782 | #ifndef SUN4V |
| 2783 | #define PART5_Z_SUN4V_2 0 |
| 2784 | #else |
| 2785 | #define PART5_Z_SUN4V_2 1 |
| 2786 | #endif |
| 2787 | #ifndef PART5_Z_ADDR_2 |
| 2788 | #define PART5_Z_ADDR_2 0x2d000000 |
| 2789 | #endif |
| 2790 | #ifndef PART5_Z_TSB_SIZE_2 |
| 2791 | #define PART5_Z_TSB_SIZE_2 1 |
| 2792 | #endif |
| 2793 | #ifndef PART5_Z_PAGE_SIZE_2 |
| 2794 | #define PART5_Z_PAGE_SIZE_2 0 |
| 2795 | #endif |
| 2796 | #ifndef PART5_Z_TSB_CONFIG_2 |
| 2797 | #define PART5_Z_TSB_CONFIG_2 ((PART5_Z_HWTEN_2 << 63) | (PART5_Z_USECTX0_2 << 62) | (PART5_Z_USECTX1_2 << 61) | (PART5_Z_ADDR_2 & 0xffffffe000) | (PART5_Z_RANOTPA_2 << 8) | (PART5_Z_PAGE_SIZE_2 << 4) | (PART5_Z_TSB_SIZE_2)) |
| 2798 | #endif |
| 2799 | define(part_5_z_tsb_config_2, `0x'dnl' |
| 2800 | mpeval(PART5_Z_TSB_CONFIG_2,16))dnl |
| 2801 | |
| 2802 | #ifndef PART5_NZ_HWTEN_2 |
| 2803 | #define PART5_NZ_HWTEN_2 1 |
| 2804 | #endif |
| 2805 | #ifndef PART5_NZ_USECTX0_2 |
| 2806 | #define PART5_NZ_USECTX0_2 0 |
| 2807 | #endif |
| 2808 | #ifndef PART5_NZ_USECTX1_2 |
| 2809 | #define PART5_NZ_USECTX1_2 0 |
| 2810 | #endif |
| 2811 | #ifndef PART5_NZ_RANOTPA_2 |
| 2812 | #define PART5_NZ_RANOTPA_2 1 |
| 2813 | #endif |
| 2814 | #ifndef SUN4V |
| 2815 | #define PART5_NZ_SUN4V_2 0 |
| 2816 | #else |
| 2817 | #define PART5_NZ_SUN4V_2 1 |
| 2818 | #endif |
| 2819 | #ifndef PART5_NZ_ADDR_2 |
| 2820 | #define PART5_NZ_ADDR_2 0x2e000000 |
| 2821 | #endif |
| 2822 | #ifndef PART5_NZ_TSB_SIZE_2 |
| 2823 | #define PART5_NZ_TSB_SIZE_2 1 |
| 2824 | #endif |
| 2825 | #ifndef PART5_NZ_PAGE_SIZE_2 |
| 2826 | #define PART5_NZ_PAGE_SIZE_2 0 |
| 2827 | #endif |
| 2828 | #ifndef PART5_NZ_TSB_CONFIG_2 |
| 2829 | #define PART5_NZ_TSB_CONFIG_2 ((PART5_NZ_HWTEN_2 << 63) | (PART5_NZ_USECTX0_2 << 62) | (PART5_NZ_USECTX1_2 << 61) | (PART5_NZ_ADDR_2 & 0xffffffe000) | (PART5_NZ_RANOTPA_2 << 8) | (PART5_NZ_PAGE_SIZE_2 << 4) | (PART5_NZ_TSB_SIZE_2)) |
| 2830 | #endif |
| 2831 | define(part_5_nz_tsb_config_2, `0x'dnl' |
| 2832 | mpeval(PART5_NZ_TSB_CONFIG_2,16))dnl |
| 2833 | |
| 2834 | #ifndef PART5_Z_HWTEN_3 |
| 2835 | #define PART5_Z_HWTEN_3 1 |
| 2836 | #endif |
| 2837 | #ifndef PART5_Z_USECTX0_3 |
| 2838 | #define PART5_Z_USECTX0_3 0 |
| 2839 | #endif |
| 2840 | #ifndef PART5_Z_USECTX1_3 |
| 2841 | #define PART5_Z_USECTX1_3 0 |
| 2842 | #endif |
| 2843 | #ifndef PART5_Z_RANOTPA_3 |
| 2844 | #define PART5_Z_RANOTPA_3 1 |
| 2845 | #endif |
| 2846 | #ifndef SUN4V |
| 2847 | #define PART5_Z_SUN4V_3 0 |
| 2848 | #else |
| 2849 | #define PART5_Z_SUN4V_3 1 |
| 2850 | #endif |
| 2851 | #ifndef PART5_Z_ADDR_3 |
| 2852 | #define PART5_Z_ADDR_3 0x2f000000 |
| 2853 | #endif |
| 2854 | #ifndef PART5_Z_TSB_SIZE_3 |
| 2855 | #define PART5_Z_TSB_SIZE_3 1 |
| 2856 | #endif |
| 2857 | #ifndef PART5_Z_PAGE_SIZE_3 |
| 2858 | #define PART5_Z_PAGE_SIZE_3 0 |
| 2859 | #endif |
| 2860 | #ifndef PART5_Z_TSB_CONFIG_3 |
| 2861 | #define PART5_Z_TSB_CONFIG_3 ((PART5_Z_HWTEN_3 << 63) | (PART5_Z_USECTX0_3 << 62) | (PART5_Z_USECTX1_3 << 61) | (PART5_Z_ADDR_3 & 0xffffffe000) | (PART5_Z_RANOTPA_3 << 8) | (PART5_Z_PAGE_SIZE_3 << 4) | (PART5_Z_TSB_SIZE_3)) |
| 2862 | #endif |
| 2863 | define(part_5_z_tsb_config_3, `0x'dnl' |
| 2864 | mpeval(PART5_Z_TSB_CONFIG_3,16))dnl |
| 2865 | |
| 2866 | #ifndef PART5_NZ_HWTEN_3 |
| 2867 | #define PART5_NZ_HWTEN_3 1 |
| 2868 | #endif |
| 2869 | #ifndef PART5_NZ_USECTX0_3 |
| 2870 | #define PART5_NZ_USECTX0_3 0 |
| 2871 | #endif |
| 2872 | #ifndef PART5_NZ_USECTX1_3 |
| 2873 | #define PART5_NZ_USECTX1_3 0 |
| 2874 | #endif |
| 2875 | #ifndef PART5_NZ_RANOTPA_3 |
| 2876 | #define PART5_NZ_RANOTPA_3 1 |
| 2877 | #endif |
| 2878 | #ifndef SUN4V |
| 2879 | #define PART5_NZ_SUN4V_3 0 |
| 2880 | #else |
| 2881 | #define PART5_NZ_SUN4V_3 1 |
| 2882 | #endif |
| 2883 | #ifndef PART5_NZ_ADDR_3 |
| 2884 | #define PART5_NZ_ADDR_3 0x30000000 |
| 2885 | #endif |
| 2886 | #ifndef PART5_NZ_TSB_SIZE_3 |
| 2887 | #define PART5_NZ_TSB_SIZE_3 1 |
| 2888 | #endif |
| 2889 | #ifndef PART5_NZ_PAGE_SIZE_3 |
| 2890 | #define PART5_NZ_PAGE_SIZE_3 0 |
| 2891 | #endif |
| 2892 | #ifndef PART5_NZ_TSB_CONFIG_3 |
| 2893 | #define PART5_NZ_TSB_CONFIG_3 ((PART5_NZ_HWTEN_3 << 63) | (PART5_NZ_USECTX0_3 << 62) | (PART5_NZ_USECTX1_3 << 61) | (PART5_NZ_ADDR_3 & 0xffffffe000) | (PART5_NZ_RANOTPA_3 << 8) | (PART5_NZ_PAGE_SIZE_3 << 4) | (PART5_NZ_TSB_SIZE_3)) |
| 2894 | #endif |
| 2895 | define(part_5_nz_tsb_config_3, `0x'dnl' |
| 2896 | mpeval(PART5_NZ_TSB_CONFIG_3,16))dnl |
| 2897 | |
| 2898 | #ifndef PART5_PHY_OFF_X_0 |
| 2899 | #define PART5_PHY_OFF_X_0 1 |
| 2900 | #endif |
| 2901 | #ifndef PART5_PHY_OFF_P_0 |
| 2902 | #define PART5_PHY_OFF_P_0 0 |
| 2903 | #endif |
| 2904 | #ifndef PART5_PHY_OFF_W_0 |
| 2905 | #define PART5_PHY_OFF_W_0 0 |
| 2906 | #endif |
| 2907 | #ifndef PART5_PHY_OFF_0 |
| 2908 | #define PART5_PHY_OFF_0 ((PART_5_BASE) | (PART5_PHY_OFF_X_1 << 12) | (PART5_PHY_OFF_P_1 << 11) | (PART5_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 2909 | #endif |
| 2910 | |
| 2911 | #ifndef PART5_PHY_OFF_X_1 |
| 2912 | #define PART5_PHY_OFF_X_1 1 |
| 2913 | #endif |
| 2914 | #ifndef PART5_PHY_OFF_P_1 |
| 2915 | #define PART5_PHY_OFF_P_1 0 |
| 2916 | #endif |
| 2917 | #ifndef PART5_PHY_OFF_W_1 |
| 2918 | #define PART5_PHY_OFF_W_1 0 |
| 2919 | #endif |
| 2920 | #ifndef PART5_PHY_OFF_1 |
| 2921 | #define PART5_PHY_OFF_1 ((PART_5_BASE) | (PART5_PHY_OFF_X_1 << 12) | (PART5_PHY_OFF_P_1 << 11) | (PART5_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 2922 | #endif |
| 2923 | |
| 2924 | #ifndef PART5_PHY_OFF_X_2 |
| 2925 | #define PART5_PHY_OFF_X_2 1 |
| 2926 | #endif |
| 2927 | #ifndef PART5_PHY_OFF_P_2 |
| 2928 | #define PART5_PHY_OFF_P_2 0 |
| 2929 | #endif |
| 2930 | #ifndef PART5_PHY_OFF_W_2 |
| 2931 | #define PART5_PHY_OFF_W_2 0 |
| 2932 | #endif |
| 2933 | #ifndef PART5_PHY_OFF_2 |
| 2934 | #define PART5_PHY_OFF_2 ((PART_5_BASE) | (PART5_PHY_OFF_X_2 << 12) | (PART5_PHY_OFF_P_2 << 11) | (PART5_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 2935 | #endif |
| 2936 | |
| 2937 | #ifndef PART5_PHY_OFF_X_3 |
| 2938 | #define PART5_PHY_OFF_X_3 1 |
| 2939 | #endif |
| 2940 | #ifndef PART5_PHY_OFF_P_3 |
| 2941 | #define PART5_PHY_OFF_P_3 0 |
| 2942 | #endif |
| 2943 | #ifndef PART5_PHY_OFF_W_3 |
| 2944 | #define PART5_PHY_OFF_W_3 0 |
| 2945 | #endif |
| 2946 | #ifndef PART5_PHY_OFF_3 |
| 2947 | #define PART5_PHY_OFF_3 ((PART_5_BASE) | (PART5_PHY_OFF_X_3 << 12) | (PART5_PHY_OFF_P_3 << 11) | (PART5_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 2948 | #endif |
| 2949 | |
| 2950 | dnl 6 //////////////////////// |
| 2951 | |
| 2952 | #ifndef PART6_Z_HWTEN_0 |
| 2953 | #define PART6_Z_HWTEN_0 1 |
| 2954 | #endif |
| 2955 | #ifndef PART6_Z_USECTX0_0 |
| 2956 | #define PART6_Z_USECTX0_0 0 |
| 2957 | #endif |
| 2958 | #ifndef PART6_Z_USECTX1_0 |
| 2959 | #define PART6_Z_USECTX1_0 0 |
| 2960 | #endif |
| 2961 | #ifndef PART6_Z_RANOTPA_0 |
| 2962 | #define PART6_Z_RANOTPA_0 1 |
| 2963 | #endif |
| 2964 | #ifndef SUN4V |
| 2965 | #define PART6_Z_SUN4V_0 0 |
| 2966 | #else |
| 2967 | #define PART6_Z_SUN4V_0 1 |
| 2968 | #endif |
| 2969 | #ifndef PART6_Z_ADDR_0 |
| 2970 | #define PART6_Z_ADDR_0 0x31000000 |
| 2971 | #endif |
| 2972 | #ifndef PART6_Z_TSB_SIZE_0 |
| 2973 | #define PART6_Z_TSB_SIZE_0 1 |
| 2974 | #endif |
| 2975 | #ifndef PART6_Z_PAGE_SIZE_0 |
| 2976 | #define PART6_Z_PAGE_SIZE_0 0 |
| 2977 | #endif |
| 2978 | #ifndef PART6_Z_TSB_CONFIG_0 |
| 2979 | #define PART6_Z_TSB_CONFIG_0 ((PART6_Z_HWTEN_0 << 63) | (PART6_Z_USECTX0_0 << 62) | (PART6_Z_USECTX1_0 << 61) | (PART6_Z_ADDR_0 & 0xffffffe000) | (PART6_Z_RANOTPA_0 << 8) | (PART6_Z_PAGE_SIZE_0 << 4) | (PART6_Z_TSB_SIZE_0)) |
| 2980 | #endif |
| 2981 | define(part_6_z_tsb_config_0, `0x'dnl' |
| 2982 | mpeval(PART6_Z_TSB_CONFIG_0,16))dnl |
| 2983 | |
| 2984 | #ifndef PART6_NZ_HWTEN_0 |
| 2985 | #define PART6_NZ_HWTEN_0 1 |
| 2986 | #endif |
| 2987 | #ifndef PART6_NZ_USECTX0_0 |
| 2988 | #define PART6_NZ_USECTX0_0 0 |
| 2989 | #endif |
| 2990 | #ifndef PART6_NZ_USECTX1_0 |
| 2991 | #define PART6_NZ_USECTX1_0 0 |
| 2992 | #endif |
| 2993 | #ifndef PART6_NZ_RANOTPA_0 |
| 2994 | #define PART6_NZ_RANOTPA_0 1 |
| 2995 | #endif |
| 2996 | #ifndef SUN4V |
| 2997 | #define PART6_NZ_SUN4V_0 0 |
| 2998 | #else |
| 2999 | #define PART6_NZ_SUN4V_0 1 |
| 3000 | #endif |
| 3001 | #ifndef PART6_NZ_ADDR_0 |
| 3002 | #define PART6_NZ_ADDR_0 0x32000000 |
| 3003 | #endif |
| 3004 | #ifndef PART6_NZ_TSB_SIZE_0 |
| 3005 | #define PART6_NZ_TSB_SIZE_0 1 |
| 3006 | #endif |
| 3007 | #ifndef PART6_NZ_PAGE_SIZE_0 |
| 3008 | #define PART6_NZ_PAGE_SIZE_0 0 |
| 3009 | #endif |
| 3010 | #ifndef PART6_NZ_TSB_CONFIG_0 |
| 3011 | #define PART6_NZ_TSB_CONFIG_0 ((PART6_NZ_HWTEN_0 << 63) | (PART6_NZ_USECTX0_0 << 62) | (PART6_NZ_USECTX1_0 << 61) | (PART6_NZ_ADDR_0 & 0xffffffe000) | (PART6_NZ_RANOTPA_0 << 8) | (PART6_NZ_PAGE_SIZE_0 << 4) | (PART6_NZ_TSB_SIZE_0)) |
| 3012 | #endif |
| 3013 | define(part_6_nz_tsb_config_0, `0x'dnl' |
| 3014 | mpeval(PART6_NZ_TSB_CONFIG_0,16))dnl |
| 3015 | |
| 3016 | #ifndef PART6_Z_HWTEN_1 |
| 3017 | #define PART6_Z_HWTEN_1 1 |
| 3018 | #endif |
| 3019 | #ifndef PART6_Z_USECTX0_1 |
| 3020 | #define PART6_Z_USECTX0_1 0 |
| 3021 | #endif |
| 3022 | #ifndef PART6_Z_USECTX1_1 |
| 3023 | #define PART6_Z_USECTX1_1 0 |
| 3024 | #endif |
| 3025 | #ifndef PART6_Z_RANOTPA_1 |
| 3026 | #define PART6_Z_RANOTPA_1 1 |
| 3027 | #endif |
| 3028 | #ifndef SUN4V |
| 3029 | #define PART6_Z_SUN4V_1 0 |
| 3030 | #else |
| 3031 | #define PART6_Z_SUN4V_1 1 |
| 3032 | #endif |
| 3033 | #ifndef PART6_Z_ADDR_1 |
| 3034 | #define PART6_Z_ADDR_1 0x33000000 |
| 3035 | #endif |
| 3036 | #ifndef PART6_Z_TSB_SIZE_1 |
| 3037 | #define PART6_Z_TSB_SIZE_1 1 |
| 3038 | #endif |
| 3039 | #ifndef PART6_Z_PAGE_SIZE_1 |
| 3040 | #define PART6_Z_PAGE_SIZE_1 0 |
| 3041 | #endif |
| 3042 | #ifndef PART6_Z_TSB_CONFIG_1 |
| 3043 | #define PART6_Z_TSB_CONFIG_1 ((PART6_Z_HWTEN_1 << 63) | (PART6_Z_USECTX0_1 << 62) | (PART6_Z_USECTX1_1 << 61) | (PART6_Z_ADDR_1 & 0xffffffe000) | (PART6_Z_RANOTPA_1 << 8) | (PART6_Z_PAGE_SIZE_1 << 4) | (PART6_Z_TSB_SIZE_1)) |
| 3044 | #endif |
| 3045 | define(part_6_z_tsb_config_1, `0x'dnl' |
| 3046 | mpeval(PART6_Z_TSB_CONFIG_1,16))dnl |
| 3047 | |
| 3048 | #ifndef PART6_NZ_HWTEN_1 |
| 3049 | #define PART6_NZ_HWTEN_1 1 |
| 3050 | #endif |
| 3051 | #ifndef PART6_NZ_USECTX0_1 |
| 3052 | #define PART6_NZ_USECTX0_1 0 |
| 3053 | #endif |
| 3054 | #ifndef PART6_NZ_USECTX1_1 |
| 3055 | #define PART6_NZ_USECTX1_1 0 |
| 3056 | #endif |
| 3057 | #ifndef PART6_NZ_RANOTPA_1 |
| 3058 | #define PART6_NZ_RANOTPA_1 1 |
| 3059 | #endif |
| 3060 | #ifndef SUN4V |
| 3061 | #define PART6_NZ_SUN4V_1 0 |
| 3062 | #else |
| 3063 | #define PART6_NZ_SUN4V_1 1 |
| 3064 | #endif |
| 3065 | #ifndef PART6_NZ_ADDR_1 |
| 3066 | #define PART6_NZ_ADDR_1 0x34000000 |
| 3067 | #endif |
| 3068 | #ifndef PART6_NZ_TSB_SIZE_1 |
| 3069 | #define PART6_NZ_TSB_SIZE_1 1 |
| 3070 | #endif |
| 3071 | #ifndef PART6_NZ_PAGE_SIZE_1 |
| 3072 | #define PART6_NZ_PAGE_SIZE_1 0 |
| 3073 | #endif |
| 3074 | #ifndef PART6_NZ_TSB_CONFIG_1 |
| 3075 | #define PART6_NZ_TSB_CONFIG_1 ((PART6_NZ_HWTEN_1 << 63) | (PART6_NZ_USECTX0_1 << 62) | (PART6_NZ_USECTX1_1 << 61) | (PART6_NZ_ADDR_1 & 0xffffffe000) | (PART6_NZ_RANOTPA_1 << 8) | (PART6_NZ_PAGE_SIZE_1 << 4) | (PART6_NZ_TSB_SIZE_1)) |
| 3076 | #endif |
| 3077 | define(part_6_nz_tsb_config_1, `0x'dnl' |
| 3078 | mpeval(PART6_NZ_TSB_CONFIG_1,16))dnl |
| 3079 | |
| 3080 | #ifndef PART6_Z_HWTEN_2 |
| 3081 | #define PART6_Z_HWTEN_2 1 |
| 3082 | #endif |
| 3083 | #ifndef PART6_Z_USECTX0_2 |
| 3084 | #define PART6_Z_USECTX0_2 0 |
| 3085 | #endif |
| 3086 | #ifndef PART6_Z_USECTX1_2 |
| 3087 | #define PART6_Z_USECTX1_2 0 |
| 3088 | #endif |
| 3089 | #ifndef PART6_Z_RANOTPA_2 |
| 3090 | #define PART6_Z_RANOTPA_2 1 |
| 3091 | #endif |
| 3092 | #ifndef SUN4V |
| 3093 | #define PART6_Z_SUN4V_2 0 |
| 3094 | #else |
| 3095 | #define PART6_Z_SUN4V_2 1 |
| 3096 | #endif |
| 3097 | #ifndef PART6_Z_ADDR_2 |
| 3098 | #define PART6_Z_ADDR_2 0x35000000 |
| 3099 | #endif |
| 3100 | #ifndef PART6_Z_TSB_SIZE_2 |
| 3101 | #define PART6_Z_TSB_SIZE_2 1 |
| 3102 | #endif |
| 3103 | #ifndef PART6_Z_PAGE_SIZE_2 |
| 3104 | #define PART6_Z_PAGE_SIZE_2 0 |
| 3105 | #endif |
| 3106 | #ifndef PART6_Z_TSB_CONFIG_2 |
| 3107 | #define PART6_Z_TSB_CONFIG_2 ((PART6_Z_HWTEN_2 << 63) | (PART6_Z_USECTX0_2 << 62) | (PART6_Z_USECTX1_2 << 61) | (PART6_Z_ADDR_2 & 0xffffffe000) | (PART6_Z_RANOTPA_2 << 8) | (PART6_Z_PAGE_SIZE_2 << 4) | (PART6_Z_TSB_SIZE_2)) |
| 3108 | #endif |
| 3109 | define(part_6_z_tsb_config_2, `0x'dnl' |
| 3110 | mpeval(PART6_Z_TSB_CONFIG_2,16))dnl |
| 3111 | |
| 3112 | #ifndef PART6_NZ_HWTEN_2 |
| 3113 | #define PART6_NZ_HWTEN_2 1 |
| 3114 | #endif |
| 3115 | #ifndef PART6_NZ_USECTX0_2 |
| 3116 | #define PART6_NZ_USECTX0_2 0 |
| 3117 | #endif |
| 3118 | #ifndef PART6_NZ_USECTX1_2 |
| 3119 | #define PART6_NZ_USECTX1_2 0 |
| 3120 | #endif |
| 3121 | #ifndef PART6_NZ_RANOTPA_2 |
| 3122 | #define PART6_NZ_RANOTPA_2 1 |
| 3123 | #endif |
| 3124 | #ifndef SUN4V |
| 3125 | #define PART6_NZ_SUN4V_2 0 |
| 3126 | #else |
| 3127 | #define PART6_NZ_SUN4V_2 1 |
| 3128 | #endif |
| 3129 | #ifndef PART6_NZ_ADDR_2 |
| 3130 | #define PART6_NZ_ADDR_2 0x36000000 |
| 3131 | #endif |
| 3132 | #ifndef PART6_NZ_TSB_SIZE_2 |
| 3133 | #define PART6_NZ_TSB_SIZE_2 1 |
| 3134 | #endif |
| 3135 | #ifndef PART6_NZ_PAGE_SIZE_2 |
| 3136 | #define PART6_NZ_PAGE_SIZE_2 0 |
| 3137 | #endif |
| 3138 | #ifndef PART6_NZ_TSB_CONFIG_2 |
| 3139 | #define PART6_NZ_TSB_CONFIG_2 ((PART6_NZ_HWTEN_2 << 63) | (PART6_NZ_USECTX0_2 << 62) | (PART6_NZ_USECTX1_2 << 61) | (PART6_NZ_ADDR_2 & 0xffffffe000) | (PART6_NZ_RANOTPA_2 << 8) | (PART6_NZ_PAGE_SIZE_2 << 4) | (PART6_NZ_TSB_SIZE_2)) |
| 3140 | #endif |
| 3141 | define(part_6_nz_tsb_config_2, `0x'dnl' |
| 3142 | mpeval(PART6_NZ_TSB_CONFIG_2,16))dnl |
| 3143 | |
| 3144 | #ifndef PART6_Z_HWTEN_3 |
| 3145 | #define PART6_Z_HWTEN_3 1 |
| 3146 | #endif |
| 3147 | #ifndef PART6_Z_USECTX0_3 |
| 3148 | #define PART6_Z_USECTX0_3 0 |
| 3149 | #endif |
| 3150 | #ifndef PART6_Z_USECTX1_3 |
| 3151 | #define PART6_Z_USECTX1_3 0 |
| 3152 | #endif |
| 3153 | #ifndef PART6_Z_RANOTPA_3 |
| 3154 | #define PART6_Z_RANOTPA_3 1 |
| 3155 | #endif |
| 3156 | #ifndef SUN4V |
| 3157 | #define PART6_Z_SUN4V_3 0 |
| 3158 | #else |
| 3159 | #define PART6_Z_SUN4V_3 1 |
| 3160 | #endif |
| 3161 | #ifndef PART6_Z_ADDR_3 |
| 3162 | #define PART6_Z_ADDR_3 0x37000000 |
| 3163 | #endif |
| 3164 | #ifndef PART6_Z_TSB_SIZE_3 |
| 3165 | #define PART6_Z_TSB_SIZE_3 1 |
| 3166 | #endif |
| 3167 | #ifndef PART6_Z_PAGE_SIZE_3 |
| 3168 | #define PART6_Z_PAGE_SIZE_3 0 |
| 3169 | #endif |
| 3170 | #ifndef PART6_Z_TSB_CONFIG_3 |
| 3171 | #define PART6_Z_TSB_CONFIG_3 ((PART6_Z_HWTEN_3 << 63) | (PART6_Z_USECTX0_3 << 62) | (PART6_Z_USECTX1_3 << 61) | (PART6_Z_ADDR_3 & 0xffffffe000) | (PART6_Z_RANOTPA_3 << 8) | (PART6_Z_PAGE_SIZE_3 << 4) | (PART6_Z_TSB_SIZE_3)) |
| 3172 | #endif |
| 3173 | define(part_6_z_tsb_config_3, `0x'dnl' |
| 3174 | mpeval(PART6_Z_TSB_CONFIG_3,16))dnl |
| 3175 | |
| 3176 | #ifndef PART6_NZ_HWTEN_3 |
| 3177 | #define PART6_NZ_HWTEN_3 1 |
| 3178 | #endif |
| 3179 | #ifndef PART6_NZ_USECTX0_3 |
| 3180 | #define PART6_NZ_USECTX0_3 0 |
| 3181 | #endif |
| 3182 | #ifndef PART6_NZ_USECTX1_3 |
| 3183 | #define PART6_NZ_USECTX1_3 0 |
| 3184 | #endif |
| 3185 | #ifndef PART6_NZ_RANOTPA_3 |
| 3186 | #define PART6_NZ_RANOTPA_3 1 |
| 3187 | #endif |
| 3188 | #ifndef SUN4V |
| 3189 | #define PART6_NZ_SUN4V_3 0 |
| 3190 | #else |
| 3191 | #define PART6_NZ_SUN4V_3 1 |
| 3192 | #endif |
| 3193 | #ifndef PART6_NZ_ADDR_3 |
| 3194 | #define PART6_NZ_ADDR_3 0x38000000 |
| 3195 | #endif |
| 3196 | #ifndef PART6_NZ_TSB_SIZE_3 |
| 3197 | #define PART6_NZ_TSB_SIZE_3 1 |
| 3198 | #endif |
| 3199 | #ifndef PART6_NZ_PAGE_SIZE_3 |
| 3200 | #define PART6_NZ_PAGE_SIZE_3 0 |
| 3201 | #endif |
| 3202 | #ifndef PART6_NZ_TSB_CONFIG_3 |
| 3203 | #define PART6_NZ_TSB_CONFIG_3 ((PART6_NZ_HWTEN_3 << 63) | (PART6_NZ_USECTX0_3 << 62) | (PART6_NZ_USECTX1_3 << 61) | (PART6_NZ_ADDR_3 & 0xffffffe000) | (PART6_NZ_RANOTPA_3 << 8) | (PART6_NZ_PAGE_SIZE_3 << 4) | (PART6_NZ_TSB_SIZE_3)) |
| 3204 | #endif |
| 3205 | define(part_6_nz_tsb_config_3, `0x'dnl' |
| 3206 | mpeval(PART6_NZ_TSB_CONFIG_3,16))dnl |
| 3207 | |
| 3208 | #ifndef PART6_PHY_OFF_X_0 |
| 3209 | #define PART6_PHY_OFF_X_0 1 |
| 3210 | #endif |
| 3211 | #ifndef PART6_PHY_OFF_P_0 |
| 3212 | #define PART6_PHY_OFF_P_0 0 |
| 3213 | #endif |
| 3214 | #ifndef PART6_PHY_OFF_W_0 |
| 3215 | #define PART6_PHY_OFF_W_0 0 |
| 3216 | #endif |
| 3217 | #ifndef PART6_PHY_OFF_0 |
| 3218 | #define PART6_PHY_OFF_0 ((PART_6_BASE) | (PART6_PHY_OFF_X_1 << 12) | (PART6_PHY_OFF_P_1 << 11) | (PART6_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 3219 | #endif |
| 3220 | |
| 3221 | #ifndef PART6_PHY_OFF_X_1 |
| 3222 | #define PART6_PHY_OFF_X_1 1 |
| 3223 | #endif |
| 3224 | #ifndef PART6_PHY_OFF_P_1 |
| 3225 | #define PART6_PHY_OFF_P_1 0 |
| 3226 | #endif |
| 3227 | #ifndef PART6_PHY_OFF_W_1 |
| 3228 | #define PART6_PHY_OFF_W_1 0 |
| 3229 | #endif |
| 3230 | #ifndef PART6_PHY_OFF_1 |
| 3231 | #define PART6_PHY_OFF_1 ((PART_6_BASE) | (PART6_PHY_OFF_X_1 << 12) | (PART6_PHY_OFF_P_1 << 11) | (PART6_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 3232 | #endif |
| 3233 | |
| 3234 | #ifndef PART6_PHY_OFF_X_2 |
| 3235 | #define PART6_PHY_OFF_X_2 1 |
| 3236 | #endif |
| 3237 | #ifndef PART6_PHY_OFF_P_2 |
| 3238 | #define PART6_PHY_OFF_P_2 0 |
| 3239 | #endif |
| 3240 | #ifndef PART6_PHY_OFF_W_2 |
| 3241 | #define PART6_PHY_OFF_W_2 0 |
| 3242 | #endif |
| 3243 | #ifndef PART6_PHY_OFF_2 |
| 3244 | #define PART6_PHY_OFF_2 ((PART_6_BASE) | (PART6_PHY_OFF_X_2 << 12) | (PART6_PHY_OFF_P_2 << 11) | (PART6_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 3245 | #endif |
| 3246 | |
| 3247 | #ifndef PART6_PHY_OFF_X_3 |
| 3248 | #define PART6_PHY_OFF_X_3 1 |
| 3249 | #endif |
| 3250 | #ifndef PART6_PHY_OFF_P_3 |
| 3251 | #define PART6_PHY_OFF_P_3 0 |
| 3252 | #endif |
| 3253 | #ifndef PART6_PHY_OFF_W_3 |
| 3254 | #define PART6_PHY_OFF_W_3 0 |
| 3255 | #endif |
| 3256 | #ifndef PART6_PHY_OFF_3 |
| 3257 | #define PART6_PHY_OFF_3 ((PART_6_BASE) | (PART6_PHY_OFF_X_3 << 12) | (PART6_PHY_OFF_P_3 << 11) | (PART6_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 3258 | #endif |
| 3259 | |
| 3260 | dnl 7 //////////////////////// |
| 3261 | |
| 3262 | |
| 3263 | #ifndef PART7_Z_HWTEN_0 |
| 3264 | #define PART7_Z_HWTEN_0 1 |
| 3265 | #endif |
| 3266 | #ifndef PART7_Z_USECTX0_0 |
| 3267 | #define PART7_Z_USECTX0_0 0 |
| 3268 | #endif |
| 3269 | #ifndef PART7_Z_USECTX1_0 |
| 3270 | #define PART7_Z_USECTX1_0 0 |
| 3271 | #endif |
| 3272 | #ifndef PART7_Z_RANOTPA_0 |
| 3273 | #define PART7_Z_RANOTPA_0 1 |
| 3274 | #endif |
| 3275 | #ifndef SUN4V |
| 3276 | #define PART7_Z_SUN4V_0 0 |
| 3277 | #else |
| 3278 | #define PART7_Z_SUN4V_0 1 |
| 3279 | #endif |
| 3280 | #ifndef PART7_Z_ADDR_0 |
| 3281 | #define PART7_Z_ADDR_0 0x39000000 |
| 3282 | #endif |
| 3283 | #ifndef PART7_Z_TSB_SIZE_0 |
| 3284 | #define PART7_Z_TSB_SIZE_0 1 |
| 3285 | #endif |
| 3286 | #ifndef PART7_Z_PAGE_SIZE_0 |
| 3287 | #define PART7_Z_PAGE_SIZE_0 0 |
| 3288 | #endif |
| 3289 | #ifndef PART7_Z_TSB_CONFIG_0 |
| 3290 | #define PART7_Z_TSB_CONFIG_0 ((PART7_Z_HWTEN_0 << 63) | (PART7_Z_USECTX0_0 << 62) | (PART7_Z_USECTX1_0 << 61) | (PART7_Z_ADDR_0 & 0xffffffe000) | (PART7_Z_RANOTPA_0 << 8) | (PART7_Z_PAGE_SIZE_0 << 4) | (PART7_Z_TSB_SIZE_0)) |
| 3291 | #endif |
| 3292 | define(part_7_z_tsb_config_0, `0x'dnl' |
| 3293 | mpeval(PART7_Z_TSB_CONFIG_0,16))dnl |
| 3294 | |
| 3295 | #ifndef PART7_NZ_HWTEN_0 |
| 3296 | #define PART7_NZ_HWTEN_0 1 |
| 3297 | #endif |
| 3298 | #ifndef PART7_NZ_USECTX0_0 |
| 3299 | #define PART7_NZ_USECTX0_0 0 |
| 3300 | #endif |
| 3301 | #ifndef PART7_NZ_USECTX1_0 |
| 3302 | #define PART7_NZ_USECTX1_0 0 |
| 3303 | #endif |
| 3304 | #ifndef PART7_NZ_RANOTPA_0 |
| 3305 | #define PART7_NZ_RANOTPA_0 1 |
| 3306 | #endif |
| 3307 | #ifndef SUN4V |
| 3308 | #define PART7_NZ_SUN4V_0 0 |
| 3309 | #else |
| 3310 | #define PART7_NZ_SUN4V_0 1 |
| 3311 | #endif |
| 3312 | #ifndef PART7_NZ_ADDR_0 |
| 3313 | #define PART7_NZ_ADDR_0 0x3a000000 |
| 3314 | #endif |
| 3315 | #ifndef PART7_NZ_TSB_SIZE_0 |
| 3316 | #define PART7_NZ_TSB_SIZE_0 1 |
| 3317 | #endif |
| 3318 | #ifndef PART7_NZ_PAGE_SIZE_0 |
| 3319 | #define PART7_NZ_PAGE_SIZE_0 0 |
| 3320 | #endif |
| 3321 | #ifndef PART7_NZ_TSB_CONFIG_0 |
| 3322 | #define PART7_NZ_TSB_CONFIG_0 ((PART7_NZ_HWTEN_0 << 63) | (PART7_NZ_USECTX0_0 << 62) | (PART7_NZ_USECTX1_0 << 61) | (PART7_NZ_ADDR_0 & 0xffffffe000) | (PART7_NZ_RANOTPA_0 << 8) | (PART7_NZ_PAGE_SIZE_0 << 4) | (PART7_NZ_TSB_SIZE_0)) |
| 3323 | #endif |
| 3324 | define(part_7_nz_tsb_config_0, `0x'dnl' |
| 3325 | mpeval(PART7_NZ_TSB_CONFIG_0,16))dnl |
| 3326 | |
| 3327 | #ifndef PART7_Z_HWTEN_1 |
| 3328 | #define PART7_Z_HWTEN_1 1 |
| 3329 | #endif |
| 3330 | #ifndef PART7_Z_USECTX0_1 |
| 3331 | #define PART7_Z_USECTX0_1 0 |
| 3332 | #endif |
| 3333 | #ifndef PART7_Z_USECTX1_1 |
| 3334 | #define PART7_Z_USECTX1_1 0 |
| 3335 | #endif |
| 3336 | #ifndef PART7_Z_RANOTPA_1 |
| 3337 | #define PART7_Z_RANOTPA_1 1 |
| 3338 | #endif |
| 3339 | #ifndef SUN4V |
| 3340 | #define PART7_Z_SUN4V_1 0 |
| 3341 | #else |
| 3342 | #define PART7_Z_SUN4V_1 1 |
| 3343 | #endif |
| 3344 | #ifndef PART7_Z_ADDR_1 |
| 3345 | #define PART7_Z_ADDR_1 0x3b000000 |
| 3346 | #endif |
| 3347 | #ifndef PART7_Z_TSB_SIZE_1 |
| 3348 | #define PART7_Z_TSB_SIZE_1 1 |
| 3349 | #endif |
| 3350 | #ifndef PART7_Z_PAGE_SIZE_1 |
| 3351 | #define PART7_Z_PAGE_SIZE_1 0 |
| 3352 | #endif |
| 3353 | #ifndef PART7_Z_TSB_CONFIG_1 |
| 3354 | #define PART7_Z_TSB_CONFIG_1 ((PART7_Z_HWTEN_1 << 63) | (PART7_Z_USECTX0_1 << 62) | (PART7_Z_USECTX1_1 << 61) | (PART7_Z_ADDR_1 & 0xffffffe000) | (PART7_Z_RANOTPA_1 << 8) | (PART7_Z_PAGE_SIZE_1 << 4) | (PART7_Z_TSB_SIZE_1)) |
| 3355 | #endif |
| 3356 | define(part_7_z_tsb_config_1, `0x'dnl' |
| 3357 | mpeval(PART7_Z_TSB_CONFIG_1,16))dnl |
| 3358 | |
| 3359 | #ifndef PART7_NZ_HWTEN_1 |
| 3360 | #define PART7_NZ_HWTEN_1 1 |
| 3361 | #endif |
| 3362 | #ifndef PART7_NZ_USECTX0_1 |
| 3363 | #define PART7_NZ_USECTX0_1 0 |
| 3364 | #endif |
| 3365 | #ifndef PART7_NZ_USECTX1_1 |
| 3366 | #define PART7_NZ_USECTX1_1 0 |
| 3367 | #endif |
| 3368 | #ifndef PART7_NZ_RANOTPA_1 |
| 3369 | #define PART7_NZ_RANOTPA_1 1 |
| 3370 | #endif |
| 3371 | #ifndef SUN4V |
| 3372 | #define PART7_NZ_SUN4V_1 0 |
| 3373 | #else |
| 3374 | #define PART7_NZ_SUN4V_1 1 |
| 3375 | #endif |
| 3376 | #ifndef PART7_NZ_ADDR_1 |
| 3377 | #define PART7_NZ_ADDR_1 0x3c000000 |
| 3378 | #endif |
| 3379 | #ifndef PART7_NZ_TSB_SIZE_1 |
| 3380 | #define PART7_NZ_TSB_SIZE_1 1 |
| 3381 | #endif |
| 3382 | #ifndef PART7_NZ_PAGE_SIZE_1 |
| 3383 | #define PART7_NZ_PAGE_SIZE_1 0 |
| 3384 | #endif |
| 3385 | #ifndef PART7_NZ_TSB_CONFIG_1 |
| 3386 | #define PART7_NZ_TSB_CONFIG_1 ((PART7_NZ_HWTEN_1 << 63) | (PART7_NZ_USECTX0_1 << 62) | (PART7_NZ_USECTX1_1 << 61) | (PART7_NZ_ADDR_1 & 0xffffffe000) | (PART7_NZ_RANOTPA_1 << 8) | (PART7_NZ_PAGE_SIZE_1 << 4) | (PART7_NZ_TSB_SIZE_1)) |
| 3387 | #endif |
| 3388 | define(part_7_nz_tsb_config_1, `0x'dnl' |
| 3389 | mpeval(PART7_NZ_TSB_CONFIG_1,16))dnl |
| 3390 | |
| 3391 | #ifndef PART7_Z_HWTEN_2 |
| 3392 | #define PART7_Z_HWTEN_2 1 |
| 3393 | #endif |
| 3394 | #ifndef PART7_Z_USECTX0_2 |
| 3395 | #define PART7_Z_USECTX0_2 0 |
| 3396 | #endif |
| 3397 | #ifndef PART7_Z_USECTX1_2 |
| 3398 | #define PART7_Z_USECTX1_2 0 |
| 3399 | #endif |
| 3400 | #ifndef PART7_Z_RANOTPA_2 |
| 3401 | #define PART7_Z_RANOTPA_2 1 |
| 3402 | #endif |
| 3403 | #ifndef SUN4V |
| 3404 | #define PART7_Z_SUN4V_2 0 |
| 3405 | #else |
| 3406 | #define PART7_Z_SUN4V_2 1 |
| 3407 | #endif |
| 3408 | #ifndef PART7_Z_ADDR_2 |
| 3409 | #define PART7_Z_ADDR_2 0x3d000000 |
| 3410 | #endif |
| 3411 | #ifndef PART7_Z_TSB_SIZE_2 |
| 3412 | #define PART7_Z_TSB_SIZE_2 1 |
| 3413 | #endif |
| 3414 | #ifndef PART7_Z_PAGE_SIZE_2 |
| 3415 | #define PART7_Z_PAGE_SIZE_2 0 |
| 3416 | #endif |
| 3417 | #ifndef PART7_Z_TSB_CONFIG_2 |
| 3418 | #define PART7_Z_TSB_CONFIG_2 ((PART7_Z_HWTEN_2 << 63) | (PART7_Z_USECTX0_2 << 62) | (PART7_Z_USECTX1_2 << 61) | (PART7_Z_ADDR_2 & 0xffffffe000) | (PART7_Z_RANOTPA_2 << 8) | (PART7_Z_PAGE_SIZE_2 << 4) | (PART7_Z_TSB_SIZE_2)) |
| 3419 | #endif |
| 3420 | define(part_7_z_tsb_config_2, `0x'dnl' |
| 3421 | mpeval(PART7_Z_TSB_CONFIG_2,16))dnl |
| 3422 | |
| 3423 | #ifndef PART7_NZ_HWTEN_2 |
| 3424 | #define PART7_NZ_HWTEN_2 1 |
| 3425 | #endif |
| 3426 | #ifndef PART7_NZ_USECTX0_2 |
| 3427 | #define PART7_NZ_USECTX0_2 0 |
| 3428 | #endif |
| 3429 | #ifndef PART7_NZ_USECTX1_2 |
| 3430 | #define PART7_NZ_USECTX1_2 0 |
| 3431 | #endif |
| 3432 | #ifndef PART7_NZ_RANOTPA_2 |
| 3433 | #define PART7_NZ_RANOTPA_2 1 |
| 3434 | #endif |
| 3435 | #ifndef SUN4V |
| 3436 | #define PART7_NZ_SUN4V_2 0 |
| 3437 | #else |
| 3438 | #define PART7_NZ_SUN4V_2 1 |
| 3439 | #endif |
| 3440 | #ifndef PART7_NZ_ADDR_2 |
| 3441 | #define PART7_NZ_ADDR_2 0x3e000000 |
| 3442 | #endif |
| 3443 | #ifndef PART7_NZ_TSB_SIZE_2 |
| 3444 | #define PART7_NZ_TSB_SIZE_2 1 |
| 3445 | #endif |
| 3446 | #ifndef PART7_NZ_PAGE_SIZE_2 |
| 3447 | #define PART7_NZ_PAGE_SIZE_2 0 |
| 3448 | #endif |
| 3449 | #ifndef PART7_NZ_TSB_CONFIG_2 |
| 3450 | #define PART7_NZ_TSB_CONFIG_2 ((PART7_NZ_HWTEN_2 << 63) | (PART7_NZ_USECTX0_2 << 62) | (PART7_NZ_USECTX1_2 << 61) | (PART7_NZ_ADDR_2 & 0xffffffe000) | (PART7_NZ_RANOTPA_2 << 8) | (PART7_NZ_PAGE_SIZE_2 << 4) | (PART7_NZ_TSB_SIZE_2)) |
| 3451 | #endif |
| 3452 | define(part_7_nz_tsb_config_2, `0x'dnl' |
| 3453 | mpeval(PART7_NZ_TSB_CONFIG_2,16))dnl |
| 3454 | |
| 3455 | #ifndef PART7_Z_HWTEN_3 |
| 3456 | #define PART7_Z_HWTEN_3 1 |
| 3457 | #endif |
| 3458 | #ifndef PART7_Z_USECTX0_3 |
| 3459 | #define PART7_Z_USECTX0_3 0 |
| 3460 | #endif |
| 3461 | #ifndef PART7_Z_USECTX1_3 |
| 3462 | #define PART7_Z_USECTX1_3 0 |
| 3463 | #endif |
| 3464 | #ifndef PART7_Z_RANOTPA_3 |
| 3465 | #define PART7_Z_RANOTPA_3 1 |
| 3466 | #endif |
| 3467 | #ifndef SUN4V |
| 3468 | #define PART7_Z_SUN4V_3 0 |
| 3469 | #else |
| 3470 | #define PART7_Z_SUN4V_3 1 |
| 3471 | #endif |
| 3472 | #ifndef PART7_Z_ADDR_3 |
| 3473 | #define PART7_Z_ADDR_3 0x3f000000 |
| 3474 | #endif |
| 3475 | #ifndef PART7_Z_TSB_SIZE_3 |
| 3476 | #define PART7_Z_TSB_SIZE_3 1 |
| 3477 | #endif |
| 3478 | #ifndef PART7_Z_PAGE_SIZE_3 |
| 3479 | #define PART7_Z_PAGE_SIZE_3 0 |
| 3480 | #endif |
| 3481 | #ifndef PART7_Z_TSB_CONFIG_3 |
| 3482 | #define PART7_Z_TSB_CONFIG_3 ((PART7_Z_HWTEN_3 << 63) | (PART7_Z_USECTX0_3 << 62) | (PART7_Z_USECTX1_3 << 61) | (PART7_Z_ADDR_3 & 0xffffffe000) | (PART7_Z_RANOTPA_3 << 8) | (PART7_Z_PAGE_SIZE_3 << 4) | (PART7_Z_TSB_SIZE_3)) |
| 3483 | #endif |
| 3484 | define(part_7_z_tsb_config_3, `0x'dnl' |
| 3485 | mpeval(PART7_Z_TSB_CONFIG_3,16))dnl |
| 3486 | |
| 3487 | #ifndef PART7_NZ_HWTEN_3 |
| 3488 | #define PART7_NZ_HWTEN_3 1 |
| 3489 | #endif |
| 3490 | #ifndef PART7_NZ_USECTX0_3 |
| 3491 | #define PART7_NZ_USECTX0_3 0 |
| 3492 | #endif |
| 3493 | #ifndef PART7_NZ_USECTX1_3 |
| 3494 | #define PART7_NZ_USECTX1_3 0 |
| 3495 | #endif |
| 3496 | #ifndef PART7_NZ_RANOTPA_3 |
| 3497 | #define PART7_NZ_RANOTPA_3 1 |
| 3498 | #endif |
| 3499 | #ifndef SUN4V |
| 3500 | #define PART7_NZ_SUN4V_3 0 |
| 3501 | #else |
| 3502 | #define PART7_NZ_SUN4V_3 1 |
| 3503 | #endif |
| 3504 | #ifndef PART7_NZ_ADDR_3 |
| 3505 | #define PART7_NZ_ADDR_3 0x40000000 |
| 3506 | #endif |
| 3507 | #ifndef PART7_NZ_TSB_SIZE_3 |
| 3508 | #define PART7_NZ_TSB_SIZE_3 1 |
| 3509 | #endif |
| 3510 | #ifndef PART7_NZ_PAGE_SIZE_3 |
| 3511 | #define PART7_NZ_PAGE_SIZE_3 0 |
| 3512 | #endif |
| 3513 | #ifndef PART7_NZ_TSB_CONFIG_3 |
| 3514 | #define PART7_NZ_TSB_CONFIG_3 ((PART7_NZ_HWTEN_3 << 63) | (PART7_NZ_USECTX0_3 << 62) | (PART7_NZ_USECTX1_3 << 61) | (PART7_NZ_ADDR_3 & 0xffffffe000) | (PART7_NZ_RANOTPA_3 << 8) | (PART7_NZ_PAGE_SIZE_3 << 4) | (PART7_NZ_TSB_SIZE_3)) |
| 3515 | #endif |
| 3516 | define(part_7_nz_tsb_config_3, `0x'dnl' |
| 3517 | mpeval(PART7_NZ_TSB_CONFIG_3,16))dnl |
| 3518 | |
| 3519 | #ifndef PART7_PHY_OFF_X_0 |
| 3520 | #define PART7_PHY_OFF_X_0 1 |
| 3521 | #endif |
| 3522 | #ifndef PART7_PHY_OFF_P_0 |
| 3523 | #define PART7_PHY_OFF_P_0 0 |
| 3524 | #endif |
| 3525 | #ifndef PART7_PHY_OFF_W_0 |
| 3526 | #define PART7_PHY_OFF_W_0 0 |
| 3527 | #endif |
| 3528 | #ifndef PART7_PHY_OFF_0 |
| 3529 | #define PART7_PHY_OFF_0 ((PART_7_BASE) | (PART7_PHY_OFF_X_1 << 12) | (PART7_PHY_OFF_P_1 << 11) | (PART7_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 3530 | #endif |
| 3531 | |
| 3532 | #ifndef PART7_PHY_OFF_X_1 |
| 3533 | #define PART7_PHY_OFF_X_1 1 |
| 3534 | #endif |
| 3535 | #ifndef PART7_PHY_OFF_P_1 |
| 3536 | #define PART7_PHY_OFF_P_1 0 |
| 3537 | #endif |
| 3538 | #ifndef PART7_PHY_OFF_W_1 |
| 3539 | #define PART7_PHY_OFF_W_1 0 |
| 3540 | #endif |
| 3541 | #ifndef PART7_PHY_OFF_1 |
| 3542 | #define PART7_PHY_OFF_1 ((PART_7_BASE) | (PART7_PHY_OFF_X_1 << 12) | (PART7_PHY_OFF_P_1 << 11) | (PART7_PHY_OFF_W_1 << 10) | (0x0000000000000000)) |
| 3543 | #endif |
| 3544 | |
| 3545 | #ifndef PART7_PHY_OFF_X_2 |
| 3546 | #define PART7_PHY_OFF_X_2 1 |
| 3547 | #endif |
| 3548 | #ifndef PART7_PHY_OFF_P_2 |
| 3549 | #define PART7_PHY_OFF_P_2 0 |
| 3550 | #endif |
| 3551 | #ifndef PART7_PHY_OFF_W_2 |
| 3552 | #define PART7_PHY_OFF_W_2 0 |
| 3553 | #endif |
| 3554 | #ifndef PART7_PHY_OFF_2 |
| 3555 | #define PART7_PHY_OFF_2 ((PART_7_BASE) | (PART7_PHY_OFF_X_2 << 12) | (PART7_PHY_OFF_P_2 << 11) | (PART7_PHY_OFF_W_2 << 10) | (0x0000000000000000)) |
| 3556 | #endif |
| 3557 | |
| 3558 | #ifndef PART7_PHY_OFF_X_3 |
| 3559 | #define PART7_PHY_OFF_X_3 1 |
| 3560 | #endif |
| 3561 | #ifndef PART7_PHY_OFF_P_3 |
| 3562 | #define PART7_PHY_OFF_P_3 0 |
| 3563 | #endif |
| 3564 | #ifndef PART7_PHY_OFF_W_3 |
| 3565 | #define PART7_PHY_OFF_W_3 0 |
| 3566 | #endif |
| 3567 | #ifndef PART7_PHY_OFF_3 |
| 3568 | #define PART7_PHY_OFF_3 ((PART_7_BASE) | (PART7_PHY_OFF_X_3 << 12) | (PART7_PHY_OFF_P_3 << 11) | (PART7_PHY_OFF_W_3 << 10) | (0x0000000000000000)) |
| 3569 | #endif |
| 3570 | |
| 3571 | |
| 3572 | dnl Done //////////////////////// |
| 3573 | |
| 3574 | #if !(PART0_NZ_RANOTPA_0 & PART0_Z_RANOTPA_0 & PART0_NZ_RANOTPA_1 & PART0_Z_RANOTPA_1 & PART0_NZ_RANOTPA_2 & PART0_Z_RANOTPA_2 & PART0_NZ_RANOTPA_3 & PART0_Z_RANOTPA_3 & PART1_NZ_RANOTPA_0 & PART1_Z_RANOTPA_0 & PART1_NZ_RANOTPA_1 & PART1_Z_RANOTPA_1 & PART1_NZ_RANOTPA_2 & PART1_Z_RANOTPA_2 & PART1_NZ_RANOTPA_3 & PART1_Z_RANOTPA_3 & PART2_NZ_RANOTPA_0 & PART2_Z_RANOTPA_0 & PART2_NZ_RANOTPA_1 & PART2_Z_RANOTPA_1 & PART2_NZ_RANOTPA_2 & PART2_Z_RANOTPA_2 & PART2_NZ_RANOTPA_3 & PART2_Z_RANOTPA_3 & PART3_NZ_RANOTPA_0 & PART3_Z_RANOTPA_0 & PART3_NZ_RANOTPA_1 & PART3_Z_RANOTPA_1 & PART3_NZ_RANOTPA_2 & PART3_Z_RANOTPA_2 & PART3_NZ_RANOTPA_3 & PART3_Z_RANOTPA_3 & PART4_NZ_RANOTPA_0 & PART4_Z_RANOTPA_0 & PART4_NZ_RANOTPA_1 & PART4_Z_RANOTPA_1 & PART4_NZ_RANOTPA_2 & PART4_Z_RANOTPA_2 & PART4_NZ_RANOTPA_3 & PART4_Z_RANOTPA_3 & PART5_NZ_RANOTPA_0 & PART5_Z_RANOTPA_0 & PART5_NZ_RANOTPA_1 & PART5_Z_RANOTPA_1 & PART5_NZ_RANOTPA_2 & PART5_Z_RANOTPA_2 & PART5_NZ_RANOTPA_3 & PART5_Z_RANOTPA_3 & PART6_NZ_RANOTPA_0 & PART6_Z_RANOTPA_0 & PART6_NZ_RANOTPA_1 & PART6_Z_RANOTPA_1 & PART6_NZ_RANOTPA_2 & PART6_Z_RANOTPA_2 & PART6_NZ_RANOTPA_3 & PART6_Z_RANOTPA_3 & PART7_NZ_RANOTPA_0 & PART7_Z_RANOTPA_0 & PART7_NZ_RANOTPA_1 & PART7_Z_RANOTPA_1 & PART7_NZ_RANOTPA_2 & PART7_Z_RANOTPA_2 & PART7_NZ_RANOTPA_3 & PART7_Z_RANOTPA_3) |
| 3575 | #define SOME_TSB_PANOTRA |
| 3576 | #endif |
| 3577 | |
| 3578 | |
| 3579 | #ifndef NO_DECLARE_TSB |
| 3580 | #ifdef GOLDFINGER |
| 3581 | |
| 3582 | #ifdef PART_0_USED |
| 3583 | MIDAS_TSB_LINK part_0_tsb_link PART_0_LINK_AREA_BASE_ADDR |
| 3584 | #ifndef USE_N1_TSB_NAMES |
| 3585 | MIDAS_TSB part_0_ctx_zero_tsb_config_0 part_0_z_tsb_config_0 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3586 | MIDAS_TSB part_0_ctx_nonzero_tsb_config_0 part_0_nz_tsb_config_0 link=part_0_tsb_link ttefmt=sun4v |
| 3587 | MIDAS_TSB part_0_ctx_zero_tsb_config_1 part_0_z_tsb_config_1 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3588 | MIDAS_TSB part_0_ctx_nonzero_tsb_config_1 part_0_nz_tsb_config_1 link=part_0_tsb_link ttefmt=sun4v |
| 3589 | MIDAS_TSB part_0_ctx_zero_tsb_config_2 part_0_z_tsb_config_2 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3590 | MIDAS_TSB part_0_ctx_nonzero_tsb_config_2 part_0_nz_tsb_config_2 link=part_0_tsb_link ttefmt=sun4v |
| 3591 | MIDAS_TSB part_0_ctx_zero_tsb_config_3 part_0_z_tsb_config_3 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3592 | MIDAS_TSB part_0_ctx_nonzero_tsb_config_3 part_0_nz_tsb_config_3 link=part_0_tsb_link ttefmt=sun4v |
| 3593 | #else |
| 3594 | MIDAS_TSB part_0_i_ctx_zero_ps0_tsb part_0_z_tsb_config_0 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3595 | MIDAS_TSB part_0_i_ctx_nonzero_ps0_tsb part_0_nz_tsb_config_0 link=part_0_tsb_link ttefmt=sun4v |
| 3596 | MIDAS_TSB part_0_d_ctx_zero_ps0_tsb part_0_z_tsb_config_1 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3597 | MIDAS_TSB part_0_d_ctx_nonzero_ps0_tsb part_0_nz_tsb_config_1 link=part_0_tsb_link ttefmt=sun4v |
| 3598 | MIDAS_TSB part_0_i_ctx_zero_ps1_tsb part_0_z_tsb_config_2 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3599 | MIDAS_TSB part_0_i_ctx_nonzero_ps1_tsb part_0_nz_tsb_config_2 link=part_0_tsb_link ttefmt=sun4v |
| 3600 | MIDAS_TSB part_0_d_ctx_zero_ps1_tsb part_0_z_tsb_config_3 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v |
| 3601 | MIDAS_TSB part_0_d_ctx_nonzero_ps1_tsb part_0_nz_tsb_config_3 link=part_0_tsb_link ttefmt=sun4v |
| 3602 | #endif |
| 3603 | #endif |
| 3604 | |
| 3605 | #ifdef PART_1_USED |
| 3606 | MIDAS_TSB_LINK part_1_tsb_link PART_1_LINK_AREA_BASE_ADDR |
| 3607 | #ifndef USE_N1_TSB_NAMES |
| 3608 | MIDAS_TSB part_1_ctx_zero_tsb_config_0 part_1_z_tsb_config_0 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3609 | MIDAS_TSB part_1_ctx_nonzero_tsb_config_0 part_1_nz_tsb_config_0 link=part_1_tsb_link ttefmt=sun4v |
| 3610 | MIDAS_TSB part_1_ctx_zero_tsb_config_1 part_1_z_tsb_config_1 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3611 | MIDAS_TSB part_1_ctx_nonzero_tsb_config_1 part_1_nz_tsb_config_1 link=part_1_tsb_link ttefmt=sun4v |
| 3612 | MIDAS_TSB part_1_ctx_zero_tsb_config_2 part_1_z_tsb_config_2 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3613 | MIDAS_TSB part_1_ctx_nonzero_tsb_config_2 part_1_nz_tsb_config_2 link=part_1_tsb_link ttefmt=sun4v |
| 3614 | MIDAS_TSB part_1_ctx_zero_tsb_config_3 part_1_z_tsb_config_3 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3615 | MIDAS_TSB part_1_ctx_nonzero_tsb_config_3 part_1_nz_tsb_config_3 link=part_1_tsb_link ttefmt=sun4v |
| 3616 | #else |
| 3617 | MIDAS_TSB part_1_i_ctx_zero_ps0_tsb part_1_z_tsb_config_0 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3618 | MIDAS_TSB part_1_i_ctx_nonzero_ps0_tsb part_1_nz_tsb_config_0 link=part_1_tsb_link ttefmt=sun4v |
| 3619 | MIDAS_TSB part_1_d_ctx_zero_ps0_tsb part_1_z_tsb_config_1 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3620 | MIDAS_TSB part_1_d_ctx_nonzero_ps0_tsb part_1_nz_tsb_config_1 link=part_1_tsb_link ttefmt=sun4v |
| 3621 | MIDAS_TSB part_1_i_ctx_zero_ps1_tsb part_1_z_tsb_config_2 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3622 | MIDAS_TSB part_1_i_ctx_nonzero_ps1_tsb part_1_nz_tsb_config_2 link=part_1_tsb_link ttefmt=sun4v |
| 3623 | MIDAS_TSB part_1_d_ctx_zero_ps1_tsb part_1_z_tsb_config_3 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v |
| 3624 | MIDAS_TSB part_1_d_ctx_nonzero_ps1_tsb part_1_nz_tsb_config_3 link=part_1_tsb_link ttefmt=sun4v |
| 3625 | #endif |
| 3626 | |
| 3627 | #endif |
| 3628 | |
| 3629 | #ifdef PART_2_USED |
| 3630 | MIDAS_TSB_LINK part_2_tsb_link PART_2_LINK_AREA_BASE_ADDR |
| 3631 | #ifndef USE_N1_TSB_NAMES |
| 3632 | MIDAS_TSB part_2_ctx_zero_tsb_config_0 part_2_z_tsb_config_0 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3633 | MIDAS_TSB part_2_ctx_nonzero_tsb_config_0 part_2_nz_tsb_config_0 link=part_2_tsb_link ttefmt=sun4v |
| 3634 | MIDAS_TSB part_2_ctx_zero_tsb_config_1 part_2_z_tsb_config_1 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3635 | MIDAS_TSB part_2_ctx_nonzero_tsb_config_1 part_2_nz_tsb_config_1 link=part_2_tsb_link ttefmt=sun4v |
| 3636 | MIDAS_TSB part_2_ctx_zero_tsb_config_2 part_2_z_tsb_config_2 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3637 | MIDAS_TSB part_2_ctx_nonzero_tsb_config_2 part_2_nz_tsb_config_2 link=part_2_tsb_link ttefmt=sun4v |
| 3638 | MIDAS_TSB part_2_ctx_zero_tsb_config_3 part_2_z_tsb_config_3 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3639 | MIDAS_TSB part_2_ctx_nonzero_tsb_config_3 part_2_nz_tsb_config_3 link=part_2_tsb_link ttefmt=sun4v |
| 3640 | #else |
| 3641 | MIDAS_TSB part_2_i_ctx_zero_ps0_tsb part_2_z_tsb_config_0 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3642 | MIDAS_TSB part_2_i_ctx_nonzero_ps0_tsb part_2_nz_tsb_config_0 link=part_2_tsb_link ttefmt=sun4v |
| 3643 | MIDAS_TSB part_2_d_ctx_zero_ps0_tsb part_2_z_tsb_config_1 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3644 | MIDAS_TSB part_2_d_ctx_nonzero_ps0_tsb part_2_nz_tsb_config_1 link=part_2_tsb_link ttefmt=sun4v |
| 3645 | MIDAS_TSB part_2_i_ctx_zero_ps1_tsb part_2_z_tsb_config_2 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3646 | MIDAS_TSB part_2_i_ctx_nonzero_ps1_tsb part_2_nz_tsb_config_2 link=part_2_tsb_link ttefmt=sun4v |
| 3647 | MIDAS_TSB part_2_d_ctx_zero_ps1_tsb part_2_z_tsb_config_3 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v |
| 3648 | MIDAS_TSB part_2_d_ctx_nonzero_ps1_tsb part_2_nz_tsb_config_3 link=part_2_tsb_link ttefmt=sun4v |
| 3649 | #endif |
| 3650 | #endif |
| 3651 | |
| 3652 | #ifdef PART_3_USED |
| 3653 | MIDAS_TSB_LINK part_3_tsb_link PART_3_LINK_AREA_BASE_ADDR |
| 3654 | #ifndef USE_N1_TSB_NAMES |
| 3655 | MIDAS_TSB part_3_ctx_zero_tsb_config_0 part_3_z_tsb_config_0 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3656 | MIDAS_TSB part_3_ctx_nonzero_tsb_config_0 part_3_nz_tsb_config_0 link=part_3_tsb_link ttefmt=sun4v |
| 3657 | MIDAS_TSB part_3_ctx_zero_tsb_config_1 part_3_z_tsb_config_1 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3658 | MIDAS_TSB part_3_ctx_nonzero_tsb_config_1 part_3_nz_tsb_config_1 link=part_3_tsb_link ttefmt=sun4v |
| 3659 | MIDAS_TSB part_3_ctx_zero_tsb_config_2 part_3_z_tsb_config_2 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3660 | MIDAS_TSB part_3_ctx_nonzero_tsb_config_2 part_3_nz_tsb_config_2 link=part_3_tsb_link ttefmt=sun4v |
| 3661 | MIDAS_TSB part_3_ctx_zero_tsb_config_3 part_3_z_tsb_config_3 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3662 | MIDAS_TSB part_3_ctx_nonzero_tsb_config_3 part_3_nz_tsb_config_3 link=part_3_tsb_link ttefmt=sun4v |
| 3663 | #else |
| 3664 | MIDAS_TSB part_3_i_ctx_zero_ps0_tsb part_3_z_tsb_config_0 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3665 | MIDAS_TSB part_3_i_ctx_nonzero_ps0_tsb part_3_nz_tsb_config_0 link=part_3_tsb_link ttefmt=sun4v |
| 3666 | MIDAS_TSB part_3_d_ctx_zero_ps0_tsb part_3_z_tsb_config_1 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3667 | MIDAS_TSB part_3_d_ctx_nonzero_ps0_tsb part_3_nz_tsb_config_1 link=part_3_tsb_link ttefmt=sun4v |
| 3668 | MIDAS_TSB part_3_i_ctx_zero_ps1_tsb part_3_z_tsb_config_2 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3669 | MIDAS_TSB part_3_i_ctx_nonzero_ps1_tsb part_3_nz_tsb_config_2 link=part_3_tsb_link ttefmt=sun4v |
| 3670 | MIDAS_TSB part_3_d_ctx_zero_ps1_tsb part_3_z_tsb_config_3 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v |
| 3671 | MIDAS_TSB part_3_d_ctx_nonzero_ps1_tsb part_3_nz_tsb_config_3 link=part_3_tsb_link ttefmt=sun4v |
| 3672 | #endif |
| 3673 | #endif |
| 3674 | |
| 3675 | #ifdef PART_4_USED |
| 3676 | MIDAS_TSB_LINK part_4_tsb_link PART_4_LINK_AREA_BASE_ADDR |
| 3677 | #ifndef USE_N1_TSB_NAMES |
| 3678 | MIDAS_TSB part_4_ctx_zero_tsb_config_0 part_4_z_tsb_config_0 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3679 | MIDAS_TSB part_4_ctx_nonzero_tsb_config_0 part_4_nz_tsb_config_0 link=part_4_tsb_link ttefmt=sun4v |
| 3680 | MIDAS_TSB part_4_ctx_zero_tsb_config_1 part_4_z_tsb_config_1 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3681 | MIDAS_TSB part_4_ctx_nonzero_tsb_config_1 part_4_nz_tsb_config_1 link=part_4_tsb_link ttefmt=sun4v |
| 3682 | MIDAS_TSB part_4_ctx_zero_tsb_config_2 part_4_z_tsb_config_2 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3683 | MIDAS_TSB part_4_ctx_nonzero_tsb_config_2 part_4_nz_tsb_config_2 link=part_4_tsb_link ttefmt=sun4v |
| 3684 | MIDAS_TSB part_4_ctx_zero_tsb_config_3 part_4_z_tsb_config_3 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3685 | MIDAS_TSB part_4_ctx_nonzero_tsb_config_3 part_4_nz_tsb_config_3 link=part_4_tsb_link ttefmt=sun4v |
| 3686 | #else |
| 3687 | MIDAS_TSB part_4_i_ctx_zero_ps0_tsb part_4_z_tsb_config_0 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3688 | MIDAS_TSB part_4_i_ctx_nonzero_ps0_tsb part_4_nz_tsb_config_0 link=part_4_tsb_link ttefmt=sun4v |
| 3689 | MIDAS_TSB part_4_d_ctx_zero_ps0_tsb part_4_z_tsb_config_1 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3690 | MIDAS_TSB part_4_d_ctx_nonzero_ps0_tsb part_4_nz_tsb_config_1 link=part_4_tsb_link ttefmt=sun4v |
| 3691 | MIDAS_TSB part_4_i_ctx_zero_ps1_tsb part_4_z_tsb_config_2 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3692 | MIDAS_TSB part_4_i_ctx_nonzero_ps1_tsb part_4_nz_tsb_config_2 link=part_4_tsb_link ttefmt=sun4v |
| 3693 | MIDAS_TSB part_4_d_ctx_zero_ps1_tsb part_4_z_tsb_config_3 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v |
| 3694 | MIDAS_TSB part_4_d_ctx_nonzero_ps1_tsb part_4_nz_tsb_config_3 link=part_4_tsb_link ttefmt=sun4v |
| 3695 | #endif |
| 3696 | #endif |
| 3697 | |
| 3698 | #ifdef PART_5_USED |
| 3699 | MIDAS_TSB_LINK part_5_tsb_link PART_5_LINK_AREA_BASE_ADDR |
| 3700 | #ifndef USE_N1_TSB_NAMES |
| 3701 | MIDAS_TSB part_5_ctx_zero_tsb_config_0 part_5_z_tsb_config_0 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3702 | MIDAS_TSB part_5_ctx_nonzero_tsb_config_0 part_5_nz_tsb_config_0 link=part_5_tsb_link ttefmt=sun4v |
| 3703 | MIDAS_TSB part_5_ctx_zero_tsb_config_1 part_5_z_tsb_config_1 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3704 | MIDAS_TSB part_5_ctx_nonzero_tsb_config_1 part_5_nz_tsb_config_1 link=part_5_tsb_link ttefmt=sun4v |
| 3705 | MIDAS_TSB part_5_ctx_zero_tsb_config_2 part_5_z_tsb_config_2 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3706 | MIDAS_TSB part_5_ctx_nonzero_tsb_config_2 part_5_nz_tsb_config_2 link=part_5_tsb_link ttefmt=sun4v |
| 3707 | MIDAS_TSB part_5_ctx_zero_tsb_config_3 part_5_z_tsb_config_3 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3708 | MIDAS_TSB part_5_ctx_nonzero_tsb_config_3 part_5_nz_tsb_config_3 link=part_5_tsb_link ttefmt=sun4v |
| 3709 | #else |
| 3710 | MIDAS_TSB part_5_i_ctx_zero_ps0_tsb part_5_z_tsb_config_0 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3711 | MIDAS_TSB part_5_i_ctx_nonzero_ps0_tsb part_5_nz_tsb_config_0 link=part_5_tsb_link ttefmt=sun4v |
| 3712 | MIDAS_TSB part_5_d_ctx_zero_ps0_tsb part_5_z_tsb_config_1 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3713 | MIDAS_TSB part_5_d_ctx_nonzero_ps0_tsb part_5_nz_tsb_config_1 link=part_5_tsb_link ttefmt=sun4v |
| 3714 | MIDAS_TSB part_5_i_ctx_zero_ps1_tsb part_5_z_tsb_config_2 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3715 | MIDAS_TSB part_5_i_ctx_nonzero_ps1_tsb part_5_nz_tsb_config_2 link=part_5_tsb_link ttefmt=sun4v |
| 3716 | MIDAS_TSB part_5_d_ctx_zero_ps1_tsb part_5_z_tsb_config_3 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v |
| 3717 | MIDAS_TSB part_5_d_ctx_nonzero_ps1_tsb part_5_nz_tsb_config_3 link=part_5_tsb_link ttefmt=sun4v |
| 3718 | #endif |
| 3719 | #endif |
| 3720 | |
| 3721 | #ifdef PART_6_USED |
| 3722 | MIDAS_TSB_LINK part_6_tsb_link PART_6_LINK_AREA_BASE_ADDR |
| 3723 | #ifndef USE_N1_TSB_NAMES |
| 3724 | MIDAS_TSB part_6_ctx_zero_tsb_config_0 part_6_z_tsb_config_0 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3725 | MIDAS_TSB part_6_ctx_nonzero_tsb_config_0 part_6_nz_tsb_config_0 link=part_6_tsb_link ttefmt=sun4v |
| 3726 | MIDAS_TSB part_6_ctx_zero_tsb_config_1 part_6_z_tsb_config_1 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3727 | MIDAS_TSB part_6_ctx_nonzero_tsb_config_1 part_6_nz_tsb_config_1 link=part_6_tsb_link ttefmt=sun4v |
| 3728 | MIDAS_TSB part_6_ctx_zero_tsb_config_2 part_6_z_tsb_config_2 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3729 | MIDAS_TSB part_6_ctx_nonzero_tsb_config_2 part_6_nz_tsb_config_2 link=part_6_tsb_link ttefmt=sun4v |
| 3730 | MIDAS_TSB part_6_ctx_zero_tsb_config_3 part_6_z_tsb_config_3 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3731 | MIDAS_TSB part_6_ctx_nonzero_tsb_config_3 part_6_nz_tsb_config_3 link=part_6_tsb_link ttefmt=sun4v |
| 3732 | #else |
| 3733 | MIDAS_TSB part_6_i_ctx_zero_ps0_tsb part_6_z_tsb_config_0 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3734 | MIDAS_TSB part_6_i_ctx_nonzero_ps0_tsb part_6_nz_tsb_config_0 link=part_6_tsb_link ttefmt=sun4v |
| 3735 | MIDAS_TSB part_6_d_ctx_zero_ps0_tsb part_6_z_tsb_config_1 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3736 | MIDAS_TSB part_6_d_ctx_nonzero_ps0_tsb part_6_nz_tsb_config_1 link=part_6_tsb_link ttefmt=sun4v |
| 3737 | MIDAS_TSB part_6_i_ctx_zero_ps1_tsb part_6_z_tsb_config_2 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3738 | MIDAS_TSB part_6_i_ctx_nonzero_ps1_tsb part_6_nz_tsb_config_2 link=part_6_tsb_link ttefmt=sun4v |
| 3739 | MIDAS_TSB part_6_d_ctx_zero_ps1_tsb part_6_z_tsb_config_3 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v |
| 3740 | MIDAS_TSB part_6_d_ctx_nonzero_ps1_tsb part_6_nz_tsb_config_3 link=part_6_tsb_link ttefmt=sun4v |
| 3741 | #endif |
| 3742 | #endif |
| 3743 | |
| 3744 | #ifdef PART_7_USED |
| 3745 | MIDAS_TSB_LINK part_7_tsb_link PART_7_LINK_AREA_BASE_ADDR |
| 3746 | #ifndef USE_N1_TSB_NAMES |
| 3747 | MIDAS_TSB part_7_ctx_zero_tsb_config_0 part_7_z_tsb_config_0 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3748 | MIDAS_TSB part_7_ctx_nonzero_tsb_config_0 part_7_nz_tsb_config_0 link=part_7_tsb_link ttefmt=sun4v |
| 3749 | MIDAS_TSB part_7_ctx_zero_tsb_config_1 part_7_z_tsb_config_1 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3750 | MIDAS_TSB part_7_ctx_nonzero_tsb_config_1 part_7_nz_tsb_config_1 link=part_7_tsb_link ttefmt=sun4v |
| 3751 | MIDAS_TSB part_7_ctx_zero_tsb_config_2 part_7_z_tsb_config_2 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3752 | MIDAS_TSB part_7_ctx_nonzero_tsb_config_2 part_7_nz_tsb_config_2 link=part_7_tsb_link ttefmt=sun4v |
| 3753 | MIDAS_TSB part_7_ctx_zero_tsb_config_3 part_7_z_tsb_config_3 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3754 | MIDAS_TSB part_7_ctx_nonzero_tsb_config_3 part_7_nz_tsb_config_3 link=part_7_tsb_link ttefmt=sun4v |
| 3755 | #else |
| 3756 | MIDAS_TSB part_7_i_ctx_zero_ps0_tsb part_7_z_tsb_config_0 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3757 | MIDAS_TSB part_7_i_ctx_nonzero_ps0_tsb part_7_nz_tsb_config_0 link=part_7_tsb_link ttefmt=sun4v |
| 3758 | MIDAS_TSB part_7_d_ctx_zero_ps0_tsb part_7_z_tsb_config_1 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3759 | MIDAS_TSB part_7_d_ctx_nonzero_ps0_tsb part_7_nz_tsb_config_1 link=part_7_tsb_link ttefmt=sun4v |
| 3760 | MIDAS_TSB part_7_i_ctx_zero_ps1_tsb part_7_z_tsb_config_2 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3761 | MIDAS_TSB part_7_i_ctx_nonzero_ps1_tsb part_7_nz_tsb_config_2 link=part_7_tsb_link ttefmt=sun4v |
| 3762 | MIDAS_TSB part_7_d_ctx_zero_ps1_tsb part_7_z_tsb_config_3 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v |
| 3763 | MIDAS_TSB part_7_d_ctx_nonzero_ps1_tsb part_7_nz_tsb_config_3 link=part_7_tsb_link ttefmt=sun4v |
| 3764 | #endif |
| 3765 | #endif |
| 3766 | |
| 3767 | #else |
| 3768 | |
| 3769 | part_0_ctx_zero_tsb_config_0 part_0_z_tsb_config_0 |
| 3770 | part_0_ctx_nonzero_tsb_config_0 part_0_nz_tsb_config_0 |
| 3771 | part_0_ctx_zero_tsb_config_1 part_0_z_tsb_config_1 |
| 3772 | part_0_ctx_nonzero_tsb_config_1 part_0_nz_tsb_config_1 |
| 3773 | part_0_ctx_zero_tsb_config_2 part_0_z_tsb_config_2 |
| 3774 | part_0_ctx_nonzero_tsb_config_2 part_0_nz_tsb_config_2 |
| 3775 | part_0_ctx_zero_tsb_config_3 part_0_z_tsb_config_3 |
| 3776 | part_0_ctx_nonzero_tsb_config_3 part_0_nz_tsb_config_3 |
| 3777 | |
| 3778 | part_1_ctx_zero_tsb_config_0 part_1_z_tsb_config_0 |
| 3779 | part_1_ctx_nonzero_tsb_config_0 part_1_nz_tsb_config_0 |
| 3780 | part_1_ctx_zero_tsb_config_1 part_1_z_tsb_config_1 |
| 3781 | part_1_ctx_nonzero_tsb_config_1 part_1_nz_tsb_config_1 |
| 3782 | part_1_ctx_zero_tsb_config_2 part_1_z_tsb_config_2 |
| 3783 | part_1_ctx_nonzero_tsb_config_2 part_1_nz_tsb_config_2 |
| 3784 | part_1_ctx_zero_tsb_config_3 part_1_z_tsb_config_3 |
| 3785 | part_1_ctx_nonzero_tsb_config_3 part_1_nz_tsb_config_3 |
| 3786 | |
| 3787 | part_2_ctx_zero_tsb_config_0 part_2_z_tsb_config_0 |
| 3788 | part_2_ctx_nonzero_tsb_config_0 part_2_nz_tsb_config_0 |
| 3789 | part_2_ctx_zero_tsb_config_1 part_2_z_tsb_config_1 |
| 3790 | part_2_ctx_nonzero_tsb_config_1 part_2_nz_tsb_config_1 |
| 3791 | part_2_ctx_zero_tsb_config_2 part_2_z_tsb_config_2 |
| 3792 | part_2_ctx_nonzero_tsb_config_2 part_2_nz_tsb_config_2 |
| 3793 | part_2_ctx_zero_tsb_config_3 part_2_z_tsb_config_3 |
| 3794 | part_2_ctx_nonzero_tsb_config_3 part_2_nz_tsb_config_3 |
| 3795 | |
| 3796 | part_3_ctx_zero_tsb_config_0 part_3_z_tsb_config_0 |
| 3797 | part_3_ctx_nonzero_tsb_config_0 part_3_nz_tsb_config_0 |
| 3798 | part_3_ctx_zero_tsb_config_1 part_3_z_tsb_config_1 |
| 3799 | part_3_ctx_nonzero_tsb_config_1 part_3_nz_tsb_config_1 |
| 3800 | part_3_ctx_zero_tsb_config_2 part_3_z_tsb_config_2 |
| 3801 | part_3_ctx_nonzero_tsb_config_2 part_3_nz_tsb_config_2 |
| 3802 | part_3_ctx_zero_tsb_config_3 part_3_z_tsb_config_3 |
| 3803 | part_3_ctx_nonzero_tsb_config_3 part_3_nz_tsb_config_3 |
| 3804 | |
| 3805 | part_4_ctx_zero_tsb_config_0 part_4_z_tsb_config_0 |
| 3806 | part_4_ctx_nonzero_tsb_config_0 part_4_nz_tsb_config_0 |
| 3807 | part_4_ctx_zero_tsb_config_1 part_4_z_tsb_config_1 |
| 3808 | part_4_ctx_nonzero_tsb_config_1 part_4_nz_tsb_config_1 |
| 3809 | part_4_ctx_zero_tsb_config_2 part_4_z_tsb_config_2 |
| 3810 | part_4_ctx_nonzero_tsb_config_2 part_4_nz_tsb_config_2 |
| 3811 | part_4_ctx_zero_tsb_config_3 part_4_z_tsb_config_3 |
| 3812 | part_4_ctx_nonzero_tsb_config_3 part_4_nz_tsb_config_3 |
| 3813 | |
| 3814 | part_5_ctx_zero_tsb_config_0 part_5_z_tsb_config_0 |
| 3815 | part_5_ctx_nonzero_tsb_config_0 part_5_nz_tsb_config_0 |
| 3816 | part_5_ctx_zero_tsb_config_1 part_5_z_tsb_config_1 |
| 3817 | part_5_ctx_nonzero_tsb_config_1 part_5_nz_tsb_config_1 |
| 3818 | part_5_ctx_zero_tsb_config_2 part_5_z_tsb_config_2 |
| 3819 | part_5_ctx_nonzero_tsb_config_2 part_5_nz_tsb_config_2 |
| 3820 | part_5_ctx_zero_tsb_config_3 part_5_z_tsb_config_3 |
| 3821 | part_5_ctx_nonzero_tsb_config_3 part_5_nz_tsb_config_3 |
| 3822 | |
| 3823 | |
| 3824 | part_6_ctx_zero_tsb_config_0 part_6_z_tsb_config_0 |
| 3825 | part_6_ctx_nonzero_tsb_config_0 part_6_nz_tsb_config_0 |
| 3826 | part_6_ctx_zero_tsb_config_1 part_6_z_tsb_config_1 |
| 3827 | part_6_ctx_nonzero_tsb_config_1 part_6_nz_tsb_config_1 |
| 3828 | part_6_ctx_zero_tsb_config_2 part_6_z_tsb_config_2 |
| 3829 | part_6_ctx_nonzero_tsb_config_2 part_6_nz_tsb_config_2 |
| 3830 | part_6_ctx_zero_tsb_config_3 part_6_z_tsb_config_3 |
| 3831 | part_6_ctx_nonzero_tsb_config_3 part_6_nz_tsb_config_3 |
| 3832 | |
| 3833 | |
| 3834 | part_7_ctx_zero_tsb_config_0 part_7_z_tsb_config_0 |
| 3835 | part_7_ctx_nonzero_tsb_config_0 part_7_nz_tsb_config_0 |
| 3836 | part_7_ctx_zero_tsb_config_1 part_7_z_tsb_config_1 |
| 3837 | part_7_ctx_nonzero_tsb_config_1 part_7_nz_tsb_config_1 |
| 3838 | part_7_ctx_zero_tsb_config_2 part_7_z_tsb_config_2 |
| 3839 | part_7_ctx_nonzero_tsb_config_2 part_7_nz_tsb_config_2 |
| 3840 | part_7_ctx_zero_tsb_config_3 part_7_z_tsb_config_3 |
| 3841 | part_7_ctx_nonzero_tsb_config_3 part_7_nz_tsb_config_3 |
| 3842 | |
| 3843 | |
| 3844 | #endif |
| 3845 | #endif |
| 3846 | |