| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: err_handlers.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #ifndef __HTRAPS_HAS_ERR_HANDLERS__ |
| 39 | .global INST_ACCESS_MMU_ERROR_HANDLER |
| 40 | .global INST_ACCESS_ERROR_HANDLER |
| 41 | .global INT_PROC_ERR_HANDLER |
| 42 | .global DATA_ACCESS_MMU_ERROR_HANDLER |
| 43 | .global DATA_ACCESS_ERROR_HANDLER |
| 44 | .global HW_CORRECTED_ERROR_HANDLER |
| 45 | .global SW_RECOVERABLE_ERROR_HANDLER |
| 46 | .global STORE_ERROR_HANDLER |
| 47 | |
| 48 | SECTION .HTRAPS |
| 49 | .text |
| 50 | ! For ITTM, ITTP, ITDP errors, err_type is < 4. Issue demap all to the VA in TPC[TL]. |
| 51 | ! (Demap pg requires context knowledge - too much work) |
| 52 | ! For ITMU (err_type = 4), rd sfar to chk MRA index. |
| 53 | ! For ITL2U and ITL2ND errors issue retry. |
| 54 | |
| 55 | INST_ACCESS_MMU_ERROR_HANDLER: |
| 56 | read_isfsr: |
| 57 | add %g0, SFSR_VA, %g1 |
| 58 | ldxa [%g1]ASI_ISFSR, %g2 |
| 59 | cmp %g2, ISFSR_ITMU |
| 60 | be,a chk_sfar !! sfar stores the MRA index |
| 61 | bg,a clear_isfsr |
| 62 | demap_all: |
| 63 | rdpr %tpc, %g3 |
| 64 | mov 0x80, %g3 |
| 65 | ba clear_isfsr |
| 66 | stxa %g0, [%g3]ASI_IMMU_DEMAP |
| 67 | chk_sfar: |
| 68 | add %g0, SFAR_VA, %g3 |
| 69 | ldxa [%g3]ASI_SFAR, %g4 |
| 70 | clear_isfsr: |
| 71 | stxa %g0, [%g1]ASI_ISFSR |
| 72 | retry |
| 73 | |
| 74 | INST_ACCESS_ERROR_HANDLER: |
| 75 | add %g0, SFSR_VA, %g1 |
| 76 | ldxa [%g1]ASI_ISFSR, %g2 |
| 77 | rdpr %tpc, %g3 |
| 78 | stxa %g0, [%g1]ASI_ISFSR |
| 79 | retry |
| 80 | |
| 81 | INT_PROC_ERR_HANDLER: |
| 82 | read_ipe_dsfsr: |
| 83 | add %g0, SFSR_VA, %g1 |
| 84 | ldxa [%g1]ASI_DSFSR, %g2 |
| 85 | read_ipe_dsfar: |
| 86 | add %g0, SFAR_VA, %g1 |
| 87 | ldxa [%g1]ASI_SFAR, %g3 |
| 88 | |
| 89 | cmp %g2, DSFSR_FRFU |
| 90 | bl irf_error |
| 91 | cmp %g2, DSFSR_SBDLC |
| 92 | bl frf_error |
| 93 | cmp %g2, DSFSR_MRAU |
| 94 | bl stb_error |
| 95 | be mra_error |
| 96 | cmp %g2, DSFSR_SCAC |
| 97 | bl tsa_error |
| 98 | cmp %g2, DSFSR_TCCP |
| 99 | bl,a sca_error |
| 100 | ipe_tcc_error: |
| 101 | and %g3, 0x3, %g3 !! get the tca index |
| 102 | sllx %g3, 3, %g3 |
| 103 | mov %g3, %g4 |
| 104 | ldxa [%g3]ASI_TICK_ACCESS, %g5 !! read ecc |
| 105 | or %g3, 0x20, %g3 !!set NP bit to read data |
| 106 | ldxa [%g3]ASI_TICK_ACCESS, %g5 !! read data |
| 107 | setx ipe_clr_tcc_err, %g1, %g3 |
| 108 | jmp %g3+%g4 |
| 109 | nop |
| 110 | ipe_clr_tcc_err: |
| 111 | wr %g0, %g5, %tick_cmpr |
| 112 | ba,a ipe_clear_dsfsr |
| 113 | ipe_clr_stick_err: |
| 114 | wr %g0, %g5, %sys_tick_cmpr |
| 115 | ba,a ipe_clear_dsfsr |
| 116 | ipe_clr_hstick_err: |
| 117 | wrhpr %g0, %g5, %hsys_tick_cmpr |
| 118 | ba,a ipe_clear_dsfsr |
| 119 | |
| 120 | stb_error: |
| 121 | and %g3, 0x7, %g3 !! get stb_index |
| 122 | sllx %g3, 3, %g3 |
| 123 | ipe_rd_stb_entry_data: |
| 124 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 125 | ipe_rd_stb_entry_ecc: |
| 126 | or %g3, 0x40, %g3 |
| 127 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 128 | ipe_rd_stb_entry_addr: |
| 129 | or %g3, 0x80, %g3 |
| 130 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 131 | ipe_rd_stb_entry_par: |
| 132 | and %g3, 0xbf, %g3 |
| 133 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 134 | ipe_rd_stb_ptr: |
| 135 | add %g0, 0x100, %g1 !! read the stb ptr |
| 136 | ldxa [%g1]ASI_STB_ACCESS, %g2 |
| 137 | ba,a ipe_clear_dsfsr |
| 138 | |
| 139 | mra_error: |
| 140 | and %g3, 0x7, %g3 !! get mra_index |
| 141 | sllx %g3, 4, %g3 |
| 142 | setx ipe_rd_mra, %g1, %g4 |
| 143 | jmp %g3+%g4 |
| 144 | nop |
| 145 | ipe_rd_mra: |
| 146 | ipe_rd_mra_0: |
| 147 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %g1 |
| 148 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 |
| 149 | ba ipe_clear_dsfsr |
| 150 | nop |
| 151 | ipe_rd_mra_1: |
| 152 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g1 |
| 153 | ldxa [%g1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 |
| 154 | ba ipe_clear_dsfsr |
| 155 | nop |
| 156 | ipe_rd_mra_2: |
| 157 | add %g0, ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0, %g1 |
| 158 | ldxa [%g1]ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG, %g2 |
| 159 | ba ipe_clear_dsfsr |
| 160 | nop |
| 161 | ipe_rd_mra_3: |
| 162 | add %g0, ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2, %g1 |
| 163 | ldxa [%g1]ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG, %g2 |
| 164 | ba ipe_clear_dsfsr |
| 165 | nop |
| 166 | ipe_rd_mra_4: |
| 167 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %g1 |
| 168 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g2 |
| 169 | ba ipe_clear_dsfsr |
| 170 | nop |
| 171 | ipe_rd_mra_5: |
| 172 | add %g0, ASI_MMU_PHYSICAL_OFFSET_1, %g1 |
| 173 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g2 |
| 174 | ba ipe_clear_dsfsr |
| 175 | nop |
| 176 | ipe_rd_mra_6: |
| 177 | add %g0, ASI_MMU_PHYSICAL_OFFSET_2, %g1 |
| 178 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g2 |
| 179 | ba ipe_clear_dsfsr |
| 180 | nop |
| 181 | ipe_rd_mra_7: |
| 182 | add %g0, ASI_MMU_PHYSICAL_OFFSET_3, %g1 |
| 183 | ldxa [%g1]ASI_MMU_PHYSICAL_OFFSET, %g2 |
| 184 | ba ipe_clear_dsfsr |
| 185 | nop |
| 186 | |
| 187 | sca_error: |
| 188 | and %g3, 0x7, %g3 !! get sca_index |
| 189 | sllx %g3, 3, %g3 |
| 190 | mov %g3, %g4 |
| 191 | ldxa [%g3]ASI_SCRATCHPAD_ACCESS, %g5 !! read ecc |
| 192 | or %g3, 0x40, %g3 !!set NP bit to read data |
| 193 | ldxa [%g3]ASI_SCRATCHPAD_ACCESS, %g5 !! read data |
| 194 | ipe_clr_sca_err: |
| 195 | stxa %g5, [%g4]ASI_HYP_SCRATCHPAD |
| 196 | ba ipe_clear_dsfsr |
| 197 | nop |
| 198 | |
| 199 | tsa_error: |
| 200 | and %g3, 0x7, %g3 !! get tsa_index |
| 201 | rdpr %tl, %g1 !! store the current tl |
| 202 | cmp %g3, 6 |
| 203 | bl ipe_priv_reg_err |
| 204 | be ipe_mondo_reg_err |
| 205 | bg FAIL |
| 206 | |
| 207 | ipe_priv_reg_err: |
| 208 | inc %g3 |
| 209 | wrpr %g0, %g3, %tl |
| 210 | rdpr %tstate, %g2 |
| 211 | wrpr %g0, %g2, %tstate !! shd clear the error |
| 212 | wrpr %g0, %g1, %tl |
| 213 | ba ipe_clear_dsfsr |
| 214 | nop |
| 215 | |
| 216 | ipe_mondo_reg_err: |
| 217 | add %g0, ASI_CPU_MONDO_QUEUE_HEAD, %g1 |
| 218 | ldxa [%g1]ASI_QUEUE, %g2 |
| 219 | stxa %g2, [%g1]ASI_QUEUE |
| 220 | ba ipe_clear_dsfsr |
| 221 | nop |
| 222 | |
| 223 | irf_error: |
| 224 | ipe_get_reg_no: |
| 225 | and %g3, 0x1f, %g1 |
| 226 | ipe_rd_irf_ecc: |
| 227 | sllx %g1, 3, %g2 |
| 228 | ldxa [%g2]ASI_IRF_ECC_REG, %g4 |
| 229 | ipe_get_syndrome: |
| 230 | srlx %g3, 7, %g2 |
| 231 | and %g2, 0xff, %g2 |
| 232 | ipe_get_gl: |
| 233 | srlx %g3, 5, %g2 |
| 234 | and %g2, 0x3, %g2 |
| 235 | |
| 236 | rdpr %gl, %g7 !! read the current gl |
| 237 | cmp %g1, 0x7 |
| 238 | bg ipe_rd_array !! err not in global |
| 239 | cmp %g2, 0x3 !! If gl of err reg is less then max gl then clr the err |
| 240 | be,a ipe_rd_array |
| 241 | wrpr %g0, %g2, %gl !! restore the gl to error gl |
| 242 | |
| 243 | ipe_rd_array: |
| 244 | setx ipe_rd_err_reg, %g4, %g5 |
| 245 | sllx %g1, 3, %g6 |
| 246 | jmp %g5+%g6 |
| 247 | nop |
| 248 | ipe_rd_err_reg: |
| 249 | ipe_rd_g0: |
| 250 | stxa %r0, [%g0]ASI_SCRATCHPAD |
| 251 | ba,a ipe_wr_err_rg |
| 252 | ipe_rd_g1: |
| 253 | stxa %r1, [%g0]ASI_SCRATCHPAD |
| 254 | ba,a ipe_wr_err_rg |
| 255 | ipe_rd_g2: |
| 256 | stxa %r2, [%g0]ASI_SCRATCHPAD |
| 257 | ba,a ipe_wr_err_rg |
| 258 | ipe_rd_g3: |
| 259 | stxa %r3, [%g0]ASI_SCRATCHPAD |
| 260 | ba,a ipe_wr_err_rg |
| 261 | ipe_rd_g4: |
| 262 | stxa %r4, [%g0]ASI_SCRATCHPAD |
| 263 | ba,a ipe_wr_err_rg |
| 264 | ipe_rd_g5: |
| 265 | stxa %r5, [%g0]ASI_SCRATCHPAD |
| 266 | ba,a ipe_wr_err_rg |
| 267 | ipe_rd_g6: |
| 268 | stxa %r6, [%g0]ASI_SCRATCHPAD |
| 269 | ba,a ipe_wr_err_rg |
| 270 | ipe_rd_g7: |
| 271 | stxa %r7, [%g0]ASI_SCRATCHPAD |
| 272 | ba,a ipe_wr_err_rg |
| 273 | ipe_rd_r8: |
| 274 | stxa %r8, [%g0]ASI_SCRATCHPAD |
| 275 | ba,a ipe_wr_err_rg |
| 276 | ipe_rd_r9: |
| 277 | stxa %r9, [%g0]ASI_SCRATCHPAD |
| 278 | ba,a ipe_wr_err_rg |
| 279 | ipe_rd_r10: |
| 280 | stxa %r10, [%g0]ASI_SCRATCHPAD |
| 281 | ba,a ipe_wr_err_rg |
| 282 | ipe_rd_r11: |
| 283 | stxa %r11, [%g0]ASI_SCRATCHPAD |
| 284 | ba,a ipe_wr_err_rg |
| 285 | ipe_rd_r12: |
| 286 | stxa %r12, [%g0]ASI_SCRATCHPAD |
| 287 | ba,a ipe_wr_err_rg |
| 288 | ipe_rd_r13: |
| 289 | stxa %r13, [%g0]ASI_SCRATCHPAD |
| 290 | ba,a ipe_wr_err_rg |
| 291 | ipe_rd_r14: |
| 292 | stxa %r14, [%g0]ASI_SCRATCHPAD |
| 293 | ba,a ipe_wr_err_rg |
| 294 | ipe_rd_r15: |
| 295 | stxa %r15, [%g0]ASI_SCRATCHPAD |
| 296 | ba,a ipe_wr_err_rg |
| 297 | ipe_rd_r16: |
| 298 | stxa %r16, [%g0]ASI_SCRATCHPAD |
| 299 | ba,a ipe_wr_err_rg |
| 300 | ipe_rd_r17: |
| 301 | stxa %r17, [%g0]ASI_SCRATCHPAD |
| 302 | ba,a ipe_wr_err_rg |
| 303 | ipe_rd_r18: |
| 304 | stxa %r18, [%g0]ASI_SCRATCHPAD |
| 305 | ba,a ipe_wr_err_rg |
| 306 | ipe_rd_r19: |
| 307 | stxa %r19, [%g0]ASI_SCRATCHPAD |
| 308 | ba,a ipe_wr_err_rg |
| 309 | ipe_rd_r20: |
| 310 | stxa %r20, [%g0]ASI_SCRATCHPAD |
| 311 | ba,a ipe_wr_err_rg |
| 312 | ipe_rd_r21: |
| 313 | stxa %r21, [%g0]ASI_SCRATCHPAD |
| 314 | ba,a ipe_wr_err_rg |
| 315 | ipe_rd_r22: |
| 316 | stxa %r22, [%g0]ASI_SCRATCHPAD |
| 317 | ba,a ipe_wr_err_rg |
| 318 | ipe_rd_r23: |
| 319 | stxa %r23, [%g0]ASI_SCRATCHPAD |
| 320 | ba,a ipe_wr_err_rg |
| 321 | ipe_rd_r24: |
| 322 | stxa %r24, [%g0]ASI_SCRATCHPAD |
| 323 | ba,a ipe_wr_err_rg |
| 324 | ipe_rd_r25: |
| 325 | stxa %r25, [%g0]ASI_SCRATCHPAD |
| 326 | ba,a ipe_wr_err_rg |
| 327 | ipe_rd_r26: |
| 328 | stxa %r26, [%g0]ASI_SCRATCHPAD |
| 329 | ba,a ipe_wr_err_rg |
| 330 | ipe_rd_r27: |
| 331 | stxa %r27, [%g0]ASI_SCRATCHPAD |
| 332 | ba,a ipe_wr_err_rg |
| 333 | ipe_rd_r28: |
| 334 | stxa %r28, [%g0]ASI_SCRATCHPAD |
| 335 | ba,a ipe_wr_err_rg |
| 336 | ipe_rd_r29: |
| 337 | stxa %r29, [%g0]ASI_SCRATCHPAD |
| 338 | ba,a ipe_wr_err_rg |
| 339 | ipe_rd_r30: |
| 340 | stxa %r30, [%g0]ASI_SCRATCHPAD |
| 341 | ba,a ipe_wr_err_rg |
| 342 | ipe_rd_r31: |
| 343 | stxa %r31, [%g0]ASI_SCRATCHPAD |
| 344 | ipe_wr_err_rg: |
| 345 | setx ipe_wr_g0, %g4, %g5 |
| 346 | jmp %g5+%g6 |
| 347 | nop |
| 348 | |
| 349 | ipe_wr_g0: |
| 350 | ldxa [%g0]ASI_SCRATCHPAD, %r0 |
| 351 | ba,a ipe_restore_gl |
| 352 | ipe_wr_g1: |
| 353 | ldxa [%g0]ASI_SCRATCHPAD, %r1 |
| 354 | ba,a ipe_restore_gl |
| 355 | ipe_wr_g2: |
| 356 | ldxa [%g0]ASI_SCRATCHPAD, %r2 |
| 357 | ba,a ipe_restore_gl |
| 358 | ipe_wr_g3: |
| 359 | ldxa [%g0]ASI_SCRATCHPAD, %r3 |
| 360 | ba,a ipe_restore_gl |
| 361 | ipe_wr_g4: |
| 362 | ldxa [%g0]ASI_SCRATCHPAD, %r4 |
| 363 | ba,a ipe_restore_gl |
| 364 | ipe_wr_g5: |
| 365 | ldxa [%g0]ASI_SCRATCHPAD, %r5 |
| 366 | ba,a ipe_restore_gl |
| 367 | ipe_wr_g6: |
| 368 | ldxa [%g0]ASI_SCRATCHPAD, %r6 |
| 369 | ba,a ipe_restore_gl |
| 370 | ipe_wr_g7: |
| 371 | ldxa [%g0]ASI_SCRATCHPAD, %r7 |
| 372 | ba,a ipe_restore_gl |
| 373 | ipe_wr_r8: |
| 374 | ldxa [%g0]ASI_SCRATCHPAD, %r8 |
| 375 | ba,a ipe_restore_gl |
| 376 | ipe_wr_r9: |
| 377 | ldxa [%g0]ASI_SCRATCHPAD, %r9 |
| 378 | ba,a ipe_restore_gl |
| 379 | ipe_wr_r10: |
| 380 | ldxa [%g0]ASI_SCRATCHPAD, %r10 |
| 381 | ba,a ipe_restore_gl |
| 382 | ipe_wr_r11: |
| 383 | ldxa [%g0]ASI_SCRATCHPAD, %r11 |
| 384 | ba,a ipe_restore_gl |
| 385 | ipe_wr_r12: |
| 386 | ldxa [%g0]ASI_SCRATCHPAD, %r12 |
| 387 | ba,a ipe_restore_gl |
| 388 | ipe_wr_r13: |
| 389 | ldxa [%g0]ASI_SCRATCHPAD, %r13 |
| 390 | ba,a ipe_restore_gl |
| 391 | ipe_wr_r14: |
| 392 | ldxa [%g0]ASI_SCRATCHPAD, %r14 |
| 393 | ba,a ipe_restore_gl |
| 394 | ipe_wr_r15: |
| 395 | ldxa [%g0]ASI_SCRATCHPAD, %r15 |
| 396 | ba,a ipe_restore_gl |
| 397 | ipe_wr_r16: |
| 398 | ldxa [%g0]ASI_SCRATCHPAD, %r16 |
| 399 | ba,a ipe_restore_gl |
| 400 | ipe_wr_r17: |
| 401 | ldxa [%g0]ASI_SCRATCHPAD, %r17 |
| 402 | ba,a ipe_restore_gl |
| 403 | ipe_wr_r18: |
| 404 | ldxa [%g0]ASI_SCRATCHPAD, %r18 |
| 405 | ba,a ipe_restore_gl |
| 406 | ipe_wr_r19: |
| 407 | ldxa [%g0]ASI_SCRATCHPAD, %r19 |
| 408 | ba,a ipe_restore_gl |
| 409 | ipe_wr_r20: |
| 410 | ldxa [%g0]ASI_SCRATCHPAD, %r20 |
| 411 | ba,a ipe_restore_gl |
| 412 | ipe_wr_r21: |
| 413 | ldxa [%g0]ASI_SCRATCHPAD, %r21 |
| 414 | ba,a ipe_restore_gl |
| 415 | ipe_wr_r22: |
| 416 | ldxa [%g0]ASI_SCRATCHPAD, %r22 |
| 417 | ba,a ipe_restore_gl |
| 418 | ipe_wr_r23: |
| 419 | ldxa [%g0]ASI_SCRATCHPAD, %r23 |
| 420 | ba,a ipe_restore_gl |
| 421 | ipe_wr_r24: |
| 422 | ldxa [%g0]ASI_SCRATCHPAD, %r24 |
| 423 | ba,a ipe_restore_gl |
| 424 | ipe_wr_r25: |
| 425 | ldxa [%g0]ASI_SCRATCHPAD, %r25 |
| 426 | ba,a ipe_restore_gl |
| 427 | ipe_wr_r26: |
| 428 | ldxa [%g0]ASI_SCRATCHPAD, %r26 |
| 429 | ba,a ipe_restore_gl |
| 430 | ipe_wr_r27: |
| 431 | ldxa [%g0]ASI_SCRATCHPAD, %r27 |
| 432 | ba,a ipe_restore_gl |
| 433 | ipe_wr_r28: |
| 434 | ldxa [%g0]ASI_SCRATCHPAD, %r28 |
| 435 | ba,a ipe_restore_gl |
| 436 | ipe_wr_r29: |
| 437 | ldxa [%g0]ASI_SCRATCHPAD, %r29 |
| 438 | ba,a ipe_restore_gl |
| 439 | ipe_wr_r30: |
| 440 | ldxa [%g0]ASI_SCRATCHPAD, %r30 |
| 441 | ba,a ipe_restore_gl |
| 442 | ipe_wr_r31: |
| 443 | ldxa [%g0]ASI_SCRATCHPAD, %r31 |
| 444 | ipe_restore_gl: |
| 445 | wrpr %g0, %g7, %gl |
| 446 | ba ipe_clear_dsfsr |
| 447 | nop |
| 448 | |
| 449 | frf_error: |
| 450 | ipe_get_frf_reg_no: |
| 451 | and %g3, 0x3f, %g1 |
| 452 | ipe_get_frf_even_syndrome: |
| 453 | srlx %g3, 6, %g2 |
| 454 | and %g2, 0x7f, %g2 |
| 455 | ipe_get_frf_odd_syndrome: |
| 456 | srlx %g3, 13, %g2 |
| 457 | and %g2, 0x7f, %g2 |
| 458 | ipe_rd_frf_ecc: |
| 459 | sllx %g1, 3, %g1 |
| 460 | ldxa [%g1]ASI_FRF_ECC_REG, %g3 |
| 461 | |
| 462 | ipe_clear_dsfsr: |
| 463 | add %g0, SFSR_VA, %g1 |
| 464 | stxa %g0, [%g1]ASI_DSFSR |
| 465 | retry |
| 466 | |
| 467 | DATA_ACCESS_MMU_ERROR_HANDLER: |
| 468 | dme_read_dsfsr: |
| 469 | add %g0, SFSR_VA, %g1 |
| 470 | ldxa [%g1]ASI_DSFSR, %g2 |
| 471 | dme_read_dsfar: |
| 472 | add %g0, SFAR_VA, %g4 |
| 473 | ldxa [%g4]ASI_SFAR, %g3 |
| 474 | cmp %g2, DSFSR_DTMU |
| 475 | bge,a dme_clear_dsfsr |
| 476 | dme_demap_all: |
| 477 | mov 0x80, %g3 |
| 478 | stxa %g0, [%g3]ASI_DMMU_DEMAP |
| 479 | dme_clear_dsfsr: |
| 480 | stxa %g0, [%g1]ASI_DSFSR |
| 481 | retry |
| 482 | |
| 483 | DATA_ACCESS_ERROR_HANDLER: |
| 484 | add %g0, SFSR_VA, %g1 |
| 485 | ldxa [%g1]ASI_DSFSR, %g2 |
| 486 | stxa %g0, [%g1]ASI_DSFSR |
| 487 | retry |
| 488 | |
| 489 | HW_CORRECTED_ERROR_HANDLER: |
| 490 | hce_read_desr: |
| 491 | ldxa [%g0]ASI_DESR, %g1 !! Also clears desr |
| 492 | hce_chk_errt: |
| 493 | srlx %g1, 56, %g2 |
| 494 | and %g2, 0x1F, %g2 |
| 495 | cmp %g2, DESR_ICDP |
| 496 | ble hce_ic_error |
| 497 | cmp %g2, DESR_DCDP |
| 498 | ble hce_dc_error |
| 499 | cmp %g2, DESR_SBDPC |
| 500 | be,a hce_sbdpc_error |
| 501 | retry !! Can't do much for l2c errors |
| 502 | |
| 503 | hce_dc_error: |
| 504 | and %g1, 0x1ff, %g2 |
| 505 | sllx %g2, 4, %g2 !! index is in bits 10:4 of addr |
| 506 | add %g0, 0x800, %g1 |
| 507 | sllx %g1, 2, %g1 !! for reading data, bit 13 of index shd be 1 |
| 508 | hce_dc_rd_tag: |
| 509 | ldxa [%g2]ASI_DC_TAG, %g3 |
| 510 | /* |
| 511 | hce_dc_rd_data: |
| 512 | ldxa [%g2+%g1]ASI_DC_DATA, %g4 |
| 513 | or %g2, 0x8, %g2 !! read MSB 8 bytes from cache line |
| 514 | ldxa [%g2+%g1]ASI_DC_DATA, %g4 |
| 515 | */ |
| 516 | retry |
| 517 | |
| 518 | hce_ic_error: |
| 519 | and %g1, 0x1ff, %g2 |
| 520 | sllx %g2, 5, %g2 !! index is in bits 10:5 of addr for tag read |
| 521 | sllx %g2, 1, %g1 !! index is in bits 11:6 of addr for data read |
| 522 | hce_ic_rd_tag: |
| 523 | ldxa [%g0+%g2]ASI_IC_TAG, %g3 |
| 524 | mov %g0, %g2 |
| 525 | hce_ic_rd_instr: |
| 526 | ldxa [%g1]ASI_IC_INSTR, %g4 |
| 527 | add %g1, 8, %g1 |
| 528 | cmp %g2, 7 |
| 529 | bl hce_ic_rd_instr |
| 530 | inc %g2 |
| 531 | retry |
| 532 | |
| 533 | hce_sbdpc_error: |
| 534 | and %g1, 0x7, %g3 !! get stb_index |
| 535 | sllx %g3, 3, %g3 |
| 536 | hce_rd_stb_entry_data: |
| 537 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 538 | hce_rd_stb_entry_ecc: |
| 539 | or %g3, 0x40, %g3 |
| 540 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 541 | hce_rd_stb_entry_addr: |
| 542 | or %g3, 0x80, %g3 |
| 543 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 544 | hce_rd_stb_entry_par: |
| 545 | and %g3, 0xbf, %g3 |
| 546 | ldxa [%g3]ASI_STB_ACCESS, %g2 |
| 547 | retry |
| 548 | |
| 549 | !! The sw_recoverable_err trap is taken mostly for uncorrectable errors. |
| 550 | !! Most of these are due to errors on L2c returns. Can't chk much in the |
| 551 | !! trap handler for these. |
| 552 | |
| 553 | SW_RECOVERABLE_ERROR_HANDLER: |
| 554 | swe_read_desr: |
| 555 | ldxa [%g0]ASI_DESR, %g1 !! Also clears desr |
| 556 | retry |
| 557 | |
| 558 | STORE_ERROR_HANDLER: |
| 559 | ste_read_dfesr: |
| 560 | add %g0, DFESR_VA, %g1 |
| 561 | ldxa [%g1]ASI_DFESR, %g2 !! read the DFESR |
| 562 | retry |
| 563 | |
| 564 | FAIL: EXIT_BAD |
| 565 | nop |
| 566 | #endif |