| 1 | /************************************************************************ |
| 2 | Test case code start |
| 3 | ************************************************************************/ |
| 4 | |
| 5 | .text |
| 6 | .global main_th_56 |
| 7 | .global main_th_57 |
| 8 | .global main_th_58 |
| 9 | .global main_th_59 |
| 10 | .global main_th_60 |
| 11 | .global main_th_61 |
| 12 | .global main_th_62 |
| 13 | .global main_th_63 |
| 14 | |
| 15 | ! |
| 16 | ! Thread 0 Start |
| 17 | ! |
| 18 | main_th_56: |
| 19 | TEST |
| 20 | setx t56_data_area, %g1, %l7 |
| 21 | setx t56_blk_area,%g1,%g5; |
| 22 | setx 0x5555555555555555, %g3, %g4 |
| 23 | |
| 24 | !# Enable PMU to count instructions... |
| 25 | setx t56_t62_perf,%g3,%g6; |
| 26 | ldx [%g6],%g6; |
| 27 | wr %g0, %g0, %pic |
| 28 | wr %g6, %g0, %pcr |
| 29 | |
| 30 | !# Make sure FP trap enables are off... |
| 31 | |
| 32 | stx %g0, [%l7] |
| 33 | ldx [%l7], %fsr |
| 34 | |
| 35 | stx %g4, [%l7] |
| 36 | ldd [%l7], %f6 |
| 37 | fxtod %f6, %f0 |
| 38 | fxtod %f6, %f2 |
| 39 | |
| 40 | |
| 41 | !# Execute Main Diag .. |
| 42 | setx loop_cnt_4, %g2,%g1 !msa |
| 43 | set 0x0, %g2 |
| 44 | addcc %g0, 0x0, %g3 |
| 45 | setx 0xffffffffffffffff, %g2, %l2 |
| 46 | t56_start: |
| 47 | xor %l1, %l2, %l1 |
| 48 | !#add %l0, 0x1efe, %l0 |
| 49 | add %l0, -0xefe, %l0 |
| 50 | fmuld %f0, %f2, %f4 |
| 51 | ldd [%l7], %f6 |
| 52 | |
| 53 | !stb %g0,[%g5] |
| 54 | |
| 55 | xor %l1, %l2, %l1 |
| 56 | add %l0, -0xefe, %l0 |
| 57 | fmuld %f0, %f2, %f4 |
| 58 | ldd [%l7], %f6 |
| 59 | |
| 60 | bpos %xcc,t56_start |
| 61 | subcc %g1,1,%g1 |
| 62 | |
| 63 | setx t56_perf_cnt,%g1,%g2 |
| 64 | rd %pic,%g1; |
| 65 | stx %g1,[%g2]; |
| 66 | EXIT_GOOD |
| 67 | |
| 68 | ! |
| 69 | ! Thread 1 Start |
| 70 | ! |
| 71 | main_th_57: |
| 72 | TEST |
| 73 | setx t57_data_area, %g1, %l7 |
| 74 | setx t57_blk_area,%g1,%g5; |
| 75 | |
| 76 | !# Initialize registers .. |
| 77 | !# Enable PMU to count instructions... |
| 78 | setx t56_t62_perf,%g3,%g6; |
| 79 | ldx [%g6],%g6; |
| 80 | !#setx 0x17f85fe7, %g3, %g6 |
| 81 | wr %g0, %g0, %pic |
| 82 | wr %g6, %g0, %pcr |
| 83 | |
| 84 | !# Make sure FP trap enables are off... |
| 85 | stx %g0, [%l7] |
| 86 | ldx [%l7], %fsr |
| 87 | |
| 88 | setx 0xf0f0f0abcdef9fff, %g3, %g4 |
| 89 | stx %g4, [%l7] |
| 90 | ldd [%l7], %f6 |
| 91 | fxtod %f6, %f0 |
| 92 | fxtod %f6, %f2 |
| 93 | |
| 94 | !# Execute Main Diag .. |
| 95 | setx loop_cnt_3, %g2, %g1 |
| 96 | set 0x0, %g2 |
| 97 | addcc %g0, 0x0, %g3 |
| 98 | setx 0xffffffffffffffff, %g2, %l2 |
| 99 | ba,a t57_start |
| 100 | .align 32 |
| 101 | t57_start: |
| 102 | |
| 103 | !addcc %g1,-0xfff,%g1 |
| 104 | |
| 105 | ldd [%l7], %f6 |
| 106 | fmuld %f0, %f2, %f4 |
| 107 | add %l0, -0xefe, %l0 |
| 108 | xor %l1, %l2, %l1 |
| 109 | |
| 110 | !stxa %l2,[%g5] 0xe2 |
| 111 | stb %l2,[%g5] |
| 112 | |
| 113 | ldd [%l7], %f6 |
| 114 | fmuld %f0, %f2, %f4 |
| 115 | add %l0, -0xefe, %l0 |
| 116 | xor %l1, %l2, %l1 |
| 117 | |
| 118 | bpos %xcc,t57_start |
| 119 | !addcc %g1,-0xfff,%g1 |
| 120 | subcc %g1,1,%g1 |
| 121 | |
| 122 | setx t57_perf_cnt,%g1,%g2 |
| 123 | rd %pic,%g1; |
| 124 | stx %g1,[%g2]; |
| 125 | EXIT_GOOD |
| 126 | |
| 127 | ! |
| 128 | ! Thread 2 T2_Start |
| 129 | ! |
| 130 | main_th_58: |
| 131 | TEST |
| 132 | setx t58_data_area, %g1, %l7 |
| 133 | setx t58_blk_area,%g1,%g5; |
| 134 | |
| 135 | !# Initialize registers .. |
| 136 | !# Enable PMU to count instructions... |
| 137 | setx t56_t62_perf,%g3,%g6; |
| 138 | ldx [%g6],%g6; |
| 139 | !#setx 0x17f85fe7, %g3, %g6 |
| 140 | wr %g0, %g0, %pic |
| 141 | wr %g6, %g0, %pcr |
| 142 | |
| 143 | !# Make sure FP trap enables are off... |
| 144 | stx %g0, [%l7] |
| 145 | ldx [%l7], %fsr |
| 146 | |
| 147 | setx 0xefefefdcdcababab, %g3, %g4 |
| 148 | stx %g4, [%l7] |
| 149 | ldd [%l7], %f6 |
| 150 | fxtod %f6, %f0 |
| 151 | fxtod %f6, %f2 |
| 152 | |
| 153 | |
| 154 | !# Execute Main Diag .. |
| 155 | setx loop_cnt_3, %g2, %g1 |
| 156 | set 0x0, %g2 |
| 157 | addcc %g0, 0x0, %g3 |
| 158 | ba,a t58_start |
| 159 | .align 32 |
| 160 | t58_start: |
| 161 | ldx [%l7], %l5 |
| 162 | fmuld %f0, %f2, %f4 |
| 163 | fmuld %f0, %f2, %f4 |
| 164 | fmuld %f0, %f2, %f4 |
| 165 | add %l0, -0xefe, %l0 |
| 166 | xor %l1, %l2, %l1 |
| 167 | stb %g0,[%g5] |
| 168 | |
| 169 | ldd [%l7], %f6 |
| 170 | fmuld %f0, %f2, %f4 |
| 171 | add %l0, -0xefe, %l0 |
| 172 | xor %l1, %l2, %l1 |
| 173 | |
| 174 | bpos %xcc, t58_start |
| 175 | !addcc %g1,-0xfff,%g1 |
| 176 | subcc %g1,1,%g1 |
| 177 | setx t58_perf_cnt,%g1,%g2 |
| 178 | rd %pic,%g1; |
| 179 | stx %g1,[%g2]; |
| 180 | EXIT_GOOD |
| 181 | |
| 182 | ! |
| 183 | ! Thread 3 T2_Start |
| 184 | ! |
| 185 | main_th_59: |
| 186 | TEST |
| 187 | setx t59_data_area, %g1, %l7 |
| 188 | setx t59_blk_area,%g1,%g5; |
| 189 | |
| 190 | !# Initialize registers .. |
| 191 | !# Enable PMU to count instructions... |
| 192 | setx t56_t62_perf,%g3,%g6; |
| 193 | ldx [%g6],%g6; |
| 194 | !#setx 0x17f85fe7, %g3, %g6 |
| 195 | wr %g0, %g0, %pic |
| 196 | wr %g6, %g0, %pcr |
| 197 | |
| 198 | !# Make sure FP trap enables are off... |
| 199 | stx %g0, [%l7] |
| 200 | ldx [%l7], %fsr |
| 201 | |
| 202 | setx 0xf9f8f7f6f5f4f3f2, %g3, %g4 |
| 203 | stx %g4, [%l7] |
| 204 | ldd [%l7], %f6 |
| 205 | fxtod %f6, %f0 |
| 206 | fxtod %f6, %f2 |
| 207 | |
| 208 | |
| 209 | !# Execute Main Diag .. |
| 210 | setx loop_cnt_2, %g2, %g1 |
| 211 | set 0x0, %g2 |
| 212 | addcc %g0, 0x0, %g3 |
| 213 | ba,a t59_start |
| 214 | .align 32 |
| 215 | t59_start: |
| 216 | xor %l1, %l2, %l1 |
| 217 | add %l0, -0xefe, %l0 |
| 218 | ldx [%l7], %l5 |
| 219 | !# fmuld %f0, %f2, %f4 |
| 220 | |
| 221 | !stb %g0,[%g5] |
| 222 | xor %l1, %l2, %l1 |
| 223 | add %l0, -0xefe, %l0 |
| 224 | ldd [%l7], %f6 |
| 225 | !# fmuld %f0, %f2, %f4 |
| 226 | |
| 227 | bpos %xcc,t59_start |
| 228 | !addcc %g1,-0xfff,%g1 |
| 229 | subcc %g1,1,%g1 |
| 230 | setx t59_perf_cnt,%g1,%g2 |
| 231 | rd %pic,%g1; |
| 232 | stx %g1,[%g2]; |
| 233 | EXIT_GOOD |
| 234 | |
| 235 | ! |
| 236 | ! Thread 4 T3_Start |
| 237 | ! |
| 238 | main_th_60: |
| 239 | TEST |
| 240 | setx t60_data_area, %g1, %l7 |
| 241 | setx t60_blk_area,%g1,%g5; |
| 242 | |
| 243 | !# Initialize registers .. |
| 244 | !# Enable PMU to count instructions... |
| 245 | setx t56_t62_perf,%g3,%g6; |
| 246 | ldx [%g6],%g6; |
| 247 | !#setx 0x17f85fe7, %g3, %g6 |
| 248 | wr %g0, %g0, %pic |
| 249 | wr %g6, %g0, %pcr |
| 250 | |
| 251 | |
| 252 | !# Make sure trap enables are off... |
| 253 | !# Global registers |
| 254 | setx 0xaaaaaaaaaaaaaaaa, %g3, %g4 |
| 255 | stx %g0, [%l7] |
| 256 | ldx [%l7], %fsr |
| 257 | |
| 258 | stx %g4, [%l7] |
| 259 | ldd [%l7], %f6 |
| 260 | fxtod %f6, %f0 |
| 261 | fxtod %f6, %f2 |
| 262 | |
| 263 | |
| 264 | !# Execute Main Diag .. |
| 265 | setx loop_cnt, %g2, %g1 |
| 266 | set 0x0, %g2 |
| 267 | addcc %g0, 0x0, %g3 |
| 268 | t60_start: |
| 269 | ldx [%l7], %l5 |
| 270 | fmuld %f0, %f2, %f4 |
| 271 | !# add %l0, -0xemv, %l0 |
| 272 | xor %l1, %l2, %l1 |
| 273 | |
| 274 | !stb %g4,[%g5] |
| 275 | ldd [%l7], %f6 |
| 276 | fmuld %f0, %f2, %f4 |
| 277 | add %l0, -0xefe, %l0 |
| 278 | xor %l1, %l2, %l1 |
| 279 | ldx [%l7], %l5 |
| 280 | |
| 281 | bpos %xcc,t60_start |
| 282 | !addcc %g1,-0xfff,%g1 |
| 283 | subcc %g1,1,%g1 |
| 284 | |
| 285 | setx t60_perf_cnt,%g1,%g2 |
| 286 | rd %pic,%g1; |
| 287 | stx %g1,[%g2]; |
| 288 | EXIT_GOOD |
| 289 | |
| 290 | ! |
| 291 | ! Thread 5 Start |
| 292 | ! |
| 293 | main_th_61: |
| 294 | TEST |
| 295 | setx t61_data_area, %g1, %l7 |
| 296 | setx t61_blk_area,%g1,%g5; |
| 297 | |
| 298 | !# Initialize registers .. |
| 299 | !# Enable PMU to count instructions... |
| 300 | setx t56_t62_perf,%g3,%g6; |
| 301 | ldx [%g6],%g6; |
| 302 | !#setx 0x17f85fe7, %g3, %g6 |
| 303 | wr %g0, %g0, %pic |
| 304 | wr %g6, %g0, %pcr |
| 305 | |
| 306 | |
| 307 | !# Make sure trap enables are off... |
| 308 | !# Global registers |
| 309 | setx 0xaaaaaaaaaaaaaaaa, %g3, %g4 |
| 310 | stx %g0, [%l7] |
| 311 | ldx [%l7], %fsr |
| 312 | |
| 313 | stx %g4, [%l7] |
| 314 | ldd [%l7], %f6 |
| 315 | fxtod %f6, %f0 |
| 316 | fxtod %f6, %f2 |
| 317 | |
| 318 | |
| 319 | !# Execute Main Diag .. |
| 320 | setx loop_cnt, %g2, %g1 |
| 321 | set 0x0, %g2 |
| 322 | addcc %g0, 0x0, %g3 |
| 323 | ba,a t61_start |
| 324 | .align 32 |
| 325 | t61_start: |
| 326 | ldx [%l7], %l5 |
| 327 | ldx [%l7], %l5 |
| 328 | ldx [%l7], %l5 |
| 329 | ldx [%l7], %l5 |
| 330 | fmuld %f0, %f2, %f4 |
| 331 | add %l0, -0xefe, %l0 |
| 332 | xor %l1, %l2, %l1 |
| 333 | |
| 334 | !stb %g4,[%g5] |
| 335 | ldd [%l7], %f6 |
| 336 | fmuld %f0, %f2, %f4 |
| 337 | add %l0, -0xefe, %l0 |
| 338 | xor %l1, %l2, %l1 |
| 339 | |
| 340 | bpos %xcc,t61_start |
| 341 | !addcc %g1,-0xfff,%g1 |
| 342 | subcc %g1,1,%g1 |
| 343 | setx t61_perf_cnt,%g1,%g2 |
| 344 | rd %pic,%g1; |
| 345 | stx %g1,[%g2]; |
| 346 | EXIT_GOOD |
| 347 | |
| 348 | ! |
| 349 | ! Thread 6 Start |
| 350 | ! |
| 351 | main_th_62: |
| 352 | TEST |
| 353 | setx t62_data_area, %g1, %l7 |
| 354 | setx t62_blk_area,%g1,%g5; |
| 355 | |
| 356 | !# Initialize registers .. |
| 357 | !# Enable PMU to count instructions... |
| 358 | setx t56_t62_perf,%g3,%g6; |
| 359 | ldx [%g6],%g6; |
| 360 | !#setx 0x17f85fe7, %g3, %g6 |
| 361 | wr %g0, %g0, %pic |
| 362 | wr %g6, %g0, %pcr |
| 363 | |
| 364 | !# Make sure trap enables are off... |
| 365 | !# Global registers |
| 366 | setx 0xfedcba9876543210, %g3, %g4 |
| 367 | stx %g0, [%l7] |
| 368 | ldx [%l7], %fsr |
| 369 | |
| 370 | stx %g4, [%l7] |
| 371 | ldd [%l7], %f6 |
| 372 | fxtod %f6, %f0 |
| 373 | fxtod %f6, %f2 |
| 374 | |
| 375 | |
| 376 | !# Execute Main Diag .. |
| 377 | setx loop_cnt_2, %g2, %g1 |
| 378 | set 0x0, %g2 |
| 379 | addcc %g0, 0x0, %g3 |
| 380 | ba,a t62_start |
| 381 | .align 32 |
| 382 | t62_start: |
| 383 | ldx [%l7], %l5 |
| 384 | ldx [%l7], %l5 |
| 385 | !# fmuld %f0, %f2, %f4 |
| 386 | !# add %l0, 0x1efe, %l0 |
| 387 | !# xor %l1, %l2, %l1 |
| 388 | |
| 389 | !stb %g4,[%g5] |
| 390 | ldd [%l7], %f6 |
| 391 | fmuld %f0, %f2, %f4 |
| 392 | ldx [%l7], %l5 |
| 393 | !# add %l0, 0x1efe, %l0 |
| 394 | !# xor %l1, %l2, %l1 |
| 395 | |
| 396 | bpos %xcc,t62_start |
| 397 | !addcc %g1,-0xfff,%g1 |
| 398 | subcc %g1,1,%g1 |
| 399 | setx t62_perf_cnt,%g1,%g2 |
| 400 | rd %pic,%g1; |
| 401 | stx %g1,[%g2]; |
| 402 | EXIT_GOOD |
| 403 | |
| 404 | ! |
| 405 | ! Thread 7 Start |
| 406 | ! |
| 407 | ! |
| 408 | main_th_63: |
| 409 | TEST |
| 410 | |
| 411 | setx 0x712345000, %g7, %l0 ! bits [16:8] selects index in 4 bank mode |
| 412 | setx 0x723456040, %g7, %l1 |
| 413 | setx 0x734567080, %g7, %l2 |
| 414 | setx 0x7456780c0, %g7, %l3 |
| 415 | setx 0x756789100, %g7, %l4 |
| 416 | setx 0x76789a140, %g7, %l5 |
| 417 | setx 0x7789ab180, %g7, %l6 |
| 418 | setx 0x789abc1c0, %g7, %l7 |
| 419 | |
| 420 | setx NUM_LOOP_TH7, %i0, %o1 |
| 421 | loop_th63: |
| 422 | !Bank0 |
| 423 | ld [%l0], %i1 !ld miss |
| 424 | ld [%l0+0x8], %i2 !ld hit |
| 425 | st %g0, [%l0+0x200] !st miss |
| 426 | st %g0, [%l0+0x208] !st hit |
| 427 | |
| 428 | !Bank1 |
| 429 | ld [%l1], %i1 !ld miss |
| 430 | ld [%l1+0x8], %i2 !ld hit |
| 431 | st %g0, [%l1+0x200] !st miss |
| 432 | st %g0, [%l1+0x208] !st hit |
| 433 | |
| 434 | !Bank2 |
| 435 | ld [%l2], %i1 !ld miss |
| 436 | ld [%l2+0x8], %i2 !ld hit |
| 437 | st %g0, [%l2+0x200] !st miss |
| 438 | st %g0, [%l2+0x208] !st hit |
| 439 | |
| 440 | !Bank3 |
| 441 | ld [%l3], %i1 !ld miss |
| 442 | ld [%l3+0x8], %i2 !ld hit |
| 443 | st %g0, [%l3+0x200] !st miss |
| 444 | st %g0, [%l3+0x208] !st hit |
| 445 | |
| 446 | !Bank4 |
| 447 | ld [%l4], %i1 !ld miss |
| 448 | ld [%l4+0x8], %i2 !ld hit |
| 449 | st %g0, [%l4+0x200] !st miss |
| 450 | st %g0, [%l4+0x208] !st hit |
| 451 | |
| 452 | !Bank5 |
| 453 | ld [%l5], %i1 !ld miss |
| 454 | ld [%l5+0x8], %i2 !ld hit |
| 455 | st %g0, [%l5+0x200] !st miss |
| 456 | st %g0, [%l5+0x208] !st hit |
| 457 | |
| 458 | !Bank6 |
| 459 | ld [%l6], %i1 !ld miss |
| 460 | ld [%l6+0x8], %i2 !ld hit |
| 461 | st %g0, [%l6+0x200] !st miss |
| 462 | st %g0, [%l6+0x208] !st hit |
| 463 | |
| 464 | !Bank7 |
| 465 | ld [%l7], %i1 !ld miss |
| 466 | ld [%l7+0x8], %i2 !ld hit |
| 467 | st %g0, [%l7+0x200] !st miss |
| 468 | st %g0, [%l7+0x208] !st hit |
| 469 | |
| 470 | |
| 471 | add %l0, 0x400, %l0 |
| 472 | add %l1, 0x400, %l1 |
| 473 | add %l2, 0x400, %l2 |
| 474 | add %l3, 0x400, %l3 |
| 475 | add %l4, 0x400, %l4 |
| 476 | add %l5, 0x400, %l5 |
| 477 | add %l6, 0x400, %l6 |
| 478 | add %l7, 0x400, %l7 |
| 479 | |
| 480 | |
| 481 | dec %o1 |
| 482 | cmp %o1, 0 |
| 483 | bne %xcc, loop_th63 |
| 484 | nop |
| 485 | |
| 486 | EXIT_GOOD |
| 487 | !================================================================================================= |
| 488 | fail_t63_1: |
| 489 | set 0x1,%g2; |
| 490 | ba fail_t63; |
| 491 | nop; |
| 492 | fail_t63_2: |
| 493 | set 0x2,%g2; |
| 494 | ba fail_t63; |
| 495 | nop; |
| 496 | fail_t63_3: |
| 497 | set 0x3,%g2; |
| 498 | ba fail_t63; |
| 499 | nop; |
| 500 | fail_t63_4: |
| 501 | set 0x4,%g2; |
| 502 | ba fail_t63; |
| 503 | nop; |
| 504 | fail_t63_5: |
| 505 | set 0x5,%g2; |
| 506 | ba fail_t63; |
| 507 | nop; |
| 508 | fail_t63_6: |
| 509 | set 0x6,%g2; |
| 510 | ba fail_t63; |
| 511 | nop; |
| 512 | fail_t63_7: |
| 513 | set 0x7,%g2; |
| 514 | ba fail_t63; |
| 515 | nop; |
| 516 | fail_t63_8: |
| 517 | set 0x8,%g2; |
| 518 | ba fail_t63; |
| 519 | nop; |
| 520 | fail_t63_9: |
| 521 | set 0x9,%g2; |
| 522 | ba fail_t63; |
| 523 | nop; |
| 524 | fail_t63_10: |
| 525 | set 0xa,%g2; |
| 526 | ba fail_t63; |
| 527 | nop; |
| 528 | fail_t63_11: |
| 529 | set 0xb,%g2; |
| 530 | ba fail_t63; |
| 531 | nop; |
| 532 | fail_t63_12: |
| 533 | set 0xc,%g2; |
| 534 | ba fail_t63; |
| 535 | nop; |
| 536 | fail_t63_13: |
| 537 | set 0xd,%g2; |
| 538 | ba fail_t63; |
| 539 | nop; |
| 540 | fail_t63_14: |
| 541 | set 0xe,%g2; |
| 542 | ba fail_t63; |
| 543 | nop; |
| 544 | fail_t63_15: |
| 545 | set 0xf,%g2; |
| 546 | ba fail_t63; |
| 547 | nop; |
| 548 | fail_t63_16: |
| 549 | set 0x10,%g2; |
| 550 | ba fail_t63; |
| 551 | nop; |
| 552 | fail_t63: |
| 553 | setx t63_fail,%g3,%g1 |
| 554 | stx %g2,[%g1] |
| 555 | EXIT_BAD |
| 556 | |
| 557 | /************************************************************************ |
| 558 | Test case data start |
| 559 | ************************************************************************/ |
| 560 | .data |
| 561 | |
| 562 | t56_data_area: |
| 563 | .skip 16384 |
| 564 | |
| 565 | t57_data_area: |
| 566 | .skip 16384 |
| 567 | .skip 16 |
| 568 | |
| 569 | t58_data_area: |
| 570 | .skip 16384 |
| 571 | .skip 16 |
| 572 | |
| 573 | t59_data_area: |
| 574 | .skip 16384 |
| 575 | .skip 16 |
| 576 | |
| 577 | t60_data_area: |
| 578 | .skip 16384 |
| 579 | .skip 16 |
| 580 | |
| 581 | t61_data_area: |
| 582 | .skip 16384 |
| 583 | .skip 16 |
| 584 | |
| 585 | t62_data_area: |
| 586 | .skip 16384 |
| 587 | .skip 16 |
| 588 | |
| 589 | t63_data_area: |
| 590 | .align 16 |
| 591 | !# A operand, 32 doublewords |
| 592 | !# %l7 points to here: |
| 593 | .xword 0xb61e0f74d889169f !# a[0] for 3 |
| 594 | .xword 0xeb7dad6d2db34663 !# a[1] for 3 |
| 595 | .xword 0x000000069fad6615 !# a[2] for 3 |
| 596 | .xword 0x0 !# a[3] for 3 |
| 597 | .xword 0x0 !# a[4] for 3 |
| 598 | .xword 0x0 !# a[5] for 3 |
| 599 | .xword 0x0 !# a[6] for 3 |
| 600 | .xword 0x0 !# a[7] for 3 |
| 601 | |
| 602 | .xword 0x85587F96342B939A |
| 603 | .xword 0x00DD7AAD15E30EB1 |
| 604 | .xword 0xFFFFEEEE00006000 |
| 605 | .xword 0xFFFFEEEE00007000 |
| 606 | .xword 0x222D15F21092A854 |
| 607 | .xword 0xFFFFEEEE00009000 |
| 608 | .xword 0xFD2CB924281A7FB1 |
| 609 | .xword 0xFFFFEEEE0000B000 |
| 610 | |
| 611 | .xword 0x12D7C16982229DCF |
| 612 | .xword 0xA75C18D599E04451 |
| 613 | .xword 0xA3BE82C81B280E9D |
| 614 | .xword 0x8964B57FD2745FFB |
| 615 | .xword 0x4103465563EB1347 |
| 616 | .xword 0xB4181F76C7A2CE01 |
| 617 | .xword 0xFFFFFFFF10005000 |
| 618 | .xword 0x4AC14D5A55D9D2BD |
| 619 | |
| 620 | !#.xword 0x9711E4D4E862AFA7 |
| 621 | .xword 0x2313258847A86E70 |
| 622 | .xword 0x47A084C3801DE4F9 |
| 623 | .xword 0x6B655B6A27D64052 |
| 624 | .xword 0x48CBC2665D6D8BB8 |
| 625 | .xword 0xD60A8BF421AA5DC8 |
| 626 | .xword 0xF4529D511F583B2D |
| 627 | .xword 0xFFFFFFFF1000D000 |
| 628 | .xword 0x27A0C706E2B783D4 |
| 629 | |
| 630 | !# m[0] starts here |
| 631 | .xword 0x00004FFF0000FFFF !# |
| 632 | .xword 0x0FFF8000FFFF0001 !# |
| 633 | .xword 0xF000FFFF0000FF00 !# |
| 634 | .xword 0x0000FFFF0000FF00 !# |
| 635 | .xword 0x1A890F27A74D6D4F !# |
| 636 | .xword 0xB34C93D130DF03BC !# |
| 637 | .xword 0xFD33BC46D2B25B52 !# |
| 638 | .xword 0x0FFFFFFF00006000 !# |
| 639 | |
| 640 | .xword 0x9000111122223333 |
| 641 | .xword 0x4444555566667777 |
| 642 | .xword 0xFFFFEEEE00006000 |
| 643 | .xword 0xFFFFEEEE00007000 |
| 644 | .xword 0x222D15F21092A854 |
| 645 | .xword 0xFFFFEEEE00009000 |
| 646 | .xword 0xFD2CB924281A7FB1 |
| 647 | .xword 0xFFFFEEEE0000B000 |
| 648 | |
| 649 | .xword 0x0000111122223333 |
| 650 | .xword 0x0000111122223333 |
| 651 | .xword 0x0000111122223333 |
| 652 | .xword 0x0000111122223333 |
| 653 | .xword 0x0000111122223333 |
| 654 | .xword 0x0000111122223333 |
| 655 | .xword 0x0000111122223333 |
| 656 | .xword 0x0000111122223333 |
| 657 | |
| 658 | .xword 0x0000111122223333 |
| 659 | .xword 0x0000111122223333 |
| 660 | .xword 0xA000111122223333 |
| 661 | .xword 0x0000111122223333 |
| 662 | .xword 0x0000111122223333 |
| 663 | .xword 0x0000111122223333 |
| 664 | .xword 0x0000111122223333 |
| 665 | .xword 0xFFFFFFFF22223333 |
| 666 | |
| 667 | !# N operand, 32 doublewords |
| 668 | .xword 0x00000000000000c9 !# 3. n[0] |
| 669 | .xword 0x0000000000000000 !# 3. n[1] |
| 670 | .xword 0x0000000800000000 !# 3. n[2] |
| 671 | .xword 0x0 !# 3. n[3] |
| 672 | .xword 0x0 !# 3. n[4] |
| 673 | .xword 0x0 !# 3. n[5] |
| 674 | .xword 0x0 !# 3. n[6] |
| 675 | .xword 0x0 !# 3. n[7] |
| 676 | |
| 677 | .xword 0xFFFFFFFF00007000 |
| 678 | .xword 0xFFFFFFFF00008000 |
| 679 | .xword 0xFFFFFFFF00009000 |
| 680 | .xword 0xFFFFFFFF0000A000 |
| 681 | .xword 0xFFFFFFFF0000B000 |
| 682 | .xword 0xFFFFFFFF0000C000 |
| 683 | .xword 0xFAEDBEEF0000D000 |
| 684 | .xword 0xFFFFFFFF0000E000 |
| 685 | |
| 686 | .xword 0xFFFFFFFF0000F000 |
| 687 | .xword 0xFFFFFFFF10000000 |
| 688 | .xword 0xFFFFFFFF10001000 |
| 689 | .xword 0xFFFFFFFF10002000 |
| 690 | .xword 0xFFFFFFFF10003000 |
| 691 | .xword 0xFFFFFFFF10004000 |
| 692 | .xword 0xFFFFFFFF10005000 |
| 693 | .xword 0xFFFFFFFF10006000 |
| 694 | |
| 695 | .xword 0xFFFFFFFF10007000 |
| 696 | .xword 0xFFFFFFFF10008000 |
| 697 | .xword 0xFFFFFFFF10009000 |
| 698 | .xword 0xFFFFFFFF1000A000 |
| 699 | .xword 0xFFFFFFFF1000B000 |
| 700 | .xword 0xEFFFFFFF1000C000 |
| 701 | .xword 0xFFFFFFFF1000D000 |
| 702 | .xword 0xFFFFFFFF1000E000 |
| 703 | |
| 704 | !# E starts here |
| 705 | .xword 0xAAAAAAAAAAAAAAAA !# 3. e[0] |
| 706 | .xword 0xAAAAAAAAAAAAAAAA !# 3. e[1] |
| 707 | .xword 0x0000000AAAAAAAAA !# 3. e[2] |
| 708 | .xword 0x0 !# 3. e[3] |
| 709 | .xword 0x0 !# 3. e[4] |
| 710 | .xword 0x0 !# 3. e[5] |
| 711 | .xword 0x0 !# 3. e[6] |
| 712 | .xword 0x0 !# 3. e[7] |
| 713 | |
| 714 | .xword 0x0000111122223333 |
| 715 | .xword 0x0000111122223333 |
| 716 | .xword 0x0000111122223333 |
| 717 | .xword 0x0000111122223333 |
| 718 | .xword 0x0000111122223333 |
| 719 | .xword 0x0000111122223333 |
| 720 | .xword 0x0000111122223333 |
| 721 | .xword 0x0000111122223333 |
| 722 | |
| 723 | .xword 0x0000111122223333 |
| 724 | .xword 0x0000111122223333 |
| 725 | .xword 0x0000111122223333 |
| 726 | .xword 0x0000111122223333 |
| 727 | .xword 0x0000111122223333 |
| 728 | .xword 0x0000111122223333 |
| 729 | .xword 0x0000111122223333 |
| 730 | .xword 0x0000111122223333 |
| 731 | |
| 732 | .xword 0x0000111122223333 |
| 733 | .xword 0x0000111122223333 |
| 734 | .xword 0x0000111122223333 |
| 735 | .xword 0x0000111122223333 |
| 736 | .xword 0x0000111122223333 |
| 737 | .xword 0x0000111122223333 |
| 738 | .xword 0x0000111122223333 |
| 739 | .xword 0x0000111122223333 |
| 740 | |
| 741 | !# Initial X value |
| 742 | .xword 0xb61e0f74d889169f !# a[0] for 3 |
| 743 | .xword 0xeb7dad6d2db34663 !# a[1] for 3 |
| 744 | .xword 0x000000069fad6615 !# a[2] for 3 |
| 745 | !#.xword 0x0000001920000000 !# x[0] for 3 |
| 746 | !#.xword 0x0000000000000000 !# x[1] for 3 |
| 747 | !#.xword 0x0000000000000000 !# x[2] for 3 |
| 748 | .xword 0x0 !# x[3] for 3 |
| 749 | .xword 0x0 !# x[4] for 3 |
| 750 | .xword 0x0 !# x[5] for 3 |
| 751 | .xword 0x0 !# x[6] for 3 |
| 752 | .xword 0x0 !# x[7] for 3 |
| 753 | |
| 754 | t63_expected_x: |
| 755 | !# Expected X result starts here |
| 756 | .xword 0x9890891c6f7c2d0b !# 3. X[0] |
| 757 | .xword 0x8d0356cf2e263a36 !# 3. X[1] |
| 758 | .xword 0x000000074dc55ef7 !# 3. X[2] |
| 759 | |
| 760 | t63_div_area: |
| 761 | .xword 0x0011223344556677 !# junk area for divide wait loop operand storage |
| 762 | .skip 16 |
| 763 | |
| 764 | !================================================================================================ |
| 765 | !================================================================================================= |
| 766 | .align 65536 |
| 767 | !# Subtest 1 start |
| 768 | !# input data |
| 769 | cleartext_t63: |
| 770 | .xword 0x0011223344556677 |
| 771 | .xword 0x8899aabbccddeeff |
| 772 | .skip 16384 |
| 773 | |
| 774 | !# AES initial state (also where final state will be written) |
| 775 | .align 16 |
| 776 | aes_state_t63: |
| 777 | .xword 0x0001020304050607 |
| 778 | .xword 0x08090a0b0c0d0e0f |
| 779 | .xword 0x1011121314151617 |
| 780 | .xword 0x18191a1b1c1d1e1f |
| 781 | |
| 782 | !# expected ciphertext |
| 783 | ciphertext_t63: |
| 784 | .xword 0x8ea2b7ca516745bf |
| 785 | .xword 0xeafc49904b496089 |
| 786 | .skip 16384 |
| 787 | |
| 788 | !# temporary area for storing expected result |
| 789 | result_t63: |
| 790 | .xword 0xDEADBEEFDEADBEEF |
| 791 | .xword 0xDEADBEEFDEADBEEF |
| 792 | .skip 16384 |
| 793 | |
| 794 | !################################################ |
| 795 | !# CWQ data area, set aside 512 CW's worth |
| 796 | !# 512*8*8 = 32KB |
| 797 | .align 32*1024 |
| 798 | CWQ_BASE_t63: |
| 799 | .xword 0xAAAAAAAAAAAAAAA |
| 800 | .xword 0xAAAAAAAAAAAAAAA |
| 801 | .xword 0xAAAAAAAAAAAAAAA |
| 802 | .xword 0xAAAAAAAAAAAAAAA |
| 803 | .xword 0xAAAAAAAAAAAAAAA |
| 804 | .xword 0xAAAAAAAAAAAAAAA |
| 805 | .xword 0xAAAAAAAAAAAAAAA |
| 806 | .xword 0xAAAAAAAAAAAAAAA |
| 807 | .align 32*1024 |
| 808 | CWQ_LAST_t63: |
| 809 | .skip 16 |
| 810 | |
| 811 | !=================================================================================================1 |
| 812 | .global t63_fail |
| 813 | t63_fail: |
| 814 | .xword 0x0000000000000000 |
| 815 | !================================================================================================== |
| 816 | .global t56_t62_perf |
| 817 | .global t63_perf |
| 818 | .global t56_perf_cnt |
| 819 | .global t57_perf_cnt |
| 820 | .global t58_perf_cnt |
| 821 | .global t59_perf_cnt |
| 822 | .global t60_perf_cnt |
| 823 | .global t61_perf_cnt |
| 824 | .global t62_perf_cnt |
| 825 | .global t63_perf_cnt |
| 826 | t56_t62_perf: |
| 827 | .xword 0x0000000017f85fe7 |
| 828 | t63_perf: |
| 829 | .xword 0x0000000057f99fe7 |
| 830 | t56_perf_cnt: |
| 831 | .xword 0x0000000000000000 |
| 832 | t57_perf_cnt: |
| 833 | .xword 0x0000000000000000 |
| 834 | t58_perf_cnt: |
| 835 | .xword 0x0000000000000000 |
| 836 | t59_perf_cnt: |
| 837 | .xword 0x0000000000000000 |
| 838 | t60_perf_cnt: |
| 839 | .xword 0x0000000000000000 |
| 840 | t61_perf_cnt: |
| 841 | .xword 0x0000000000000000 |
| 842 | t62_perf_cnt: |
| 843 | .xword 0x0000000000000000 |
| 844 | t63_perf_cnt: |
| 845 | .xword 0x0000000000000000 |
| 846 | .skip 16 |
| 847 | !================================================================================================== |
| 848 | .align 256 * 1024 |
| 849 | t56_blk_area: |
| 850 | .xword 0x00ffffffffffffff |
| 851 | .xword 0xffffffffffffffff |
| 852 | .xword 0xffffffffffffffff |
| 853 | .xword 0xffffffffffffffff |
| 854 | .xword 0xffffffffffffffff |
| 855 | .xword 0xffffffffffffffff |
| 856 | .xword 0xffffffffffffffff |
| 857 | .xword 0xffffffffffffffff |
| 858 | .xword 0xffffffffffffffff |
| 859 | .xword 0xffffffffffffffff |
| 860 | .xword 0xffffffffffffffff |
| 861 | .xword 0xffffffffffffffff |
| 862 | .xword 0xffffffffffffffff |
| 863 | .xword 0xffffffffffffffff |
| 864 | .xword 0xffffffffffffffff |
| 865 | .xword 0xffffffffffffffff |
| 866 | .skip 64 |
| 867 | .align 256 * 1024 |
| 868 | t57_blk_area: |
| 869 | .xword 0x0100000000000000 |
| 870 | .xword 0x0000000000000000 |
| 871 | .xword 0x0000000000000000 |
| 872 | .xword 0x0000000000000000 |
| 873 | .xword 0x0000000000000000 |
| 874 | .xword 0x0000000000000000 |
| 875 | .xword 0x0000000000000000 |
| 876 | .xword 0x0000000000000000 |
| 877 | .xword 0x0000000000000000 |
| 878 | .xword 0x0000000000000000 |
| 879 | .xword 0x0000000000000000 |
| 880 | .xword 0x0000000000000000 |
| 881 | .xword 0x0000000000000000 |
| 882 | .xword 0x0000000000000000 |
| 883 | .xword 0x0000000000000000 |
| 884 | .xword 0x0000000000000000 |
| 885 | .skip 64 |
| 886 | .align 256 * 1024 |
| 887 | t58_blk_area: |
| 888 | .xword 0x02ffffffffffffff |
| 889 | .xword 0xffffffffffffffff |
| 890 | .xword 0xffffffffffffffff |
| 891 | .xword 0xffffffffffffffff |
| 892 | .xword 0xffffffffffffffff |
| 893 | .xword 0xffffffffffffffff |
| 894 | .xword 0xffffffffffffffff |
| 895 | .xword 0xffffffffffffffff |
| 896 | .xword 0xffffffffffffffff |
| 897 | .xword 0xffffffffffffffff |
| 898 | .xword 0xffffffffffffffff |
| 899 | .xword 0xffffffffffffffff |
| 900 | .xword 0xffffffffffffffff |
| 901 | .xword 0xffffffffffffffff |
| 902 | .xword 0xffffffffffffffff |
| 903 | .xword 0xffffffffffffffff |
| 904 | .skip 64 |
| 905 | .align 256 * 1024 |
| 906 | t59_blk_area: |
| 907 | .xword 0x0300000000000000 |
| 908 | .xword 0x0000000000000000 |
| 909 | .xword 0x0000000000000000 |
| 910 | .xword 0x0000000000000000 |
| 911 | .xword 0x0000000000000000 |
| 912 | .xword 0x0000000000000000 |
| 913 | .xword 0x0000000000000000 |
| 914 | .xword 0x0000000000000000 |
| 915 | .xword 0x0000000000000000 |
| 916 | .xword 0x0000000000000000 |
| 917 | .xword 0x0000000000000000 |
| 918 | .xword 0x0000000000000000 |
| 919 | .xword 0x0000000000000000 |
| 920 | .xword 0x0000000000000000 |
| 921 | .xword 0x0000000000000000 |
| 922 | .xword 0x0000000000000000 |
| 923 | .skip 64 |
| 924 | .align 256 * 1024 |
| 925 | t60_blk_area: |
| 926 | .xword 0x04ffffffffffffff |
| 927 | .xword 0xffffffffffffffff |
| 928 | .xword 0xffffffffffffffff |
| 929 | .xword 0xffffffffffffffff |
| 930 | .xword 0xffffffffffffffff |
| 931 | .xword 0xffffffffffffffff |
| 932 | .xword 0xffffffffffffffff |
| 933 | .xword 0xffffffffffffffff |
| 934 | .xword 0xffffffffffffffff |
| 935 | .xword 0xffffffffffffffff |
| 936 | .xword 0xffffffffffffffff |
| 937 | .xword 0xffffffffffffffff |
| 938 | .xword 0xffffffffffffffff |
| 939 | .xword 0xffffffffffffffff |
| 940 | .xword 0xffffffffffffffff |
| 941 | .xword 0xffffffffffffffff |
| 942 | .skip 64 |
| 943 | .align 256 * 1024 |
| 944 | t61_blk_area: |
| 945 | .xword 0x0500000000000000 |
| 946 | .xword 0x0000000000000000 |
| 947 | .xword 0x0000000000000000 |
| 948 | .xword 0x0000000000000000 |
| 949 | .xword 0x0000000000000000 |
| 950 | .xword 0x0000000000000000 |
| 951 | .xword 0x0000000000000000 |
| 952 | .xword 0x0000000000000000 |
| 953 | .xword 0x0000000000000000 |
| 954 | .xword 0x0000000000000000 |
| 955 | .xword 0x0000000000000000 |
| 956 | .xword 0x0000000000000000 |
| 957 | .xword 0x0000000000000000 |
| 958 | .xword 0x0000000000000000 |
| 959 | .xword 0x0000000000000000 |
| 960 | .xword 0x0000000000000000 |
| 961 | .skip 64 |
| 962 | .align 256 * 1024 |
| 963 | t62_blk_area: |
| 964 | .xword 0x06ffffffffffffff |
| 965 | .xword 0xffffffffffffffff |
| 966 | .xword 0xffffffffffffffff |
| 967 | .xword 0xffffffffffffffff |
| 968 | .xword 0xffffffffffffffff |
| 969 | .xword 0xffffffffffffffff |
| 970 | .xword 0xffffffffffffffff |
| 971 | .xword 0xffffffffffffffff |
| 972 | .xword 0xffffffffffffffff |
| 973 | .xword 0xffffffffffffffff |
| 974 | .xword 0xffffffffffffffff |
| 975 | .xword 0xffffffffffffffff |
| 976 | .xword 0xffffffffffffffff |
| 977 | .xword 0xffffffffffffffff |
| 978 | .xword 0xffffffffffffffff |
| 979 | .xword 0xffffffffffffffff |
| 980 | .skip 64 |
| 981 | .align 256 * 1024 |
| 982 | t63_blk_area: |
| 983 | .xword 0x0700000000000000 |
| 984 | .xword 0x0000000000000000 |
| 985 | .xword 0x0000000000000000 |
| 986 | .xword 0x0000000000000000 |
| 987 | .xword 0x0000000000000000 |
| 988 | .xword 0x0000000000000000 |
| 989 | .xword 0x0000000000000000 |
| 990 | .xword 0x0000000000000000 |
| 991 | .xword 0x0000000000000000 |
| 992 | .xword 0x0000000000000000 |
| 993 | .xword 0x0000000000000000 |
| 994 | .xword 0x0000000000000000 |
| 995 | .xword 0x0000000000000000 |
| 996 | .xword 0x0000000000000000 |
| 997 | .xword 0x0000000000000000 |
| 998 | .xword 0x0000000000000000 |
| 999 | .skip 64 |