| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: system_init.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #ifdef SEND_BOOT_TRACE_TO_SSI |
| 39 | |
| 40 | #define BOOT_TRACE_TO_SSI dec %i2; stb %i2, [%i1] |
| 41 | |
| 42 | #else |
| 43 | #define BOOT_TRACE_TO_SSI |
| 44 | #endif |
| 45 | |
| 46 | |
| 47 | |
| 48 | /* First, set the PEU SERDES PLL ratio, since that requires WMR |
| 49 | * which should be done prior to enabling caches */ |
| 50 | |
| 51 | #include "peu_set_serdes_pll_ratio.s" |
| 52 | |
| 53 | /* |
| 54 | * Set up PEU registers for dtm |
| 55 | */ |
| 56 | #ifdef DTM_ENABLED |
| 57 | #ifdef SEND_BOOT_TRACE_TO_SSI |
| 58 | set_address_ssi_boot_trace: |
| 59 | setx 0xfffff00000, %i0, %i1 |
| 60 | sub %g0, 1, %i2 |
| 61 | sth %i2, [%i1] |
| 62 | #endif |
| 63 | |
| 64 | programm_peu_reg_dtm: |
| 65 | #define PEU_IOMMU_CNTL_REG_ADDR 0x8800640000 |
| 66 | #define PEU_IOMMU_DATA 0x0000000000000002 |
| 67 | |
| 68 | #define PEU_SYMBOL_TIMER_REG_ADDR 0x88006e2078 |
| 69 | #define PEU_SYMBOL_TIMER_DATA 0x20 |
| 70 | |
| 71 | #define PEU_MAC_CTRL_REG_ADDR 0x88006e2060 |
| 72 | #define PEU_MAC_CTRL_REG_SCRAMBLE_MASK 0xfffffffffffffffd |
| 73 | #define PEU_MAC_CTRL_REG_SCRAMBLE_DATA 0x0000000000000002 |
| 74 | |
| 75 | setx PEU_IOMMU_DATA, %o1, %g4 |
| 76 | setx PEU_IOMMU_CNTL_REG_ADDR, %o1, %g2 |
| 77 | stx %g4, [%g2] |
| 78 | nop |
| 79 | |
| 80 | ! Disable scrambling so that peu_mio_debug_txdata is meaningful. |
| 81 | programm_peu_scrambling_reg_dtm: |
| 82 | setx PEU_MAC_CTRL_REG_ADDR, %o1, %g2 |
| 83 | setx PEU_MAC_CTRL_REG_SCRAMBLE_MASK, %o1, %g4 |
| 84 | ldx [%g2], %o1 |
| 85 | and %o1, %g4, %g3 |
| 86 | setx PEU_MAC_CTRL_REG_SCRAMBLE_DATA, %o1, %g4 |
| 87 | or %g3, %g4, %g4 |
| 88 | stx %g4, [%g2] |
| 89 | |
| 90 | |
| 91 | #include "peu_init_dtm.h" |
| 92 | end_programm_peu_dtm: |
| 93 | #endif |
| 94 | ! end of ifdef DTM_ENABLED |
| 95 | |
| 96 | |
| 97 | |
| 98 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 99 | ! Configure L2-cache |
| 100 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 101 | #ifdef L2_REG_PROG |
| 102 | BOOT_TRACE_TO_SSI |
| 103 | system_init_l2_prog: |
| 104 | setx cregs_l2_ctl_reg_r64, %g2, %l1 |
| 105 | mov 0xa9, %g2 |
| 106 | sllx %g2, 32, %g2 |
| 107 | #ifdef BANK01 |
| 108 | stx %l1, [%g2 + 0x000] |
| 109 | stx %l1, [%g2 + 0x040] |
| 110 | #endif |
| 111 | #ifdef BANK23 |
| 112 | stx %l1, [%g2 + 0x080] |
| 113 | stx %l1, [%g2 + 0x0c0] |
| 114 | #endif |
| 115 | #ifdef BANK45 |
| 116 | stx %l1, [%g2 + 0x100] |
| 117 | stx %l1, [%g2 + 0x140] |
| 118 | #endif |
| 119 | #ifdef BANK67 |
| 120 | stx %l1, [%g2 + 0x180] |
| 121 | stx %l1, [%g2 + 0x1c0] |
| 122 | #endif |
| 123 | #ifndef SET_L2_ERROR_EN_REG |
| 124 | #define SET_L2_ERROR_EN_REG 1 |
| 125 | #endif /* SET_L2_ERROR_EN_REG */ |
| 126 | #endif /* L2_REG_PROG */ |
| 127 | |
| 128 | |
| 129 | #if SET_L2_ERROR_EN_REG |
| 130 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 131 | ! L2_ERROR_EN_REG ( bit 0 is CEEN, bit 1 is NCEEN ) |
| 132 | ! |
| 133 | ! Errors are always logged in the L2_ERROR_STATUS_REG |
| 134 | ! and L2_ERROR_ADDRESS_REG regardless of the setting of the CEEN and |
| 135 | ! NCEEN bits in L2_ERROR_EN_REG. |
| 136 | ! L2_ERROR_EN_REG only controls whether or not the error is reported back |
| 137 | ! to the appropriate virtual core. |
| 138 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 139 | BOOT_TRACE_TO_SSI |
| 140 | ! enable l2 error trap |
| 141 | system_init_set_l2_error_en_reg: |
| 142 | setx cregs_l2_error_en_reg_r64, %g2, %l1 |
| 143 | mov 0xaa, %g2 |
| 144 | sllx %g2, 32, %g2 |
| 145 | #ifdef BANK01 |
| 146 | stx %l1, [%g2 + 0x000] |
| 147 | stx %l1, [%g2 + 0x040] |
| 148 | #endif |
| 149 | #ifdef BANK23 |
| 150 | stx %l1, [%g2 + 0x080] |
| 151 | stx %l1, [%g2 + 0x0c0] |
| 152 | #endif |
| 153 | #ifdef BANK45 |
| 154 | stx %l1, [%g2 + 0x100] |
| 155 | stx %l1, [%g2 + 0x140] |
| 156 | #endif |
| 157 | #ifdef BANK67 |
| 158 | stx %l1, [%g2 + 0x180] |
| 159 | stx %l1, [%g2 + 0x1c0] |
| 160 | #endif |
| 161 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 162 | #endif /* SET_L2_ERROR_EN_REG */ |
| 163 | |
| 164 | |
| 165 | !! L2 should be enabled by now, lets get l1 enabled. |
| 166 | #if (CREGS_L2_CTL_REG_DIS == 0) |
| 167 | system_init_enable_l1: |
| 168 | mov (CREGS_LSU_CTL_REG_DC << 1 | CREGS_LSU_CTL_REG_IC), %g2 |
| 169 | stxa %g2, [%g0] 0x45 |
| 170 | #endif |
| 171 | |
| 172 | |
| 173 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 174 | !!Debug port programming for modes |
| 175 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 176 | #ifdef DEBUG_SOC_OBS |
| 177 | system_init_enable_debug_soc_obs: |
| 178 | mov 0x86, %g2 |
| 179 | sllx %g2, 32, %g2 |
| 180 | mov 0x1, %l1 |
| 181 | stx %l1, [%g2] |
| 182 | #endif |
| 183 | |
| 184 | #ifdef DEBUG_SOC_CUS |
| 185 | system_init_enable_debug_soc_cus: |
| 186 | mov 0x86, %g2 |
| 187 | sllx %g2, 32, %g2 |
| 188 | setx DEBUG_SOC_CUS, %l2, %l1 |
| 189 | stx %l1, [%g2] |
| 190 | #endif |
| 191 | |
| 192 | #ifdef DEBUG_SOC_RAND |
| 193 | system_init_enable_debug_soc_rand: |
| 194 | mov 0x86, %g2 |
| 195 | sllx %g2, 32, %g2 |
| 196 | setx TG_SEED, %l2, %l1 |
| 197 | or %l1, 0x1, %l1 |
| 198 | stx %l1, [%g2] |
| 199 | #endif |
| 200 | |
| 201 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 202 | !!Progam the SSI clock ratio io2clk/4 |
| 203 | !!system defaults to io2clk/8 |
| 204 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 205 | #ifdef SSI_CLK_4 |
| 206 | system_init_program_ssi_clk_4: |
| 207 | #include "ncu_defines.h" |
| 208 | setx NCU_SCKSEL, %l2, %l1 |
| 209 | mov 0x1, %l2 |
| 210 | stx %l2, [%l1] |
| 211 | #endif |
| 212 | |
| 213 | #ifdef SSI_CLK_8_2 |
| 214 | system_init_program_ssi_clk_8_2: |
| 215 | #include "ncu_defines.h" |
| 216 | setx NCU_SCKSEL, %l2, %l1 |
| 217 | mov 0x2, %l2 |
| 218 | stx %l2, [%l1] |
| 219 | #endif |
| 220 | |
| 221 | #ifdef SSI_CLK_8_3 |
| 222 | system_init_program_ssi_clk_8_3: |
| 223 | #include "ncu_defines.h" |
| 224 | setx NCU_SCKSEL, %l2, %l1 |
| 225 | mov 0x3, %l2 |
| 226 | stx %l2, [%l1] |
| 227 | #endif |
| 228 | |
| 229 | ! *************************************************************** |
| 230 | ! PCI Express Link Training included here for the master thread |
| 231 | ! to execute if desired by the diag (non DTM mode version) |
| 232 | ! *************************************************************** |
| 233 | #ifndef DTM_ENABLED |
| 234 | #if defined(ENABLE_PCIE_LINK_TRAINING) || defined(FC_NO_PEU_VERA) |
| 235 | #include "peu_init.h" |
| 236 | #endif |
| 237 | #endif |
| 238 | |
| 239 | ! *************************************************************** |
| 240 | ! NIU initialization included here for the master thread to execute |
| 241 | ! |
| 242 | ! *************************************************************** |
| 243 | #if defined(TX_TEST) || defined(RX_TEST) |
| 244 | |
| 245 | #ifndef FC_NO_NIU_T2 |
| 246 | #include "niu_defines.h" |
| 247 | call N2_NIU_INIT |
| 248 | nop |
| 249 | ba system_init_N2_NIU_Basic_init_done |
| 250 | nop |
| 251 | #include "niu_init.h" |
| 252 | #endif |
| 253 | |
| 254 | system_init_N2_NIU_Basic_init_done: |
| 255 | nop |
| 256 | #endif |
| 257 | |
| 258 | #ifdef CREGS_TICK_ENABLE |
| 259 | BOOT_TRACE_TO_SSI |
| 260 | system_init_enable_tick: |
| 261 | ! Tick-enable is chip level .. |
| 262 | mov CREGS_TICK_ENABLE, %g2 |
| 263 | mov 0x38, %g3 |
| 264 | stxa %g2, [%g3]0x41 |
| 265 | #endif |
| 266 | |
| 267 | #if ENABLE_INTR0x60 |
| 268 | #include "interrupt0x60_sys_init.s" |
| 269 | #endif /* ENABLE_INTR0x60 */ |