| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: PCIeEgrDPeDrainState.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define ENABLE_PCIE_LINK_TRAINING |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | #ifndef PCIE_USE_SSYS_RESET |
| 41 | #define RESET_STAT_CHECK |
| 42 | #define RESET_CHECK_REG |
| 43 | #define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler |
| 44 | #endif |
| 45 | |
| 46 | #define H_HT0_Data_access_error_0x32 |
| 47 | #define SUN_H_HT0_Data_access_error_0x32 \ |
| 48 | inc %l4; \ |
| 49 | done; |
| 50 | |
| 51 | #include "hboot.s" |
| 52 | #include "peu_defines.h" |
| 53 | #include "dmu_peu_regs.h" |
| 54 | #include "rst_defines.h" |
| 55 | |
| 56 | #define MEM_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) |
| 57 | #define DMA_DATA_ADDR 0x0000000123456000 |
| 58 | #define DMARD_ADDR1 0xfffc000123456000 |
| 59 | #define DMARD_ADDR2 0xfffc000123457000 |
| 60 | #define DMARD_ADDR3 0xfffc000123458000 |
| 61 | #define DMARD_ADDR4 0xfffc000123459000 |
| 62 | |
| 63 | /* |
| 64 | Test case code start |
| 65 | */ |
| 66 | .text |
| 67 | .global main |
| 68 | |
| 69 | main: |
| 70 | ta T_CHANGE_HPRIV |
| 71 | nop |
| 72 | |
| 73 | /************************************************************ |
| 74 | Check if this is the first time thru here |
| 75 | ************************************************************/ |
| 76 | setx test_entered, %g1, %g2 |
| 77 | ldx [%g2], %g3 |
| 78 | #ifdef PCIE_USE_SSYS_RESET |
| 79 | brnz %g3, test_failed ! test should only be one-pass |
| 80 | #else |
| 81 | brnz %g3, After_Warm_Reset |
| 82 | #endif |
| 83 | nop |
| 84 | |
| 85 | ! First time thru, Store a non-zero value there |
| 86 | dec %g3 |
| 87 | stx %g3, [%g2] |
| 88 | |
| 89 | /************************************************************ |
| 90 | make sure the detect.quiet bit is set |
| 91 | ************************************************************/ |
| 92 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3 |
| 93 | ldx [%g3], %g4 |
| 94 | mov 0x100, %g5 |
| 95 | orcc %g5, %g4, %g5 ! OR in bit 8 == 1 |
| 96 | stx %g5, [%g3] |
| 97 | ldx [%g3], %g4 |
| 98 | |
| 99 | /************************************************************ |
| 100 | Fire off some PIOs and DMA Reads, then bring down the link. |
| 101 | ************************************************************/ |
| 102 | Start_PIOs_and_DMARDs: |
| 103 | setx MEM_WR_ADDR, %g1, %g2 |
| 104 | setx 0x3335373992828384, %g1, %l0 |
| 105 | stb %l0, [%g2] |
| 106 | sth %l0, [%g2 + 4] |
| 107 | stw %l0, [%g2 + 8] |
| 108 | ldx [%g2], %l1 |
| 109 | |
| 110 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3 |
| 111 | ldx [%g3], %l3 |
| 112 | stx %l3, [%g3] ! clear any OE status bits |
| 113 | |
| 114 | /*************************************************************** |
| 115 | Write the EDI_PAR and EDI_TRG fields of the ILU DIAGNOSTIC CSR |
| 116 | ***************************************************************/ |
| 117 | nop; nop; nop; nop; |
| 118 | ! This user event will force the next PIO to NOT to call expectPCIE(). |
| 119 | ! $EV trig_pc_d(1,@VA(.MAIN.Bring_down_the_link)) -> EnablePCIeIgCmd("PIO_NULLIFY",0,0,0,1) |
| 120 | Bring_down_the_link: |
| 121 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g4 |
| 122 | ldx [%g4], %l3 |
| 123 | best_set_reg(0x00001020, %g1, %l4) ! set bits 12 & 5 (EDI_PAR & EDI_TRG) |
| 124 | or %l3, %l4, %l3 |
| 125 | stx %l3, [%g4] ! set the EDP error injection triggers |
| 126 | |
| 127 | |
| 128 | stx %l0, [%g2 + 16] ! PIO write ===> should get the EDP error |
| 129 | |
| 130 | |
| 131 | ! now wait for "Egress Data Parity Error (EDP)" primary or secondary status to be set |
| 132 | mov 10, %l0 |
| 133 | setx 0x0000200000002000, %g1, %l1 ! mask for EDP Primary and Secondary Events |
| 134 | Wait_for_EDP: |
| 135 | ldx [%g3], %l3 |
| 136 | andcc %l1, %l3, %l4 |
| 137 | bne %xcc, Check_drain_state |
| 138 | nop |
| 139 | dec %l0 |
| 140 | brnz %l0, Wait_for_EDP |
| 141 | nop |
| 142 | b test_failed |
| 143 | nop |
| 144 | |
| 145 | /************************************************************ |
| 146 | check that drain.state bit is set in the PEU Status Register |
| 147 | ************************************************************/ |
| 148 | Check_drain_state: |
| 149 | |
| 150 | ! This user event will force the next PIO to NOT to call expectPCIE(). |
| 151 | ! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1) |
| 152 | |
| 153 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g3 |
| 154 | ldx [%g3], %g4 |
| 155 | mov 0x100, %g5 |
| 156 | andcc %g4, %g5, %l0 |
| 157 | bz test_failed ! branch if drain state is not set |
| 158 | nop |
| 159 | |
| 160 | ! issue PIO read request(s) - these should complete with Bus Error |
| 161 | mov 0, %l4 |
| 162 | setx MEM_WR_ADDR, %g1, %g4 |
| 163 | PioBusErr: |
| 164 | ldx [%g4], %l3 ! ==> this should get a bus error |
| 165 | |
| 166 | dec %l4 ! <== only one interrupt expected |
| 167 | brnz %l4, test_failed |
| 168 | |
| 169 | ! insure that no outstanding DMA read requests are outstanding |
| 170 | ! by checking that there are no entries on the Transaction Scoreboard |
| 171 | setx FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g5 |
| 172 | mov 0, %l0 |
| 173 | dec %l0 |
| 174 | mov 0x01, %l1 |
| 175 | xor %l1, %l0, %l1 |
| 176 | Wait_for_dma_read_clear: |
| 177 | ldx [%g5], %l4 |
| 178 | andcc %l4, %l1, %l2 |
| 179 | bnz Wait_for_dma_read_clear |
| 180 | |
| 181 | ! clear the link down bit |
| 182 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g2 |
| 183 | ldx [%g2], %l1 |
| 184 | stx %l1, [%g2] ! RW1C |
| 185 | ldx [%g2], %l1 |
| 186 | brnz %l1, test_failed ! branch if link down is not cleared |
| 187 | nop |
| 188 | |
| 189 | ! clear the drain bit - its also a RW1C bit |
| 190 | mov 0x100, %g5 |
| 191 | stx %g5, [%g3] ! RW1C |
| 192 | ldx [%g3], %g4 |
| 193 | andcc %g4, %g5, %g4 |
| 194 | bnz test_failed ! branch if drain state is not cleared |
| 195 | nop |
| 196 | |
| 197 | /************************************************************ |
| 198 | do the warm reset |
| 199 | ************************************************************/ |
| 200 | do_WARM_RESET: |
| 201 | ! xxx trig_pc_d(1,@VA(.MAIN.do_WARM_RESET)) -> EnablePCIeIgCmd("SOFTRESET",0,0,0,1) |
| 202 | #ifdef PCIE_USE_SSYS_RESET |
| 203 | setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg |
| 204 | mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data |
| 205 | stx %g7, [%g5] ! Subsystem Reset |
| 206 | |
| 207 | mov 10, %l0 ! loop timeout count |
| 208 | |
| 209 | Wait4SsysReset: |
| 210 | ldx [%g5], %l7 ! check if reset bit has cleared |
| 211 | brz %l7, redo_link_training |
| 212 | nop |
| 213 | dec %l0 |
| 214 | brnz %l0, Wait4SsysReset |
| 215 | nop |
| 216 | ba test_failed ! Subsystem reset should have completed |
| 217 | nop |
| 218 | /************************************************************ |
| 219 | Now redo link training... |
| 220 | ************************************************************/ |
| 221 | redo_link_training: |
| 222 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3 |
| 223 | ldx [%g3], %g4 |
| 224 | mov 0x0010, %g5 ! FAST LINK MODE, for simulation. |
| 225 | or %g4, %g5, %g5 |
| 226 | stx %g5, [%g3] |
| 227 | |
| 228 | ! clear bit 8, to not remain in Detect.Quiet state |
| 229 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3 |
| 230 | mov 0x001, %l4 |
| 231 | stx %l4, [%g3] |
| 232 | |
| 233 | ! enable bypass in IOMMU |
| 234 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 |
| 235 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 |
| 236 | stx %g3, [%g2] |
| 237 | |
| 238 | ! wait for the "Link Up" status bit to get set in the PEU |
| 239 | ! (this code copied from peu_init.h) |
| 240 | |
| 241 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3 |
| 242 | ldx [%g3], %l4 |
| 243 | stx %l4, [%g3] ! clear any status bits that are set |
| 244 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4 |
| 245 | mov 255, %l0 |
| 246 | mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1 |
| 247 | |
| 248 | LinkTrainingLoop2: |
| 249 | ldx [%g3], %l4 ! bit 8 is Link Up primary event |
| 250 | ldx [%g4], %l5 ! bits 48:44 are the LTSSM state |
| 251 | andcc %l1, %l4, %l4 |
| 252 | bne After_Warm_Reset |
| 253 | nop |
| 254 | |
| 255 | dec %l0 |
| 256 | brnz %l0, LinkTrainingLoop2 |
| 257 | nop |
| 258 | b test_failed |
| 259 | nop |
| 260 | #else |
| 261 | setx RST_RESET_GEN, %g1, %g5 ! warm reset reg |
| 262 | mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data |
| 263 | mov 25, %l0 ! loop timeout count |
| 264 | |
| 265 | stx %g7, [%g5] ! Warm Reset |
| 266 | ldx [%g5], %g7 |
| 267 | |
| 268 | Wait4WarmReset: |
| 269 | dec %l0 |
| 270 | brnz %l0, Wait4WarmReset |
| 271 | nop |
| 272 | ba test_failed ! Warm reset should have happened |
| 273 | nop |
| 274 | #endif |
| 275 | |
| 276 | /******************************************************************** |
| 277 | Do a couple of PIOs and DMAs to verify that the PCIe link is working. |
| 278 | ********************************************************************/ |
| 279 | After_Warm_Reset: |
| 280 | nop |
| 281 | ! clear any error bits from from the DLPL Status reg |
| 282 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6 |
| 283 | ldx [%g6], %l7 |
| 284 | stx %l7, [%g6] ! RW1C |
| 285 | ldx [%g6], %l7 |
| 286 | brnz %l7, test_failed ! branch if it is not cleared |
| 287 | nop |
| 288 | |
| 289 | DmaRd5: nop |
| 290 | ! $EV trig_pc_d(1, @VA(.MAIN.DmaRd5)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR2,DMARD_ADDR2,"64'h40",1) |
| 291 | setx MEM_WR_ADDR, %g1, %g5 |
| 292 | mov 0, %l4 |
| 293 | stx %g3, [%g5] ! 3 PIO Writes |
| 294 | stx %g4, [%g5+8] |
| 295 | stx %g5, [%g5+16] |
| 296 | DmaRd6: nop |
| 297 | ! $EV trig_pc_d(1, @VA(.MAIN.DmaRd6)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR3,DMARD_ADDR3,"64'h40",1) |
| 298 | ldx [%g5], %l0 ! 3 PIO Reads |
| 299 | ldx [%g5+8], %l1 |
| 300 | ldx [%g5+16], %l2 |
| 301 | |
| 302 | DmaRd7: nop |
| 303 | ! $EV trig_pc_d(1, @VA(.MAIN.DmaRd7)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR4,DMARD_ADDR4,"64'h40",1) |
| 304 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3 |
| 305 | ldx [%g3], %l5 ! bit 8 is Link Up primary event |
| 306 | |
| 307 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4 |
| 308 | ldx [%g4], %l6 ! bits 48:44 are the LTSSM state |
| 309 | |
| 310 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6 |
| 311 | ldx [%g6], %l7 ! dlpl status |
| 312 | |
| 313 | brnz %l4, test_failed ! no interrupts were expected |
| 314 | nop |
| 315 | nop |
| 316 | |
| 317 | test_passed: |
| 318 | EXIT_GOOD |
| 319 | |
| 320 | test_failed: |
| 321 | EXIT_BAD |
| 322 | |
| 323 | |
| 324 | /************************************************************************ |
| 325 | Test case data start |
| 326 | ************************************************************************/ |
| 327 | .align 64 |
| 328 | test_entered: |
| 329 | .xword 0 |
| 330 | |
| 331 | |
| 332 | SECTION .DATA DATA_VA=DMA_DATA_ADDR |
| 333 | attr_data { |
| 334 | Name = .DATA, |
| 335 | hypervisor, |
| 336 | compressimage |
| 337 | } |
| 338 | .data |
| 339 | init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004) |
| 340 | /************************************************************************/ |