| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: RegRdReset.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | #include "hboot.s" |
| 41 | #include "peu_defines.h" |
| 42 | #include "dmu_peu_regs.h" |
| 43 | |
| 44 | #ifndef NO_SELF_CHECK |
| 45 | #define BNE_TEST_FAIL bne test_failed |
| 46 | #else |
| 47 | #define BNE_TEST_FAIL nop |
| 48 | #endif |
| 49 | |
| 50 | /* |
| 51 | Test case code start |
| 52 | */ |
| 53 | .text |
| 54 | .global main |
| 55 | |
| 56 | main: |
| 57 | ta T_CHANGE_HPRIV |
| 58 | nop |
| 59 | |
| 60 | !setx N2_DMU_PEU_BASE_ADDR, %g1, %g7 |
| 61 | REG_TEST_0: |
| 62 | setx FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_0) + 8, 16, 16)) -> printf("\nRead REG_TEST_0\n") |
| 63 | !set FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_0) + 8, 16, 16)) -> printf("\nRead REG_TEST_0\n") |
| 64 | setx FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_POR_VALUE, %g1, %g3 |
| 65 | ldx [%g2], %g4 |
| 66 | xorcc %g3, %g4, %g5 |
| 67 | BNE_TEST_FAIL |
| 68 | nop |
| 69 | |
| 70 | REG_TEST_1: |
| 71 | setx FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_1) + 8, 16, 16)) -> printf("\nRead REG_TEST_1\n") |
| 72 | setx FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_POR_VALUE, %g1, %g3 |
| 73 | ldx [%g2], %g4 |
| 74 | xorcc %g3, %g4, %g5 |
| 75 | BNE_TEST_FAIL |
| 76 | nop |
| 77 | |
| 78 | REG_TEST_2: |
| 79 | setx FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_2) + 8, 16, 16)) -> printf("\nRead REG_TEST_2\n") |
| 80 | setx FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_POR_VALUE, %g1, %g3 |
| 81 | ldx [%g2], %g4 |
| 82 | xorcc %g3, %g4, %g5 |
| 83 | BNE_TEST_FAIL |
| 84 | nop |
| 85 | |
| 86 | REG_TEST_3: |
| 87 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_3) + 8, 16, 16)) -> printf("\nRead REG_TEST_3\n") |
| 88 | #ifdef DTM_ENABLED |
| 89 | setx FIRE_DLC_MMU_CSR_A_CTL_POR_VALUE+2, %g1, %g3 ! Bypass enable is set |
| 90 | #else |
| 91 | setx FIRE_DLC_MMU_CSR_A_CTL_POR_VALUE, %g1, %g3 |
| 92 | #endif |
| 93 | ldx [%g2], %g4 |
| 94 | xorcc %g3, %g4, %g5 |
| 95 | BNE_TEST_FAIL |
| 96 | nop |
| 97 | |
| 98 | REG_TEST_4: |
| 99 | setx FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_4) + 8, 16, 16)) -> printf("\nRead REG_TEST_4\n") |
| 100 | setx FIRE_DLC_MMU_CSR_A_TSB_POR_VALUE, %g1, %g3 |
| 101 | ldx [%g2], %g4 |
| 102 | xorcc %g3, %g4, %g5 |
| 103 | BNE_TEST_FAIL |
| 104 | nop |
| 105 | |
| 106 | REG_TEST_5: |
| 107 | setx FIRE_DLC_MMU_CSR_A_FSH_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_5) + 8, 16, 16)) -> printf("\nRead REG_TEST_5\n") |
| 108 | setx FIRE_DLC_MMU_CSR_A_FSH_POR_VALUE, %g1, %g3 |
| 109 | ldx [%g2], %g4 |
| 110 | xorcc %g3, %g4, %g5 |
| 111 | BNE_TEST_FAIL |
| 112 | nop |
| 113 | |
| 114 | REG_TEST_6: |
| 115 | setx FIRE_DLC_MMU_CSR_A_INV_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_6) + 8, 16, 16)) -> printf("\nRead REG_TEST_6\n") |
| 116 | setx FIRE_DLC_MMU_CSR_A_INV_POR_VALUE, %g1, %g3 |
| 117 | ldx [%g2], %g4 |
| 118 | xorcc %g3, %g4, %g5 |
| 119 | BNE_TEST_FAIL |
| 120 | nop |
| 121 | |
| 122 | REG_TEST_7: |
| 123 | setx FIRE_DLC_MMU_CSR_A_LOG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_7) + 8, 16, 16)) -> printf("\nRead REG_TEST_7\n") |
| 124 | setx FIRE_DLC_MMU_CSR_A_LOG_POR_VALUE, %g1, %g3 |
| 125 | ldx [%g2], %g4 |
| 126 | xorcc %g3, %g4, %g5 |
| 127 | BNE_TEST_FAIL |
| 128 | nop |
| 129 | |
| 130 | REG_TEST_8: |
| 131 | setx FIRE_DLC_MMU_CSR_A_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_8) + 8, 16, 16)) -> printf("\nRead REG_TEST_8\n") |
| 132 | setx FIRE_DLC_MMU_CSR_A_INT_EN_POR_VALUE, %g1, %g3 |
| 133 | ldx [%g2], %g4 |
| 134 | xorcc %g3, %g4, %g5 |
| 135 | BNE_TEST_FAIL |
| 136 | nop |
| 137 | |
| 138 | REG_TEST_9: |
| 139 | setx FIRE_DLC_MMU_CSR_A_EN_ERR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_9) + 8, 16, 16)) -> printf("\nRead REG_TEST_9\n") |
| 140 | setx FIRE_DLC_MMU_CSR_A_EN_ERR_POR_VALUE, %g1, %g3 |
| 141 | ldx [%g2], %g4 |
| 142 | xorcc %g3, %g4, %g5 |
| 143 | BNE_TEST_FAIL |
| 144 | nop |
| 145 | |
| 146 | REG_TEST_10: |
| 147 | setx FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_10) + 8, 16, 16)) -> printf("\nRead REG_TEST_10\n") |
| 148 | setx FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 149 | ldx [%g2], %g4 |
| 150 | xorcc %g3, %g4, %g5 |
| 151 | BNE_TEST_FAIL |
| 152 | nop |
| 153 | |
| 154 | REG_TEST_11: |
| 155 | setx FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_11) + 8, 16, 16)) -> printf("\nRead REG_TEST_11\n") |
| 156 | setx FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 157 | ldx [%g2], %g4 |
| 158 | xorcc %g3, %g4, %g5 |
| 159 | BNE_TEST_FAIL |
| 160 | nop |
| 161 | |
| 162 | REG_TEST_12: |
| 163 | setx FIRE_DLC_MMU_CSR_A_FLTA_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_12) + 8, 16, 16)) -> printf("\nRead REG_TEST_12\n") |
| 164 | setx FIRE_DLC_MMU_CSR_A_FLTA_POR_VALUE, %g1, %g3 |
| 165 | ldx [%g2], %g4 |
| 166 | xorcc %g3, %g4, %g5 |
| 167 | BNE_TEST_FAIL |
| 168 | nop |
| 169 | |
| 170 | REG_TEST_13: |
| 171 | setx FIRE_DLC_MMU_CSR_A_FLTS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_13) + 8, 16, 16)) -> printf("\nRead REG_TEST_13\n") |
| 172 | setx FIRE_DLC_MMU_CSR_A_FLTS_POR_VALUE, %g1, %g3 |
| 173 | ldx [%g2], %g4 |
| 174 | xorcc %g3, %g4, %g5 |
| 175 | BNE_TEST_FAIL |
| 176 | nop |
| 177 | |
| 178 | REG_TEST_14: |
| 179 | setx FIRE_DLC_MMU_CSR_A_PRFC_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_14) + 8, 16, 16)) -> printf("\nRead REG_TEST_14\n") |
| 180 | setx FIRE_DLC_MMU_CSR_A_PRFC_POR_VALUE, %g1, %g3 |
| 181 | ldx [%g2], %g4 |
| 182 | xorcc %g3, %g4, %g5 |
| 183 | BNE_TEST_FAIL |
| 184 | nop |
| 185 | |
| 186 | REG_TEST_15: |
| 187 | setx FIRE_DLC_MMU_CSR_A_PRF0_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_15) + 8, 16, 16)) -> printf("\nRead REG_TEST_15\n") |
| 188 | setx FIRE_DLC_MMU_CSR_A_PRF0_POR_VALUE, %g1, %g3 |
| 189 | ldx [%g2], %g4 |
| 190 | xorcc %g3, %g4, %g5 |
| 191 | BNE_TEST_FAIL |
| 192 | nop |
| 193 | |
| 194 | REG_TEST_16: |
| 195 | setx FIRE_DLC_MMU_CSR_A_PRF1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_16) + 8, 16, 16)) -> printf("\nRead REG_TEST_16\n") |
| 196 | setx FIRE_DLC_MMU_CSR_A_PRF1_POR_VALUE, %g1, %g3 |
| 197 | ldx [%g2], %g4 |
| 198 | xorcc %g3, %g4, %g5 |
| 199 | BNE_TEST_FAIL |
| 200 | nop |
| 201 | |
| 202 | REG_TEST_17: |
| 203 | setx FIRE_DLC_MMU_CSR_A_VTB_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_17) + 8, 16, 16)) -> printf("\nRead REG_TEST_17\n") |
| 204 | setx FIRE_DLC_MMU_CSR_A_VTB_POR_VALUE, %g1, %g3 |
| 205 | ldx [%g2], %g4 |
| 206 | xorcc %g3, %g4, %g5 |
| 207 | BNE_TEST_FAIL |
| 208 | nop |
| 209 | |
| 210 | REG_TEST_18: |
| 211 | setx FIRE_DLC_MMU_CSR_A_PTB_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_18) + 8, 16, 16)) -> printf("\nRead REG_TEST_18\n") |
| 212 | setx FIRE_DLC_MMU_CSR_A_PTB_POR_VALUE, %g1, %g3 |
| 213 | ldx [%g2], %g4 |
| 214 | xorcc %g3, %g4, %g5 |
| 215 | BNE_TEST_FAIL |
| 216 | nop |
| 217 | |
| 218 | REG_TEST_19: |
| 219 | setx FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_19) + 8, 16, 16)) -> printf("\nRead REG_TEST_19\n") |
| 220 | setx FIRE_DLC_MMU_CSR_A_DEV2IOTSB_POR_VALUE, %g1, %g3 |
| 221 | ldx [%g2], %g4 |
| 222 | xorcc %g3, %g4, %g5 |
| 223 | BNE_TEST_FAIL |
| 224 | nop |
| 225 | |
| 226 | REG_TEST_20: |
| 227 | setx FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_20) + 8, 16, 16)) -> printf("\nRead REG_TEST_20\n") |
| 228 | setx FIRE_DLC_MMU_CSR_A_IOTSBDESC_POR_VALUE, %g1, %g3 |
| 229 | ldx [%g2], %g4 |
| 230 | xorcc %g3, %g4, %g5 |
| 231 | BNE_TEST_FAIL |
| 232 | nop |
| 233 | |
| 234 | REG_TEST_21: |
| 235 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_21) + 8, 16, 16)) -> printf("\nRead REG_TEST_21\n") |
| 236 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_POR_VALUE, %g1, %g3 |
| 237 | ldx [%g2], %g4 |
| 238 | xorcc %g3, %g4, %g5 |
| 239 | BNE_TEST_FAIL |
| 240 | nop |
| 241 | |
| 242 | REG_TEST_22: |
| 243 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_22) + 8, 16, 16)) -> printf("\nRead REG_TEST_22\n") |
| 244 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_POR_VALUE, %g1, %g3 |
| 245 | ldx [%g2], %g4 |
| 246 | xorcc %g3, %g4, %g5 |
| 247 | BNE_TEST_FAIL |
| 248 | nop |
| 249 | |
| 250 | REG_TEST_23: |
| 251 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_23) + 8, 16, 16)) -> printf("\nRead REG_TEST_23\n") |
| 252 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_POR_VALUE, %g1, %g3 |
| 253 | ldx [%g2], %g4 |
| 254 | xorcc %g3, %g4, %g5 |
| 255 | BNE_TEST_FAIL |
| 256 | nop |
| 257 | |
| 258 | REG_TEST_24: |
| 259 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_24) + 8, 16, 16)) -> printf("\nRead REG_TEST_24\n") |
| 260 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_POR_VALUE, %g1, %g3 |
| 261 | ldx [%g2], %g4 |
| 262 | xorcc %g3, %g4, %g5 |
| 263 | BNE_TEST_FAIL |
| 264 | nop |
| 265 | |
| 266 | REG_TEST_25: |
| 267 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_25) + 8, 16, 16)) -> printf("\nRead REG_TEST_25\n") |
| 268 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_POR_VALUE, %g1, %g3 |
| 269 | ldx [%g2], %g4 |
| 270 | xorcc %g3, %g4, %g5 |
| 271 | BNE_TEST_FAIL |
| 272 | nop |
| 273 | |
| 274 | REG_TEST_26: |
| 275 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_26) + 8, 16, 16)) -> printf("\nRead REG_TEST_26\n") |
| 276 | setx FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_POR_VALUE, %g1, %g3 |
| 277 | ldx [%g2], %g4 |
| 278 | xorcc %g3, %g4, %g5 |
| 279 | BNE_TEST_FAIL |
| 280 | nop |
| 281 | |
| 282 | REG_TEST_27: |
| 283 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_27) + 8, 16, 16)) -> printf("\nRead REG_TEST_27\n") |
| 284 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_POR_VALUE, %g1, %g3 |
| 285 | ldx [%g2], %g4 |
| 286 | xorcc %g3, %g4, %g5 |
| 287 | BNE_TEST_FAIL |
| 288 | nop |
| 289 | |
| 290 | REG_TEST_28: |
| 291 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_28) + 8, 16, 16)) -> printf("\nRead REG_TEST_28\n") |
| 292 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_POR_VALUE, %g1, %g3 |
| 293 | ldx [%g2], %g4 |
| 294 | xorcc %g3, %g4, %g5 |
| 295 | BNE_TEST_FAIL |
| 296 | nop |
| 297 | |
| 298 | REG_TEST_29: |
| 299 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_29) + 8, 16, 16)) -> printf("\nRead REG_TEST_29\n") |
| 300 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_POR_VALUE, %g1, %g3 |
| 301 | ldx [%g2], %g4 |
| 302 | xorcc %g3, %g4, %g5 |
| 303 | BNE_TEST_FAIL |
| 304 | nop |
| 305 | |
| 306 | REG_TEST_30: |
| 307 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_30) + 8, 16, 16)) -> printf("\nRead REG_TEST_30\n") |
| 308 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 309 | ldx [%g2], %g4 |
| 310 | xorcc %g3, %g4, %g5 |
| 311 | BNE_TEST_FAIL |
| 312 | nop |
| 313 | |
| 314 | REG_TEST_31: |
| 315 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_31) + 8, 16, 16)) -> printf("\nRead REG_TEST_31\n") |
| 316 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 317 | ldx [%g2], %g4 |
| 318 | xorcc %g3, %g4, %g5 |
| 319 | BNE_TEST_FAIL |
| 320 | nop |
| 321 | |
| 322 | REG_TEST_32: |
| 323 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_32) + 8, 16, 16)) -> printf("\nRead REG_TEST_32\n") |
| 324 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_POR_VALUE, %g1, %g3 |
| 325 | ldx [%g2], %g4 |
| 326 | xorcc %g3, %g4, %g5 |
| 327 | BNE_TEST_FAIL |
| 328 | nop |
| 329 | |
| 330 | REG_TEST_33: |
| 331 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_33) + 8, 16, 16)) -> printf("\nRead REG_TEST_33\n") |
| 332 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_POR_VALUE, %g1, %g3 |
| 333 | ldx [%g2], %g4 |
| 334 | xorcc %g3, %g4, %g5 |
| 335 | BNE_TEST_FAIL |
| 336 | nop |
| 337 | |
| 338 | REG_TEST_34: |
| 339 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_34) + 8, 16, 16)) -> printf("\nRead REG_TEST_34\n") |
| 340 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_POR_VALUE, %g1, %g3 |
| 341 | ldx [%g2], %g4 |
| 342 | xorcc %g3, %g4, %g5 |
| 343 | BNE_TEST_FAIL |
| 344 | nop |
| 345 | |
| 346 | REG_TEST_35: |
| 347 | setx FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_35) + 8, 16, 16)) -> printf("\nRead REG_TEST_35\n") |
| 348 | setx FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_POR_VALUE, %g1, %g3 |
| 349 | ldx [%g2], %g4 |
| 350 | xorcc %g3, %g4, %g5 |
| 351 | BNE_TEST_FAIL |
| 352 | nop |
| 353 | |
| 354 | REG_TEST_36: |
| 355 | setx FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_36) + 8, 16, 16)) -> printf("\nRead REG_TEST_36\n") |
| 356 | setx FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_POR_VALUE, %g1, %g3 |
| 357 | ldx [%g2], %g4 |
| 358 | xorcc %g3, %g4, %g5 |
| 359 | BNE_TEST_FAIL |
| 360 | nop |
| 361 | |
| 362 | REG_TEST_37: |
| 363 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_37) + 8, 16, 16)) -> printf("\nRead REG_TEST_37\n") |
| 364 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_POR_VALUE, %g1, %g3 |
| 365 | ldx [%g2], %g4 |
| 366 | xorcc %g3, %g4, %g5 |
| 367 | BNE_TEST_FAIL |
| 368 | nop |
| 369 | |
| 370 | REG_TEST_38: |
| 371 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_38) + 8, 16, 16)) -> printf("\nRead REG_TEST_38\n") |
| 372 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_POR_VALUE, %g1, %g3 |
| 373 | ldx [%g2], %g4 |
| 374 | xorcc %g3, %g4, %g5 |
| 375 | BNE_TEST_FAIL |
| 376 | nop |
| 377 | |
| 378 | REG_TEST_39: |
| 379 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_39) + 8, 16, 16)) -> printf("\nRead REG_TEST_39\n") |
| 380 | setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_POR_VALUE, %g1, %g3 |
| 381 | ldx [%g2], %g4 |
| 382 | xorcc %g3, %g4, %g5 |
| 383 | BNE_TEST_FAIL |
| 384 | nop |
| 385 | |
| 386 | REG_TEST_40: |
| 387 | setx FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_40) + 8, 16, 16)) -> printf("\nRead REG_TEST_40\n") |
| 388 | setx FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_POR_VALUE, %g1, %g3 |
| 389 | ldx [%g2], %g4 |
| 390 | xorcc %g3, %g4, %g5 |
| 391 | BNE_TEST_FAIL |
| 392 | nop |
| 393 | |
| 394 | REG_TEST_41: |
| 395 | setx FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_41) + 8, 16, 16)) -> printf("\nRead REG_TEST_41\n") |
| 396 | setx FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_POR_VALUE, %g1, %g3 |
| 397 | ldx [%g2], %g4 |
| 398 | xorcc %g3, %g4, %g5 |
| 399 | BNE_TEST_FAIL |
| 400 | nop |
| 401 | |
| 402 | REG_TEST_42: |
| 403 | setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_42) + 8, 16, 16)) -> printf("\nRead REG_TEST_42\n") |
| 404 | setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_POR_VALUE, %g1, %g3 |
| 405 | ldx [%g2], %g4 |
| 406 | xorcc %g3, %g4, %g5 |
| 407 | BNE_TEST_FAIL |
| 408 | nop |
| 409 | |
| 410 | REG_TEST_43: |
| 411 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_43) + 8, 16, 16)) -> printf("\nRead REG_TEST_43\n") |
| 412 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_POR_VALUE, %g1, %g3 |
| 413 | ldx [%g2], %g4 |
| 414 | xorcc %g3, %g4, %g5 |
| 415 | BNE_TEST_FAIL |
| 416 | nop |
| 417 | |
| 418 | REG_TEST_44: |
| 419 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_44) + 8, 16, 16)) -> printf("\nRead REG_TEST_44\n") |
| 420 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_POR_VALUE, %g1, %g3 |
| 421 | ldx [%g2], %g4 |
| 422 | xorcc %g3, %g4, %g5 |
| 423 | BNE_TEST_FAIL |
| 424 | nop |
| 425 | |
| 426 | REG_TEST_45: |
| 427 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_45) + 8, 16, 16)) -> printf("\nRead REG_TEST_45\n") |
| 428 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_POR_VALUE, %g1, %g3 |
| 429 | ldx [%g2], %g4 |
| 430 | xorcc %g3, %g4, %g5 |
| 431 | BNE_TEST_FAIL |
| 432 | nop |
| 433 | |
| 434 | REG_TEST_46: |
| 435 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_46) + 8, 16, 16)) -> printf("\nRead REG_TEST_46\n") |
| 436 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_POR_VALUE, %g1, %g3 |
| 437 | ldx [%g2], %g4 |
| 438 | xorcc %g3, %g4, %g5 |
| 439 | BNE_TEST_FAIL |
| 440 | nop |
| 441 | |
| 442 | REG_TEST_47: |
| 443 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_47) + 8, 16, 16)) -> printf("\nRead REG_TEST_47\n") |
| 444 | setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_POR_VALUE, %g1, %g3 |
| 445 | ldx [%g2], %g4 |
| 446 | xorcc %g3, %g4, %g5 |
| 447 | BNE_TEST_FAIL |
| 448 | nop |
| 449 | |
| 450 | REG_TEST_48: |
| 451 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_48) + 8, 16, 16)) -> printf("\nRead REG_TEST_48\n") |
| 452 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_POR_VALUE, %g1, %g3 |
| 453 | ldx [%g2], %g4 |
| 454 | xorcc %g3, %g4, %g5 |
| 455 | BNE_TEST_FAIL |
| 456 | nop |
| 457 | |
| 458 | REG_TEST_49: |
| 459 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_49) + 8, 16, 16)) -> printf("\nRead REG_TEST_49\n") |
| 460 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_POR_VALUE, %g1, %g3 |
| 461 | ldx [%g2], %g4 |
| 462 | xorcc %g3, %g4, %g5 |
| 463 | BNE_TEST_FAIL |
| 464 | nop |
| 465 | |
| 466 | REG_TEST_50: |
| 467 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_50) + 8, 16, 16)) -> printf("\nRead REG_TEST_50\n") |
| 468 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_POR_VALUE, %g1, %g3 |
| 469 | ldx [%g2], %g4 |
| 470 | xorcc %g3, %g4, %g5 |
| 471 | BNE_TEST_FAIL |
| 472 | nop |
| 473 | |
| 474 | REG_TEST_51: |
| 475 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_51) + 8, 16, 16)) -> printf("\nRead REG_TEST_51\n") |
| 476 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_POR_VALUE, %g1, %g3 |
| 477 | ldx [%g2], %g4 |
| 478 | xorcc %g3, %g4, %g5 |
| 479 | BNE_TEST_FAIL |
| 480 | nop |
| 481 | |
| 482 | REG_TEST_52: |
| 483 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_52) + 8, 16, 16)) -> printf("\nRead REG_TEST_52\n") |
| 484 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_POR_VALUE, %g1, %g3 |
| 485 | ldx [%g2], %g4 |
| 486 | xorcc %g3, %g4, %g5 |
| 487 | BNE_TEST_FAIL |
| 488 | nop |
| 489 | |
| 490 | REG_TEST_53: |
| 491 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_53) + 8, 16, 16)) -> printf("\nRead REG_TEST_53\n") |
| 492 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_POR_VALUE, %g1, %g3 |
| 493 | ldx [%g2], %g4 |
| 494 | xorcc %g3, %g4, %g5 |
| 495 | BNE_TEST_FAIL |
| 496 | nop |
| 497 | |
| 498 | REG_TEST_54: |
| 499 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_54) + 8, 16, 16)) -> printf("\nRead REG_TEST_54\n") |
| 500 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_POR_VALUE, %g1, %g3 |
| 501 | ldx [%g2], %g4 |
| 502 | xorcc %g3, %g4, %g5 |
| 503 | BNE_TEST_FAIL |
| 504 | nop |
| 505 | |
| 506 | REG_TEST_55: |
| 507 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_55) + 8, 16, 16)) -> printf("\nRead REG_TEST_55\n") |
| 508 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_POR_VALUE, %g1, %g3 |
| 509 | ldx [%g2], %g4 |
| 510 | xorcc %g3, %g4, %g5 |
| 511 | BNE_TEST_FAIL |
| 512 | nop |
| 513 | |
| 514 | REG_TEST_56: |
| 515 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_56) + 8, 16, 16)) -> printf("\nRead REG_TEST_56\n") |
| 516 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_POR_VALUE, %g1, %g3 |
| 517 | ldx [%g2], %g4 |
| 518 | xorcc %g3, %g4, %g5 |
| 519 | BNE_TEST_FAIL |
| 520 | nop |
| 521 | |
| 522 | REG_TEST_57: |
| 523 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_57) + 8, 16, 16)) -> printf("\nRead REG_TEST_57\n") |
| 524 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_POR_VALUE, %g1, %g3 |
| 525 | ldx [%g2], %g4 |
| 526 | xorcc %g3, %g4, %g5 |
| 527 | BNE_TEST_FAIL |
| 528 | nop |
| 529 | |
| 530 | REG_TEST_58: |
| 531 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_58) + 8, 16, 16)) -> printf("\nRead REG_TEST_58\n") |
| 532 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_POR_VALUE, %g1, %g3 |
| 533 | ldx [%g2], %g4 |
| 534 | xorcc %g3, %g4, %g5 |
| 535 | BNE_TEST_FAIL |
| 536 | nop |
| 537 | |
| 538 | REG_TEST_59: |
| 539 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_59) + 8, 16, 16)) -> printf("\nRead REG_TEST_59\n") |
| 540 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_POR_VALUE, %g1, %g3 |
| 541 | ldx [%g2], %g4 |
| 542 | xorcc %g3, %g4, %g5 |
| 543 | BNE_TEST_FAIL |
| 544 | nop |
| 545 | |
| 546 | REG_TEST_60: |
| 547 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_60) + 8, 16, 16)) -> printf("\nRead REG_TEST_60\n") |
| 548 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_POR_VALUE, %g1, %g3 |
| 549 | ldx [%g2], %g4 |
| 550 | xorcc %g3, %g4, %g5 |
| 551 | BNE_TEST_FAIL |
| 552 | nop |
| 553 | |
| 554 | REG_TEST_61: |
| 555 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_61) + 8, 16, 16)) -> printf("\nRead REG_TEST_61\n") |
| 556 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_POR_VALUE, %g1, %g3 |
| 557 | ldx [%g2], %g4 |
| 558 | xorcc %g3, %g4, %g5 |
| 559 | BNE_TEST_FAIL |
| 560 | nop |
| 561 | |
| 562 | REG_TEST_62: |
| 563 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_62) + 8, 16, 16)) -> printf("\nRead REG_TEST_62\n") |
| 564 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_POR_VALUE, %g1, %g3 |
| 565 | ldx [%g2], %g4 |
| 566 | xorcc %g3, %g4, %g5 |
| 567 | BNE_TEST_FAIL |
| 568 | nop |
| 569 | |
| 570 | REG_TEST_63: |
| 571 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_63) + 8, 16, 16)) -> printf("\nRead REG_TEST_63\n") |
| 572 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_POR_VALUE, %g1, %g3 |
| 573 | ldx [%g2], %g4 |
| 574 | xorcc %g3, %g4, %g5 |
| 575 | BNE_TEST_FAIL |
| 576 | nop |
| 577 | |
| 578 | REG_TEST_64: |
| 579 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_64) + 8, 16, 16)) -> printf("\nRead REG_TEST_64\n") |
| 580 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_POR_VALUE, %g1, %g3 |
| 581 | ldx [%g2], %g4 |
| 582 | xorcc %g3, %g4, %g5 |
| 583 | BNE_TEST_FAIL |
| 584 | nop |
| 585 | |
| 586 | REG_TEST_65: |
| 587 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_65) + 8, 16, 16)) -> printf("\nRead REG_TEST_65\n") |
| 588 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_POR_VALUE, %g1, %g3 |
| 589 | ldx [%g2], %g4 |
| 590 | xorcc %g3, %g4, %g5 |
| 591 | BNE_TEST_FAIL |
| 592 | nop |
| 593 | |
| 594 | REG_TEST_66: |
| 595 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_66) + 8, 16, 16)) -> printf("\nRead REG_TEST_66\n") |
| 596 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_POR_VALUE, %g1, %g3 |
| 597 | ldx [%g2], %g4 |
| 598 | xorcc %g3, %g4, %g5 |
| 599 | BNE_TEST_FAIL |
| 600 | nop |
| 601 | |
| 602 | REG_TEST_67: |
| 603 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_67) + 8, 16, 16)) -> printf("\nRead REG_TEST_67\n") |
| 604 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_POR_VALUE, %g1, %g3 |
| 605 | ldx [%g2], %g4 |
| 606 | xorcc %g3, %g4, %g5 |
| 607 | BNE_TEST_FAIL |
| 608 | nop |
| 609 | |
| 610 | REG_TEST_68: |
| 611 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_68) + 8, 16, 16)) -> printf("\nRead REG_TEST_68\n") |
| 612 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_POR_VALUE, %g1, %g3 |
| 613 | ldx [%g2], %g4 |
| 614 | xorcc %g3, %g4, %g5 |
| 615 | BNE_TEST_FAIL |
| 616 | nop |
| 617 | |
| 618 | REG_TEST_69: |
| 619 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_69) + 8, 16, 16)) -> printf("\nRead REG_TEST_69\n") |
| 620 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_POR_VALUE, %g1, %g3 |
| 621 | ldx [%g2], %g4 |
| 622 | xorcc %g3, %g4, %g5 |
| 623 | BNE_TEST_FAIL |
| 624 | nop |
| 625 | |
| 626 | REG_TEST_70: |
| 627 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_70) + 8, 16, 16)) -> printf("\nRead REG_TEST_70\n") |
| 628 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_POR_VALUE, %g1, %g3 |
| 629 | ldx [%g2], %g4 |
| 630 | xorcc %g3, %g4, %g5 |
| 631 | BNE_TEST_FAIL |
| 632 | nop |
| 633 | |
| 634 | REG_TEST_71: |
| 635 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_71) + 8, 16, 16)) -> printf("\nRead REG_TEST_71\n") |
| 636 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_POR_VALUE, %g1, %g3 |
| 637 | ldx [%g2], %g4 |
| 638 | xorcc %g3, %g4, %g5 |
| 639 | BNE_TEST_FAIL |
| 640 | nop |
| 641 | |
| 642 | REG_TEST_72: |
| 643 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_72) + 8, 16, 16)) -> printf("\nRead REG_TEST_72\n") |
| 644 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_POR_VALUE, %g1, %g3 |
| 645 | ldx [%g2], %g4 |
| 646 | xorcc %g3, %g4, %g5 |
| 647 | BNE_TEST_FAIL |
| 648 | nop |
| 649 | |
| 650 | REG_TEST_73: |
| 651 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_73) + 8, 16, 16)) -> printf("\nRead REG_TEST_73\n") |
| 652 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_POR_VALUE, %g1, %g3 |
| 653 | ldx [%g2], %g4 |
| 654 | xorcc %g3, %g4, %g5 |
| 655 | BNE_TEST_FAIL |
| 656 | nop |
| 657 | |
| 658 | REG_TEST_74: |
| 659 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_74) + 8, 16, 16)) -> printf("\nRead REG_TEST_74\n") |
| 660 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_POR_VALUE, %g1, %g3 |
| 661 | ldx [%g2], %g4 |
| 662 | xorcc %g3, %g4, %g5 |
| 663 | BNE_TEST_FAIL |
| 664 | nop |
| 665 | |
| 666 | REG_TEST_75: |
| 667 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_75) + 8, 16, 16)) -> printf("\nRead REG_TEST_75\n") |
| 668 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_POR_VALUE, %g1, %g3 |
| 669 | ldx [%g2], %g4 |
| 670 | xorcc %g3, %g4, %g5 |
| 671 | BNE_TEST_FAIL |
| 672 | nop |
| 673 | |
| 674 | REG_TEST_76: |
| 675 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_76) + 8, 16, 16)) -> printf("\nRead REG_TEST_76\n") |
| 676 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_POR_VALUE, %g1, %g3 |
| 677 | ldx [%g2], %g4 |
| 678 | xorcc %g3, %g4, %g5 |
| 679 | BNE_TEST_FAIL |
| 680 | nop |
| 681 | |
| 682 | REG_TEST_77: |
| 683 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_77) + 8, 16, 16)) -> printf("\nRead REG_TEST_77\n") |
| 684 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_POR_VALUE, %g1, %g3 |
| 685 | ldx [%g2], %g4 |
| 686 | xorcc %g3, %g4, %g5 |
| 687 | BNE_TEST_FAIL |
| 688 | nop |
| 689 | |
| 690 | REG_TEST_78: |
| 691 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_78) + 8, 16, 16)) -> printf("\nRead REG_TEST_78\n") |
| 692 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_POR_VALUE, %g1, %g3 |
| 693 | ldx [%g2], %g4 |
| 694 | xorcc %g3, %g4, %g5 |
| 695 | BNE_TEST_FAIL |
| 696 | nop |
| 697 | |
| 698 | REG_TEST_79: |
| 699 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_79) + 8, 16, 16)) -> printf("\nRead REG_TEST_79\n") |
| 700 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_POR_VALUE, %g1, %g3 |
| 701 | ldx [%g2], %g4 |
| 702 | xorcc %g3, %g4, %g5 |
| 703 | BNE_TEST_FAIL |
| 704 | nop |
| 705 | |
| 706 | REG_TEST_80: |
| 707 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_80) + 8, 16, 16)) -> printf("\nRead REG_TEST_80\n") |
| 708 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_POR_VALUE, %g1, %g3 |
| 709 | ldx [%g2], %g4 |
| 710 | xorcc %g3, %g4, %g5 |
| 711 | BNE_TEST_FAIL |
| 712 | nop |
| 713 | |
| 714 | REG_TEST_81: |
| 715 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_81) + 8, 16, 16)) -> printf("\nRead REG_TEST_81\n") |
| 716 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_POR_VALUE, %g1, %g3 |
| 717 | ldx [%g2], %g4 |
| 718 | xorcc %g3, %g4, %g5 |
| 719 | BNE_TEST_FAIL |
| 720 | nop |
| 721 | |
| 722 | REG_TEST_82: |
| 723 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_82) + 8, 16, 16)) -> printf("\nRead REG_TEST_82\n") |
| 724 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_POR_VALUE, %g1, %g3 |
| 725 | ldx [%g2], %g4 |
| 726 | xorcc %g3, %g4, %g5 |
| 727 | BNE_TEST_FAIL |
| 728 | nop |
| 729 | |
| 730 | REG_TEST_83: |
| 731 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_83) + 8, 16, 16)) -> printf("\nRead REG_TEST_83\n") |
| 732 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_POR_VALUE, %g1, %g3 |
| 733 | ldx [%g2], %g4 |
| 734 | xorcc %g3, %g4, %g5 |
| 735 | BNE_TEST_FAIL |
| 736 | nop |
| 737 | |
| 738 | REG_TEST_84: |
| 739 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_84) + 8, 16, 16)) -> printf("\nRead REG_TEST_84\n") |
| 740 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_POR_VALUE, %g1, %g3 |
| 741 | ldx [%g2], %g4 |
| 742 | xorcc %g3, %g4, %g5 |
| 743 | BNE_TEST_FAIL |
| 744 | nop |
| 745 | |
| 746 | REG_TEST_85: |
| 747 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_85) + 8, 16, 16)) -> printf("\nRead REG_TEST_85\n") |
| 748 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_POR_VALUE, %g1, %g3 |
| 749 | ldx [%g2], %g4 |
| 750 | xorcc %g3, %g4, %g5 |
| 751 | BNE_TEST_FAIL |
| 752 | nop |
| 753 | |
| 754 | REG_TEST_86: |
| 755 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_86) + 8, 16, 16)) -> printf("\nRead REG_TEST_86\n") |
| 756 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_POR_VALUE, %g1, %g3 |
| 757 | ldx [%g2], %g4 |
| 758 | xorcc %g3, %g4, %g5 |
| 759 | BNE_TEST_FAIL |
| 760 | nop |
| 761 | |
| 762 | REG_TEST_87: |
| 763 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_87) + 8, 16, 16)) -> printf("\nRead REG_TEST_87\n") |
| 764 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_POR_VALUE, %g1, %g3 |
| 765 | ldx [%g2], %g4 |
| 766 | xorcc %g3, %g4, %g5 |
| 767 | BNE_TEST_FAIL |
| 768 | nop |
| 769 | |
| 770 | REG_TEST_88: |
| 771 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_88) + 8, 16, 16)) -> printf("\nRead REG_TEST_88\n") |
| 772 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_POR_VALUE, %g1, %g3 |
| 773 | ldx [%g2], %g4 |
| 774 | xorcc %g3, %g4, %g5 |
| 775 | BNE_TEST_FAIL |
| 776 | nop |
| 777 | |
| 778 | REG_TEST_89: |
| 779 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_89) + 8, 16, 16)) -> printf("\nRead REG_TEST_89\n") |
| 780 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_POR_VALUE, %g1, %g3 |
| 781 | ldx [%g2], %g4 |
| 782 | xorcc %g3, %g4, %g5 |
| 783 | BNE_TEST_FAIL |
| 784 | nop |
| 785 | |
| 786 | REG_TEST_90: |
| 787 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_90) + 8, 16, 16)) -> printf("\nRead REG_TEST_90\n") |
| 788 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_POR_VALUE, %g1, %g3 |
| 789 | ldx [%g2], %g4 |
| 790 | xorcc %g3, %g4, %g5 |
| 791 | BNE_TEST_FAIL |
| 792 | nop |
| 793 | |
| 794 | REG_TEST_91: |
| 795 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_91) + 8, 16, 16)) -> printf("\nRead REG_TEST_91\n") |
| 796 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_POR_VALUE, %g1, %g3 |
| 797 | ldx [%g2], %g4 |
| 798 | xorcc %g3, %g4, %g5 |
| 799 | BNE_TEST_FAIL |
| 800 | nop |
| 801 | |
| 802 | REG_TEST_92: |
| 803 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_92) + 8, 16, 16)) -> printf("\nRead REG_TEST_92\n") |
| 804 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_POR_VALUE, %g1, %g3 |
| 805 | ldx [%g2], %g4 |
| 806 | xorcc %g3, %g4, %g5 |
| 807 | BNE_TEST_FAIL |
| 808 | nop |
| 809 | |
| 810 | REG_TEST_93: |
| 811 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_93) + 8, 16, 16)) -> printf("\nRead REG_TEST_93\n") |
| 812 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_POR_VALUE, %g1, %g3 |
| 813 | ldx [%g2], %g4 |
| 814 | xorcc %g3, %g4, %g5 |
| 815 | BNE_TEST_FAIL |
| 816 | nop |
| 817 | |
| 818 | REG_TEST_94: |
| 819 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_94) + 8, 16, 16)) -> printf("\nRead REG_TEST_94\n") |
| 820 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_POR_VALUE, %g1, %g3 |
| 821 | ldx [%g2], %g4 |
| 822 | xorcc %g3, %g4, %g5 |
| 823 | BNE_TEST_FAIL |
| 824 | nop |
| 825 | |
| 826 | REG_TEST_95: |
| 827 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_95) + 8, 16, 16)) -> printf("\nRead REG_TEST_95\n") |
| 828 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_POR_VALUE, %g1, %g3 |
| 829 | ldx [%g2], %g4 |
| 830 | xorcc %g3, %g4, %g5 |
| 831 | BNE_TEST_FAIL |
| 832 | nop |
| 833 | |
| 834 | REG_TEST_96: |
| 835 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_96) + 8, 16, 16)) -> printf("\nRead REG_TEST_96\n") |
| 836 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_POR_VALUE, %g1, %g3 |
| 837 | ldx [%g2], %g4 |
| 838 | xorcc %g3, %g4, %g5 |
| 839 | BNE_TEST_FAIL |
| 840 | nop |
| 841 | |
| 842 | REG_TEST_97: |
| 843 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_97) + 8, 16, 16)) -> printf("\nRead REG_TEST_97\n") |
| 844 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_POR_VALUE, %g1, %g3 |
| 845 | ldx [%g2], %g4 |
| 846 | xorcc %g3, %g4, %g5 |
| 847 | BNE_TEST_FAIL |
| 848 | nop |
| 849 | |
| 850 | REG_TEST_98: |
| 851 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_98) + 8, 16, 16)) -> printf("\nRead REG_TEST_98\n") |
| 852 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_POR_VALUE, %g1, %g3 |
| 853 | ldx [%g2], %g4 |
| 854 | xorcc %g3, %g4, %g5 |
| 855 | BNE_TEST_FAIL |
| 856 | nop |
| 857 | |
| 858 | REG_TEST_99: |
| 859 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_99) + 8, 16, 16)) -> printf("\nRead REG_TEST_99\n") |
| 860 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_POR_VALUE, %g1, %g3 |
| 861 | ldx [%g2], %g4 |
| 862 | xorcc %g3, %g4, %g5 |
| 863 | BNE_TEST_FAIL |
| 864 | nop |
| 865 | |
| 866 | REG_TEST_100: |
| 867 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_100) + 8, 16, 16)) -> printf("\nRead REG_TEST_100\n") |
| 868 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_POR_VALUE, %g1, %g3 |
| 869 | ldx [%g2], %g4 |
| 870 | xorcc %g3, %g4, %g5 |
| 871 | BNE_TEST_FAIL |
| 872 | nop |
| 873 | |
| 874 | REG_TEST_101: |
| 875 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_101) + 8, 16, 16)) -> printf("\nRead REG_TEST_101\n") |
| 876 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_POR_VALUE, %g1, %g3 |
| 877 | ldx [%g2], %g4 |
| 878 | xorcc %g3, %g4, %g5 |
| 879 | BNE_TEST_FAIL |
| 880 | nop |
| 881 | |
| 882 | REG_TEST_102: |
| 883 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_102) + 8, 16, 16)) -> printf("\nRead REG_TEST_102\n") |
| 884 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_POR_VALUE, %g1, %g3 |
| 885 | ldx [%g2], %g4 |
| 886 | xorcc %g3, %g4, %g5 |
| 887 | BNE_TEST_FAIL |
| 888 | nop |
| 889 | |
| 890 | REG_TEST_103: |
| 891 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_103) + 8, 16, 16)) -> printf("\nRead REG_TEST_103\n") |
| 892 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_POR_VALUE, %g1, %g3 |
| 893 | ldx [%g2], %g4 |
| 894 | xorcc %g3, %g4, %g5 |
| 895 | BNE_TEST_FAIL |
| 896 | nop |
| 897 | |
| 898 | REG_TEST_104: |
| 899 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_104) + 8, 16, 16)) -> printf("\nRead REG_TEST_104\n") |
| 900 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_POR_VALUE, %g1, %g3 |
| 901 | ldx [%g2], %g4 |
| 902 | xorcc %g3, %g4, %g5 |
| 903 | BNE_TEST_FAIL |
| 904 | nop |
| 905 | |
| 906 | REG_TEST_105: |
| 907 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_105) + 8, 16, 16)) -> printf("\nRead REG_TEST_105\n") |
| 908 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_POR_VALUE, %g1, %g3 |
| 909 | ldx [%g2], %g4 |
| 910 | xorcc %g3, %g4, %g5 |
| 911 | BNE_TEST_FAIL |
| 912 | nop |
| 913 | |
| 914 | REG_TEST_106: |
| 915 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_106) + 8, 16, 16)) -> printf("\nRead REG_TEST_106\n") |
| 916 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_POR_VALUE, %g1, %g3 |
| 917 | ldx [%g2], %g4 |
| 918 | xorcc %g3, %g4, %g5 |
| 919 | BNE_TEST_FAIL |
| 920 | nop |
| 921 | |
| 922 | REG_TEST_107: |
| 923 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_107) + 8, 16, 16)) -> printf("\nRead REG_TEST_107\n") |
| 924 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_POR_VALUE, %g1, %g3 |
| 925 | ldx [%g2], %g4 |
| 926 | xorcc %g3, %g4, %g5 |
| 927 | BNE_TEST_FAIL |
| 928 | nop |
| 929 | |
| 930 | REG_TEST_108: |
| 931 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_108) + 8, 16, 16)) -> printf("\nRead REG_TEST_108\n") |
| 932 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_POR_VALUE, %g1, %g3 |
| 933 | ldx [%g2], %g4 |
| 934 | xorcc %g3, %g4, %g5 |
| 935 | BNE_TEST_FAIL |
| 936 | nop |
| 937 | |
| 938 | REG_TEST_109: |
| 939 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_109) + 8, 16, 16)) -> printf("\nRead REG_TEST_109\n") |
| 940 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_POR_VALUE, %g1, %g3 |
| 941 | ldx [%g2], %g4 |
| 942 | xorcc %g3, %g4, %g5 |
| 943 | BNE_TEST_FAIL |
| 944 | nop |
| 945 | |
| 946 | REG_TEST_110: |
| 947 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_110) + 8, 16, 16)) -> printf("\nRead REG_TEST_110\n") |
| 948 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_POR_VALUE, %g1, %g3 |
| 949 | ldx [%g2], %g4 |
| 950 | xorcc %g3, %g4, %g5 |
| 951 | BNE_TEST_FAIL |
| 952 | nop |
| 953 | |
| 954 | REG_TEST_111: |
| 955 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_111) + 8, 16, 16)) -> printf("\nRead REG_TEST_111\n") |
| 956 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_POR_VALUE, %g1, %g3 |
| 957 | ldx [%g2], %g4 |
| 958 | xorcc %g3, %g4, %g5 |
| 959 | BNE_TEST_FAIL |
| 960 | nop |
| 961 | |
| 962 | REG_TEST_112: |
| 963 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_112) + 8, 16, 16)) -> printf("\nRead REG_TEST_112\n") |
| 964 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_POR_VALUE, %g1, %g3 |
| 965 | ldx [%g2], %g4 |
| 966 | xorcc %g3, %g4, %g5 |
| 967 | BNE_TEST_FAIL |
| 968 | nop |
| 969 | |
| 970 | REG_TEST_113: |
| 971 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_113) + 8, 16, 16)) -> printf("\nRead REG_TEST_113\n") |
| 972 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_POR_VALUE, %g1, %g3 |
| 973 | ldx [%g2], %g4 |
| 974 | xorcc %g3, %g4, %g5 |
| 975 | BNE_TEST_FAIL |
| 976 | nop |
| 977 | |
| 978 | REG_TEST_114: |
| 979 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_114) + 8, 16, 16)) -> printf("\nRead REG_TEST_114\n") |
| 980 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_POR_VALUE, %g1, %g3 |
| 981 | ldx [%g2], %g4 |
| 982 | xorcc %g3, %g4, %g5 |
| 983 | BNE_TEST_FAIL |
| 984 | nop |
| 985 | |
| 986 | REG_TEST_115: |
| 987 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_115) + 8, 16, 16)) -> printf("\nRead REG_TEST_115\n") |
| 988 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_POR_VALUE, %g1, %g3 |
| 989 | ldx [%g2], %g4 |
| 990 | xorcc %g3, %g4, %g5 |
| 991 | BNE_TEST_FAIL |
| 992 | nop |
| 993 | |
| 994 | REG_TEST_116: |
| 995 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_116) + 8, 16, 16)) -> printf("\nRead REG_TEST_116\n") |
| 996 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_POR_VALUE, %g1, %g3 |
| 997 | ldx [%g2], %g4 |
| 998 | xorcc %g3, %g4, %g5 |
| 999 | BNE_TEST_FAIL |
| 1000 | nop |
| 1001 | |
| 1002 | REG_TEST_117: |
| 1003 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_117) + 8, 16, 16)) -> printf("\nRead REG_TEST_117\n") |
| 1004 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_POR_VALUE, %g1, %g3 |
| 1005 | ldx [%g2], %g4 |
| 1006 | xorcc %g3, %g4, %g5 |
| 1007 | BNE_TEST_FAIL |
| 1008 | nop |
| 1009 | |
| 1010 | REG_TEST_118: |
| 1011 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_118) + 8, 16, 16)) -> printf("\nRead REG_TEST_118\n") |
| 1012 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_POR_VALUE, %g1, %g3 |
| 1013 | ldx [%g2], %g4 |
| 1014 | xorcc %g3, %g4, %g5 |
| 1015 | BNE_TEST_FAIL |
| 1016 | nop |
| 1017 | |
| 1018 | REG_TEST_119: |
| 1019 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_119) + 8, 16, 16)) -> printf("\nRead REG_TEST_119\n") |
| 1020 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_POR_VALUE, %g1, %g3 |
| 1021 | ldx [%g2], %g4 |
| 1022 | xorcc %g3, %g4, %g5 |
| 1023 | BNE_TEST_FAIL |
| 1024 | nop |
| 1025 | |
| 1026 | REG_TEST_120: |
| 1027 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_120) + 8, 16, 16)) -> printf("\nRead REG_TEST_120\n") |
| 1028 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_POR_VALUE, %g1, %g3 |
| 1029 | ldx [%g2], %g4 |
| 1030 | xorcc %g3, %g4, %g5 |
| 1031 | BNE_TEST_FAIL |
| 1032 | nop |
| 1033 | |
| 1034 | REG_TEST_121: |
| 1035 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_121) + 8, 16, 16)) -> printf("\nRead REG_TEST_121\n") |
| 1036 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_POR_VALUE, %g1, %g3 |
| 1037 | ldx [%g2], %g4 |
| 1038 | xorcc %g3, %g4, %g5 |
| 1039 | BNE_TEST_FAIL |
| 1040 | nop |
| 1041 | |
| 1042 | REG_TEST_122: |
| 1043 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_122) + 8, 16, 16)) -> printf("\nRead REG_TEST_122\n") |
| 1044 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_POR_VALUE, %g1, %g3 |
| 1045 | ldx [%g2], %g4 |
| 1046 | xorcc %g3, %g4, %g5 |
| 1047 | BNE_TEST_FAIL |
| 1048 | nop |
| 1049 | |
| 1050 | REG_TEST_123: |
| 1051 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_123) + 8, 16, 16)) -> printf("\nRead REG_TEST_123\n") |
| 1052 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_POR_VALUE, %g1, %g3 |
| 1053 | ldx [%g2], %g4 |
| 1054 | xorcc %g3, %g4, %g5 |
| 1055 | BNE_TEST_FAIL |
| 1056 | nop |
| 1057 | |
| 1058 | REG_TEST_124: |
| 1059 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_124) + 8, 16, 16)) -> printf("\nRead REG_TEST_124\n") |
| 1060 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_POR_VALUE, %g1, %g3 |
| 1061 | ldx [%g2], %g4 |
| 1062 | xorcc %g3, %g4, %g5 |
| 1063 | BNE_TEST_FAIL |
| 1064 | nop |
| 1065 | |
| 1066 | REG_TEST_125: |
| 1067 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_125) + 8, 16, 16)) -> printf("\nRead REG_TEST_125\n") |
| 1068 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_POR_VALUE, %g1, %g3 |
| 1069 | ldx [%g2], %g4 |
| 1070 | xorcc %g3, %g4, %g5 |
| 1071 | BNE_TEST_FAIL |
| 1072 | nop |
| 1073 | |
| 1074 | REG_TEST_126: |
| 1075 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_126) + 8, 16, 16)) -> printf("\nRead REG_TEST_126\n") |
| 1076 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_POR_VALUE, %g1, %g3 |
| 1077 | ldx [%g2], %g4 |
| 1078 | xorcc %g3, %g4, %g5 |
| 1079 | BNE_TEST_FAIL |
| 1080 | nop |
| 1081 | |
| 1082 | REG_TEST_127: |
| 1083 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_127) + 8, 16, 16)) -> printf("\nRead REG_TEST_127\n") |
| 1084 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_POR_VALUE, %g1, %g3 |
| 1085 | ldx [%g2], %g4 |
| 1086 | xorcc %g3, %g4, %g5 |
| 1087 | BNE_TEST_FAIL |
| 1088 | nop |
| 1089 | |
| 1090 | REG_TEST_128: |
| 1091 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_128) + 8, 16, 16)) -> printf("\nRead REG_TEST_128\n") |
| 1092 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_POR_VALUE, %g1, %g3 |
| 1093 | ldx [%g2], %g4 |
| 1094 | xorcc %g3, %g4, %g5 |
| 1095 | BNE_TEST_FAIL |
| 1096 | nop |
| 1097 | |
| 1098 | REG_TEST_129: |
| 1099 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_129) + 8, 16, 16)) -> printf("\nRead REG_TEST_129\n") |
| 1100 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_POR_VALUE, %g1, %g3 |
| 1101 | ldx [%g2], %g4 |
| 1102 | xorcc %g3, %g4, %g5 |
| 1103 | BNE_TEST_FAIL |
| 1104 | nop |
| 1105 | |
| 1106 | REG_TEST_130: |
| 1107 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_130) + 8, 16, 16)) -> printf("\nRead REG_TEST_130\n") |
| 1108 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_POR_VALUE, %g1, %g3 |
| 1109 | ldx [%g2], %g4 |
| 1110 | xorcc %g3, %g4, %g5 |
| 1111 | BNE_TEST_FAIL |
| 1112 | nop |
| 1113 | |
| 1114 | REG_TEST_131: |
| 1115 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_131) + 8, 16, 16)) -> printf("\nRead REG_TEST_131\n") |
| 1116 | setx FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_POR_VALUE, %g1, %g3 |
| 1117 | ldx [%g2], %g4 |
| 1118 | xorcc %g3, %g4, %g5 |
| 1119 | BNE_TEST_FAIL |
| 1120 | nop |
| 1121 | |
| 1122 | REG_TEST_132: |
| 1123 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_132) + 8, 16, 16)) -> printf("\nRead REG_TEST_132\n") |
| 1124 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_POR_VALUE, %g1, %g3 |
| 1125 | ldx [%g2], %g4 |
| 1126 | xorcc %g3, %g4, %g5 |
| 1127 | BNE_TEST_FAIL |
| 1128 | nop |
| 1129 | |
| 1130 | REG_TEST_133: |
| 1131 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_133) + 8, 16, 16)) -> printf("\nRead REG_TEST_133\n") |
| 1132 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_POR_VALUE, %g1, %g3 |
| 1133 | ldx [%g2], %g4 |
| 1134 | xorcc %g3, %g4, %g5 |
| 1135 | BNE_TEST_FAIL |
| 1136 | nop |
| 1137 | |
| 1138 | REG_TEST_134: |
| 1139 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_134) + 8, 16, 16)) -> printf("\nRead REG_TEST_134\n") |
| 1140 | setx FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_POR_VALUE, %g1, %g3 |
| 1141 | ldx [%g2], %g4 |
| 1142 | xorcc %g3, %g4, %g5 |
| 1143 | BNE_TEST_FAIL |
| 1144 | nop |
| 1145 | |
| 1146 | REG_TEST_135: |
| 1147 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_135) + 8, 16, 16)) -> printf("\nRead REG_TEST_135\n") |
| 1148 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_POR_VALUE, %g1, %g3 |
| 1149 | ldx [%g2], %g4 |
| 1150 | xorcc %g3, %g4, %g5 |
| 1151 | BNE_TEST_FAIL |
| 1152 | nop |
| 1153 | |
| 1154 | REG_TEST_136: |
| 1155 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_136) + 8, 16, 16)) -> printf("\nRead REG_TEST_136\n") |
| 1156 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_POR_VALUE, %g1, %g3 |
| 1157 | ldx [%g2], %g4 |
| 1158 | xorcc %g3, %g4, %g5 |
| 1159 | BNE_TEST_FAIL |
| 1160 | nop |
| 1161 | |
| 1162 | REG_TEST_137: |
| 1163 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_137) + 8, 16, 16)) -> printf("\nRead REG_TEST_137\n") |
| 1164 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_POR_VALUE, %g1, %g3 |
| 1165 | ldx [%g2], %g4 |
| 1166 | xorcc %g3, %g4, %g5 |
| 1167 | BNE_TEST_FAIL |
| 1168 | nop |
| 1169 | |
| 1170 | REG_TEST_138: |
| 1171 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_138) + 8, 16, 16)) -> printf("\nRead REG_TEST_138\n") |
| 1172 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_POR_VALUE, %g1, %g3 |
| 1173 | ldx [%g2], %g4 |
| 1174 | xorcc %g3, %g4, %g5 |
| 1175 | BNE_TEST_FAIL |
| 1176 | nop |
| 1177 | |
| 1178 | REG_TEST_139: |
| 1179 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_139) + 8, 16, 16)) -> printf("\nRead REG_TEST_139\n") |
| 1180 | setx FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_POR_VALUE, %g1, %g3 |
| 1181 | ldx [%g2], %g4 |
| 1182 | xorcc %g3, %g4, %g5 |
| 1183 | BNE_TEST_FAIL |
| 1184 | nop |
| 1185 | |
| 1186 | REG_TEST_140: |
| 1187 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_140) + 8, 16, 16)) -> printf("\nRead REG_TEST_140\n") |
| 1188 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_POR_VALUE, %g1, %g3 |
| 1189 | ldx [%g2], %g4 |
| 1190 | xorcc %g3, %g4, %g5 |
| 1191 | BNE_TEST_FAIL |
| 1192 | nop |
| 1193 | |
| 1194 | REG_TEST_141: |
| 1195 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_141) + 8, 16, 16)) -> printf("\nRead REG_TEST_141\n") |
| 1196 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 1197 | ldx [%g2], %g4 |
| 1198 | xorcc %g3, %g4, %g5 |
| 1199 | BNE_TEST_FAIL |
| 1200 | nop |
| 1201 | |
| 1202 | REG_TEST_142: |
| 1203 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_142) + 8, 16, 16)) -> printf("\nRead REG_TEST_142\n") |
| 1204 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 1205 | ldx [%g2], %g4 |
| 1206 | xorcc %g3, %g4, %g5 |
| 1207 | BNE_TEST_FAIL |
| 1208 | nop |
| 1209 | |
| 1210 | REG_TEST_143: |
| 1211 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_143) + 8, 16, 16)) -> printf("\nRead REG_TEST_143\n") |
| 1212 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_POR_VALUE, %g1, %g3 |
| 1213 | ldx [%g2], %g4 |
| 1214 | xorcc %g3, %g4, %g5 |
| 1215 | BNE_TEST_FAIL |
| 1216 | nop |
| 1217 | |
| 1218 | REG_TEST_144: |
| 1219 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_144) + 8, 16, 16)) -> printf("\nRead REG_TEST_144\n") |
| 1220 | setx FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_POR_VALUE, %g1, %g3 |
| 1221 | ldx [%g2], %g4 |
| 1222 | xorcc %g3, %g4, %g5 |
| 1223 | BNE_TEST_FAIL |
| 1224 | nop |
| 1225 | |
| 1226 | REG_TEST_145: |
| 1227 | setx FIRE_DLC_PSB_CSR_A_PSB_DMA_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_145) + 8, 16, 16)) -> printf("\nRead REG_TEST_145\n") |
| 1228 | setx FIRE_DLC_PSB_CSR_A_PSB_DMA_POR_VALUE, %g1, %g3 |
| 1229 | ldx [%g2], %g4 |
| 1230 | xorcc %g3, %g4, %g5 |
| 1231 | BNE_TEST_FAIL |
| 1232 | nop |
| 1233 | |
| 1234 | REG_TEST_146: |
| 1235 | setx FIRE_DLC_PSB_CSR_A_PSB_PIO_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_146) + 8, 16, 16)) -> printf("\nRead REG_TEST_146\n") |
| 1236 | setx FIRE_DLC_PSB_CSR_A_PSB_PIO_POR_VALUE, %g1, %g3 |
| 1237 | ldx [%g2], %g4 |
| 1238 | xorcc %g3, %g4, %g5 |
| 1239 | BNE_TEST_FAIL |
| 1240 | nop |
| 1241 | |
| 1242 | REG_TEST_147: |
| 1243 | setx FIRE_DLC_TSB_CSR_A_TSB_DMA_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_147) + 8, 16, 16)) -> printf("\nRead REG_TEST_147\n") |
| 1244 | setx FIRE_DLC_TSB_CSR_A_TSB_DMA_POR_VALUE, %g1, %g3 |
| 1245 | ldx [%g2], %g4 |
| 1246 | xorcc %g3, %g4, %g5 |
| 1247 | BNE_TEST_FAIL |
| 1248 | nop |
| 1249 | |
| 1250 | REG_TEST_148: |
| 1251 | setx FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_148) + 8, 16, 16)) -> printf("\nRead REG_TEST_148\n") |
| 1252 | setx FIRE_DLC_TSB_CSR_A_TSB_STS_POR_VALUE, %g1, %g3 |
| 1253 | ldx [%g2], %g4 |
| 1254 | xorcc %g3, %g4, %g5 |
| 1255 | BNE_TEST_FAIL |
| 1256 | nop |
| 1257 | |
| 1258 | REG_TEST_149: |
| 1259 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_149) + 8, 16, 16)) -> printf("\nRead REG_TEST_149\n") |
| 1260 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POR_VALUE, %g1, %g3 |
| 1261 | ldx [%g2], %g4 |
| 1262 | xorcc %g3, %g4, %g5 |
| 1263 | BNE_TEST_FAIL |
| 1264 | nop |
| 1265 | |
| 1266 | REG_TEST_150: |
| 1267 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_150) + 8, 16, 16)) -> printf("\nRead REG_TEST_150\n") |
| 1268 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_POR_VALUE, %g1, %g3 |
| 1269 | ldx [%g2], %g4 |
| 1270 | xorcc %g3, %g4, %g5 |
| 1271 | BNE_TEST_FAIL |
| 1272 | nop |
| 1273 | |
| 1274 | REG_TEST_151: |
| 1275 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_151) + 8, 16, 16)) -> printf("\nRead REG_TEST_151\n") |
| 1276 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_POR_VALUE, %g1, %g3 |
| 1277 | ldx [%g2], %g4 |
| 1278 | xorcc %g3, %g4, %g5 |
| 1279 | BNE_TEST_FAIL |
| 1280 | nop |
| 1281 | |
| 1282 | REG_TEST_152: |
| 1283 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_152) + 8, 16, 16)) -> printf("\nRead REG_TEST_152\n") |
| 1284 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 1285 | ldx [%g2], %g4 |
| 1286 | xorcc %g3, %g4, %g5 |
| 1287 | BNE_TEST_FAIL |
| 1288 | nop |
| 1289 | |
| 1290 | REG_TEST_153: |
| 1291 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_153) + 8, 16, 16)) -> printf("\nRead REG_TEST_153\n") |
| 1292 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 1293 | ldx [%g2], %g4 |
| 1294 | xorcc %g3, %g4, %g5 |
| 1295 | BNE_TEST_FAIL |
| 1296 | nop |
| 1297 | |
| 1298 | REG_TEST_154: |
| 1299 | setx FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_154) + 8, 16, 16)) -> printf("\nRead REG_TEST_154\n") |
| 1300 | setx FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_POR_VALUE, %g1, %g3 |
| 1301 | ldx [%g2], %g4 |
| 1302 | xorcc %g3, %g4, %g5 |
| 1303 | BNE_TEST_FAIL |
| 1304 | nop |
| 1305 | |
| 1306 | REG_TEST_155: |
| 1307 | setx FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_155) + 8, 16, 16)) -> printf("\nRead REG_TEST_155\n") |
| 1308 | setx FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_POR_VALUE, %g1, %g3 |
| 1309 | ldx [%g2], %g4 |
| 1310 | xorcc %g3, %g4, %g5 |
| 1311 | BNE_TEST_FAIL |
| 1312 | nop |
| 1313 | |
| 1314 | REG_TEST_156: |
| 1315 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_156) + 8, 16, 16)) -> printf("\nRead REG_TEST_156\n") |
| 1316 | #ifdef DTM_ENABLED |
| 1317 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POR_VALUE+4, %g1, %g3 ! Half rate |
| 1318 | #else |
| 1319 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POR_VALUE, %g1, %g3 |
| 1320 | #endif |
| 1321 | ldx [%g2], %g4 |
| 1322 | xorcc %g3, %g4, %g5 |
| 1323 | BNE_TEST_FAIL |
| 1324 | nop |
| 1325 | |
| 1326 | REG_TEST_157: |
| 1327 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_157) + 8, 16, 16)) -> printf("\nRead REG_TEST_157\n") |
| 1328 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_POR_VALUE, %g1, %g3 |
| 1329 | ldx [%g2], %g4 |
| 1330 | xorcc %g3, %g4, %g5 |
| 1331 | BNE_TEST_FAIL |
| 1332 | nop |
| 1333 | |
| 1334 | REG_TEST_158: |
| 1335 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_158) + 8, 16, 16)) -> printf("\nRead REG_TEST_158\n") |
| 1336 | #ifdef DTM_ENABLED |
| 1337 | set 4, %g3 ! Data link active state |
| 1338 | #else |
| 1339 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_POR_VALUE, %g1, %g3 |
| 1340 | #endif |
| 1341 | ldx [%g2], %g4 |
| 1342 | xorcc %g3, %g4, %g5 |
| 1343 | BNE_TEST_FAIL |
| 1344 | nop |
| 1345 | |
| 1346 | REG_TEST_159: |
| 1347 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_159) + 8, 16, 16)) -> printf("\nRead REG_TEST_159\n") |
| 1348 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_POR_VALUE, %g1, %g3 |
| 1349 | ldx [%g2], %g4 |
| 1350 | xorcc %g3, %g4, %g5 |
| 1351 | BNE_TEST_FAIL |
| 1352 | nop |
| 1353 | |
| 1354 | REG_TEST_160: |
| 1355 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_160) + 8, 16, 16)) -> printf("\nRead REG_TEST_160\n") |
| 1356 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_POR_VALUE, %g1, %g3 |
| 1357 | ldx [%g2], %g4 |
| 1358 | xorcc %g3, %g4, %g5 |
| 1359 | BNE_TEST_FAIL |
| 1360 | nop |
| 1361 | |
| 1362 | REG_TEST_161: |
| 1363 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_161) + 8, 16, 16)) -> printf("\nRead REG_TEST_161\n") |
| 1364 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_POR_VALUE, %g1, %g3 |
| 1365 | ldx [%g2], %g4 |
| 1366 | xorcc %g3, %g4, %g5 |
| 1367 | BNE_TEST_FAIL |
| 1368 | nop |
| 1369 | |
| 1370 | REG_TEST_162: |
| 1371 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_162) + 8, 16, 16)) -> printf("\nRead REG_TEST_162\n") |
| 1372 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_POR_VALUE, %g1, %g3 |
| 1373 | ldx [%g2], %g4 |
| 1374 | xorcc %g3, %g4, %g5 |
| 1375 | BNE_TEST_FAIL |
| 1376 | nop |
| 1377 | |
| 1378 | REG_TEST_163: |
| 1379 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_163) + 8, 16, 16)) -> printf("\nRead REG_TEST_163\n") |
| 1380 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_POR_VALUE, %g1, %g3 |
| 1381 | ldx [%g2], %g4 |
| 1382 | xorcc %g3, %g4, %g5 |
| 1383 | BNE_TEST_FAIL |
| 1384 | nop |
| 1385 | |
| 1386 | REG_TEST_164: |
| 1387 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_164) + 8, 16, 16)) -> printf("\nRead REG_TEST_164\n") |
| 1388 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_POR_VALUE, %g1, %g3 |
| 1389 | ldx [%g2], %g4 |
| 1390 | xorcc %g3, %g4, %g5 |
| 1391 | BNE_TEST_FAIL |
| 1392 | nop |
| 1393 | |
| 1394 | REG_TEST_165: |
| 1395 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_165) + 8, 16, 16)) -> printf("\nRead REG_TEST_165\n") |
| 1396 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_POR_VALUE, %g1, %g3 |
| 1397 | ldx [%g2], %g4 |
| 1398 | xorcc %g3, %g4, %g5 |
| 1399 | BNE_TEST_FAIL |
| 1400 | nop |
| 1401 | |
| 1402 | REG_TEST_166: |
| 1403 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_166) + 8, 16, 16)) -> printf("\nRead REG_TEST_166\n") |
| 1404 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_POR_VALUE, %g1, %g3 |
| 1405 | ldx [%g2], %g4 |
| 1406 | xorcc %g3, %g4, %g5 |
| 1407 | BNE_TEST_FAIL |
| 1408 | nop |
| 1409 | |
| 1410 | REG_TEST_167: |
| 1411 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_167) + 8, 16, 16)) -> printf("\nRead REG_TEST_167\n") |
| 1412 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_POR_VALUE, %g1, %g3 |
| 1413 | ldx [%g2], %g4 |
| 1414 | xorcc %g3, %g4, %g5 |
| 1415 | BNE_TEST_FAIL |
| 1416 | nop |
| 1417 | |
| 1418 | REG_TEST_168: |
| 1419 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_168) + 8, 16, 16)) -> printf("\nRead REG_TEST_168\n") |
| 1420 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_POR_VALUE, %g1, %g3 |
| 1421 | ldx [%g2], %g4 |
| 1422 | xorcc %g3, %g4, %g5 |
| 1423 | BNE_TEST_FAIL |
| 1424 | nop |
| 1425 | |
| 1426 | REG_TEST_169: |
| 1427 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_169) + 8, 16, 16)) -> printf("\nRead REG_TEST_169\n") |
| 1428 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_POR_VALUE, %g1, %g3 |
| 1429 | ldx [%g2], %g4 |
| 1430 | xorcc %g3, %g4, %g5 |
| 1431 | BNE_TEST_FAIL |
| 1432 | nop |
| 1433 | |
| 1434 | REG_TEST_170: |
| 1435 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_170) + 8, 16, 16)) -> printf("\nRead REG_TEST_170\n") |
| 1436 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 1437 | ldx [%g2], %g4 |
| 1438 | xorcc %g3, %g4, %g5 |
| 1439 | BNE_TEST_FAIL |
| 1440 | nop |
| 1441 | |
| 1442 | REG_TEST_171: |
| 1443 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_171) + 8, 16, 16)) -> printf("\nRead REG_TEST_171\n") |
| 1444 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 1445 | ldx [%g2], %g4 |
| 1446 | xorcc %g3, %g4, %g5 |
| 1447 | BNE_TEST_FAIL |
| 1448 | nop |
| 1449 | |
| 1450 | REG_TEST_172: |
| 1451 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_172) + 8, 16, 16)) -> printf("\nRead REG_TEST_172\n") |
| 1452 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_POR_VALUE, %g1, %g3 |
| 1453 | ldx [%g2], %g4 |
| 1454 | xorcc %g3, %g4, %g5 |
| 1455 | BNE_TEST_FAIL |
| 1456 | nop |
| 1457 | |
| 1458 | REG_TEST_173: |
| 1459 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_173) + 8, 16, 16)) -> printf("\nRead REG_TEST_173\n") |
| 1460 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_POR_VALUE, %g1, %g3 |
| 1461 | ldx [%g2], %g4 |
| 1462 | xorcc %g3, %g4, %g5 |
| 1463 | BNE_TEST_FAIL |
| 1464 | nop |
| 1465 | |
| 1466 | /*************************************************** |
| 1467 | REG_TEST_174: |
| 1468 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_174) + 8, 16, 16)) -> printf("\nRead REG_TEST_174\n") |
| 1469 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_POR_VALUE, %g1, %g3 |
| 1470 | ldx [%g2], %g4 |
| 1471 | xorcc %g3, %g4, %g5 |
| 1472 | BNE_TEST_FAIL |
| 1473 | nop |
| 1474 | ********************************************/ |
| 1475 | |
| 1476 | REG_TEST_175: |
| 1477 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_175) + 8, 16, 16)) -> printf("\nRead REG_TEST_175\n") |
| 1478 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_POR_VALUE, %g1, %g3 |
| 1479 | ldx [%g2], %g4 |
| 1480 | xorcc %g3, %g4, %g5 |
| 1481 | BNE_TEST_FAIL |
| 1482 | nop |
| 1483 | |
| 1484 | REG_TEST_176: |
| 1485 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_176) + 8, 16, 16)) -> printf("\nRead REG_TEST_176\n") |
| 1486 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_POR_VALUE, %g1, %g3 |
| 1487 | ldx [%g2], %g4 |
| 1488 | xorcc %g3, %g4, %g5 |
| 1489 | BNE_TEST_FAIL |
| 1490 | nop |
| 1491 | |
| 1492 | REG_TEST_177: |
| 1493 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_177) + 8, 16, 16)) -> printf("\nRead REG_TEST_177\n") |
| 1494 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_POR_VALUE, %g1, %g3 |
| 1495 | ldx [%g2], %g4 |
| 1496 | xorcc %g3, %g4, %g5 |
| 1497 | BNE_TEST_FAIL |
| 1498 | nop |
| 1499 | |
| 1500 | REG_TEST_178: |
| 1501 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_178) + 8, 16, 16)) -> printf("\nRead REG_TEST_178\n") |
| 1502 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_POR_VALUE, %g1, %g3 |
| 1503 | ldx [%g2], %g4 |
| 1504 | xorcc %g3, %g4, %g5 |
| 1505 | BNE_TEST_FAIL |
| 1506 | nop |
| 1507 | |
| 1508 | REG_TEST_179: |
| 1509 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_179) + 8, 16, 16)) -> printf("\nRead REG_TEST_179\n") |
| 1510 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_POR_VALUE, %g1, %g3 |
| 1511 | ldx [%g2], %g4 |
| 1512 | xorcc %g3, %g4, %g5 |
| 1513 | BNE_TEST_FAIL |
| 1514 | nop |
| 1515 | |
| 1516 | REG_TEST_180: |
| 1517 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_180) + 8, 16, 16)) -> printf("\nRead REG_TEST_180\n") |
| 1518 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_POR_VALUE, %g1, %g3 |
| 1519 | ldx [%g2], %g4 |
| 1520 | xorcc %g3, %g4, %g5 |
| 1521 | BNE_TEST_FAIL |
| 1522 | nop |
| 1523 | |
| 1524 | REG_TEST_181: |
| 1525 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_181) + 8, 16, 16)) -> printf("\nRead REG_TEST_181\n") |
| 1526 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_POR_VALUE, %g1, %g3 |
| 1527 | ldx [%g2], %g4 |
| 1528 | xorcc %g3, %g4, %g5 |
| 1529 | BNE_TEST_FAIL |
| 1530 | nop |
| 1531 | |
| 1532 | REG_TEST_182: |
| 1533 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_182) + 8, 16, 16)) -> printf("\nRead REG_TEST_182\n") |
| 1534 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_POR_VALUE, %g1, %g3 |
| 1535 | ldx [%g2], %g4 |
| 1536 | xorcc %g3, %g4, %g5 |
| 1537 | BNE_TEST_FAIL |
| 1538 | nop |
| 1539 | |
| 1540 | REG_TEST_183: |
| 1541 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_183) + 8, 16, 16)) -> printf("\nRead REG_TEST_183\n") |
| 1542 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_POR_VALUE, %g1, %g3 |
| 1543 | ldx [%g2], %g4 |
| 1544 | xorcc %g3, %g4, %g5 |
| 1545 | BNE_TEST_FAIL |
| 1546 | nop |
| 1547 | |
| 1548 | REG_TEST_184: |
| 1549 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_184) + 8, 16, 16)) -> printf("\nRead REG_TEST_184\n") |
| 1550 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_POR_VALUE, %g1, %g3 |
| 1551 | ldx [%g2], %g4 |
| 1552 | xorcc %g3, %g4, %g5 |
| 1553 | BNE_TEST_FAIL |
| 1554 | nop |
| 1555 | |
| 1556 | REG_TEST_185: |
| 1557 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_185) + 8, 16, 16)) -> printf("\nRead REG_TEST_185\n") |
| 1558 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_POR_VALUE, %g1, %g3 |
| 1559 | ldx [%g2], %g4 |
| 1560 | xorcc %g3, %g4, %g5 |
| 1561 | BNE_TEST_FAIL |
| 1562 | nop |
| 1563 | |
| 1564 | REG_TEST_186: |
| 1565 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_186) + 8, 16, 16)) -> printf("\nRead REG_TEST_186\n") |
| 1566 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_POR_VALUE, %g1, %g3 |
| 1567 | ldx [%g2], %g4 |
| 1568 | xorcc %g3, %g4, %g5 |
| 1569 | BNE_TEST_FAIL |
| 1570 | nop |
| 1571 | |
| 1572 | REG_TEST_187: |
| 1573 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_187) + 8, 16, 16)) -> printf("\nRead REG_TEST_187\n") |
| 1574 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_POR_VALUE, %g1, %g3 |
| 1575 | ldx [%g2], %g4 |
| 1576 | xorcc %g3, %g4, %g5 |
| 1577 | BNE_TEST_FAIL |
| 1578 | nop |
| 1579 | |
| 1580 | REG_TEST_188: |
| 1581 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_188) + 8, 16, 16)) -> printf("\nRead REG_TEST_188\n") |
| 1582 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_POR_VALUE, %g1, %g3 |
| 1583 | ldx [%g2], %g4 |
| 1584 | xorcc %g3, %g4, %g5 |
| 1585 | BNE_TEST_FAIL |
| 1586 | nop |
| 1587 | |
| 1588 | REG_TEST_189: |
| 1589 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_189) + 8, 16, 16)) -> printf("\nRead REG_TEST_189\n") |
| 1590 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_POR_VALUE, %g1, %g3 |
| 1591 | ldx [%g2], %g4 |
| 1592 | xorcc %g3, %g4, %g5 |
| 1593 | BNE_TEST_FAIL |
| 1594 | nop |
| 1595 | |
| 1596 | REG_TEST_190: |
| 1597 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_190) + 8, 16, 16)) -> printf("\nRead REG_TEST_190\n") |
| 1598 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_POR_VALUE, %g1, %g3 |
| 1599 | ldx [%g2], %g4 |
| 1600 | xorcc %g3, %g4, %g5 |
| 1601 | BNE_TEST_FAIL |
| 1602 | nop |
| 1603 | |
| 1604 | REG_TEST_191: |
| 1605 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_191) + 8, 16, 16)) -> printf("\nRead REG_TEST_191\n") |
| 1606 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_POR_VALUE, %g1, %g3 |
| 1607 | ldx [%g2], %g4 |
| 1608 | xorcc %g3, %g4, %g5 |
| 1609 | BNE_TEST_FAIL |
| 1610 | nop |
| 1611 | |
| 1612 | REG_TEST_192: |
| 1613 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_192) + 8, 16, 16)) -> printf("\nRead REG_TEST_192\n") |
| 1614 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 1615 | ldx [%g2], %g4 |
| 1616 | xorcc %g3, %g4, %g5 |
| 1617 | BNE_TEST_FAIL |
| 1618 | nop |
| 1619 | |
| 1620 | REG_TEST_193: |
| 1621 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_193) + 8, 16, 16)) -> printf("\nRead REG_TEST_193\n") |
| 1622 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 1623 | ldx [%g2], %g4 |
| 1624 | xorcc %g3, %g4, %g5 |
| 1625 | BNE_TEST_FAIL |
| 1626 | nop |
| 1627 | |
| 1628 | REG_TEST_194: |
| 1629 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_194) + 8, 16, 16)) -> printf("\nRead REG_TEST_194\n") |
| 1630 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_POR_VALUE, %g1, %g3 |
| 1631 | ldx [%g2], %g4 |
| 1632 | xorcc %g3, %g4, %g5 |
| 1633 | BNE_TEST_FAIL |
| 1634 | nop |
| 1635 | |
| 1636 | REG_TEST_195: |
| 1637 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_195) + 8, 16, 16)) -> printf("\nRead REG_TEST_195\n") |
| 1638 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_POR_VALUE, %g1, %g3 |
| 1639 | ldx [%g2], %g4 |
| 1640 | xorcc %g3, %g4, %g5 |
| 1641 | BNE_TEST_FAIL |
| 1642 | nop |
| 1643 | |
| 1644 | REG_TEST_196: |
| 1645 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_196) + 8, 16, 16)) -> printf("\nRead REG_TEST_196\n") |
| 1646 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_POR_VALUE, %g1, %g3 |
| 1647 | ldx [%g2], %g4 |
| 1648 | xorcc %g3, %g4, %g5 |
| 1649 | /* this reg is not in the PRM, so don't bother to check the fetched value (yet) |
| 1650 | ! BNE_TEST_FAIL */ |
| 1651 | nop |
| 1652 | |
| 1653 | REG_TEST_197: |
| 1654 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_197) + 8, 16, 16)) -> printf("\nRead REG_TEST_197\n") |
| 1655 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_POR_VALUE, %g1, %g3 |
| 1656 | ldx [%g2], %g4 |
| 1657 | xorcc %g3, %g4, %g5 |
| 1658 | /* this reg is not in the PRM, so don't bother to check the fetched value (yet) |
| 1659 | ! BNE_TEST_FAIL */ |
| 1660 | nop |
| 1661 | |
| 1662 | REG_TEST_198: |
| 1663 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_198) + 8, 16, 16)) -> printf("\nRead REG_TEST_198\n") |
| 1664 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_POR_VALUE, %g1, %g3 |
| 1665 | ldx [%g2], %g4 |
| 1666 | xorcc %g3, %g4, %g5 |
| 1667 | BNE_TEST_FAIL |
| 1668 | nop |
| 1669 | |
| 1670 | REG_TEST_199: |
| 1671 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_199) + 8, 16, 16)) -> printf("\nRead REG_TEST_199\n") |
| 1672 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_POR_VALUE, %g1, %g3 |
| 1673 | ldx [%g2], %g4 |
| 1674 | xorcc %g3, %g4, %g5 |
| 1675 | BNE_TEST_FAIL |
| 1676 | nop |
| 1677 | |
| 1678 | REG_TEST_200: |
| 1679 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_200) + 8, 16, 16)) -> printf("\nRead REG_TEST_200\n") |
| 1680 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_POR_VALUE, %g1, %g3 |
| 1681 | ldx [%g2], %g4 |
| 1682 | xorcc %g3, %g4, %g5 |
| 1683 | BNE_TEST_FAIL |
| 1684 | nop |
| 1685 | |
| 1686 | REG_TEST_201: |
| 1687 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_201) + 8, 16, 16)) -> printf("\nRead REG_TEST_201\n") |
| 1688 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 1689 | ldx [%g2], %g4 |
| 1690 | xorcc %g3, %g4, %g5 |
| 1691 | BNE_TEST_FAIL |
| 1692 | nop |
| 1693 | |
| 1694 | REG_TEST_202: |
| 1695 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_202) + 8, 16, 16)) -> printf("\nRead REG_TEST_202\n") |
| 1696 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 1697 | ldx [%g2], %g4 |
| 1698 | xorcc %g3, %g4, %g5 |
| 1699 | BNE_TEST_FAIL |
| 1700 | nop |
| 1701 | |
| 1702 | REG_TEST_203: |
| 1703 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_203) + 8, 16, 16)) -> printf("\nRead REG_TEST_203\n") |
| 1704 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_PEU_DLPL_SERDES_REV_POR_VALUE, %g1, %g3 |
| 1705 | ldx [%g2], %g4 |
| 1706 | xorcc %g3, %g4, %g5 |
| 1707 | BNE_TEST_FAIL |
| 1708 | nop |
| 1709 | |
| 1710 | REG_TEST_204: |
| 1711 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_204) + 8, 16, 16)) -> printf("\nRead REG_TEST_204\n") |
| 1712 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_POR_VALUE, %g1, %g3 |
| 1713 | ldx [%g2], %g4 |
| 1714 | xorcc %g3, %g4, %g5 |
| 1715 | BNE_TEST_FAIL |
| 1716 | nop |
| 1717 | |
| 1718 | REG_TEST_205: |
| 1719 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_205) + 8, 16, 16)) -> printf("\nRead REG_TEST_205\n") |
| 1720 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_POR_VALUE, %g1, %g3 |
| 1721 | ldx [%g2], %g4 |
| 1722 | xorcc %g3, %g4, %g5 |
| 1723 | BNE_TEST_FAIL |
| 1724 | nop |
| 1725 | |
| 1726 | REG_TEST_206: |
| 1727 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_206) + 8, 16, 16)) -> printf("\nRead REG_TEST_206\n") |
| 1728 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_POR_VALUE, %g1, %g3 |
| 1729 | ldx [%g2], %g4 |
| 1730 | xorcc %g3, %g4, %g5 |
| 1731 | BNE_TEST_FAIL |
| 1732 | nop |
| 1733 | |
| 1734 | REG_TEST_207: |
| 1735 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_207) + 8, 16, 16)) -> printf("\nRead REG_TEST_207\n") |
| 1736 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_POR_VALUE, %g1, %g3 |
| 1737 | ldx [%g2], %g4 |
| 1738 | xorcc %g3, %g4, %g5 |
| 1739 | BNE_TEST_FAIL |
| 1740 | nop |
| 1741 | |
| 1742 | REG_TEST_208: |
| 1743 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_208) + 8, 16, 16)) -> printf("\nRead REG_TEST_208\n") |
| 1744 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_POR_VALUE, %g1, %g3 |
| 1745 | ldx [%g2], %g4 |
| 1746 | xorcc %g3, %g4, %g5 |
| 1747 | BNE_TEST_FAIL |
| 1748 | nop |
| 1749 | |
| 1750 | REG_TEST_209: |
| 1751 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_209) + 8, 16, 16)) -> printf("\nRead REG_TEST_209\n") |
| 1752 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_POR_VALUE, %g1, %g3 |
| 1753 | ldx [%g2], %g4 |
| 1754 | xorcc %g3, %g4, %g5 |
| 1755 | BNE_TEST_FAIL |
| 1756 | nop |
| 1757 | |
| 1758 | REG_TEST_210: |
| 1759 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_210) + 8, 16, 16)) -> printf("\nRead REG_TEST_210\n") |
| 1760 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_POR_VALUE, %g1, %g3 |
| 1761 | ldx [%g2], %g4 |
| 1762 | xorcc %g3, %g4, %g5 |
| 1763 | BNE_TEST_FAIL |
| 1764 | nop |
| 1765 | |
| 1766 | REG_TEST_211: |
| 1767 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_211) + 8, 16, 16)) -> printf("\nRead REG_TEST_211\n") |
| 1768 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_POR_VALUE, %g1, %g3 |
| 1769 | ldx [%g2], %g4 |
| 1770 | xorcc %g3, %g4, %g5 |
| 1771 | BNE_TEST_FAIL |
| 1772 | nop |
| 1773 | |
| 1774 | REG_TEST_212: |
| 1775 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_212) + 8, 16, 16)) -> printf("\nRead REG_TEST_212\n") |
| 1776 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_POR_VALUE, %g1, %g3 |
| 1777 | ldx [%g2], %g4 |
| 1778 | xorcc %g3, %g4, %g5 |
| 1779 | BNE_TEST_FAIL |
| 1780 | nop |
| 1781 | |
| 1782 | REG_TEST_213: |
| 1783 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_213) + 8, 16, 16)) -> printf("\nRead REG_TEST_213\n") |
| 1784 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_POR_VALUE, %g1, %g3 |
| 1785 | ldx [%g2], %g4 |
| 1786 | xorcc %g3, %g4, %g5 |
| 1787 | BNE_TEST_FAIL |
| 1788 | nop |
| 1789 | |
| 1790 | REG_TEST_214: |
| 1791 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_214) + 8, 16, 16)) -> printf("\nRead REG_TEST_214\n") |
| 1792 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_POR_VALUE, %g1, %g3 |
| 1793 | ldx [%g2], %g4 |
| 1794 | xorcc %g3, %g4, %g5 |
| 1795 | BNE_TEST_FAIL |
| 1796 | nop |
| 1797 | |
| 1798 | /*************************************************** |
| 1799 | REG_TEST_215: |
| 1800 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_215) + 8, 16, 16)) -> printf("\nRead REG_TEST_215\n") |
| 1801 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_POR_VALUE, %g1, %g3 |
| 1802 | ldx [%g2], %g4 |
| 1803 | xorcc %g3, %g4, %g5 |
| 1804 | BNE_TEST_FAIL |
| 1805 | nop |
| 1806 | *******************************************************/ |
| 1807 | |
| 1808 | REG_TEST_216: |
| 1809 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_216) + 8, 16, 16)) -> printf("\nRead REG_TEST_216\n") |
| 1810 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_POR_VALUE, %g1, %g3 |
| 1811 | ldx [%g2], %g4 |
| 1812 | xorcc %g3, %g4, %g5 |
| 1813 | BNE_TEST_FAIL |
| 1814 | nop |
| 1815 | |
| 1816 | REG_TEST_217: |
| 1817 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_217) + 8, 16, 16)) -> printf("\nRead REG_TEST_217\n") |
| 1818 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_POR_VALUE, %g1, %g3 |
| 1819 | ldx [%g2], %g4 |
| 1820 | xorcc %g3, %g4, %g5 |
| 1821 | BNE_TEST_FAIL |
| 1822 | nop |
| 1823 | |
| 1824 | REG_TEST_218: |
| 1825 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_218) + 8, 16, 16)) -> printf("\nRead REG_TEST_218\n") |
| 1826 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_POR_VALUE, %g1, %g3 |
| 1827 | ldx [%g2], %g4 |
| 1828 | xorcc %g3, %g4, %g5 |
| 1829 | BNE_TEST_FAIL |
| 1830 | nop |
| 1831 | |
| 1832 | ! check this reg |
| 1833 | ! RTL returns 0x18000 |
| 1834 | /************************************* |
| 1835 | REG_TEST_219: |
| 1836 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_219) + 8, 16, 16)) -> printf("\nRead REG_TEST_219\n") |
| 1837 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE, %g1, %g3 |
| 1838 | ldx [%g2], %g4 |
| 1839 | xorcc %g3, %g4, %g5 |
| 1840 | BNE_TEST_FAIL |
| 1841 | nop |
| 1842 | *********************************/ |
| 1843 | |
| 1844 | ! check this reg |
| 1845 | ! RTL returns 0x18000 |
| 1846 | /************************************* |
| 1847 | REG_TEST_220: |
| 1848 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_220) + 8, 16, 16)) -> printf("\nRead REG_TEST_220\n") |
| 1849 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE, %g1, %g3 |
| 1850 | ldx [%g2], %g4 |
| 1851 | xorcc %g3, %g4, %g5 |
| 1852 | BNE_TEST_FAIL |
| 1853 | nop |
| 1854 | |
| 1855 | REG_TEST_221: |
| 1856 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_221) + 8, 16, 16)) -> printf("\nRead REG_TEST_221\n") |
| 1857 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_POR_VALUE, %g1, %g3 |
| 1858 | ldx [%g2], %g4 |
| 1859 | xorcc %g3, %g4, %g5 |
| 1860 | BNE_TEST_FAIL |
| 1861 | nop |
| 1862 | *********************************/ |
| 1863 | |
| 1864 | REG_TEST_222: |
| 1865 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_222) + 8, 16, 16)) -> printf("\nRead REG_TEST_222\n") |
| 1866 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_POR_VALUE, %g1, %g3 |
| 1867 | ldx [%g2], %g4 |
| 1868 | xorcc %g3, %g4, %g5 |
| 1869 | BNE_TEST_FAIL |
| 1870 | nop |
| 1871 | |
| 1872 | REG_TEST_223: |
| 1873 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_223) + 8, 16, 16)) -> printf("\nRead REG_TEST_223\n") |
| 1874 | #ifdef DTM_ENABLED |
| 1875 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_POR_VALUE|7, %g1, %g3 ! 100 Mhz |
| 1876 | #else |
| 1877 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_POR_VALUE, %g1, %g3 |
| 1878 | #endif |
| 1879 | ldx [%g2], %g4 |
| 1880 | xorcc %g3, %g4, %g5 |
| 1881 | BNE_TEST_FAIL |
| 1882 | nop |
| 1883 | |
| 1884 | REG_TEST_224: |
| 1885 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_224) + 8, 16, 16)) -> printf("\nRead REG_TEST_224\n") |
| 1886 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE, %g1, %g3 |
| 1887 | ldx [%g2], %g4 |
| 1888 | xorcc %g3, %g4, %g5 |
| 1889 | BNE_TEST_FAIL |
| 1890 | nop |
| 1891 | |
| 1892 | ! check this reg |
| 1893 | ! RTL returns X |
| 1894 | /************************************* |
| 1895 | REG_TEST_225: |
| 1896 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_225) + 8, 16, 16)) -> printf("\nRead REG_TEST_225\n") |
| 1897 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_POR_VALUE, %g1, %g3 |
| 1898 | ldx [%g2], %g4 |
| 1899 | xorcc %g3, %g4, %g5 |
| 1900 | BNE_TEST_FAIL |
| 1901 | nop |
| 1902 | |
| 1903 | REG_TEST_226: |
| 1904 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_226) + 8, 16, 16)) -> printf("\nRead REG_TEST_226\n") |
| 1905 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE, %g1, %g3 |
| 1906 | ldx [%g2], %g4 |
| 1907 | xorcc %g3, %g4, %g5 |
| 1908 | BNE_TEST_FAIL |
| 1909 | nop |
| 1910 | |
| 1911 | REG_TEST_227: |
| 1912 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_227) + 8, 16, 16)) -> printf("\nRead REG_TEST_227\n") |
| 1913 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_POR_VALUE, %g1, %g3 |
| 1914 | ldx [%g2], %g4 |
| 1915 | xorcc %g3, %g4, %g5 |
| 1916 | BNE_TEST_FAIL |
| 1917 | nop |
| 1918 | |
| 1919 | REG_TEST_228: |
| 1920 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_ADDR, %g1, %g2 ! $EV trig_pc_d(1, expr(@VA(.MAIN.REG_TEST_228) + 8, 16, 16)) -> printf("\nRead REG_TEST_228\n") |
| 1921 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_POR_VALUE, %g1, %g3 |
| 1922 | ldx [%g2], %g4 |
| 1923 | xorcc %g3, %g4, %g5 |
| 1924 | BNE_TEST_FAIL |
| 1925 | nop |
| 1926 | ***************************************************/ |
| 1927 | |
| 1928 | test_passed: |
| 1929 | EXIT_GOOD |
| 1930 | |
| 1931 | test_failed: |
| 1932 | EXIT_BAD |
| 1933 | |