| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: err_itdp_diag.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MY_HP_TEXT_PA 0x1050000000 |
| 39 | #define MY_HP_DATA_PA 0x1050001000 |
| 40 | |
| 41 | #define ASI_PRIMARY_CONTEXT_0 0x21 |
| 42 | #define ASI_ITLB_DATA_IN_REG 0x54 |
| 43 | #define ASI_DMMU_TAG_ACCESS 0x58 |
| 44 | #define ASI_DTLB_DATA_IN_REG 0x5c |
| 45 | #define ASI_DMMU_SFAR 0x58 |
| 46 | |
| 47 | |
| 48 | #define MY_USER_TEXT_VA000 0x7a000000 |
| 49 | #define MY_USER_TEXT_RA000 0x7b000000 |
| 50 | #define MY_USER_TEXT_PA000 0x107b000000 |
| 51 | #define MY_USER_TEXT_VA001 0x7a010000 |
| 52 | #define MY_USER_TEXT_RA001 0x7b010000 |
| 53 | #define MY_USER_TEXT_PA001 0x107b010000 |
| 54 | |
| 55 | #define MY_USER_DATA_VA000 0x6a000000 |
| 56 | #define MY_USER_DATA_RA000 0x6b000000 |
| 57 | #define MY_USER_DATA_PA000 0x106b000000 |
| 58 | #define MY_USER_DATA_VA001 0x6a010000 |
| 59 | #define MY_USER_DATA_RA001 0x6b010000 |
| 60 | #define MY_USER_DATA_PA001 0x106b010000 |
| 61 | |
| 62 | #define IMDU_ERR_EN 0xa0000000 |
| 63 | #define IMTU_ERR_EN 0x90000000 |
| 64 | #define DMDU_ERR_EN 0x88000000 |
| 65 | #define DMTU_ERR_EN 0x84000000 |
| 66 | #define IRCU_ERR_EN 0x82000000 |
| 67 | #define FRCU_ERR_EN 0x81000000 |
| 68 | #define SCAU_ERR_EN 0x80800000 |
| 69 | #define TCCU_ERR_EN 0x80400000 |
| 70 | #define TSAU_ERR_EN 0x80200000 |
| 71 | #define MRAU_ERR_EN 0x80100000 |
| 72 | #define STAU_ERR_EN 0x80080000 |
| 73 | #define STDU_ERR_EN 0x80020000 |
| 74 | |
| 75 | #define ASI_DESR 0x4c |
| 76 | #define ASI_DFESR 0x4c |
| 77 | #define DFESR_VA 0x8 |
| 78 | #define ASI_DSFSR 0x58 |
| 79 | #define ASI_ISFSR 0x50 |
| 80 | #define SFSR_VA 0x18 |
| 81 | #define ASI_SFAR 0x58 |
| 82 | #define SFAR_VA 0x20 |
| 83 | #define ASI_ERR_INJ 0x43 |
| 84 | #define ASI_CETER 0x4C |
| 85 | #define CETER_VA 0x18 |
| 86 | #define ASI_CERER 0x4C |
| 87 | #define CERER_VA 0x10 |
| 88 | |
| 89 | |
| 90 | #define MAIN_PAGE_HV_ALSO |
| 91 | !! enable error detcetion. Disable error injection. |
| 92 | #define H_HT0_Mem_Address_Not_Aligned_0x34 |
| 93 | #define My_HT0_Mem_Address_Not_Aligned_0x34 \ |
| 94 | add %g0, CERER_VA, %g3; \ |
| 95 | stxa %o2, [%g3]ASI_CERER; \ |
| 96 | stxa %g0, [%g0]ASI_ERR_INJ; \ |
| 97 | done;nop;nop;nop;nop |
| 98 | |
| 99 | |
| 100 | #define H_HT0_Data_Access_MMU_Error_0x72 |
| 101 | #define SUN_H_HT0_Data_Access_MMU_Error_0x72 \ |
| 102 | ba DATA_ACCESS_ERROR_HANDLER; \ |
| 103 | nop;nop;nop;nop;nop;nop;nop |
| 104 | |
| 105 | #define H_HT0_Instruction_Access_MMU_Error_0x71 |
| 106 | #define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \ |
| 107 | ba INST_ACCESS_ERROR_HANDLER; \ |
| 108 | nop;nop;nop;nop;nop;nop;nop |
| 109 | |
| 110 | #define CETER_PSCCE 0 |
| 111 | #define CETER_DE 0 |
| 112 | #define CETER_PSCCE 0 |
| 113 | #include "hboot.s" |
| 114 | |
| 115 | /************************************************************************ |
| 116 | Test case: |
| 117 | ************************************************************************/ |
| 118 | |
| 119 | .text |
| 120 | .global main |
| 121 | !! Enable err_injection and err_detection. The pg to which we are jumping |
| 122 | !! is a tLB miss, it will be loaded in TLB with err injected and then |
| 123 | !! on the TLB lookup error will be seen. When we first lookup the pg, it is |
| 124 | !! a TLB miss. The err_hanlder clears error detection but err_injection is |
| 125 | !!on so pg is reloaded with parity err. |
| 126 | main: /* test begin */ |
| 127 | ta T_CHANGE_HPRIV |
| 128 | |
| 129 | !! Enable CERER |
| 130 | setx 0x4000000000000000, %l0, %o2 !! enable ITDP errs |
| 131 | add %g0, CERER_VA, %g3 !!g3 has cerer va |
| 132 | |
| 133 | stxa %o2, [%g3]ASI_CERER |
| 134 | |
| 135 | !! Enable error injection |
| 136 | setx IMDU_ERR_EN, %l0, %l1 |
| 137 | stxa %l1, [%g0]ASI_ERR_INJ |
| 138 | |
| 139 | ta T_CHANGE_NONHPRIV |
| 140 | mov %g0, %i0 |
| 141 | setx user_code_begin_000, %g1, %l4 |
| 142 | jmp %l4 |
| 143 | nop |
| 144 | EXIT_BAD |
| 145 | nop |
| 146 | |
| 147 | |
| 148 | |
| 149 | /************************************************************************ |
| 150 | Test case data start |
| 151 | ************************************************************************/ |
| 152 | .data |
| 153 | .global user_data_start |
| 154 | user_data_start: |
| 155 | .word 0xD6B3479D |
| 156 | .word 0xDB28926C |
| 157 | |
| 158 | !#*********************************************************************** |
| 159 | |
| 160 | SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000 |
| 161 | attr_text { |
| 162 | Name = .My_User_Section_4v000, |
| 163 | part_0_ctx_nonzero_tsb_config_2, |
| 164 | VA = MY_USER_TEXT_VA000, |
| 165 | RA = MY_USER_TEXT_RA000, |
| 166 | PA = ra2pa(MY_USER_TEXT_RA000, 0), |
| 167 | TTE_Context = PCONTEXT, |
| 168 | TTE_V = 1, |
| 169 | TTE_NFO = 0, |
| 170 | TTE_L = 0, |
| 171 | TTE_Soft = 0, |
| 172 | TTE_IE = 0, |
| 173 | TTE_E = 0, |
| 174 | TTE_CP = 1, |
| 175 | TTE_CV = 0, |
| 176 | TTE_P = 0, |
| 177 | TTE_EP = 1, |
| 178 | TTE_W = 0, |
| 179 | TTE_SW1 = 0, |
| 180 | TTE_SW0 = 0, |
| 181 | TTE_RSVD1 = 0, |
| 182 | TTE_Size = 0, |
| 183 | } |
| 184 | |
| 185 | !! Take mis aligned trap. The trap handler enables err_detection and |
| 186 | !! clears err_injection. On return from trap handler, mmu_err trap is |
| 187 | !! taken for label TH0_done. The pg is reloaded with no err. |
| 188 | .text |
| 189 | .global user_code_begin_000 |
| 190 | user_code_begin_000: |
| 191 | cmp %i0, 0x1 |
| 192 | bne FAIL |
| 193 | mov %g0, %i0 |
| 194 | setx user_data_begin_000, %g1, %l3 |
| 195 | setx TH0_DONE, %g1, %l4 |
| 196 | ld [%l3+1], %g1 !cause mem_addr_not_aligned trap |
| 197 | TH0_DONE: |
| 198 | cmp %i0, 0x1 |
| 199 | bne FAIL |
| 200 | setx user_code_begin_001, %g1, %l4 |
| 201 | jmp %l4 |
| 202 | mov %g0, %i0 |
| 203 | |
| 204 | FAIL: EXIT_BAD |
| 205 | nop |
| 206 | |
| 207 | attr_data { |
| 208 | Name = .My_User_Section_4v000, |
| 209 | part_0_ctx_nonzero_tsb_config_1, |
| 210 | VA = MY_USER_DATA_VA000, |
| 211 | RA = MY_USER_DATA_RA000, |
| 212 | PA = ra2pa(MY_USER_DATA_RA000, 0), |
| 213 | TTE_Context = PCONTEXT, |
| 214 | TTE_V = 1, |
| 215 | TTE_NFO = 0, |
| 216 | TTE_L = 0, |
| 217 | TTE_Soft = 0, |
| 218 | TTE_IE = 0, |
| 219 | TTE_E = 0, |
| 220 | TTE_CP = 1, |
| 221 | TTE_CV = 0, |
| 222 | TTE_P = 0, |
| 223 | TTE_EP = 0, |
| 224 | TTE_W = 1, |
| 225 | TTE_SW1 = 0, |
| 226 | TTE_SW0 = 0, |
| 227 | TTE_RSVD1 = 0, |
| 228 | TTE_Size = 0, |
| 229 | } |
| 230 | .data |
| 231 | .global user_data_begin_000 |
| 232 | user_data_begin_000: |
| 233 | .word 0x6c7e |
| 234 | .word 0x2fbf |
| 235 | .word 0x2c83 |
| 236 | .word 0x11ab0 |
| 237 | |
| 238 | SECTION .My_User_Section_4v001 TEXT_VA=MY_USER_TEXT_VA001, DATA_VA=MY_USER_DATA_VA001 |
| 239 | attr_text { |
| 240 | Name = .My_User_Section_4v001, |
| 241 | part_0_ctx_nonzero_tsb_config_2, |
| 242 | VA = MY_USER_TEXT_VA001, |
| 243 | RA = MY_USER_TEXT_RA001, |
| 244 | PA = ra2pa(MY_USER_TEXT_RA001, 0), |
| 245 | TTE_Context = PCONTEXT, |
| 246 | TTE_V = 1, |
| 247 | TTE_NFO = 0, |
| 248 | TTE_L = 0, |
| 249 | TTE_Soft = 0, |
| 250 | TTE_IE = 0, |
| 251 | TTE_E = 0, |
| 252 | TTE_CP = 1, |
| 253 | TTE_CV = 0, |
| 254 | TTE_P = 0, |
| 255 | TTE_EP = 1, |
| 256 | TTE_W = 0, |
| 257 | TTE_SW1 = 0, |
| 258 | TTE_SW0 = 0, |
| 259 | TTE_RSVD1 = 0, |
| 260 | TTE_Size = 0, |
| 261 | } |
| 262 | attr_text { |
| 263 | NAME = .My_User_Section_4v001, |
| 264 | hypervisor |
| 265 | } |
| 266 | |
| 267 | !! Chk if there is an err in the delay slot and delay slot is annulled |
| 268 | !! then err is not reported. |
| 269 | !! pg _001 has no error. Lable TGT0 represents the last inst. of |
| 270 | !! pg_001 and TGT1 represents the first inst. of next pg. |
| 271 | !! There are two iterations, in the first iteration inst in delay slot is |
| 272 | !! executed and causes pg to be loaded with err in tlb. Alignment trap |
| 273 | !! is taken that causes err_detection to be enabled. On return from |
| 274 | !!trap handler the delay slot inst has an err but it is not reported as |
| 275 | !! the delay slot os annulled. |
| 276 | .text |
| 277 | .global user_code_begin_001 |
| 278 | .skip 8124 |
| 279 | user_code_begin_001: |
| 280 | mov %g0, %i1 ! to control branch execution |
| 281 | ta T_CHANGE_HPRIV |
| 282 | !! Enable error injection |
| 283 | stxa %l1, [%g0]ASI_ERR_INJ |
| 284 | ta T_CHANGE_NONHPRIV |
| 285 | setx TGT1, %g1, %l4 |
| 286 | setx user_data_begin_000, %g1, %l3 |
| 287 | GO_BACK: brz,a %i1, TGT1 !! load entry in ITLB |
| 288 | TGT0: add %g0, %g7, %g5 !! dummy inst |
| 289 | TGT1: add %g0, 1, %i1 |
| 290 | brz,a %i0, GO_BACK |
| 291 | ld [%l3+1], %g1 !cause mem_addr_not_aligned trap |
| 292 | cmp %i0, 1 |
| 293 | bnz FAIL |
| 294 | nop |
| 295 | EXIT_GOOD |
| 296 | nop |
| 297 | |
| 298 | FAIL: EXIT_BAD |
| 299 | nop |
| 300 | |
| 301 | attr_data { |
| 302 | Name = .My_User_Section_4v001, |
| 303 | part_0_ctx_nonzero_tsb_config_1, |
| 304 | VA = MY_USER_DATA_VA001, |
| 305 | RA = MY_USER_DATA_RA001, |
| 306 | PA = ra2pa(MY_USER_DATA_RA001, 0), |
| 307 | TTE_Context = PCONTEXT, |
| 308 | TTE_V = 1, |
| 309 | TTE_NFO = 0, |
| 310 | TTE_L = 0, |
| 311 | TTE_Soft = 0, |
| 312 | TTE_IE = 0, |
| 313 | TTE_E = 0, |
| 314 | TTE_CP = 1, |
| 315 | TTE_CV = 0, |
| 316 | TTE_P = 0, |
| 317 | TTE_EP = 0, |
| 318 | TTE_W = 1, |
| 319 | TTE_SW1 = 0, |
| 320 | TTE_SW0 = 0, |
| 321 | TTE_RSVD1 = 0, |
| 322 | TTE_Size = 0, |
| 323 | } |
| 324 | attr_data { |
| 325 | NAME = .My_User_Section_4v001, |
| 326 | hypervisor |
| 327 | } |
| 328 | |
| 329 | .data |
| 330 | .global user_data_begin_001 |
| 331 | user_data_begin_001: |
| 332 | .word 0x10731 |
| 333 | .word 0xd027 |
| 334 | .word 0x1350e |
| 335 | .word 0x10e9d |
| 336 | |
| 337 | |
| 338 | .global DATA_ACCESS_ERROR_HANDLER |
| 339 | .global INST_ACCESS_ERROR_HANDLER |
| 340 | |
| 341 | SECTION .HTRAPS |
| 342 | .text |
| 343 | DATA_ACCESS_ERROR_HANDLER: |
| 344 | add %g0, SFSR_VA, %g5 ! |
| 345 | ldxa [%g5]ASI_DSFSR, %o1 ! |
| 346 | cmp %o1, 0x3 |
| 347 | bne FAIL |
| 348 | add %g0, SFAR_VA, %g6 !!g6 has sfar va |
| 349 | ldxa [%g6]ASI_SFAR, %o1 |
| 350 | cmp %o1, %l3 |
| 351 | bne FAIL |
| 352 | //issue demap pg |
| 353 | xor %o1, 0x1fff, %o1 |
| 354 | stxa %g0, [%o1] ASI_DMMU_DEMAP |
| 355 | //disable errors |
| 356 | add %g0, CERER_VA, %g3 |
| 357 | stxa %g0, [%g3]ASI_CERER |
| 358 | add %g0, 1, %i0 ! |
| 359 | retry |
| 360 | nop |
| 361 | |
| 362 | |
| 363 | INST_ACCESS_ERROR_HANDLER: |
| 364 | add %g0, SFSR_VA, %g5 ! |
| 365 | ldxa [%g5]ASI_ISFSR, %o1 ! |
| 366 | cmp %o1, 0x3 |
| 367 | bne FAIL |
| 368 | stxa %g0, [%g5]ASI_ISFSR |
| 369 | add %g0, SFAR_VA, %g6 !!g6 has sfar va |
| 370 | ldxa [%g6]ASI_SFAR, %o1 |
| 371 | !!brnz %o1, FAIL |
| 372 | rdpr %tpc, %o1 |
| 373 | cmp %o1, %l4 !! cmp pc matches the expected pc |
| 374 | bne FAIL |
| 375 | !issue demap pg |
| 376 | srlx %o1, 0xd, %o1 |
| 377 | sllx %o1, 0xd, %o1 |
| 378 | stxa %g0, [%o1] ASI_IMMU_DEMAP |
| 379 | !disable errors |
| 380 | add %g0, CERER_VA, %g3 |
| 381 | stxa %g0, [%g3]ASI_CERER |
| 382 | add %g0, 1, %i0 ! |
| 383 | retry |
| 384 | |
| 385 | FAIL: EXIT_BAD |
| 386 | nop |