| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: pmu_ccx_sel5_0x04_thAll.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define PIC_COUNT_th0 0x6 |
| 39 | #define PIC_COUNT_th1 0x9 |
| 40 | #define PIC_COUNT_th2 0xa |
| 41 | #define PIC_COUNT_th3 0xf |
| 42 | #define PIC_COUNT_th4 0x3 |
| 43 | #define PIC_COUNT_th5 0x2 |
| 44 | #define PIC_COUNT_th6 0xe |
| 45 | #define PIC_COUNT_th7 0x1 |
| 46 | |
| 47 | #define MAIN_PAGE_HV_ALSO |
| 48 | #include "hboot.s" |
| 49 | |
| 50 | .text |
| 51 | .global main |
| 52 | |
| 53 | main: |
| 54 | |
| 55 | ! Get TID |
| 56 | ta T_RD_THID |
| 57 | mov %o1, %l6 |
| 58 | nop |
| 59 | |
| 60 | cmp %l6, 0 |
| 61 | be thread_0 |
| 62 | nop |
| 63 | |
| 64 | cmp %l6, 1 |
| 65 | be thread_1 |
| 66 | nop |
| 67 | |
| 68 | cmp %l6, 2 |
| 69 | be thread_2 |
| 70 | nop |
| 71 | |
| 72 | cmp %l6, 3 |
| 73 | be thread_3 |
| 74 | nop |
| 75 | |
| 76 | cmp %l6, 4 |
| 77 | be thread_4 |
| 78 | nop |
| 79 | |
| 80 | cmp %l6, 5 |
| 81 | be thread_5 |
| 82 | nop |
| 83 | |
| 84 | cmp %l6, 6 |
| 85 | be thread_6 |
| 86 | nop |
| 87 | |
| 88 | cmp %l6, 7 |
| 89 | be thread_7 |
| 90 | nop |
| 91 | |
| 92 | thread_0: |
| 93 | |
| 94 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 95 | |
| 96 | !# Switch to hpriv mode |
| 97 | ta T_CHANGE_HPRIV |
| 98 | !# Check to make sure pic is zero |
| 99 | rd %pic, %g4 |
| 100 | cmp %g0, %g4 |
| 101 | bne,pn %icc, fail |
| 102 | nop |
| 103 | |
| 104 | !# Setup PCR Register |
| 105 | set 0x0000000020414108, %g2 |
| 106 | wr %g2, %g0, %pcr |
| 107 | |
| 108 | or %g0, %g0, %g3 |
| 109 | ccx_ld_th0: |
| 110 | umul %g3, 32, %g4 |
| 111 | setx DATA0_0x0, %g1, %l5 |
| 112 | ldx [%l5 + %g4], %l1 |
| 113 | add %g3, 1 , %g3 |
| 114 | cmp %g3, PIC_COUNT_th0 |
| 115 | bne,pn %xcc, ccx_ld_th0 |
| 116 | nop |
| 117 | |
| 118 | membar #Sync |
| 119 | |
| 120 | check_pic_th0: |
| 121 | rd %pic, %g4 |
| 122 | mov %g4, %i7 |
| 123 | cmp %g4, PIC_COUNT_th0 |
| 124 | bne,pn %icc, fail |
| 125 | nop |
| 126 | |
| 127 | check_pic1_isZero_th0: |
| 128 | setx 0xffffffff00000000, %l5, %l0 |
| 129 | and %i7, %l0, %i7 |
| 130 | cmp %i7, 0x0 |
| 131 | bne,pn %icc, fail |
| 132 | nop |
| 133 | |
| 134 | EXIT_GOOD |
| 135 | |
| 136 | thread_1: |
| 137 | |
| 138 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 139 | |
| 140 | !# Switch to hpriv mode |
| 141 | ta T_CHANGE_HPRIV |
| 142 | !# Check to make sure pic is zero |
| 143 | rd %pic, %g4 |
| 144 | cmp %g0, %g4 |
| 145 | bne,pn %icc, fail |
| 146 | nop |
| 147 | |
| 148 | !# Setup PCR Register |
| 149 | set 0x0000000020414108, %g2 |
| 150 | wr %g2, %g0, %pcr |
| 151 | |
| 152 | or %g0, %g0, %g3 |
| 153 | ccx_ld_th1: |
| 154 | umul %g3, 32, %g4 |
| 155 | setx DATA1_0x0, %g1, %l5 |
| 156 | ldx [%l5 + %g4], %l1 |
| 157 | add %g3, 1 , %g3 |
| 158 | cmp %g3, PIC_COUNT_th1 |
| 159 | bne,pn %xcc, ccx_ld_th1 |
| 160 | nop |
| 161 | |
| 162 | membar #Sync |
| 163 | |
| 164 | check_pic_th1: |
| 165 | rd %pic, %g4 |
| 166 | mov %g4, %i7 |
| 167 | cmp %g4, PIC_COUNT_th1 |
| 168 | bne,pn %icc, fail |
| 169 | nop |
| 170 | |
| 171 | check_pic1_isZero_th1: |
| 172 | setx 0xffffffff00000000, %l5, %l0 |
| 173 | and %i7, %l0, %i7 |
| 174 | cmp %i7, 0x0 |
| 175 | bne,pn %icc, fail |
| 176 | nop |
| 177 | |
| 178 | EXIT_GOOD |
| 179 | |
| 180 | thread_2: |
| 181 | |
| 182 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 183 | |
| 184 | !# Switch to hpriv mode |
| 185 | ta T_CHANGE_HPRIV |
| 186 | !# Check to make sure pic is zero |
| 187 | rd %pic, %g4 |
| 188 | cmp %g0, %g4 |
| 189 | bne,pn %icc, fail |
| 190 | nop |
| 191 | |
| 192 | !# Setup PCR Register |
| 193 | set 0x0000000020414108, %g2 |
| 194 | wr %g2, %g0, %pcr |
| 195 | |
| 196 | or %g0, %g0, %g3 |
| 197 | ccx_ld_th2: |
| 198 | umul %g3, 32, %g4 |
| 199 | setx DATA2_0x0, %g1, %l5 |
| 200 | ldx [%l5 + %g4], %l1 |
| 201 | add %g3, 1 , %g3 |
| 202 | cmp %g3, PIC_COUNT_th2 |
| 203 | bne,pn %xcc, ccx_ld_th2 |
| 204 | nop |
| 205 | |
| 206 | membar #Sync |
| 207 | |
| 208 | check_pic_th2: |
| 209 | rd %pic, %g4 |
| 210 | mov %g4, %i7 |
| 211 | cmp %g4, PIC_COUNT_th2 |
| 212 | bne,pn %icc, fail |
| 213 | nop |
| 214 | |
| 215 | check_pic1_isZero_th2: |
| 216 | setx 0xffffffff00000000, %l5, %l0 |
| 217 | and %i7, %l0, %i7 |
| 218 | cmp %i7, 0x0 |
| 219 | bne,pn %icc, fail |
| 220 | nop |
| 221 | |
| 222 | EXIT_GOOD |
| 223 | |
| 224 | thread_3: |
| 225 | |
| 226 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 227 | |
| 228 | !# Switch to hpriv mode |
| 229 | ta T_CHANGE_HPRIV |
| 230 | !# Check to make sure pic is zero |
| 231 | rd %pic, %g4 |
| 232 | cmp %g0, %g4 |
| 233 | bne,pn %icc, fail |
| 234 | nop |
| 235 | |
| 236 | !# Setup PCR Register |
| 237 | set 0x0000000020414108, %g2 |
| 238 | wr %g2, %g0, %pcr |
| 239 | |
| 240 | or %g0, %g0, %g3 |
| 241 | ccx_ld_th3: |
| 242 | umul %g3, 32, %g4 |
| 243 | setx DATA3_0x0, %g1, %l5 |
| 244 | ldx [%l5 + %g4], %l1 |
| 245 | add %g3, 1 , %g3 |
| 246 | cmp %g3, PIC_COUNT_th3 |
| 247 | bne,pn %xcc, ccx_ld_th3 |
| 248 | nop |
| 249 | |
| 250 | membar #Sync |
| 251 | |
| 252 | check_pic_th3: |
| 253 | rd %pic, %g4 |
| 254 | mov %g4, %i7 |
| 255 | cmp %g4, PIC_COUNT_th3 |
| 256 | bne,pn %icc, fail |
| 257 | nop |
| 258 | |
| 259 | check_pic1_isZero_th3: |
| 260 | setx 0xffffffff00000000, %l5, %l0 |
| 261 | and %i7, %l0, %i7 |
| 262 | cmp %i7, 0x0 |
| 263 | bne,pn %icc, fail |
| 264 | nop |
| 265 | |
| 266 | EXIT_GOOD |
| 267 | |
| 268 | |
| 269 | thread_4: |
| 270 | |
| 271 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 272 | |
| 273 | !# Switch to hpriv mode |
| 274 | ta T_CHANGE_HPRIV |
| 275 | !# Check to make sure pic is zero |
| 276 | rd %pic, %g4 |
| 277 | cmp %g0, %g4 |
| 278 | bne,pn %icc, fail |
| 279 | nop |
| 280 | |
| 281 | !# Setup PCR Register |
| 282 | set 0x0000000020414108, %g2 |
| 283 | wr %g2, %g0, %pcr |
| 284 | |
| 285 | or %g0, %g0, %g3 |
| 286 | ccx_ld_th4: |
| 287 | umul %g3, 32, %g4 |
| 288 | setx DATA4_0x0, %g1, %l5 |
| 289 | ldx [%l5 + %g4], %l1 |
| 290 | add %g3, 1 , %g3 |
| 291 | cmp %g3, PIC_COUNT_th4 |
| 292 | bne,pn %xcc, ccx_ld_th4 |
| 293 | nop |
| 294 | |
| 295 | membar #Sync |
| 296 | |
| 297 | check_pic_th4: |
| 298 | rd %pic, %g4 |
| 299 | mov %g4, %i7 |
| 300 | cmp %g4, PIC_COUNT_th4 |
| 301 | bne,pn %icc, fail |
| 302 | nop |
| 303 | |
| 304 | check_pic1_isZero_th4: |
| 305 | setx 0xffffffff00000000, %l5, %l0 |
| 306 | and %i7, %l0, %i7 |
| 307 | cmp %i7, 0x0 |
| 308 | bne,pn %icc, fail |
| 309 | nop |
| 310 | |
| 311 | EXIT_GOOD |
| 312 | |
| 313 | thread_5: |
| 314 | |
| 315 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 316 | |
| 317 | !# Switch to hpriv mode |
| 318 | ta T_CHANGE_HPRIV |
| 319 | !# Check to make sure pic is zero |
| 320 | rd %pic, %g4 |
| 321 | cmp %g0, %g4 |
| 322 | bne,pn %icc, fail |
| 323 | nop |
| 324 | |
| 325 | !# Setup PCR Register |
| 326 | set 0x0000000020414108, %g2 |
| 327 | wr %g2, %g0, %pcr |
| 328 | |
| 329 | or %g0, %g0, %g3 |
| 330 | ccx_ld_th5: |
| 331 | umul %g3, 32, %g4 |
| 332 | setx DATA5_0x0, %g1, %l5 |
| 333 | ldx [%l5 + %g4], %l1 |
| 334 | add %g3, 1 , %g3 |
| 335 | cmp %g3, PIC_COUNT_th5 |
| 336 | bne,pn %xcc, ccx_ld_th5 |
| 337 | nop |
| 338 | |
| 339 | membar #Sync |
| 340 | |
| 341 | check_pic_th5: |
| 342 | rd %pic, %g4 |
| 343 | mov %g4, %i7 |
| 344 | cmp %g4, PIC_COUNT_th5 |
| 345 | bne,pn %icc, fail |
| 346 | nop |
| 347 | |
| 348 | check_pic1_isZero_th5: |
| 349 | setx 0xffffffff00000000, %l5, %l0 |
| 350 | and %i7, %l0, %i7 |
| 351 | cmp %i7, 0x0 |
| 352 | bne,pn %icc, fail |
| 353 | nop |
| 354 | |
| 355 | EXIT_GOOD |
| 356 | |
| 357 | thread_6: |
| 358 | |
| 359 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 360 | |
| 361 | !# Switch to hpriv mode |
| 362 | ta T_CHANGE_HPRIV |
| 363 | !# Check to make sure pic is zero |
| 364 | rd %pic, %g4 |
| 365 | cmp %g0, %g4 |
| 366 | bne,pn %icc, fail |
| 367 | nop |
| 368 | |
| 369 | !# Setup PCR Register |
| 370 | set 0x0000000020414108, %g2 |
| 371 | wr %g2, %g0, %pcr |
| 372 | |
| 373 | or %g0, %g0, %g3 |
| 374 | ccx_ld_th6: |
| 375 | umul %g3, 32, %g4 |
| 376 | setx DATA6_0x0, %g1, %l5 |
| 377 | ldx [%l5 + %g4], %l1 |
| 378 | add %g3, 1 , %g3 |
| 379 | cmp %g3, PIC_COUNT_th6 |
| 380 | bne,pn %xcc, ccx_ld_th6 |
| 381 | nop |
| 382 | |
| 383 | membar #Sync |
| 384 | |
| 385 | check_pic_th6: |
| 386 | rd %pic, %g4 |
| 387 | mov %g4, %i7 |
| 388 | cmp %g4, PIC_COUNT_th6 |
| 389 | bne,pn %icc, fail |
| 390 | nop |
| 391 | |
| 392 | check_pic1_isZero_th6: |
| 393 | setx 0xffffffff00000000, %l5, %l0 |
| 394 | and %i7, %l0, %i7 |
| 395 | cmp %i7, 0x0 |
| 396 | bne,pn %icc, fail |
| 397 | nop |
| 398 | |
| 399 | EXIT_GOOD |
| 400 | |
| 401 | thread_7: |
| 402 | |
| 403 | setx 0x0000deadbeefbad0, %l5, %l4 |
| 404 | |
| 405 | !# Switch to hpriv mode |
| 406 | ta T_CHANGE_HPRIV |
| 407 | !# Check to make sure pic is zero |
| 408 | rd %pic, %g4 |
| 409 | cmp %g0, %g4 |
| 410 | bne,pn %icc, fail |
| 411 | nop |
| 412 | |
| 413 | !# Setup PCR Register |
| 414 | set 0x0000000020414108, %g2 |
| 415 | wr %g2, %g0, %pcr |
| 416 | |
| 417 | or %g0, %g0, %g3 |
| 418 | ccx_ld_th7: |
| 419 | umul %g3, 32, %g4 |
| 420 | setx DATA7_0x0, %g1, %l5 |
| 421 | ldx [%l5 + %g4], %l1 |
| 422 | add %g3, 1 , %g3 |
| 423 | cmp %g3, PIC_COUNT_th7 |
| 424 | bne,pn %xcc, ccx_ld_th7 |
| 425 | nop |
| 426 | |
| 427 | membar #Sync |
| 428 | |
| 429 | check_pic_th7: |
| 430 | rd %pic, %g4 |
| 431 | mov %g4, %i7 |
| 432 | cmp %g4, PIC_COUNT_th7 |
| 433 | bne,pn %icc, fail |
| 434 | nop |
| 435 | |
| 436 | check_pic1_isZero_th7: |
| 437 | setx 0xffffffff00000000, %l5, %l0 |
| 438 | and %i7, %l0, %i7 |
| 439 | cmp %i7, 0x0 |
| 440 | bne,pn %icc, fail |
| 441 | nop |
| 442 | |
| 443 | EXIT_GOOD |
| 444 | |
| 445 | fail: |
| 446 | EXIT_BAD |
| 447 | |
| 448 | .data |
| 449 | user_data_start: |
| 450 | scratch_area: |
| 451 | |
| 452 | !data for thread_0 |
| 453 | .align 32 |
| 454 | DATA0_0x0: |
| 455 | .xword 0x0000000000000000 |
| 456 | .align 32 |
| 457 | DATA0_0x1: |
| 458 | .xword 0x1111111111111111 |
| 459 | .align 32 |
| 460 | DATA0_0x2: |
| 461 | .xword 0x2222222222222222 |
| 462 | .align 32 |
| 463 | DATA0_0x3: |
| 464 | .xword 0x3333333333333333 |
| 465 | .align 32 |
| 466 | DATA0_0x4: |
| 467 | .xword 0x4444444444444444 |
| 468 | .align 32 |
| 469 | DATA0_0x5: |
| 470 | .xword 0x5555555555555555 |
| 471 | .align 32 |
| 472 | DATA0_0x6: |
| 473 | .xword 0x6666666666666666 |
| 474 | .align 32 |
| 475 | DATA0_0x7: |
| 476 | .xword 0x7777777777777777 |
| 477 | .align 32 |
| 478 | DATA0_0x8: |
| 479 | .xword 0x8888888888888888 |
| 480 | .align 32 |
| 481 | DATA0_0x9: |
| 482 | .xword 0x9999999999999999 |
| 483 | .align 32 |
| 484 | DATA0_0xa: |
| 485 | .xword 0xaaaaaaaaaaaaaaaa |
| 486 | .align 32 |
| 487 | DATA0_0xb: |
| 488 | .xword 0xbbbbbbbbbbbbbbbb |
| 489 | .align 32 |
| 490 | DATA0_0xc: |
| 491 | .xword 0xcccccccccccccccc |
| 492 | .align 32 |
| 493 | DATA0_0xd: |
| 494 | .xword 0xdddddddddddddddd |
| 495 | .align 32 |
| 496 | DATA0_0xe: |
| 497 | .xword 0xeeeeeeeeeeeeeeee |
| 498 | .align 32 |
| 499 | DATA0_0xf: |
| 500 | .xword 0xffffffffffffffff |
| 501 | |
| 502 | !data for thread_1 |
| 503 | .align 32 |
| 504 | DATA1_0x0: |
| 505 | .xword 0x0000000000000000 |
| 506 | .align 32 |
| 507 | DATA1_0x1: |
| 508 | .xword 0x1111111111111111 |
| 509 | .align 32 |
| 510 | DATA1_0x2: |
| 511 | .xword 0x2222222222222222 |
| 512 | .align 32 |
| 513 | DATA1_0x3: |
| 514 | .xword 0x3333333333333333 |
| 515 | .align 32 |
| 516 | DATA1_0x4: |
| 517 | .xword 0x4444444444444444 |
| 518 | .align 32 |
| 519 | DATA1_0x5: |
| 520 | .xword 0x5555555555555555 |
| 521 | .align 32 |
| 522 | DATA1_0x6: |
| 523 | .xword 0x6666666666666666 |
| 524 | .align 32 |
| 525 | DATA1_0x7: |
| 526 | .xword 0x7777777777777777 |
| 527 | .align 32 |
| 528 | DATA1_0x8: |
| 529 | .xword 0x8888888888888888 |
| 530 | .align 32 |
| 531 | DATA1_0x9: |
| 532 | .xword 0x9999999999999999 |
| 533 | .align 32 |
| 534 | DATA1_0xa: |
| 535 | .xword 0xaaaaaaaaaaaaaaaa |
| 536 | .align 32 |
| 537 | DATA1_0xb: |
| 538 | .xword 0xbbbbbbbbbbbbbbbb |
| 539 | .align 32 |
| 540 | DATA1_0xc: |
| 541 | .xword 0xcccccccccccccccc |
| 542 | .align 32 |
| 543 | DATA1_0xd: |
| 544 | .xword 0xdddddddddddddddd |
| 545 | .align 32 |
| 546 | DATA1_0xe: |
| 547 | .xword 0xeeeeeeeeeeeeeeee |
| 548 | .align 32 |
| 549 | DATA1_0xf: |
| 550 | .xword 0xffffffffffffffff |
| 551 | |
| 552 | !data for thread_2 |
| 553 | .align 32 |
| 554 | DATA2_0x0: |
| 555 | .xword 0x0000000000000000 |
| 556 | .align 32 |
| 557 | DATA2_0x1: |
| 558 | .xword 0x1111111111111111 |
| 559 | .align 32 |
| 560 | DATA2_0x2: |
| 561 | .xword 0x2222222222222222 |
| 562 | .align 32 |
| 563 | DATA2_0x3: |
| 564 | .xword 0x3333333333333333 |
| 565 | .align 32 |
| 566 | DATA2_0x4: |
| 567 | .xword 0x4444444444444444 |
| 568 | .align 32 |
| 569 | DATA2_0x5: |
| 570 | .xword 0x5555555555555555 |
| 571 | .align 32 |
| 572 | DATA2_0x6: |
| 573 | .xword 0x6666666666666666 |
| 574 | .align 32 |
| 575 | DATA2_0x7: |
| 576 | .xword 0x7777777777777777 |
| 577 | .align 32 |
| 578 | DATA2_0x8: |
| 579 | .xword 0x8888888888888888 |
| 580 | .align 32 |
| 581 | DATA2_0x9: |
| 582 | .xword 0x9999999999999999 |
| 583 | .align 32 |
| 584 | DATA2_0xa: |
| 585 | .xword 0xaaaaaaaaaaaaaaaa |
| 586 | .align 32 |
| 587 | DATA2_0xb: |
| 588 | .xword 0xbbbbbbbbbbbbbbbb |
| 589 | .align 32 |
| 590 | DATA2_0xc: |
| 591 | .xword 0xcccccccccccccccc |
| 592 | .align 32 |
| 593 | DATA2_0xd: |
| 594 | .xword 0xdddddddddddddddd |
| 595 | .align 32 |
| 596 | DATA2_0xe: |
| 597 | .xword 0xeeeeeeeeeeeeeeee |
| 598 | .align 32 |
| 599 | DATA2_0xf: |
| 600 | .xword 0xffffffffffffffff |
| 601 | |
| 602 | !data for thread_3 |
| 603 | .align 32 |
| 604 | DATA3_0x0: |
| 605 | .xword 0x0000000000000000 |
| 606 | .align 32 |
| 607 | DATA3_0x1: |
| 608 | .xword 0x1111111111111111 |
| 609 | .align 32 |
| 610 | DATA3_0x2: |
| 611 | .xword 0x2222222222222222 |
| 612 | .align 32 |
| 613 | DATA3_0x3: |
| 614 | .xword 0x3333333333333333 |
| 615 | .align 32 |
| 616 | DATA3_0x4: |
| 617 | .xword 0x4444444444444444 |
| 618 | .align 32 |
| 619 | DATA3_0x5: |
| 620 | .xword 0x5555555555555555 |
| 621 | .align 32 |
| 622 | DATA3_0x6: |
| 623 | .xword 0x6666666666666666 |
| 624 | .align 32 |
| 625 | DATA3_0x7: |
| 626 | .xword 0x7777777777777777 |
| 627 | .align 32 |
| 628 | DATA3_0x8: |
| 629 | .xword 0x8888888888888888 |
| 630 | .align 32 |
| 631 | DATA3_0x9: |
| 632 | .xword 0x9999999999999999 |
| 633 | .align 32 |
| 634 | DATA3_0xa: |
| 635 | .xword 0xaaaaaaaaaaaaaaaa |
| 636 | .align 32 |
| 637 | DATA3_0xb: |
| 638 | .xword 0xbbbbbbbbbbbbbbbb |
| 639 | .align 32 |
| 640 | DATA3_0xc: |
| 641 | .xword 0xcccccccccccccccc |
| 642 | .align 32 |
| 643 | DATA3_0xd: |
| 644 | .xword 0xdddddddddddddddd |
| 645 | .align 32 |
| 646 | DATA3_0xe: |
| 647 | .xword 0xeeeeeeeeeeeeeeee |
| 648 | .align 32 |
| 649 | DATA3_0xf: |
| 650 | .xword 0xffffffffffffffff |
| 651 | |
| 652 | !data for thread_4 |
| 653 | .align 32 |
| 654 | DATA4_0x0: |
| 655 | .xword 0x0000000000000000 |
| 656 | .align 32 |
| 657 | DATA4_0x1: |
| 658 | .xword 0x1111111111111111 |
| 659 | .align 32 |
| 660 | DATA4_0x2: |
| 661 | .xword 0x2222222222222222 |
| 662 | .align 32 |
| 663 | DATA4_0x3: |
| 664 | .xword 0x3333333333333333 |
| 665 | .align 32 |
| 666 | DATA4_0x4: |
| 667 | .xword 0x4444444444444444 |
| 668 | .align 32 |
| 669 | DATA4_0x5: |
| 670 | .xword 0x5555555555555555 |
| 671 | .align 32 |
| 672 | DATA4_0x6: |
| 673 | .xword 0x6666666666666666 |
| 674 | .align 32 |
| 675 | DATA4_0x7: |
| 676 | .xword 0x7777777777777777 |
| 677 | .align 32 |
| 678 | DATA4_0x8: |
| 679 | .xword 0x8888888888888888 |
| 680 | .align 32 |
| 681 | DATA4_0x9: |
| 682 | .xword 0x9999999999999999 |
| 683 | .align 32 |
| 684 | DATA4_0xa: |
| 685 | .xword 0xaaaaaaaaaaaaaaaa |
| 686 | .align 32 |
| 687 | DATA4_0xb: |
| 688 | .xword 0xbbbbbbbbbbbbbbbb |
| 689 | .align 32 |
| 690 | DATA4_0xc: |
| 691 | .xword 0xcccccccccccccccc |
| 692 | .align 32 |
| 693 | DATA4_0xd: |
| 694 | .xword 0xdddddddddddddddd |
| 695 | .align 32 |
| 696 | DATA4_0xe: |
| 697 | .xword 0xeeeeeeeeeeeeeeee |
| 698 | .align 32 |
| 699 | DATA4_0xf: |
| 700 | .xword 0xffffffffffffffff |
| 701 | |
| 702 | !data for thread_5 |
| 703 | .align 32 |
| 704 | DATA5_0x0: |
| 705 | .xword 0x0000000000000000 |
| 706 | .align 32 |
| 707 | DATA5_0x1: |
| 708 | .xword 0x1111111111111111 |
| 709 | .align 32 |
| 710 | DATA5_0x2: |
| 711 | .xword 0x2222222222222222 |
| 712 | .align 32 |
| 713 | DATA5_0x3: |
| 714 | .xword 0x3333333333333333 |
| 715 | .align 32 |
| 716 | DATA5_0x4: |
| 717 | .xword 0x4444444444444444 |
| 718 | .align 32 |
| 719 | DATA5_0x5: |
| 720 | .xword 0x5555555555555555 |
| 721 | .align 32 |
| 722 | DATA5_0x6: |
| 723 | .xword 0x6666666666666666 |
| 724 | .align 32 |
| 725 | DATA5_0x7: |
| 726 | .xword 0x7777777777777777 |
| 727 | .align 32 |
| 728 | DATA5_0x8: |
| 729 | .xword 0x8888888888888888 |
| 730 | .align 32 |
| 731 | DATA5_0x9: |
| 732 | .xword 0x9999999999999999 |
| 733 | .align 32 |
| 734 | DATA5_0xa: |
| 735 | .xword 0xaaaaaaaaaaaaaaaa |
| 736 | .align 32 |
| 737 | DATA5_0xb: |
| 738 | .xword 0xbbbbbbbbbbbbbbbb |
| 739 | .align 32 |
| 740 | DATA5_0xc: |
| 741 | .xword 0xcccccccccccccccc |
| 742 | .align 32 |
| 743 | DATA5_0xd: |
| 744 | .xword 0xdddddddddddddddd |
| 745 | .align 32 |
| 746 | DATA5_0xe: |
| 747 | .xword 0xeeeeeeeeeeeeeeee |
| 748 | .align 32 |
| 749 | DATA5_0xf: |
| 750 | .xword 0xffffffffffffffff |
| 751 | |
| 752 | !data for thread_6 |
| 753 | .align 32 |
| 754 | DATA6_0x0: |
| 755 | .xword 0x0000000000000000 |
| 756 | .align 32 |
| 757 | DATA6_0x1: |
| 758 | .xword 0x1111111111111111 |
| 759 | .align 32 |
| 760 | DATA6_0x2: |
| 761 | .xword 0x2222222222222222 |
| 762 | .align 32 |
| 763 | DATA6_0x3: |
| 764 | .xword 0x3333333333333333 |
| 765 | .align 32 |
| 766 | DATA6_0x4: |
| 767 | .xword 0x4444444444444444 |
| 768 | .align 32 |
| 769 | DATA6_0x5: |
| 770 | .xword 0x5555555555555555 |
| 771 | .align 32 |
| 772 | DATA6_0x6: |
| 773 | .xword 0x6666666666666666 |
| 774 | .align 32 |
| 775 | DATA6_0x7: |
| 776 | .xword 0x7777777777777777 |
| 777 | .align 32 |
| 778 | DATA6_0x8: |
| 779 | .xword 0x8888888888888888 |
| 780 | .align 32 |
| 781 | DATA6_0x9: |
| 782 | .xword 0x9999999999999999 |
| 783 | .align 32 |
| 784 | DATA6_0xa: |
| 785 | .xword 0xaaaaaaaaaaaaaaaa |
| 786 | .align 32 |
| 787 | DATA6_0xb: |
| 788 | .xword 0xbbbbbbbbbbbbbbbb |
| 789 | .align 32 |
| 790 | DATA6_0xc: |
| 791 | .xword 0xcccccccccccccccc |
| 792 | .align 32 |
| 793 | DATA6_0xd: |
| 794 | .xword 0xdddddddddddddddd |
| 795 | .align 32 |
| 796 | DATA6_0xe: |
| 797 | .xword 0xeeeeeeeeeeeeeeee |
| 798 | .align 32 |
| 799 | DATA6_0xf: |
| 800 | .xword 0xffffffffffffffff |
| 801 | |
| 802 | !data for thread_7 |
| 803 | .align 32 |
| 804 | DATA7_0x0: |
| 805 | .xword 0x0000000000000000 |
| 806 | .align 32 |
| 807 | DATA7_0x1: |
| 808 | .xword 0x1111111111111111 |
| 809 | .align 32 |
| 810 | DATA7_0x2: |
| 811 | .xword 0x2222222222222222 |
| 812 | .align 32 |
| 813 | DATA7_0x3: |
| 814 | .xword 0x3333333333333333 |
| 815 | .align 32 |
| 816 | DATA7_0x4: |
| 817 | .xword 0x4444444444444444 |
| 818 | .align 32 |
| 819 | DATA7_0x5: |
| 820 | .xword 0x5555555555555555 |
| 821 | .align 32 |
| 822 | DATA7_0x6: |
| 823 | .xword 0x6666666666666666 |
| 824 | .align 32 |
| 825 | DATA7_0x7: |
| 826 | .xword 0x7777777777777777 |
| 827 | .align 32 |
| 828 | DATA7_0x8: |
| 829 | .xword 0x8888888888888888 |
| 830 | .align 32 |
| 831 | DATA7_0x9: |
| 832 | .xword 0x9999999999999999 |
| 833 | .align 32 |
| 834 | DATA7_0xa: |
| 835 | .xword 0xaaaaaaaaaaaaaaaa |
| 836 | .align 32 |
| 837 | DATA7_0xb: |
| 838 | .xword 0xbbbbbbbbbbbbbbbb |
| 839 | .align 32 |
| 840 | DATA7_0xc: |
| 841 | .xword 0xcccccccccccccccc |
| 842 | .align 32 |
| 843 | DATA7_0xd: |
| 844 | .xword 0xdddddddddddddddd |
| 845 | .align 32 |
| 846 | DATA7_0xe: |
| 847 | .xword 0xeeeeeeeeeeeeeeee |
| 848 | .align 32 |
| 849 | DATA7_0xf: |
| 850 | .xword 0xffffffffffffffff |
| 851 | |
| 852 | .end |
| 853 | |
| 854 | #if 0 |
| 855 | #endif |