| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: tlu_rand5fc_8149597.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | # 518 "diag.j.pp" |
| 39 | #define IMMU_SKIP_IF_NO_TTE |
| 40 | #define DMMU_SKIP_IF_NO_TTE |
| 41 | #define PORTABLE_CORE |
| 42 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 43 | #define MAIN_PAGE_HV_ALSO |
| 44 | #define MAIN_PAGE_VA_IS_RA_ALSO |
| 45 | #define DISABLE_PART_LIMIT_CHECK |
| 46 | #define MAIN_PAGE_USE_CONFIG 3 |
| 47 | #define PART0_Z_TSB_SIZE_3 10 |
| 48 | #define PART0_Z_PAGE_SIZE_3 1 |
| 49 | #define PART0_NZ_TSB_SIZE_3 10 |
| 50 | #define PART0_NZ_PAGE_SIZE_3 1 |
| 51 | #define PART0_Z_TSB_SIZE_1 3 |
| 52 | #define PART0_NZ_TSB_SIZE_1 3 |
| 53 | |
| 54 | #define PART_0_BASE 0x0 |
| 55 | #define USER_PAGE_CUSTOM_MAP |
| 56 | #define MAIN_BASE_TEXT_VA 0x333000000 |
| 57 | #define MAIN_BASE_TEXT_RA 0x033000000 |
| 58 | #define MAIN_BASE_DATA_VA 0x379400000 |
| 59 | #define MAIN_BASE_DATA_RA 0x079400000 |
| 60 | #define HIGHVA_HIGHNUM 0x3 |
| 61 | |
| 62 | #d |
| 63 | # 544 "diag.j.pp" |
| 64 | #undef H_HT0_Instruction_Access_MMU_Error_0x71 |
| 65 | #define H_HT0_Instruction_Access_MMU_Error_0x71 inst_access_mmu_error_handler |
| 66 | #undef H_HT0_Instruction_access_error_0x0a |
| 67 | #define H_HT0_Instruction_access_error_0x0a inst_access_error_handler |
| 68 | #undef H_HT0_Internal_Processor_Error_0x29 |
| 69 | #define H_HT0_Internal_Processor_Error_0x29 int_proc_err_handler |
| 70 | #undef H_HT0_Data_Access_MMU_Error_0x72 |
| 71 | #define H_HT0_Data_Access_MMU_Error_0x72 data_access_mmu_error_handler |
| 72 | #undef H_HT0_Data_access_error_0x32 |
| 73 | #define H_HT0_Data_access_error_0x32 data_access_error_handler |
| 74 | #undef H_HT0_Hw_Corrected_Error_0x63 |
| 75 | #define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler |
| 76 | #undef H_HT0_Sw_Recoverable_Error_0x40 |
| 77 | #define H_HT0_Sw_Recoverable_Error_0x40 sw_recoverable_error_handler |
| 78 | #undef H_HT0_Store_Error_0x07 |
| 79 | #define H_HT0_Store_Error_0x07 store_error_handler |
| 80 | |
| 81 | #define DAE_SKIP_IF_SOCU_ERROR |
| 82 | # 5 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 83 | #ifndef T_HANDLER_RAND4_1 |
| 84 | #define T_HANDLER_RAND4_1 b .+16;\ |
| 85 | sdiv %r1, %r0, %l4;nop;nop |
| 86 | #endif |
| 87 | #ifndef T_HANDLER_RAND7_1 |
| 88 | #define T_HANDLER_RAND7_1 b .+28;\ |
| 89 | pdist %f4, %f6, %f20; \ |
| 90 | nop; nop ; nop; nop; illtrap |
| 91 | #endif |
| 92 | #ifndef T_HANDLER_RAND4_2 |
| 93 | #define T_HANDLER_RAND4_2 save %i7, %g0, %i7; \ |
| 94 | save %i7, %g0, %i7; \ |
| 95 | restore %i7, %g0, %i7;\ |
| 96 | restore %i7, %g0, %i7; |
| 97 | #endif |
| 98 | #ifndef T_HANDLER_RAND7_2 |
| 99 | #define T_HANDLER_RAND7_2 b .+8 ;\ |
| 100 | rdpr %pstate, %l2;\ |
| 101 | b .+8 ;\ |
| 102 | rdpr %tstate, %l3;\ |
| 103 | b .+12 ;\ |
| 104 | wrpr %l3, %r0, %tstate; nop |
| 105 | #endif |
| 106 | #ifndef T_HANDLER_RAND4_3 |
| 107 | #define T_HANDLER_RAND4_3 save %i7, %g0, %i7;\ |
| 108 | restore %i7, %g0, %i7;\ |
| 109 | save %i7, %g0, %i7; \ |
| 110 | restore %i7, %g0, %i7; |
| 111 | #endif |
| 112 | #ifndef T_HANDLER_RAND7_3 |
| 113 | #define T_HANDLER_RAND7_3 b .+8 ;\ |
| 114 | rdpr %tnpc, %l2;\ |
| 115 | and %l2, 0xfc0, %l2;\ |
| 116 | add %i7, %l2, %l2;\ |
| 117 | stda %f16,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY ;\ |
| 118 | b .+8 ;\ |
| 119 | stda %f0,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE ; |
| 120 | #endif |
| 121 | #ifndef T_HANDLER_RAND4_4 |
| 122 | #define T_HANDLER_RAND4_4 b .+4 ; b .+4; b .+4; b .+4 |
| 123 | #endif |
| 124 | #ifndef T_HANDLER_RAND7_4 |
| 125 | #define T_HANDLER_RAND7_4 b .+8;\ |
| 126 | save %i7, %g0, %i7; \ |
| 127 | b,a .+8;\ |
| 128 | b .+12;\ |
| 129 | stw %i7, [%i7];\ |
| 130 | b .-8;;\ |
| 131 | restore %i7, %g0, %i7; |
| 132 | |
| 133 | #endif |
| 134 | #ifndef T_HANDLER_RAND4_5 |
| 135 | #define T_HANDLER_RAND4_5 ldda [%r31]ASI_NUCLEUS_QUAD_LDD, %l4;\ |
| 136 | sdiv %l4, %l5, %l7;\ |
| 137 | add %r31, 128, %l5;\ |
| 138 | stda %l4, [%i7]ASI_BLOCK_PRIMARY_LITTLE; |
| 139 | #endif |
| 140 | #ifndef T_HANDLER_RAND7_5 |
| 141 | #define T_HANDLER_RAND7_5 save %i7, %g0, %i7;\ |
| 142 | rdpr %tnpc, %l2;\ |
| 143 | wrpr %l2, %tpc;\ |
| 144 | add %l2, 4, %l2;\ |
| 145 | wrpr %l2, %tnpc;\ |
| 146 | restore %i7, %g0, %i7;\ |
| 147 | retry; |
| 148 | #endif |
| 149 | #ifndef T_HANDLER_RAND4_6 |
| 150 | #define T_HANDLER_RAND4_6 ldda [%r31]ASI_BLOCK_AS_IF_USER_PRIMARY, %l2;\ |
| 151 | rd %fprs, %l2; \ |
| 152 | wr %l2, 0x4, %fprs ;\ |
| 153 | stda %f0,[%r31]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE; |
| 154 | #endif |
| 155 | #ifndef T_HANDLER_RAND7_6 |
| 156 | #define T_HANDLER_RAND7_6 umul %o4, 2, %o5;\ |
| 157 | rdpr %tnpc, %l2;\ |
| 158 | wrpr %l2, %tpc;\ |
| 159 | add %l2, 4, %l2;\ |
| 160 | wrpr %l2, %tnpc;\ |
| 161 | stw %l2, [%i7];\ |
| 162 | retry; |
| 163 | #endif |
| 164 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 165 | #ifndef HT_HANDLER_RAND4_1 |
| 166 | #define HT_HANDLER_RAND4_1 mov 0x80, %l3;\ |
| 167 | b .+12;\ |
| 168 | stxa %l3, [%l3]0x57 ;\ |
| 169 | nop |
| 170 | #endif |
| 171 | #ifndef HT_HANDLER_RAND7_1 |
| 172 | #define HT_HANDLER_RAND7_1 b .+28;\ |
| 173 | pdist %f4, %f4, %f20;\ |
| 174 | nop; nop ; nop; nop; illtrap |
| 175 | #endif |
| 176 | #ifndef HT_HANDLER_RAND4_2 |
| 177 | #define HT_HANDLER_RAND4_2 rdpr %tstate, %l2;\ |
| 178 | b .+12;\ |
| 179 | wrpr %l2, 0x800, %tstate;\ |
| 180 | nop; |
| 181 | #endif |
| 182 | #ifndef HT_HANDLER_RAND7_2 |
| 183 | #define HT_HANDLER_RAND7_2 b .+8 ;\ |
| 184 | rdhpr %hpstate, %l2;\ |
| 185 | b .+8 ;\ |
| 186 | rdhpr %htstate, %l3;\ |
| 187 | b .+12 ;\ |
| 188 | wrhpr %l3, %r0, %htstate; nop |
| 189 | #endif |
| 190 | #ifndef HT_HANDLER_RAND4_3 |
| 191 | #define HT_HANDLER_RAND4_3 stxa %l4, [%r31]ASI_AS_IF_USER_PRIMARY;\ |
| 192 | mov 0x80, %l3;\ |
| 193 | stxa %l3, [%l3]0x5f ;\ |
| 194 | b .+8 ;\ |
| 195 | ldxa [%r31]ASI_AS_IF_USER_PRIMARY, %l4; |
| 196 | #endif |
| 197 | #ifndef HT_HANDLER_RAND7_3 |
| 198 | #define HT_HANDLER_RAND7_3 b .+8 ;\ |
| 199 | rdpr %tnpc, %l2;\ |
| 200 | and %l2, 0xfc0, %l2;\ |
| 201 | add %i7, %l2, %l2;\ |
| 202 | stda %f16,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY ;\ |
| 203 | b .+8 ;\ |
| 204 | stda %f0,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE ; |
| 205 | #endif |
| 206 | #ifndef HT_HANDLER_RAND4_4 |
| 207 | #define HT_HANDLER_RAND4_4 ldda [%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE, %l3;\ |
| 208 | b .+12 ;\ |
| 209 | stxa %l3, [%g0]ASI_LSU_CONTROL; nop |
| 210 | #endif |
| 211 | #ifndef HT_HANDLER_RAND7_4 |
| 212 | #define HT_HANDLER_RAND7_4 rdpr %tnpc, %l3;\ |
| 213 | and %l3, 0xff, %l3;\ |
| 214 | sllx %l3, 26, %l3;\ |
| 215 | ldxa [%g0]0x45, %l4;\ |
| 216 | or %l3, %l4, %l3 ;\ |
| 217 | stxa %l3, [%g0]0x45 ;\ |
| 218 | nop; |
| 219 | #endif |
| 220 | #ifndef HT_HANDLER_RAND4_5 |
| 221 | #define HT_HANDLER_RAND4_5 ldda [%r31]ASI_NUCLEUS_QUAD_LDD, %l4;\ |
| 222 | sdiv %l4, %l5, %l6;\ |
| 223 | sdiv %l3, %l6, %l7;\ |
| 224 | stda %f32, [%r31]ASI_BLOCK_PRIMARY_LITTLE; |
| 225 | #endif |
| 226 | #ifndef HT_HANDLER_RAND7_5 |
| 227 | #define HT_HANDLER_RAND7_5 save %i7, %g0, %i7;\ |
| 228 | rdpr %tnpc, %l2;\ |
| 229 | wrpr %l2, %tpc;\ |
| 230 | add %l2, 4, %l2;\ |
| 231 | wrpr %l2, %tnpc;\ |
| 232 | restore %i7, %g0, %i7;\ |
| 233 | retry; |
| 234 | #endif |
| 235 | #ifndef HT_HANDLER_RAND4_6 |
| 236 | #define HT_HANDLER_RAND4_6 ld [%r31], %l2;\ |
| 237 | rd %fprs, %l2; \ |
| 238 | wr %l2, 0x4, %fprs ;\ |
| 239 | stda %f0,[%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE; |
| 240 | #endif |
| 241 | #ifndef HT_HANDLER_RAND7_6 |
| 242 | #define HT_HANDLER_RAND7_6 rdhpr %htstate, %o4;\ |
| 243 | rdpr %tnpc, %l2;\ |
| 244 | wrpr %l2, %tpc;\ |
| 245 | add %l2, 4, %l2;\ |
| 246 | wrpr %l2, %tnpc;\ |
| 247 | wrhpr %o4, %r0, %htstate;\ |
| 248 | retry; |
| 249 | #endif |
| 250 | |
| 251 | !!!!!!!!!!!!!!!!!!!!!!!!! |
| 252 | !! Disable trap checking |
| 253 | #define NO_TRAPCHECK |
| 254 | |
| 255 | ! Enable Traps |
| 256 | #define ENABLE_T1_Privileged_Opcode_0x11 |
| 257 | #define ENABLE_T1_Fp_Disabled_0x20 |
| 258 | #define ENABLE_HT0_Watchdog_Reset_0x02 |
| 259 | |
| 260 | #define FILL_TRAP_RETRY |
| 261 | #define SPILL_TRAP_RETRY |
| 262 | #define CLEAN_WIN_RETRY |
| 263 | |
| 264 | #define My_RED_Mode_Other_Reset |
| 265 | #define My_RED_Mode_Other_Reset \ |
| 266 | ba red_other_ext;\ |
| 267 | nop;retry;nop;nop;nop;nop;nop |
| 268 | |
| 269 | #define H_HT0_Software_Initiated_Reset_0x04 |
| 270 | #define SUN_H_HT0_Software_Initiated_Reset_0x04 \ |
| 271 | setx Software_Reset_Handler, %g1, %g2 ;\ |
| 272 | jmp %g2 ;\ |
| 273 | nop |
| 274 | # 198 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 275 | #define H_T1_Clean_Window_0x24 |
| 276 | #define SUN_H_T1_Clean_Window_0x24 \ |
| 277 | rdpr %cleanwin, %l1;\ |
| 278 | add %l1,1,%l1;\ |
| 279 | wrpr %l1, %g0, %cleanwin;\ |
| 280 | retry; nop; nop; nop; nop |
| 281 | |
| 282 | #define H_T1_Clean_Window_0x25 |
| 283 | #define SUN_H_T1_Clean_Window_0x25 \ |
| 284 | rdpr %cleanwin, %l1;\ |
| 285 | add %l1,1,%l1;\ |
| 286 | wrpr %l1, %g0, %cleanwin;\ |
| 287 | retry; nop; nop; nop; nop |
| 288 | |
| 289 | #define H_T1_Clean_Window_0x26 |
| 290 | #define SUN_H_T1_Clean_Window_0x26 \ |
| 291 | rdpr %cleanwin, %l1;\ |
| 292 | add %l1,1,%l1;\ |
| 293 | wrpr %l1, %g0, %cleanwin;\ |
| 294 | retry; nop; nop; nop; nop |
| 295 | |
| 296 | #define H_T1_Clean_Window_0x27 |
| 297 | #define SUN_H_T1_Clean_Window_0x27 \ |
| 298 | rdpr %cleanwin, %l1;\ |
| 299 | add %l1,1,%l1;\ |
| 300 | wrpr %l1, %g0, %cleanwin;\ |
| 301 | retry; nop; nop; nop; nop |
| 302 | # 227 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 303 | #define H_HT0_Tag_Overflow |
| 304 | #define My_HT0_Tag_Overflow \ |
| 305 | HT_HANDLER_RAND7_1 ;\ |
| 306 | done |
| 307 | |
| 308 | #define H_T0_Tag_Overflow |
| 309 | #define My_T0_Tag_Overflow \ |
| 310 | T_HANDLER_RAND7_2 ;\ |
| 311 | done |
| 312 | |
| 313 | #define H_T1_Tag_Overflow_0x23 |
| 314 | #define SUN_H_T1_Tag_Overflow_0x23 \ |
| 315 | T_HANDLER_RAND7_3 ;\ |
| 316 | done |
| 317 | |
| 318 | #define H_T0_Window_Spill_0_Normal_Trap |
| 319 | #define SUN_H_T0_Window_Spill_0_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 320 | |
| 321 | #define H_T0_Window_Spill_1_Normal_Trap |
| 322 | #define SUN_H_T0_Window_Spill_1_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 323 | |
| 324 | #define H_T0_Window_Spill_2_Normal_Trap |
| 325 | #define SUN_H_T0_Window_Spill_2_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 326 | |
| 327 | #define H_T0_Window_Spill_3_Normal_Trap |
| 328 | #define SUN_H_T0_Window_Spill_3_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 329 | |
| 330 | #define H_T0_Window_Spill_4_Normal_Trap |
| 331 | #define SUN_H_T0_Window_Spill_4_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 332 | |
| 333 | #define H_T0_Window_Spill_5_Normal_Trap |
| 334 | #define SUN_H_T0_Window_Spill_5_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 335 | |
| 336 | #define H_T0_Window_Spill_6_Normal_Trap |
| 337 | #define SUN_H_T0_Window_Spill_6_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 338 | |
| 339 | #define H_T0_Window_Spill_7_Normal_Trap |
| 340 | #define SUN_H_T0_Window_Spill_7_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 341 | |
| 342 | #define H_T0_Window_Spill_0_Other_Trap |
| 343 | #define SUN_H_T0_Window_Spill_0_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 344 | |
| 345 | #define H_T0_Window_Spill_1_Other_Trap |
| 346 | #define SUN_H_T0_Window_Spill_1_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 347 | |
| 348 | #define H_T0_Window_Spill_2_Other_Trap |
| 349 | #define SUN_H_T0_Window_Spill_2_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 350 | |
| 351 | #define H_T0_Window_Spill_3_Other_Trap |
| 352 | #define SUN_H_T0_Window_Spill_3_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 353 | |
| 354 | #define H_T0_Window_Spill_4_Other_Trap |
| 355 | #define SUN_H_T0_Window_Spill_4_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 356 | |
| 357 | #define H_T0_Window_Spill_5_Other_Trap |
| 358 | #define SUN_H_T0_Window_Spill_5_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 359 | |
| 360 | #define H_T0_Window_Spill_6_Other_Trap |
| 361 | #define SUN_H_T0_Window_Spill_6_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 362 | |
| 363 | #define H_T0_Window_Spill_7_Other_Trap |
| 364 | #define SUN_H_T0_Window_Spill_7_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 365 | |
| 366 | #define H_T0_Window_Fill_0_Normal_Trap |
| 367 | #define SUN_H_T0_Window_Fill_0_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 368 | |
| 369 | #define H_T0_Window_Fill_1_Normal_Trap |
| 370 | #define SUN_H_T0_Window_Fill_1_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 371 | |
| 372 | #define H_T0_Window_Fill_2_Normal_Trap |
| 373 | #define SUN_H_T0_Window_Fill_2_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 374 | |
| 375 | #define H_T0_Window_Fill_3_Normal_Trap |
| 376 | #define SUN_H_T0_Window_Fill_3_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 377 | |
| 378 | #define H_T0_Window_Fill_4_Normal_Trap |
| 379 | #define SUN_H_T0_Window_Fill_4_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 380 | |
| 381 | #define H_T0_Window_Fill_5_Normal_Trap |
| 382 | #define SUN_H_T0_Window_Fill_5_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 383 | |
| 384 | #define H_T0_Window_Fill_6_Normal_Trap |
| 385 | #define SUN_H_T0_Window_Fill_6_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 386 | |
| 387 | #define H_T0_Window_Fill_7_Normal_Trap |
| 388 | #define SUN_H_T0_Window_Fill_7_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 389 | |
| 390 | #define H_T0_Window_Fill_0_Other_Trap |
| 391 | #define SUN_H_T0_Window_Fill_0_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 392 | |
| 393 | #define H_T0_Window_Fill_1_Other_Trap |
| 394 | #define SUN_H_T0_Window_Fill_1_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 395 | |
| 396 | #define H_T0_Window_Fill_2_Other_Trap |
| 397 | #define SUN_H_T0_Window_Fill_2_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 398 | |
| 399 | #define H_T0_Window_Fill_3_Other_Trap |
| 400 | #define SUN_H_T0_Window_Fill_3_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 401 | |
| 402 | #define H_T0_Window_Fill_4_Other_Trap |
| 403 | #define SUN_H_T0_Window_Fill_4_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 404 | |
| 405 | #define H_T0_Window_Fill_5_Other_Trap |
| 406 | #define SUN_H_T0_Window_Fill_5_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 407 | |
| 408 | #define H_T0_Window_Fill_6_Other_Trap |
| 409 | #define SUN_H_T0_Window_Fill_6_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 410 | |
| 411 | #define H_T0_Window_Fill_7_Other_Trap |
| 412 | #define SUN_H_T0_Window_Fill_7_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 413 | # 339 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 414 | #define H_T1_Window_Spill_0_Normal_Trap |
| 415 | #define SUN_H_T1_Window_Spill_0_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 416 | |
| 417 | #define H_T1_Window_Spill_1_Normal_Trap |
| 418 | #define SUN_H_T1_Window_Spill_1_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 419 | |
| 420 | #define H_T1_Window_Spill_2_Normal_Trap |
| 421 | #define SUN_H_T1_Window_Spill_2_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 422 | |
| 423 | #define H_T1_Window_Spill_3_Normal_Trap |
| 424 | #define SUN_H_T1_Window_Spill_3_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 425 | |
| 426 | #define H_T1_Window_Spill_4_Normal_Trap |
| 427 | #define SUN_H_T1_Window_Spill_4_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 428 | |
| 429 | #define H_T1_Window_Spill_5_Normal_Trap |
| 430 | #define SUN_H_T1_Window_Spill_5_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 431 | |
| 432 | #define H_T1_Window_Spill_6_Normal_Trap |
| 433 | #define SUN_H_T1_Window_Spill_6_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 434 | |
| 435 | #define H_T1_Window_Spill_7_Normal_Trap |
| 436 | #define SUN_H_T1_Window_Spill_7_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 437 | |
| 438 | #define H_T1_Window_Spill_0_Other_Trap |
| 439 | #define SUN_H_T1_Window_Spill_0_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 440 | |
| 441 | #define H_T1_Window_Spill_1_Other_Trap |
| 442 | #define SUN_H_T1_Window_Spill_1_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 443 | |
| 444 | #define H_T1_Window_Spill_2_Other_Trap |
| 445 | #define SUN_H_T1_Window_Spill_2_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 446 | |
| 447 | #define H_T1_Window_Spill_3_Other_Trap |
| 448 | #define SUN_H_T1_Window_Spill_3_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 449 | |
| 450 | #define H_T1_Window_Spill_4_Other_Trap |
| 451 | #define SUN_H_T1_Window_Spill_4_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 452 | |
| 453 | #define H_T1_Window_Spill_5_Other_Trap |
| 454 | #define SUN_H_T1_Window_Spill_5_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 455 | |
| 456 | #define H_T1_Window_Spill_6_Other_Trap |
| 457 | #define SUN_H_T1_Window_Spill_6_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 458 | |
| 459 | #define H_T1_Window_Spill_7_Other_Trap |
| 460 | #define SUN_H_T1_Window_Spill_7_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop; |
| 461 | |
| 462 | #define H_T1_Window_Fill_0_Normal_Trap |
| 463 | #define SUN_H_T1_Window_Fill_0_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 464 | |
| 465 | #define H_T1_Window_Fill_1_Normal_Trap |
| 466 | #define SUN_H_T1_Window_Fill_1_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 467 | |
| 468 | #define H_T1_Window_Fill_2_Normal_Trap |
| 469 | #define SUN_H_T1_Window_Fill_2_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 470 | |
| 471 | #define H_T1_Window_Fill_3_Normal_Trap |
| 472 | #define SUN_H_T1_Window_Fill_3_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 473 | |
| 474 | #define H_T1_Window_Fill_4_Normal_Trap |
| 475 | #define SUN_H_T1_Window_Fill_4_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 476 | |
| 477 | #define H_T1_Window_Fill_5_Normal_Trap |
| 478 | #define SUN_H_T1_Window_Fill_5_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 479 | |
| 480 | #define H_T1_Window_Fill_6_Normal_Trap |
| 481 | #define SUN_H_T1_Window_Fill_6_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 482 | |
| 483 | #define H_T1_Window_Fill_7_Normal_Trap |
| 484 | #define SUN_H_T1_Window_Fill_7_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 485 | |
| 486 | #define H_T1_Window_Fill_0_Other_Trap |
| 487 | #define SUN_H_T1_Window_Fill_0_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 488 | |
| 489 | #define H_T1_Window_Fill_1_Other_Trap |
| 490 | #define SUN_H_T1_Window_Fill_1_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 491 | |
| 492 | #define H_T1_Window_Fill_2_Other_Trap |
| 493 | #define SUN_H_T1_Window_Fill_2_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 494 | |
| 495 | #define H_T1_Window_Fill_3_Other_Trap |
| 496 | #define SUN_H_T1_Window_Fill_3_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 497 | |
| 498 | #define H_T1_Window_Fill_4_Other_Trap |
| 499 | #define SUN_H_T1_Window_Fill_4_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 500 | |
| 501 | #define H_T1_Window_Fill_5_Other_Trap |
| 502 | #define SUN_H_T1_Window_Fill_5_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 503 | |
| 504 | #define H_T1_Window_Fill_6_Other_Trap |
| 505 | #define SUN_H_T1_Window_Fill_6_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 506 | |
| 507 | #define H_T1_Window_Fill_7_Other_Trap |
| 508 | #define SUN_H_T1_Window_Fill_7_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop; |
| 509 | |
| 510 | #define H_T0_Trap_Instruction_0 |
| 511 | #define My_T0_Trap_Instruction_0 \ |
| 512 | T_HANDLER_RAND7_5 ;\ |
| 513 | done; |
| 514 | |
| 515 | #define H_T0_Trap_Instruction_1 |
| 516 | #define My_T0_Trap_Instruction_1 \ |
| 517 | T_HANDLER_RAND7_6 ;\ |
| 518 | done; |
| 519 | |
| 520 | #define H_T0_Trap_Instruction_2 |
| 521 | #define My_T0_Trap_Instruction_2 \ |
| 522 | inc %o3;\ |
| 523 | umul %o3, 2, %o4;\ |
| 524 | ba 1f; \ |
| 525 | save %i7, %g0, %i7; \ |
| 526 | 2: done; \ |
| 527 | nop; \ |
| 528 | 1: ba 2b; \ |
| 529 | restore %i7, %g0, %i7 |
| 530 | #define H_T0_Trap_Instruction_3 |
| 531 | #define My_T0_Trap_Instruction_3 \ |
| 532 | save %i7, %g0, %i7 ;\ |
| 533 | T_HANDLER_RAND4_5;\ |
| 534 | stw %o4, [%i7];\ |
| 535 | restore %i7, %g0, %i7 ;\ |
| 536 | done |
| 537 | #define H_T0_Trap_Instruction_4 |
| 538 | #define My_T0_Trap_Instruction_4 \ |
| 539 | T_HANDLER_RAND7_6 ;\ |
| 540 | done; |
| 541 | |
| 542 | #define H_T0_Trap_Instruction_5 |
| 543 | #define My_T0_Trap_Instruction_5 \ |
| 544 | T_HANDLER_RAND4_5;\ |
| 545 | done; |
| 546 | |
| 547 | #define H_T1_Trap_Instruction_0 |
| 548 | #define My_T1_Trap_Instruction_0 \ |
| 549 | inc %o4;\ |
| 550 | umul %o4, 2, %o5;\ |
| 551 | ba 3f; \ |
| 552 | save %i7, %g0, %i7; \ |
| 553 | 4: done; \ |
| 554 | nop; \ |
| 555 | 3: ba 4b; \ |
| 556 | restore %i7, %g0, %i7 |
| 557 | #define H_T1_Trap_Instruction_1 |
| 558 | #define My_T1_Trap_Instruction_1 \ |
| 559 | T_HANDLER_RAND7_3;\ |
| 560 | done |
| 561 | #define H_T1_Trap_Instruction_2 |
| 562 | #define My_T1_Trap_Instruction_2 \ |
| 563 | inc %o3;\ |
| 564 | umul %o3, 2, %o4;\ |
| 565 | ba 5f; \ |
| 566 | save %i7, %g0, %i7; \ |
| 567 | 6: done; \ |
| 568 | nop; \ |
| 569 | 5: ba 6b; \ |
| 570 | restore %i7, %g0, %i7 |
| 571 | #define H_T1_Trap_Instruction_3 |
| 572 | #define My_T1_Trap_Instruction_3 \ |
| 573 | T_HANDLER_RAND4_1;\ |
| 574 | done; |
| 575 | |
| 576 | #define H_T1_Trap_Instruction_4 |
| 577 | #define My_T1_Trap_Instruction_4 \ |
| 578 | T_HANDLER_RAND7_1;\ |
| 579 | done; |
| 580 | #define H_T1_Trap_Instruction_5 |
| 581 | #define My_T1_Trap_Instruction_5 \ |
| 582 | T_HANDLER_RAND7_2;\ |
| 583 | done |
| 584 | #define H_HT0_Trap_Instruction_0 |
| 585 | #define My_HT0_Trap_Instruction_0 \ |
| 586 | HT_HANDLER_RAND4_1 ;\ |
| 587 | done; |
| 588 | #define H_HT0_Trap_Instruction_1 |
| 589 | #define My_HT0_Trap_Instruction_1 \ |
| 590 | HT_HANDLER_RAND4_3 ;\ |
| 591 | done |
| 592 | #define H_HT0_Trap_Instruction_2 |
| 593 | #define My_HT0_Trap_Instruction_2 \ |
| 594 | HT_HANDLER_RAND7_5 ;\ |
| 595 | done; |
| 596 | #define H_HT0_Trap_Instruction_3 |
| 597 | #define My_HT0_Trap_Instruction_3 \ |
| 598 | HT_HANDLER_RAND4_5 ;\ |
| 599 | done |
| 600 | #define H_HT0_Trap_Instruction_4 |
| 601 | #define My_HT0_Trap_Instruction_4 \ |
| 602 | HT_HANDLER_RAND7_4 ;\ |
| 603 | done |
| 604 | #define H_HT0_Trap_Instruction_5 |
| 605 | #define My_HT0_Trap_Instruction_5 \ |
| 606 | ba htrap_5_ext;\ |
| 607 | nop; retry;\ |
| 608 | nop; nop; nop; nop; nop |
| 609 | |
| 610 | #define H_HT0_Mem_Address_Not_Aligned_0x34 |
| 611 | #define My_HT0_Mem_Address_Not_Aligned_0x34 \ |
| 612 | HT_HANDLER_RAND4_2 ;\ |
| 613 | done ; |
| 614 | #define H_HT0_Illegal_instruction_0x10 |
| 615 | #define My_HT0_Illegal_instruction_0x10 \ |
| 616 | HT_HANDLER_RAND4_2 ;\ |
| 617 | done; |
| 618 | |
| 619 | #define H_HT0_DAE_so_page_0x30 |
| 620 | #define My_HT0_DAE_so_page_0x30 \ |
| 621 | HT_HANDLER_RAND4_2;\ |
| 622 | done; |
| 623 | #define H_HT0_DAE_invalid_asi_0x14 |
| 624 | #define SUN_H_HT0_DAE_invalid_asi_0x14 \ |
| 625 | HT_HANDLER_RAND4_3 ;\ |
| 626 | done |
| 627 | #define H_HT0_DAE_privilege_violation_0x15 |
| 628 | #define SUN_H_HT0_DAE_privilege_violation_0x15 \ |
| 629 | HT_HANDLER_RAND4_4 ;\ |
| 630 | done; |
| 631 | #define H_HT0_Privileged_Action_0x37 |
| 632 | #define My_HT0_Privileged_Action_0x37 \ |
| 633 | done; \ |
| 634 | nop; nop |
| 635 | #define H_HT0_Lddf_Mem_Address_Not_Aligned_0x35 |
| 636 | #define My_HT0_Lddf_Mem_Address_Not_Aligned_0x35 \ |
| 637 | HT_HANDLER_RAND4_3 ;\ |
| 638 | done |
| 639 | #define H_HT0_Stdf_Mem_Address_Not_Aligned_0x36 |
| 640 | #define My_HT0_Stdf_Mem_Address_Not_Aligned_0x36 \ |
| 641 | HT_HANDLER_RAND7_1;\ |
| 642 | done |
| 643 | #define H_HT0_Fp_exception_ieee_754_0x21 |
| 644 | #define My_HT0_Fp_exception_ieee_754_0x21 \ |
| 645 | HT_HANDLER_RAND4_2 ;\ |
| 646 | done |
| 647 | #define H_HT0_Fp_exception_other_0x22 |
| 648 | #define My_HT0_Fp_exception_other_0x22 \ |
| 649 | HT_HANDLER_RAND7_2 ;\ |
| 650 | done |
| 651 | #define H_HT0_Division_By_Zero |
| 652 | #define My_HT0_Division_By_Zero \ |
| 653 | HT_HANDLER_RAND4_6;\ |
| 654 | done |
| 655 | #define H_T0_Division_By_Zero |
| 656 | #define My_T0_Division_By_Zero \ |
| 657 | T_HANDLER_RAND4_3;\ |
| 658 | done |
| 659 | #define H_T1_Division_By_Zero_0x28 |
| 660 | #define My_H_T1_Division_By_Zero_0x28 \ |
| 661 | T_HANDLER_RAND4_3;\ |
| 662 | done |
| 663 | #define H_T0_Division_By_Zero |
| 664 | #define My_T0_Division_By_Zero\ |
| 665 | T_HANDLER_RAND4_4 ;\ |
| 666 | done |
| 667 | #define H_T0_Fp_exception_ieee_754_0x21 |
| 668 | #define My_T0_Fp_exception_ieee_754_0x21 \ |
| 669 | T_HANDLER_RAND4_3 ;\ |
| 670 | done |
| 671 | #define H_T1_Fp_Exception_Ieee_754_0x21 |
| 672 | #define My_H_T1_Fp_Exception_Ieee_754_0x21 \ |
| 673 | T_HANDLER_RAND4_4 ;\ |
| 674 | done |
| 675 | #define H_T1_Fp_Exception_Other_0x22 |
| 676 | #define My_H_T1_Fp_Exception_Other_0x22 \ |
| 677 | T_HANDLER_RAND4_5 ;\ |
| 678 | done |
| 679 | #define H_T1_Privileged_Opcode_0x11 |
| 680 | #define SUN_H_T1_Privileged_Opcode_0x11 \ |
| 681 | T_HANDLER_RAND4_6 ;\ |
| 682 | done |
| 683 | |
| 684 | #define H_HT0_Privileged_opcode_0x11 |
| 685 | #define My_HT0_Privileged_opcode_0x11 \ |
| 686 | HT_HANDLER_RAND4_1;\ |
| 687 | done; |
| 688 | |
| 689 | #define H_HT0_Fp_disabled_0x20 |
| 690 | #define My_HT0_Fp_disabled_0x20 \ |
| 691 | mov 0x4, %l2 ;\ |
| 692 | wr %l2, 0x0, %fprs ;\ |
| 693 | sllx %l2, 10, %l3; \ |
| 694 | rdpr %tstate, %l2;\ |
| 695 | or %l2, %l3, %l2 ;\ |
| 696 | stw %l2, [%i7];\ |
| 697 | wrpr %l2, 0x0, %tstate;\ |
| 698 | retry; |
| 699 | |
| 700 | #define H_T0_Fp_disabled_0x20 |
| 701 | #define My_T0_Fp_disabled_0x20 \ |
| 702 | mov 0x4, %l2 ;\ |
| 703 | wr %l2, 0x0, %fprs ;\ |
| 704 | sllx %l2, 10, %l3; \ |
| 705 | rdpr %tstate, %l2;\ |
| 706 | or %l2, %l3, %l2 ;\ |
| 707 | wrpr %l2, 0x0, %tstate;\ |
| 708 | retry; nop |
| 709 | |
| 710 | #define H_T1_Fp_Disabled_0x20 |
| 711 | #define My_H_T1_Fp_Disabled_0x20 \ |
| 712 | mov 0x4, %l2 ;\ |
| 713 | wr %l2, 0x0, %fprs ;\ |
| 714 | sllx %l2, 10, %l3; \ |
| 715 | rdpr %tstate, %l2;\ |
| 716 | or %l2, %l3, %l2 ;\ |
| 717 | wrpr %l2, 0x0, %tstate;\ |
| 718 | stw %l2, [%i7];\ |
| 719 | retry |
| 720 | |
| 721 | #define H_HT0_Watchdog_Reset_0x02 |
| 722 | #define My_HT0_Watchdog_Reset_0x02 \ |
| 723 | ba wdog_2_ext;\ |
| 724 | nop;retry;nop;nop;nop;nop;nop |
| 725 | |
| 726 | #define H_T0_Privileged_opcode_0x11 |
| 727 | #define My_T0_Privileged_opcode_0x11 \ |
| 728 | T_HANDLER_RAND4_4;\ |
| 729 | done |
| 730 | |
| 731 | #define H_T1_Fp_exception_other_0x22 |
| 732 | #define My_T1_Fp_exception_other_0x22 \ |
| 733 | T_HANDLER_RAND7_3 ;\ |
| 734 | done; |
| 735 | |
| 736 | #define H_T0_Fp_exception_other_0x22 |
| 737 | #define My_T0_Fp_exception_other_0x22 \ |
| 738 | T_HANDLER_RAND7_4;\ |
| 739 | done |
| 740 | |
| 741 | #define H_HT0_Trap_Level_Zero_0x5f |
| 742 | #define My_HT0_Trap_Level_Zero_0x5f \ |
| 743 | not %g0, %r13; \ |
| 744 | rdhpr %hpstate, %l3;\ |
| 745 | jmp %r13;\ |
| 746 | rdhpr %htstate, %l3;\ |
| 747 | and %l3, 0xfe, %l3;\ |
| 748 | wrhpr %l3, 0, %htstate;\ |
| 749 | stw %r13, [%i7];\ |
| 750 | retry |
| 751 | |
| 752 | #define My_Watchdog_Reset |
| 753 | #define My_Watchdog_Reset \ |
| 754 | ba wdog_red_ext;\ |
| 755 | nop;retry;nop;nop;nop;nop;nop |
| 756 | |
| 757 | #define H_HT0_Control_Transfer_Instr_0x74 |
| 758 | #define My_H_HT0_Control_Transfer_Instr_0x74 \ |
| 759 | rdpr %tstate, %l3;\ |
| 760 | mov 1, %l4;\ |
| 761 | sllx %l4, 20, %l4;\ |
| 762 | wrpr %l3, %l4, %tstate ;\ |
| 763 | retry;nop; |
| 764 | |
| 765 | #define H_T0_Control_Transfer_Instr_0x74 |
| 766 | #define My_H_T0_Control_Transfer_Instr_0x74 \ |
| 767 | rdpr %tstate, %l3;\ |
| 768 | mov 1, %l4;\ |
| 769 | sllx %l4, 20, %l4;\ |
| 770 | wrpr %l3, %l4, %tstate ;\ |
| 771 | retry;nop; |
| 772 | |
| 773 | #define H_T1_Control_Transfer_Instr_0x74 |
| 774 | #define My_H_T1_Control_Transfer_Instr_0x74 \ |
| 775 | rdpr %tstate, %l3;\ |
| 776 | mov 1, %l4;\ |
| 777 | sllx %l4, 20, %l4;\ |
| 778 | wrpr %l3, %l4, %tstate ;\ |
| 779 | retry;nop; |
| 780 | # 707 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 781 | #define H_HT0_data_access_protection_0x6c |
| 782 | #define SUN_H_HT0_data_access_protection_0x6c ba daccess_prot_handler; nop |
| 783 | |
| 784 | #define H_HT0_PA_Watchpoint_0x61 |
| 785 | #define My_H_HT0_PA_Watchpoint_0x61 \ |
| 786 | HT_HANDLER_RAND7_4;\ |
| 787 | done |
| 788 | |
| 789 | #ifndef H_HT0_Data_access_error_0x32 |
| 790 | #define H_HT0_Data_access_error_0x32 |
| 791 | #define SUN_H_HT0_Data_access_error_0x32 \ |
| 792 | done;nop |
| 793 | #endif |
| 794 | # 722 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 795 | #define H_T0_VA_Watchpoint_0x62 |
| 796 | #define My_T0_VA_Watchpoint_0x62 \ |
| 797 | T_HANDLER_RAND7_5;\ |
| 798 | done |
| 799 | |
| 800 | #define H_T1_VA_Watchpoint_0x62 |
| 801 | #define SUN_H_T1_VA_Watchpoint_0x62 \ |
| 802 | T_HANDLER_RAND7_3;\ |
| 803 | done |
| 804 | |
| 805 | #define H_HT0_VA_Watchpoint_0x62 |
| 806 | #define My_H_HT0_VA_Watchpoint_0x62 \ |
| 807 | HT_HANDLER_RAND7_5;\ |
| 808 | done |
| 809 | |
| 810 | #define H_HT0_Instruction_VA_Watchpoint_0x75 |
| 811 | #define SUN_H_HT0_Instruction_VA_Watchpoint_0x75 \ |
| 812 | done; |
| 813 | |
| 814 | #define H_HT0_Instruction_Breakpoint_0x76 |
| 815 | #define SUN_H_HT0_Instruction_Breakpoint_0x76 \ |
| 816 | rdhpr %htstate, %g1;\ |
| 817 | wrhpr %g1, 0x400, %htstate;\ |
| 818 | retry;nop |
| 819 | # 748 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 820 | #define H_HT0_Instruction_address_range_0x0d |
| 821 | #define SUN_H_HT0_Instruction_address_range_0x0d \ |
| 822 | HT_HANDLER_RAND4_1;\ |
| 823 | done; |
| 824 | |
| 825 | #define H_HT0_Instruction_real_range_0x0e |
| 826 | #define SUN_H_HT0_Instruction_real_range_0x0e \ |
| 827 | HT_HANDLER_RAND4_1;\ |
| 828 | done; |
| 829 | |
| 830 | #define H_HT0_mem_real_range_0x2d |
| 831 | #define SUN_H_HT0_mem_real_range_0x2d \ |
| 832 | HT_HANDLER_RAND4_2;\ |
| 833 | done; |
| 834 | # 764 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 835 | #define H_HT0_mem_address_range_0x2e |
| 836 | #define SUN_H_HT0_mem_address_range_0x2e \ |
| 837 | HT_HANDLER_RAND4_3;\ |
| 838 | done; |
| 839 | |
| 840 | #define H_HT0_DAE_nc_page_0x16 |
| 841 | #define SUN_H_HT0_DAE_nc_page_0x16 \ |
| 842 | HT_HANDLER_RAND4_4;\ |
| 843 | done; |
| 844 | |
| 845 | #define H_HT0_DAE_nfo_page_0x17 |
| 846 | #define SUN_H_HT0_DAE_nfo_page_0x17 \ |
| 847 | HT_HANDLER_RAND4_5;\ |
| 848 | done; |
| 849 | # 780 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 850 | #define H_HT0_IAE_unauth_access_0x0b |
| 851 | #define SUN_H_HT0_IAE_unauth_access_0x0b \ |
| 852 | HT_HANDLER_RAND7_3;\ |
| 853 | done; |
| 854 | # 786 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 855 | #define H_HT0_IAE_nfo_page_0x0c |
| 856 | #define SUN_H_HT0_IAE_nfo_page_0x0c \ |
| 857 | HT_HANDLER_RAND7_6;\ |
| 858 | done; |
| 859 | # 792 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 860 | #define H_HT0_Reserved_0x3b |
| 861 | #define SUN_H_HT0_Reserved_0x3b \ |
| 862 | mov 0x80, %l3;\ |
| 863 | stxa %l3, [%l3]0x5f ;\ |
| 864 | stxa %l3, [%l3]0x57 ;\ |
| 865 | done; |
| 866 | # 802 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_handlers.s" |
| 867 | #define H_HT0_IAE_privilege_violation_0x08 |
| 868 | #define My_HT0_IAE_privilege_violation_0x08 \ |
| 869 | HT_HANDLER_RAND7_2;\ |
| 870 | done; |
| 871 | |
| 872 | #ifndef H_HT0_Instruction_Access_MMU_Error_0x71 |
| 873 | #define H_HT0_Instruction_Access_MMU_Error_0x71 |
| 874 | #define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \ |
| 875 | mov 0x80, %l3;\ |
| 876 | stxa %l3, [%l3]0x5f ;\ |
| 877 | stxa %l3, [%l3]0x57 ;\ |
| 878 | retry; |
| 879 | #endif |
| 880 | |
| 881 | #ifndef H_HT0_Data_Access_MMU_Error_0x72 |
| 882 | #define H_HT0_Data_Access_MMU_Error_0x72 |
| 883 | #define SUN_H_HT0_Data_Access_MMU_Error_0x72 \ |
| 884 | mov 0x80, %l3;\ |
| 885 | stxa %l3, [%l3]0x5f ;\ |
| 886 | stxa %l3, [%l3]0x57 ;\ |
| 887 | retry; |
| 888 | #endif |
| 889 | |
| 890 | !!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!! |
| 891 | # 12 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 892 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 893 | !!!!!!!!!!!!!!!! START of Interrupt Handlers !!!!!!!!!!!!!!!!! |
| 894 | |
| 895 | #ifndef INT_HANDLER_RAND4_1 |
| 896 | #define INT_HANDLER_RAND4_1 retry; nop; nop; nop |
| 897 | #endif |
| 898 | #ifndef INT_HANDLER_RAND7_1 |
| 899 | #define INT_HANDLER_RAND7_1 mov 0x20,%g1; mov 1, %g2;stxa %g2,[%g1]0x40 |
| 900 | #endif |
| 901 | #ifndef INT_HANDLER_RAND4_2 |
| 902 | #define INT_HANDLER_RAND4_2 retry; nop; nop; nop |
| 903 | #endif |
| 904 | #ifndef INT_HANDLER_RAND7_2 |
| 905 | #define INT_HANDLER_RAND7_2 mov 0x80,%g1;stxa %g0,[%g1]0x40 |
| 906 | #endif |
| 907 | #ifndef INT_HANDLER_RAND4_3 |
| 908 | #define INT_HANDLER_RAND4_3 retry; nop; nop; nop |
| 909 | #endif |
| 910 | #ifndef INT_HANDLER_RAND7_3 |
| 911 | #define INT_HANDLER_RAND7_3 retry; nop; nop; nop ; nop; nop; nop |
| 912 | #endif |
| 913 | #define H_HT0_Externally_Initiated_Reset_0x03 |
| 914 | #define SUN_H_HT0_Externally_Initiated_Reset_0x03 \ |
| 915 | ldxa [%g0] ASI_LSU_CTL_REG, %g1; \ |
| 916 | set cregs_lsu_ctl_reg_r64, %g1; \ |
| 917 | stxa %g1, [%g0] ASI_LSU_CTL_REG; \ |
| 918 | retry;nop |
| 919 | |
| 920 | #define My_External_Reset \ |
| 921 | ldxa [%g0] ASI_LSU_CTL_REG, %l5; \ |
| 922 | set cregs_lsu_ctl_reg_r64, %l5; \ |
| 923 | stxa %l5, [%g0] ASI_LSU_CTL_REG; \ |
| 924 | retry;nop |
| 925 | |
| 926 | !!!!! SPU Interrupt Handlers |
| 927 | |
| 928 | #define H_HT0_Control_Word_Queue_Interrupt_0x3c |
| 929 | #define My_HT0_Control_Word_Queue_Interrupt_0x3c \ |
| 930 | INT_HANDLER_RAND7_1 ;\ |
| 931 | retry ; |
| 932 | |
| 933 | #define H_HT0_Modular_Arithmetic_Interrupt_0x3d |
| 934 | #define My_H_HT0_Modular_Arithmetic_Interrupt_0x3d \ |
| 935 | INT_HANDLER_RAND7_2 ;\ |
| 936 | retry ; |
| 937 | # 59 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 938 | !!!!! HW interrupt handlers |
| 939 | |
| 940 | #define H_HT0_Interrupt_0x60 |
| 941 | #define My_HT0_Interrupt_0x60 \ |
| 942 | ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g5 ;\ |
| 943 | ldxa [%g0] ASI_SWVR_INTR_R, %g4 ;\ |
| 944 | ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g3 ;\ |
| 945 | INT_HANDLER_RAND4_1 ;\ |
| 946 | retry; |
| 947 | |
| 948 | !!!!! Queue interrupt handler |
| 949 | # 72 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 950 | #define H_T0_Cpu_Mondo_Trap_0x7c |
| 951 | #define My_T0_Cpu_Mondo_Trap_0x7c \ |
| 952 | mov 0x3c8, %g3; \ |
| 953 | ldxa [%g3] 0x25, %g5; \ |
| 954 | mov 0x3c0, %g3; \ |
| 955 | stxa %g5, [%g3] 0x25; \ |
| 956 | retry; \ |
| 957 | nop; \ |
| 958 | nop; \ |
| 959 | nop |
| 960 | |
| 961 | #define H_T0_Dev_Mondo_Trap_0x7d |
| 962 | #define My_T0_Dev_Mondo_Trap_0x7d \ |
| 963 | mov 0x3d8, %g3; \ |
| 964 | ldxa [%g3] 0x25, %g5; \ |
| 965 | mov 0x3d0, %g3; \ |
| 966 | stxa %g5, [%g3] 0x25; \ |
| 967 | retry; \ |
| 968 | nop; \ |
| 969 | nop; \ |
| 970 | nop |
| 971 | |
| 972 | #define H_T0_Resumable_Error_0x7e |
| 973 | #define My_T0_Resumable_Error_0x7e \ |
| 974 | mov 0x3e8, %g3; \ |
| 975 | ldxa [%g3] 0x25, %g5; \ |
| 976 | mov 0x3e0, %g3; \ |
| 977 | stxa %g5, [%g3] 0x25; \ |
| 978 | retry; \ |
| 979 | nop; \ |
| 980 | nop; \ |
| 981 | nop |
| 982 | |
| 983 | #define H_T1_Cpu_Mondo_Trap_0x7c |
| 984 | #define My_T1_Cpu_Mondo_Trap_0x7c \ |
| 985 | mov 0x3c8, %g3; \ |
| 986 | ldxa [%g3] 0x25, %g5; \ |
| 987 | mov 0x3c0, %g3; \ |
| 988 | stxa %g5, [%g3] 0x25; \ |
| 989 | retry; \ |
| 990 | nop; \ |
| 991 | nop; \ |
| 992 | nop |
| 993 | |
| 994 | #define H_T1_Dev_Mondo_Trap_0x7d |
| 995 | #define My_T1_Dev_Mondo_Trap_0x7d \ |
| 996 | mov 0x3d8, %g3; \ |
| 997 | ldxa [%g3] 0x25, %g5; \ |
| 998 | mov 0x3d0, %g3; \ |
| 999 | stxa %g5, [%g3] 0x25; \ |
| 1000 | retry; \ |
| 1001 | nop; \ |
| 1002 | nop; \ |
| 1003 | nop |
| 1004 | |
| 1005 | #define H_T1_Resumable_Error_0x7e |
| 1006 | #define My_T1_Resumable_Error_0x7e \ |
| 1007 | mov 0x3e8, %g3; \ |
| 1008 | ldxa [%g3] 0x25, %g5; \ |
| 1009 | mov 0x3e0, %g3; \ |
| 1010 | stxa %g5, [%g3] 0x25; \ |
| 1011 | retry; \ |
| 1012 | nop; \ |
| 1013 | nop; \ |
| 1014 | nop |
| 1015 | |
| 1016 | #define H_HT0_Reserved_0x7c |
| 1017 | #define SUN_H_HT0_Reserved_0x7c \ |
| 1018 | mov 0x3c8, %g3; \ |
| 1019 | ldxa [%g3] 0x25, %g5; \ |
| 1020 | mov 0x3c0, %g3; \ |
| 1021 | stxa %g5, [%g3] 0x25; \ |
| 1022 | retry; \ |
| 1023 | nop; \ |
| 1024 | nop; \ |
| 1025 | nop |
| 1026 | |
| 1027 | #define H_HT0_Reserved_0x7d |
| 1028 | #define SUN_H_HT0_Reserved_0x7d \ |
| 1029 | mov 0x3d8, %g3; \ |
| 1030 | ldxa [%g3] 0x25, %g5; \ |
| 1031 | mov 0x3d0, %g3; \ |
| 1032 | stxa %g5, [%g3] 0x25; \ |
| 1033 | retry; \ |
| 1034 | nop; \ |
| 1035 | nop; \ |
| 1036 | nop |
| 1037 | |
| 1038 | #define H_HT0_Reserved_0x7e |
| 1039 | #define SUN_H_HT0_Reserved_0x7e \ |
| 1040 | mov 0x3e8, %g3; \ |
| 1041 | ldxa [%g3] 0x25, %g5; \ |
| 1042 | mov 0x3e0, %g3; \ |
| 1043 | stxa %g5, [%g3] 0x25; \ |
| 1044 | retry; \ |
| 1045 | nop; \ |
| 1046 | nop; \ |
| 1047 | nop |
| 1048 | # 172 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 1049 | !!!!! Hstick-match trap handler |
| 1050 | # 175 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 1051 | #define H_T0_Reserved_0x5e |
| 1052 | #define My_T0_Reserved_0x5e \ |
| 1053 | rdhpr %hintp, %g3; \ |
| 1054 | wrhpr %g3, %g3, %hintp; \ |
| 1055 | retry; \ |
| 1056 | nop; \ |
| 1057 | nop; \ |
| 1058 | nop; \ |
| 1059 | nop; \ |
| 1060 | nop |
| 1061 | |
| 1062 | #define H_HT0_Hstick_Match_0x5e |
| 1063 | #define My_HT0_Hstick_Match_0x5e \ |
| 1064 | rdhpr %hintp, %g3; \ |
| 1065 | wrhpr %g3, %g3, %hintp; \ |
| 1066 | retry; \ |
| 1067 | nop; \ |
| 1068 | nop; \ |
| 1069 | nop; \ |
| 1070 | nop; \ |
| 1071 | nop |
| 1072 | |
| 1073 | #define H_T0_Reserved_0x5e |
| 1074 | #define My_T0_Reserved_0x5e \ |
| 1075 | rdhpr %hintp, %g3; \ |
| 1076 | wrhpr %g3, %g3, %hintp; \ |
| 1077 | retry; \ |
| 1078 | nop; \ |
| 1079 | nop; \ |
| 1080 | nop; \ |
| 1081 | nop; \ |
| 1082 | nop |
| 1083 | |
| 1084 | #define H_T1_Reserved_0x5e |
| 1085 | #define My_T1_Reserved_0x5e \ |
| 1086 | rdhpr %hintp, %g3; \ |
| 1087 | wrhpr %g3, %g3, %hintp; \ |
| 1088 | retry; \ |
| 1089 | nop; \ |
| 1090 | nop; \ |
| 1091 | nop; \ |
| 1092 | nop; \ |
| 1093 | nop |
| 1094 | # 220 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 1095 | !!!!! SW interuupt handlers |
| 1096 | # 223 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 1097 | #define H_T0_Interrupt_Level_14_0x4e |
| 1098 | #define My_T0_Interrupt_Level_14_0x4e \ |
| 1099 | rd %softint, %g3; \ |
| 1100 | sethi %hi(0x14000), %g3; \ |
| 1101 | or %g3, 0x1, %g3; \ |
| 1102 | wr %g3, %g0, %clear_softint; \ |
| 1103 | retry; \ |
| 1104 | nop; \ |
| 1105 | nop; \ |
| 1106 | nop |
| 1107 | |
| 1108 | #define H_T0_Interrupt_Level_1_0x41 |
| 1109 | #define My_T0_Interrupt_Level_1_0x41 \ |
| 1110 | rd %softint, %g3; \ |
| 1111 | or %g0, 0x2, %g3; \ |
| 1112 | wr %g3, %g0, %clear_softint; \ |
| 1113 | retry; \ |
| 1114 | nop; \ |
| 1115 | nop; \ |
| 1116 | nop; \ |
| 1117 | nop |
| 1118 | |
| 1119 | #define H_T0_Interrupt_Level_2_0x42 |
| 1120 | #define My_T0_Interrupt_Level_2_0x42 \ |
| 1121 | rd %softint, %g3; \ |
| 1122 | or %g0, 0x4, %g3; \ |
| 1123 | wr %g3, %g0, %clear_softint; \ |
| 1124 | retry; \ |
| 1125 | nop; \ |
| 1126 | nop; \ |
| 1127 | nop; \ |
| 1128 | nop |
| 1129 | |
| 1130 | #define H_T0_Interrupt_Level_3_0x43 |
| 1131 | #define My_T0_Interrupt_Level_3_0x43 \ |
| 1132 | rd %softint, %g3; \ |
| 1133 | or %g0, 0x8, %g3; \ |
| 1134 | wr %g3, %g0, %clear_softint; \ |
| 1135 | retry; \ |
| 1136 | nop; \ |
| 1137 | nop; \ |
| 1138 | nop; \ |
| 1139 | nop |
| 1140 | |
| 1141 | #define H_T0_Interrupt_Level_4_0x44 |
| 1142 | #define My_T0_Interrupt_Level_4_0x44 \ |
| 1143 | rd %softint, %g3; \ |
| 1144 | or %g0, 0x10, %g3; \ |
| 1145 | wr %g3, %g0, %clear_softint; \ |
| 1146 | retry; \ |
| 1147 | nop; \ |
| 1148 | nop; \ |
| 1149 | nop; \ |
| 1150 | nop |
| 1151 | |
| 1152 | #define H_T0_Interrupt_Level_5_0x45 |
| 1153 | #define My_T0_Interrupt_Level_5_0x45 \ |
| 1154 | rd %softint, %g3; \ |
| 1155 | or %g0, 0x20, %g3; \ |
| 1156 | wr %g3, %g0, %clear_softint; \ |
| 1157 | retry; \ |
| 1158 | nop; \ |
| 1159 | nop; \ |
| 1160 | nop; \ |
| 1161 | nop |
| 1162 | |
| 1163 | #define H_T0_Interrupt_Level_6_0x46 |
| 1164 | #define My_T0_Interrupt_Level_6_0x46 \ |
| 1165 | rd %softint, %g3; \ |
| 1166 | or %g0, 0x40, %g3; \ |
| 1167 | wr %g3, %g0, %clear_softint; \ |
| 1168 | retry; \ |
| 1169 | nop; \ |
| 1170 | nop; \ |
| 1171 | nop; \ |
| 1172 | nop |
| 1173 | |
| 1174 | #define H_T0_Interrupt_Level_7_0x47 |
| 1175 | #define My_T0_Interrupt_Level_7_0x47 \ |
| 1176 | rd %softint, %g3; \ |
| 1177 | or %g0, 0x80, %g3; \ |
| 1178 | wr %g3, %g0, %clear_softint; \ |
| 1179 | retry; \ |
| 1180 | nop; \ |
| 1181 | nop; \ |
| 1182 | nop; \ |
| 1183 | nop |
| 1184 | |
| 1185 | #define H_T0_Interrupt_Level_8_0x48 |
| 1186 | #define My_T0_Interrupt_Level_8_0x48 \ |
| 1187 | rd %softint, %g3; \ |
| 1188 | or %g0, 0x100, %g3; \ |
| 1189 | wr %g3, %g0, %clear_softint; \ |
| 1190 | retry; \ |
| 1191 | nop; \ |
| 1192 | nop; \ |
| 1193 | nop; \ |
| 1194 | nop |
| 1195 | |
| 1196 | #define H_T0_Interrupt_Level_9_0x49 |
| 1197 | #define My_T0_Interrupt_Level_9_0x49 \ |
| 1198 | rd %softint, %g3; \ |
| 1199 | or %g0, 0x200, %g3; \ |
| 1200 | wr %g3, %g0, %clear_softint; \ |
| 1201 | retry; \ |
| 1202 | nop; \ |
| 1203 | nop; \ |
| 1204 | nop; \ |
| 1205 | nop |
| 1206 | |
| 1207 | #define H_T0_Interrupt_Level_10_0x4a |
| 1208 | #define My_T0_Interrupt_Level_10_0x4a \ |
| 1209 | rd %softint, %g3; \ |
| 1210 | or %g0, 0x400, %g3; \ |
| 1211 | wr %g3, %g0, %clear_softint; \ |
| 1212 | retry; \ |
| 1213 | nop; \ |
| 1214 | nop; \ |
| 1215 | nop; \ |
| 1216 | nop |
| 1217 | |
| 1218 | #define H_T0_Interrupt_Level_11_0x4b |
| 1219 | #define My_T0_Interrupt_Level_11_0x4b \ |
| 1220 | rd %softint, %g3; \ |
| 1221 | or %g0, 0x800, %g3; \ |
| 1222 | wr %g3, %g0, %clear_softint; \ |
| 1223 | retry; \ |
| 1224 | nop; \ |
| 1225 | nop; \ |
| 1226 | nop; \ |
| 1227 | nop |
| 1228 | |
| 1229 | #define H_T0_Interrupt_Level_12_0x4c |
| 1230 | #define My_T0_Interrupt_Level_12_0x4c \ |
| 1231 | rd %softint, %g3; \ |
| 1232 | sethi %hi(0x1000), %g3; \ |
| 1233 | wr %g3, %g0, %clear_softint; \ |
| 1234 | retry; \ |
| 1235 | nop; \ |
| 1236 | nop; \ |
| 1237 | nop; \ |
| 1238 | nop |
| 1239 | |
| 1240 | #define H_T0_Interrupt_Level_13_0x4d |
| 1241 | #define My_T0_Interrupt_Level_13_0x4d \ |
| 1242 | rd %softint, %g3; \ |
| 1243 | sethi %hi(0x2000), %g3; \ |
| 1244 | wr %g3, %g0, %clear_softint; \ |
| 1245 | retry; \ |
| 1246 | nop; \ |
| 1247 | nop; \ |
| 1248 | nop; \ |
| 1249 | nop |
| 1250 | |
| 1251 | #define H_T0_Interrupt_Level_15_0x4f |
| 1252 | #define My_T0_Interrupt_Level_15_0x4f \ |
| 1253 | sethi %hi(0x8000), %g3; \ |
| 1254 | wr %g3, %g0, %clear_softint; \ |
| 1255 | wr %g0, %g0, %pic;\ |
| 1256 | sethi %hi(0x80040000), %g2;\ |
| 1257 | rd %pcr, %g3;\ |
| 1258 | andn %g3, %g2, %g3;\ |
| 1259 | wr %g3, %g0, %pcr;\ |
| 1260 | retry; |
| 1261 | |
| 1262 | |
| 1263 | #define H_T1_Interrupt_Level_14_0x4e |
| 1264 | #define My_T1_Interrupt_Level_14_0x4e \ |
| 1265 | rd %softint, %g3; \ |
| 1266 | sethi %hi(0x14000), %g3; \ |
| 1267 | or %g3, 0x1, %g3; \ |
| 1268 | wr %g3, %g0, %clear_softint; \ |
| 1269 | retry; \ |
| 1270 | nop; \ |
| 1271 | nop; \ |
| 1272 | nop |
| 1273 | |
| 1274 | #define H_T1_Interrupt_Level_1_0x41 |
| 1275 | #define My_T1_Interrupt_Level_1_0x41 \ |
| 1276 | rd %softint, %g3; \ |
| 1277 | or %g0, 0x2, %g3; \ |
| 1278 | wr %g3, %g0, %clear_softint; \ |
| 1279 | retry; \ |
| 1280 | nop; \ |
| 1281 | nop; \ |
| 1282 | nop; \ |
| 1283 | nop |
| 1284 | |
| 1285 | #define H_T1_Interrupt_Level_2_0x42 |
| 1286 | #define My_T1_Interrupt_Level_2_0x42 \ |
| 1287 | rd %softint, %g3; \ |
| 1288 | or %g0, 0x4, %g3; \ |
| 1289 | wr %g3, %g0, %clear_softint; \ |
| 1290 | retry; \ |
| 1291 | nop; \ |
| 1292 | nop; \ |
| 1293 | nop; \ |
| 1294 | nop |
| 1295 | |
| 1296 | #define H_T1_Interrupt_Level_3_0x43 |
| 1297 | #define My_T1_Interrupt_Level_3_0x43 \ |
| 1298 | rd %softint, %g3; \ |
| 1299 | or %g0, 0x8, %g3; \ |
| 1300 | wr %g3, %g0, %clear_softint; \ |
| 1301 | retry; \ |
| 1302 | nop; \ |
| 1303 | nop; \ |
| 1304 | nop; \ |
| 1305 | nop |
| 1306 | |
| 1307 | #define H_T1_Interrupt_Level_4_0x44 |
| 1308 | #define My_T1_Interrupt_Level_4_0x44 \ |
| 1309 | rd %softint, %g3; \ |
| 1310 | or %g0, 0x10, %g3; \ |
| 1311 | wr %g3, %g0, %clear_softint; \ |
| 1312 | retry; \ |
| 1313 | nop; \ |
| 1314 | nop; \ |
| 1315 | nop; \ |
| 1316 | nop |
| 1317 | |
| 1318 | #define H_T1_Interrupt_Level_5_0x45 |
| 1319 | #define My_T1_Interrupt_Level_5_0x45 \ |
| 1320 | rd %softint, %g3; \ |
| 1321 | or %g0, 0x20, %g3; \ |
| 1322 | wr %g3, %g0, %clear_softint; \ |
| 1323 | retry; \ |
| 1324 | nop; \ |
| 1325 | nop; \ |
| 1326 | nop; \ |
| 1327 | nop |
| 1328 | |
| 1329 | #define H_T1_Interrupt_Level_6_0x46 |
| 1330 | #define My_T1_Interrupt_Level_6_0x46 \ |
| 1331 | rd %softint, %g3; \ |
| 1332 | or %g0, 0x40, %g3; \ |
| 1333 | wr %g3, %g0, %clear_softint; \ |
| 1334 | retry; \ |
| 1335 | nop; \ |
| 1336 | nop; \ |
| 1337 | nop; \ |
| 1338 | nop |
| 1339 | |
| 1340 | #define H_T1_Interrupt_Level_7_0x47 |
| 1341 | #define My_T1_Interrupt_Level_7_0x47 \ |
| 1342 | rd %softint, %g3; \ |
| 1343 | or %g0, 0x80, %g3; \ |
| 1344 | wr %g3, %g0, %clear_softint; \ |
| 1345 | retry; \ |
| 1346 | nop; \ |
| 1347 | nop; \ |
| 1348 | nop; \ |
| 1349 | nop |
| 1350 | |
| 1351 | #define H_T1_Interrupt_Level_8_0x48 |
| 1352 | #define My_T1_Interrupt_Level_8_0x48 \ |
| 1353 | rd %softint, %g3; \ |
| 1354 | or %g0, 0x100, %g3; \ |
| 1355 | wr %g3, %g0, %clear_softint; \ |
| 1356 | retry; \ |
| 1357 | nop; \ |
| 1358 | nop; \ |
| 1359 | nop; \ |
| 1360 | nop |
| 1361 | |
| 1362 | #define H_T1_Interrupt_Level_9_0x49 |
| 1363 | #define My_T1_Interrupt_Level_9_0x49 \ |
| 1364 | rd %softint, %g3; \ |
| 1365 | or %g0, 0x200, %g3; \ |
| 1366 | wr %g3, %g0, %clear_softint; \ |
| 1367 | retry; \ |
| 1368 | nop; \ |
| 1369 | nop; \ |
| 1370 | nop; \ |
| 1371 | nop |
| 1372 | |
| 1373 | #define H_T1_Interrupt_Level_10_0x4a |
| 1374 | #define My_T1_Interrupt_Level_10_0x4a \ |
| 1375 | rd %softint, %g3; \ |
| 1376 | or %g0, 0x400, %g3; \ |
| 1377 | wr %g3, %g0, %clear_softint; \ |
| 1378 | retry; \ |
| 1379 | nop; \ |
| 1380 | nop; \ |
| 1381 | nop; \ |
| 1382 | nop |
| 1383 | |
| 1384 | #define H_T1_Interrupt_Level_11_0x4b |
| 1385 | #define My_T1_Interrupt_Level_11_0x4b \ |
| 1386 | rd %softint, %g3; \ |
| 1387 | or %g0, 0x800, %g3; \ |
| 1388 | wr %g3, %g0, %clear_softint; \ |
| 1389 | retry; \ |
| 1390 | nop; \ |
| 1391 | nop; \ |
| 1392 | nop; \ |
| 1393 | nop |
| 1394 | |
| 1395 | #define H_T1_Interrupt_Level_12_0x4c |
| 1396 | #define My_T1_Interrupt_Level_12_0x4c \ |
| 1397 | rd %softint, %g3; \ |
| 1398 | sethi %hi(0x1000), %g3; \ |
| 1399 | wr %g3, %g0, %clear_softint; \ |
| 1400 | retry; \ |
| 1401 | nop; \ |
| 1402 | nop; \ |
| 1403 | nop; \ |
| 1404 | nop |
| 1405 | |
| 1406 | #define H_T1_Interrupt_Level_13_0x4d |
| 1407 | #define My_T1_Interrupt_Level_13_0x4d \ |
| 1408 | rd %softint, %g3; \ |
| 1409 | sethi %hi(0x2000), %g3; \ |
| 1410 | wr %g3, %g0, %clear_softint; \ |
| 1411 | retry; \ |
| 1412 | nop; \ |
| 1413 | nop; \ |
| 1414 | nop; \ |
| 1415 | nop |
| 1416 | |
| 1417 | #define H_T1_Interrupt_Level_15_0x4f |
| 1418 | #define My_T1_Interrupt_Level_15_0x4f \ |
| 1419 | sethi %hi(0x8000), %g3; \ |
| 1420 | wr %g3, %g0, %clear_softint; \ |
| 1421 | wr %g0, %g0, %pic;\ |
| 1422 | sethi %hi(0x80040000), %g2;\ |
| 1423 | rd %pcr, %g3;\ |
| 1424 | andn %g3, %g2, %g3;\ |
| 1425 | wr %g3, %g0, %pcr;\ |
| 1426 | retry; |
| 1427 | |
| 1428 | |
| 1429 | #define H_HT0_Interrupt_Level_14_0x4e |
| 1430 | #define My_HT0_Interrupt_Level_14_0x4e \ |
| 1431 | rd %softint, %g3; \ |
| 1432 | sethi %hi(0x14000), %g3; \ |
| 1433 | or %g3, 0x1, %g3; \ |
| 1434 | wr %g3, %g0, %clear_softint; \ |
| 1435 | retry; \ |
| 1436 | nop; \ |
| 1437 | nop; \ |
| 1438 | nop |
| 1439 | |
| 1440 | #define H_HT0_Interrupt_Level_1_0x41 |
| 1441 | #define My_HT0_Interrupt_Level_1_0x41 \ |
| 1442 | rd %softint, %g3; \ |
| 1443 | or %g0, 0x2, %g3; \ |
| 1444 | wr %g3, %g0, %clear_softint; \ |
| 1445 | retry; \ |
| 1446 | nop; \ |
| 1447 | nop; \ |
| 1448 | nop; \ |
| 1449 | nop |
| 1450 | |
| 1451 | #define H_HT0_Interrupt_Level_2_0x42 |
| 1452 | #define My_HT0_Interrupt_Level_2_0x42 \ |
| 1453 | rd %softint, %g3; \ |
| 1454 | or %g0, 0x4, %g3; \ |
| 1455 | wr %g3, %g0, %clear_softint; \ |
| 1456 | retry; \ |
| 1457 | nop; \ |
| 1458 | nop; \ |
| 1459 | nop; \ |
| 1460 | nop |
| 1461 | |
| 1462 | #define H_HT0_Interrupt_Level_3_0x43 |
| 1463 | #define My_HT0_Interrupt_Level_3_0x43 \ |
| 1464 | rd %softint, %g3; \ |
| 1465 | or %g0, 0x8, %g3; \ |
| 1466 | wr %g3, %g0, %clear_softint; \ |
| 1467 | retry; \ |
| 1468 | nop; \ |
| 1469 | nop; \ |
| 1470 | nop; \ |
| 1471 | nop |
| 1472 | |
| 1473 | #define H_HT0_Interrupt_Level_4_0x44 |
| 1474 | #define My_HT0_Interrupt_Level_4_0x44 \ |
| 1475 | rd %softint, %g3; \ |
| 1476 | or %g0, 0x10, %g3; \ |
| 1477 | wr %g3, %g0, %clear_softint; \ |
| 1478 | retry; \ |
| 1479 | nop; \ |
| 1480 | nop; \ |
| 1481 | nop; \ |
| 1482 | nop |
| 1483 | |
| 1484 | #define H_HT0_Interrupt_Level_5_0x45 |
| 1485 | #define My_HT0_Interrupt_Level_5_0x45 \ |
| 1486 | rd %softint, %g3; \ |
| 1487 | or %g0, 0x20, %g3; \ |
| 1488 | wr %g3, %g0, %clear_softint; \ |
| 1489 | retry; \ |
| 1490 | nop; \ |
| 1491 | nop; \ |
| 1492 | nop; \ |
| 1493 | nop |
| 1494 | |
| 1495 | #define H_HT0_Interrupt_Level_6_0x46 |
| 1496 | #define My_HT0_Interrupt_Level_6_0x46 \ |
| 1497 | rd %softint, %g3; \ |
| 1498 | or %g0, 0x40, %g3; \ |
| 1499 | wr %g3, %g0, %clear_softint; \ |
| 1500 | retry; \ |
| 1501 | nop; \ |
| 1502 | nop; \ |
| 1503 | nop; \ |
| 1504 | nop |
| 1505 | |
| 1506 | #define H_HT0_Interrupt_Level_7_0x47 |
| 1507 | #define My_HT0_Interrupt_Level_7_0x47 \ |
| 1508 | rd %softint, %g3; \ |
| 1509 | or %g0, 0x80, %g3; \ |
| 1510 | wr %g3, %g0, %clear_softint; \ |
| 1511 | retry; \ |
| 1512 | nop; \ |
| 1513 | nop; \ |
| 1514 | nop; \ |
| 1515 | nop |
| 1516 | |
| 1517 | #define H_HT0_Interrupt_Level_8_0x48 |
| 1518 | #define My_HT0_Interrupt_Level_8_0x48 \ |
| 1519 | rd %softint, %g3; \ |
| 1520 | or %g0, 0x100, %g3; \ |
| 1521 | wr %g3, %g0, %clear_softint; \ |
| 1522 | retry; \ |
| 1523 | nop; \ |
| 1524 | nop; \ |
| 1525 | nop; \ |
| 1526 | nop |
| 1527 | |
| 1528 | #define H_HT0_Interrupt_Level_9_0x49 |
| 1529 | #define My_HT0_Interrupt_Level_9_0x49 \ |
| 1530 | rd %softint, %g3; \ |
| 1531 | or %g0, 0x200, %g3; \ |
| 1532 | wr %g3, %g0, %clear_softint; \ |
| 1533 | retry; \ |
| 1534 | nop; \ |
| 1535 | nop; \ |
| 1536 | nop; \ |
| 1537 | nop |
| 1538 | |
| 1539 | #define H_HT0_Interrupt_Level_10_0x4a |
| 1540 | #define My_HT0_Interrupt_Level_10_0x4a \ |
| 1541 | rd %softint, %g3; \ |
| 1542 | or %g0, 0x400, %g3; \ |
| 1543 | wr %g3, %g0, %clear_softint; \ |
| 1544 | retry; \ |
| 1545 | nop; \ |
| 1546 | nop; \ |
| 1547 | nop; \ |
| 1548 | nop |
| 1549 | |
| 1550 | #define H_HT0_Interrupt_Level_11_0x4b |
| 1551 | #define My_HT0_Interrupt_Level_11_0x4b \ |
| 1552 | rd %softint, %g3; \ |
| 1553 | or %g0, 0x800, %g3; \ |
| 1554 | wr %g3, %g0, %clear_softint; \ |
| 1555 | retry; \ |
| 1556 | nop; \ |
| 1557 | nop; \ |
| 1558 | nop; \ |
| 1559 | nop |
| 1560 | |
| 1561 | #define H_HT0_Interrupt_Level_12_0x4c |
| 1562 | #define My_HT0_Interrupt_Level_12_0x4c \ |
| 1563 | rd %softint, %g3; \ |
| 1564 | sethi %hi(0x1000), %g3; \ |
| 1565 | wr %g3, %g0, %clear_softint; \ |
| 1566 | retry; \ |
| 1567 | nop; \ |
| 1568 | nop; \ |
| 1569 | nop; \ |
| 1570 | nop |
| 1571 | |
| 1572 | #define H_HT0_Interrupt_Level_13_0x4d |
| 1573 | #define My_HT0_Interrupt_Level_13_0x4d \ |
| 1574 | rd %softint, %g3; \ |
| 1575 | sethi %hi(0x2000), %g3; \ |
| 1576 | wr %g3, %g0, %clear_softint; \ |
| 1577 | retry; \ |
| 1578 | nop; \ |
| 1579 | nop; \ |
| 1580 | nop; \ |
| 1581 | nop |
| 1582 | |
| 1583 | #define H_HT0_Interrupt_Level_15_0x4f |
| 1584 | #define My_HT0_Interrupt_Level_15_0x4f \ |
| 1585 | sethi %hi(0x8000), %g3; \ |
| 1586 | wr %g3, %g0, %clear_softint; \ |
| 1587 | wr %g0, %g0, %pic;\ |
| 1588 | sethi %hi(0x80040000), %g2;\ |
| 1589 | rd %pcr, %g3;\ |
| 1590 | andn %g3, %g2, %g3;\ |
| 1591 | wr %g3, %g0, %pcr;\ |
| 1592 | retry; |
| 1593 | |
| 1594 | # 710 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_intr_handlers.s" |
| 1595 | !!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!! |
| 1596 | # 566 "diag.j.pp" |
| 1597 | !# Steer towards main TBA on these errors .. |
| 1598 | !# These are redefines ... |
| 1599 | #undef SUN_H_HT0_DAE_nc_page_0x16 |
| 1600 | #define SUN_H_HT0_DAE_nc_page_0x16 \ |
| 1601 | best_set_reg(0x120000, %r1, %r2);\ |
| 1602 | wrpr %r0, %r2, %tba; \ |
| 1603 | done;nop |
| 1604 | |
| 1605 | #undef SUN_H_HT0_DAE_nfo_page_0x17 |
| 1606 | #define SUN_H_HT0_DAE_nfo_page_0x17 \ |
| 1607 | best_set_reg(0x120000, %r1, %r2);\ |
| 1608 | wrpr %r0, %r2, %tba; \ |
| 1609 | done;nop |
| 1610 | |
| 1611 | #undef SUN_H_HT0_IAE_unauth_access_0x0b |
| 1612 | #define SUN_H_HT0_IAE_unauth_access_0x0b \ |
| 1613 | set resolve_bad_tte, %g3;\ |
| 1614 | jmp %g3;\ |
| 1615 | nop |
| 1616 | |
| 1617 | #undef My_HT0_IAE_privilege_violation_0x08 |
| 1618 | #define My_HT0_IAE_privilege_violation_0x08 \ |
| 1619 | set resolve_bad_tte, %g3;\ |
| 1620 | jmp %g3;\ |
| 1621 | nop |
| 1622 | |
| 1623 | #define H_HT0_Instruction_address_range_0x0d |
| 1624 | #define SUN_H_HT0_Instruction_address_range_0x0d \ |
| 1625 | rdpr %tpc, %g1;\ |
| 1626 | rdpr %tnpc, %g2;\ |
| 1627 | stw %g1, [%i7];\ |
| 1628 | stw %g2, [%i7+4];\ |
| 1629 | jmpl %r27+8, %r27;\ |
| 1630 | fdivd %f0, %f4, %f4;\ |
| 1631 | nop; |
| 1632 | |
| 1633 | #define H_HT0_Instruction_real_range_0x0e |
| 1634 | #define SUN_H_HT0_Instruction_real_range_0x0e \ |
| 1635 | rdpr %tpc, %g1;\ |
| 1636 | rdpr %tnpc, %g2;\ |
| 1637 | stw %g1, [%i7];\ |
| 1638 | stw %g2, [%i7+4];\ |
| 1639 | jmpl %r27+8, %r27;\ |
| 1640 | fdivd %f0, %f4, %f4;\ |
| 1641 | nop; |
| 1642 | |
| 1643 | #undef SUN_H_HT0_IAE_nfo_page_0x0c |
| 1644 | #define SUN_H_HT0_IAE_nfo_page_0x0c \ |
| 1645 | set resolve_bad_tte, %g3;\ |
| 1646 | jmp %g3;\ |
| 1647 | nop |
| 1648 | |
| 1649 | #define H_HT0_Instruction_Invalid_TSB_Entry_0x2a |
| 1650 | #define SUN_H_HT0_Instruction_Invalid_TSB_Entry_0x2a \ |
| 1651 | set restore_range_regs, %g3;\ |
| 1652 | jmp %g3;\ |
| 1653 | nop |
| 1654 | |
| 1655 | #define H_HT0_Data_Invalid_TSB_Entry_0x2b |
| 1656 | #define SUN_H_HT0_Data_Invalid_TSB_Entry_0x2b \ |
| 1657 | set restore_range_regs, %g3;\ |
| 1658 | jmp %g3;\ |
| 1659 | nop |
| 1660 | |
| 1661 | #undef FAST_BOOT |
| 1662 | #include "hboot.s" |
| 1663 | |
| 1664 | #ifndef MULTIPASS |
| 1665 | #define MULTIPASS 0 |
| 1666 | #endif |
| 1667 | # 638 "diag.j.pp" |
| 1668 | #define LOMEIN_TEXT_VA [0x]mpeval(MAIN_BASE_TEXT_VA&0xffffffff,16) |
| 1669 | #define LOMEIN_DATA_VA [0x]mpeval(MAIN_BASE_DATA_VA&0xffffffff,16) |
| 1670 | changequote([, ])dnl |
| 1671 | SECTION .LOMEIN TEXT_VA=LOMEIN_TEXT_VA, DATA_VA=LOMEIN_DATA_VA |
| 1672 | attr_text { |
| 1673 | Name = .LOMEIN, |
| 1674 | VA= LOMEIN_TEXT_VA, |
| 1675 | RA= MAIN_BASE_TEXT_RA, |
| 1676 | PA= ra2pa2(MAIN_BASE_TEXT_RA, 0), |
| 1677 | part_0_ctx_nonzero_tsb_config_1, |
| 1678 | part_0_ctx_zero_tsb_config_1, |
| 1679 | TTE_G=1, TTE_Context=0x44, TTE_V=1, |
| 1680 | TTE_Size=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, |
| 1681 | TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=1, |
| 1682 | tsbonly |
| 1683 | } |
| 1684 | attr_data { |
| 1685 | Name = .LOMEIN, |
| 1686 | VA= LOMEIN_DATA_VA, |
| 1687 | RA= MAIN_BASE_DATA_RA, |
| 1688 | PA= ra2pa2(MAIN_BASE_DATA_RA, 0), |
| 1689 | part_0_ctx_nonzero_tsb_config_2, |
| 1690 | part_0_ctx_zero_tsb_config_2 |
| 1691 | TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0, |
| 1692 | TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, |
| 1693 | TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0, |
| 1694 | tsbonly |
| 1695 | } |
| 1696 | attr_data { |
| 1697 | Name = .LOMEIN, |
| 1698 | VA= LOMEIN_DATA_VA, |
| 1699 | RA= MAIN_BASE_DATA_RA, |
| 1700 | PA= ra2pa2(MAIN_BASE_DATA_RA, 0), |
| 1701 | part_0_ctx_nonzero_tsb_config_3, |
| 1702 | part_0_ctx_zero_tsb_config_3 |
| 1703 | TTE_G=1, TTE_Context=0x55, TTE_V=1, TTE_Size=0, TTE_NFO=0, |
| 1704 | TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, |
| 1705 | TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0, |
| 1706 | tsbonly |
| 1707 | } |
| 1708 | .text |
| 1709 | .align 0x100000 |
| 1710 | nop |
| 1711 | .data |
| 1712 | .word 0x0 |
| 1713 | |
| 1714 | SECTION .MAIN TEXT_VA=MAIN_BASE_TEXT_VA, DATA_VA=MAIN_BASE_DATA_VA |
| 1715 | attr_text { |
| 1716 | Name = .MAIN, |
| 1717 | VA=MAIN_BASE_TEXT_VA, |
| 1718 | RA= LOMEIN_TEXT_VA, |
| 1719 | PA= LOMEIN_TEXT_VA, |
| 1720 | part_0_ctx_nonzero_tsb_config_2, |
| 1721 | part_0_ctx_zero_tsb_config_2, |
| 1722 | TTE_G=1, TTE_Context=0x44, TTE_V=1, |
| 1723 | TTE_Size=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, |
| 1724 | TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=1, |
| 1725 | } |
| 1726 | |
| 1727 | attr_data { |
| 1728 | Name = .MAIN, |
| 1729 | VA=MAIN_BASE_DATA_VA |
| 1730 | RA= LOMEIN_DATA_VA, |
| 1731 | PA= LOMEIN_DATA_VA, |
| 1732 | part_0_ctx_nonzero_tsb_config_1, |
| 1733 | part_0_ctx_zero_tsb_config_1 |
| 1734 | TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0, |
| 1735 | TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, |
| 1736 | TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0, |
| 1737 | } |
| 1738 | |
| 1739 | attr_data { |
| 1740 | Name = .MAIN, |
| 1741 | VA=MAIN_BASE_DATA_VA |
| 1742 | RA= LOMEIN_DATA_VA, |
| 1743 | PA= LOMEIN_DATA_VA, |
| 1744 | part_0_ctx_nonzero_tsb_config_3, |
| 1745 | part_0_ctx_zero_tsb_config_3 |
| 1746 | TTE_G=1, TTE_Context=0x55, TTE_V=1, TTE_Size=0, TTE_NFO=0, |
| 1747 | TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, |
| 1748 | TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0, |
| 1749 | tsbonly |
| 1750 | } |
| 1751 | |
| 1752 | attr_text { |
| 1753 | Name = .MAIN, |
| 1754 | VA=MAIN_BASE_TEXT_VA, |
| 1755 | hypervisor |
| 1756 | } |
| 1757 | |
| 1758 | attr_data { |
| 1759 | Name = .MAIN, |
| 1760 | VA=MAIN_BASE_DATA_VA |
| 1761 | hypervisor |
| 1762 | } |
| 1763 | changequote(`,')dnl' |
| 1764 | |
| 1765 | .text |
| 1766 | .global main |
| 1767 | main: |
| 1768 | |
| 1769 | ! Set up ld/st area per thread |
| 1770 | ta T_CHANGE_HPRIV |
| 1771 | ldxa [%g0]0x63, %o2 |
| 1772 | and %o2, 0x7, %o1 |
| 1773 | brnz %o1, init_start |
| 1774 | mov 0xff, %r10 |
| 1775 | lock_sync_thds: |
| 1776 | set sync_thr_counter4, %r23 |
| 1777 | #ifndef SPC |
| 1778 | and %o2, 0x38, %o2 |
| 1779 | add %o2,%r23,%r23 !Core's sync counter |
| 1780 | #endif |
| 1781 | st %r10, [%r23] !lock sync_thr_counter4 |
| 1782 | add %r23, 64, %r23 |
| 1783 | st %r10, [%r23] !lock sync_thr_counter5 |
| 1784 | add %r23, 64, %r23 |
| 1785 | st %r10, [%r23] !lock sync_thr_counter6 |
| 1786 | init_start: |
| 1787 | ta T_CHANGE_NONHPRIV |
| 1788 | umul %r9, 256, %r31 |
| 1789 | setx user_data_start, %r1, %r3 |
| 1790 | add %r31, %r3, %r31 |
| 1791 | wr %r0, 0x4, %asi |
| 1792 | |
| 1793 | !Initializing integer registers |
| 1794 | ldx [%r31+0], %r0 |
| 1795 | ldx [%r31+8], %r1 |
| 1796 | ldx [%r31+16], %r2 |
| 1797 | ldx [%r31+24], %r3 |
| 1798 | ldx [%r31+32], %r4 |
| 1799 | ldx [%r31+40], %r5 |
| 1800 | ldx [%r31+48], %r6 |
| 1801 | ldx [%r31+56], %r7 |
| 1802 | ldx [%r31+64], %r8 |
| 1803 | ldx [%r31+72], %r9 |
| 1804 | ldx [%r31+80], %r10 |
| 1805 | ldx [%r31+88], %r11 |
| 1806 | ldx [%r31+96], %r12 |
| 1807 | ldx [%r31+104], %r13 |
| 1808 | ldx [%r31+112], %r14 |
| 1809 | mov %r31, %r15 |
| 1810 | ldx [%r31+128], %r16 |
| 1811 | ldx [%r31+136], %r17 |
| 1812 | ldx [%r31+144], %r18 |
| 1813 | ldx [%r31+152], %r19 |
| 1814 | ldx [%r31+160], %r20 |
| 1815 | ldx [%r31+168], %r21 |
| 1816 | ldx [%r31+176], %r22 |
| 1817 | ldx [%r31+184], %r23 |
| 1818 | ldx [%r31+192], %r24 |
| 1819 | ldx [%r31+200], %r25 |
| 1820 | ldx [%r31+208], %r26 |
| 1821 | ldx [%r31+216], %r27 |
| 1822 | ldx [%r31+224], %r28 |
| 1823 | ldx [%r31+232], %r29 |
| 1824 | mov 0xb4, %r14 |
| 1825 | mov 0x35, %r30 |
| 1826 | save %r31, %r0, %r31 |
| 1827 | ldx [%r31+0], %r0 |
| 1828 | ldx [%r31+8], %r1 |
| 1829 | ldx [%r31+16], %r2 |
| 1830 | ldx [%r31+24], %r3 |
| 1831 | ldx [%r31+32], %r4 |
| 1832 | ldx [%r31+40], %r5 |
| 1833 | ldx [%r31+48], %r6 |
| 1834 | ldx [%r31+56], %r7 |
| 1835 | ldx [%r31+64], %r8 |
| 1836 | ldx [%r31+72], %r9 |
| 1837 | ldx [%r31+80], %r10 |
| 1838 | ldx [%r31+88], %r11 |
| 1839 | ldx [%r31+96], %r12 |
| 1840 | ldx [%r31+104], %r13 |
| 1841 | ldx [%r31+112], %r14 |
| 1842 | mov %r31, %r15 |
| 1843 | ldx [%r31+128], %r16 |
| 1844 | ldx [%r31+136], %r17 |
| 1845 | ldx [%r31+144], %r18 |
| 1846 | ldx [%r31+152], %r19 |
| 1847 | ldx [%r31+160], %r20 |
| 1848 | ldx [%r31+168], %r21 |
| 1849 | ldx [%r31+176], %r22 |
| 1850 | ldx [%r31+184], %r23 |
| 1851 | ldx [%r31+192], %r24 |
| 1852 | ldx [%r31+200], %r25 |
| 1853 | ldx [%r31+208], %r26 |
| 1854 | ldx [%r31+216], %r27 |
| 1855 | ldx [%r31+224], %r28 |
| 1856 | ldx [%r31+232], %r29 |
| 1857 | mov 0x34, %r14 |
| 1858 | mov 0x35, %r30 |
| 1859 | save %r31, %r0, %r31 |
| 1860 | ldx [%r31+0], %r0 |
| 1861 | ldx [%r31+8], %r1 |
| 1862 | ldx [%r31+16], %r2 |
| 1863 | ldx [%r31+24], %r3 |
| 1864 | ldx [%r31+32], %r4 |
| 1865 | ldx [%r31+40], %r5 |
| 1866 | ldx [%r31+48], %r6 |
| 1867 | ldx [%r31+56], %r7 |
| 1868 | ldx [%r31+64], %r8 |
| 1869 | ldx [%r31+72], %r9 |
| 1870 | ldx [%r31+80], %r10 |
| 1871 | ldx [%r31+88], %r11 |
| 1872 | ldx [%r31+96], %r12 |
| 1873 | ldx [%r31+104], %r13 |
| 1874 | ldx [%r31+112], %r14 |
| 1875 | mov %r31, %r15 |
| 1876 | ldx [%r31+128], %r16 |
| 1877 | ldx [%r31+136], %r17 |
| 1878 | ldx [%r31+144], %r18 |
| 1879 | ldx [%r31+152], %r19 |
| 1880 | ldx [%r31+160], %r20 |
| 1881 | ldx [%r31+168], %r21 |
| 1882 | ldx [%r31+176], %r22 |
| 1883 | ldx [%r31+184], %r23 |
| 1884 | ldx [%r31+192], %r24 |
| 1885 | ldx [%r31+200], %r25 |
| 1886 | ldx [%r31+208], %r26 |
| 1887 | ldx [%r31+216], %r27 |
| 1888 | ldx [%r31+224], %r28 |
| 1889 | ldx [%r31+232], %r29 |
| 1890 | mov 0xb2, %r14 |
| 1891 | mov 0x31, %r30 |
| 1892 | save %r31, %r0, %r31 |
| 1893 | ldx [%r31+0], %r0 |
| 1894 | ldx [%r31+8], %r1 |
| 1895 | ldx [%r31+16], %r2 |
| 1896 | ldx [%r31+24], %r3 |
| 1897 | ldx [%r31+32], %r4 |
| 1898 | ldx [%r31+40], %r5 |
| 1899 | ldx [%r31+48], %r6 |
| 1900 | ldx [%r31+56], %r7 |
| 1901 | ldx [%r31+64], %r8 |
| 1902 | ldx [%r31+72], %r9 |
| 1903 | ldx [%r31+80], %r10 |
| 1904 | ldx [%r31+88], %r11 |
| 1905 | ldx [%r31+96], %r12 |
| 1906 | ldx [%r31+104], %r13 |
| 1907 | ldx [%r31+112], %r14 |
| 1908 | mov %r31, %r15 |
| 1909 | ldx [%r31+128], %r16 |
| 1910 | ldx [%r31+136], %r17 |
| 1911 | ldx [%r31+144], %r18 |
| 1912 | ldx [%r31+152], %r19 |
| 1913 | ldx [%r31+160], %r20 |
| 1914 | ldx [%r31+168], %r21 |
| 1915 | ldx [%r31+176], %r22 |
| 1916 | ldx [%r31+184], %r23 |
| 1917 | ldx [%r31+192], %r24 |
| 1918 | ldx [%r31+200], %r25 |
| 1919 | ldx [%r31+208], %r26 |
| 1920 | ldx [%r31+216], %r27 |
| 1921 | ldx [%r31+224], %r28 |
| 1922 | ldx [%r31+232], %r29 |
| 1923 | mov 0x32, %r14 |
| 1924 | mov 0x32, %r30 |
| 1925 | save %r31, %r0, %r31 |
| 1926 | ldx [%r31+0], %r0 |
| 1927 | ldx [%r31+8], %r1 |
| 1928 | ldx [%r31+16], %r2 |
| 1929 | ldx [%r31+24], %r3 |
| 1930 | ldx [%r31+32], %r4 |
| 1931 | ldx [%r31+40], %r5 |
| 1932 | ldx [%r31+48], %r6 |
| 1933 | ldx [%r31+56], %r7 |
| 1934 | ldx [%r31+64], %r8 |
| 1935 | ldx [%r31+72], %r9 |
| 1936 | ldx [%r31+80], %r10 |
| 1937 | ldx [%r31+88], %r11 |
| 1938 | ldx [%r31+96], %r12 |
| 1939 | ldx [%r31+104], %r13 |
| 1940 | ldx [%r31+112], %r14 |
| 1941 | mov %r31, %r15 |
| 1942 | ldx [%r31+128], %r16 |
| 1943 | ldx [%r31+136], %r17 |
| 1944 | ldx [%r31+144], %r18 |
| 1945 | ldx [%r31+152], %r19 |
| 1946 | ldx [%r31+160], %r20 |
| 1947 | ldx [%r31+168], %r21 |
| 1948 | ldx [%r31+176], %r22 |
| 1949 | ldx [%r31+184], %r23 |
| 1950 | ldx [%r31+192], %r24 |
| 1951 | ldx [%r31+200], %r25 |
| 1952 | ldx [%r31+208], %r26 |
| 1953 | ldx [%r31+216], %r27 |
| 1954 | ldx [%r31+224], %r28 |
| 1955 | ldx [%r31+232], %r29 |
| 1956 | mov 0xb2, %r14 |
| 1957 | mov 0x31, %r30 |
| 1958 | save %r31, %r0, %r31 |
| 1959 | ldx [%r31+0], %r0 |
| 1960 | ldx [%r31+8], %r1 |
| 1961 | ldx [%r31+16], %r2 |
| 1962 | ldx [%r31+24], %r3 |
| 1963 | ldx [%r31+32], %r4 |
| 1964 | ldx [%r31+40], %r5 |
| 1965 | ldx [%r31+48], %r6 |
| 1966 | ldx [%r31+56], %r7 |
| 1967 | ldx [%r31+64], %r8 |
| 1968 | ldx [%r31+72], %r9 |
| 1969 | ldx [%r31+80], %r10 |
| 1970 | ldx [%r31+88], %r11 |
| 1971 | ldx [%r31+96], %r12 |
| 1972 | ldx [%r31+104], %r13 |
| 1973 | ldx [%r31+112], %r14 |
| 1974 | mov %r31, %r15 |
| 1975 | ldx [%r31+128], %r16 |
| 1976 | ldx [%r31+136], %r17 |
| 1977 | ldx [%r31+144], %r18 |
| 1978 | ldx [%r31+152], %r19 |
| 1979 | ldx [%r31+160], %r20 |
| 1980 | ldx [%r31+168], %r21 |
| 1981 | ldx [%r31+176], %r22 |
| 1982 | ldx [%r31+184], %r23 |
| 1983 | ldx [%r31+192], %r24 |
| 1984 | ldx [%r31+200], %r25 |
| 1985 | ldx [%r31+208], %r26 |
| 1986 | ldx [%r31+216], %r27 |
| 1987 | ldx [%r31+224], %r28 |
| 1988 | ldx [%r31+232], %r29 |
| 1989 | mov 0xb5, %r14 |
| 1990 | mov 0xb2, %r30 |
| 1991 | save %r31, %r0, %r31 |
| 1992 | ldx [%r31+0], %r0 |
| 1993 | ldx [%r31+8], %r1 |
| 1994 | ldx [%r31+16], %r2 |
| 1995 | ldx [%r31+24], %r3 |
| 1996 | ldx [%r31+32], %r4 |
| 1997 | ldx [%r31+40], %r5 |
| 1998 | ldx [%r31+48], %r6 |
| 1999 | ldx [%r31+56], %r7 |
| 2000 | ldx [%r31+64], %r8 |
| 2001 | ldx [%r31+72], %r9 |
| 2002 | ldx [%r31+80], %r10 |
| 2003 | ldx [%r31+88], %r11 |
| 2004 | ldx [%r31+96], %r12 |
| 2005 | ldx [%r31+104], %r13 |
| 2006 | ldx [%r31+112], %r14 |
| 2007 | mov %r31, %r15 |
| 2008 | ldx [%r31+128], %r16 |
| 2009 | ldx [%r31+136], %r17 |
| 2010 | ldx [%r31+144], %r18 |
| 2011 | ldx [%r31+152], %r19 |
| 2012 | ldx [%r31+160], %r20 |
| 2013 | ldx [%r31+168], %r21 |
| 2014 | ldx [%r31+176], %r22 |
| 2015 | ldx [%r31+184], %r23 |
| 2016 | ldx [%r31+192], %r24 |
| 2017 | ldx [%r31+200], %r25 |
| 2018 | ldx [%r31+208], %r26 |
| 2019 | ldx [%r31+216], %r27 |
| 2020 | ldx [%r31+224], %r28 |
| 2021 | ldx [%r31+232], %r29 |
| 2022 | mov 0xb2, %r14 |
| 2023 | mov 0xb3, %r30 |
| 2024 | save %r31, %r0, %r31 |
| 2025 | restore |
| 2026 | restore |
| 2027 | restore |
| 2028 | !Initializing float registers |
| 2029 | ldd [%r31+0], %f0 |
| 2030 | ldd [%r31+16], %f2 |
| 2031 | ldd [%r31+32], %f4 |
| 2032 | ldd [%r31+48], %f6 |
| 2033 | ldd [%r31+64], %f8 |
| 2034 | ldd [%r31+80], %f10 |
| 2035 | ldd [%r31+96], %f12 |
| 2036 | ldd [%r31+112], %f14 |
| 2037 | ldd [%r31+128], %f16 |
| 2038 | ldd [%r31+144], %f18 |
| 2039 | ldd [%r31+160], %f20 |
| 2040 | ldd [%r31+176], %f22 |
| 2041 | ldd [%r31+192], %f24 |
| 2042 | ldd [%r31+208], %f26 |
| 2043 | ldd [%r31+224], %f28 |
| 2044 | ldd [%r31+240], %f30 |
| 2045 | !! Set TPC/TNPC to diag-finish in case we get to a strange TL .. |
| 2046 | ta T_CHANGE_HPRIV |
| 2047 | setx diag_finish, %r29, %r28 |
| 2048 | add %r28, 4, %r29 |
| 2049 | wrpr %g0, 1, %tl |
| 2050 | wrpr %r28, %tpc |
| 2051 | wrpr %r29, %tnpc |
| 2052 | wrpr %g0, 2, %tl |
| 2053 | wrpr %r28, %tpc |
| 2054 | wrpr %r29, %tnpc |
| 2055 | wrpr %g0, 3, %tl |
| 2056 | wrpr %r28, %tpc |
| 2057 | wrpr %r29, %tnpc |
| 2058 | wrpr %g0, 4, %tl |
| 2059 | wrpr %r28, %tpc |
| 2060 | wrpr %r29, %tnpc |
| 2061 | wrpr %g0, 5, %tl |
| 2062 | wrpr %r28, %tpc |
| 2063 | wrpr %r29, %tnpc |
| 2064 | wrpr %g0, 6, %tl |
| 2065 | wrpr %r28, %tpc |
| 2066 | wrpr %r29, %tnpc |
| 2067 | wrpr %g0, 0, %tl |
| 2068 | |
| 2069 | !Initializing Tick Cmprs |
| 2070 | mov 1, %g2 |
| 2071 | sllx %g2, 63, %g2 |
| 2072 | or %g1, %g2, %g1 |
| 2073 | wrhpr %g1, %g0, %hsys_tick_cmpr |
| 2074 | wr %g1, %g0, %tick_cmpr |
| 2075 | wr %g1, %g0, %sys_tick_cmpr |
| 2076 | |
| 2077 | #if (MULTIPASS > 0) |
| 2078 | mov 0x38, %g1 |
| 2079 | stxa %r0, [%g1]ASI_SCRATCHPAD |
| 2080 | #endif |
| 2081 | |
| 2082 | ! Set up fpr PMU traps |
| 2083 | set 0x21810df2, %g2 |
| 2084 | b fork_threads |
| 2085 | wr %g2, %g0, %pcr |
| 2086 | |
| 2087 | common_target: |
| 2088 | nop |
| 2089 | sub %r27, 8, %r27 |
| 2090 | and %r27, 8, %r12 |
| 2091 | mov HIGHVA_HIGHNUM, %r11 |
| 2092 | sllx %r11, 32, %r11 |
| 2093 | or %r27, %r11, %r27 |
| 2094 | brz,a %r12, .+8 |
| 2095 | lduw [%r27], %r12 ! load jmp dest into dcache - xinval |
| 2096 | jmp %r27 |
| 2097 | .word 0x87a94a46 ! 1: FCMPd fcmpd %fcc<n>, %f36, %f6 |
| 2098 | nop |
| 2099 | jmp %r27 |
| 2100 | nop |
| 2101 | fork_threads: |
| 2102 | rd %tick, %r17 |
| 2103 | mov 0x40, %g1 |
| 2104 | setup_hwtw_config: |
| 2105 | stxa %r17, [%g1]0x58 |
| 2106 | ta %icc, T_RD_THID |
| 2107 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x1 |
| 2108 | cmp %o1, 0 |
| 2109 | setx fork_lbl_0_1, %g2, %g3 |
| 2110 | be,a .+8 |
| 2111 | jmp %g3 |
| 2112 | nop |
| 2113 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x2 |
| 2114 | cmp %o1, 1 |
| 2115 | setx fork_lbl_0_2, %g2, %g3 |
| 2116 | be,a .+8 |
| 2117 | jmp %g3 |
| 2118 | nop |
| 2119 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x4 |
| 2120 | cmp %o1, 2 |
| 2121 | setx fork_lbl_0_3, %g2, %g3 |
| 2122 | be,a .+8 |
| 2123 | jmp %g3 |
| 2124 | nop |
| 2125 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x8 |
| 2126 | cmp %o1, 3 |
| 2127 | setx fork_lbl_0_4, %g2, %g3 |
| 2128 | be,a .+8 |
| 2129 | jmp %g3 |
| 2130 | nop |
| 2131 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x10 |
| 2132 | cmp %o1, 4 |
| 2133 | setx fork_lbl_0_5, %g2, %g3 |
| 2134 | be,a .+8 |
| 2135 | jmp %g3 |
| 2136 | nop |
| 2137 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x20 |
| 2138 | cmp %o1, 5 |
| 2139 | setx fork_lbl_0_6, %g2, %g3 |
| 2140 | be,a .+8 |
| 2141 | jmp %g3 |
| 2142 | nop |
| 2143 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x40 |
| 2144 | cmp %o1, 6 |
| 2145 | setx fork_lbl_0_7, %g2, %g3 |
| 2146 | be,a .+8 |
| 2147 | jmp %g3 |
| 2148 | nop |
| 2149 | ! fork: source strm = 0xffffffffffffffff; target strm = 0x80 |
| 2150 | cmp %o1, 7 |
| 2151 | setx fork_lbl_0_8, %g2, %g3 |
| 2152 | be,a .+8 |
| 2153 | jmp %g3 |
| 2154 | nop |
| 2155 | .text |
| 2156 | setx join_lbl_0_0, %g1, %g2 |
| 2157 | jmp %g2 |
| 2158 | nop |
| 2159 | .text |
| 2160 | setx join_lbl_0_0, %g1, %g2 |
| 2161 | jmp %g2 |
| 2162 | nop |
| 2163 | fork_lbl_0_8: |
| 2164 | setup_tick: |
| 2165 | setx 0x35fa54dc6e413323, %r1, %r17 |
| 2166 | wrpr %g0, %r17, %tick |
| 2167 | |
| 2168 | rd %asi, %r12 |
| 2169 | #ifdef XIR_RND_CORES |
| 2170 | setup_xir_80: |
| 2171 | setx 0xcbd887619c93dcb4, %r1, %r28 |
| 2172 | mov 0x30, %r17 |
| 2173 | stxa %r28, [%r17] 0x41 |
| 2174 | #endif |
| 2175 | setup_spu_80: |
| 2176 | wr %g0, 0x40, %asi |
| 2177 | !# allocate control word queue (e.g., setup head/tail/first/last registers) |
| 2178 | set CWQ_BASE, %l6 |
| 2179 | |
| 2180 | #ifndef SPC |
| 2181 | ldxa [%g0]0x63, %o2 |
| 2182 | and %o2, 0x38, %o2 |
| 2183 | sllx %o2, 5, %o2 !(CID*256) |
| 2184 | add %l6, %o2, %l6 |
| 2185 | #endif |
| 2186 | # 879 "diag.j.pp" |
| 2187 | !# write base addr to first, head, and tail ptr |
| 2188 | !# first store to first |
| 2189 | stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi !# first store to first |
| 2190 | |
| 2191 | stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi !# then to head |
| 2192 | stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi !# then to tail |
| 2193 | setx CWQ_LAST, %g1, %l5 !# then end of CWQ region to LAST |
| 2194 | #ifndef SPC |
| 2195 | add %l5, %o2, %l5 |
| 2196 | #endif |
| 2197 | stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi |
| 2198 | |
| 2199 | !# set CWQ control word ([39:37] is strand ID ..) |
| 2200 | best_set_reg(0x206100b0, %l1, %l2) !# Control Word |
| 2201 | sllx %l2, 32, %l2 |
| 2202 | |
| 2203 | !# write CWQ entry (%l6 points to CWQ) |
| 2204 | stx %l2, [%l6 + 0x0] |
| 2205 | |
| 2206 | setx msg, %g1, %l2 |
| 2207 | stx %l2, [%l6 + 0x8] !# source address |
| 2208 | |
| 2209 | stx %g0, [%l6 + 0x10] !# Authentication Key Address (40-bit) |
| 2210 | stx %g0, [%l6 + 0x18] !# Authentication IV Address (40-bit) |
| 2211 | stx %g0, [%l6 + 0x20] !# Authentication FSAS Address (40-bit) |
| 2212 | stx %g0, [%l6 + 0x28] !# Encryption Key Address (40-bit) |
| 2213 | stx %g0, [%l6 + 0x30] !# Encryption Initialization Vector Address (40-bit) |
| 2214 | |
| 2215 | setx results, %g1, %o3 |
| 2216 | stx %o3, [%l6 + 0x38] !# Destination Address (40-bit) |
| 2217 | |
| 2218 | membar #Sync |
| 2219 | |
| 2220 | ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2 |
| 2221 | add %l2, 0x40, %l2 |
| 2222 | stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi |
| 2223 | |
| 2224 | !# Kick off the CWQ operation by writing to the CWQ_CSR |
| 2225 | !# Set the enabled bit and reset the other bits |
| 2226 | or %g0, 0x1, %g1 |
| 2227 | stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 2228 | |
| 2229 | unlock_sync_thds_80: |
| 2230 | set sync_thr_counter6, %r23 |
| 2231 | #ifndef SPC |
| 2232 | ldxa [%g0]0x63, %o2 |
| 2233 | and %o2, 0x38, %o2 |
| 2234 | add %o2, %r23, %r23 |
| 2235 | #endif |
| 2236 | st %r0, [%r23] !unlock sync_thr_counter6 |
| 2237 | sub %r23, 64, %r23 |
| 2238 | st %r0, [%r23] !unlock sync_thr_counter5 |
| 2239 | sub %r23, 64, %r23 |
| 2240 | st %r0, [%r23] !unlock sync_thr_counter4 |
| 2241 | |
| 2242 | wr %r0, %r12, %asi |
| 2243 | ta T_CHANGE_NONHPRIV |
| 2244 | .word 0xe877e082 ! 1: STX_I stx %r20, [%r31 + 0x0082] |
| 2245 | br_longdelay4_80_0: |
| 2246 | nop |
| 2247 | not %g0, %r27 |
| 2248 | jmpl %r27+0, %r27 |
| 2249 | .word 0x9d902002 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0002, %wstate |
| 2250 | .word 0xe93fe054 ! 3: STDF_I std %f20, [0x0054, %r31] |
| 2251 | fpinit_80_1: |
| 2252 | nop |
| 2253 | setx fp_data_quads, %r19, %r20 |
| 2254 | ldd [%r20], %f0 |
| 2255 | ldd [%r20+8], %f4 |
| 2256 | ld [%r20+16], %fsr |
| 2257 | ld [%r20+24], %r19 |
| 2258 | wr %r19, %g0, %gsr |
| 2259 | .word 0x89a009a4 ! 4: FDIVs fdivs %f0, %f4, %f4 |
| 2260 | splash_lsu_80_2: |
| 2261 | nop |
| 2262 | ta T_CHANGE_HPRIV |
| 2263 | set 0x1846bed8, %r2 |
| 2264 | mov 0x7, %r1 |
| 2265 | sllx %r1, 32, %r1 |
| 2266 | or %r1, %r2, %r2 |
| 2267 | .word 0x26800001 ! 1: BL bl,a <label_0x1> |
| 2268 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 2269 | ta T_CHANGE_NONHPRIV |
| 2270 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 2271 | splash_hpstate_80_3: |
| 2272 | .word 0x81982cde ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x0cde, %hpstate |
| 2273 | memptr_80_4: |
| 2274 | set 0x60740000, %r31 |
| 2275 | .word 0x858531f5 ! 7: WRCCR_I wr %r20, 0x11f5, %ccr |
| 2276 | nop |
| 2277 | mov 0x80, %g3 |
| 2278 | .word 0x26800001 ! 1: BL bl,a <label_0x1> |
| 2279 | stxa %g3, [%g3] 0x5f |
| 2280 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 2281 | .word 0xc19fe000 ! 9: LDDFA_I ldda [%r31, 0x0000], %f0 |
| 2282 | splash_tick_80_5: |
| 2283 | nop |
| 2284 | ta T_CHANGE_HPRIV |
| 2285 | best_set_reg(0x13ff3c4654610161, %r16, %r17) |
| 2286 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 2287 | .word 0xc1bfd920 ! 11: STDFA_R stda %f0, [%r0, %r31] |
| 2288 | dvapa_80_6: |
| 2289 | nop |
| 2290 | ta T_CHANGE_HPRIV |
| 2291 | mov 0xe73, %r20 |
| 2292 | mov 0xa, %r19 |
| 2293 | sllx %r20, 23, %r20 |
| 2294 | or %r19, %r20, %r19 |
| 2295 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 2296 | mov 0x38, %r18 |
| 2297 | stxa %r31, [%r18]0x58 |
| 2298 | ta T_CHANGE_NONHPRIV |
| 2299 | .word 0xc1bfd920 ! 12: STDFA_R stda %f0, [%r0, %r31] |
| 2300 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 2301 | jmptr_80_7: |
| 2302 | nop |
| 2303 | best_set_reg(0xe0a00000, %r20, %r27) |
| 2304 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 2305 | pmu_80_8: |
| 2306 | nop |
| 2307 | ta T_CHANGE_PRIV |
| 2308 | setx 0xffffffbfffffffae, %g1, %g7 |
| 2309 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 2310 | jmptr_80_9: |
| 2311 | nop |
| 2312 | best_set_reg(0xe0a00000, %r20, %r27) |
| 2313 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 2314 | nop |
| 2315 | ta T_CHANGE_HPRIV |
| 2316 | mov 0x80, %r10 |
| 2317 | set sync_thr_counter6, %r23 |
| 2318 | #ifndef SPC |
| 2319 | ldxa [%g0]0x63, %o1 |
| 2320 | and %o1, 0x38, %o1 |
| 2321 | add %o1, %r23, %r23 |
| 2322 | #endif |
| 2323 | cas [%r23],%g0,%r10 !lock |
| 2324 | brnz %r10, sma_80_10 |
| 2325 | rd %asi, %r12 |
| 2326 | wr %g0, 0x40, %asi |
| 2327 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 2328 | set 0x000e1fff, %g1 |
| 2329 | stxa %g1, [%g0 + 0x80] %asi |
| 2330 | wr %r12, %g0, %asi |
| 2331 | st %g0, [%r23] |
| 2332 | sma_80_10: |
| 2333 | ta T_CHANGE_NONHPRIV |
| 2334 | .word 0xe9e7e00b ! 17: CASA_R casa [%r31] %asi, %r11, %r20 |
| 2335 | .word 0x87802004 ! 18: WRASI_I wr %r0, 0x0004, %asi |
| 2336 | splash_lsu_80_11: |
| 2337 | nop |
| 2338 | ta T_CHANGE_HPRIV |
| 2339 | set 0x02f655af, %r2 |
| 2340 | mov 0x7, %r1 |
| 2341 | sllx %r1, 32, %r1 |
| 2342 | or %r1, %r2, %r2 |
| 2343 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 2344 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 2345 | .word 0xe93fe1e2 ! 20: STDF_I std %f20, [0x01e2, %r31] |
| 2346 | brcommon1_80_12: |
| 2347 | nop |
| 2348 | setx common_target, %r12, %r27 |
| 2349 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 2350 | ba,a .+12 |
| 2351 | .word 0xa9b7c7c8 ! 1: PDIST pdistn %d62, %d8, %d20 |
| 2352 | ba,a .+8 |
| 2353 | jmpl %r27+0, %r27 |
| 2354 | .word 0x95b44491 ! 21: FCMPLE32 fcmple32 %d48, %d48, %r10 |
| 2355 | splash_lsu_80_13: |
| 2356 | nop |
| 2357 | ta T_CHANGE_HPRIV |
| 2358 | set 0x51f68fec, %r2 |
| 2359 | mov 0x4, %r1 |
| 2360 | sllx %r1, 32, %r1 |
| 2361 | or %r1, %r2, %r2 |
| 2362 | .word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1> |
| 2363 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 2364 | ta T_CHANGE_NONHPRIV |
| 2365 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 2366 | .word 0xc19fdc00 ! 23: LDDFA_R ldda [%r31, %r0], %f0 |
| 2367 | .word 0xe1bfc3e0 ! 24: STDFA_R stda %f16, [%r0, %r31] |
| 2368 | pmu_80_14: |
| 2369 | nop |
| 2370 | ta T_CHANGE_PRIV |
| 2371 | setx 0xffffffb8ffffffa0, %g1, %g7 |
| 2372 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 2373 | rd %tick, %r28 |
| 2374 | #if (MAX_THREADS == 8) |
| 2375 | sethi %hi(0x33800), %r27 |
| 2376 | #else |
| 2377 | sethi %hi(0x30000), %r27 |
| 2378 | #endif |
| 2379 | andn %r28, %r27, %r28 |
| 2380 | ta T_CHANGE_HPRIV |
| 2381 | stxa %r28, [%g0] 0x73 |
| 2382 | .word 0xc36b3717 ! 1: PREFETCH_I prefetch [%r12 + 0xfffff717], #one_read |
| 2383 | intvec_80_15: |
| 2384 | .word 0x97a4c9ca ! 26: FDIVd fdivd %f50, %f10, %f42 |
| 2385 | cmp_80_16: |
| 2386 | nop |
| 2387 | ta T_CHANGE_HPRIV |
| 2388 | rd %asi, %r12 |
| 2389 | wr %r0, 0x41, %asi |
| 2390 | set sync_thr_counter4, %r23 |
| 2391 | #ifndef SPC |
| 2392 | ldxa [%g0]0x63, %r8 |
| 2393 | and %r8, 0x38, %r8 ! Core ID |
| 2394 | add %r8, %r23, %r23 |
| 2395 | mov 0xff, %r9 |
| 2396 | xor %r9, 0x80, %r9 |
| 2397 | sllx %r9, %r8, %r9 ! My core mask |
| 2398 | #else |
| 2399 | mov 0, %r8 |
| 2400 | mov 0xff, %r9 |
| 2401 | xor %r9, 0x80, %r9 ! My core mask |
| 2402 | #endif |
| 2403 | mov 0x80, %r10 |
| 2404 | cmp_startwait80_16: |
| 2405 | cas [%r23],%g0,%r10 !lock |
| 2406 | brz,a %r10, continue_cmp_80_16 |
| 2407 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2408 | ld [%r23], %r10 |
| 2409 | cmp_wait80_16: |
| 2410 | brnz,a %r10, cmp_wait80_16 |
| 2411 | ld [%r23], %r10 |
| 2412 | ba cmp_startwait80_16 |
| 2413 | mov 0x80, %r10 |
| 2414 | continue_cmp_80_16: |
| 2415 | ldxa [0x58]%asi, %r14 !Running_status |
| 2416 | xnor %r14, %r13, %r14 !Bits equal |
| 2417 | brz,a %r8, cmp_multi_core_80_16 |
| 2418 | mov 0xc2, %r17 |
| 2419 | best_set_reg(0x0e000cc4361d4b95, %r16, %r17) |
| 2420 | cmp_multi_core_80_16: |
| 2421 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 2422 | and %r14, %r9, %r14 !Apply core-mask |
| 2423 | stxa %r14, [0x60]%asi |
| 2424 | st %g0, [%r23] !clear lock |
| 2425 | wr %g0, %r12, %asi |
| 2426 | .word 0x9194c00c ! 27: WRPR_PIL_R wrpr %r19, %r12, %pil |
| 2427 | nop |
| 2428 | mov 0x80, %g3 |
| 2429 | stxa %r6, [%r0] ASI_LSU_CONTROL |
| 2430 | stxa %g3, [%g3] 0x57 |
| 2431 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 2432 | #if (defined SPC || defined CMP) |
| 2433 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_80_17)+32, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 2434 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_80_17)&0xffffffff) + 56, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 2435 | xir_80_17: |
| 2436 | #else |
| 2437 | #if (defined FC) |
| 2438 | !! Generate XIR via RESET_GEN register |
| 2439 | ta T_CHANGE_HPRIV |
| 2440 | rdpr %pstate, %r18 |
| 2441 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 2442 | wrpr %r18, %pstate |
| 2443 | #ifndef XIR_RND_CORES |
| 2444 | ldxa [%g0] 0x63, %o1 |
| 2445 | mov 1, %r18 |
| 2446 | sllx %r18, %o1, %r18 |
| 2447 | #endif |
| 2448 | mov 0x30, %r19 |
| 2449 | setx 0x8900000808, %r16, %r17 |
| 2450 | mov 0x2, %r16 |
| 2451 | xir_80_17: |
| 2452 | stxa %r18, [%r19] 0x41 |
| 2453 | stx %r16, [%r17] |
| 2454 | #endif |
| 2455 | #endif |
| 2456 | .word 0xa9852894 ! 29: WR_SET_SOFTINT_I wr %r20, 0x0894, %set_softint |
| 2457 | cmp_80_18: |
| 2458 | nop |
| 2459 | ta T_CHANGE_HPRIV |
| 2460 | rd %asi, %r12 |
| 2461 | wr %r0, 0x41, %asi |
| 2462 | set sync_thr_counter4, %r23 |
| 2463 | #ifndef SPC |
| 2464 | ldxa [%g0]0x63, %r8 |
| 2465 | and %r8, 0x38, %r8 ! Core ID |
| 2466 | add %r8, %r23, %r23 |
| 2467 | mov 0xff, %r9 |
| 2468 | xor %r9, 0x80, %r9 |
| 2469 | sllx %r9, %r8, %r9 ! My core mask |
| 2470 | #else |
| 2471 | mov 0, %r8 |
| 2472 | mov 0xff, %r9 |
| 2473 | xor %r9, 0x80, %r9 ! My core mask |
| 2474 | #endif |
| 2475 | mov 0x80, %r10 |
| 2476 | cmp_startwait80_18: |
| 2477 | cas [%r23],%g0,%r10 !lock |
| 2478 | brz,a %r10, continue_cmp_80_18 |
| 2479 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2480 | ld [%r23], %r10 |
| 2481 | cmp_wait80_18: |
| 2482 | brnz,a %r10, cmp_wait80_18 |
| 2483 | ld [%r23], %r10 |
| 2484 | ba cmp_startwait80_18 |
| 2485 | mov 0x80, %r10 |
| 2486 | continue_cmp_80_18: |
| 2487 | ldxa [0x58]%asi, %r14 !Running_status |
| 2488 | xnor %r14, %r13, %r14 !Bits equal |
| 2489 | brz,a %r8, cmp_multi_core_80_18 |
| 2490 | mov 49, %r17 |
| 2491 | best_set_reg(0xcefe037aaee8500b, %r16, %r17) |
| 2492 | cmp_multi_core_80_18: |
| 2493 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 2494 | and %r14, %r9, %r14 !Apply core-mask |
| 2495 | stxa %r14, [0x60]%asi |
| 2496 | st %g0, [%r23] !clear lock |
| 2497 | wr %g0, %r12, %asi |
| 2498 | ta T_CHANGE_NONHPRIV |
| 2499 | .word 0x91a00173 ! 30: FABSq dis not found |
| 2500 | |
| 2501 | cmp_80_19: |
| 2502 | nop |
| 2503 | ta T_CHANGE_HPRIV |
| 2504 | rd %asi, %r12 |
| 2505 | wr %r0, 0x41, %asi |
| 2506 | set sync_thr_counter4, %r23 |
| 2507 | #ifndef SPC |
| 2508 | ldxa [%g0]0x63, %r8 |
| 2509 | and %r8, 0x38, %r8 ! Core ID |
| 2510 | add %r8, %r23, %r23 |
| 2511 | mov 0xff, %r9 |
| 2512 | xor %r9, 0x80, %r9 |
| 2513 | sllx %r9, %r8, %r9 ! My core mask |
| 2514 | #else |
| 2515 | mov 0, %r8 |
| 2516 | mov 0xff, %r9 |
| 2517 | xor %r9, 0x80, %r9 ! My core mask |
| 2518 | #endif |
| 2519 | mov 0x80, %r10 |
| 2520 | cmp_startwait80_19: |
| 2521 | cas [%r23],%g0,%r10 !lock |
| 2522 | brz,a %r10, continue_cmp_80_19 |
| 2523 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2524 | ld [%r23], %r10 |
| 2525 | cmp_wait80_19: |
| 2526 | brnz,a %r10, cmp_wait80_19 |
| 2527 | ld [%r23], %r10 |
| 2528 | ba cmp_startwait80_19 |
| 2529 | mov 0x80, %r10 |
| 2530 | continue_cmp_80_19: |
| 2531 | ldxa [0x58]%asi, %r14 !Running_status |
| 2532 | xnor %r14, %r13, %r14 !Bits equal |
| 2533 | brz,a %r8, cmp_multi_core_80_19 |
| 2534 | mov 5, %r17 |
| 2535 | best_set_reg(0xc000c3a54f360794, %r16, %r17) |
| 2536 | cmp_multi_core_80_19: |
| 2537 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 2538 | and %r14, %r9, %r14 !Apply core-mask |
| 2539 | stxa %r14, [0x68]%asi |
| 2540 | st %g0, [%r23] !clear lock |
| 2541 | wr %g0, %r12, %asi |
| 2542 | ta T_CHANGE_NONHPRIV |
| 2543 | .word 0xa3a00169 ! 31: FABSq dis not found |
| 2544 | |
| 2545 | tagged_80_20: |
| 2546 | tsubcctv %r9, 0x128c, %r16 |
| 2547 | .word 0xd807e0fc ! 32: LDUW_I lduw [%r31 + 0x00fc], %r12 |
| 2548 | mondo_80_21: |
| 2549 | nop |
| 2550 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 2551 | stxa %r2, [%r0+0x3c8] %asi |
| 2552 | .word 0x9d948014 ! 33: WRPR_WSTATE_R wrpr %r18, %r20, %wstate |
| 2553 | .word 0xb184c010 ! 34: WR_STICK_REG_R wr %r19, %r16, %- |
| 2554 | nop |
| 2555 | ta T_CHANGE_HPRIV |
| 2556 | mov 0x80, %r10 |
| 2557 | set sync_thr_counter6, %r23 |
| 2558 | #ifndef SPC |
| 2559 | ldxa [%g0]0x63, %o1 |
| 2560 | and %o1, 0x38, %o1 |
| 2561 | add %o1, %r23, %r23 |
| 2562 | #endif |
| 2563 | cas [%r23],%g0,%r10 !lock |
| 2564 | brnz %r10, sma_80_22 |
| 2565 | rd %asi, %r12 |
| 2566 | wr %g0, 0x40, %asi |
| 2567 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 2568 | set 0x000e1fff, %g1 |
| 2569 | stxa %g1, [%g0 + 0x80] %asi |
| 2570 | wr %r12, %g0, %asi |
| 2571 | st %g0, [%r23] |
| 2572 | sma_80_22: |
| 2573 | ta T_CHANGE_NONHPRIV |
| 2574 | .word 0xd9e7e011 ! 35: CASA_R casa [%r31] %asi, %r17, %r12 |
| 2575 | nop |
| 2576 | ta T_CHANGE_HPRIV |
| 2577 | mov 0x80, %r10 |
| 2578 | set sync_thr_counter6, %r23 |
| 2579 | #ifndef SPC |
| 2580 | ldxa [%g0]0x63, %o1 |
| 2581 | and %o1, 0x38, %o1 |
| 2582 | add %o1, %r23, %r23 |
| 2583 | #endif |
| 2584 | cas [%r23],%g0,%r10 !lock |
| 2585 | brnz %r10, sma_80_23 |
| 2586 | rd %asi, %r12 |
| 2587 | wr %g0, 0x40, %asi |
| 2588 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 2589 | set 0x00061fff, %g1 |
| 2590 | stxa %g1, [%g0 + 0x80] %asi |
| 2591 | wr %r12, %g0, %asi |
| 2592 | st %g0, [%r23] |
| 2593 | sma_80_23: |
| 2594 | ta T_CHANGE_NONHPRIV |
| 2595 | .word 0xd9e7e012 ! 36: CASA_R casa [%r31] %asi, %r18, %r12 |
| 2596 | splash_tba_80_24: |
| 2597 | nop |
| 2598 | ta T_CHANGE_PRIV |
| 2599 | set 0x120000, %r12 |
| 2600 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 2601 | splash_lsu_80_25: |
| 2602 | nop |
| 2603 | ta T_CHANGE_HPRIV |
| 2604 | set 0xd111120a, %r2 |
| 2605 | mov 0x4, %r1 |
| 2606 | sllx %r1, 32, %r1 |
| 2607 | or %r1, %r2, %r2 |
| 2608 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 2609 | ta T_CHANGE_NONHPRIV |
| 2610 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 2611 | #if (defined SPC || defined CMP1) |
| 2612 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_26) + 24, 16, 16)) -> intp(7,0,11,,,,,1) |
| 2613 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_26)&0xffffffff) + 32, 16, 16)) -> intp(4,0,7,,,,,1) |
| 2614 | #else |
| 2615 | set 0x595054f1, %r28 |
| 2616 | #if (MAX_THREADS == 8) |
| 2617 | and %r28, 0x7ff, %r28 |
| 2618 | #endif |
| 2619 | stxa %r28, [%g0] 0x73 |
| 2620 | #endif |
| 2621 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 2622 | intvec_80_26: |
| 2623 | .word 0xa9b404d2 ! 39: FCMPNE32 fcmpne32 %d16, %d18, %r20 |
| 2624 | .word 0xd727e16d ! 40: STF_I st %f11, [0x016d, %r31] |
| 2625 | .word 0xd627e1a8 ! 41: STW_I stw %r11, [%r31 + 0x01a8] |
| 2626 | jmptr_80_27: |
| 2627 | nop |
| 2628 | best_set_reg(0xe0a00000, %r20, %r27) |
| 2629 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 2630 | splash_tba_80_28: |
| 2631 | nop |
| 2632 | ta T_CHANGE_PRIV |
| 2633 | set 0x120000, %r12 |
| 2634 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 2635 | set 0xecb, %l3 |
| 2636 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 2637 | .word 0x95b4c7c9 ! 44: PDIST pdistn %d50, %d40, %d10 |
| 2638 | pmu_80_29: |
| 2639 | nop |
| 2640 | setx 0xffffffbaffffffa6, %g1, %g7 |
| 2641 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 2642 | brcommon3_80_30: |
| 2643 | nop |
| 2644 | setx common_target, %r12, %r27 |
| 2645 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 2646 | ba,a .+12 |
| 2647 | .word 0xe3e7c030 ! 1: CASA_I casa [%r31] 0x 1, %r16, %r17 |
| 2648 | ba,a .+8 |
| 2649 | jmpl %r27+0, %r27 |
| 2650 | .word 0xe31fe1b0 ! 46: LDDF_I ldd [%r31, 0x01b0], %f17 |
| 2651 | brcommon3_80_31: |
| 2652 | nop |
| 2653 | setx common_target, %r12, %r27 |
| 2654 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 2655 | ba,a .+12 |
| 2656 | .word 0xe26fe060 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x0060] |
| 2657 | ba,a .+8 |
| 2658 | jmpl %r27+0, %r27 |
| 2659 | stxa %r10, [%r0] ASI_LSU_CONTROL |
| 2660 | .word 0x93aac830 ! 47: FMOVGE fmovs %fcc1, %f16, %f9 |
| 2661 | brcommon3_80_32: |
| 2662 | nop |
| 2663 | setx common_target, %r12, %r27 |
| 2664 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 2665 | ba,a .+12 |
| 2666 | .word 0xd737e0c0 ! 1: STQF_I - %f11, [0x00c0, %r31] |
| 2667 | ba,a .+8 |
| 2668 | jmpl %r27+0, %r27 |
| 2669 | .word 0xd73fc010 ! 48: STDF_R std %f11, [%r16, %r31] |
| 2670 | nop |
| 2671 | mov 0x80, %g3 |
| 2672 | .word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 2673 | stxa %g3, [%g3] 0x5f |
| 2674 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 2675 | nop |
| 2676 | ta T_CHANGE_HPRIV ! macro |
| 2677 | donret_80_33: |
| 2678 | rd %pc, %r12 |
| 2679 | mov HIGHVA_HIGHNUM, %r10 |
| 2680 | sllx %r10, 32, %r10 |
| 2681 | or %r12, %r10, %r12 |
| 2682 | add %r12, (donretarg_80_33-donret_80_33), %r12 |
| 2683 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 2684 | andn %r11, %r10, %r11 ! low VA tnpc |
| 2685 | wrpr %g0, 0x1, %tl |
| 2686 | wrpr %g0, %r12, %tpc |
| 2687 | wrpr %g0, %r11, %tnpc |
| 2688 | set (0x00288900 | (0x8b << 24)), %r13 |
| 2689 | and %r12, 0xfff, %r14 |
| 2690 | sllx %r14, 32, %r14 |
| 2691 | or %r13, %r14, %r20 |
| 2692 | wrpr %r20, %g0, %tstate |
| 2693 | wrhpr %g0, 0x1c56, %htstate |
| 2694 | ta T_CHANGE_NONHPRIV ! rand=1 (80) |
| 2695 | ldx [%r11+%r0], %g1 |
| 2696 | done |
| 2697 | donretarg_80_33: |
| 2698 | .word 0x2a800001 ! 50: BCS bcs,a <label_0x1> |
| 2699 | #if (defined SPC || defined CMP1) |
| 2700 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_34) + 24, 16, 16)) -> intp(7,0,16,,,,,1) |
| 2701 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_34)&0xffffffff) + 48, 16, 16)) -> intp(3,0,13,,,,,1) |
| 2702 | #else |
| 2703 | set 0x36b01868, %r28 |
| 2704 | #if (MAX_THREADS == 8) |
| 2705 | and %r28, 0x7ff, %r28 |
| 2706 | #endif |
| 2707 | stxa %r28, [%g0] 0x73 |
| 2708 | #endif |
| 2709 | intvec_80_34: |
| 2710 | .word 0xa3a209d0 ! 51: FDIVd fdivd %f8, %f16, %f48 |
| 2711 | .word 0xe927e06d ! 52: STF_I st %f20, [0x006d, %r31] |
| 2712 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 2713 | splash_tba_80_35: |
| 2714 | nop |
| 2715 | ta T_CHANGE_PRIV |
| 2716 | setx 0x00000000003a0000, %r11, %r12 |
| 2717 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 2718 | .word 0xc3ed0030 ! 55: PREFETCHA_R prefetcha [%r20, %r16] 0x01, #one_read |
| 2719 | ibp_80_37: |
| 2720 | nop |
| 2721 | ta T_CHANGE_HPRIV |
| 2722 | mov 8, %r18 |
| 2723 | rd %asi, %r12 |
| 2724 | wr %r0, 0x41, %asi |
| 2725 | set sync_thr_counter4, %r23 |
| 2726 | #ifndef SPC |
| 2727 | ldxa [%g0]0x63, %r8 |
| 2728 | and %r8, 0x38, %r8 ! Core ID |
| 2729 | add %r8, %r23, %r23 |
| 2730 | #else |
| 2731 | mov 0, %r8 |
| 2732 | #endif |
| 2733 | mov 0x80, %r16 |
| 2734 | ibp_startwait80_37: |
| 2735 | cas [%r23],%g0,%r16 !lock |
| 2736 | brz,a %r16, continue_ibp_80_37 |
| 2737 | mov (~0x80&0xf0), %r16 |
| 2738 | ld [%r23], %r16 |
| 2739 | ibp_wait80_37: |
| 2740 | brnz %r16, ibp_wait80_37 |
| 2741 | ld [%r23], %r16 |
| 2742 | ba ibp_startwait80_37 |
| 2743 | mov 0x80, %r16 |
| 2744 | continue_ibp_80_37: |
| 2745 | sllx %r16, %r8, %r16 !Mask for my core only |
| 2746 | ldxa [0x58]%asi, %r17 !Running_status |
| 2747 | wait_for_stat_80_37: |
| 2748 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2749 | cmp %r13, %r17 |
| 2750 | bne,a %xcc, wait_for_stat_80_37 |
| 2751 | ldxa [0x58]%asi, %r17 !Running_status |
| 2752 | stxa %r16, [0x68]%asi !Park (W1C) |
| 2753 | ldxa [0x50]%asi, %r14 !Running_rw |
| 2754 | wait_for_ibp_80_37: |
| 2755 | ldxa [0x58]%asi, %r17 !Running_status |
| 2756 | cmp %r14, %r17 |
| 2757 | bne,a %xcc, wait_for_ibp_80_37 |
| 2758 | ldxa [0x50]%asi, %r14 !Running_rw |
| 2759 | ibp_doit80_37: |
| 2760 | best_set_reg(0x000000503ec000be,%r19, %r20) |
| 2761 | stxa %r20, [%r18]0x42 |
| 2762 | stxa %r16, [0x60] %asi !Unpark (W1S) |
| 2763 | st %g0, [%r23] !clear lock |
| 2764 | wr %r0, %r12, %asi !restore %asi |
| 2765 | ta T_CHANGE_NONHPRIV |
| 2766 | .word 0xa5a289b0 ! 56: FDIVs fdivs %f10, %f16, %f18 |
| 2767 | brcommon3_80_38: |
| 2768 | nop |
| 2769 | setx common_target, %r12, %r27 |
| 2770 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 2771 | ba,a .+12 |
| 2772 | .word 0xe937e140 ! 1: STQF_I - %f20, [0x0140, %r31] |
| 2773 | ba,a .+8 |
| 2774 | jmpl %r27+0, %r27 |
| 2775 | .word 0xe8bfc028 ! 57: STDA_R stda %r20, [%r31 + %r8] 0x01 |
| 2776 | ibp_80_39: |
| 2777 | nop |
| 2778 | ta T_CHANGE_HPRIV |
| 2779 | mov 8, %r18 |
| 2780 | rd %asi, %r12 |
| 2781 | wr %r0, 0x41, %asi |
| 2782 | set sync_thr_counter4, %r23 |
| 2783 | #ifndef SPC |
| 2784 | ldxa [%g0]0x63, %r8 |
| 2785 | and %r8, 0x38, %r8 ! Core ID |
| 2786 | add %r8, %r23, %r23 |
| 2787 | #else |
| 2788 | mov 0, %r8 |
| 2789 | #endif |
| 2790 | mov 0x80, %r16 |
| 2791 | ibp_startwait80_39: |
| 2792 | cas [%r23],%g0,%r16 !lock |
| 2793 | brz,a %r16, continue_ibp_80_39 |
| 2794 | mov (~0x80&0xf0), %r16 |
| 2795 | ld [%r23], %r16 |
| 2796 | ibp_wait80_39: |
| 2797 | brnz %r16, ibp_wait80_39 |
| 2798 | ld [%r23], %r16 |
| 2799 | ba ibp_startwait80_39 |
| 2800 | mov 0x80, %r16 |
| 2801 | continue_ibp_80_39: |
| 2802 | sllx %r16, %r8, %r16 !Mask for my core only |
| 2803 | ldxa [0x58]%asi, %r17 !Running_status |
| 2804 | wait_for_stat_80_39: |
| 2805 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2806 | cmp %r13, %r17 |
| 2807 | bne,a %xcc, wait_for_stat_80_39 |
| 2808 | ldxa [0x58]%asi, %r17 !Running_status |
| 2809 | stxa %r16, [0x68]%asi !Park (W1C) |
| 2810 | ldxa [0x50]%asi, %r14 !Running_rw |
| 2811 | wait_for_ibp_80_39: |
| 2812 | ldxa [0x58]%asi, %r17 !Running_status |
| 2813 | cmp %r14, %r17 |
| 2814 | bne,a %xcc, wait_for_ibp_80_39 |
| 2815 | ldxa [0x50]%asi, %r14 !Running_rw |
| 2816 | ibp_doit80_39: |
| 2817 | best_set_reg(0x00000040fcc0be4b,%r19, %r20) |
| 2818 | stxa %r20, [%r18]0x42 |
| 2819 | stxa %r16, [0x60] %asi !Unpark (W1S) |
| 2820 | st %g0, [%r23] !clear lock |
| 2821 | wr %r0, %r12, %asi !restore %asi |
| 2822 | ta T_CHANGE_NONHPRIV |
| 2823 | .word 0x87acca51 ! 58: FCMPd fcmpd %fcc<n>, %f50, %f48 |
| 2824 | nop |
| 2825 | ta T_CHANGE_HPRIV ! macro |
| 2826 | donret_80_40: |
| 2827 | rd %pc, %r12 |
| 2828 | mov HIGHVA_HIGHNUM, %r10 |
| 2829 | sllx %r10, 32, %r10 |
| 2830 | or %r12, %r10, %r12 |
| 2831 | add %r12, (donretarg_80_40-donret_80_40+4), %r12 |
| 2832 | add %r12, 0x4, %r11 ! seq tnpc |
| 2833 | andn %r12, %r10, %r12 ! low VA tpc |
| 2834 | wrpr %g0, 0x1, %tl |
| 2835 | wrpr %g0, %r12, %tpc |
| 2836 | wrpr %g0, %r11, %tnpc |
| 2837 | set (0x00707900 | (0x8b << 24)), %r13 |
| 2838 | and %r12, 0xfff, %r14 |
| 2839 | sllx %r14, 32, %r14 |
| 2840 | or %r13, %r14, %r20 |
| 2841 | wrpr %r20, %g0, %tstate |
| 2842 | wrhpr %g0, 0x1c17, %htstate |
| 2843 | ta T_CHANGE_NONPRIV ! rand=0 (80) |
| 2844 | ldx [%r12+%r0], %g1 |
| 2845 | retry |
| 2846 | donretarg_80_40: |
| 2847 | .word 0x2f400001 ! 59: FBPU fbu,a,pn %fcc0, <label_0x1> |
| 2848 | memptr_80_41: |
| 2849 | set 0x60740000, %r31 |
| 2850 | .word 0x8580aa21 ! 60: WRCCR_I wr %r2, 0x0a21, %ccr |
| 2851 | nop |
| 2852 | mov 0x80, %g3 |
| 2853 | stxa %r8, [%r0] ASI_LSU_CONTROL |
| 2854 | stxa %g3, [%g3] 0x5f |
| 2855 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 2856 | .word 0x9953c000 ! 62: RDPR_FQ <illegal instruction> |
| 2857 | fbul,a,pn %fcc0, skip_80_42 |
| 2858 | .word 0xa3b4c4d2 ! 1: FCMPNE32 fcmpne32 %d50, %d18, %r17 |
| 2859 | .align 1024 |
| 2860 | skip_80_42: |
| 2861 | .word 0x95a409d0 ! 63: FDIVd fdivd %f16, %f16, %f10 |
| 2862 | brgz,a,pn %r9, skip_80_43 |
| 2863 | stxa %r7, [%r0] ASI_LSU_CONTROL |
| 2864 | fbn skip_80_43 |
| 2865 | stxa %r13, [%r0] ASI_LSU_CONTROL |
| 2866 | .align 1024 |
| 2867 | skip_80_43: |
| 2868 | .word 0xc30fc000 ! 64: LDXFSR_R ld-fsr [%r31, %r0], %f1 |
| 2869 | .word 0xe19fdf20 ! 65: LDDFA_R ldda [%r31, %r0], %f16 |
| 2870 | nop |
| 2871 | ta T_CHANGE_HPRIV |
| 2872 | mov 0x80+1, %r10 |
| 2873 | set sync_thr_counter5, %r23 |
| 2874 | #ifndef SPC |
| 2875 | ldxa [%g0]0x63, %o1 |
| 2876 | and %o1, 0x38, %o1 |
| 2877 | add %o1, %r23, %r23 |
| 2878 | sllx %o1, 5, %o3 !(CID*256) |
| 2879 | #endif |
| 2880 | cas [%r23],%g0,%r10 !lock |
| 2881 | brnz %r10, cwq_80_44 |
| 2882 | rd %asi, %r12 |
| 2883 | wr %g0, 0x40, %asi |
| 2884 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 2885 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 2886 | cmp %l1, 1 |
| 2887 | bne cwq_80_44 |
| 2888 | set CWQ_BASE, %l6 |
| 2889 | #ifndef SPC |
| 2890 | add %l6, %o3, %l6 |
| 2891 | #endif |
| 2892 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 2893 | best_set_reg(0x206100d0, %l1, %l2) !# Control Word |
| 2894 | sllx %l2, 32, %l2 |
| 2895 | stx %l2, [%l6 + 0x0] |
| 2896 | membar #Sync |
| 2897 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 2898 | sub %l2, 0x40, %l2 |
| 2899 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 2900 | wr %r12, %g0, %asi |
| 2901 | st %g0, [%r23] |
| 2902 | cwq_80_44: |
| 2903 | ta T_CHANGE_NONHPRIV |
| 2904 | .word 0xa7414000 ! 66: RDPC rd %pc, %r19 |
| 2905 | mondo_80_45: |
| 2906 | nop |
| 2907 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 2908 | ta T_CHANGE_PRIV |
| 2909 | stxa %r20, [%r0+0x3e8] %asi |
| 2910 | .word 0x9d944006 ! 67: WRPR_WSTATE_R wrpr %r17, %r6, %wstate |
| 2911 | cmp_80_46: |
| 2912 | nop |
| 2913 | ta T_CHANGE_HPRIV |
| 2914 | rd %asi, %r12 |
| 2915 | wr %r0, 0x41, %asi |
| 2916 | set sync_thr_counter4, %r23 |
| 2917 | #ifndef SPC |
| 2918 | ldxa [%g0]0x63, %r8 |
| 2919 | and %r8, 0x38, %r8 ! Core ID |
| 2920 | add %r8, %r23, %r23 |
| 2921 | mov 0xff, %r9 |
| 2922 | xor %r9, 0x80, %r9 |
| 2923 | sllx %r9, %r8, %r9 ! My core mask |
| 2924 | #else |
| 2925 | mov 0, %r8 |
| 2926 | mov 0xff, %r9 |
| 2927 | xor %r9, 0x80, %r9 ! My core mask |
| 2928 | #endif |
| 2929 | mov 0x80, %r10 |
| 2930 | cmp_startwait80_46: |
| 2931 | cas [%r23],%g0,%r10 !lock |
| 2932 | brz,a %r10, continue_cmp_80_46 |
| 2933 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2934 | ld [%r23], %r10 |
| 2935 | cmp_wait80_46: |
| 2936 | brnz,a %r10, cmp_wait80_46 |
| 2937 | ld [%r23], %r10 |
| 2938 | ba cmp_startwait80_46 |
| 2939 | mov 0x80, %r10 |
| 2940 | continue_cmp_80_46: |
| 2941 | ldxa [0x58]%asi, %r14 !Running_status |
| 2942 | xnor %r14, %r13, %r14 !Bits equal |
| 2943 | brz,a %r8, cmp_multi_core_80_46 |
| 2944 | mov 25, %r17 |
| 2945 | best_set_reg(0x75a5606940c0cb66, %r16, %r17) |
| 2946 | cmp_multi_core_80_46: |
| 2947 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 2948 | and %r14, %r9, %r14 !Apply core-mask |
| 2949 | stxa %r14, [0x60]%asi |
| 2950 | st %g0, [%r23] !clear lock |
| 2951 | wr %g0, %r12, %asi |
| 2952 | ta T_CHANGE_NONHPRIV |
| 2953 | .word 0x91a00165 ! 68: FABSq dis not found |
| 2954 | |
| 2955 | cmp_80_47: |
| 2956 | nop |
| 2957 | ta T_CHANGE_HPRIV |
| 2958 | rd %asi, %r12 |
| 2959 | wr %r0, 0x41, %asi |
| 2960 | set sync_thr_counter4, %r23 |
| 2961 | #ifndef SPC |
| 2962 | ldxa [%g0]0x63, %r8 |
| 2963 | and %r8, 0x38, %r8 ! Core ID |
| 2964 | add %r8, %r23, %r23 |
| 2965 | mov 0xff, %r9 |
| 2966 | xor %r9, 0x80, %r9 |
| 2967 | sllx %r9, %r8, %r9 ! My core mask |
| 2968 | #else |
| 2969 | mov 0, %r8 |
| 2970 | mov 0xff, %r9 |
| 2971 | xor %r9, 0x80, %r9 ! My core mask |
| 2972 | #endif |
| 2973 | mov 0x80, %r10 |
| 2974 | cmp_startwait80_47: |
| 2975 | cas [%r23],%g0,%r10 !lock |
| 2976 | brz,a %r10, continue_cmp_80_47 |
| 2977 | ldxa [0x50]%asi, %r13 !Running_rw |
| 2978 | ld [%r23], %r10 |
| 2979 | cmp_wait80_47: |
| 2980 | brnz,a %r10, cmp_wait80_47 |
| 2981 | ld [%r23], %r10 |
| 2982 | ba cmp_startwait80_47 |
| 2983 | mov 0x80, %r10 |
| 2984 | continue_cmp_80_47: |
| 2985 | ldxa [0x58]%asi, %r14 !Running_status |
| 2986 | xnor %r14, %r13, %r14 !Bits equal |
| 2987 | brz,a %r8, cmp_multi_core_80_47 |
| 2988 | mov 0xc2, %r17 |
| 2989 | best_set_reg(0x37befdf8ec0eddf0, %r16, %r17) |
| 2990 | cmp_multi_core_80_47: |
| 2991 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 2992 | and %r14, %r9, %r14 !Apply core-mask |
| 2993 | stxa %r14, [0x68]%asi |
| 2994 | st %g0, [%r23] !clear lock |
| 2995 | wr %g0, %r12, %asi |
| 2996 | ta T_CHANGE_NONHPRIV |
| 2997 | .word 0x91928012 ! 69: WRPR_PIL_R wrpr %r10, %r18, %pil |
| 2998 | splash_tick_80_48: |
| 2999 | nop |
| 3000 | ta T_CHANGE_HPRIV |
| 3001 | best_set_reg(0x6dd9ef5706b99a05, %r16, %r17) |
| 3002 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 3003 | #if (defined SPC || defined CMP) |
| 3004 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_80_49)+16, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3005 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_80_49)&0xffffffff) + 56, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3006 | xir_80_49: |
| 3007 | #else |
| 3008 | #if (defined FC) |
| 3009 | !! Generate XIR via RESET_GEN register |
| 3010 | ta T_CHANGE_HPRIV |
| 3011 | rdpr %pstate, %r18 |
| 3012 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 3013 | wrpr %r18, %pstate |
| 3014 | #ifndef XIR_RND_CORES |
| 3015 | ldxa [%g0] 0x63, %o1 |
| 3016 | mov 1, %r18 |
| 3017 | sllx %r18, %o1, %r18 |
| 3018 | #endif |
| 3019 | mov 0x30, %r19 |
| 3020 | setx 0x8900000808, %r16, %r17 |
| 3021 | mov 0x2, %r16 |
| 3022 | xir_80_49: |
| 3023 | stxa %r18, [%r19] 0x41 |
| 3024 | stx %r16, [%r17] |
| 3025 | #endif |
| 3026 | #endif |
| 3027 | .word 0xa98422ad ! 71: WR_SET_SOFTINT_I wr %r16, 0x02ad, %set_softint |
| 3028 | #if (defined SPC || defined CMP1) |
| 3029 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_50) + 56, 16, 16)) -> intp(5,0,20,,,,,1) |
| 3030 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_50)&0xffffffff) + 40, 16, 16)) -> intp(6,0,26,,,,,1) |
| 3031 | #else |
| 3032 | set 0x30c01840, %r28 |
| 3033 | #if (MAX_THREADS == 8) |
| 3034 | and %r28, 0x7ff, %r28 |
| 3035 | #endif |
| 3036 | stxa %r28, [%g0] 0x73 |
| 3037 | #endif |
| 3038 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 3039 | intvec_80_50: |
| 3040 | .word 0xc369f0eb ! 72: PREFETCH_I prefetch [%r7 + 0xfffff0eb], #one_read |
| 3041 | invtsb_80_51: |
| 3042 | nop |
| 3043 | ta T_CHANGE_HPRIV |
| 3044 | rd %asi, %r21 |
| 3045 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 3046 | mov 1, %r20 |
| 3047 | sllx %r20, 63, %r20 |
| 3048 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 3049 | xor %r22 ,%r20, %r22 |
| 3050 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 3051 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 3052 | xor %r22 ,%r20, %r22 |
| 3053 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 3054 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 3055 | xor %r22 ,%r20, %r22 |
| 3056 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 3057 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 3058 | xor %r22 ,%r20, %r22 |
| 3059 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 3060 | wr %r21, %r0, %asi |
| 3061 | ta T_CHANGE_NONHPRIV |
| 3062 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 3063 | nop |
| 3064 | mov 0x80, %g3 |
| 3065 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 3066 | stxa %g3, [%g3] 0x57 |
| 3067 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 3068 | nop |
| 3069 | ta T_CHANGE_HPRIV |
| 3070 | mov 0x80, %r10 |
| 3071 | set sync_thr_counter6, %r23 |
| 3072 | #ifndef SPC |
| 3073 | ldxa [%g0]0x63, %o1 |
| 3074 | and %o1, 0x38, %o1 |
| 3075 | add %o1, %r23, %r23 |
| 3076 | #endif |
| 3077 | cas [%r23],%g0,%r10 !lock |
| 3078 | brnz %r10, sma_80_52 |
| 3079 | rd %asi, %r12 |
| 3080 | wr %g0, 0x40, %asi |
| 3081 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 3082 | set 0x001e1fff, %g1 |
| 3083 | stxa %g1, [%g0 + 0x80] %asi |
| 3084 | wr %r12, %g0, %asi |
| 3085 | st %g0, [%r23] |
| 3086 | sma_80_52: |
| 3087 | ta T_CHANGE_NONHPRIV |
| 3088 | .word 0xe5e7e014 ! 75: CASA_R casa [%r31] %asi, %r20, %r18 |
| 3089 | cmp_80_53: |
| 3090 | nop |
| 3091 | ta T_CHANGE_HPRIV |
| 3092 | rd %asi, %r12 |
| 3093 | wr %r0, 0x41, %asi |
| 3094 | set sync_thr_counter4, %r23 |
| 3095 | #ifndef SPC |
| 3096 | ldxa [%g0]0x63, %r8 |
| 3097 | and %r8, 0x38, %r8 ! Core ID |
| 3098 | add %r8, %r23, %r23 |
| 3099 | mov 0xff, %r9 |
| 3100 | xor %r9, 0x80, %r9 |
| 3101 | sllx %r9, %r8, %r9 ! My core mask |
| 3102 | #else |
| 3103 | mov 0, %r8 |
| 3104 | mov 0xff, %r9 |
| 3105 | xor %r9, 0x80, %r9 ! My core mask |
| 3106 | #endif |
| 3107 | mov 0x80, %r10 |
| 3108 | cmp_startwait80_53: |
| 3109 | cas [%r23],%g0,%r10 !lock |
| 3110 | brz,a %r10, continue_cmp_80_53 |
| 3111 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3112 | ld [%r23], %r10 |
| 3113 | cmp_wait80_53: |
| 3114 | brnz,a %r10, cmp_wait80_53 |
| 3115 | ld [%r23], %r10 |
| 3116 | ba cmp_startwait80_53 |
| 3117 | mov 0x80, %r10 |
| 3118 | continue_cmp_80_53: |
| 3119 | ldxa [0x58]%asi, %r14 !Running_status |
| 3120 | xnor %r14, %r13, %r14 !Bits equal |
| 3121 | brz,a %r8, cmp_multi_core_80_53 |
| 3122 | mov 0xb9, %r17 |
| 3123 | best_set_reg(0xba9296c1bd158538, %r16, %r17) |
| 3124 | cmp_multi_core_80_53: |
| 3125 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 3126 | and %r14, %r9, %r14 !Apply core-mask |
| 3127 | stxa %r14, [0x68]%asi |
| 3128 | st %g0, [%r23] !clear lock |
| 3129 | wr %g0, %r12, %asi |
| 3130 | .word 0x9194c011 ! 76: WRPR_PIL_R wrpr %r19, %r17, %pil |
| 3131 | pmu_80_54: |
| 3132 | nop |
| 3133 | setx 0xffffffbaffffffa3, %g1, %g7 |
| 3134 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 3135 | fpinit_80_55: |
| 3136 | nop |
| 3137 | setx fp_data_quads, %r19, %r20 |
| 3138 | ldd [%r20], %f0 |
| 3139 | ldd [%r20+8], %f4 |
| 3140 | ld [%r20+16], %fsr |
| 3141 | ld [%r20+24], %r19 |
| 3142 | wr %r19, %g0, %gsr |
| 3143 | .word 0xc3e82b59 ! 78: PREFETCHA_I prefetcha [%r0, + 0x0b59] %asi, #one_read |
| 3144 | jmptr_80_56: |
| 3145 | nop |
| 3146 | best_set_reg(0xe0a00000, %r20, %r27) |
| 3147 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 3148 | nop |
| 3149 | mov 0x80, %g3 |
| 3150 | stxa %r8, [%r0] ASI_LSU_CONTROL |
| 3151 | stxa %g3, [%g3] 0x5f |
| 3152 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 3153 | ticken_80_57: |
| 3154 | nop |
| 3155 | ta T_CHANGE_HPRIV |
| 3156 | rd %asi, %r12 |
| 3157 | wr %r0, 0x41, %asi |
| 3158 | stxa %g0, [0x38]%asi |
| 3159 | best_set_reg(0xd86624f368b787f7, %r16, %r17) |
| 3160 | wrpr %g0, %r17, %tick |
| 3161 | mov 1, %r16 |
| 3162 | stxa %r16, [0x38]%asi |
| 3163 | wr %g0, %r12, %asi |
| 3164 | .word 0x91b100e9 ! 81: EDGE16LN edge16ln %r4, %r9, %r8 |
| 3165 | #if (defined SPC || defined CMP1) |
| 3166 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_58) + 16, 16, 16)) -> intp(6,0,11,,,,,1) |
| 3167 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_58)&0xffffffff) + 40, 16, 16)) -> intp(5,0,22,,,,,1) |
| 3168 | #else |
| 3169 | set 0x4a20cab5, %r28 |
| 3170 | #if (MAX_THREADS == 8) |
| 3171 | and %r28, 0x7ff, %r28 |
| 3172 | #endif |
| 3173 | stxa %r28, [%g0] 0x73 |
| 3174 | #endif |
| 3175 | .word 0xa3b084d1 ! 1: FCMPNE32 fcmpne32 %d2, %d48, %r17 |
| 3176 | intvec_80_58: |
| 3177 | .word 0x91b404ca ! 82: FCMPNE32 fcmpne32 %d16, %d10, %r8 |
| 3178 | nop |
| 3179 | ta T_CHANGE_HPRIV |
| 3180 | mov 0x80, %r10 |
| 3181 | set sync_thr_counter6, %r23 |
| 3182 | #ifndef SPC |
| 3183 | ldxa [%g0]0x63, %o1 |
| 3184 | and %o1, 0x38, %o1 |
| 3185 | add %o1, %r23, %r23 |
| 3186 | #endif |
| 3187 | cas [%r23],%g0,%r10 !lock |
| 3188 | brnz %r10, sma_80_59 |
| 3189 | rd %asi, %r12 |
| 3190 | wr %g0, 0x40, %asi |
| 3191 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 3192 | set 0x00061fff, %g1 |
| 3193 | stxa %g1, [%g0 + 0x80] %asi |
| 3194 | wr %r12, %g0, %asi |
| 3195 | st %g0, [%r23] |
| 3196 | sma_80_59: |
| 3197 | ta T_CHANGE_NONHPRIV |
| 3198 | .word 0xe5e7e00c ! 83: CASA_R casa [%r31] %asi, %r12, %r18 |
| 3199 | fpinit_80_60: |
| 3200 | nop |
| 3201 | setx fp_data_quads, %r19, %r20 |
| 3202 | ldd [%r20], %f0 |
| 3203 | ldd [%r20+8], %f4 |
| 3204 | ld [%r20+16], %fsr |
| 3205 | ld [%r20+24], %r19 |
| 3206 | wr %r19, %g0, %gsr |
| 3207 | .word 0x87a80a44 ! 84: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 3208 | .word 0x87802020 ! 85: WRASI_I wr %r0, 0x0020, %asi |
| 3209 | .word 0xc19fdf20 ! 86: LDDFA_R ldda [%r31, %r0], %f0 |
| 3210 | splash_lsu_80_61: |
| 3211 | nop |
| 3212 | ta T_CHANGE_HPRIV |
| 3213 | set 0xe2fcc268, %r2 |
| 3214 | mov 0x3, %r1 |
| 3215 | sllx %r1, 32, %r1 |
| 3216 | or %r1, %r2, %r2 |
| 3217 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3218 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3219 | splash_lsu_80_62: |
| 3220 | nop |
| 3221 | ta T_CHANGE_HPRIV |
| 3222 | set 0x7c8f01ab, %r2 |
| 3223 | mov 0x3, %r1 |
| 3224 | sllx %r1, 32, %r1 |
| 3225 | or %r1, %r2, %r2 |
| 3226 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3227 | ta T_CHANGE_NONHPRIV |
| 3228 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3229 | splash_cmpr_80_63: |
| 3230 | mov 0, %r18 |
| 3231 | sllx %r18, 63, %r18 |
| 3232 | rd %tick, %r17 |
| 3233 | add %r17, 0x60, %r17 |
| 3234 | or %r17, %r18, %r17 |
| 3235 | ta T_CHANGE_HPRIV |
| 3236 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 3237 | .word 0xb3800011 ! 89: WR_STICK_CMPR_REG_R wr %r0, %r17, %- |
| 3238 | nop |
| 3239 | mov 0x80, %g3 |
| 3240 | .word 0x22800001 ! 1: BE be,a <label_0x1> |
| 3241 | stxa %g3, [%g3] 0x5f |
| 3242 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 3243 | splash_tba_80_64: |
| 3244 | nop |
| 3245 | ta T_CHANGE_PRIV |
| 3246 | set 0x120000, %r12 |
| 3247 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 3248 | dvapa_80_65: |
| 3249 | nop |
| 3250 | ta T_CHANGE_HPRIV |
| 3251 | mov 0xb8d, %r20 |
| 3252 | mov 0x11, %r19 |
| 3253 | sllx %r20, 23, %r20 |
| 3254 | or %r19, %r20, %r19 |
| 3255 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 3256 | mov 0x38, %r18 |
| 3257 | stxa %r31, [%r18]0x58 |
| 3258 | ta T_CHANGE_NONHPRIV |
| 3259 | .word 0xe4dfc02c ! 92: LDXA_R ldxa [%r31, %r12] 0x01, %r18 |
| 3260 | splash_lsu_80_66: |
| 3261 | nop |
| 3262 | ta T_CHANGE_HPRIV |
| 3263 | set 0x33526812, %r2 |
| 3264 | mov 0x5, %r1 |
| 3265 | sllx %r1, 32, %r1 |
| 3266 | or %r1, %r2, %r2 |
| 3267 | .word 0x20800001 ! 1: BN bn,a <label_0x1> |
| 3268 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3269 | ta T_CHANGE_NONHPRIV |
| 3270 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3271 | ibp_80_67: |
| 3272 | nop |
| 3273 | ta T_CHANGE_HPRIV |
| 3274 | mov 8, %r18 |
| 3275 | rd %asi, %r12 |
| 3276 | wr %r0, 0x41, %asi |
| 3277 | set sync_thr_counter4, %r23 |
| 3278 | #ifndef SPC |
| 3279 | ldxa [%g0]0x63, %r8 |
| 3280 | and %r8, 0x38, %r8 ! Core ID |
| 3281 | add %r8, %r23, %r23 |
| 3282 | #else |
| 3283 | mov 0, %r8 |
| 3284 | #endif |
| 3285 | mov 0x80, %r16 |
| 3286 | ibp_startwait80_67: |
| 3287 | cas [%r23],%g0,%r16 !lock |
| 3288 | brz,a %r16, continue_ibp_80_67 |
| 3289 | mov (~0x80&0xf0), %r16 |
| 3290 | ld [%r23], %r16 |
| 3291 | ibp_wait80_67: |
| 3292 | brnz %r16, ibp_wait80_67 |
| 3293 | ld [%r23], %r16 |
| 3294 | ba ibp_startwait80_67 |
| 3295 | mov 0x80, %r16 |
| 3296 | continue_ibp_80_67: |
| 3297 | sllx %r16, %r8, %r16 !Mask for my core only |
| 3298 | ldxa [0x58]%asi, %r17 !Running_status |
| 3299 | wait_for_stat_80_67: |
| 3300 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3301 | cmp %r13, %r17 |
| 3302 | bne,a %xcc, wait_for_stat_80_67 |
| 3303 | ldxa [0x58]%asi, %r17 !Running_status |
| 3304 | stxa %r16, [0x68]%asi !Park (W1C) |
| 3305 | ldxa [0x50]%asi, %r14 !Running_rw |
| 3306 | wait_for_ibp_80_67: |
| 3307 | ldxa [0x58]%asi, %r17 !Running_status |
| 3308 | cmp %r14, %r17 |
| 3309 | bne,a %xcc, wait_for_ibp_80_67 |
| 3310 | ldxa [0x50]%asi, %r14 !Running_rw |
| 3311 | ibp_doit80_67: |
| 3312 | best_set_reg(0x00000040b9fe4b94,%r19, %r20) |
| 3313 | stxa %r20, [%r18]0x42 |
| 3314 | stxa %r16, [0x60] %asi !Unpark (W1S) |
| 3315 | st %g0, [%r23] !clear lock |
| 3316 | wr %r0, %r12, %asi !restore %asi |
| 3317 | .word 0xe497c029 ! 94: LDUHA_R lduha [%r31, %r9] 0x01, %r18 |
| 3318 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 3319 | nop |
| 3320 | ta T_CHANGE_HPRIV |
| 3321 | mov 0x80, %r10 |
| 3322 | set sync_thr_counter6, %r23 |
| 3323 | #ifndef SPC |
| 3324 | ldxa [%g0]0x63, %o1 |
| 3325 | and %o1, 0x38, %o1 |
| 3326 | add %o1, %r23, %r23 |
| 3327 | #endif |
| 3328 | cas [%r23],%g0,%r10 !lock |
| 3329 | brnz %r10, sma_80_68 |
| 3330 | rd %asi, %r12 |
| 3331 | wr %g0, 0x40, %asi |
| 3332 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 3333 | set 0x00121fff, %g1 |
| 3334 | stxa %g1, [%g0 + 0x80] %asi |
| 3335 | wr %r12, %g0, %asi |
| 3336 | st %g0, [%r23] |
| 3337 | sma_80_68: |
| 3338 | ta T_CHANGE_NONHPRIV |
| 3339 | .word 0xe5e7e010 ! 96: CASA_R casa [%r31] %asi, %r16, %r18 |
| 3340 | #if (defined SPC || defined CMP) |
| 3341 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_80_69)+24, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3342 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_80_69)&0xffffffff) + 16, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3343 | xir_80_69: |
| 3344 | #else |
| 3345 | #if (defined FC) |
| 3346 | !! Generate XIR via RESET_GEN register |
| 3347 | ta T_CHANGE_HPRIV |
| 3348 | rdpr %pstate, %r18 |
| 3349 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 3350 | wrpr %r18, %pstate |
| 3351 | #ifndef XIR_RND_CORES |
| 3352 | ldxa [%g0] 0x63, %o1 |
| 3353 | mov 1, %r18 |
| 3354 | sllx %r18, %o1, %r18 |
| 3355 | #endif |
| 3356 | mov 0x30, %r19 |
| 3357 | setx 0x8900000808, %r16, %r17 |
| 3358 | mov 0x2, %r16 |
| 3359 | xir_80_69: |
| 3360 | stxa %r18, [%r19] 0x41 |
| 3361 | stx %r16, [%r17] |
| 3362 | #endif |
| 3363 | #endif |
| 3364 | .word 0xa9816b74 ! 97: WR_SET_SOFTINT_I wr %r5, 0x0b74, %set_softint |
| 3365 | #if (defined SPC || defined CMP1) |
| 3366 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_70) + 40, 16, 16)) -> intp(1,0,22,,,,,1) |
| 3367 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_80_70)&0xffffffff) + 8, 16, 16)) -> intp(6,0,22,,,,,1) |
| 3368 | #else |
| 3369 | set 0xafd01f39, %r28 |
| 3370 | #if (MAX_THREADS == 8) |
| 3371 | and %r28, 0x7ff, %r28 |
| 3372 | #endif |
| 3373 | stxa %r28, [%g0] 0x73 |
| 3374 | #endif |
| 3375 | intvec_80_70: |
| 3376 | .word 0x95a249d4 ! 98: FDIVd fdivd %f40, %f20, %f10 |
| 3377 | fpinit_80_71: |
| 3378 | nop |
| 3379 | setx fp_data_quads, %r19, %r20 |
| 3380 | ldd [%r20], %f0 |
| 3381 | ldd [%r20+8], %f4 |
| 3382 | ld [%r20+16], %fsr |
| 3383 | ld [%r20+24], %r19 |
| 3384 | wr %r19, %g0, %gsr |
| 3385 | .word 0xc3e8228f ! 99: PREFETCHA_I prefetcha [%r0, + 0x028f] %asi, #one_read |
| 3386 | splash_lsu_80_72: |
| 3387 | nop |
| 3388 | ta T_CHANGE_HPRIV |
| 3389 | set 0x56cd396b, %r2 |
| 3390 | mov 0x5, %r1 |
| 3391 | sllx %r1, 32, %r1 |
| 3392 | or %r1, %r2, %r2 |
| 3393 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3394 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3395 | ticken_80_73: |
| 3396 | nop |
| 3397 | ta T_CHANGE_HPRIV |
| 3398 | rd %asi, %r12 |
| 3399 | wr %r0, 0x41, %asi |
| 3400 | stxa %g0, [0x38]%asi |
| 3401 | best_set_reg(0x53672f119fbbaea9, %r16, %r17) |
| 3402 | wrpr %g0, %r17, %tick |
| 3403 | mov 1, %r16 |
| 3404 | stxa %r16, [0x38]%asi |
| 3405 | wr %g0, %r12, %asi |
| 3406 | .word 0xa5b480f4 ! 101: EDGE16LN edge16ln %r18, %r20, %r18 |
| 3407 | nop |
| 3408 | ta T_CHANGE_HPRIV |
| 3409 | mov 0x80, %r10 |
| 3410 | set sync_thr_counter6, %r23 |
| 3411 | #ifndef SPC |
| 3412 | ldxa [%g0]0x63, %o1 |
| 3413 | and %o1, 0x38, %o1 |
| 3414 | add %o1, %r23, %r23 |
| 3415 | #endif |
| 3416 | cas [%r23],%g0,%r10 !lock |
| 3417 | brnz %r10, sma_80_74 |
| 3418 | rd %asi, %r12 |
| 3419 | wr %g0, 0x40, %asi |
| 3420 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 3421 | set 0x00061fff, %g1 |
| 3422 | stxa %g1, [%g0 + 0x80] %asi |
| 3423 | wr %r12, %g0, %asi |
| 3424 | st %g0, [%r23] |
| 3425 | sma_80_74: |
| 3426 | ta T_CHANGE_NONHPRIV |
| 3427 | .word 0xd7e7e00a ! 102: CASA_R casa [%r31] %asi, %r10, %r11 |
| 3428 | nop |
| 3429 | mov 0x80, %g3 |
| 3430 | .word 0x3a800001 ! 1: BCC bcc,a <label_0x1> |
| 3431 | stxa %g3, [%g3] 0x5f |
| 3432 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 3433 | invtsb_80_75: |
| 3434 | nop |
| 3435 | ta T_CHANGE_HPRIV |
| 3436 | rd %asi, %r21 |
| 3437 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 3438 | mov 1, %r20 |
| 3439 | sllx %r20, 63, %r20 |
| 3440 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 3441 | xor %r22 ,%r20, %r22 |
| 3442 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 3443 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 3444 | xor %r22 ,%r20, %r22 |
| 3445 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 3446 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 3447 | xor %r22 ,%r20, %r22 |
| 3448 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 3449 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 3450 | xor %r22 ,%r20, %r22 |
| 3451 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 3452 | wr %r21, %r0, %asi |
| 3453 | ta T_CHANGE_NONHPRIV |
| 3454 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 3455 | .word 0xe19fdc00 ! 105: LDDFA_R ldda [%r31, %r0], %f16 |
| 3456 | splash_lsu_80_77: |
| 3457 | nop |
| 3458 | ta T_CHANGE_HPRIV |
| 3459 | set 0xece8419f, %r2 |
| 3460 | mov 0x2, %r1 |
| 3461 | sllx %r1, 32, %r1 |
| 3462 | or %r1, %r2, %r2 |
| 3463 | .word 0x22cb0001 ! 1: BRZ brz,a,pt %r12,<label_0xb0001> |
| 3464 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3465 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3466 | .word 0xe1bfdf20 ! 107: STDFA_R stda %f16, [%r0, %r31] |
| 3467 | cmp_80_78: |
| 3468 | nop |
| 3469 | ta T_CHANGE_HPRIV |
| 3470 | rd %asi, %r12 |
| 3471 | wr %r0, 0x41, %asi |
| 3472 | set sync_thr_counter4, %r23 |
| 3473 | #ifndef SPC |
| 3474 | ldxa [%g0]0x63, %r8 |
| 3475 | and %r8, 0x38, %r8 ! Core ID |
| 3476 | add %r8, %r23, %r23 |
| 3477 | mov 0xff, %r9 |
| 3478 | xor %r9, 0x80, %r9 |
| 3479 | sllx %r9, %r8, %r9 ! My core mask |
| 3480 | #else |
| 3481 | mov 0, %r8 |
| 3482 | mov 0xff, %r9 |
| 3483 | xor %r9, 0x80, %r9 ! My core mask |
| 3484 | #endif |
| 3485 | mov 0x80, %r10 |
| 3486 | cmp_startwait80_78: |
| 3487 | cas [%r23],%g0,%r10 !lock |
| 3488 | brz,a %r10, continue_cmp_80_78 |
| 3489 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3490 | ld [%r23], %r10 |
| 3491 | cmp_wait80_78: |
| 3492 | brnz,a %r10, cmp_wait80_78 |
| 3493 | ld [%r23], %r10 |
| 3494 | ba cmp_startwait80_78 |
| 3495 | mov 0x80, %r10 |
| 3496 | continue_cmp_80_78: |
| 3497 | ldxa [0x58]%asi, %r14 !Running_status |
| 3498 | xnor %r14, %r13, %r14 !Bits equal |
| 3499 | brz,a %r8, cmp_multi_core_80_78 |
| 3500 | mov 59, %r17 |
| 3501 | best_set_reg(0x84ec48351a966b79, %r16, %r17) |
| 3502 | cmp_multi_core_80_78: |
| 3503 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 3504 | and %r14, %r9, %r14 !Apply core-mask |
| 3505 | stxa %r14, [0x60]%asi |
| 3506 | st %g0, [%r23] !clear lock |
| 3507 | wr %g0, %r12, %asi |
| 3508 | .word 0x91918010 ! 108: WRPR_PIL_R wrpr %r6, %r16, %pil |
| 3509 | splash_lsu_80_79: |
| 3510 | nop |
| 3511 | ta T_CHANGE_HPRIV |
| 3512 | set 0xb84ffc99, %r2 |
| 3513 | mov 0x4, %r1 |
| 3514 | sllx %r1, 32, %r1 |
| 3515 | or %r1, %r2, %r2 |
| 3516 | .word 0x2acc8001 ! 1: BRNZ brnz,a,pt %r18,<label_0xc8001> |
| 3517 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3518 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3519 | .word 0xc1bfd960 ! 110: STDFA_R stda %f0, [%r0, %r31] |
| 3520 | bvc skip_80_80 |
| 3521 | ba skip_80_80 |
| 3522 | .align 128 |
| 3523 | skip_80_80: |
| 3524 | .word 0x39400001 ! 111: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 3525 | .word 0xc1bfc3e0 ! 112: STDFA_R stda %f0, [%r0, %r31] |
| 3526 | rd %tick, %r28 |
| 3527 | #if (MAX_THREADS == 8) |
| 3528 | sethi %hi(0x33800), %r27 |
| 3529 | #else |
| 3530 | sethi %hi(0x30000), %r27 |
| 3531 | #endif |
| 3532 | andn %r28, %r27, %r28 |
| 3533 | ta T_CHANGE_HPRIV |
| 3534 | stxa %r28, [%g0] 0x73 |
| 3535 | intvec_80_81: |
| 3536 | .word 0x39400001 ! 113: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 3537 | .word 0xc1bfe060 ! 114: STDFA_I stda %f0, [0x0060, %r31] |
| 3538 | nop |
| 3539 | mov 0x80, %g3 |
| 3540 | .word 0x3d400001 ! 1: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3541 | stxa %g3, [%g3] 0x5f |
| 3542 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 3543 | jmptr_80_82: |
| 3544 | nop |
| 3545 | best_set_reg(0xe0a00000, %r20, %r27) |
| 3546 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 3547 | splash_tba_80_83: |
| 3548 | nop |
| 3549 | ta T_CHANGE_PRIV |
| 3550 | setx 0x00000000003a0000, %r11, %r12 |
| 3551 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 3552 | cmp_80_84: |
| 3553 | nop |
| 3554 | ta T_CHANGE_HPRIV |
| 3555 | rd %asi, %r12 |
| 3556 | wr %r0, 0x41, %asi |
| 3557 | set sync_thr_counter4, %r23 |
| 3558 | #ifndef SPC |
| 3559 | ldxa [%g0]0x63, %r8 |
| 3560 | and %r8, 0x38, %r8 ! Core ID |
| 3561 | add %r8, %r23, %r23 |
| 3562 | mov 0xff, %r9 |
| 3563 | xor %r9, 0x80, %r9 |
| 3564 | sllx %r9, %r8, %r9 ! My core mask |
| 3565 | #else |
| 3566 | mov 0, %r8 |
| 3567 | mov 0xff, %r9 |
| 3568 | xor %r9, 0x80, %r9 ! My core mask |
| 3569 | #endif |
| 3570 | mov 0x80, %r10 |
| 3571 | cmp_startwait80_84: |
| 3572 | cas [%r23],%g0,%r10 !lock |
| 3573 | brz,a %r10, continue_cmp_80_84 |
| 3574 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3575 | ld [%r23], %r10 |
| 3576 | cmp_wait80_84: |
| 3577 | brnz,a %r10, cmp_wait80_84 |
| 3578 | ld [%r23], %r10 |
| 3579 | ba cmp_startwait80_84 |
| 3580 | mov 0x80, %r10 |
| 3581 | continue_cmp_80_84: |
| 3582 | ldxa [0x58]%asi, %r14 !Running_status |
| 3583 | xnor %r14, %r13, %r14 !Bits equal |
| 3584 | brz,a %r8, cmp_multi_core_80_84 |
| 3585 | mov 0xe1, %r17 |
| 3586 | best_set_reg(0x4653c94ab63ca68f, %r16, %r17) |
| 3587 | cmp_multi_core_80_84: |
| 3588 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 3589 | and %r14, %r9, %r14 !Apply core-mask |
| 3590 | stxa %r14, [0x60]%asi |
| 3591 | st %g0, [%r23] !clear lock |
| 3592 | wr %g0, %r12, %asi |
| 3593 | ta T_CHANGE_NONHPRIV |
| 3594 | .word 0x9191800b ! 118: WRPR_PIL_R wrpr %r6, %r11, %pil |
| 3595 | #if (defined SPC || defined CMP) |
| 3596 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_80_85)+24, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3597 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_80_85)&0xffffffff) + 32, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3598 | xir_80_85: |
| 3599 | #else |
| 3600 | #if (defined FC) |
| 3601 | !! Generate XIR via RESET_GEN register |
| 3602 | ta T_CHANGE_HPRIV |
| 3603 | rdpr %pstate, %r18 |
| 3604 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 3605 | wrpr %r18, %pstate |
| 3606 | #ifndef XIR_RND_CORES |
| 3607 | ldxa [%g0] 0x63, %o1 |
| 3608 | mov 1, %r18 |
| 3609 | sllx %r18, %o1, %r18 |
| 3610 | #endif |
| 3611 | mov 0x30, %r19 |
| 3612 | setx 0x8900000808, %r16, %r17 |
| 3613 | mov 0x2, %r16 |
| 3614 | xir_80_85: |
| 3615 | stxa %r18, [%r19] 0x41 |
| 3616 | stx %r16, [%r17] |
| 3617 | #endif |
| 3618 | #endif |
| 3619 | .word 0xa98533a8 ! 119: WR_SET_SOFTINT_I wr %r20, 0x13a8, %set_softint |
| 3620 | cwp_80_86: |
| 3621 | set user_data_start, %o7 |
| 3622 | .word 0x93902006 ! 120: WRPR_CWP_I wrpr %r0, 0x0006, %cwp |
| 3623 | nop |
| 3624 | mov 0x80, %g3 |
| 3625 | stxa %r13, [%r0] ASI_LSU_CONTROL |
| 3626 | stxa %g3, [%g3] 0x57 |
| 3627 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 3628 | nop |
| 3629 | ta T_CHANGE_HPRIV ! macro |
| 3630 | donret_80_87: |
| 3631 | rd %pc, %r12 |
| 3632 | mov HIGHVA_HIGHNUM, %r10 |
| 3633 | sllx %r10, 32, %r10 |
| 3634 | or %r12, %r10, %r12 |
| 3635 | add %r12, (donretarg_80_87-donret_80_87), %r12 |
| 3636 | add %r12, 0x4, %r11 ! seq tnpc |
| 3637 | andn %r11, %r10, %r11 ! low VA tnpc |
| 3638 | wrpr %g0, 0x1, %tl |
| 3639 | wrpr %g0, %r12, %tpc |
| 3640 | wrpr %g0, %r11, %tnpc |
| 3641 | set (0x00cdd000 | (0x8a << 24)), %r13 |
| 3642 | and %r12, 0xfff, %r14 |
| 3643 | sllx %r14, 32, %r14 |
| 3644 | or %r13, %r14, %r20 |
| 3645 | wrpr %r20, %g0, %tstate |
| 3646 | wrhpr %g0, 0x98d, %htstate |
| 3647 | ta T_CHANGE_NONPRIV ! rand=0 (80) |
| 3648 | ldx [%r11+%r0], %g1 |
| 3649 | done |
| 3650 | donretarg_80_87: |
| 3651 | .word 0xe66fe13c ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x013c] |
| 3652 | invtsb_80_88: |
| 3653 | nop |
| 3654 | ta T_CHANGE_HPRIV |
| 3655 | rd %asi, %r21 |
| 3656 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 3657 | mov 1, %r20 |
| 3658 | sllx %r20, 63, %r20 |
| 3659 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 3660 | xor %r22 ,%r20, %r22 |
| 3661 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 3662 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 3663 | xor %r22 ,%r20, %r22 |
| 3664 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 3665 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 3666 | xor %r22 ,%r20, %r22 |
| 3667 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 3668 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 3669 | xor %r22 ,%r20, %r22 |
| 3670 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 3671 | wr %r21, %r0, %asi |
| 3672 | ta T_CHANGE_NONHPRIV |
| 3673 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 3674 | .word 0x9545c000 ! 124: RD_TICK_CMPR_REG rd %-, %r10 |
| 3675 | .word 0xc19fdc00 ! 125: LDDFA_R ldda [%r31, %r0], %f0 |
| 3676 | nop |
| 3677 | ta T_CHANGE_HPRIV |
| 3678 | mov 0x80+1, %r10 |
| 3679 | set sync_thr_counter5, %r23 |
| 3680 | #ifndef SPC |
| 3681 | ldxa [%g0]0x63, %o1 |
| 3682 | and %o1, 0x38, %o1 |
| 3683 | add %o1, %r23, %r23 |
| 3684 | sllx %o1, 5, %o3 !(CID*256) |
| 3685 | #endif |
| 3686 | cas [%r23],%g0,%r10 !lock |
| 3687 | brnz %r10, cwq_80_89 |
| 3688 | rd %asi, %r12 |
| 3689 | wr %g0, 0x40, %asi |
| 3690 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 3691 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 3692 | cmp %l1, 1 |
| 3693 | bne cwq_80_89 |
| 3694 | set CWQ_BASE, %l6 |
| 3695 | #ifndef SPC |
| 3696 | add %l6, %o3, %l6 |
| 3697 | #endif |
| 3698 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 3699 | best_set_reg(0x20610010, %l1, %l2) !# Control Word |
| 3700 | sllx %l2, 32, %l2 |
| 3701 | stx %l2, [%l6 + 0x0] |
| 3702 | membar #Sync |
| 3703 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 3704 | sub %l2, 0x40, %l2 |
| 3705 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 3706 | wr %r12, %g0, %asi |
| 3707 | st %g0, [%r23] |
| 3708 | cwq_80_89: |
| 3709 | ta T_CHANGE_NONHPRIV |
| 3710 | .word 0xa9414000 ! 126: RDPC rd %pc, %r20 |
| 3711 | cmp_80_90: |
| 3712 | nop |
| 3713 | ta T_CHANGE_HPRIV |
| 3714 | rd %asi, %r12 |
| 3715 | wr %r0, 0x41, %asi |
| 3716 | set sync_thr_counter4, %r23 |
| 3717 | #ifndef SPC |
| 3718 | ldxa [%g0]0x63, %r8 |
| 3719 | and %r8, 0x38, %r8 ! Core ID |
| 3720 | add %r8, %r23, %r23 |
| 3721 | mov 0xff, %r9 |
| 3722 | xor %r9, 0x80, %r9 |
| 3723 | sllx %r9, %r8, %r9 ! My core mask |
| 3724 | #else |
| 3725 | mov 0, %r8 |
| 3726 | mov 0xff, %r9 |
| 3727 | xor %r9, 0x80, %r9 ! My core mask |
| 3728 | #endif |
| 3729 | mov 0x80, %r10 |
| 3730 | cmp_startwait80_90: |
| 3731 | cas [%r23],%g0,%r10 !lock |
| 3732 | brz,a %r10, continue_cmp_80_90 |
| 3733 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3734 | ld [%r23], %r10 |
| 3735 | cmp_wait80_90: |
| 3736 | brnz,a %r10, cmp_wait80_90 |
| 3737 | ld [%r23], %r10 |
| 3738 | ba cmp_startwait80_90 |
| 3739 | mov 0x80, %r10 |
| 3740 | continue_cmp_80_90: |
| 3741 | ldxa [0x58]%asi, %r14 !Running_status |
| 3742 | xnor %r14, %r13, %r14 !Bits equal |
| 3743 | brz,a %r8, cmp_multi_core_80_90 |
| 3744 | mov 0x68, %r17 |
| 3745 | best_set_reg(0x6ceb81a2ca3b526e, %r16, %r17) |
| 3746 | cmp_multi_core_80_90: |
| 3747 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 3748 | and %r14, %r9, %r14 !Apply core-mask |
| 3749 | stxa %r14, [0x60]%asi |
| 3750 | st %g0, [%r23] !clear lock |
| 3751 | wr %g0, %r12, %asi |
| 3752 | ta T_CHANGE_NONHPRIV |
| 3753 | .word 0xa5a00174 ! 127: FABSq dis not found |
| 3754 | |
| 3755 | #if (defined SPC || defined CMP) |
| 3756 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_80_91)+32, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3757 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_80_91)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x80),1,3,,,,,1) |
| 3758 | xir_80_91: |
| 3759 | #else |
| 3760 | #if (defined FC) |
| 3761 | !! Generate XIR via RESET_GEN register |
| 3762 | ta T_CHANGE_HPRIV |
| 3763 | rdpr %pstate, %r18 |
| 3764 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 3765 | wrpr %r18, %pstate |
| 3766 | #ifndef XIR_RND_CORES |
| 3767 | ldxa [%g0] 0x63, %o1 |
| 3768 | mov 1, %r18 |
| 3769 | sllx %r18, %o1, %r18 |
| 3770 | #endif |
| 3771 | mov 0x30, %r19 |
| 3772 | setx 0x8900000808, %r16, %r17 |
| 3773 | mov 0x2, %r16 |
| 3774 | xir_80_91: |
| 3775 | stxa %r18, [%r19] 0x41 |
| 3776 | stx %r16, [%r17] |
| 3777 | #endif |
| 3778 | #endif |
| 3779 | .word 0xa9846b2b ! 128: WR_SET_SOFTINT_I wr %r17, 0x0b2b, %set_softint |
| 3780 | memptr_80_92: |
| 3781 | set 0x60340000, %r31 |
| 3782 | .word 0x8584258f ! 129: WRCCR_I wr %r16, 0x058f, %ccr |
| 3783 | rd %tick, %r28 |
| 3784 | #if (MAX_THREADS == 8) |
| 3785 | sethi %hi(0x33800), %r27 |
| 3786 | #else |
| 3787 | sethi %hi(0x30000), %r27 |
| 3788 | #endif |
| 3789 | andn %r28, %r27, %r28 |
| 3790 | ta T_CHANGE_HPRIV |
| 3791 | stxa %r28, [%g0] 0x73 |
| 3792 | intvec_80_93: |
| 3793 | .word 0xa7b4c4c3 ! 130: FCMPNE32 fcmpne32 %d50, %d34, %r19 |
| 3794 | splash_tick_80_94: |
| 3795 | nop |
| 3796 | ta T_CHANGE_HPRIV |
| 3797 | best_set_reg(0x435ae92b637f0328, %r16, %r17) |
| 3798 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 3799 | memptr_80_95: |
| 3800 | set 0x60540000, %r31 |
| 3801 | .word 0x8581b230 ! 132: WRCCR_I wr %r6, 0x1230, %ccr |
| 3802 | splash_hpstate_80_96: |
| 3803 | .word 0x34800001 ! 1: BG bg,a <label_0x1> |
| 3804 | .word 0x81983415 ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x1415, %hpstate |
| 3805 | jmptr_80_97: |
| 3806 | nop |
| 3807 | best_set_reg(0xe0a00000, %r20, %r27) |
| 3808 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 3809 | bgu,a skip_80_98 |
| 3810 | stxa %r7, [%r0] ASI_LSU_CONTROL |
| 3811 | fbuge,a,pn %fcc0, skip_80_98 |
| 3812 | stxa %r17, [%r0] ASI_LSU_CONTROL |
| 3813 | .align 128 |
| 3814 | skip_80_98: |
| 3815 | .word 0xd3e7c020 ! 135: CASA_I casa [%r31] 0x 1, %r0, %r9 |
| 3816 | .word 0x8d903041 ! 136: WRPR_PSTATE_I wrpr %r0, 0x1041, %pstate |
| 3817 | cmp_80_100: |
| 3818 | nop |
| 3819 | ta T_CHANGE_HPRIV |
| 3820 | rd %asi, %r12 |
| 3821 | wr %r0, 0x41, %asi |
| 3822 | set sync_thr_counter4, %r23 |
| 3823 | #ifndef SPC |
| 3824 | ldxa [%g0]0x63, %r8 |
| 3825 | and %r8, 0x38, %r8 ! Core ID |
| 3826 | add %r8, %r23, %r23 |
| 3827 | mov 0xff, %r9 |
| 3828 | xor %r9, 0x80, %r9 |
| 3829 | sllx %r9, %r8, %r9 ! My core mask |
| 3830 | #else |
| 3831 | mov 0, %r8 |
| 3832 | mov 0xff, %r9 |
| 3833 | xor %r9, 0x80, %r9 ! My core mask |
| 3834 | #endif |
| 3835 | mov 0x80, %r10 |
| 3836 | cmp_startwait80_100: |
| 3837 | cas [%r23],%g0,%r10 !lock |
| 3838 | brz,a %r10, continue_cmp_80_100 |
| 3839 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3840 | ld [%r23], %r10 |
| 3841 | cmp_wait80_100: |
| 3842 | brnz,a %r10, cmp_wait80_100 |
| 3843 | ld [%r23], %r10 |
| 3844 | ba cmp_startwait80_100 |
| 3845 | mov 0x80, %r10 |
| 3846 | continue_cmp_80_100: |
| 3847 | ldxa [0x58]%asi, %r14 !Running_status |
| 3848 | xnor %r14, %r13, %r14 !Bits equal |
| 3849 | brz,a %r8, cmp_multi_core_80_100 |
| 3850 | mov 0x8a, %r17 |
| 3851 | best_set_reg(0x226e9bb71c5a9c2e, %r16, %r17) |
| 3852 | cmp_multi_core_80_100: |
| 3853 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 3854 | and %r14, %r9, %r14 !Apply core-mask |
| 3855 | stxa %r14, [0x60]%asi |
| 3856 | st %g0, [%r23] !clear lock |
| 3857 | wr %g0, %r12, %asi |
| 3858 | .word 0xa3a00170 ! 137: FABSq dis not found |
| 3859 | |
| 3860 | nop |
| 3861 | ta T_CHANGE_HPRIV |
| 3862 | mov 0x80, %r10 |
| 3863 | set sync_thr_counter6, %r23 |
| 3864 | #ifndef SPC |
| 3865 | ldxa [%g0]0x63, %o1 |
| 3866 | and %o1, 0x38, %o1 |
| 3867 | add %o1, %r23, %r23 |
| 3868 | #endif |
| 3869 | cas [%r23],%g0,%r10 !lock |
| 3870 | brnz %r10, sma_80_101 |
| 3871 | rd %asi, %r12 |
| 3872 | wr %g0, 0x40, %asi |
| 3873 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 3874 | set 0x001a1fff, %g1 |
| 3875 | stxa %g1, [%g0 + 0x80] %asi |
| 3876 | wr %r12, %g0, %asi |
| 3877 | st %g0, [%r23] |
| 3878 | sma_80_101: |
| 3879 | ta T_CHANGE_NONHPRIV |
| 3880 | .word 0xe1e7e00b ! 138: CASA_R casa [%r31] %asi, %r11, %r16 |
| 3881 | ticken_80_102: |
| 3882 | nop |
| 3883 | ta T_CHANGE_HPRIV |
| 3884 | rd %asi, %r12 |
| 3885 | wr %r0, 0x41, %asi |
| 3886 | stxa %g0, [0x38]%asi |
| 3887 | best_set_reg(0x240ea2c9565d48a4, %r16, %r17) |
| 3888 | wrpr %g0, %r17, %tick |
| 3889 | mov 1, %r16 |
| 3890 | stxa %r16, [0x38]%asi |
| 3891 | wr %g0, %r12, %asi |
| 3892 | .word 0xa5b400eb ! 139: EDGE16LN edge16ln %r16, %r11, %r18 |
| 3893 | splash_lsu_80_103: |
| 3894 | nop |
| 3895 | ta T_CHANGE_HPRIV |
| 3896 | set 0x30af08ce, %r2 |
| 3897 | mov 0x2, %r1 |
| 3898 | sllx %r1, 32, %r1 |
| 3899 | or %r1, %r2, %r2 |
| 3900 | .word 0x30800001 ! 1: BA ba,a <label_0x1> |
| 3901 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 3902 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 3903 | .word 0x956c400c ! 141: SDIVX_R sdivx %r17, %r12, %r10 |
| 3904 | .word 0xc19fe000 ! 142: LDDFA_I ldda [%r31, 0x0000], %f0 |
| 3905 | cmp_80_104: |
| 3906 | nop |
| 3907 | ta T_CHANGE_HPRIV |
| 3908 | rd %asi, %r12 |
| 3909 | wr %r0, 0x41, %asi |
| 3910 | set sync_thr_counter4, %r23 |
| 3911 | #ifndef SPC |
| 3912 | ldxa [%g0]0x63, %r8 |
| 3913 | and %r8, 0x38, %r8 ! Core ID |
| 3914 | add %r8, %r23, %r23 |
| 3915 | mov 0xff, %r9 |
| 3916 | xor %r9, 0x80, %r9 |
| 3917 | sllx %r9, %r8, %r9 ! My core mask |
| 3918 | #else |
| 3919 | mov 0, %r8 |
| 3920 | mov 0xff, %r9 |
| 3921 | xor %r9, 0x80, %r9 ! My core mask |
| 3922 | #endif |
| 3923 | mov 0x80, %r10 |
| 3924 | cmp_startwait80_104: |
| 3925 | cas [%r23],%g0,%r10 !lock |
| 3926 | brz,a %r10, continue_cmp_80_104 |
| 3927 | ldxa [0x50]%asi, %r13 !Running_rw |
| 3928 | ld [%r23], %r10 |
| 3929 | cmp_wait80_104: |
| 3930 | brnz,a %r10, cmp_wait80_104 |
| 3931 | ld [%r23], %r10 |
| 3932 | ba cmp_startwait80_104 |
| 3933 | mov 0x80, %r10 |
| 3934 | continue_cmp_80_104: |
| 3935 | ldxa [0x58]%asi, %r14 !Running_status |
| 3936 | xnor %r14, %r13, %r14 !Bits equal |
| 3937 | brz,a %r8, cmp_multi_core_80_104 |
| 3938 | mov 36, %r17 |
| 3939 | best_set_reg(0x24675290b57af9e5, %r16, %r17) |
| 3940 | cmp_multi_core_80_104: |
| 3941 | and %r14, %r17, %r14 !Apply set/clear mask to bits equal |
| 3942 | and %r14, %r9, %r14 !Apply core-mask |
| 3943 | stxa %r14, [0x60]%asi |
| 3944 | st %g0, [%r23] !clear lock |
| 3945 | wr %g0, %r12, %asi |
| 3946 | .word 0x91950006 ! 143: WRPR_PIL_R wrpr %r20, %r6, %pil |
| 3947 | splash_hpstate_80_105: |
| 3948 | ta T_CHANGE_NONHPRIV |
| 3949 | .word 0x81983ba4 ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x1ba4, %hpstate |
| 3950 | splash_tick_80_106: |
| 3951 | nop |
| 3952 | ta T_CHANGE_HPRIV |
| 3953 | best_set_reg(0x3deb81030a93c6eb, %r16, %r17) |
| 3954 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 3955 | nop |
| 3956 | ta T_CHANGE_HPRIV |
| 3957 | mov 0x80, %r10 |
| 3958 | set sync_thr_counter6, %r23 |
| 3959 | #ifndef SPC |
| 3960 | ldxa [%g0]0x63, %o1 |
| 3961 | and %o1, 0x38, %o1 |
| 3962 | add %o1, %r23, %r23 |
| 3963 | #endif |
| 3964 | cas [%r23],%g0,%r10 !lock |
| 3965 | brnz %r10, sma_80_107 |
| 3966 | rd %asi, %r12 |
| 3967 | wr %g0, 0x40, %asi |
| 3968 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 3969 | set 0x001e1fff, %g1 |
| 3970 | stxa %g1, [%g0 + 0x80] %asi |
| 3971 | wr %r12, %g0, %asi |
| 3972 | st %g0, [%r23] |
| 3973 | sma_80_107: |
| 3974 | ta T_CHANGE_NONHPRIV |
| 3975 | .word 0xd1e7e00c ! 146: CASA_R casa [%r31] %asi, %r12, %r8 |
| 3976 | fpinit_80_108: |
| 3977 | nop |
| 3978 | setx fp_data_quads, %r19, %r20 |
| 3979 | ldd [%r20], %f0 |
| 3980 | ldd [%r20+8], %f4 |
| 3981 | ld [%r20+16], %fsr |
| 3982 | ld [%r20+24], %r19 |
| 3983 | wr %r19, %g0, %gsr |
| 3984 | .word 0x91a009c4 ! 147: FDIVd fdivd %f0, %f4, %f8 |
| 3985 | intveclr_80_109: |
| 3986 | nop |
| 3987 | ta T_CHANGE_HPRIV |
| 3988 | setx 0xb0d314e1ba80279a, %r1, %r28 |
| 3989 | stxa %r28, [%g0] 0x72 |
| 3990 | ta T_CHANGE_NONHPRIV |
| 3991 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 3992 | brcommon3_80_110: |
| 3993 | nop |
| 3994 | setx common_target, %r12, %r27 |
| 3995 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 3996 | ba,a .+12 |
| 3997 | .word 0xd06fe050 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x0050] |
| 3998 | ba,a .+8 |
| 3999 | jmpl %r27+0, %r27 |
| 4000 | .word 0xd09fe1e0 ! 149: LDDA_I ldda [%r31, + 0x01e0] %asi, %r8 |
| 4001 | .word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1> |
| 4002 | .word 0x8d903cbf ! 150: WRPR_PSTATE_I wrpr %r0, 0x1cbf, %pstate |
| 4003 | # 953 "diag.j.pp" |
| 4004 | cmpenall_80_112: |
| 4005 | nop |
| 4006 | nop |
| 4007 | ta T_CHANGE_HPRIV |
| 4008 | rd %asi, %r12 |
| 4009 | wr %r0, 0x41, %asi |
| 4010 | set sync_thr_counter4, %r23 |
| 4011 | #ifndef SPC |
| 4012 | ldxa [%g0]0x63, %r8 |
| 4013 | and %r8, 0x38, %r8 ! Core ID |
| 4014 | add %r8, %r23, %r23 |
| 4015 | mov 0xff, %r9 |
| 4016 | sllx %r9, %r8, %r9 ! My core mask |
| 4017 | #else |
| 4018 | mov 0xff, %r9 ! My core mask |
| 4019 | #endif |
| 4020 | cmpenall_startwait80_112: |
| 4021 | mov 0x80, %r10 |
| 4022 | cas [%r23],%g0,%r10 !lock |
| 4023 | brz,a %r10, continue_cmpenall_80_112 |
| 4024 | nop |
| 4025 | cmpenall_wait80_112: |
| 4026 | ld [%r23], %r10 |
| 4027 | brnz %r10, cmpenall_wait80_112 |
| 4028 | nop |
| 4029 | ba,a cmpenall_startwait80_112 |
| 4030 | continue_cmpenall_80_112: |
| 4031 | ldxa [0x58]%asi, %r14 !Running_status |
| 4032 | wait_for_cmpstat_80_112: |
| 4033 | ldxa [0x50]%asi, %r13 !Running_rw |
| 4034 | cmp %r13, %r14 |
| 4035 | bne,a %xcc, wait_for_cmpstat_80_112 |
| 4036 | ldxa [0x58]%asi, %r14 !Running_status |
| 4037 | ldxa [0x10]%asi, %r14 !Get enabled threads |
| 4038 | and %r14, %r9, %r14 !My core mask |
| 4039 | stxa %r14, [0x60]%asi !W1S |
| 4040 | ldxa [0x58]%asi, %r16 !Running_status |
| 4041 | wait_for_cmpstat2_80_112: |
| 4042 | and %r16, %r9, %r16 !My core mask |
| 4043 | cmp %r14, %r16 |
| 4044 | bne,a %xcc, wait_for_cmpstat2_80_112 |
| 4045 | ldxa [0x58]%asi, %r16 !Running_status |
| 4046 | st %g0, [%r23] !clear lock |
| 4047 | #if (MULTIPASS > 0) |
| 4048 | multipass_check_mt: |
| 4049 | rd %asi, %r12 |
| 4050 | wr %g0, ASI_SCRATCHPAD, %asi |
| 4051 | ldxa [0x38]%asi, %r10 |
| 4052 | cmp %r10, MULTIPASS |
| 4053 | inc %r10 |
| 4054 | stxa %r10, [0x38]%asi |
| 4055 | be finish_diag |
| 4056 | wr %g0, %r12, %asi |
| 4057 | lock_sync_thds_again: |
| 4058 | mov 0xff, %r10 |
| 4059 | set sync_thr_counter4, %r23 |
| 4060 | #ifndef SPC |
| 4061 | add %o2,%r9,%r23 !Core's sync counter |
| 4062 | #endif |
| 4063 | st %r10, [%r23] !lock sync_thr_counter4 |
| 4064 | add %r23, 64, %r23 |
| 4065 | st %r10, [%r23] !lock sync_thr_counter5 |
| 4066 | add %r23, 64, %r23 |
| 4067 | st %r10, [%r23] !lock sync_thr_counter6 |
| 4068 | ba fork_threads |
| 4069 | wrpr %g0, %g0, %gl |
| 4070 | #endif |
| 4071 | nop |
| 4072 | nop |
| 4073 | ta T_CHANGE_PRIV |
| 4074 | wrpr %g0, %g0, %gl |
| 4075 | nop |
| 4076 | nop |
| 4077 | .text |
| 4078 | setx join_lbl_0_0, %g1, %g2 |
| 4079 | jmp %g2 |
| 4080 | nop |
| 4081 | fork_lbl_0_7: |
| 4082 | ta T_CHANGE_NONHPRIV |
| 4083 | .word 0xe877e022 ! 1: STX_I stx %r20, [%r31 + 0x0022] |
| 4084 | br_longdelay4_40_0: |
| 4085 | nop |
| 4086 | not %g0, %r27 |
| 4087 | jmpl %r27+0, %r27 |
| 4088 | .word 0x9d902000 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0000, %wstate |
| 4089 | .word 0xe93fe00c ! 3: STDF_I std %f20, [0x000c, %r31] |
| 4090 | fpinit_40_1: |
| 4091 | nop |
| 4092 | setx fp_data_quads, %r19, %r20 |
| 4093 | ldd [%r20], %f0 |
| 4094 | ldd [%r20+8], %f4 |
| 4095 | ld [%r20+16], %fsr |
| 4096 | ld [%r20+24], %r19 |
| 4097 | wr %r19, %g0, %gsr |
| 4098 | .word 0x8db00484 ! 4: FCMPLE32 fcmple32 %d0, %d4, %r6 |
| 4099 | splash_lsu_40_2: |
| 4100 | nop |
| 4101 | ta T_CHANGE_HPRIV |
| 4102 | set 0xaf0ecd73, %r2 |
| 4103 | mov 0x3, %r1 |
| 4104 | sllx %r1, 32, %r1 |
| 4105 | or %r1, %r2, %r2 |
| 4106 | .word 0x21400001 ! 1: FBPN fbn,a,pn %fcc0, <label_0x1> |
| 4107 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4108 | ta T_CHANGE_NONHPRIV |
| 4109 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4110 | splash_hpstate_40_3: |
| 4111 | .word 0x81982c1f ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x0c1f, %hpstate |
| 4112 | memptr_40_4: |
| 4113 | set 0x60740000, %r31 |
| 4114 | .word 0x85836c23 ! 7: WRCCR_I wr %r13, 0x0c23, %ccr |
| 4115 | nop |
| 4116 | mov 0x80, %g3 |
| 4117 | .word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1> |
| 4118 | stxa %g3, [%g3] 0x5f |
| 4119 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 4120 | .word 0xe19fe1c0 ! 9: LDDFA_I ldda [%r31, 0x01c0], %f16 |
| 4121 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 4122 | .word 0xe1bfc2c0 ! 11: STDFA_R stda %f16, [%r0, %r31] |
| 4123 | dvapa_40_6: |
| 4124 | nop |
| 4125 | ta T_CHANGE_HPRIV |
| 4126 | mov 0xa42, %r20 |
| 4127 | mov 0xb, %r19 |
| 4128 | sllx %r20, 23, %r20 |
| 4129 | or %r19, %r20, %r19 |
| 4130 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 4131 | mov 0x38, %r18 |
| 4132 | stxa %r31, [%r18]0x58 |
| 4133 | ta T_CHANGE_NONHPRIV |
| 4134 | .word 0xc19fe180 ! 12: LDDFA_I ldda [%r31, 0x0180], %f0 |
| 4135 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 4136 | jmptr_40_7: |
| 4137 | nop |
| 4138 | best_set_reg(0xe1200000, %r20, %r27) |
| 4139 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 4140 | pmu_40_8: |
| 4141 | nop |
| 4142 | ta T_CHANGE_PRIV |
| 4143 | setx 0xffffffb0ffffffa4, %g1, %g7 |
| 4144 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 4145 | jmptr_40_9: |
| 4146 | nop |
| 4147 | best_set_reg(0xe1200000, %r20, %r27) |
| 4148 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 4149 | nop |
| 4150 | ta T_CHANGE_HPRIV |
| 4151 | mov 0x40, %r10 |
| 4152 | set sync_thr_counter6, %r23 |
| 4153 | #ifndef SPC |
| 4154 | ldxa [%g0]0x63, %o1 |
| 4155 | and %o1, 0x38, %o1 |
| 4156 | add %o1, %r23, %r23 |
| 4157 | #endif |
| 4158 | cas [%r23],%g0,%r10 !lock |
| 4159 | brnz %r10, sma_40_10 |
| 4160 | rd %asi, %r12 |
| 4161 | wr %g0, 0x40, %asi |
| 4162 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4163 | set 0x00021fff, %g1 |
| 4164 | stxa %g1, [%g0 + 0x80] %asi |
| 4165 | wr %r12, %g0, %asi |
| 4166 | st %g0, [%r23] |
| 4167 | sma_40_10: |
| 4168 | ta T_CHANGE_NONHPRIV |
| 4169 | .word 0xe9e7e011 ! 17: CASA_R casa [%r31] %asi, %r17, %r20 |
| 4170 | .word 0x87802020 ! 18: WRASI_I wr %r0, 0x0020, %asi |
| 4171 | splash_lsu_40_11: |
| 4172 | nop |
| 4173 | ta T_CHANGE_HPRIV |
| 4174 | set 0x3915a99d, %r2 |
| 4175 | mov 0x2, %r1 |
| 4176 | sllx %r1, 32, %r1 |
| 4177 | or %r1, %r2, %r2 |
| 4178 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4179 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4180 | .word 0xe93fe078 ! 20: STDF_I std %f20, [0x0078, %r31] |
| 4181 | brcommon1_40_12: |
| 4182 | nop |
| 4183 | setx common_target, %r12, %r27 |
| 4184 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 4185 | ba,a .+12 |
| 4186 | .word 0xa9b7c7cc ! 1: PDIST pdistn %d62, %d12, %d20 |
| 4187 | ba,a .+8 |
| 4188 | jmpl %r27+0, %r27 |
| 4189 | .word 0x9f8022aa ! 21: SIR sir 0x02aa |
| 4190 | splash_lsu_40_13: |
| 4191 | nop |
| 4192 | ta T_CHANGE_HPRIV |
| 4193 | set 0x95677068, %r2 |
| 4194 | mov 0x1, %r1 |
| 4195 | sllx %r1, 32, %r1 |
| 4196 | or %r1, %r2, %r2 |
| 4197 | .word 0x2d400001 ! 1: FBPG fbg,a,pn %fcc0, <label_0x1> |
| 4198 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4199 | ta T_CHANGE_NONHPRIV |
| 4200 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4201 | .word 0xc19fd920 ! 23: LDDFA_R ldda [%r31, %r0], %f0 |
| 4202 | .word 0xc1bfdf20 ! 24: STDFA_R stda %f0, [%r0, %r31] |
| 4203 | pmu_40_14: |
| 4204 | nop |
| 4205 | ta T_CHANGE_PRIV |
| 4206 | setx 0xffffffbeffffffa8, %g1, %g7 |
| 4207 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 4208 | rd %tick, %r28 |
| 4209 | #if (MAX_THREADS == 8) |
| 4210 | sethi %hi(0x33800), %r27 |
| 4211 | #else |
| 4212 | sethi %hi(0x30000), %r27 |
| 4213 | #endif |
| 4214 | andn %r28, %r27, %r28 |
| 4215 | ta T_CHANGE_HPRIV |
| 4216 | stxa %r28, [%g0] 0x73 |
| 4217 | .word 0x91a449d1 ! 1: FDIVd fdivd %f48, %f48, %f8 |
| 4218 | intvec_40_15: |
| 4219 | .word 0x95a409c6 ! 26: FDIVd fdivd %f16, %f6, %f10 |
| 4220 | .word 0x91908008 ! 27: WRPR_PIL_R wrpr %r2, %r8, %pil |
| 4221 | nop |
| 4222 | mov 0x80, %g3 |
| 4223 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 4224 | stxa %g3, [%g3] 0x57 |
| 4225 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 4226 | #if (defined SPC || defined CMP) |
| 4227 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_40_17)+32, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 4228 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_40_17)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 4229 | xir_40_17: |
| 4230 | #else |
| 4231 | #if (defined FC) |
| 4232 | !! Generate XIR via RESET_GEN register |
| 4233 | ta T_CHANGE_HPRIV |
| 4234 | rdpr %pstate, %r18 |
| 4235 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 4236 | wrpr %r18, %pstate |
| 4237 | #ifndef XIR_RND_CORES |
| 4238 | ldxa [%g0] 0x63, %o1 |
| 4239 | mov 1, %r18 |
| 4240 | sllx %r18, %o1, %r18 |
| 4241 | #endif |
| 4242 | mov 0x30, %r19 |
| 4243 | setx 0x8900000808, %r16, %r17 |
| 4244 | mov 0x2, %r16 |
| 4245 | xir_40_17: |
| 4246 | stxa %r18, [%r19] 0x41 |
| 4247 | stx %r16, [%r17] |
| 4248 | #endif |
| 4249 | #endif |
| 4250 | .word 0xa9852418 ! 29: WR_SET_SOFTINT_I wr %r20, 0x0418, %set_softint |
| 4251 | .word 0xa5a00161 ! 30: FABSq dis not found |
| 4252 | |
| 4253 | .word 0x93a00166 ! 31: FABSq dis not found |
| 4254 | |
| 4255 | tagged_40_20: |
| 4256 | tsubcctv %r13, 0x1bc6, %r17 |
| 4257 | .word 0xd807e0a4 ! 32: LDUW_I lduw [%r31 + 0x00a4], %r12 |
| 4258 | mondo_40_21: |
| 4259 | nop |
| 4260 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 4261 | stxa %r7, [%r0+0x3c8] %asi |
| 4262 | .word 0x9d940014 ! 33: WRPR_WSTATE_R wrpr %r16, %r20, %wstate |
| 4263 | .word 0xb1830013 ! 34: WR_STICK_REG_R wr %r12, %r19, %- |
| 4264 | nop |
| 4265 | ta T_CHANGE_HPRIV |
| 4266 | mov 0x40, %r10 |
| 4267 | set sync_thr_counter6, %r23 |
| 4268 | #ifndef SPC |
| 4269 | ldxa [%g0]0x63, %o1 |
| 4270 | and %o1, 0x38, %o1 |
| 4271 | add %o1, %r23, %r23 |
| 4272 | #endif |
| 4273 | cas [%r23],%g0,%r10 !lock |
| 4274 | brnz %r10, sma_40_22 |
| 4275 | rd %asi, %r12 |
| 4276 | wr %g0, 0x40, %asi |
| 4277 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4278 | set 0x00161fff, %g1 |
| 4279 | stxa %g1, [%g0 + 0x80] %asi |
| 4280 | wr %r12, %g0, %asi |
| 4281 | st %g0, [%r23] |
| 4282 | sma_40_22: |
| 4283 | ta T_CHANGE_NONHPRIV |
| 4284 | .word 0xd9e7e00c ! 35: CASA_R casa [%r31] %asi, %r12, %r12 |
| 4285 | nop |
| 4286 | ta T_CHANGE_HPRIV |
| 4287 | mov 0x40, %r10 |
| 4288 | set sync_thr_counter6, %r23 |
| 4289 | #ifndef SPC |
| 4290 | ldxa [%g0]0x63, %o1 |
| 4291 | and %o1, 0x38, %o1 |
| 4292 | add %o1, %r23, %r23 |
| 4293 | #endif |
| 4294 | cas [%r23],%g0,%r10 !lock |
| 4295 | brnz %r10, sma_40_23 |
| 4296 | rd %asi, %r12 |
| 4297 | wr %g0, 0x40, %asi |
| 4298 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4299 | set 0x001e1fff, %g1 |
| 4300 | stxa %g1, [%g0 + 0x80] %asi |
| 4301 | wr %r12, %g0, %asi |
| 4302 | st %g0, [%r23] |
| 4303 | sma_40_23: |
| 4304 | ta T_CHANGE_NONHPRIV |
| 4305 | .word 0xd9e7e00c ! 36: CASA_R casa [%r31] %asi, %r12, %r12 |
| 4306 | splash_tba_40_24: |
| 4307 | nop |
| 4308 | ta T_CHANGE_PRIV |
| 4309 | set 0x120000, %r12 |
| 4310 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 4311 | splash_lsu_40_25: |
| 4312 | nop |
| 4313 | ta T_CHANGE_HPRIV |
| 4314 | set 0xfea700d7, %r2 |
| 4315 | mov 0x4, %r1 |
| 4316 | sllx %r1, 32, %r1 |
| 4317 | or %r1, %r2, %r2 |
| 4318 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4319 | ta T_CHANGE_NONHPRIV |
| 4320 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4321 | #if (defined SPC || defined CMP1) |
| 4322 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_26) + 48, 16, 16)) -> intp(7,0,2,,,,,1) |
| 4323 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_40_26)&0xffffffff) + 48, 16, 16)) -> intp(0,0,2,,,,,1) |
| 4324 | #else |
| 4325 | set 0x6cc0f16b, %r28 |
| 4326 | #if (MAX_THREADS == 8) |
| 4327 | and %r28, 0x7ff, %r28 |
| 4328 | #endif |
| 4329 | stxa %r28, [%g0] 0x73 |
| 4330 | #endif |
| 4331 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 4332 | intvec_40_26: |
| 4333 | .word 0xc36afd54 ! 39: PREFETCH_I prefetch [%r11 + 0xfffffd54], #one_read |
| 4334 | .word 0xd727e0b4 ! 40: STF_I st %f11, [0x00b4, %r31] |
| 4335 | .word 0xd627e07c ! 41: STW_I stw %r11, [%r31 + 0x007c] |
| 4336 | jmptr_40_27: |
| 4337 | nop |
| 4338 | best_set_reg(0xe1200000, %r20, %r27) |
| 4339 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 4340 | splash_tba_40_28: |
| 4341 | nop |
| 4342 | ta T_CHANGE_PRIV |
| 4343 | set 0x120000, %r12 |
| 4344 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 4345 | set 0x3af, %l3 |
| 4346 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 4347 | .word 0x95b047d3 ! 44: PDIST pdistn %d32, %d50, %d10 |
| 4348 | pmu_40_29: |
| 4349 | nop |
| 4350 | setx 0xffffffb8ffffffa2, %g1, %g7 |
| 4351 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 4352 | brcommon3_40_30: |
| 4353 | nop |
| 4354 | setx common_target, %r12, %r27 |
| 4355 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 4356 | ba,a .+12 |
| 4357 | .word 0xe3e7c032 ! 1: CASA_I casa [%r31] 0x 1, %r18, %r17 |
| 4358 | ba,a .+8 |
| 4359 | jmpl %r27+0, %r27 |
| 4360 | .word 0xe3e7e010 ! 46: CASA_R casa [%r31] %asi, %r16, %r17 |
| 4361 | brcommon3_40_31: |
| 4362 | nop |
| 4363 | setx common_target, %r12, %r27 |
| 4364 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 4365 | ba,a .+12 |
| 4366 | .word 0xe26fe150 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x0150] |
| 4367 | ba,a .+8 |
| 4368 | jmpl %r27+0, %r27 |
| 4369 | stxa %r13, [%r0] ASI_LSU_CONTROL |
| 4370 | .word 0xa1aac831 ! 47: FMOVGE fmovs %fcc1, %f17, %f16 |
| 4371 | brcommon3_40_32: |
| 4372 | nop |
| 4373 | setx common_target, %r12, %r27 |
| 4374 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 4375 | ba,a .+12 |
| 4376 | .word 0xd737e1a0 ! 1: STQF_I - %f11, [0x01a0, %r31] |
| 4377 | ba,a .+8 |
| 4378 | jmpl %r27+0, %r27 |
| 4379 | .word 0xd6dfc032 ! 48: LDXA_R ldxa [%r31, %r18] 0x01, %r11 |
| 4380 | nop |
| 4381 | mov 0x80, %g3 |
| 4382 | .word 0x2cc98001 ! 1: BRGZ brgz,a,pt %r6,<label_0x98001> |
| 4383 | stxa %g3, [%g3] 0x5f |
| 4384 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 4385 | nop |
| 4386 | ta T_CHANGE_HPRIV ! macro |
| 4387 | donret_40_33: |
| 4388 | rd %pc, %r12 |
| 4389 | mov HIGHVA_HIGHNUM, %r10 |
| 4390 | sllx %r10, 32, %r10 |
| 4391 | or %r12, %r10, %r12 |
| 4392 | add %r12, (donretarg_40_33-donret_40_33), %r12 |
| 4393 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 4394 | andn %r11, %r10, %r11 ! low VA tnpc |
| 4395 | wrpr %g0, 0x1, %tl |
| 4396 | wrpr %g0, %r12, %tpc |
| 4397 | wrpr %g0, %r11, %tnpc |
| 4398 | set (0x00c2b300 | (57 << 24)), %r13 |
| 4399 | and %r12, 0xfff, %r14 |
| 4400 | sllx %r14, 32, %r14 |
| 4401 | or %r13, %r14, %r20 |
| 4402 | wrpr %r20, %g0, %tstate |
| 4403 | wrhpr %g0, 0x6ed, %htstate |
| 4404 | ta T_CHANGE_NONHPRIV ! rand=1 (40) |
| 4405 | ldx [%r11+%r0], %g1 |
| 4406 | done |
| 4407 | donretarg_40_33: |
| 4408 | .word 0x3d400001 ! 50: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4409 | #if (defined SPC || defined CMP1) |
| 4410 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_34) + 56, 16, 16)) -> intp(1,0,31,,,,,1) |
| 4411 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_40_34)&0xffffffff) + 56, 16, 16)) -> intp(3,0,29,,,,,1) |
| 4412 | #else |
| 4413 | set 0x34900460, %r28 |
| 4414 | #if (MAX_THREADS == 8) |
| 4415 | and %r28, 0x7ff, %r28 |
| 4416 | #endif |
| 4417 | stxa %r28, [%g0] 0x73 |
| 4418 | #endif |
| 4419 | intvec_40_34: |
| 4420 | .word 0x9f8026ad ! 51: SIR sir 0x06ad |
| 4421 | .word 0xe927e056 ! 52: STF_I st %f20, [0x0056, %r31] |
| 4422 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 4423 | splash_tba_40_35: |
| 4424 | nop |
| 4425 | ta T_CHANGE_PRIV |
| 4426 | setx 0x0000000400380000, %r11, %r12 |
| 4427 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 4428 | iaw_40_36: |
| 4429 | nop |
| 4430 | ta T_CHANGE_HPRIV |
| 4431 | mov 8, %r18 |
| 4432 | rd %asi, %r12 |
| 4433 | wr %r0, 0x41, %asi |
| 4434 | set sync_thr_counter4, %r23 |
| 4435 | #ifndef SPC |
| 4436 | ldxa [%g0]0x63, %r8 |
| 4437 | and %r8, 0x38, %r8 ! Core ID |
| 4438 | add %r8, %r23, %r23 |
| 4439 | #else |
| 4440 | mov 0, %r8 |
| 4441 | #endif |
| 4442 | mov 0x40, %r16 |
| 4443 | iaw_startwait40_36: |
| 4444 | cas [%r23],%g0,%r16 !lock |
| 4445 | brz,a %r16, continue_iaw_40_36 |
| 4446 | mov (~0x40&0xf0), %r16 |
| 4447 | ld [%r23], %r16 |
| 4448 | iaw_wait40_36: |
| 4449 | brnz %r16, iaw_wait40_36 |
| 4450 | ld [%r23], %r16 |
| 4451 | ba iaw_startwait40_36 |
| 4452 | mov 0x40, %r16 |
| 4453 | continue_iaw_40_36: |
| 4454 | sllx %r16, %r8, %r16 !Mask for my core only |
| 4455 | ldxa [0x58]%asi, %r17 !Running_status |
| 4456 | wait_for_stat_40_36: |
| 4457 | ldxa [0x50]%asi, %r13 !Running_rw |
| 4458 | cmp %r13, %r17 |
| 4459 | bne,a %xcc, wait_for_stat_40_36 |
| 4460 | ldxa [0x58]%asi, %r17 !Running_status |
| 4461 | stxa %r16, [0x68]%asi !Park (W1C) |
| 4462 | ldxa [0x50]%asi, %r14 !Running_rw |
| 4463 | wait_for_iaw_40_36: |
| 4464 | ldxa [0x58]%asi, %r17 !Running_status |
| 4465 | cmp %r14, %r17 |
| 4466 | bne,a %xcc, wait_for_iaw_40_36 |
| 4467 | ldxa [0x50]%asi, %r14 !Running_rw |
| 4468 | iaw_doit40_36: |
| 4469 | mov 0x38, %r18 |
| 4470 | iaw2_40_36: |
| 4471 | rdpr %tba, %r19 |
| 4472 | mov 0x320, %r20 |
| 4473 | sllx %r20, 5, %r20 |
| 4474 | add %r20, %r19, %r19 |
| 4475 | stxa %r19, [%r18]0x50 |
| 4476 | stxa %r16, [0x60] %asi ! Unpark (W1S) |
| 4477 | st %g0, [%r23] !clear lock |
| 4478 | wr %r0, %r12, %asi ! restore %asi |
| 4479 | ta T_CHANGE_NONHPRIV |
| 4480 | .word 0x91b047c9 ! 55: PDIST pdistn %d32, %d40, %d8 |
| 4481 | ibp_40_37: |
| 4482 | nop |
| 4483 | ta T_CHANGE_NONHPRIV |
| 4484 | .word 0x93a309b3 ! 56: FDIVs fdivs %f12, %f19, %f9 |
| 4485 | brcommon3_40_38: |
| 4486 | nop |
| 4487 | setx common_target, %r12, %r27 |
| 4488 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 4489 | ba,a .+12 |
| 4490 | .word 0xe937e180 ! 1: STQF_I - %f20, [0x0180, %r31] |
| 4491 | ba,a .+8 |
| 4492 | jmpl %r27+0, %r27 |
| 4493 | .word 0xe89fe170 ! 57: LDDA_I ldda [%r31, + 0x0170] %asi, %r20 |
| 4494 | ibp_40_39: |
| 4495 | nop |
| 4496 | ta T_CHANGE_NONHPRIV |
| 4497 | .word 0xc3ec4026 ! 58: PREFETCHA_R prefetcha [%r17, %r6] 0x01, #one_read |
| 4498 | nop |
| 4499 | ta T_CHANGE_HPRIV ! macro |
| 4500 | donret_40_40: |
| 4501 | rd %pc, %r12 |
| 4502 | mov HIGHVA_HIGHNUM, %r10 |
| 4503 | sllx %r10, 32, %r10 |
| 4504 | or %r12, %r10, %r12 |
| 4505 | add %r12, (donretarg_40_40-donret_40_40+4), %r12 |
| 4506 | add %r12, 0x4, %r11 ! seq tnpc |
| 4507 | andn %r12, %r10, %r12 ! low VA tpc |
| 4508 | wrpr %g0, 0x2, %tl |
| 4509 | wrpr %g0, %r12, %tpc |
| 4510 | wrpr %g0, %r11, %tnpc |
| 4511 | set (0x00720d00 | (16 << 24)), %r13 |
| 4512 | and %r12, 0xfff, %r14 |
| 4513 | sllx %r14, 32, %r14 |
| 4514 | or %r13, %r14, %r20 |
| 4515 | wrpr %r20, %g0, %tstate |
| 4516 | wrhpr %g0, 0x179f, %htstate |
| 4517 | ta T_CHANGE_NONPRIV ! rand=0 (40) |
| 4518 | ldx [%r12+%r0], %g1 |
| 4519 | retry |
| 4520 | donretarg_40_40: |
| 4521 | .word 0x2cccc001 ! 59: BRGZ brgz,a,pt %r19,<label_0xcc001> |
| 4522 | memptr_40_41: |
| 4523 | set 0x60540000, %r31 |
| 4524 | .word 0x8580bab6 ! 60: WRCCR_I wr %r2, 0x1ab6, %ccr |
| 4525 | nop |
| 4526 | mov 0x80, %g3 |
| 4527 | stxa %r20, [%r0] ASI_LSU_CONTROL |
| 4528 | stxa %g3, [%g3] 0x5f |
| 4529 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 4530 | .word 0xa753c000 ! 62: RDPR_FQ <illegal instruction> |
| 4531 | fbo skip_40_42 |
| 4532 | brlez,pt %r19, skip_40_42 |
| 4533 | .align 1024 |
| 4534 | skip_40_42: |
| 4535 | .word 0x9ba4c9d4 ! 63: FDIVd fdivd %f50, %f20, %f44 |
| 4536 | fbn skip_40_43 |
| 4537 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 4538 | brlz,pn %r19, skip_40_43 |
| 4539 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 4540 | .align 1024 |
| 4541 | skip_40_43: |
| 4542 | .word 0xc36fe1fc ! 64: PREFETCH_I prefetch [%r31 + 0x01fc], #one_read |
| 4543 | .word 0xe19fc3e0 ! 65: LDDFA_R ldda [%r31, %r0], %f16 |
| 4544 | nop |
| 4545 | ta T_CHANGE_HPRIV |
| 4546 | mov 0x40+1, %r10 |
| 4547 | set sync_thr_counter5, %r23 |
| 4548 | #ifndef SPC |
| 4549 | ldxa [%g0]0x63, %o1 |
| 4550 | and %o1, 0x38, %o1 |
| 4551 | add %o1, %r23, %r23 |
| 4552 | sllx %o1, 5, %o3 !(CID*256) |
| 4553 | #endif |
| 4554 | cas [%r23],%g0,%r10 !lock |
| 4555 | brnz %r10, cwq_40_44 |
| 4556 | rd %asi, %r12 |
| 4557 | wr %g0, 0x40, %asi |
| 4558 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 4559 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 4560 | cmp %l1, 1 |
| 4561 | bne cwq_40_44 |
| 4562 | set CWQ_BASE, %l6 |
| 4563 | #ifndef SPC |
| 4564 | add %l6, %o3, %l6 |
| 4565 | #endif |
| 4566 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 4567 | best_set_reg(0x20610090, %l1, %l2) !# Control Word |
| 4568 | sllx %l2, 32, %l2 |
| 4569 | stx %l2, [%l6 + 0x0] |
| 4570 | membar #Sync |
| 4571 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 4572 | sub %l2, 0x40, %l2 |
| 4573 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 4574 | wr %r12, %g0, %asi |
| 4575 | st %g0, [%r23] |
| 4576 | cwq_40_44: |
| 4577 | ta T_CHANGE_NONHPRIV |
| 4578 | .word 0x9b414000 ! 66: RDPC rd %pc, %r13 |
| 4579 | mondo_40_45: |
| 4580 | nop |
| 4581 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 4582 | ta T_CHANGE_PRIV |
| 4583 | stxa %r19, [%r0+0x3c8] %asi |
| 4584 | .word 0x9d914013 ! 67: WRPR_WSTATE_R wrpr %r5, %r19, %wstate |
| 4585 | .word 0xa7a00167 ! 68: FABSq dis not found |
| 4586 | |
| 4587 | .word 0x9190c00d ! 69: WRPR_PIL_R wrpr %r3, %r13, %pil |
| 4588 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 4589 | #if (defined SPC || defined CMP) |
| 4590 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_40_49)+24, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 4591 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_40_49)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 4592 | xir_40_49: |
| 4593 | #else |
| 4594 | #if (defined FC) |
| 4595 | !! Generate XIR via RESET_GEN register |
| 4596 | ta T_CHANGE_HPRIV |
| 4597 | rdpr %pstate, %r18 |
| 4598 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 4599 | wrpr %r18, %pstate |
| 4600 | #ifndef XIR_RND_CORES |
| 4601 | ldxa [%g0] 0x63, %o1 |
| 4602 | mov 1, %r18 |
| 4603 | sllx %r18, %o1, %r18 |
| 4604 | #endif |
| 4605 | mov 0x30, %r19 |
| 4606 | setx 0x8900000808, %r16, %r17 |
| 4607 | mov 0x2, %r16 |
| 4608 | xir_40_49: |
| 4609 | stxa %r18, [%r19] 0x41 |
| 4610 | stx %r16, [%r17] |
| 4611 | #endif |
| 4612 | #endif |
| 4613 | .word 0xa9853678 ! 71: WR_SET_SOFTINT_I wr %r20, 0x1678, %set_softint |
| 4614 | #if (defined SPC || defined CMP1) |
| 4615 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_50) + 0, 16, 16)) -> intp(5,0,27,,,,,1) |
| 4616 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_40_50)&0xffffffff) + 8, 16, 16)) -> intp(7,0,13,,,,,1) |
| 4617 | #else |
| 4618 | set 0xa690fcb6, %r28 |
| 4619 | #if (MAX_THREADS == 8) |
| 4620 | and %r28, 0x7ff, %r28 |
| 4621 | #endif |
| 4622 | stxa %r28, [%g0] 0x73 |
| 4623 | #endif |
| 4624 | .word 0xa9b404d0 ! 1: FCMPNE32 fcmpne32 %d16, %d16, %r20 |
| 4625 | intvec_40_50: |
| 4626 | .word 0x39400001 ! 72: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 4627 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 4628 | nop |
| 4629 | mov 0x80, %g3 |
| 4630 | stxa %r12, [%r0] ASI_LSU_CONTROL |
| 4631 | stxa %g3, [%g3] 0x57 |
| 4632 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 4633 | nop |
| 4634 | ta T_CHANGE_HPRIV |
| 4635 | mov 0x40, %r10 |
| 4636 | set sync_thr_counter6, %r23 |
| 4637 | #ifndef SPC |
| 4638 | ldxa [%g0]0x63, %o1 |
| 4639 | and %o1, 0x38, %o1 |
| 4640 | add %o1, %r23, %r23 |
| 4641 | #endif |
| 4642 | cas [%r23],%g0,%r10 !lock |
| 4643 | brnz %r10, sma_40_52 |
| 4644 | rd %asi, %r12 |
| 4645 | wr %g0, 0x40, %asi |
| 4646 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4647 | set 0x00021fff, %g1 |
| 4648 | stxa %g1, [%g0 + 0x80] %asi |
| 4649 | wr %r12, %g0, %asi |
| 4650 | st %g0, [%r23] |
| 4651 | sma_40_52: |
| 4652 | ta T_CHANGE_NONHPRIV |
| 4653 | .word 0xe5e7e011 ! 75: CASA_R casa [%r31] %asi, %r17, %r18 |
| 4654 | .word 0x91940014 ! 76: WRPR_PIL_R wrpr %r16, %r20, %pil |
| 4655 | pmu_40_54: |
| 4656 | nop |
| 4657 | setx 0xffffffb1ffffffa8, %g1, %g7 |
| 4658 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 4659 | fpinit_40_55: |
| 4660 | nop |
| 4661 | setx fp_data_quads, %r19, %r20 |
| 4662 | ldd [%r20], %f0 |
| 4663 | ldd [%r20+8], %f4 |
| 4664 | ld [%r20+16], %fsr |
| 4665 | ld [%r20+24], %r19 |
| 4666 | wr %r19, %g0, %gsr |
| 4667 | .word 0x91a009a4 ! 78: FDIVs fdivs %f0, %f4, %f8 |
| 4668 | jmptr_40_56: |
| 4669 | nop |
| 4670 | best_set_reg(0xe1200000, %r20, %r27) |
| 4671 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 4672 | nop |
| 4673 | mov 0x80, %g3 |
| 4674 | stxa %r20, [%r0] ASI_LSU_CONTROL |
| 4675 | stxa %g3, [%g3] 0x57 |
| 4676 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 4677 | .word 0xa1b500f2 ! 81: EDGE16LN edge16ln %r20, %r18, %r16 |
| 4678 | #if (defined SPC || defined CMP1) |
| 4679 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_58) + 32, 16, 16)) -> intp(0,0,23,,,,,1) |
| 4680 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_40_58)&0xffffffff) + 24, 16, 16)) -> intp(3,0,12,,,,,1) |
| 4681 | #else |
| 4682 | set 0xe590a6f0, %r28 |
| 4683 | #if (MAX_THREADS == 8) |
| 4684 | and %r28, 0x7ff, %r28 |
| 4685 | #endif |
| 4686 | stxa %r28, [%g0] 0x73 |
| 4687 | #endif |
| 4688 | .word 0x9f803b73 ! 1: SIR sir 0x1b73 |
| 4689 | intvec_40_58: |
| 4690 | .word 0x39400001 ! 82: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 4691 | nop |
| 4692 | ta T_CHANGE_HPRIV |
| 4693 | mov 0x40, %r10 |
| 4694 | set sync_thr_counter6, %r23 |
| 4695 | #ifndef SPC |
| 4696 | ldxa [%g0]0x63, %o1 |
| 4697 | and %o1, 0x38, %o1 |
| 4698 | add %o1, %r23, %r23 |
| 4699 | #endif |
| 4700 | cas [%r23],%g0,%r10 !lock |
| 4701 | brnz %r10, sma_40_59 |
| 4702 | rd %asi, %r12 |
| 4703 | wr %g0, 0x40, %asi |
| 4704 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4705 | set 0x000e1fff, %g1 |
| 4706 | stxa %g1, [%g0 + 0x80] %asi |
| 4707 | wr %r12, %g0, %asi |
| 4708 | st %g0, [%r23] |
| 4709 | sma_40_59: |
| 4710 | ta T_CHANGE_NONHPRIV |
| 4711 | .word 0xe5e7e013 ! 83: CASA_R casa [%r31] %asi, %r19, %r18 |
| 4712 | fpinit_40_60: |
| 4713 | nop |
| 4714 | setx fp_data_quads, %r19, %r20 |
| 4715 | ldd [%r20], %f0 |
| 4716 | ldd [%r20+8], %f4 |
| 4717 | ld [%r20+16], %fsr |
| 4718 | ld [%r20+24], %r19 |
| 4719 | wr %r19, %g0, %gsr |
| 4720 | .word 0x89a009c4 ! 84: FDIVd fdivd %f0, %f4, %f4 |
| 4721 | .word 0x87802088 ! 85: WRASI_I wr %r0, 0x0088, %asi |
| 4722 | .word 0xc19fc2c0 ! 86: LDDFA_R ldda [%r31, %r0], %f0 |
| 4723 | splash_lsu_40_61: |
| 4724 | nop |
| 4725 | ta T_CHANGE_HPRIV |
| 4726 | set 0xc65b759f, %r2 |
| 4727 | mov 0x1, %r1 |
| 4728 | sllx %r1, 32, %r1 |
| 4729 | or %r1, %r2, %r2 |
| 4730 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4731 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4732 | splash_lsu_40_62: |
| 4733 | nop |
| 4734 | ta T_CHANGE_HPRIV |
| 4735 | set 0xa69cd245, %r2 |
| 4736 | mov 0x6, %r1 |
| 4737 | sllx %r1, 32, %r1 |
| 4738 | or %r1, %r2, %r2 |
| 4739 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4740 | ta T_CHANGE_NONHPRIV |
| 4741 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4742 | splash_cmpr_40_63: |
| 4743 | mov 0, %r18 |
| 4744 | sllx %r18, 63, %r18 |
| 4745 | rd %tick, %r17 |
| 4746 | add %r17, 0x100, %r17 |
| 4747 | or %r17, %r18, %r17 |
| 4748 | ta T_CHANGE_HPRIV |
| 4749 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 4750 | .word 0xaf800011 ! 89: WR_TICK_CMPR_REG_R wr %r0, %r17, %- |
| 4751 | nop |
| 4752 | mov 0x80, %g3 |
| 4753 | .word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1> |
| 4754 | stxa %g3, [%g3] 0x57 |
| 4755 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 4756 | splash_tba_40_64: |
| 4757 | nop |
| 4758 | ta T_CHANGE_PRIV |
| 4759 | set 0x120000, %r12 |
| 4760 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 4761 | dvapa_40_65: |
| 4762 | nop |
| 4763 | ta T_CHANGE_HPRIV |
| 4764 | mov 0xe75, %r20 |
| 4765 | mov 0x1c, %r19 |
| 4766 | sllx %r20, 23, %r20 |
| 4767 | or %r19, %r20, %r19 |
| 4768 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 4769 | mov 0x38, %r18 |
| 4770 | stxa %r31, [%r18]0x58 |
| 4771 | ta T_CHANGE_NONHPRIV |
| 4772 | .word 0xe49fe1c0 ! 92: LDDA_I ldda [%r31, + 0x01c0] %asi, %r18 |
| 4773 | splash_lsu_40_66: |
| 4774 | nop |
| 4775 | ta T_CHANGE_HPRIV |
| 4776 | set 0x98e5fef9, %r2 |
| 4777 | mov 0x7, %r1 |
| 4778 | sllx %r1, 32, %r1 |
| 4779 | or %r1, %r2, %r2 |
| 4780 | .word 0x21400001 ! 1: FBPN fbn,a,pn %fcc0, <label_0x1> |
| 4781 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4782 | ta T_CHANGE_NONHPRIV |
| 4783 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4784 | ibp_40_67: |
| 4785 | nop |
| 4786 | .word 0xe5e7e00d ! 94: CASA_R casa [%r31] %asi, %r13, %r18 |
| 4787 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 4788 | nop |
| 4789 | ta T_CHANGE_HPRIV |
| 4790 | mov 0x40, %r10 |
| 4791 | set sync_thr_counter6, %r23 |
| 4792 | #ifndef SPC |
| 4793 | ldxa [%g0]0x63, %o1 |
| 4794 | and %o1, 0x38, %o1 |
| 4795 | add %o1, %r23, %r23 |
| 4796 | #endif |
| 4797 | cas [%r23],%g0,%r10 !lock |
| 4798 | brnz %r10, sma_40_68 |
| 4799 | rd %asi, %r12 |
| 4800 | wr %g0, 0x40, %asi |
| 4801 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4802 | set 0x001a1fff, %g1 |
| 4803 | stxa %g1, [%g0 + 0x80] %asi |
| 4804 | wr %r12, %g0, %asi |
| 4805 | st %g0, [%r23] |
| 4806 | sma_40_68: |
| 4807 | ta T_CHANGE_NONHPRIV |
| 4808 | .word 0xe5e7e014 ! 96: CASA_R casa [%r31] %asi, %r20, %r18 |
| 4809 | #if (defined SPC || defined CMP) |
| 4810 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_40_69)+8, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 4811 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_40_69)&0xffffffff) + 40, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 4812 | xir_40_69: |
| 4813 | #else |
| 4814 | #if (defined FC) |
| 4815 | !! Generate XIR via RESET_GEN register |
| 4816 | ta T_CHANGE_HPRIV |
| 4817 | rdpr %pstate, %r18 |
| 4818 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 4819 | wrpr %r18, %pstate |
| 4820 | #ifndef XIR_RND_CORES |
| 4821 | ldxa [%g0] 0x63, %o1 |
| 4822 | mov 1, %r18 |
| 4823 | sllx %r18, %o1, %r18 |
| 4824 | #endif |
| 4825 | mov 0x30, %r19 |
| 4826 | setx 0x8900000808, %r16, %r17 |
| 4827 | mov 0x2, %r16 |
| 4828 | xir_40_69: |
| 4829 | stxa %r18, [%r19] 0x41 |
| 4830 | stx %r16, [%r17] |
| 4831 | #endif |
| 4832 | #endif |
| 4833 | .word 0xa9846428 ! 97: WR_SET_SOFTINT_I wr %r17, 0x0428, %set_softint |
| 4834 | #if (defined SPC || defined CMP1) |
| 4835 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_70) + 24, 16, 16)) -> intp(6,0,25,,,,,1) |
| 4836 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_40_70)&0xffffffff) + 32, 16, 16)) -> intp(7,0,9,,,,,1) |
| 4837 | #else |
| 4838 | set 0xc5c0a343, %r28 |
| 4839 | #if (MAX_THREADS == 8) |
| 4840 | and %r28, 0x7ff, %r28 |
| 4841 | #endif |
| 4842 | stxa %r28, [%g0] 0x73 |
| 4843 | #endif |
| 4844 | intvec_40_70: |
| 4845 | .word 0xa7a509d4 ! 98: FDIVd fdivd %f20, %f20, %f50 |
| 4846 | fpinit_40_71: |
| 4847 | nop |
| 4848 | setx fp_data_quads, %r19, %r20 |
| 4849 | ldd [%r20], %f0 |
| 4850 | ldd [%r20+8], %f4 |
| 4851 | ld [%r20+16], %fsr |
| 4852 | ld [%r20+24], %r19 |
| 4853 | wr %r19, %g0, %gsr |
| 4854 | .word 0x89a009a4 ! 99: FDIVs fdivs %f0, %f4, %f4 |
| 4855 | splash_lsu_40_72: |
| 4856 | nop |
| 4857 | ta T_CHANGE_HPRIV |
| 4858 | set 0xf9ce3466, %r2 |
| 4859 | mov 0x1, %r1 |
| 4860 | sllx %r1, 32, %r1 |
| 4861 | or %r1, %r2, %r2 |
| 4862 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4863 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4864 | .word 0xa7b240f3 ! 101: EDGE16LN edge16ln %r9, %r19, %r19 |
| 4865 | nop |
| 4866 | ta T_CHANGE_HPRIV |
| 4867 | mov 0x40, %r10 |
| 4868 | set sync_thr_counter6, %r23 |
| 4869 | #ifndef SPC |
| 4870 | ldxa [%g0]0x63, %o1 |
| 4871 | and %o1, 0x38, %o1 |
| 4872 | add %o1, %r23, %r23 |
| 4873 | #endif |
| 4874 | cas [%r23],%g0,%r10 !lock |
| 4875 | brnz %r10, sma_40_74 |
| 4876 | rd %asi, %r12 |
| 4877 | wr %g0, 0x40, %asi |
| 4878 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 4879 | set 0x001a1fff, %g1 |
| 4880 | stxa %g1, [%g0 + 0x80] %asi |
| 4881 | wr %r12, %g0, %asi |
| 4882 | st %g0, [%r23] |
| 4883 | sma_40_74: |
| 4884 | ta T_CHANGE_NONHPRIV |
| 4885 | .word 0xd7e7e00c ! 102: CASA_R casa [%r31] %asi, %r12, %r11 |
| 4886 | nop |
| 4887 | mov 0x80, %g3 |
| 4888 | .word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1> |
| 4889 | stxa %g3, [%g3] 0x5f |
| 4890 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 4891 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 4892 | iaw_40_76: |
| 4893 | nop |
| 4894 | ta T_CHANGE_HPRIV |
| 4895 | mov 8, %r18 |
| 4896 | rd %asi, %r12 |
| 4897 | wr %r0, 0x41, %asi |
| 4898 | set sync_thr_counter4, %r23 |
| 4899 | #ifndef SPC |
| 4900 | ldxa [%g0]0x63, %r8 |
| 4901 | and %r8, 0x38, %r8 ! Core ID |
| 4902 | add %r8, %r23, %r23 |
| 4903 | #else |
| 4904 | mov 0, %r8 |
| 4905 | #endif |
| 4906 | mov 0x40, %r16 |
| 4907 | iaw_startwait40_76: |
| 4908 | cas [%r23],%g0,%r16 !lock |
| 4909 | brz,a %r16, continue_iaw_40_76 |
| 4910 | mov (~0x40&0xf0), %r16 |
| 4911 | ld [%r23], %r16 |
| 4912 | iaw_wait40_76: |
| 4913 | brnz %r16, iaw_wait40_76 |
| 4914 | ld [%r23], %r16 |
| 4915 | ba iaw_startwait40_76 |
| 4916 | mov 0x40, %r16 |
| 4917 | continue_iaw_40_76: |
| 4918 | sllx %r16, %r8, %r16 !Mask for my core only |
| 4919 | ldxa [0x58]%asi, %r17 !Running_status |
| 4920 | wait_for_stat_40_76: |
| 4921 | ldxa [0x50]%asi, %r13 !Running_rw |
| 4922 | cmp %r13, %r17 |
| 4923 | bne,a %xcc, wait_for_stat_40_76 |
| 4924 | ldxa [0x58]%asi, %r17 !Running_status |
| 4925 | stxa %r16, [0x68]%asi !Park (W1C) |
| 4926 | ldxa [0x50]%asi, %r14 !Running_rw |
| 4927 | wait_for_iaw_40_76: |
| 4928 | ldxa [0x58]%asi, %r17 !Running_status |
| 4929 | cmp %r14, %r17 |
| 4930 | bne,a %xcc, wait_for_iaw_40_76 |
| 4931 | ldxa [0x50]%asi, %r14 !Running_rw |
| 4932 | iaw_doit40_76: |
| 4933 | mov 0x38, %r18 |
| 4934 | iaw2_40_76: |
| 4935 | rdpr %tba, %r19 |
| 4936 | mov 0x21, %r20 |
| 4937 | sllx %r20, 5, %r20 |
| 4938 | add %r20, %r19, %r19 |
| 4939 | stxa %r19, [%r18]0x50 |
| 4940 | stxa %r16, [0x60] %asi ! Unpark (W1S) |
| 4941 | st %g0, [%r23] !clear lock |
| 4942 | wr %r0, %r12, %asi ! restore %asi |
| 4943 | ta T_CHANGE_NONHPRIV |
| 4944 | .word 0xc1bfde00 ! 105: STDFA_R stda %f0, [%r0, %r31] |
| 4945 | splash_lsu_40_77: |
| 4946 | nop |
| 4947 | ta T_CHANGE_HPRIV |
| 4948 | set 0xa9a409f2, %r2 |
| 4949 | mov 0x3, %r1 |
| 4950 | sllx %r1, 32, %r1 |
| 4951 | or %r1, %r2, %r2 |
| 4952 | .word 0x20800001 ! 1: BN bn,a <label_0x1> |
| 4953 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4954 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4955 | .word 0xe1bfc2c0 ! 107: STDFA_R stda %f16, [%r0, %r31] |
| 4956 | .word 0x9194c00d ! 108: WRPR_PIL_R wrpr %r19, %r13, %pil |
| 4957 | splash_lsu_40_79: |
| 4958 | nop |
| 4959 | ta T_CHANGE_HPRIV |
| 4960 | set 0xc35f7384, %r2 |
| 4961 | mov 0x7, %r1 |
| 4962 | sllx %r1, 32, %r1 |
| 4963 | or %r1, %r2, %r2 |
| 4964 | .word 0x3f400001 ! 1: FBPO fbo,a,pn %fcc0, <label_0x1> |
| 4965 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 4966 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4967 | .word 0xe1bfc2c0 ! 110: STDFA_R stda %f16, [%r0, %r31] |
| 4968 | ba,a skip_40_80 |
| 4969 | fbo,a,pn %fcc0, skip_40_80 |
| 4970 | .align 128 |
| 4971 | skip_40_80: |
| 4972 | .word 0x39400001 ! 111: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 4973 | .word 0xe1bfd920 ! 112: STDFA_R stda %f16, [%r0, %r31] |
| 4974 | rd %tick, %r28 |
| 4975 | #if (MAX_THREADS == 8) |
| 4976 | sethi %hi(0x33800), %r27 |
| 4977 | #else |
| 4978 | sethi %hi(0x30000), %r27 |
| 4979 | #endif |
| 4980 | andn %r28, %r27, %r28 |
| 4981 | ta T_CHANGE_HPRIV |
| 4982 | stxa %r28, [%g0] 0x73 |
| 4983 | intvec_40_81: |
| 4984 | .word 0x39400001 ! 113: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 4985 | .word 0xe1bfe100 ! 114: STDFA_I stda %f16, [0x0100, %r31] |
| 4986 | nop |
| 4987 | mov 0x80, %g3 |
| 4988 | .word 0x3d400001 ! 1: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 4989 | stxa %g3, [%g3] 0x5f |
| 4990 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 4991 | jmptr_40_82: |
| 4992 | nop |
| 4993 | best_set_reg(0xe1200000, %r20, %r27) |
| 4994 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 4995 | splash_tba_40_83: |
| 4996 | nop |
| 4997 | ta T_CHANGE_PRIV |
| 4998 | setx 0x0000000400380000, %r11, %r12 |
| 4999 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 5000 | .word 0x91944012 ! 118: WRPR_PIL_R wrpr %r17, %r18, %pil |
| 5001 | #if (defined SPC || defined CMP) |
| 5002 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_40_85)+0, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 5003 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_40_85)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 5004 | xir_40_85: |
| 5005 | #else |
| 5006 | #if (defined FC) |
| 5007 | !! Generate XIR via RESET_GEN register |
| 5008 | ta T_CHANGE_HPRIV |
| 5009 | rdpr %pstate, %r18 |
| 5010 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 5011 | wrpr %r18, %pstate |
| 5012 | #ifndef XIR_RND_CORES |
| 5013 | ldxa [%g0] 0x63, %o1 |
| 5014 | mov 1, %r18 |
| 5015 | sllx %r18, %o1, %r18 |
| 5016 | #endif |
| 5017 | mov 0x30, %r19 |
| 5018 | setx 0x8900000808, %r16, %r17 |
| 5019 | mov 0x2, %r16 |
| 5020 | xir_40_85: |
| 5021 | stxa %r18, [%r19] 0x41 |
| 5022 | stx %r16, [%r17] |
| 5023 | #endif |
| 5024 | #endif |
| 5025 | .word 0xa980b7b3 ! 119: WR_SET_SOFTINT_I wr %r2, 0x17b3, %set_softint |
| 5026 | cwp_40_86: |
| 5027 | set user_data_start, %o7 |
| 5028 | .word 0x93902002 ! 120: WRPR_CWP_I wrpr %r0, 0x0002, %cwp |
| 5029 | nop |
| 5030 | mov 0x80, %g3 |
| 5031 | stxa %r20, [%r0] ASI_LSU_CONTROL |
| 5032 | stxa %g3, [%g3] 0x57 |
| 5033 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 5034 | nop |
| 5035 | ta T_CHANGE_HPRIV ! macro |
| 5036 | donret_40_87: |
| 5037 | rd %pc, %r12 |
| 5038 | mov HIGHVA_HIGHNUM, %r10 |
| 5039 | sllx %r10, 32, %r10 |
| 5040 | or %r12, %r10, %r12 |
| 5041 | add %r12, (donretarg_40_87-donret_40_87), %r12 |
| 5042 | add %r12, 0x4, %r11 ! seq tnpc |
| 5043 | andn %r11, %r10, %r11 ! low VA tnpc |
| 5044 | wrpr %g0, 0x1, %tl |
| 5045 | wrpr %g0, %r12, %tpc |
| 5046 | wrpr %g0, %r11, %tnpc |
| 5047 | set (0x001cb200 | (0x4f << 24)), %r13 |
| 5048 | and %r12, 0xfff, %r14 |
| 5049 | sllx %r14, 32, %r14 |
| 5050 | or %r13, %r14, %r20 |
| 5051 | wrpr %r20, %g0, %tstate |
| 5052 | wrhpr %g0, 0x155, %htstate |
| 5053 | ta T_CHANGE_NONPRIV ! rand=0 (40) |
| 5054 | ldx [%r11+%r0], %g1 |
| 5055 | done |
| 5056 | donretarg_40_87: |
| 5057 | .word 0xe66fe0b6 ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x00b6] |
| 5058 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 5059 | .word 0x9b45c000 ! 124: RD_TICK_CMPR_REG rd %-, %r13 |
| 5060 | .word 0xe19fd960 ! 125: LDDFA_R ldda [%r31, %r0], %f16 |
| 5061 | nop |
| 5062 | ta T_CHANGE_HPRIV |
| 5063 | mov 0x40+1, %r10 |
| 5064 | set sync_thr_counter5, %r23 |
| 5065 | #ifndef SPC |
| 5066 | ldxa [%g0]0x63, %o1 |
| 5067 | and %o1, 0x38, %o1 |
| 5068 | add %o1, %r23, %r23 |
| 5069 | sllx %o1, 5, %o3 !(CID*256) |
| 5070 | #endif |
| 5071 | cas [%r23],%g0,%r10 !lock |
| 5072 | brnz %r10, cwq_40_89 |
| 5073 | rd %asi, %r12 |
| 5074 | wr %g0, 0x40, %asi |
| 5075 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 5076 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 5077 | cmp %l1, 1 |
| 5078 | bne cwq_40_89 |
| 5079 | set CWQ_BASE, %l6 |
| 5080 | #ifndef SPC |
| 5081 | add %l6, %o3, %l6 |
| 5082 | #endif |
| 5083 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 5084 | best_set_reg(0x20610080, %l1, %l2) !# Control Word |
| 5085 | sllx %l2, 32, %l2 |
| 5086 | stx %l2, [%l6 + 0x0] |
| 5087 | membar #Sync |
| 5088 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 5089 | sub %l2, 0x40, %l2 |
| 5090 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 5091 | wr %r12, %g0, %asi |
| 5092 | st %g0, [%r23] |
| 5093 | cwq_40_89: |
| 5094 | ta T_CHANGE_NONHPRIV |
| 5095 | .word 0x93414000 ! 126: RDPC rd %pc, %r9 |
| 5096 | .word 0x93a00164 ! 127: FABSq dis not found |
| 5097 | |
| 5098 | #if (defined SPC || defined CMP) |
| 5099 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_40_91)+24, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 5100 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_40_91)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x40),1,3,,,,,1) |
| 5101 | xir_40_91: |
| 5102 | #else |
| 5103 | #if (defined FC) |
| 5104 | !! Generate XIR via RESET_GEN register |
| 5105 | ta T_CHANGE_HPRIV |
| 5106 | rdpr %pstate, %r18 |
| 5107 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 5108 | wrpr %r18, %pstate |
| 5109 | #ifndef XIR_RND_CORES |
| 5110 | ldxa [%g0] 0x63, %o1 |
| 5111 | mov 1, %r18 |
| 5112 | sllx %r18, %o1, %r18 |
| 5113 | #endif |
| 5114 | mov 0x30, %r19 |
| 5115 | setx 0x8900000808, %r16, %r17 |
| 5116 | mov 0x2, %r16 |
| 5117 | xir_40_91: |
| 5118 | stxa %r18, [%r19] 0x41 |
| 5119 | stx %r16, [%r17] |
| 5120 | #endif |
| 5121 | #endif |
| 5122 | .word 0xa98533d8 ! 128: WR_SET_SOFTINT_I wr %r20, 0x13d8, %set_softint |
| 5123 | memptr_40_92: |
| 5124 | set 0x60740000, %r31 |
| 5125 | .word 0x85846400 ! 129: WRCCR_I wr %r17, 0x0400, %ccr |
| 5126 | rd %tick, %r28 |
| 5127 | #if (MAX_THREADS == 8) |
| 5128 | sethi %hi(0x33800), %r27 |
| 5129 | #else |
| 5130 | sethi %hi(0x30000), %r27 |
| 5131 | #endif |
| 5132 | andn %r28, %r27, %r28 |
| 5133 | ta T_CHANGE_HPRIV |
| 5134 | stxa %r28, [%g0] 0x73 |
| 5135 | intvec_40_93: |
| 5136 | .word 0xc36c6283 ! 130: PREFETCH_I prefetch [%r17 + 0x0283], #one_read |
| 5137 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 5138 | memptr_40_95: |
| 5139 | set 0x60740000, %r31 |
| 5140 | .word 0x8584fc58 ! 132: WRCCR_I wr %r19, 0x1c58, %ccr |
| 5141 | splash_hpstate_40_96: |
| 5142 | .word 0x30800001 ! 1: BA ba,a <label_0x1> |
| 5143 | .word 0x81982b9d ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x0b9d, %hpstate |
| 5144 | jmptr_40_97: |
| 5145 | nop |
| 5146 | best_set_reg(0xe1200000, %r20, %r27) |
| 5147 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 5148 | fbge skip_40_98 |
| 5149 | stxa %r9, [%r0] ASI_LSU_CONTROL |
| 5150 | .word 0xa3b304cb ! 1: FCMPNE32 fcmpne32 %d12, %d42, %r17 |
| 5151 | stxa %r9, [%r0] ASI_LSU_CONTROL |
| 5152 | .align 128 |
| 5153 | skip_40_98: |
| 5154 | .word 0xc32fc000 ! 135: STXFSR_R st-sfr %f1, [%r0, %r31] |
| 5155 | .word 0x8d902511 ! 136: WRPR_PSTATE_I wrpr %r0, 0x0511, %pstate |
| 5156 | .word 0xa1a00171 ! 137: FABSq dis not found |
| 5157 | |
| 5158 | nop |
| 5159 | ta T_CHANGE_HPRIV |
| 5160 | mov 0x40, %r10 |
| 5161 | set sync_thr_counter6, %r23 |
| 5162 | #ifndef SPC |
| 5163 | ldxa [%g0]0x63, %o1 |
| 5164 | and %o1, 0x38, %o1 |
| 5165 | add %o1, %r23, %r23 |
| 5166 | #endif |
| 5167 | cas [%r23],%g0,%r10 !lock |
| 5168 | brnz %r10, sma_40_101 |
| 5169 | rd %asi, %r12 |
| 5170 | wr %g0, 0x40, %asi |
| 5171 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5172 | set 0x00121fff, %g1 |
| 5173 | stxa %g1, [%g0 + 0x80] %asi |
| 5174 | wr %r12, %g0, %asi |
| 5175 | st %g0, [%r23] |
| 5176 | sma_40_101: |
| 5177 | ta T_CHANGE_NONHPRIV |
| 5178 | .word 0xe1e7e008 ! 138: CASA_R casa [%r31] %asi, %r8, %r16 |
| 5179 | .word 0xa3b480e5 ! 139: EDGE16LN edge16ln %r18, %r5, %r17 |
| 5180 | splash_lsu_40_103: |
| 5181 | nop |
| 5182 | ta T_CHANGE_HPRIV |
| 5183 | set 0x17ac0964, %r2 |
| 5184 | mov 0x4, %r1 |
| 5185 | sllx %r1, 32, %r1 |
| 5186 | or %r1, %r2, %r2 |
| 5187 | .word 0x2d400001 ! 1: FBPG fbg,a,pn %fcc0, <label_0x1> |
| 5188 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5189 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5190 | .word 0xa5688012 ! 141: SDIVX_R sdivx %r2, %r18, %r18 |
| 5191 | .word 0xc19fe000 ! 142: LDDFA_I ldda [%r31, 0x0000], %f0 |
| 5192 | .word 0x91944004 ! 143: WRPR_PIL_R wrpr %r17, %r4, %pil |
| 5193 | splash_hpstate_40_105: |
| 5194 | ta T_CHANGE_NONHPRIV |
| 5195 | .word 0x81983c15 ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x1c15, %hpstate |
| 5196 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 5197 | nop |
| 5198 | ta T_CHANGE_HPRIV |
| 5199 | mov 0x40, %r10 |
| 5200 | set sync_thr_counter6, %r23 |
| 5201 | #ifndef SPC |
| 5202 | ldxa [%g0]0x63, %o1 |
| 5203 | and %o1, 0x38, %o1 |
| 5204 | add %o1, %r23, %r23 |
| 5205 | #endif |
| 5206 | cas [%r23],%g0,%r10 !lock |
| 5207 | brnz %r10, sma_40_107 |
| 5208 | rd %asi, %r12 |
| 5209 | wr %g0, 0x40, %asi |
| 5210 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5211 | set 0x00121fff, %g1 |
| 5212 | stxa %g1, [%g0 + 0x80] %asi |
| 5213 | wr %r12, %g0, %asi |
| 5214 | st %g0, [%r23] |
| 5215 | sma_40_107: |
| 5216 | ta T_CHANGE_NONHPRIV |
| 5217 | .word 0xd1e7e013 ! 146: CASA_R casa [%r31] %asi, %r19, %r8 |
| 5218 | fpinit_40_108: |
| 5219 | nop |
| 5220 | setx fp_data_quads, %r19, %r20 |
| 5221 | ldd [%r20], %f0 |
| 5222 | ldd [%r20+8], %f4 |
| 5223 | ld [%r20+16], %fsr |
| 5224 | ld [%r20+24], %r19 |
| 5225 | wr %r19, %g0, %gsr |
| 5226 | .word 0x91a009c4 ! 147: FDIVd fdivd %f0, %f4, %f8 |
| 5227 | intveclr_40_109: |
| 5228 | nop |
| 5229 | ta T_CHANGE_HPRIV |
| 5230 | setx 0xbc2e70680e78965b, %r1, %r28 |
| 5231 | stxa %r28, [%g0] 0x72 |
| 5232 | ta T_CHANGE_NONHPRIV |
| 5233 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 5234 | brcommon3_40_110: |
| 5235 | nop |
| 5236 | setx common_target, %r12, %r27 |
| 5237 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 5238 | ba,a .+12 |
| 5239 | .word 0xd06fe0e0 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x00e0] |
| 5240 | ba,a .+8 |
| 5241 | jmpl %r27+0, %r27 |
| 5242 | .word 0xd0bfc028 ! 149: STDA_R stda %r8, [%r31 + %r8] 0x01 |
| 5243 | .word 0x3a800001 ! 1: BCC bcc,a <label_0x1> |
| 5244 | .word 0x8d903212 ! 150: WRPR_PSTATE_I wrpr %r0, 0x1212, %pstate |
| 5245 | nop |
| 5246 | nop |
| 5247 | ta T_CHANGE_PRIV |
| 5248 | wrpr %g0, %g0, %gl |
| 5249 | nop |
| 5250 | nop |
| 5251 | .text |
| 5252 | setx join_lbl_0_0, %g1, %g2 |
| 5253 | jmp %g2 |
| 5254 | nop |
| 5255 | fork_lbl_0_6: |
| 5256 | ta T_CHANGE_NONHPRIV |
| 5257 | .word 0xe877e039 ! 1: STX_I stx %r20, [%r31 + 0x0039] |
| 5258 | br_longdelay4_20_0: |
| 5259 | nop |
| 5260 | not %g0, %r27 |
| 5261 | jmpl %r27+0, %r27 |
| 5262 | .word 0x9d902003 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0003, %wstate |
| 5263 | .word 0xe93fe1e6 ! 3: STDF_I std %f20, [0x01e6, %r31] |
| 5264 | fpinit_20_1: |
| 5265 | nop |
| 5266 | setx fp_data_quads, %r19, %r20 |
| 5267 | ldd [%r20], %f0 |
| 5268 | ldd [%r20+8], %f4 |
| 5269 | ld [%r20+16], %fsr |
| 5270 | ld [%r20+24], %r19 |
| 5271 | wr %r19, %g0, %gsr |
| 5272 | .word 0x89a009c4 ! 4: FDIVd fdivd %f0, %f4, %f4 |
| 5273 | splash_lsu_20_2: |
| 5274 | nop |
| 5275 | ta T_CHANGE_HPRIV |
| 5276 | set 0x1fd74ff7, %r2 |
| 5277 | mov 0x4, %r1 |
| 5278 | sllx %r1, 32, %r1 |
| 5279 | or %r1, %r2, %r2 |
| 5280 | .word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1> |
| 5281 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5282 | ta T_CHANGE_NONHPRIV |
| 5283 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5284 | splash_hpstate_20_3: |
| 5285 | .word 0x81982cc5 ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x0cc5, %hpstate |
| 5286 | memptr_20_4: |
| 5287 | set 0x60540000, %r31 |
| 5288 | .word 0x8584ac98 ! 7: WRCCR_I wr %r18, 0x0c98, %ccr |
| 5289 | nop |
| 5290 | mov 0x80, %g3 |
| 5291 | .word 0x2a800001 ! 1: BCS bcs,a <label_0x1> |
| 5292 | stxa %g3, [%g3] 0x5f |
| 5293 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 5294 | .word 0xc19fe040 ! 9: LDDFA_I ldda [%r31, 0x0040], %f0 |
| 5295 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 5296 | .word 0xe1bfd960 ! 11: STDFA_R stda %f16, [%r0, %r31] |
| 5297 | dvapa_20_6: |
| 5298 | nop |
| 5299 | ta T_CHANGE_HPRIV |
| 5300 | mov 0xc51, %r20 |
| 5301 | mov 0x1a, %r19 |
| 5302 | sllx %r20, 23, %r20 |
| 5303 | or %r19, %r20, %r19 |
| 5304 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 5305 | mov 0x38, %r18 |
| 5306 | stxa %r31, [%r18]0x58 |
| 5307 | ta T_CHANGE_NONHPRIV |
| 5308 | .word 0xe1bfe080 ! 12: STDFA_I stda %f16, [0x0080, %r31] |
| 5309 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 5310 | jmptr_20_7: |
| 5311 | nop |
| 5312 | best_set_reg(0xe1a00000, %r20, %r27) |
| 5313 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 5314 | pmu_20_8: |
| 5315 | nop |
| 5316 | ta T_CHANGE_PRIV |
| 5317 | setx 0xffffffb4ffffffae, %g1, %g7 |
| 5318 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 5319 | jmptr_20_9: |
| 5320 | nop |
| 5321 | best_set_reg(0xe1a00000, %r20, %r27) |
| 5322 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 5323 | nop |
| 5324 | ta T_CHANGE_HPRIV |
| 5325 | mov 0x20, %r10 |
| 5326 | set sync_thr_counter6, %r23 |
| 5327 | #ifndef SPC |
| 5328 | ldxa [%g0]0x63, %o1 |
| 5329 | and %o1, 0x38, %o1 |
| 5330 | add %o1, %r23, %r23 |
| 5331 | #endif |
| 5332 | cas [%r23],%g0,%r10 !lock |
| 5333 | brnz %r10, sma_20_10 |
| 5334 | rd %asi, %r12 |
| 5335 | wr %g0, 0x40, %asi |
| 5336 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5337 | set 0x000a1fff, %g1 |
| 5338 | stxa %g1, [%g0 + 0x80] %asi |
| 5339 | wr %r12, %g0, %asi |
| 5340 | st %g0, [%r23] |
| 5341 | sma_20_10: |
| 5342 | ta T_CHANGE_NONHPRIV |
| 5343 | .word 0xe9e7e012 ! 17: CASA_R casa [%r31] %asi, %r18, %r20 |
| 5344 | .word 0x87802010 ! 18: WRASI_I wr %r0, 0x0010, %asi |
| 5345 | splash_lsu_20_11: |
| 5346 | nop |
| 5347 | ta T_CHANGE_HPRIV |
| 5348 | set 0x1e119b37, %r2 |
| 5349 | mov 0x4, %r1 |
| 5350 | sllx %r1, 32, %r1 |
| 5351 | or %r1, %r2, %r2 |
| 5352 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5353 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5354 | .word 0xe93fe070 ! 20: STDF_I std %f20, [0x0070, %r31] |
| 5355 | brcommon1_20_12: |
| 5356 | nop |
| 5357 | setx common_target, %r12, %r27 |
| 5358 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 5359 | ba,a .+12 |
| 5360 | .word 0xa9b7c7ca ! 1: PDIST pdistn %d62, %d10, %d20 |
| 5361 | ba,a .+8 |
| 5362 | jmpl %r27+0, %r27 |
| 5363 | .word 0x87a90a45 ! 21: FCMPd fcmpd %fcc<n>, %f4, %f36 |
| 5364 | splash_lsu_20_13: |
| 5365 | nop |
| 5366 | ta T_CHANGE_HPRIV |
| 5367 | set 0x9ab8abb5, %r2 |
| 5368 | mov 0x5, %r1 |
| 5369 | sllx %r1, 32, %r1 |
| 5370 | or %r1, %r2, %r2 |
| 5371 | .word 0x20800001 ! 1: BN bn,a <label_0x1> |
| 5372 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5373 | ta T_CHANGE_NONHPRIV |
| 5374 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5375 | .word 0xc19fde00 ! 23: LDDFA_R ldda [%r31, %r0], %f0 |
| 5376 | .word 0xc1bfc2c0 ! 24: STDFA_R stda %f0, [%r0, %r31] |
| 5377 | pmu_20_14: |
| 5378 | nop |
| 5379 | ta T_CHANGE_PRIV |
| 5380 | setx 0xffffffb5ffffffaa, %g1, %g7 |
| 5381 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 5382 | rd %tick, %r28 |
| 5383 | #if (MAX_THREADS == 8) |
| 5384 | sethi %hi(0x33800), %r27 |
| 5385 | #else |
| 5386 | sethi %hi(0x30000), %r27 |
| 5387 | #endif |
| 5388 | andn %r28, %r27, %r28 |
| 5389 | ta T_CHANGE_HPRIV |
| 5390 | stxa %r28, [%g0] 0x73 |
| 5391 | .word 0x9f802193 ! 1: SIR sir 0x0193 |
| 5392 | intvec_20_15: |
| 5393 | .word 0x9f8027e2 ! 26: SIR sir 0x07e2 |
| 5394 | .word 0x91948014 ! 27: WRPR_PIL_R wrpr %r18, %r20, %pil |
| 5395 | nop |
| 5396 | mov 0x80, %g3 |
| 5397 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 5398 | stxa %g3, [%g3] 0x57 |
| 5399 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 5400 | #if (defined SPC || defined CMP) |
| 5401 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_20_17)+0, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 5402 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_20_17)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 5403 | xir_20_17: |
| 5404 | #else |
| 5405 | #if (defined FC) |
| 5406 | !! Generate XIR via RESET_GEN register |
| 5407 | ta T_CHANGE_HPRIV |
| 5408 | rdpr %pstate, %r18 |
| 5409 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 5410 | wrpr %r18, %pstate |
| 5411 | #ifndef XIR_RND_CORES |
| 5412 | ldxa [%g0] 0x63, %o1 |
| 5413 | mov 1, %r18 |
| 5414 | sllx %r18, %o1, %r18 |
| 5415 | #endif |
| 5416 | mov 0x30, %r19 |
| 5417 | setx 0x8900000808, %r16, %r17 |
| 5418 | mov 0x2, %r16 |
| 5419 | xir_20_17: |
| 5420 | stxa %r18, [%r19] 0x41 |
| 5421 | stx %r16, [%r17] |
| 5422 | #endif |
| 5423 | #endif |
| 5424 | .word 0xa98461da ! 29: WR_SET_SOFTINT_I wr %r17, 0x01da, %set_softint |
| 5425 | .word 0x97a0016d ! 30: FABSq dis not found |
| 5426 | |
| 5427 | .word 0xa1a0016c ! 31: FABSq dis not found |
| 5428 | |
| 5429 | tagged_20_20: |
| 5430 | tsubcctv %r7, 0x1ca8, %r18 |
| 5431 | .word 0xd807e0f4 ! 32: LDUW_I lduw [%r31 + 0x00f4], %r12 |
| 5432 | mondo_20_21: |
| 5433 | nop |
| 5434 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 5435 | stxa %r4, [%r0+0x3e0] %asi |
| 5436 | .word 0x9d944010 ! 33: WRPR_WSTATE_R wrpr %r17, %r16, %wstate |
| 5437 | .word 0xb184800b ! 34: WR_STICK_REG_R wr %r18, %r11, %- |
| 5438 | nop |
| 5439 | ta T_CHANGE_HPRIV |
| 5440 | mov 0x20, %r10 |
| 5441 | set sync_thr_counter6, %r23 |
| 5442 | #ifndef SPC |
| 5443 | ldxa [%g0]0x63, %o1 |
| 5444 | and %o1, 0x38, %o1 |
| 5445 | add %o1, %r23, %r23 |
| 5446 | #endif |
| 5447 | cas [%r23],%g0,%r10 !lock |
| 5448 | brnz %r10, sma_20_22 |
| 5449 | rd %asi, %r12 |
| 5450 | wr %g0, 0x40, %asi |
| 5451 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5452 | set 0x001e1fff, %g1 |
| 5453 | stxa %g1, [%g0 + 0x80] %asi |
| 5454 | wr %r12, %g0, %asi |
| 5455 | st %g0, [%r23] |
| 5456 | sma_20_22: |
| 5457 | ta T_CHANGE_NONHPRIV |
| 5458 | .word 0xd9e7e00b ! 35: CASA_R casa [%r31] %asi, %r11, %r12 |
| 5459 | nop |
| 5460 | ta T_CHANGE_HPRIV |
| 5461 | mov 0x20, %r10 |
| 5462 | set sync_thr_counter6, %r23 |
| 5463 | #ifndef SPC |
| 5464 | ldxa [%g0]0x63, %o1 |
| 5465 | and %o1, 0x38, %o1 |
| 5466 | add %o1, %r23, %r23 |
| 5467 | #endif |
| 5468 | cas [%r23],%g0,%r10 !lock |
| 5469 | brnz %r10, sma_20_23 |
| 5470 | rd %asi, %r12 |
| 5471 | wr %g0, 0x40, %asi |
| 5472 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5473 | set 0x000e1fff, %g1 |
| 5474 | stxa %g1, [%g0 + 0x80] %asi |
| 5475 | wr %r12, %g0, %asi |
| 5476 | st %g0, [%r23] |
| 5477 | sma_20_23: |
| 5478 | ta T_CHANGE_NONHPRIV |
| 5479 | .word 0xd9e7e013 ! 36: CASA_R casa [%r31] %asi, %r19, %r12 |
| 5480 | splash_tba_20_24: |
| 5481 | nop |
| 5482 | ta T_CHANGE_PRIV |
| 5483 | set 0x120000, %r12 |
| 5484 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 5485 | splash_lsu_20_25: |
| 5486 | nop |
| 5487 | ta T_CHANGE_HPRIV |
| 5488 | set 0xd9511c57, %r2 |
| 5489 | mov 0x1, %r1 |
| 5490 | sllx %r1, 32, %r1 |
| 5491 | or %r1, %r2, %r2 |
| 5492 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5493 | ta T_CHANGE_NONHPRIV |
| 5494 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5495 | #if (defined SPC || defined CMP1) |
| 5496 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_26) + 16, 16, 16)) -> intp(5,0,8,,,,,1) |
| 5497 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_26)&0xffffffff) + 24, 16, 16)) -> intp(1,0,10,,,,,1) |
| 5498 | #else |
| 5499 | set 0xbc004129, %r28 |
| 5500 | #if (MAX_THREADS == 8) |
| 5501 | and %r28, 0x7ff, %r28 |
| 5502 | #endif |
| 5503 | stxa %r28, [%g0] 0x73 |
| 5504 | #endif |
| 5505 | .word 0x9f802b4d ! 1: SIR sir 0x0b4d |
| 5506 | intvec_20_26: |
| 5507 | .word 0x9f803215 ! 39: SIR sir 0x1215 |
| 5508 | .word 0xd727e095 ! 40: STF_I st %f11, [0x0095, %r31] |
| 5509 | .word 0xd627e076 ! 41: STW_I stw %r11, [%r31 + 0x0076] |
| 5510 | jmptr_20_27: |
| 5511 | nop |
| 5512 | best_set_reg(0xe1a00000, %r20, %r27) |
| 5513 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 5514 | splash_tba_20_28: |
| 5515 | nop |
| 5516 | ta T_CHANGE_PRIV |
| 5517 | set 0x120000, %r12 |
| 5518 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 5519 | set 0x1ca1, %l3 |
| 5520 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 5521 | .word 0x99b0c7cd ! 44: PDIST pdistn %d34, %d44, %d12 |
| 5522 | pmu_20_29: |
| 5523 | nop |
| 5524 | setx 0xffffffb5ffffffa9, %g1, %g7 |
| 5525 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 5526 | brcommon3_20_30: |
| 5527 | nop |
| 5528 | setx common_target, %r12, %r27 |
| 5529 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 5530 | ba,a .+12 |
| 5531 | .word 0xe3e7c034 ! 1: CASA_I casa [%r31] 0x 1, %r20, %r17 |
| 5532 | ba,a .+8 |
| 5533 | jmpl %r27+0, %r27 |
| 5534 | .word 0xe31fe170 ! 46: LDDF_I ldd [%r31, 0x0170], %f17 |
| 5535 | brcommon3_20_31: |
| 5536 | nop |
| 5537 | setx common_target, %r12, %r27 |
| 5538 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 5539 | ba,a .+12 |
| 5540 | .word 0xe26fe170 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x0170] |
| 5541 | ba,a .+8 |
| 5542 | jmpl %r27+0, %r27 |
| 5543 | stxa %r9, [%r0] ASI_LSU_CONTROL |
| 5544 | .word 0x91aac825 ! 47: FMOVGE fmovs %fcc1, %f5, %f8 |
| 5545 | brcommon3_20_32: |
| 5546 | nop |
| 5547 | setx common_target, %r12, %r27 |
| 5548 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 5549 | ba,a .+12 |
| 5550 | .word 0xd737e010 ! 1: STQF_I - %f11, [0x0010, %r31] |
| 5551 | ba,a .+8 |
| 5552 | jmpl %r27+0, %r27 |
| 5553 | .word 0xd6bfc029 ! 48: STDA_R stda %r11, [%r31 + %r9] 0x01 |
| 5554 | nop |
| 5555 | mov 0x80, %g3 |
| 5556 | .word 0x26800001 ! 1: BL bl,a <label_0x1> |
| 5557 | stxa %g3, [%g3] 0x57 |
| 5558 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 5559 | nop |
| 5560 | ta T_CHANGE_HPRIV ! macro |
| 5561 | donret_20_33: |
| 5562 | rd %pc, %r12 |
| 5563 | mov HIGHVA_HIGHNUM, %r10 |
| 5564 | sllx %r10, 32, %r10 |
| 5565 | or %r12, %r10, %r12 |
| 5566 | add %r12, (donretarg_20_33-donret_20_33), %r12 |
| 5567 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 5568 | andn %r11, %r10, %r11 ! low VA tnpc |
| 5569 | wrpr %g0, 0x1, %tl |
| 5570 | wrpr %g0, %r12, %tpc |
| 5571 | wrpr %g0, %r11, %tnpc |
| 5572 | set (0x0044f600 | (28 << 24)), %r13 |
| 5573 | and %r12, 0xfff, %r14 |
| 5574 | sllx %r14, 32, %r14 |
| 5575 | or %r13, %r14, %r20 |
| 5576 | wrpr %r20, %g0, %tstate |
| 5577 | wrhpr %g0, 0x1d9, %htstate |
| 5578 | ta T_CHANGE_NONHPRIV ! rand=1 (20) |
| 5579 | ldx [%r11+%r0], %g1 |
| 5580 | done |
| 5581 | donretarg_20_33: |
| 5582 | .word 0x2e800001 ! 50: BVS bvs,a <label_0x1> |
| 5583 | #if (defined SPC || defined CMP1) |
| 5584 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_34) + 56, 16, 16)) -> intp(6,0,13,,,,,1) |
| 5585 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_34)&0xffffffff) + 24, 16, 16)) -> intp(7,0,22,,,,,1) |
| 5586 | #else |
| 5587 | set 0x5fd0898c, %r28 |
| 5588 | #if (MAX_THREADS == 8) |
| 5589 | and %r28, 0x7ff, %r28 |
| 5590 | #endif |
| 5591 | stxa %r28, [%g0] 0x73 |
| 5592 | #endif |
| 5593 | intvec_20_34: |
| 5594 | .word 0xa9a4c9d1 ! 51: FDIVd fdivd %f50, %f48, %f20 |
| 5595 | .word 0xe927e172 ! 52: STF_I st %f20, [0x0172, %r31] |
| 5596 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 5597 | splash_tba_20_35: |
| 5598 | nop |
| 5599 | ta T_CHANGE_PRIV |
| 5600 | setx 0x00000004003a0000, %r11, %r12 |
| 5601 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 5602 | .word 0xa5a409a1 ! 55: FDIVs fdivs %f16, %f1, %f18 |
| 5603 | ibp_20_37: |
| 5604 | nop |
| 5605 | ta T_CHANGE_NONHPRIV |
| 5606 | .word 0xc3e88028 ! 56: PREFETCHA_R prefetcha [%r2, %r8] 0x01, #one_read |
| 5607 | brcommon3_20_38: |
| 5608 | nop |
| 5609 | setx common_target, %r12, %r27 |
| 5610 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 5611 | ba,a .+12 |
| 5612 | .word 0xe937e050 ! 1: STQF_I - %f20, [0x0050, %r31] |
| 5613 | ba,a .+8 |
| 5614 | jmpl %r27+0, %r27 |
| 5615 | .word 0xe91fe0b0 ! 57: LDDF_I ldd [%r31, 0x00b0], %f20 |
| 5616 | ibp_20_39: |
| 5617 | nop |
| 5618 | ta T_CHANGE_NONHPRIV |
| 5619 | .word 0x97a509ad ! 58: FDIVs fdivs %f20, %f13, %f11 |
| 5620 | nop |
| 5621 | ta T_CHANGE_HPRIV ! macro |
| 5622 | donret_20_40: |
| 5623 | rd %pc, %r12 |
| 5624 | mov HIGHVA_HIGHNUM, %r10 |
| 5625 | sllx %r10, 32, %r10 |
| 5626 | or %r12, %r10, %r12 |
| 5627 | add %r12, (donretarg_20_40-donret_20_40+4), %r12 |
| 5628 | add %r12, 0x4, %r11 ! seq tnpc |
| 5629 | andn %r12, %r10, %r12 ! low VA tpc |
| 5630 | wrpr %g0, 0x2, %tl |
| 5631 | wrpr %g0, %r12, %tpc |
| 5632 | wrpr %g0, %r11, %tnpc |
| 5633 | set (0x00eb8800 | (20 << 24)), %r13 |
| 5634 | and %r12, 0xfff, %r14 |
| 5635 | sllx %r14, 32, %r14 |
| 5636 | or %r13, %r14, %r20 |
| 5637 | wrpr %r20, %g0, %tstate |
| 5638 | wrhpr %g0, 0xa4b, %htstate |
| 5639 | ta T_CHANGE_NONPRIV ! rand=0 (20) |
| 5640 | ldx [%r12+%r0], %g1 |
| 5641 | retry |
| 5642 | donretarg_20_40: |
| 5643 | .word 0x3c800001 ! 59: BPOS bpos,a <label_0x1> |
| 5644 | memptr_20_41: |
| 5645 | set 0x60140000, %r31 |
| 5646 | .word 0x8584b307 ! 60: WRCCR_I wr %r18, 0x1307, %ccr |
| 5647 | nop |
| 5648 | mov 0x80, %g3 |
| 5649 | stxa %r10, [%r0] ASI_LSU_CONTROL |
| 5650 | stxa %g3, [%g3] 0x5f |
| 5651 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 5652 | .word 0x9953c000 ! 62: RDPR_FQ <illegal instruction> |
| 5653 | brnz,pn %r8, skip_20_42 |
| 5654 | .word 0x97a049c5 ! 1: FDIVd fdivd %f32, %f36, %f42 |
| 5655 | .align 1024 |
| 5656 | skip_20_42: |
| 5657 | .word 0x39400001 ! 63: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 5658 | fbne skip_20_43 |
| 5659 | stxa %r13, [%r0] ASI_LSU_CONTROL |
| 5660 | fbl skip_20_43 |
| 5661 | stxa %r8, [%r0] ASI_LSU_CONTROL |
| 5662 | .align 1024 |
| 5663 | skip_20_43: |
| 5664 | .word 0xc30fc000 ! 64: LDXFSR_R ld-fsr [%r31, %r0], %f1 |
| 5665 | .word 0xc19fdc00 ! 65: LDDFA_R ldda [%r31, %r0], %f0 |
| 5666 | nop |
| 5667 | ta T_CHANGE_HPRIV |
| 5668 | mov 0x20+1, %r10 |
| 5669 | set sync_thr_counter5, %r23 |
| 5670 | #ifndef SPC |
| 5671 | ldxa [%g0]0x63, %o1 |
| 5672 | and %o1, 0x38, %o1 |
| 5673 | add %o1, %r23, %r23 |
| 5674 | sllx %o1, 5, %o3 !(CID*256) |
| 5675 | #endif |
| 5676 | cas [%r23],%g0,%r10 !lock |
| 5677 | brnz %r10, cwq_20_44 |
| 5678 | rd %asi, %r12 |
| 5679 | wr %g0, 0x40, %asi |
| 5680 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 5681 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 5682 | cmp %l1, 1 |
| 5683 | bne cwq_20_44 |
| 5684 | set CWQ_BASE, %l6 |
| 5685 | #ifndef SPC |
| 5686 | add %l6, %o3, %l6 |
| 5687 | #endif |
| 5688 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 5689 | best_set_reg(0x20610070, %l1, %l2) !# Control Word |
| 5690 | sllx %l2, 32, %l2 |
| 5691 | stx %l2, [%l6 + 0x0] |
| 5692 | membar #Sync |
| 5693 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 5694 | sub %l2, 0x40, %l2 |
| 5695 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 5696 | wr %r12, %g0, %asi |
| 5697 | st %g0, [%r23] |
| 5698 | cwq_20_44: |
| 5699 | ta T_CHANGE_NONHPRIV |
| 5700 | .word 0xa1414000 ! 66: RDPC rd %pc, %r16 |
| 5701 | mondo_20_45: |
| 5702 | nop |
| 5703 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 5704 | ta T_CHANGE_PRIV |
| 5705 | stxa %r18, [%r0+0x3c8] %asi |
| 5706 | .word 0x9d940014 ! 67: WRPR_WSTATE_R wrpr %r16, %r20, %wstate |
| 5707 | .word 0xa7a00173 ! 68: FABSq dis not found |
| 5708 | |
| 5709 | .word 0x91940001 ! 69: WRPR_PIL_R wrpr %r16, %r1, %pil |
| 5710 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 5711 | #if (defined SPC || defined CMP) |
| 5712 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_20_49)+8, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 5713 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_20_49)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 5714 | xir_20_49: |
| 5715 | #else |
| 5716 | #if (defined FC) |
| 5717 | !! Generate XIR via RESET_GEN register |
| 5718 | ta T_CHANGE_HPRIV |
| 5719 | rdpr %pstate, %r18 |
| 5720 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 5721 | wrpr %r18, %pstate |
| 5722 | #ifndef XIR_RND_CORES |
| 5723 | ldxa [%g0] 0x63, %o1 |
| 5724 | mov 1, %r18 |
| 5725 | sllx %r18, %o1, %r18 |
| 5726 | #endif |
| 5727 | mov 0x30, %r19 |
| 5728 | setx 0x8900000808, %r16, %r17 |
| 5729 | mov 0x2, %r16 |
| 5730 | xir_20_49: |
| 5731 | stxa %r18, [%r19] 0x41 |
| 5732 | stx %r16, [%r17] |
| 5733 | #endif |
| 5734 | #endif |
| 5735 | .word 0xa9847665 ! 71: WR_SET_SOFTINT_I wr %r17, 0x1665, %set_softint |
| 5736 | #if (defined SPC || defined CMP1) |
| 5737 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_50) + 0, 16, 16)) -> intp(2,0,0,,,,,1) |
| 5738 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_50)&0xffffffff) + 56, 16, 16)) -> intp(4,0,11,,,,,1) |
| 5739 | #else |
| 5740 | set 0xff2038dd, %r28 |
| 5741 | #if (MAX_THREADS == 8) |
| 5742 | and %r28, 0x7ff, %r28 |
| 5743 | #endif |
| 5744 | stxa %r28, [%g0] 0x73 |
| 5745 | #endif |
| 5746 | .word 0x9f802b9c ! 1: SIR sir 0x0b9c |
| 5747 | intvec_20_50: |
| 5748 | .word 0x9ba409d0 ! 72: FDIVd fdivd %f16, %f16, %f44 |
| 5749 | invtsb_20_51: |
| 5750 | nop |
| 5751 | ta T_CHANGE_HPRIV |
| 5752 | rd %asi, %r21 |
| 5753 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 5754 | mov 1, %r20 |
| 5755 | sllx %r20, 63, %r20 |
| 5756 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 5757 | xor %r22 ,%r20, %r22 |
| 5758 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 5759 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 5760 | xor %r22 ,%r20, %r22 |
| 5761 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 5762 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 5763 | xor %r22 ,%r20, %r22 |
| 5764 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 5765 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 5766 | xor %r22 ,%r20, %r22 |
| 5767 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 5768 | wr %r21, %r0, %asi |
| 5769 | ta T_CHANGE_NONHPRIV |
| 5770 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 5771 | nop |
| 5772 | mov 0x80, %g3 |
| 5773 | stxa %r10, [%r0] ASI_LSU_CONTROL |
| 5774 | stxa %g3, [%g3] 0x57 |
| 5775 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 5776 | nop |
| 5777 | ta T_CHANGE_HPRIV |
| 5778 | mov 0x20, %r10 |
| 5779 | set sync_thr_counter6, %r23 |
| 5780 | #ifndef SPC |
| 5781 | ldxa [%g0]0x63, %o1 |
| 5782 | and %o1, 0x38, %o1 |
| 5783 | add %o1, %r23, %r23 |
| 5784 | #endif |
| 5785 | cas [%r23],%g0,%r10 !lock |
| 5786 | brnz %r10, sma_20_52 |
| 5787 | rd %asi, %r12 |
| 5788 | wr %g0, 0x40, %asi |
| 5789 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5790 | set 0x001a1fff, %g1 |
| 5791 | stxa %g1, [%g0 + 0x80] %asi |
| 5792 | wr %r12, %g0, %asi |
| 5793 | st %g0, [%r23] |
| 5794 | sma_20_52: |
| 5795 | ta T_CHANGE_NONHPRIV |
| 5796 | .word 0xe5e7e00d ! 75: CASA_R casa [%r31] %asi, %r13, %r18 |
| 5797 | .word 0x91950014 ! 76: WRPR_PIL_R wrpr %r20, %r20, %pil |
| 5798 | pmu_20_54: |
| 5799 | nop |
| 5800 | setx 0xffffffbcffffffa0, %g1, %g7 |
| 5801 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 5802 | fpinit_20_55: |
| 5803 | nop |
| 5804 | setx fp_data_quads, %r19, %r20 |
| 5805 | ldd [%r20], %f0 |
| 5806 | ldd [%r20+8], %f4 |
| 5807 | ld [%r20+16], %fsr |
| 5808 | ld [%r20+24], %r19 |
| 5809 | wr %r19, %g0, %gsr |
| 5810 | .word 0x8da009c4 ! 78: FDIVd fdivd %f0, %f4, %f6 |
| 5811 | jmptr_20_56: |
| 5812 | nop |
| 5813 | best_set_reg(0xe1a00000, %r20, %r27) |
| 5814 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 5815 | nop |
| 5816 | mov 0x80, %g3 |
| 5817 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 5818 | stxa %g3, [%g3] 0x57 |
| 5819 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 5820 | .word 0x91b040f0 ! 81: EDGE16LN edge16ln %r1, %r16, %r8 |
| 5821 | #if (defined SPC || defined CMP1) |
| 5822 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_58) + 24, 16, 16)) -> intp(2,0,6,,,,,1) |
| 5823 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_58)&0xffffffff) + 16, 16, 16)) -> intp(6,0,2,,,,,1) |
| 5824 | #else |
| 5825 | set 0x35e01f10, %r28 |
| 5826 | #if (MAX_THREADS == 8) |
| 5827 | and %r28, 0x7ff, %r28 |
| 5828 | #endif |
| 5829 | stxa %r28, [%g0] 0x73 |
| 5830 | #endif |
| 5831 | .word 0x99a309c9 ! 1: FDIVd fdivd %f12, %f40, %f12 |
| 5832 | intvec_20_58: |
| 5833 | .word 0xc36a6d47 ! 82: PREFETCH_I prefetch [%r9 + 0x0d47], #one_read |
| 5834 | nop |
| 5835 | ta T_CHANGE_HPRIV |
| 5836 | mov 0x20, %r10 |
| 5837 | set sync_thr_counter6, %r23 |
| 5838 | #ifndef SPC |
| 5839 | ldxa [%g0]0x63, %o1 |
| 5840 | and %o1, 0x38, %o1 |
| 5841 | add %o1, %r23, %r23 |
| 5842 | #endif |
| 5843 | cas [%r23],%g0,%r10 !lock |
| 5844 | brnz %r10, sma_20_59 |
| 5845 | rd %asi, %r12 |
| 5846 | wr %g0, 0x40, %asi |
| 5847 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5848 | set 0x00161fff, %g1 |
| 5849 | stxa %g1, [%g0 + 0x80] %asi |
| 5850 | wr %r12, %g0, %asi |
| 5851 | st %g0, [%r23] |
| 5852 | sma_20_59: |
| 5853 | ta T_CHANGE_NONHPRIV |
| 5854 | .word 0xe5e7e010 ! 83: CASA_R casa [%r31] %asi, %r16, %r18 |
| 5855 | fpinit_20_60: |
| 5856 | nop |
| 5857 | setx fp_data_quads, %r19, %r20 |
| 5858 | ldd [%r20], %f0 |
| 5859 | ldd [%r20+8], %f4 |
| 5860 | ld [%r20+16], %fsr |
| 5861 | ld [%r20+24], %r19 |
| 5862 | wr %r19, %g0, %gsr |
| 5863 | .word 0x91a009c4 ! 84: FDIVd fdivd %f0, %f4, %f8 |
| 5864 | .word 0x87802010 ! 85: WRASI_I wr %r0, 0x0010, %asi |
| 5865 | .word 0xe19fdc00 ! 86: LDDFA_R ldda [%r31, %r0], %f16 |
| 5866 | splash_lsu_20_61: |
| 5867 | nop |
| 5868 | ta T_CHANGE_HPRIV |
| 5869 | set 0xe8abe0ee, %r2 |
| 5870 | mov 0x3, %r1 |
| 5871 | sllx %r1, 32, %r1 |
| 5872 | or %r1, %r2, %r2 |
| 5873 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5874 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5875 | splash_lsu_20_62: |
| 5876 | nop |
| 5877 | ta T_CHANGE_HPRIV |
| 5878 | set 0x6a11bae6, %r2 |
| 5879 | mov 0x7, %r1 |
| 5880 | sllx %r1, 32, %r1 |
| 5881 | or %r1, %r2, %r2 |
| 5882 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5883 | ta T_CHANGE_NONHPRIV |
| 5884 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5885 | splash_cmpr_20_63: |
| 5886 | mov 1, %r18 |
| 5887 | sllx %r18, 63, %r18 |
| 5888 | rd %tick, %r17 |
| 5889 | add %r17, 0x60, %r17 |
| 5890 | or %r17, %r18, %r17 |
| 5891 | ta T_CHANGE_HPRIV |
| 5892 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 5893 | .word 0xb3800011 ! 89: WR_STICK_CMPR_REG_R wr %r0, %r17, %- |
| 5894 | nop |
| 5895 | mov 0x80, %g3 |
| 5896 | .word 0x22c98001 ! 1: BRZ brz,a,pt %r6,<label_0x98001> |
| 5897 | stxa %g3, [%g3] 0x5f |
| 5898 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 5899 | splash_tba_20_64: |
| 5900 | nop |
| 5901 | ta T_CHANGE_PRIV |
| 5902 | set 0x120000, %r12 |
| 5903 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 5904 | dvapa_20_65: |
| 5905 | nop |
| 5906 | ta T_CHANGE_HPRIV |
| 5907 | mov 0xa85, %r20 |
| 5908 | mov 0x0, %r19 |
| 5909 | sllx %r20, 23, %r20 |
| 5910 | or %r19, %r20, %r19 |
| 5911 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 5912 | mov 0x38, %r18 |
| 5913 | stxa %r31, [%r18]0x58 |
| 5914 | ta T_CHANGE_NONHPRIV |
| 5915 | .word 0xe51fe0e0 ! 92: LDDF_I ldd [%r31, 0x00e0], %f18 |
| 5916 | splash_lsu_20_66: |
| 5917 | nop |
| 5918 | ta T_CHANGE_HPRIV |
| 5919 | set 0x48610697, %r2 |
| 5920 | mov 0x6, %r1 |
| 5921 | sllx %r1, 32, %r1 |
| 5922 | or %r1, %r2, %r2 |
| 5923 | .word 0x2d400001 ! 1: FBPG fbg,a,pn %fcc0, <label_0x1> |
| 5924 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 5925 | ta T_CHANGE_NONHPRIV |
| 5926 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 5927 | ibp_20_67: |
| 5928 | nop |
| 5929 | .word 0xe51fe1d0 ! 94: LDDF_I ldd [%r31, 0x01d0], %f18 |
| 5930 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 5931 | nop |
| 5932 | ta T_CHANGE_HPRIV |
| 5933 | mov 0x20, %r10 |
| 5934 | set sync_thr_counter6, %r23 |
| 5935 | #ifndef SPC |
| 5936 | ldxa [%g0]0x63, %o1 |
| 5937 | and %o1, 0x38, %o1 |
| 5938 | add %o1, %r23, %r23 |
| 5939 | #endif |
| 5940 | cas [%r23],%g0,%r10 !lock |
| 5941 | brnz %r10, sma_20_68 |
| 5942 | rd %asi, %r12 |
| 5943 | wr %g0, 0x40, %asi |
| 5944 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 5945 | set 0x001a1fff, %g1 |
| 5946 | stxa %g1, [%g0 + 0x80] %asi |
| 5947 | wr %r12, %g0, %asi |
| 5948 | st %g0, [%r23] |
| 5949 | sma_20_68: |
| 5950 | ta T_CHANGE_NONHPRIV |
| 5951 | .word 0xe5e7e010 ! 96: CASA_R casa [%r31] %asi, %r16, %r18 |
| 5952 | #if (defined SPC || defined CMP) |
| 5953 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_20_69)+0, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 5954 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_20_69)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 5955 | xir_20_69: |
| 5956 | #else |
| 5957 | #if (defined FC) |
| 5958 | !! Generate XIR via RESET_GEN register |
| 5959 | ta T_CHANGE_HPRIV |
| 5960 | rdpr %pstate, %r18 |
| 5961 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 5962 | wrpr %r18, %pstate |
| 5963 | #ifndef XIR_RND_CORES |
| 5964 | ldxa [%g0] 0x63, %o1 |
| 5965 | mov 1, %r18 |
| 5966 | sllx %r18, %o1, %r18 |
| 5967 | #endif |
| 5968 | mov 0x30, %r19 |
| 5969 | setx 0x8900000808, %r16, %r17 |
| 5970 | mov 0x2, %r16 |
| 5971 | xir_20_69: |
| 5972 | stxa %r18, [%r19] 0x41 |
| 5973 | stx %r16, [%r17] |
| 5974 | #endif |
| 5975 | #endif |
| 5976 | .word 0xa981221e ! 97: WR_SET_SOFTINT_I wr %r4, 0x021e, %set_softint |
| 5977 | #if (defined SPC || defined CMP1) |
| 5978 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_70) + 40, 16, 16)) -> intp(4,0,28,,,,,1) |
| 5979 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_20_70)&0xffffffff) + 32, 16, 16)) -> intp(7,0,15,,,,,1) |
| 5980 | #else |
| 5981 | set 0xfd0086e9, %r28 |
| 5982 | #if (MAX_THREADS == 8) |
| 5983 | and %r28, 0x7ff, %r28 |
| 5984 | #endif |
| 5985 | stxa %r28, [%g0] 0x73 |
| 5986 | #endif |
| 5987 | intvec_20_70: |
| 5988 | .word 0x39400001 ! 98: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 5989 | fpinit_20_71: |
| 5990 | nop |
| 5991 | setx fp_data_quads, %r19, %r20 |
| 5992 | ldd [%r20], %f0 |
| 5993 | ldd [%r20+8], %f4 |
| 5994 | ld [%r20+16], %fsr |
| 5995 | ld [%r20+24], %r19 |
| 5996 | wr %r19, %g0, %gsr |
| 5997 | .word 0x87a80a44 ! 99: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 5998 | splash_lsu_20_72: |
| 5999 | nop |
| 6000 | ta T_CHANGE_HPRIV |
| 6001 | set 0xa9749179, %r2 |
| 6002 | mov 0x7, %r1 |
| 6003 | sllx %r1, 32, %r1 |
| 6004 | or %r1, %r2, %r2 |
| 6005 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6006 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6007 | .word 0x9bb040f1 ! 101: EDGE16LN edge16ln %r1, %r17, %r13 |
| 6008 | nop |
| 6009 | ta T_CHANGE_HPRIV |
| 6010 | mov 0x20, %r10 |
| 6011 | set sync_thr_counter6, %r23 |
| 6012 | #ifndef SPC |
| 6013 | ldxa [%g0]0x63, %o1 |
| 6014 | and %o1, 0x38, %o1 |
| 6015 | add %o1, %r23, %r23 |
| 6016 | #endif |
| 6017 | cas [%r23],%g0,%r10 !lock |
| 6018 | brnz %r10, sma_20_74 |
| 6019 | rd %asi, %r12 |
| 6020 | wr %g0, 0x40, %asi |
| 6021 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6022 | set 0x001e1fff, %g1 |
| 6023 | stxa %g1, [%g0 + 0x80] %asi |
| 6024 | wr %r12, %g0, %asi |
| 6025 | st %g0, [%r23] |
| 6026 | sma_20_74: |
| 6027 | ta T_CHANGE_NONHPRIV |
| 6028 | .word 0xd7e7e008 ! 102: CASA_R casa [%r31] %asi, %r8, %r11 |
| 6029 | nop |
| 6030 | mov 0x80, %g3 |
| 6031 | .word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 6032 | stxa %g3, [%g3] 0x5f |
| 6033 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 6034 | invtsb_20_75: |
| 6035 | nop |
| 6036 | ta T_CHANGE_HPRIV |
| 6037 | rd %asi, %r21 |
| 6038 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 6039 | mov 1, %r20 |
| 6040 | sllx %r20, 63, %r20 |
| 6041 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 6042 | xor %r22 ,%r20, %r22 |
| 6043 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 6044 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 6045 | xor %r22 ,%r20, %r22 |
| 6046 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 6047 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 6048 | xor %r22 ,%r20, %r22 |
| 6049 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 6050 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 6051 | xor %r22 ,%r20, %r22 |
| 6052 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 6053 | wr %r21, %r0, %asi |
| 6054 | ta T_CHANGE_NONHPRIV |
| 6055 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 6056 | .word 0xe19fdc00 ! 105: LDDFA_R ldda [%r31, %r0], %f16 |
| 6057 | splash_lsu_20_77: |
| 6058 | nop |
| 6059 | ta T_CHANGE_HPRIV |
| 6060 | set 0xf30efe17, %r2 |
| 6061 | mov 0x5, %r1 |
| 6062 | sllx %r1, 32, %r1 |
| 6063 | or %r1, %r2, %r2 |
| 6064 | .word 0x2a800001 ! 1: BCS bcs,a <label_0x1> |
| 6065 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6066 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6067 | .word 0xe1bfdb60 ! 107: STDFA_R stda %f16, [%r0, %r31] |
| 6068 | .word 0x91948001 ! 108: WRPR_PIL_R wrpr %r18, %r1, %pil |
| 6069 | splash_lsu_20_79: |
| 6070 | nop |
| 6071 | ta T_CHANGE_HPRIV |
| 6072 | set 0x2a66ded0, %r2 |
| 6073 | mov 0x3, %r1 |
| 6074 | sllx %r1, 32, %r1 |
| 6075 | or %r1, %r2, %r2 |
| 6076 | .word 0x24800001 ! 1: BLE ble,a <label_0x1> |
| 6077 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6078 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6079 | .word 0xe1bfdb60 ! 110: STDFA_R stda %f16, [%r0, %r31] |
| 6080 | ble,a skip_20_80 |
| 6081 | fblg skip_20_80 |
| 6082 | .align 128 |
| 6083 | skip_20_80: |
| 6084 | .word 0x93a489c8 ! 111: FDIVd fdivd %f18, %f8, %f40 |
| 6085 | .word 0xc1bfc2c0 ! 112: STDFA_R stda %f0, [%r0, %r31] |
| 6086 | rd %tick, %r28 |
| 6087 | #if (MAX_THREADS == 8) |
| 6088 | sethi %hi(0x33800), %r27 |
| 6089 | #else |
| 6090 | sethi %hi(0x30000), %r27 |
| 6091 | #endif |
| 6092 | andn %r28, %r27, %r28 |
| 6093 | ta T_CHANGE_HPRIV |
| 6094 | stxa %r28, [%g0] 0x73 |
| 6095 | intvec_20_81: |
| 6096 | .word 0x9f80391f ! 113: SIR sir 0x191f |
| 6097 | .word 0xe1bfe0a0 ! 114: STDFA_I stda %f16, [0x00a0, %r31] |
| 6098 | nop |
| 6099 | mov 0x80, %g3 |
| 6100 | .word 0x22cd0001 ! 1: BRZ brz,a,pt %r20,<label_0xd0001> |
| 6101 | stxa %g3, [%g3] 0x5f |
| 6102 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 6103 | jmptr_20_82: |
| 6104 | nop |
| 6105 | best_set_reg(0xe1a00000, %r20, %r27) |
| 6106 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 6107 | splash_tba_20_83: |
| 6108 | nop |
| 6109 | ta T_CHANGE_PRIV |
| 6110 | setx 0x00000004003a0000, %r11, %r12 |
| 6111 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 6112 | .word 0x91928011 ! 118: WRPR_PIL_R wrpr %r10, %r17, %pil |
| 6113 | #if (defined SPC || defined CMP) |
| 6114 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_20_85)+8, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 6115 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_20_85)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 6116 | xir_20_85: |
| 6117 | #else |
| 6118 | #if (defined FC) |
| 6119 | !! Generate XIR via RESET_GEN register |
| 6120 | ta T_CHANGE_HPRIV |
| 6121 | rdpr %pstate, %r18 |
| 6122 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 6123 | wrpr %r18, %pstate |
| 6124 | #ifndef XIR_RND_CORES |
| 6125 | ldxa [%g0] 0x63, %o1 |
| 6126 | mov 1, %r18 |
| 6127 | sllx %r18, %o1, %r18 |
| 6128 | #endif |
| 6129 | mov 0x30, %r19 |
| 6130 | setx 0x8900000808, %r16, %r17 |
| 6131 | mov 0x2, %r16 |
| 6132 | xir_20_85: |
| 6133 | stxa %r18, [%r19] 0x41 |
| 6134 | stx %r16, [%r17] |
| 6135 | #endif |
| 6136 | #endif |
| 6137 | .word 0xa981e559 ! 119: WR_SET_SOFTINT_I wr %r7, 0x0559, %set_softint |
| 6138 | cwp_20_86: |
| 6139 | set user_data_start, %o7 |
| 6140 | .word 0x93902003 ! 120: WRPR_CWP_I wrpr %r0, 0x0003, %cwp |
| 6141 | nop |
| 6142 | mov 0x80, %g3 |
| 6143 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 6144 | stxa %g3, [%g3] 0x57 |
| 6145 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 6146 | nop |
| 6147 | ta T_CHANGE_HPRIV ! macro |
| 6148 | donret_20_87: |
| 6149 | rd %pc, %r12 |
| 6150 | mov HIGHVA_HIGHNUM, %r10 |
| 6151 | sllx %r10, 32, %r10 |
| 6152 | or %r12, %r10, %r12 |
| 6153 | add %r12, (donretarg_20_87-donret_20_87), %r12 |
| 6154 | add %r12, 0x4, %r11 ! seq tnpc |
| 6155 | andn %r11, %r10, %r11 ! low VA tnpc |
| 6156 | wrpr %g0, 0x1, %tl |
| 6157 | wrpr %g0, %r12, %tpc |
| 6158 | wrpr %g0, %r11, %tnpc |
| 6159 | set (0x00f24300 | (0x83 << 24)), %r13 |
| 6160 | and %r12, 0xfff, %r14 |
| 6161 | sllx %r14, 32, %r14 |
| 6162 | or %r13, %r14, %r20 |
| 6163 | wrpr %r20, %g0, %tstate |
| 6164 | wrhpr %g0, 0x347, %htstate |
| 6165 | ta T_CHANGE_NONPRIV ! rand=0 (20) |
| 6166 | ldx [%r11+%r0], %g1 |
| 6167 | done |
| 6168 | donretarg_20_87: |
| 6169 | .word 0xe66fe019 ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x0019] |
| 6170 | invtsb_20_88: |
| 6171 | nop |
| 6172 | ta T_CHANGE_HPRIV |
| 6173 | rd %asi, %r21 |
| 6174 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 6175 | mov 1, %r20 |
| 6176 | sllx %r20, 63, %r20 |
| 6177 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 6178 | xor %r22 ,%r20, %r22 |
| 6179 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 6180 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 6181 | xor %r22 ,%r20, %r22 |
| 6182 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 6183 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 6184 | xor %r22 ,%r20, %r22 |
| 6185 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 6186 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 6187 | xor %r22 ,%r20, %r22 |
| 6188 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 6189 | wr %r21, %r0, %asi |
| 6190 | ta T_CHANGE_NONHPRIV |
| 6191 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 6192 | .word 0x9745c000 ! 124: RD_TICK_CMPR_REG rd %-, %r11 |
| 6193 | .word 0xc19fde00 ! 125: LDDFA_R ldda [%r31, %r0], %f0 |
| 6194 | nop |
| 6195 | ta T_CHANGE_HPRIV |
| 6196 | mov 0x20+1, %r10 |
| 6197 | set sync_thr_counter5, %r23 |
| 6198 | #ifndef SPC |
| 6199 | ldxa [%g0]0x63, %o1 |
| 6200 | and %o1, 0x38, %o1 |
| 6201 | add %o1, %r23, %r23 |
| 6202 | sllx %o1, 5, %o3 !(CID*256) |
| 6203 | #endif |
| 6204 | cas [%r23],%g0,%r10 !lock |
| 6205 | brnz %r10, cwq_20_89 |
| 6206 | rd %asi, %r12 |
| 6207 | wr %g0, 0x40, %asi |
| 6208 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 6209 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 6210 | cmp %l1, 1 |
| 6211 | bne cwq_20_89 |
| 6212 | set CWQ_BASE, %l6 |
| 6213 | #ifndef SPC |
| 6214 | add %l6, %o3, %l6 |
| 6215 | #endif |
| 6216 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 6217 | best_set_reg(0x206100a0, %l1, %l2) !# Control Word |
| 6218 | sllx %l2, 32, %l2 |
| 6219 | stx %l2, [%l6 + 0x0] |
| 6220 | membar #Sync |
| 6221 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 6222 | sub %l2, 0x40, %l2 |
| 6223 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 6224 | wr %r12, %g0, %asi |
| 6225 | st %g0, [%r23] |
| 6226 | cwq_20_89: |
| 6227 | ta T_CHANGE_NONHPRIV |
| 6228 | .word 0xa5414000 ! 126: RDPC rd %pc, %r18 |
| 6229 | .word 0xa7a00171 ! 127: FABSq dis not found |
| 6230 | |
| 6231 | #if (defined SPC || defined CMP) |
| 6232 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_20_91)+0, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 6233 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_20_91)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x20),1,3,,,,,1) |
| 6234 | xir_20_91: |
| 6235 | #else |
| 6236 | #if (defined FC) |
| 6237 | !! Generate XIR via RESET_GEN register |
| 6238 | ta T_CHANGE_HPRIV |
| 6239 | rdpr %pstate, %r18 |
| 6240 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 6241 | wrpr %r18, %pstate |
| 6242 | #ifndef XIR_RND_CORES |
| 6243 | ldxa [%g0] 0x63, %o1 |
| 6244 | mov 1, %r18 |
| 6245 | sllx %r18, %o1, %r18 |
| 6246 | #endif |
| 6247 | mov 0x30, %r19 |
| 6248 | setx 0x8900000808, %r16, %r17 |
| 6249 | mov 0x2, %r16 |
| 6250 | xir_20_91: |
| 6251 | stxa %r18, [%r19] 0x41 |
| 6252 | stx %r16, [%r17] |
| 6253 | #endif |
| 6254 | #endif |
| 6255 | .word 0xa9836ca2 ! 128: WR_SET_SOFTINT_I wr %r13, 0x0ca2, %set_softint |
| 6256 | memptr_20_92: |
| 6257 | set 0x60540000, %r31 |
| 6258 | .word 0x85806323 ! 129: WRCCR_I wr %r1, 0x0323, %ccr |
| 6259 | rd %tick, %r28 |
| 6260 | #if (MAX_THREADS == 8) |
| 6261 | sethi %hi(0x33800), %r27 |
| 6262 | #else |
| 6263 | sethi %hi(0x30000), %r27 |
| 6264 | #endif |
| 6265 | andn %r28, %r27, %r28 |
| 6266 | ta T_CHANGE_HPRIV |
| 6267 | stxa %r28, [%g0] 0x73 |
| 6268 | intvec_20_93: |
| 6269 | .word 0x93b0c4c9 ! 130: FCMPNE32 fcmpne32 %d34, %d40, %r9 |
| 6270 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 6271 | memptr_20_95: |
| 6272 | set 0x60140000, %r31 |
| 6273 | .word 0x8584bc28 ! 132: WRCCR_I wr %r18, 0x1c28, %ccr |
| 6274 | splash_hpstate_20_96: |
| 6275 | .word 0x3c800001 ! 1: BPOS bpos,a <label_0x1> |
| 6276 | .word 0x8198368f ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x168f, %hpstate |
| 6277 | jmptr_20_97: |
| 6278 | nop |
| 6279 | best_set_reg(0xe1a00000, %r20, %r27) |
| 6280 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 6281 | bleu,a skip_20_98 |
| 6282 | stxa %r11, [%r0] ASI_LSU_CONTROL |
| 6283 | .word 0x9f80367d ! 1: SIR sir 0x167d |
| 6284 | stxa %r16, [%r0] ASI_LSU_CONTROL |
| 6285 | .align 128 |
| 6286 | skip_20_98: |
| 6287 | .word 0xc32fc000 ! 135: STXFSR_R st-sfr %f1, [%r0, %r31] |
| 6288 | .word 0x8d9030e8 ! 136: WRPR_PSTATE_I wrpr %r0, 0x10e8, %pstate |
| 6289 | .word 0x99a00168 ! 137: FABSq dis not found |
| 6290 | |
| 6291 | nop |
| 6292 | ta T_CHANGE_HPRIV |
| 6293 | mov 0x20, %r10 |
| 6294 | set sync_thr_counter6, %r23 |
| 6295 | #ifndef SPC |
| 6296 | ldxa [%g0]0x63, %o1 |
| 6297 | and %o1, 0x38, %o1 |
| 6298 | add %o1, %r23, %r23 |
| 6299 | #endif |
| 6300 | cas [%r23],%g0,%r10 !lock |
| 6301 | brnz %r10, sma_20_101 |
| 6302 | rd %asi, %r12 |
| 6303 | wr %g0, 0x40, %asi |
| 6304 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6305 | set 0x000e1fff, %g1 |
| 6306 | stxa %g1, [%g0 + 0x80] %asi |
| 6307 | wr %r12, %g0, %asi |
| 6308 | st %g0, [%r23] |
| 6309 | sma_20_101: |
| 6310 | ta T_CHANGE_NONHPRIV |
| 6311 | .word 0xe1e7e010 ! 138: CASA_R casa [%r31] %asi, %r16, %r16 |
| 6312 | .word 0xa7b140e7 ! 139: EDGE16LN edge16ln %r5, %r7, %r19 |
| 6313 | splash_lsu_20_103: |
| 6314 | nop |
| 6315 | ta T_CHANGE_HPRIV |
| 6316 | set 0x86b1693a, %r2 |
| 6317 | mov 0x3, %r1 |
| 6318 | sllx %r1, 32, %r1 |
| 6319 | or %r1, %r2, %r2 |
| 6320 | .word 0x30800001 ! 1: BA ba,a <label_0x1> |
| 6321 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6322 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6323 | .word 0x95684011 ! 141: SDIVX_R sdivx %r1, %r17, %r10 |
| 6324 | .word 0xe19fe000 ! 142: LDDFA_I ldda [%r31, 0x0000], %f16 |
| 6325 | .word 0x91940001 ! 143: WRPR_PIL_R wrpr %r16, %r1, %pil |
| 6326 | splash_hpstate_20_105: |
| 6327 | ta T_CHANGE_NONHPRIV |
| 6328 | .word 0x81983d8f ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x1d8f, %hpstate |
| 6329 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 6330 | nop |
| 6331 | ta T_CHANGE_HPRIV |
| 6332 | mov 0x20, %r10 |
| 6333 | set sync_thr_counter6, %r23 |
| 6334 | #ifndef SPC |
| 6335 | ldxa [%g0]0x63, %o1 |
| 6336 | and %o1, 0x38, %o1 |
| 6337 | add %o1, %r23, %r23 |
| 6338 | #endif |
| 6339 | cas [%r23],%g0,%r10 !lock |
| 6340 | brnz %r10, sma_20_107 |
| 6341 | rd %asi, %r12 |
| 6342 | wr %g0, 0x40, %asi |
| 6343 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6344 | set 0x001a1fff, %g1 |
| 6345 | stxa %g1, [%g0 + 0x80] %asi |
| 6346 | wr %r12, %g0, %asi |
| 6347 | st %g0, [%r23] |
| 6348 | sma_20_107: |
| 6349 | ta T_CHANGE_NONHPRIV |
| 6350 | .word 0xd1e7e00b ! 146: CASA_R casa [%r31] %asi, %r11, %r8 |
| 6351 | fpinit_20_108: |
| 6352 | nop |
| 6353 | setx fp_data_quads, %r19, %r20 |
| 6354 | ldd [%r20], %f0 |
| 6355 | ldd [%r20+8], %f4 |
| 6356 | ld [%r20+16], %fsr |
| 6357 | ld [%r20+24], %r19 |
| 6358 | wr %r19, %g0, %gsr |
| 6359 | .word 0x91a009a4 ! 147: FDIVs fdivs %f0, %f4, %f8 |
| 6360 | intveclr_20_109: |
| 6361 | nop |
| 6362 | ta T_CHANGE_HPRIV |
| 6363 | setx 0xe83f03ce9e2cda7d, %r1, %r28 |
| 6364 | stxa %r28, [%g0] 0x72 |
| 6365 | ta T_CHANGE_NONHPRIV |
| 6366 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 6367 | brcommon3_20_110: |
| 6368 | nop |
| 6369 | setx common_target, %r12, %r27 |
| 6370 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 6371 | ba,a .+12 |
| 6372 | .word 0xd06fe030 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x0030] |
| 6373 | ba,a .+8 |
| 6374 | jmpl %r27+0, %r27 |
| 6375 | .word 0xd11fe060 ! 149: LDDF_I ldd [%r31, 0x0060], %f8 |
| 6376 | .word 0x3b400001 ! 1: FBPLE fble,a,pn %fcc0, <label_0x1> |
| 6377 | .word 0x8d903a23 ! 150: WRPR_PSTATE_I wrpr %r0, 0x1a23, %pstate |
| 6378 | nop |
| 6379 | nop |
| 6380 | ta T_CHANGE_PRIV |
| 6381 | wrpr %g0, %g0, %gl |
| 6382 | nop |
| 6383 | nop |
| 6384 | .text |
| 6385 | setx join_lbl_0_0, %g1, %g2 |
| 6386 | jmp %g2 |
| 6387 | nop |
| 6388 | fork_lbl_0_5: |
| 6389 | ta T_CHANGE_NONHPRIV |
| 6390 | .word 0xe877e0ba ! 1: STX_I stx %r20, [%r31 + 0x00ba] |
| 6391 | br_longdelay4_10_0: |
| 6392 | nop |
| 6393 | not %g0, %r27 |
| 6394 | jmpl %r27+0, %r27 |
| 6395 | .word 0x9d902002 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0002, %wstate |
| 6396 | .word 0xe93fe0a8 ! 3: STDF_I std %f20, [0x00a8, %r31] |
| 6397 | fpinit_10_1: |
| 6398 | nop |
| 6399 | setx fp_data_quads, %r19, %r20 |
| 6400 | ldd [%r20], %f0 |
| 6401 | ldd [%r20+8], %f4 |
| 6402 | ld [%r20+16], %fsr |
| 6403 | ld [%r20+24], %r19 |
| 6404 | wr %r19, %g0, %gsr |
| 6405 | .word 0x87a80a44 ! 4: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 6406 | splash_lsu_10_2: |
| 6407 | nop |
| 6408 | ta T_CHANGE_HPRIV |
| 6409 | set 0xd444aa0e, %r2 |
| 6410 | mov 0x3, %r1 |
| 6411 | sllx %r1, 32, %r1 |
| 6412 | or %r1, %r2, %r2 |
| 6413 | .word 0x33400001 ! 1: FBPE fbe,a,pn %fcc0, <label_0x1> |
| 6414 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6415 | ta T_CHANGE_NONHPRIV |
| 6416 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6417 | splash_hpstate_10_3: |
| 6418 | .word 0x81983f1b ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x1f1b, %hpstate |
| 6419 | memptr_10_4: |
| 6420 | set 0x60540000, %r31 |
| 6421 | .word 0x8584abeb ! 7: WRCCR_I wr %r18, 0x0beb, %ccr |
| 6422 | nop |
| 6423 | mov 0x80, %g3 |
| 6424 | .word 0x29400001 ! 1: FBPL fbl,a,pn %fcc0, <label_0x1> |
| 6425 | stxa %g3, [%g3] 0x5f |
| 6426 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 6427 | .word 0xe19fe040 ! 9: LDDFA_I ldda [%r31, 0x0040], %f16 |
| 6428 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 6429 | .word 0xe1bfc3e0 ! 11: STDFA_R stda %f16, [%r0, %r31] |
| 6430 | dvapa_10_6: |
| 6431 | nop |
| 6432 | ta T_CHANGE_HPRIV |
| 6433 | mov 0xf0d, %r20 |
| 6434 | mov 0x9, %r19 |
| 6435 | sllx %r20, 23, %r20 |
| 6436 | or %r19, %r20, %r19 |
| 6437 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 6438 | mov 0x38, %r18 |
| 6439 | stxa %r31, [%r18]0x58 |
| 6440 | ta T_CHANGE_NONHPRIV |
| 6441 | .word 0xc1bfdf20 ! 12: STDFA_R stda %f0, [%r0, %r31] |
| 6442 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 6443 | jmptr_10_7: |
| 6444 | nop |
| 6445 | best_set_reg(0xe0200000, %r20, %r27) |
| 6446 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 6447 | pmu_10_8: |
| 6448 | nop |
| 6449 | ta T_CHANGE_PRIV |
| 6450 | setx 0xffffffbcffffffac, %g1, %g7 |
| 6451 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 6452 | jmptr_10_9: |
| 6453 | nop |
| 6454 | best_set_reg(0xe0200000, %r20, %r27) |
| 6455 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 6456 | nop |
| 6457 | ta T_CHANGE_HPRIV |
| 6458 | mov 0x10, %r10 |
| 6459 | set sync_thr_counter6, %r23 |
| 6460 | #ifndef SPC |
| 6461 | ldxa [%g0]0x63, %o1 |
| 6462 | and %o1, 0x38, %o1 |
| 6463 | add %o1, %r23, %r23 |
| 6464 | #endif |
| 6465 | cas [%r23],%g0,%r10 !lock |
| 6466 | brnz %r10, sma_10_10 |
| 6467 | rd %asi, %r12 |
| 6468 | wr %g0, 0x40, %asi |
| 6469 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6470 | set 0x000a1fff, %g1 |
| 6471 | stxa %g1, [%g0 + 0x80] %asi |
| 6472 | wr %r12, %g0, %asi |
| 6473 | st %g0, [%r23] |
| 6474 | sma_10_10: |
| 6475 | ta T_CHANGE_NONHPRIV |
| 6476 | .word 0xe9e7e010 ! 17: CASA_R casa [%r31] %asi, %r16, %r20 |
| 6477 | .word 0x87802058 ! 18: WRASI_I wr %r0, 0x0058, %asi |
| 6478 | splash_lsu_10_11: |
| 6479 | nop |
| 6480 | ta T_CHANGE_HPRIV |
| 6481 | set 0xe6b9acc4, %r2 |
| 6482 | mov 0x1, %r1 |
| 6483 | sllx %r1, 32, %r1 |
| 6484 | or %r1, %r2, %r2 |
| 6485 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6486 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6487 | .word 0xe93fe169 ! 20: STDF_I std %f20, [0x0169, %r31] |
| 6488 | brcommon1_10_12: |
| 6489 | nop |
| 6490 | setx common_target, %r12, %r27 |
| 6491 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 6492 | ba,a .+12 |
| 6493 | .word 0xa9b7c7c9 ! 1: PDIST pdistn %d62, %d40, %d20 |
| 6494 | ba,a .+8 |
| 6495 | jmpl %r27+0, %r27 |
| 6496 | .word 0x87aa8a51 ! 21: FCMPd fcmpd %fcc<n>, %f10, %f48 |
| 6497 | splash_lsu_10_13: |
| 6498 | nop |
| 6499 | ta T_CHANGE_HPRIV |
| 6500 | set 0xb6e197a2, %r2 |
| 6501 | mov 0x2, %r1 |
| 6502 | sllx %r1, 32, %r1 |
| 6503 | or %r1, %r2, %r2 |
| 6504 | .word 0x32800001 ! 1: BNE bne,a <label_0x1> |
| 6505 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6506 | ta T_CHANGE_NONHPRIV |
| 6507 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6508 | .word 0xe19fd960 ! 23: LDDFA_R ldda [%r31, %r0], %f16 |
| 6509 | .word 0xe1bfda00 ! 24: STDFA_R stda %f16, [%r0, %r31] |
| 6510 | pmu_10_14: |
| 6511 | nop |
| 6512 | ta T_CHANGE_PRIV |
| 6513 | setx 0xffffffb1ffffffad, %g1, %g7 |
| 6514 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 6515 | rd %tick, %r28 |
| 6516 | #if (MAX_THREADS == 8) |
| 6517 | sethi %hi(0x33800), %r27 |
| 6518 | #else |
| 6519 | sethi %hi(0x30000), %r27 |
| 6520 | #endif |
| 6521 | andn %r28, %r27, %r28 |
| 6522 | ta T_CHANGE_HPRIV |
| 6523 | stxa %r28, [%g0] 0x73 |
| 6524 | .word 0xa7a349d4 ! 1: FDIVd fdivd %f44, %f20, %f50 |
| 6525 | intvec_10_15: |
| 6526 | .word 0x95b144d4 ! 26: FCMPNE32 fcmpne32 %d36, %d20, %r10 |
| 6527 | .word 0x91944012 ! 27: WRPR_PIL_R wrpr %r17, %r18, %pil |
| 6528 | nop |
| 6529 | mov 0x80, %g3 |
| 6530 | stxa %g3, [%g3] 0x5f |
| 6531 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 6532 | #if (defined SPC || defined CMP) |
| 6533 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_10_17)+24, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 6534 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_10_17)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 6535 | xir_10_17: |
| 6536 | #else |
| 6537 | #if (defined FC) |
| 6538 | !! Generate XIR via RESET_GEN register |
| 6539 | ta T_CHANGE_HPRIV |
| 6540 | rdpr %pstate, %r18 |
| 6541 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 6542 | wrpr %r18, %pstate |
| 6543 | #ifndef XIR_RND_CORES |
| 6544 | ldxa [%g0] 0x63, %o1 |
| 6545 | mov 1, %r18 |
| 6546 | sllx %r18, %o1, %r18 |
| 6547 | #endif |
| 6548 | mov 0x30, %r19 |
| 6549 | setx 0x8900000808, %r16, %r17 |
| 6550 | mov 0x2, %r16 |
| 6551 | xir_10_17: |
| 6552 | stxa %r18, [%r19] 0x41 |
| 6553 | stx %r16, [%r17] |
| 6554 | #endif |
| 6555 | #endif |
| 6556 | .word 0xa9852545 ! 29: WR_SET_SOFTINT_I wr %r20, 0x0545, %set_softint |
| 6557 | .word 0xa7a00161 ! 30: FABSq dis not found |
| 6558 | |
| 6559 | .word 0xa3a00167 ! 31: FABSq dis not found |
| 6560 | |
| 6561 | tagged_10_20: |
| 6562 | tsubcctv %r6, 0x1575, %r16 |
| 6563 | .word 0xd807e1d1 ! 32: LDUW_I lduw [%r31 + 0x01d1], %r12 |
| 6564 | mondo_10_21: |
| 6565 | nop |
| 6566 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 6567 | stxa %r2, [%r0+0x3e0] %asi |
| 6568 | .word 0x9d940010 ! 33: WRPR_WSTATE_R wrpr %r16, %r16, %wstate |
| 6569 | .word 0xb181800b ! 34: WR_STICK_REG_R wr %r6, %r11, %- |
| 6570 | nop |
| 6571 | ta T_CHANGE_HPRIV |
| 6572 | mov 0x10, %r10 |
| 6573 | set sync_thr_counter6, %r23 |
| 6574 | #ifndef SPC |
| 6575 | ldxa [%g0]0x63, %o1 |
| 6576 | and %o1, 0x38, %o1 |
| 6577 | add %o1, %r23, %r23 |
| 6578 | #endif |
| 6579 | cas [%r23],%g0,%r10 !lock |
| 6580 | brnz %r10, sma_10_22 |
| 6581 | rd %asi, %r12 |
| 6582 | wr %g0, 0x40, %asi |
| 6583 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6584 | set 0x00161fff, %g1 |
| 6585 | stxa %g1, [%g0 + 0x80] %asi |
| 6586 | wr %r12, %g0, %asi |
| 6587 | st %g0, [%r23] |
| 6588 | sma_10_22: |
| 6589 | ta T_CHANGE_NONHPRIV |
| 6590 | .word 0xd9e7e00b ! 35: CASA_R casa [%r31] %asi, %r11, %r12 |
| 6591 | nop |
| 6592 | ta T_CHANGE_HPRIV |
| 6593 | mov 0x10, %r10 |
| 6594 | set sync_thr_counter6, %r23 |
| 6595 | #ifndef SPC |
| 6596 | ldxa [%g0]0x63, %o1 |
| 6597 | and %o1, 0x38, %o1 |
| 6598 | add %o1, %r23, %r23 |
| 6599 | #endif |
| 6600 | cas [%r23],%g0,%r10 !lock |
| 6601 | brnz %r10, sma_10_23 |
| 6602 | rd %asi, %r12 |
| 6603 | wr %g0, 0x40, %asi |
| 6604 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6605 | set 0x00021fff, %g1 |
| 6606 | stxa %g1, [%g0 + 0x80] %asi |
| 6607 | wr %r12, %g0, %asi |
| 6608 | st %g0, [%r23] |
| 6609 | sma_10_23: |
| 6610 | ta T_CHANGE_NONHPRIV |
| 6611 | .word 0xd9e7e010 ! 36: CASA_R casa [%r31] %asi, %r16, %r12 |
| 6612 | splash_tba_10_24: |
| 6613 | nop |
| 6614 | ta T_CHANGE_PRIV |
| 6615 | set 0x120000, %r12 |
| 6616 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 6617 | splash_lsu_10_25: |
| 6618 | nop |
| 6619 | ta T_CHANGE_HPRIV |
| 6620 | set 0x7295da7d, %r2 |
| 6621 | mov 0x6, %r1 |
| 6622 | sllx %r1, 32, %r1 |
| 6623 | or %r1, %r2, %r2 |
| 6624 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6625 | ta T_CHANGE_NONHPRIV |
| 6626 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6627 | #if (defined SPC || defined CMP1) |
| 6628 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_26) + 40, 16, 16)) -> intp(6,0,11,,,,,1) |
| 6629 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_26)&0xffffffff) + 48, 16, 16)) -> intp(2,0,27,,,,,1) |
| 6630 | #else |
| 6631 | set 0xe58091ce, %r28 |
| 6632 | #if (MAX_THREADS == 8) |
| 6633 | and %r28, 0x7ff, %r28 |
| 6634 | #endif |
| 6635 | stxa %r28, [%g0] 0x73 |
| 6636 | #endif |
| 6637 | .word 0x9ba489c3 ! 1: FDIVd fdivd %f18, %f34, %f44 |
| 6638 | intvec_10_26: |
| 6639 | .word 0xa7b284d0 ! 39: FCMPNE32 fcmpne32 %d10, %d16, %r19 |
| 6640 | .word 0xd727e0e0 ! 40: STF_I st %f11, [0x00e0, %r31] |
| 6641 | .word 0xd627e09e ! 41: STW_I stw %r11, [%r31 + 0x009e] |
| 6642 | jmptr_10_27: |
| 6643 | nop |
| 6644 | best_set_reg(0xe0200000, %r20, %r27) |
| 6645 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 6646 | splash_tba_10_28: |
| 6647 | nop |
| 6648 | ta T_CHANGE_PRIV |
| 6649 | set 0x120000, %r12 |
| 6650 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 6651 | set 0x1ee4, %l3 |
| 6652 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 6653 | .word 0x97b487c4 ! 44: PDIST pdistn %d18, %d4, %d42 |
| 6654 | pmu_10_29: |
| 6655 | nop |
| 6656 | setx 0xffffffb5ffffffa7, %g1, %g7 |
| 6657 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 6658 | brcommon3_10_30: |
| 6659 | nop |
| 6660 | setx common_target, %r12, %r27 |
| 6661 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 6662 | ba,a .+12 |
| 6663 | .word 0xe3e7c032 ! 1: CASA_I casa [%r31] 0x 1, %r18, %r17 |
| 6664 | ba,a .+8 |
| 6665 | jmpl %r27+0, %r27 |
| 6666 | .word 0xe29fe1c0 ! 46: LDDA_I ldda [%r31, + 0x01c0] %asi, %r17 |
| 6667 | brcommon3_10_31: |
| 6668 | nop |
| 6669 | setx common_target, %r12, %r27 |
| 6670 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 6671 | ba,a .+12 |
| 6672 | .word 0xe26fe0d0 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x00d0] |
| 6673 | ba,a .+8 |
| 6674 | jmpl %r27+0, %r27 |
| 6675 | stxa %r12, [%r0] ASI_LSU_CONTROL |
| 6676 | .word 0x95aac830 ! 47: FMOVGE fmovs %fcc1, %f16, %f10 |
| 6677 | brcommon3_10_32: |
| 6678 | nop |
| 6679 | setx common_target, %r12, %r27 |
| 6680 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 6681 | ba,a .+12 |
| 6682 | .word 0xd737e160 ! 1: STQF_I - %f11, [0x0160, %r31] |
| 6683 | ba,a .+8 |
| 6684 | jmpl %r27+0, %r27 |
| 6685 | .word 0xd69fc032 ! 48: LDDA_R ldda [%r31, %r18] 0x01, %r11 |
| 6686 | nop |
| 6687 | mov 0x80, %g3 |
| 6688 | .word 0x2e800001 ! 1: BVS bvs,a <label_0x1> |
| 6689 | stxa %g3, [%g3] 0x5f |
| 6690 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 6691 | nop |
| 6692 | ta T_CHANGE_HPRIV ! macro |
| 6693 | donret_10_33: |
| 6694 | rd %pc, %r12 |
| 6695 | mov HIGHVA_HIGHNUM, %r10 |
| 6696 | sllx %r10, 32, %r10 |
| 6697 | or %r12, %r10, %r12 |
| 6698 | add %r12, (donretarg_10_33-donret_10_33), %r12 |
| 6699 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 6700 | andn %r11, %r10, %r11 ! low VA tnpc |
| 6701 | wrpr %g0, 0x1, %tl |
| 6702 | wrpr %g0, %r12, %tpc |
| 6703 | wrpr %g0, %r11, %tnpc |
| 6704 | set (0x00454600 | (0x89 << 24)), %r13 |
| 6705 | and %r12, 0xfff, %r14 |
| 6706 | sllx %r14, 32, %r14 |
| 6707 | or %r13, %r14, %r20 |
| 6708 | wrpr %r20, %g0, %tstate |
| 6709 | wrhpr %g0, 0x190f, %htstate |
| 6710 | ta T_CHANGE_NONHPRIV ! rand=1 (10) |
| 6711 | ldx [%r11+%r0], %g1 |
| 6712 | done |
| 6713 | donretarg_10_33: |
| 6714 | .word 0x26c98001 ! 50: BRLZ brlz,a,pt %r6,<label_0x98001> |
| 6715 | #if (defined SPC || defined CMP1) |
| 6716 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_34) + 48, 16, 16)) -> intp(6,0,9,,,,,1) |
| 6717 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_34)&0xffffffff) + 48, 16, 16)) -> intp(4,0,19,,,,,1) |
| 6718 | #else |
| 6719 | set 0xcfb0985c, %r28 |
| 6720 | #if (MAX_THREADS == 8) |
| 6721 | and %r28, 0x7ff, %r28 |
| 6722 | #endif |
| 6723 | stxa %r28, [%g0] 0x73 |
| 6724 | #endif |
| 6725 | intvec_10_34: |
| 6726 | .word 0x39400001 ! 51: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 6727 | .word 0xe927e123 ! 52: STF_I st %f20, [0x0123, %r31] |
| 6728 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 6729 | splash_tba_10_35: |
| 6730 | nop |
| 6731 | ta T_CHANGE_PRIV |
| 6732 | setx 0x0000000000380000, %r11, %r12 |
| 6733 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 6734 | .word 0xc3ea0023 ! 55: PREFETCHA_R prefetcha [%r8, %r3] 0x01, #one_read |
| 6735 | ibp_10_37: |
| 6736 | nop |
| 6737 | ta T_CHANGE_NONHPRIV |
| 6738 | .word 0xa7a349c7 ! 56: FDIVd fdivd %f44, %f38, %f50 |
| 6739 | brcommon3_10_38: |
| 6740 | nop |
| 6741 | setx common_target, %r12, %r27 |
| 6742 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 6743 | ba,a .+12 |
| 6744 | .word 0xe937e0f0 ! 1: STQF_I - %f20, [0x00f0, %r31] |
| 6745 | ba,a .+8 |
| 6746 | jmpl %r27+0, %r27 |
| 6747 | .word 0xe8dfc032 ! 57: LDXA_R ldxa [%r31, %r18] 0x01, %r20 |
| 6748 | ibp_10_39: |
| 6749 | nop |
| 6750 | ta T_CHANGE_NONHPRIV |
| 6751 | .word 0xa5702576 ! 58: POPC_I popc 0x0576, %r18 |
| 6752 | nop |
| 6753 | ta T_CHANGE_HPRIV ! macro |
| 6754 | donret_10_40: |
| 6755 | rd %pc, %r12 |
| 6756 | mov HIGHVA_HIGHNUM, %r10 |
| 6757 | sllx %r10, 32, %r10 |
| 6758 | or %r12, %r10, %r12 |
| 6759 | add %r12, (donretarg_10_40-donret_10_40+4), %r12 |
| 6760 | add %r12, 0x4, %r11 ! seq tnpc |
| 6761 | andn %r12, %r10, %r12 ! low VA tpc |
| 6762 | wrpr %g0, 0x1, %tl |
| 6763 | wrpr %g0, %r12, %tpc |
| 6764 | wrpr %g0, %r11, %tnpc |
| 6765 | set (0x00e23500 | (54 << 24)), %r13 |
| 6766 | and %r12, 0xfff, %r14 |
| 6767 | sllx %r14, 32, %r14 |
| 6768 | or %r13, %r14, %r20 |
| 6769 | wrpr %r20, %g0, %tstate |
| 6770 | wrhpr %g0, 0x1f5e, %htstate |
| 6771 | ta T_CHANGE_NONPRIV ! rand=0 (10) |
| 6772 | ldx [%r12+%r0], %g1 |
| 6773 | retry |
| 6774 | donretarg_10_40: |
| 6775 | .word 0x27400001 ! 59: FBPUL fbul,a,pn %fcc0, <label_0x1> |
| 6776 | memptr_10_41: |
| 6777 | set 0x60140000, %r31 |
| 6778 | .word 0x8584f3df ! 60: WRCCR_I wr %r19, 0x13df, %ccr |
| 6779 | nop |
| 6780 | mov 0x80, %g3 |
| 6781 | stxa %g3, [%g3] 0x57 |
| 6782 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 6783 | .word 0xa953c000 ! 62: RDPR_FQ <illegal instruction> |
| 6784 | .word 0x9ba049cc ! 63: FDIVd fdivd %f32, %f12, %f44 |
| 6785 | .word 0xc36fe052 ! 64: PREFETCH_I prefetch [%r31 + 0x0052], #one_read |
| 6786 | .word 0xe19fd960 ! 65: LDDFA_R ldda [%r31, %r0], %f16 |
| 6787 | nop |
| 6788 | ta T_CHANGE_HPRIV |
| 6789 | mov 0x10+1, %r10 |
| 6790 | set sync_thr_counter5, %r23 |
| 6791 | #ifndef SPC |
| 6792 | ldxa [%g0]0x63, %o1 |
| 6793 | and %o1, 0x38, %o1 |
| 6794 | add %o1, %r23, %r23 |
| 6795 | sllx %o1, 5, %o3 !(CID*256) |
| 6796 | #endif |
| 6797 | cas [%r23],%g0,%r10 !lock |
| 6798 | brnz %r10, cwq_10_44 |
| 6799 | rd %asi, %r12 |
| 6800 | wr %g0, 0x40, %asi |
| 6801 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 6802 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 6803 | cmp %l1, 1 |
| 6804 | bne cwq_10_44 |
| 6805 | set CWQ_BASE, %l6 |
| 6806 | #ifndef SPC |
| 6807 | add %l6, %o3, %l6 |
| 6808 | #endif |
| 6809 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 6810 | best_set_reg(0x206100b0, %l1, %l2) !# Control Word |
| 6811 | sllx %l2, 32, %l2 |
| 6812 | stx %l2, [%l6 + 0x0] |
| 6813 | membar #Sync |
| 6814 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 6815 | sub %l2, 0x40, %l2 |
| 6816 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 6817 | wr %r12, %g0, %asi |
| 6818 | st %g0, [%r23] |
| 6819 | cwq_10_44: |
| 6820 | ta T_CHANGE_NONHPRIV |
| 6821 | .word 0xa3414000 ! 66: RDPC rd %pc, %r17 |
| 6822 | mondo_10_45: |
| 6823 | nop |
| 6824 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 6825 | ta T_CHANGE_PRIV |
| 6826 | stxa %r12, [%r0+0x3e0] %asi |
| 6827 | .word 0x9d914001 ! 67: WRPR_WSTATE_R wrpr %r5, %r1, %wstate |
| 6828 | .word 0xa5a00165 ! 68: FABSq dis not found |
| 6829 | |
| 6830 | .word 0x91950012 ! 69: WRPR_PIL_R wrpr %r20, %r18, %pil |
| 6831 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 6832 | #if (defined SPC || defined CMP) |
| 6833 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_10_49)+0, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 6834 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_10_49)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 6835 | xir_10_49: |
| 6836 | #else |
| 6837 | #if (defined FC) |
| 6838 | !! Generate XIR via RESET_GEN register |
| 6839 | ta T_CHANGE_HPRIV |
| 6840 | rdpr %pstate, %r18 |
| 6841 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 6842 | wrpr %r18, %pstate |
| 6843 | #ifndef XIR_RND_CORES |
| 6844 | ldxa [%g0] 0x63, %o1 |
| 6845 | mov 1, %r18 |
| 6846 | sllx %r18, %o1, %r18 |
| 6847 | #endif |
| 6848 | mov 0x30, %r19 |
| 6849 | setx 0x8900000808, %r16, %r17 |
| 6850 | mov 0x2, %r16 |
| 6851 | xir_10_49: |
| 6852 | stxa %r18, [%r19] 0x41 |
| 6853 | stx %r16, [%r17] |
| 6854 | #endif |
| 6855 | #endif |
| 6856 | .word 0xa984b66f ! 71: WR_SET_SOFTINT_I wr %r18, 0x166f, %set_softint |
| 6857 | #if (defined SPC || defined CMP1) |
| 6858 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_50) + 56, 16, 16)) -> intp(3,0,27,,,,,1) |
| 6859 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_50)&0xffffffff) + 32, 16, 16)) -> intp(1,0,17,,,,,1) |
| 6860 | #else |
| 6861 | set 0x2da06a2d, %r28 |
| 6862 | #if (MAX_THREADS == 8) |
| 6863 | and %r28, 0x7ff, %r28 |
| 6864 | #endif |
| 6865 | stxa %r28, [%g0] 0x73 |
| 6866 | #endif |
| 6867 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 6868 | intvec_10_50: |
| 6869 | .word 0x39400001 ! 72: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 6870 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 6871 | nop |
| 6872 | mov 0x80, %g3 |
| 6873 | stxa %g3, [%g3] 0x5f |
| 6874 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 6875 | nop |
| 6876 | ta T_CHANGE_HPRIV |
| 6877 | mov 0x10, %r10 |
| 6878 | set sync_thr_counter6, %r23 |
| 6879 | #ifndef SPC |
| 6880 | ldxa [%g0]0x63, %o1 |
| 6881 | and %o1, 0x38, %o1 |
| 6882 | add %o1, %r23, %r23 |
| 6883 | #endif |
| 6884 | cas [%r23],%g0,%r10 !lock |
| 6885 | brnz %r10, sma_10_52 |
| 6886 | rd %asi, %r12 |
| 6887 | wr %g0, 0x40, %asi |
| 6888 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6889 | set 0x001e1fff, %g1 |
| 6890 | stxa %g1, [%g0 + 0x80] %asi |
| 6891 | wr %r12, %g0, %asi |
| 6892 | st %g0, [%r23] |
| 6893 | sma_10_52: |
| 6894 | ta T_CHANGE_NONHPRIV |
| 6895 | .word 0xe5e7e00d ! 75: CASA_R casa [%r31] %asi, %r13, %r18 |
| 6896 | .word 0x91944011 ! 76: WRPR_PIL_R wrpr %r17, %r17, %pil |
| 6897 | pmu_10_54: |
| 6898 | nop |
| 6899 | setx 0xffffffbcffffffa8, %g1, %g7 |
| 6900 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 6901 | fpinit_10_55: |
| 6902 | nop |
| 6903 | setx fp_data_quads, %r19, %r20 |
| 6904 | ldd [%r20], %f0 |
| 6905 | ldd [%r20+8], %f4 |
| 6906 | ld [%r20+16], %fsr |
| 6907 | ld [%r20+24], %r19 |
| 6908 | wr %r19, %g0, %gsr |
| 6909 | .word 0xc3e82b59 ! 78: PREFETCHA_I prefetcha [%r0, + 0x0b59] %asi, #one_read |
| 6910 | jmptr_10_56: |
| 6911 | nop |
| 6912 | best_set_reg(0xe0200000, %r20, %r27) |
| 6913 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 6914 | nop |
| 6915 | mov 0x80, %g3 |
| 6916 | stxa %g3, [%g3] 0x57 |
| 6917 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 6918 | .word 0xa9b300f0 ! 81: EDGE16LN edge16ln %r12, %r16, %r20 |
| 6919 | #if (defined SPC || defined CMP1) |
| 6920 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_58) + 24, 16, 16)) -> intp(3,0,16,,,,,1) |
| 6921 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_58)&0xffffffff) + 16, 16, 16)) -> intp(3,0,20,,,,,1) |
| 6922 | #else |
| 6923 | set 0xc706138, %r28 |
| 6924 | #if (MAX_THREADS == 8) |
| 6925 | and %r28, 0x7ff, %r28 |
| 6926 | #endif |
| 6927 | stxa %r28, [%g0] 0x73 |
| 6928 | #endif |
| 6929 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 6930 | intvec_10_58: |
| 6931 | .word 0x9f802b35 ! 82: SIR sir 0x0b35 |
| 6932 | nop |
| 6933 | ta T_CHANGE_HPRIV |
| 6934 | mov 0x10, %r10 |
| 6935 | set sync_thr_counter6, %r23 |
| 6936 | #ifndef SPC |
| 6937 | ldxa [%g0]0x63, %o1 |
| 6938 | and %o1, 0x38, %o1 |
| 6939 | add %o1, %r23, %r23 |
| 6940 | #endif |
| 6941 | cas [%r23],%g0,%r10 !lock |
| 6942 | brnz %r10, sma_10_59 |
| 6943 | rd %asi, %r12 |
| 6944 | wr %g0, 0x40, %asi |
| 6945 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 6946 | set 0x001e1fff, %g1 |
| 6947 | stxa %g1, [%g0 + 0x80] %asi |
| 6948 | wr %r12, %g0, %asi |
| 6949 | st %g0, [%r23] |
| 6950 | sma_10_59: |
| 6951 | ta T_CHANGE_NONHPRIV |
| 6952 | .word 0xe5e7e011 ! 83: CASA_R casa [%r31] %asi, %r17, %r18 |
| 6953 | fpinit_10_60: |
| 6954 | nop |
| 6955 | setx fp_data_quads, %r19, %r20 |
| 6956 | ldd [%r20], %f0 |
| 6957 | ldd [%r20+8], %f4 |
| 6958 | ld [%r20+16], %fsr |
| 6959 | ld [%r20+24], %r19 |
| 6960 | wr %r19, %g0, %gsr |
| 6961 | .word 0x91a009a4 ! 84: FDIVs fdivs %f0, %f4, %f8 |
| 6962 | .word 0x8780201c ! 85: WRASI_I wr %r0, 0x001c, %asi |
| 6963 | .word 0xe19fdf20 ! 86: LDDFA_R ldda [%r31, %r0], %f16 |
| 6964 | splash_lsu_10_61: |
| 6965 | nop |
| 6966 | ta T_CHANGE_HPRIV |
| 6967 | set 0xbb0bac49, %r2 |
| 6968 | mov 0x1, %r1 |
| 6969 | sllx %r1, 32, %r1 |
| 6970 | or %r1, %r2, %r2 |
| 6971 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6972 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6973 | splash_lsu_10_62: |
| 6974 | nop |
| 6975 | ta T_CHANGE_HPRIV |
| 6976 | set 0x6b94383a, %r2 |
| 6977 | mov 0x1, %r1 |
| 6978 | sllx %r1, 32, %r1 |
| 6979 | or %r1, %r2, %r2 |
| 6980 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 6981 | ta T_CHANGE_NONHPRIV |
| 6982 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 6983 | splash_cmpr_10_63: |
| 6984 | mov 1, %r18 |
| 6985 | sllx %r18, 63, %r18 |
| 6986 | rd %tick, %r17 |
| 6987 | add %r17, 0x80, %r17 |
| 6988 | or %r17, %r18, %r17 |
| 6989 | ta T_CHANGE_HPRIV |
| 6990 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 6991 | .word 0xb3800011 ! 89: WR_STICK_CMPR_REG_R wr %r0, %r17, %- |
| 6992 | nop |
| 6993 | mov 0x80, %g3 |
| 6994 | .word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1> |
| 6995 | stxa %g3, [%g3] 0x57 |
| 6996 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 6997 | splash_tba_10_64: |
| 6998 | nop |
| 6999 | ta T_CHANGE_PRIV |
| 7000 | set 0x120000, %r12 |
| 7001 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 7002 | dvapa_10_65: |
| 7003 | nop |
| 7004 | ta T_CHANGE_HPRIV |
| 7005 | mov 0xddf, %r20 |
| 7006 | mov 0x11, %r19 |
| 7007 | sllx %r20, 23, %r20 |
| 7008 | or %r19, %r20, %r19 |
| 7009 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 7010 | mov 0x38, %r18 |
| 7011 | stxa %r31, [%r18]0x58 |
| 7012 | ta T_CHANGE_NONHPRIV |
| 7013 | .word 0xe51fe070 ! 92: LDDF_I ldd [%r31, 0x0070], %f18 |
| 7014 | splash_lsu_10_66: |
| 7015 | nop |
| 7016 | ta T_CHANGE_HPRIV |
| 7017 | set 0x7e537379, %r2 |
| 7018 | mov 0x7, %r1 |
| 7019 | sllx %r1, 32, %r1 |
| 7020 | or %r1, %r2, %r2 |
| 7021 | .word 0x34800001 ! 1: BG bg,a <label_0x1> |
| 7022 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7023 | ta T_CHANGE_NONHPRIV |
| 7024 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7025 | ibp_10_67: |
| 7026 | nop |
| 7027 | .word 0xe5e7e008 ! 94: CASA_R casa [%r31] %asi, %r8, %r18 |
| 7028 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 7029 | nop |
| 7030 | ta T_CHANGE_HPRIV |
| 7031 | mov 0x10, %r10 |
| 7032 | set sync_thr_counter6, %r23 |
| 7033 | #ifndef SPC |
| 7034 | ldxa [%g0]0x63, %o1 |
| 7035 | and %o1, 0x38, %o1 |
| 7036 | add %o1, %r23, %r23 |
| 7037 | #endif |
| 7038 | cas [%r23],%g0,%r10 !lock |
| 7039 | brnz %r10, sma_10_68 |
| 7040 | rd %asi, %r12 |
| 7041 | wr %g0, 0x40, %asi |
| 7042 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7043 | set 0x000e1fff, %g1 |
| 7044 | stxa %g1, [%g0 + 0x80] %asi |
| 7045 | wr %r12, %g0, %asi |
| 7046 | st %g0, [%r23] |
| 7047 | sma_10_68: |
| 7048 | ta T_CHANGE_NONHPRIV |
| 7049 | .word 0xe5e7e00a ! 96: CASA_R casa [%r31] %asi, %r10, %r18 |
| 7050 | #if (defined SPC || defined CMP) |
| 7051 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_10_69)+8, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 7052 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_10_69)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 7053 | xir_10_69: |
| 7054 | #else |
| 7055 | #if (defined FC) |
| 7056 | !! Generate XIR via RESET_GEN register |
| 7057 | ta T_CHANGE_HPRIV |
| 7058 | rdpr %pstate, %r18 |
| 7059 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 7060 | wrpr %r18, %pstate |
| 7061 | #ifndef XIR_RND_CORES |
| 7062 | ldxa [%g0] 0x63, %o1 |
| 7063 | mov 1, %r18 |
| 7064 | sllx %r18, %o1, %r18 |
| 7065 | #endif |
| 7066 | mov 0x30, %r19 |
| 7067 | setx 0x8900000808, %r16, %r17 |
| 7068 | mov 0x2, %r16 |
| 7069 | xir_10_69: |
| 7070 | stxa %r18, [%r19] 0x41 |
| 7071 | stx %r16, [%r17] |
| 7072 | #endif |
| 7073 | #endif |
| 7074 | .word 0xa982e29f ! 97: WR_SET_SOFTINT_I wr %r11, 0x029f, %set_softint |
| 7075 | #if (defined SPC || defined CMP1) |
| 7076 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_70) + 56, 16, 16)) -> intp(0,0,31,,,,,1) |
| 7077 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_10_70)&0xffffffff) + 56, 16, 16)) -> intp(4,0,24,,,,,1) |
| 7078 | #else |
| 7079 | set 0xe8b05005, %r28 |
| 7080 | #if (MAX_THREADS == 8) |
| 7081 | and %r28, 0x7ff, %r28 |
| 7082 | #endif |
| 7083 | stxa %r28, [%g0] 0x73 |
| 7084 | #endif |
| 7085 | intvec_10_70: |
| 7086 | .word 0x97b0c4c2 ! 98: FCMPNE32 fcmpne32 %d34, %d2, %r11 |
| 7087 | fpinit_10_71: |
| 7088 | nop |
| 7089 | setx fp_data_quads, %r19, %r20 |
| 7090 | ldd [%r20], %f0 |
| 7091 | ldd [%r20+8], %f4 |
| 7092 | ld [%r20+16], %fsr |
| 7093 | ld [%r20+24], %r19 |
| 7094 | wr %r19, %g0, %gsr |
| 7095 | .word 0x89a009c4 ! 99: FDIVd fdivd %f0, %f4, %f4 |
| 7096 | splash_lsu_10_72: |
| 7097 | nop |
| 7098 | ta T_CHANGE_HPRIV |
| 7099 | set 0xbcb37f43, %r2 |
| 7100 | mov 0x6, %r1 |
| 7101 | sllx %r1, 32, %r1 |
| 7102 | or %r1, %r2, %r2 |
| 7103 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7104 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7105 | .word 0xa3b340f4 ! 101: EDGE16LN edge16ln %r13, %r20, %r17 |
| 7106 | nop |
| 7107 | ta T_CHANGE_HPRIV |
| 7108 | mov 0x10, %r10 |
| 7109 | set sync_thr_counter6, %r23 |
| 7110 | #ifndef SPC |
| 7111 | ldxa [%g0]0x63, %o1 |
| 7112 | and %o1, 0x38, %o1 |
| 7113 | add %o1, %r23, %r23 |
| 7114 | #endif |
| 7115 | cas [%r23],%g0,%r10 !lock |
| 7116 | brnz %r10, sma_10_74 |
| 7117 | rd %asi, %r12 |
| 7118 | wr %g0, 0x40, %asi |
| 7119 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7120 | set 0x001e1fff, %g1 |
| 7121 | stxa %g1, [%g0 + 0x80] %asi |
| 7122 | wr %r12, %g0, %asi |
| 7123 | st %g0, [%r23] |
| 7124 | sma_10_74: |
| 7125 | ta T_CHANGE_NONHPRIV |
| 7126 | .word 0xd7e7e00c ! 102: CASA_R casa [%r31] %asi, %r12, %r11 |
| 7127 | nop |
| 7128 | mov 0x80, %g3 |
| 7129 | .word 0x24800001 ! 1: BLE ble,a <label_0x1> |
| 7130 | stxa %g3, [%g3] 0x5f |
| 7131 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 7132 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 7133 | .word 0xe1bfc2c0 ! 105: STDFA_R stda %f16, [%r0, %r31] |
| 7134 | splash_lsu_10_77: |
| 7135 | nop |
| 7136 | ta T_CHANGE_HPRIV |
| 7137 | set 0x64c258e9, %r2 |
| 7138 | mov 0x3, %r1 |
| 7139 | sllx %r1, 32, %r1 |
| 7140 | or %r1, %r2, %r2 |
| 7141 | .word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1> |
| 7142 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7143 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7144 | .word 0xc1bfdf20 ! 107: STDFA_R stda %f0, [%r0, %r31] |
| 7145 | .word 0x91948011 ! 108: WRPR_PIL_R wrpr %r18, %r17, %pil |
| 7146 | splash_lsu_10_79: |
| 7147 | nop |
| 7148 | ta T_CHANGE_HPRIV |
| 7149 | set 0xfb87e10c, %r2 |
| 7150 | mov 0x2, %r1 |
| 7151 | sllx %r1, 32, %r1 |
| 7152 | or %r1, %r2, %r2 |
| 7153 | .word 0x38800001 ! 1: BGU bgu,a <label_0x1> |
| 7154 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7155 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7156 | .word 0xc1bfdc00 ! 110: STDFA_R stda %f0, [%r0, %r31] |
| 7157 | .word 0x99b344c7 ! 111: FCMPNE32 fcmpne32 %d44, %d38, %r12 |
| 7158 | .word 0xe1bfc3e0 ! 112: STDFA_R stda %f16, [%r0, %r31] |
| 7159 | rd %tick, %r28 |
| 7160 | #if (MAX_THREADS == 8) |
| 7161 | sethi %hi(0x33800), %r27 |
| 7162 | #else |
| 7163 | sethi %hi(0x30000), %r27 |
| 7164 | #endif |
| 7165 | andn %r28, %r27, %r28 |
| 7166 | ta T_CHANGE_HPRIV |
| 7167 | stxa %r28, [%g0] 0x73 |
| 7168 | intvec_10_81: |
| 7169 | .word 0x91a409d2 ! 113: FDIVd fdivd %f16, %f18, %f8 |
| 7170 | .word 0xe1bfe0e0 ! 114: STDFA_I stda %f16, [0x00e0, %r31] |
| 7171 | nop |
| 7172 | mov 0x80, %g3 |
| 7173 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 7174 | stxa %g3, [%g3] 0x5f |
| 7175 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 7176 | jmptr_10_82: |
| 7177 | nop |
| 7178 | best_set_reg(0xe0200000, %r20, %r27) |
| 7179 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 7180 | splash_tba_10_83: |
| 7181 | nop |
| 7182 | ta T_CHANGE_PRIV |
| 7183 | setx 0x0000000000380000, %r11, %r12 |
| 7184 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 7185 | .word 0x91914012 ! 118: WRPR_PIL_R wrpr %r5, %r18, %pil |
| 7186 | #if (defined SPC || defined CMP) |
| 7187 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_10_85)+8, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 7188 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_10_85)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 7189 | xir_10_85: |
| 7190 | #else |
| 7191 | #if (defined FC) |
| 7192 | !! Generate XIR via RESET_GEN register |
| 7193 | ta T_CHANGE_HPRIV |
| 7194 | rdpr %pstate, %r18 |
| 7195 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 7196 | wrpr %r18, %pstate |
| 7197 | #ifndef XIR_RND_CORES |
| 7198 | ldxa [%g0] 0x63, %o1 |
| 7199 | mov 1, %r18 |
| 7200 | sllx %r18, %o1, %r18 |
| 7201 | #endif |
| 7202 | mov 0x30, %r19 |
| 7203 | setx 0x8900000808, %r16, %r17 |
| 7204 | mov 0x2, %r16 |
| 7205 | xir_10_85: |
| 7206 | stxa %r18, [%r19] 0x41 |
| 7207 | stx %r16, [%r17] |
| 7208 | #endif |
| 7209 | #endif |
| 7210 | .word 0xa982a580 ! 119: WR_SET_SOFTINT_I wr %r10, 0x0580, %set_softint |
| 7211 | cwp_10_86: |
| 7212 | set user_data_start, %o7 |
| 7213 | .word 0x93902005 ! 120: WRPR_CWP_I wrpr %r0, 0x0005, %cwp |
| 7214 | nop |
| 7215 | mov 0x80, %g3 |
| 7216 | stxa %g3, [%g3] 0x5f |
| 7217 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 7218 | nop |
| 7219 | ta T_CHANGE_HPRIV ! macro |
| 7220 | donret_10_87: |
| 7221 | rd %pc, %r12 |
| 7222 | mov HIGHVA_HIGHNUM, %r10 |
| 7223 | sllx %r10, 32, %r10 |
| 7224 | or %r12, %r10, %r12 |
| 7225 | add %r12, (donretarg_10_87-donret_10_87), %r12 |
| 7226 | add %r12, 0x4, %r11 ! seq tnpc |
| 7227 | andn %r11, %r10, %r11 ! low VA tnpc |
| 7228 | wrpr %g0, 0x1, %tl |
| 7229 | wrpr %g0, %r12, %tpc |
| 7230 | wrpr %g0, %r11, %tnpc |
| 7231 | set (0x00710100 | (28 << 24)), %r13 |
| 7232 | and %r12, 0xfff, %r14 |
| 7233 | sllx %r14, 32, %r14 |
| 7234 | or %r13, %r14, %r20 |
| 7235 | wrpr %r20, %g0, %tstate |
| 7236 | wrhpr %g0, 0x109f, %htstate |
| 7237 | ta T_CHANGE_NONPRIV ! rand=0 (10) |
| 7238 | ldx [%r11+%r0], %g1 |
| 7239 | done |
| 7240 | donretarg_10_87: |
| 7241 | .word 0xe66fe0a9 ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x00a9] |
| 7242 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 7243 | .word 0x9345c000 ! 124: RD_TICK_CMPR_REG rd %-, %r9 |
| 7244 | .word 0xe19fde00 ! 125: LDDFA_R ldda [%r31, %r0], %f16 |
| 7245 | nop |
| 7246 | ta T_CHANGE_HPRIV |
| 7247 | mov 0x10+1, %r10 |
| 7248 | set sync_thr_counter5, %r23 |
| 7249 | #ifndef SPC |
| 7250 | ldxa [%g0]0x63, %o1 |
| 7251 | and %o1, 0x38, %o1 |
| 7252 | add %o1, %r23, %r23 |
| 7253 | sllx %o1, 5, %o3 !(CID*256) |
| 7254 | #endif |
| 7255 | cas [%r23],%g0,%r10 !lock |
| 7256 | brnz %r10, cwq_10_89 |
| 7257 | rd %asi, %r12 |
| 7258 | wr %g0, 0x40, %asi |
| 7259 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 7260 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 7261 | cmp %l1, 1 |
| 7262 | bne cwq_10_89 |
| 7263 | set CWQ_BASE, %l6 |
| 7264 | #ifndef SPC |
| 7265 | add %l6, %o3, %l6 |
| 7266 | #endif |
| 7267 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 7268 | best_set_reg(0x206100a0, %l1, %l2) !# Control Word |
| 7269 | sllx %l2, 32, %l2 |
| 7270 | stx %l2, [%l6 + 0x0] |
| 7271 | membar #Sync |
| 7272 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 7273 | sub %l2, 0x40, %l2 |
| 7274 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 7275 | wr %r12, %g0, %asi |
| 7276 | st %g0, [%r23] |
| 7277 | cwq_10_89: |
| 7278 | ta T_CHANGE_NONHPRIV |
| 7279 | .word 0x99414000 ! 126: RDPC rd %pc, %r12 |
| 7280 | .word 0xa3a00174 ! 127: FABSq dis not found |
| 7281 | |
| 7282 | #if (defined SPC || defined CMP) |
| 7283 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_10_91)+32, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 7284 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_10_91)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x10),1,3,,,,,1) |
| 7285 | xir_10_91: |
| 7286 | #else |
| 7287 | #if (defined FC) |
| 7288 | !! Generate XIR via RESET_GEN register |
| 7289 | ta T_CHANGE_HPRIV |
| 7290 | rdpr %pstate, %r18 |
| 7291 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 7292 | wrpr %r18, %pstate |
| 7293 | #ifndef XIR_RND_CORES |
| 7294 | ldxa [%g0] 0x63, %o1 |
| 7295 | mov 1, %r18 |
| 7296 | sllx %r18, %o1, %r18 |
| 7297 | #endif |
| 7298 | mov 0x30, %r19 |
| 7299 | setx 0x8900000808, %r16, %r17 |
| 7300 | mov 0x2, %r16 |
| 7301 | xir_10_91: |
| 7302 | stxa %r18, [%r19] 0x41 |
| 7303 | stx %r16, [%r17] |
| 7304 | #endif |
| 7305 | #endif |
| 7306 | .word 0xa98331ba ! 128: WR_SET_SOFTINT_I wr %r12, 0x11ba, %set_softint |
| 7307 | memptr_10_92: |
| 7308 | set 0x60740000, %r31 |
| 7309 | .word 0x8584be90 ! 129: WRCCR_I wr %r18, 0x1e90, %ccr |
| 7310 | rd %tick, %r28 |
| 7311 | #if (MAX_THREADS == 8) |
| 7312 | sethi %hi(0x33800), %r27 |
| 7313 | #else |
| 7314 | sethi %hi(0x30000), %r27 |
| 7315 | #endif |
| 7316 | andn %r28, %r27, %r28 |
| 7317 | ta T_CHANGE_HPRIV |
| 7318 | stxa %r28, [%g0] 0x73 |
| 7319 | intvec_10_93: |
| 7320 | .word 0xc36caf4d ! 130: PREFETCH_I prefetch [%r18 + 0x0f4d], #one_read |
| 7321 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 7322 | memptr_10_95: |
| 7323 | set 0x60340000, %r31 |
| 7324 | .word 0x8584e87d ! 132: WRCCR_I wr %r19, 0x087d, %ccr |
| 7325 | splash_hpstate_10_96: |
| 7326 | .word 0x26ca4001 ! 1: BRLZ brlz,a,pt %r9,<label_0xa4001> |
| 7327 | .word 0x81983d97 ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x1d97, %hpstate |
| 7328 | jmptr_10_97: |
| 7329 | nop |
| 7330 | best_set_reg(0xe0200000, %r20, %r27) |
| 7331 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 7332 | .word 0xd3e7c020 ! 135: CASA_I casa [%r31] 0x 1, %r0, %r9 |
| 7333 | .word 0x8d903af5 ! 136: WRPR_PSTATE_I wrpr %r0, 0x1af5, %pstate |
| 7334 | .word 0x99a00171 ! 137: FABSq dis not found |
| 7335 | |
| 7336 | nop |
| 7337 | ta T_CHANGE_HPRIV |
| 7338 | mov 0x10, %r10 |
| 7339 | set sync_thr_counter6, %r23 |
| 7340 | #ifndef SPC |
| 7341 | ldxa [%g0]0x63, %o1 |
| 7342 | and %o1, 0x38, %o1 |
| 7343 | add %o1, %r23, %r23 |
| 7344 | #endif |
| 7345 | cas [%r23],%g0,%r10 !lock |
| 7346 | brnz %r10, sma_10_101 |
| 7347 | rd %asi, %r12 |
| 7348 | wr %g0, 0x40, %asi |
| 7349 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7350 | set 0x00021fff, %g1 |
| 7351 | stxa %g1, [%g0 + 0x80] %asi |
| 7352 | wr %r12, %g0, %asi |
| 7353 | st %g0, [%r23] |
| 7354 | sma_10_101: |
| 7355 | ta T_CHANGE_NONHPRIV |
| 7356 | .word 0xe1e7e010 ! 138: CASA_R casa [%r31] %asi, %r16, %r16 |
| 7357 | .word 0xa9b0c0e6 ! 139: EDGE16LN edge16ln %r3, %r6, %r20 |
| 7358 | splash_lsu_10_103: |
| 7359 | nop |
| 7360 | ta T_CHANGE_HPRIV |
| 7361 | set 0x9951c12a, %r2 |
| 7362 | mov 0x4, %r1 |
| 7363 | sllx %r1, 32, %r1 |
| 7364 | or %r1, %r2, %r2 |
| 7365 | .word 0x3b400001 ! 1: FBPLE fble,a,pn %fcc0, <label_0x1> |
| 7366 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7367 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7368 | .word 0x996b4011 ! 141: SDIVX_R sdivx %r13, %r17, %r12 |
| 7369 | .word 0xc19fe060 ! 142: LDDFA_I ldda [%r31, 0x0060], %f0 |
| 7370 | .word 0x9194400a ! 143: WRPR_PIL_R wrpr %r17, %r10, %pil |
| 7371 | splash_hpstate_10_105: |
| 7372 | ta T_CHANGE_NONHPRIV |
| 7373 | .word 0x819821cd ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x01cd, %hpstate |
| 7374 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 7375 | nop |
| 7376 | ta T_CHANGE_HPRIV |
| 7377 | mov 0x10, %r10 |
| 7378 | set sync_thr_counter6, %r23 |
| 7379 | #ifndef SPC |
| 7380 | ldxa [%g0]0x63, %o1 |
| 7381 | and %o1, 0x38, %o1 |
| 7382 | add %o1, %r23, %r23 |
| 7383 | #endif |
| 7384 | cas [%r23],%g0,%r10 !lock |
| 7385 | brnz %r10, sma_10_107 |
| 7386 | rd %asi, %r12 |
| 7387 | wr %g0, 0x40, %asi |
| 7388 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7389 | set 0x000a1fff, %g1 |
| 7390 | stxa %g1, [%g0 + 0x80] %asi |
| 7391 | wr %r12, %g0, %asi |
| 7392 | st %g0, [%r23] |
| 7393 | sma_10_107: |
| 7394 | ta T_CHANGE_NONHPRIV |
| 7395 | .word 0xd1e7e011 ! 146: CASA_R casa [%r31] %asi, %r17, %r8 |
| 7396 | fpinit_10_108: |
| 7397 | nop |
| 7398 | setx fp_data_quads, %r19, %r20 |
| 7399 | ldd [%r20], %f0 |
| 7400 | ldd [%r20+8], %f4 |
| 7401 | ld [%r20+16], %fsr |
| 7402 | ld [%r20+24], %r19 |
| 7403 | wr %r19, %g0, %gsr |
| 7404 | .word 0x89a009a4 ! 147: FDIVs fdivs %f0, %f4, %f4 |
| 7405 | intveclr_10_109: |
| 7406 | nop |
| 7407 | ta T_CHANGE_HPRIV |
| 7408 | setx 0x18ce3ecde50394c5, %r1, %r28 |
| 7409 | stxa %r28, [%g0] 0x72 |
| 7410 | ta T_CHANGE_NONHPRIV |
| 7411 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 7412 | brcommon3_10_110: |
| 7413 | nop |
| 7414 | setx common_target, %r12, %r27 |
| 7415 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 7416 | ba,a .+12 |
| 7417 | .word 0xd06fe1b0 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x01b0] |
| 7418 | ba,a .+8 |
| 7419 | jmpl %r27+0, %r27 |
| 7420 | .word 0xd13fc00b ! 149: STDF_R std %f8, [%r11, %r31] |
| 7421 | .word 0x32800001 ! 1: BNE bne,a <label_0x1> |
| 7422 | .word 0x8d90368d ! 150: WRPR_PSTATE_I wrpr %r0, 0x168d, %pstate |
| 7423 | nop |
| 7424 | nop |
| 7425 | ta T_CHANGE_PRIV |
| 7426 | wrpr %g0, %g0, %gl |
| 7427 | nop |
| 7428 | nop |
| 7429 | .text |
| 7430 | setx join_lbl_0_0, %g1, %g2 |
| 7431 | jmp %g2 |
| 7432 | nop |
| 7433 | fork_lbl_0_4: |
| 7434 | ta T_CHANGE_NONHPRIV |
| 7435 | .word 0xe877e039 ! 1: STX_I stx %r20, [%r31 + 0x0039] |
| 7436 | br_longdelay4_8_0: |
| 7437 | nop |
| 7438 | not %g0, %r27 |
| 7439 | jmpl %r27+0, %r27 |
| 7440 | .word 0x9d902005 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0005, %wstate |
| 7441 | .word 0xe93fe1b1 ! 3: STDF_I std %f20, [0x01b1, %r31] |
| 7442 | fpinit_8_1: |
| 7443 | nop |
| 7444 | setx fp_data_quads, %r19, %r20 |
| 7445 | ldd [%r20], %f0 |
| 7446 | ldd [%r20+8], %f4 |
| 7447 | ld [%r20+16], %fsr |
| 7448 | ld [%r20+24], %r19 |
| 7449 | wr %r19, %g0, %gsr |
| 7450 | .word 0x91a009a4 ! 4: FDIVs fdivs %f0, %f4, %f8 |
| 7451 | splash_lsu_8_2: |
| 7452 | nop |
| 7453 | ta T_CHANGE_HPRIV |
| 7454 | set 0xec7cd304, %r2 |
| 7455 | mov 0x5, %r1 |
| 7456 | sllx %r1, 32, %r1 |
| 7457 | or %r1, %r2, %r2 |
| 7458 | .word 0x20800001 ! 1: BN bn,a <label_0x1> |
| 7459 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7460 | ta T_CHANGE_NONHPRIV |
| 7461 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7462 | splash_hpstate_8_3: |
| 7463 | .word 0x819824d5 ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x04d5, %hpstate |
| 7464 | memptr_8_4: |
| 7465 | set 0x60740000, %r31 |
| 7466 | .word 0x85852cd0 ! 7: WRCCR_I wr %r20, 0x0cd0, %ccr |
| 7467 | nop |
| 7468 | mov 0x80, %g3 |
| 7469 | .word 0x26800001 ! 1: BL bl,a <label_0x1> |
| 7470 | stxa %g3, [%g3] 0x5f |
| 7471 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 7472 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 7473 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 7474 | .word 0xe19fe1c0 ! 9: LDDFA_I ldda [%r31, 0x01c0], %f16 |
| 7475 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 7476 | .word 0xe1bfdc00 ! 11: STDFA_R stda %f16, [%r0, %r31] |
| 7477 | dvapa_8_6: |
| 7478 | nop |
| 7479 | ta T_CHANGE_HPRIV |
| 7480 | mov 0x981, %r20 |
| 7481 | mov 0xe, %r19 |
| 7482 | sllx %r20, 23, %r20 |
| 7483 | or %r19, %r20, %r19 |
| 7484 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 7485 | mov 0x38, %r18 |
| 7486 | stxa %r31, [%r18]0x58 |
| 7487 | ta T_CHANGE_NONHPRIV |
| 7488 | .word 0xc19fdc00 ! 12: LDDFA_R ldda [%r31, %r0], %f0 |
| 7489 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 7490 | jmptr_8_7: |
| 7491 | nop |
| 7492 | best_set_reg(0xe0a00000, %r20, %r27) |
| 7493 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 7494 | pmu_8_8: |
| 7495 | nop |
| 7496 | ta T_CHANGE_PRIV |
| 7497 | setx 0xffffffb9ffffffa2, %g1, %g7 |
| 7498 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 7499 | jmptr_8_9: |
| 7500 | nop |
| 7501 | best_set_reg(0xe0a00000, %r20, %r27) |
| 7502 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 7503 | nop |
| 7504 | ta T_CHANGE_HPRIV |
| 7505 | mov 0x8, %r10 |
| 7506 | set sync_thr_counter6, %r23 |
| 7507 | #ifndef SPC |
| 7508 | ldxa [%g0]0x63, %o1 |
| 7509 | and %o1, 0x38, %o1 |
| 7510 | add %o1, %r23, %r23 |
| 7511 | #endif |
| 7512 | cas [%r23],%g0,%r10 !lock |
| 7513 | brnz %r10, sma_8_10 |
| 7514 | rd %asi, %r12 |
| 7515 | wr %g0, 0x40, %asi |
| 7516 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7517 | set 0x000a1fff, %g1 |
| 7518 | stxa %g1, [%g0 + 0x80] %asi |
| 7519 | wr %r12, %g0, %asi |
| 7520 | st %g0, [%r23] |
| 7521 | sma_8_10: |
| 7522 | ta T_CHANGE_NONHPRIV |
| 7523 | .word 0xe9e7e009 ! 17: CASA_R casa [%r31] %asi, %r9, %r20 |
| 7524 | .word 0x87802055 ! 18: WRASI_I wr %r0, 0x0055, %asi |
| 7525 | splash_lsu_8_11: |
| 7526 | nop |
| 7527 | ta T_CHANGE_HPRIV |
| 7528 | set 0x693f31f2, %r2 |
| 7529 | mov 0x3, %r1 |
| 7530 | sllx %r1, 32, %r1 |
| 7531 | or %r1, %r2, %r2 |
| 7532 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7533 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7534 | .word 0xe93fe001 ! 20: STDF_I std %f20, [0x0001, %r31] |
| 7535 | brcommon1_8_12: |
| 7536 | nop |
| 7537 | setx common_target, %r12, %r27 |
| 7538 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 7539 | ba,a .+12 |
| 7540 | .word 0xa9b7c7d2 ! 1: PDIST pdistn %d62, %d18, %d20 |
| 7541 | ba,a .+8 |
| 7542 | jmpl %r27+0, %r27 |
| 7543 | .word 0x9f8021b2 ! 21: SIR sir 0x01b2 |
| 7544 | splash_lsu_8_13: |
| 7545 | nop |
| 7546 | ta T_CHANGE_HPRIV |
| 7547 | set 0x8321efe4, %r2 |
| 7548 | mov 0x5, %r1 |
| 7549 | sllx %r1, 32, %r1 |
| 7550 | or %r1, %r2, %r2 |
| 7551 | .word 0x36800001 ! 1: BGE bge,a <label_0x1> |
| 7552 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7553 | ta T_CHANGE_NONHPRIV |
| 7554 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7555 | .word 0xe19fd960 ! 23: LDDFA_R ldda [%r31, %r0], %f16 |
| 7556 | .word 0xe1bfdc00 ! 24: STDFA_R stda %f16, [%r0, %r31] |
| 7557 | pmu_8_14: |
| 7558 | nop |
| 7559 | ta T_CHANGE_PRIV |
| 7560 | setx 0xffffffb0ffffffab, %g1, %g7 |
| 7561 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 7562 | rd %tick, %r28 |
| 7563 | #if (MAX_THREADS == 8) |
| 7564 | sethi %hi(0x33800), %r27 |
| 7565 | #else |
| 7566 | sethi %hi(0x30000), %r27 |
| 7567 | #endif |
| 7568 | andn %r28, %r27, %r28 |
| 7569 | ta T_CHANGE_HPRIV |
| 7570 | stxa %r28, [%g0] 0x73 |
| 7571 | .word 0xa7a449d4 ! 1: FDIVd fdivd %f48, %f20, %f50 |
| 7572 | intvec_8_15: |
| 7573 | .word 0xa9a109d3 ! 26: FDIVd fdivd %f4, %f50, %f20 |
| 7574 | .word 0x91914007 ! 27: WRPR_PIL_R wrpr %r5, %r7, %pil |
| 7575 | nop |
| 7576 | mov 0x80, %g3 |
| 7577 | stxa %r7, [%r0] ASI_LSU_CONTROL |
| 7578 | stxa %g3, [%g3] 0x57 |
| 7579 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 7580 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 7581 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 7582 | #if (defined SPC || defined CMP) |
| 7583 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_8_17)+40, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 7584 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_8_17)&0xffffffff) + 56, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 7585 | xir_8_17: |
| 7586 | #else |
| 7587 | #if (defined FC) |
| 7588 | !! Generate XIR via RESET_GEN register |
| 7589 | ta T_CHANGE_HPRIV |
| 7590 | rdpr %pstate, %r18 |
| 7591 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 7592 | wrpr %r18, %pstate |
| 7593 | #ifndef XIR_RND_CORES |
| 7594 | ldxa [%g0] 0x63, %o1 |
| 7595 | mov 1, %r18 |
| 7596 | sllx %r18, %o1, %r18 |
| 7597 | #endif |
| 7598 | mov 0x30, %r19 |
| 7599 | setx 0x8900000808, %r16, %r17 |
| 7600 | mov 0x2, %r16 |
| 7601 | xir_8_17: |
| 7602 | stxa %r18, [%r19] 0x41 |
| 7603 | stx %r16, [%r17] |
| 7604 | #endif |
| 7605 | #endif |
| 7606 | .word 0xa9853de9 ! 29: WR_SET_SOFTINT_I wr %r20, 0x1de9, %set_softint |
| 7607 | .word 0xa5a00172 ! 30: FABSq dis not found |
| 7608 | |
| 7609 | .word 0x95a00164 ! 31: FABSq dis not found |
| 7610 | |
| 7611 | tagged_8_20: |
| 7612 | tsubcctv %r18, 0x13eb, %r13 |
| 7613 | .word 0xd807e1e8 ! 32: LDUW_I lduw [%r31 + 0x01e8], %r12 |
| 7614 | mondo_8_21: |
| 7615 | nop |
| 7616 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 7617 | stxa %r12, [%r0+0x3e0] %asi |
| 7618 | .word 0x9d90800c ! 33: WRPR_WSTATE_R wrpr %r2, %r12, %wstate |
| 7619 | .word 0xb180c013 ! 34: WR_STICK_REG_R wr %r3, %r19, %- |
| 7620 | nop |
| 7621 | ta T_CHANGE_HPRIV |
| 7622 | mov 0x8, %r10 |
| 7623 | set sync_thr_counter6, %r23 |
| 7624 | #ifndef SPC |
| 7625 | ldxa [%g0]0x63, %o1 |
| 7626 | and %o1, 0x38, %o1 |
| 7627 | add %o1, %r23, %r23 |
| 7628 | #endif |
| 7629 | cas [%r23],%g0,%r10 !lock |
| 7630 | brnz %r10, sma_8_22 |
| 7631 | rd %asi, %r12 |
| 7632 | wr %g0, 0x40, %asi |
| 7633 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7634 | set 0x00061fff, %g1 |
| 7635 | stxa %g1, [%g0 + 0x80] %asi |
| 7636 | wr %r12, %g0, %asi |
| 7637 | st %g0, [%r23] |
| 7638 | sma_8_22: |
| 7639 | ta T_CHANGE_NONHPRIV |
| 7640 | .word 0xd9e7e009 ! 35: CASA_R casa [%r31] %asi, %r9, %r12 |
| 7641 | nop |
| 7642 | ta T_CHANGE_HPRIV |
| 7643 | mov 0x8, %r10 |
| 7644 | set sync_thr_counter6, %r23 |
| 7645 | #ifndef SPC |
| 7646 | ldxa [%g0]0x63, %o1 |
| 7647 | and %o1, 0x38, %o1 |
| 7648 | add %o1, %r23, %r23 |
| 7649 | #endif |
| 7650 | cas [%r23],%g0,%r10 !lock |
| 7651 | brnz %r10, sma_8_23 |
| 7652 | rd %asi, %r12 |
| 7653 | wr %g0, 0x40, %asi |
| 7654 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 7655 | set 0x001a1fff, %g1 |
| 7656 | stxa %g1, [%g0 + 0x80] %asi |
| 7657 | wr %r12, %g0, %asi |
| 7658 | st %g0, [%r23] |
| 7659 | sma_8_23: |
| 7660 | ta T_CHANGE_NONHPRIV |
| 7661 | .word 0xd9e7e00d ! 36: CASA_R casa [%r31] %asi, %r13, %r12 |
| 7662 | splash_tba_8_24: |
| 7663 | nop |
| 7664 | ta T_CHANGE_PRIV |
| 7665 | set 0x120000, %r12 |
| 7666 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 7667 | splash_lsu_8_25: |
| 7668 | nop |
| 7669 | ta T_CHANGE_HPRIV |
| 7670 | set 0x7e939dc3, %r2 |
| 7671 | mov 0x5, %r1 |
| 7672 | sllx %r1, 32, %r1 |
| 7673 | or %r1, %r2, %r2 |
| 7674 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 7675 | ta T_CHANGE_NONHPRIV |
| 7676 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 7677 | #if (defined SPC || defined CMP1) |
| 7678 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_26) + 0, 16, 16)) -> intp(0,0,8,,,,,1) |
| 7679 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_26)&0xffffffff) + 32, 16, 16)) -> intp(1,0,5,,,,,1) |
| 7680 | #else |
| 7681 | set 0x5880bcab, %r28 |
| 7682 | #if (MAX_THREADS == 8) |
| 7683 | and %r28, 0x7ff, %r28 |
| 7684 | #endif |
| 7685 | stxa %r28, [%g0] 0x73 |
| 7686 | #endif |
| 7687 | .word 0xc368aeb1 ! 1: PREFETCH_I prefetch [%r2 + 0x0eb1], #one_read |
| 7688 | intvec_8_26: |
| 7689 | .word 0x9f803c22 ! 39: SIR sir 0x1c22 |
| 7690 | .word 0xd727e077 ! 40: STF_I st %f11, [0x0077, %r31] |
| 7691 | .word 0xd627e05e ! 41: STW_I stw %r11, [%r31 + 0x005e] |
| 7692 | jmptr_8_27: |
| 7693 | nop |
| 7694 | best_set_reg(0xe0a00000, %r20, %r27) |
| 7695 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 7696 | splash_tba_8_28: |
| 7697 | nop |
| 7698 | ta T_CHANGE_PRIV |
| 7699 | set 0x120000, %r12 |
| 7700 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 7701 | set 0x1b03, %l3 |
| 7702 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 7703 | .word 0x99b247d2 ! 44: PDIST pdistn %d40, %d18, %d12 |
| 7704 | pmu_8_29: |
| 7705 | nop |
| 7706 | setx 0xffffffb4ffffffa7, %g1, %g7 |
| 7707 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 7708 | brcommon3_8_30: |
| 7709 | nop |
| 7710 | setx common_target, %r12, %r27 |
| 7711 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 7712 | ba,a .+12 |
| 7713 | .word 0xe3e7c030 ! 1: CASA_I casa [%r31] 0x 1, %r16, %r17 |
| 7714 | ba,a .+8 |
| 7715 | jmpl %r27+0, %r27 |
| 7716 | .word 0xe31fc00c ! 46: LDDF_R ldd [%r31, %r12], %f17 |
| 7717 | brcommon3_8_31: |
| 7718 | nop |
| 7719 | setx common_target, %r12, %r27 |
| 7720 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 7721 | ba,a .+12 |
| 7722 | .word 0xe26fe0c0 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x00c0] |
| 7723 | ba,a .+8 |
| 7724 | jmpl %r27+0, %r27 |
| 7725 | stxa %r7, [%r0] ASI_LSU_CONTROL |
| 7726 | .word 0x97aac832 ! 47: FMOVGE fmovs %fcc1, %f18, %f11 |
| 7727 | brcommon3_8_32: |
| 7728 | nop |
| 7729 | setx common_target, %r12, %r27 |
| 7730 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 7731 | ba,a .+12 |
| 7732 | .word 0xd737e180 ! 1: STQF_I - %f11, [0x0180, %r31] |
| 7733 | ba,a .+8 |
| 7734 | jmpl %r27+0, %r27 |
| 7735 | .word 0xc32fc014 ! 48: STXFSR_R st-sfr %f1, [%r20, %r31] |
| 7736 | nop |
| 7737 | mov 0x80, %g3 |
| 7738 | .word 0x2e800001 ! 1: BVS bvs,a <label_0x1> |
| 7739 | stxa %g3, [%g3] 0x5f |
| 7740 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 7741 | nop |
| 7742 | ta T_CHANGE_HPRIV ! macro |
| 7743 | donret_8_33: |
| 7744 | rd %pc, %r12 |
| 7745 | mov HIGHVA_HIGHNUM, %r10 |
| 7746 | sllx %r10, 32, %r10 |
| 7747 | or %r12, %r10, %r12 |
| 7748 | add %r12, (donretarg_8_33-donret_8_33), %r12 |
| 7749 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 7750 | andn %r11, %r10, %r11 ! low VA tnpc |
| 7751 | wrpr %g0, 0x1, %tl |
| 7752 | wrpr %g0, %r12, %tpc |
| 7753 | wrpr %g0, %r11, %tnpc |
| 7754 | set (0x002c4800 | (0x58 << 24)), %r13 |
| 7755 | and %r12, 0xfff, %r14 |
| 7756 | sllx %r14, 32, %r14 |
| 7757 | or %r13, %r14, %r20 |
| 7758 | wrpr %r20, %g0, %tstate |
| 7759 | wrhpr %g0, 0x645, %htstate |
| 7760 | ta T_CHANGE_NONHPRIV ! rand=1 (8) |
| 7761 | ldx [%r11+%r0], %g1 |
| 7762 | done |
| 7763 | donretarg_8_33: |
| 7764 | .word 0x2f400001 ! 50: FBPU fbu,a,pn %fcc0, <label_0x1> |
| 7765 | #if (defined SPC || defined CMP1) |
| 7766 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_34) + 48, 16, 16)) -> intp(3,0,15,,,,,1) |
| 7767 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_34)&0xffffffff) + 8, 16, 16)) -> intp(0,0,26,,,,,1) |
| 7768 | #else |
| 7769 | set 0xb10cc4f, %r28 |
| 7770 | #if (MAX_THREADS == 8) |
| 7771 | and %r28, 0x7ff, %r28 |
| 7772 | #endif |
| 7773 | stxa %r28, [%g0] 0x73 |
| 7774 | #endif |
| 7775 | intvec_8_34: |
| 7776 | .word 0xc369fb4d ! 51: PREFETCH_I prefetch [%r7 + 0xfffffb4d], #one_read |
| 7777 | .word 0xe927e1b0 ! 52: STF_I st %f20, [0x01b0, %r31] |
| 7778 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 7779 | splash_tba_8_35: |
| 7780 | nop |
| 7781 | ta T_CHANGE_PRIV |
| 7782 | setx 0x00000000003a0000, %r11, %r12 |
| 7783 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 7784 | iaw_8_36: |
| 7785 | nop |
| 7786 | ta T_CHANGE_HPRIV |
| 7787 | mov 8, %r18 |
| 7788 | rd %asi, %r12 |
| 7789 | wr %r0, 0x41, %asi |
| 7790 | set sync_thr_counter4, %r23 |
| 7791 | #ifndef SPC |
| 7792 | ldxa [%g0]0x63, %r8 |
| 7793 | and %r8, 0x38, %r8 ! Core ID |
| 7794 | add %r8, %r23, %r23 |
| 7795 | #else |
| 7796 | mov 0, %r8 |
| 7797 | #endif |
| 7798 | mov 0x8, %r16 |
| 7799 | iaw_startwait8_36: |
| 7800 | cas [%r23],%g0,%r16 !lock |
| 7801 | brz,a %r16, continue_iaw_8_36 |
| 7802 | mov (~0x8&0xf), %r16 |
| 7803 | ld [%r23], %r16 |
| 7804 | iaw_wait8_36: |
| 7805 | brnz %r16, iaw_wait8_36 |
| 7806 | ld [%r23], %r16 |
| 7807 | ba iaw_startwait8_36 |
| 7808 | mov 0x8, %r16 |
| 7809 | continue_iaw_8_36: |
| 7810 | sllx %r16, %r8, %r16 !Mask for my core only |
| 7811 | ldxa [0x58]%asi, %r17 !Running_status |
| 7812 | wait_for_stat_8_36: |
| 7813 | ldxa [0x50]%asi, %r13 !Running_rw |
| 7814 | cmp %r13, %r17 |
| 7815 | bne,a %xcc, wait_for_stat_8_36 |
| 7816 | ldxa [0x58]%asi, %r17 !Running_status |
| 7817 | stxa %r16, [0x68]%asi !Park (W1C) |
| 7818 | ldxa [0x50]%asi, %r14 !Running_rw |
| 7819 | wait_for_iaw_8_36: |
| 7820 | ldxa [0x58]%asi, %r17 !Running_status |
| 7821 | cmp %r14, %r17 |
| 7822 | bne,a %xcc, wait_for_iaw_8_36 |
| 7823 | ldxa [0x50]%asi, %r14 !Running_rw |
| 7824 | iaw_doit8_36: |
| 7825 | mov 0x38, %r18 |
| 7826 | iaw2_8_36: |
| 7827 | rdpr %tba, %r19 |
| 7828 | mov 0x320, %r20 |
| 7829 | sllx %r20, 5, %r20 |
| 7830 | add %r20, %r19, %r19 |
| 7831 | stxa %r19, [%r18]0x50 |
| 7832 | stxa %r16, [0x60] %asi ! Unpark (W1S) |
| 7833 | st %g0, [%r23] !clear lock |
| 7834 | wr %r0, %r12, %asi ! restore %asi |
| 7835 | ta T_CHANGE_NONHPRIV |
| 7836 | .word 0x97b40486 ! 55: FCMPLE32 fcmple32 %d16, %d6, %r11 |
| 7837 | ibp_8_37: |
| 7838 | nop |
| 7839 | ta T_CHANGE_NONHPRIV |
| 7840 | .word 0xa3703380 ! 56: POPC_I popc 0x1380, %r17 |
| 7841 | brcommon3_8_38: |
| 7842 | nop |
| 7843 | setx common_target, %r12, %r27 |
| 7844 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 7845 | ba,a .+12 |
| 7846 | .word 0xe937e0b0 ! 1: STQF_I - %f20, [0x00b0, %r31] |
| 7847 | ba,a .+8 |
| 7848 | jmpl %r27+0, %r27 |
| 7849 | .word 0xe9e7e00b ! 57: CASA_R casa [%r31] %asi, %r11, %r20 |
| 7850 | ibp_8_39: |
| 7851 | nop |
| 7852 | ta T_CHANGE_NONHPRIV |
| 7853 | .word 0xa3a409b0 ! 58: FDIVs fdivs %f16, %f16, %f17 |
| 7854 | nop |
| 7855 | ta T_CHANGE_HPRIV ! macro |
| 7856 | donret_8_40: |
| 7857 | rd %pc, %r12 |
| 7858 | mov HIGHVA_HIGHNUM, %r10 |
| 7859 | sllx %r10, 32, %r10 |
| 7860 | or %r12, %r10, %r12 |
| 7861 | add %r12, (donretarg_8_40-donret_8_40+4), %r12 |
| 7862 | add %r12, 0x4, %r11 ! seq tnpc |
| 7863 | andn %r12, %r10, %r12 ! low VA tpc |
| 7864 | wrpr %g0, 0x1, %tl |
| 7865 | wrpr %g0, %r12, %tpc |
| 7866 | wrpr %g0, %r11, %tnpc |
| 7867 | set (0x00dea800 | (48 << 24)), %r13 |
| 7868 | and %r12, 0xfff, %r14 |
| 7869 | sllx %r14, 32, %r14 |
| 7870 | or %r13, %r14, %r20 |
| 7871 | wrpr %r20, %g0, %tstate |
| 7872 | wrhpr %g0, 0x1ad7, %htstate |
| 7873 | ta T_CHANGE_NONPRIV ! rand=0 (8) |
| 7874 | ldx [%r12+%r0], %g1 |
| 7875 | retry |
| 7876 | donretarg_8_40: |
| 7877 | .word 0x25400001 ! 59: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 7878 | memptr_8_41: |
| 7879 | set 0x60340000, %r31 |
| 7880 | .word 0x85847b29 ! 60: WRCCR_I wr %r17, 0x1b29, %ccr |
| 7881 | nop |
| 7882 | mov 0x80, %g3 |
| 7883 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 7884 | stxa %g3, [%g3] 0x5f |
| 7885 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 7886 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 7887 | .word 0x9153c000 ! 62: RDPR_FQ <illegal instruction> |
| 7888 | fbu skip_8_42 |
| 7889 | fbuge,a,pn %fcc0, skip_8_42 |
| 7890 | .align 1024 |
| 7891 | skip_8_42: |
| 7892 | .word 0x87a8ca44 ! 63: FCMPd fcmpd %fcc<n>, %f34, %f4 |
| 7893 | fbg,a,pn %fcc0, skip_8_43 |
| 7894 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 7895 | fbug,a,pn %fcc0, skip_8_43 |
| 7896 | stxa %r15, [%r0] ASI_LSU_CONTROL |
| 7897 | .align 1024 |
| 7898 | skip_8_43: |
| 7899 | .word 0xc30fc000 ! 64: LDXFSR_R ld-fsr [%r31, %r0], %f1 |
| 7900 | .word 0xc19fc2c0 ! 65: LDDFA_R ldda [%r31, %r0], %f0 |
| 7901 | nop |
| 7902 | ta T_CHANGE_HPRIV |
| 7903 | mov 0x8+1, %r10 |
| 7904 | set sync_thr_counter5, %r23 |
| 7905 | #ifndef SPC |
| 7906 | ldxa [%g0]0x63, %o1 |
| 7907 | and %o1, 0x38, %o1 |
| 7908 | add %o1, %r23, %r23 |
| 7909 | sllx %o1, 5, %o3 !(CID*256) |
| 7910 | #endif |
| 7911 | cas [%r23],%g0,%r10 !lock |
| 7912 | brnz %r10, cwq_8_44 |
| 7913 | rd %asi, %r12 |
| 7914 | wr %g0, 0x40, %asi |
| 7915 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 7916 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 7917 | cmp %l1, 1 |
| 7918 | bne cwq_8_44 |
| 7919 | set CWQ_BASE, %l6 |
| 7920 | #ifndef SPC |
| 7921 | add %l6, %o3, %l6 |
| 7922 | #endif |
| 7923 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 7924 | best_set_reg(0x20610070, %l1, %l2) !# Control Word |
| 7925 | sllx %l2, 32, %l2 |
| 7926 | stx %l2, [%l6 + 0x0] |
| 7927 | membar #Sync |
| 7928 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 7929 | sub %l2, 0x40, %l2 |
| 7930 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 7931 | wr %r12, %g0, %asi |
| 7932 | st %g0, [%r23] |
| 7933 | cwq_8_44: |
| 7934 | ta T_CHANGE_NONHPRIV |
| 7935 | .word 0x97414000 ! 66: RDPC rd %pc, %r11 |
| 7936 | mondo_8_45: |
| 7937 | nop |
| 7938 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 7939 | ta T_CHANGE_PRIV |
| 7940 | stxa %r8, [%r0+0x3c8] %asi |
| 7941 | .word 0x9d94000c ! 67: WRPR_WSTATE_R wrpr %r16, %r12, %wstate |
| 7942 | .word 0xa7a00161 ! 68: FABSq dis not found |
| 7943 | |
| 7944 | .word 0x91948004 ! 69: WRPR_PIL_R wrpr %r18, %r4, %pil |
| 7945 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 7946 | #if (defined SPC || defined CMP) |
| 7947 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_8_49)+56, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 7948 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_8_49)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 7949 | xir_8_49: |
| 7950 | #else |
| 7951 | #if (defined FC) |
| 7952 | !! Generate XIR via RESET_GEN register |
| 7953 | ta T_CHANGE_HPRIV |
| 7954 | rdpr %pstate, %r18 |
| 7955 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 7956 | wrpr %r18, %pstate |
| 7957 | #ifndef XIR_RND_CORES |
| 7958 | ldxa [%g0] 0x63, %o1 |
| 7959 | mov 1, %r18 |
| 7960 | sllx %r18, %o1, %r18 |
| 7961 | #endif |
| 7962 | mov 0x30, %r19 |
| 7963 | setx 0x8900000808, %r16, %r17 |
| 7964 | mov 0x2, %r16 |
| 7965 | xir_8_49: |
| 7966 | stxa %r18, [%r19] 0x41 |
| 7967 | stx %r16, [%r17] |
| 7968 | #endif |
| 7969 | #endif |
| 7970 | .word 0xa981f201 ! 71: WR_SET_SOFTINT_I wr %r7, 0x1201, %set_softint |
| 7971 | #if (defined SPC || defined CMP1) |
| 7972 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_50) + 0, 16, 16)) -> intp(7,0,18,,,,,1) |
| 7973 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_50)&0xffffffff) + 40, 16, 16)) -> intp(6,0,9,,,,,1) |
| 7974 | #else |
| 7975 | set 0x1370c2f8, %r28 |
| 7976 | #if (MAX_THREADS == 8) |
| 7977 | and %r28, 0x7ff, %r28 |
| 7978 | #endif |
| 7979 | stxa %r28, [%g0] 0x73 |
| 7980 | #endif |
| 7981 | .word 0xc36b7245 ! 1: PREFETCH_I prefetch [%r13 + 0xfffff245], #one_read |
| 7982 | intvec_8_50: |
| 7983 | .word 0x39400001 ! 72: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 7984 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 7985 | nop |
| 7986 | mov 0x80, %g3 |
| 7987 | stxa %r15, [%r0] ASI_LSU_CONTROL |
| 7988 | stxa %g3, [%g3] 0x57 |
| 7989 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 7990 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 7991 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 7992 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 7993 | nop |
| 7994 | ta T_CHANGE_HPRIV |
| 7995 | mov 0x8, %r10 |
| 7996 | set sync_thr_counter6, %r23 |
| 7997 | #ifndef SPC |
| 7998 | ldxa [%g0]0x63, %o1 |
| 7999 | and %o1, 0x38, %o1 |
| 8000 | add %o1, %r23, %r23 |
| 8001 | #endif |
| 8002 | cas [%r23],%g0,%r10 !lock |
| 8003 | brnz %r10, sma_8_52 |
| 8004 | rd %asi, %r12 |
| 8005 | wr %g0, 0x40, %asi |
| 8006 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8007 | set 0x001e1fff, %g1 |
| 8008 | stxa %g1, [%g0 + 0x80] %asi |
| 8009 | wr %r12, %g0, %asi |
| 8010 | st %g0, [%r23] |
| 8011 | sma_8_52: |
| 8012 | ta T_CHANGE_NONHPRIV |
| 8013 | .word 0xe5e7e010 ! 75: CASA_R casa [%r31] %asi, %r16, %r18 |
| 8014 | .word 0x9190c010 ! 76: WRPR_PIL_R wrpr %r3, %r16, %pil |
| 8015 | pmu_8_54: |
| 8016 | nop |
| 8017 | setx 0xffffffb2ffffffaa, %g1, %g7 |
| 8018 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 8019 | fpinit_8_55: |
| 8020 | nop |
| 8021 | setx fp_data_quads, %r19, %r20 |
| 8022 | ldd [%r20], %f0 |
| 8023 | ldd [%r20+8], %f4 |
| 8024 | ld [%r20+16], %fsr |
| 8025 | ld [%r20+24], %r19 |
| 8026 | wr %r19, %g0, %gsr |
| 8027 | .word 0x8db00484 ! 78: FCMPLE32 fcmple32 %d0, %d4, %r6 |
| 8028 | jmptr_8_56: |
| 8029 | nop |
| 8030 | best_set_reg(0xe0a00000, %r20, %r27) |
| 8031 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 8032 | nop |
| 8033 | mov 0x80, %g3 |
| 8034 | stxa %r12, [%r0] ASI_LSU_CONTROL |
| 8035 | stxa %g3, [%g3] 0x5f |
| 8036 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 8037 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 8038 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 8039 | .word 0x95b340e3 ! 81: EDGE16LN edge16ln %r13, %r3, %r10 |
| 8040 | #if (defined SPC || defined CMP1) |
| 8041 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_58) + 0, 16, 16)) -> intp(2,0,22,,,,,1) |
| 8042 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_58)&0xffffffff) + 0, 16, 16)) -> intp(0,0,22,,,,,1) |
| 8043 | #else |
| 8044 | set 0xef10d61c, %r28 |
| 8045 | #if (MAX_THREADS == 8) |
| 8046 | and %r28, 0x7ff, %r28 |
| 8047 | #endif |
| 8048 | stxa %r28, [%g0] 0x73 |
| 8049 | #endif |
| 8050 | .word 0xc36c6e5a ! 1: PREFETCH_I prefetch [%r17 + 0x0e5a], #one_read |
| 8051 | intvec_8_58: |
| 8052 | .word 0x39400001 ! 82: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 8053 | nop |
| 8054 | ta T_CHANGE_HPRIV |
| 8055 | mov 0x8, %r10 |
| 8056 | set sync_thr_counter6, %r23 |
| 8057 | #ifndef SPC |
| 8058 | ldxa [%g0]0x63, %o1 |
| 8059 | and %o1, 0x38, %o1 |
| 8060 | add %o1, %r23, %r23 |
| 8061 | #endif |
| 8062 | cas [%r23],%g0,%r10 !lock |
| 8063 | brnz %r10, sma_8_59 |
| 8064 | rd %asi, %r12 |
| 8065 | wr %g0, 0x40, %asi |
| 8066 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8067 | set 0x00061fff, %g1 |
| 8068 | stxa %g1, [%g0 + 0x80] %asi |
| 8069 | wr %r12, %g0, %asi |
| 8070 | st %g0, [%r23] |
| 8071 | sma_8_59: |
| 8072 | ta T_CHANGE_NONHPRIV |
| 8073 | .word 0xe5e7e00b ! 83: CASA_R casa [%r31] %asi, %r11, %r18 |
| 8074 | fpinit_8_60: |
| 8075 | nop |
| 8076 | setx fp_data_quads, %r19, %r20 |
| 8077 | ldd [%r20], %f0 |
| 8078 | ldd [%r20+8], %f4 |
| 8079 | ld [%r20+16], %fsr |
| 8080 | ld [%r20+24], %r19 |
| 8081 | wr %r19, %g0, %gsr |
| 8082 | .word 0x91a009a4 ! 84: FDIVs fdivs %f0, %f4, %f8 |
| 8083 | .word 0x87802058 ! 85: WRASI_I wr %r0, 0x0058, %asi |
| 8084 | .word 0xe19fda00 ! 86: LDDFA_R ldda [%r31, %r0], %f16 |
| 8085 | splash_lsu_8_61: |
| 8086 | nop |
| 8087 | ta T_CHANGE_HPRIV |
| 8088 | set 0x545d1ace, %r2 |
| 8089 | mov 0x1, %r1 |
| 8090 | sllx %r1, 32, %r1 |
| 8091 | or %r1, %r2, %r2 |
| 8092 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8093 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8094 | splash_lsu_8_62: |
| 8095 | nop |
| 8096 | ta T_CHANGE_HPRIV |
| 8097 | set 0x6fca9ccd, %r2 |
| 8098 | mov 0x1, %r1 |
| 8099 | sllx %r1, 32, %r1 |
| 8100 | or %r1, %r2, %r2 |
| 8101 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8102 | ta T_CHANGE_NONHPRIV |
| 8103 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8104 | splash_cmpr_8_63: |
| 8105 | mov 0, %r18 |
| 8106 | sllx %r18, 63, %r18 |
| 8107 | rd %tick, %r17 |
| 8108 | add %r17, 0x80, %r17 |
| 8109 | or %r17, %r18, %r17 |
| 8110 | ta T_CHANGE_HPRIV |
| 8111 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 8112 | .word 0xb3800011 ! 89: WR_STICK_CMPR_REG_R wr %r0, %r17, %- |
| 8113 | nop |
| 8114 | mov 0x80, %g3 |
| 8115 | .word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1> |
| 8116 | stxa %g3, [%g3] 0x57 |
| 8117 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 8118 | splash_tba_8_64: |
| 8119 | nop |
| 8120 | ta T_CHANGE_PRIV |
| 8121 | set 0x120000, %r12 |
| 8122 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 8123 | dvapa_8_65: |
| 8124 | nop |
| 8125 | ta T_CHANGE_HPRIV |
| 8126 | mov 0xa50, %r20 |
| 8127 | mov 0x4, %r19 |
| 8128 | sllx %r20, 23, %r20 |
| 8129 | or %r19, %r20, %r19 |
| 8130 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 8131 | mov 0x38, %r18 |
| 8132 | stxa %r31, [%r18]0x58 |
| 8133 | ta T_CHANGE_NONHPRIV |
| 8134 | .word 0xe4dfc030 ! 92: LDXA_R ldxa [%r31, %r16] 0x01, %r18 |
| 8135 | splash_lsu_8_66: |
| 8136 | nop |
| 8137 | ta T_CHANGE_HPRIV |
| 8138 | set 0x6af7fe68, %r2 |
| 8139 | mov 0x3, %r1 |
| 8140 | sllx %r1, 32, %r1 |
| 8141 | or %r1, %r2, %r2 |
| 8142 | .word 0x24800001 ! 1: BLE ble,a <label_0x1> |
| 8143 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8144 | ta T_CHANGE_NONHPRIV |
| 8145 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8146 | ibp_8_67: |
| 8147 | nop |
| 8148 | .word 0x9f8021d0 ! 94: SIR sir 0x01d0 |
| 8149 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 8150 | nop |
| 8151 | ta T_CHANGE_HPRIV |
| 8152 | mov 0x8, %r10 |
| 8153 | set sync_thr_counter6, %r23 |
| 8154 | #ifndef SPC |
| 8155 | ldxa [%g0]0x63, %o1 |
| 8156 | and %o1, 0x38, %o1 |
| 8157 | add %o1, %r23, %r23 |
| 8158 | #endif |
| 8159 | cas [%r23],%g0,%r10 !lock |
| 8160 | brnz %r10, sma_8_68 |
| 8161 | rd %asi, %r12 |
| 8162 | wr %g0, 0x40, %asi |
| 8163 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8164 | set 0x00021fff, %g1 |
| 8165 | stxa %g1, [%g0 + 0x80] %asi |
| 8166 | wr %r12, %g0, %asi |
| 8167 | st %g0, [%r23] |
| 8168 | sma_8_68: |
| 8169 | ta T_CHANGE_NONHPRIV |
| 8170 | .word 0xe5e7e011 ! 96: CASA_R casa [%r31] %asi, %r17, %r18 |
| 8171 | #if (defined SPC || defined CMP) |
| 8172 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_8_69)+16, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 8173 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_8_69)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 8174 | xir_8_69: |
| 8175 | #else |
| 8176 | #if (defined FC) |
| 8177 | !! Generate XIR via RESET_GEN register |
| 8178 | ta T_CHANGE_HPRIV |
| 8179 | rdpr %pstate, %r18 |
| 8180 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 8181 | wrpr %r18, %pstate |
| 8182 | #ifndef XIR_RND_CORES |
| 8183 | ldxa [%g0] 0x63, %o1 |
| 8184 | mov 1, %r18 |
| 8185 | sllx %r18, %o1, %r18 |
| 8186 | #endif |
| 8187 | mov 0x30, %r19 |
| 8188 | setx 0x8900000808, %r16, %r17 |
| 8189 | mov 0x2, %r16 |
| 8190 | xir_8_69: |
| 8191 | stxa %r18, [%r19] 0x41 |
| 8192 | stx %r16, [%r17] |
| 8193 | #endif |
| 8194 | #endif |
| 8195 | .word 0xa984f071 ! 97: WR_SET_SOFTINT_I wr %r19, 0x1071, %set_softint |
| 8196 | #if (defined SPC || defined CMP1) |
| 8197 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_70) + 56, 16, 16)) -> intp(3,0,9,,,,,1) |
| 8198 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_8_70)&0xffffffff) + 56, 16, 16)) -> intp(3,0,12,,,,,1) |
| 8199 | #else |
| 8200 | set 0x8600f0f4, %r28 |
| 8201 | #if (MAX_THREADS == 8) |
| 8202 | and %r28, 0x7ff, %r28 |
| 8203 | #endif |
| 8204 | stxa %r28, [%g0] 0x73 |
| 8205 | #endif |
| 8206 | intvec_8_70: |
| 8207 | .word 0x97a349d3 ! 98: FDIVd fdivd %f44, %f50, %f42 |
| 8208 | fpinit_8_71: |
| 8209 | nop |
| 8210 | setx fp_data_quads, %r19, %r20 |
| 8211 | ldd [%r20], %f0 |
| 8212 | ldd [%r20+8], %f4 |
| 8213 | ld [%r20+16], %fsr |
| 8214 | ld [%r20+24], %r19 |
| 8215 | wr %r19, %g0, %gsr |
| 8216 | .word 0xc3e8228f ! 99: PREFETCHA_I prefetcha [%r0, + 0x028f] %asi, #one_read |
| 8217 | splash_lsu_8_72: |
| 8218 | nop |
| 8219 | ta T_CHANGE_HPRIV |
| 8220 | set 0x58edda22, %r2 |
| 8221 | mov 0x1, %r1 |
| 8222 | sllx %r1, 32, %r1 |
| 8223 | or %r1, %r2, %r2 |
| 8224 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8225 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8226 | .word 0x97b140e3 ! 101: EDGE16LN edge16ln %r5, %r3, %r11 |
| 8227 | nop |
| 8228 | ta T_CHANGE_HPRIV |
| 8229 | mov 0x8, %r10 |
| 8230 | set sync_thr_counter6, %r23 |
| 8231 | #ifndef SPC |
| 8232 | ldxa [%g0]0x63, %o1 |
| 8233 | and %o1, 0x38, %o1 |
| 8234 | add %o1, %r23, %r23 |
| 8235 | #endif |
| 8236 | cas [%r23],%g0,%r10 !lock |
| 8237 | brnz %r10, sma_8_74 |
| 8238 | rd %asi, %r12 |
| 8239 | wr %g0, 0x40, %asi |
| 8240 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8241 | set 0x00061fff, %g1 |
| 8242 | stxa %g1, [%g0 + 0x80] %asi |
| 8243 | wr %r12, %g0, %asi |
| 8244 | st %g0, [%r23] |
| 8245 | sma_8_74: |
| 8246 | ta T_CHANGE_NONHPRIV |
| 8247 | .word 0xd7e7e011 ! 102: CASA_R casa [%r31] %asi, %r17, %r11 |
| 8248 | nop |
| 8249 | mov 0x80, %g3 |
| 8250 | .word 0x24ccc001 ! 1: BRLEZ brlez,a,pt %r19,<label_0xcc001> |
| 8251 | stxa %g3, [%g3] 0x57 |
| 8252 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 8253 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 8254 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 8255 | iaw_8_76: |
| 8256 | nop |
| 8257 | ta T_CHANGE_HPRIV |
| 8258 | mov 8, %r18 |
| 8259 | rd %asi, %r12 |
| 8260 | wr %r0, 0x41, %asi |
| 8261 | set sync_thr_counter4, %r23 |
| 8262 | #ifndef SPC |
| 8263 | ldxa [%g0]0x63, %r8 |
| 8264 | and %r8, 0x38, %r8 ! Core ID |
| 8265 | add %r8, %r23, %r23 |
| 8266 | #else |
| 8267 | mov 0, %r8 |
| 8268 | #endif |
| 8269 | mov 0x8, %r16 |
| 8270 | iaw_startwait8_76: |
| 8271 | cas [%r23],%g0,%r16 !lock |
| 8272 | brz,a %r16, continue_iaw_8_76 |
| 8273 | mov (~0x8&0xf), %r16 |
| 8274 | ld [%r23], %r16 |
| 8275 | iaw_wait8_76: |
| 8276 | brnz %r16, iaw_wait8_76 |
| 8277 | ld [%r23], %r16 |
| 8278 | ba iaw_startwait8_76 |
| 8279 | mov 0x8, %r16 |
| 8280 | continue_iaw_8_76: |
| 8281 | sllx %r16, %r8, %r16 !Mask for my core only |
| 8282 | ldxa [0x58]%asi, %r17 !Running_status |
| 8283 | wait_for_stat_8_76: |
| 8284 | ldxa [0x50]%asi, %r13 !Running_rw |
| 8285 | cmp %r13, %r17 |
| 8286 | bne,a %xcc, wait_for_stat_8_76 |
| 8287 | ldxa [0x58]%asi, %r17 !Running_status |
| 8288 | stxa %r16, [0x68]%asi !Park (W1C) |
| 8289 | ldxa [0x50]%asi, %r14 !Running_rw |
| 8290 | wait_for_iaw_8_76: |
| 8291 | ldxa [0x58]%asi, %r17 !Running_status |
| 8292 | cmp %r14, %r17 |
| 8293 | bne,a %xcc, wait_for_iaw_8_76 |
| 8294 | ldxa [0x50]%asi, %r14 !Running_rw |
| 8295 | iaw_doit8_76: |
| 8296 | mov 0x38, %r18 |
| 8297 | iaw2_8_76: |
| 8298 | rdpr %tba, %r19 |
| 8299 | mov 0x211, %r20 |
| 8300 | sllx %r20, 5, %r20 |
| 8301 | add %r20, %r19, %r19 |
| 8302 | stxa %r19, [%r18]0x50 |
| 8303 | stxa %r16, [0x60] %asi ! Unpark (W1S) |
| 8304 | st %g0, [%r23] !clear lock |
| 8305 | wr %r0, %r12, %asi ! restore %asi |
| 8306 | ta T_CHANGE_NONHPRIV |
| 8307 | .word 0xe19fe0e0 ! 105: LDDFA_I ldda [%r31, 0x00e0], %f16 |
| 8308 | splash_lsu_8_77: |
| 8309 | nop |
| 8310 | ta T_CHANGE_HPRIV |
| 8311 | set 0x5ac702d2, %r2 |
| 8312 | mov 0x6, %r1 |
| 8313 | sllx %r1, 32, %r1 |
| 8314 | or %r1, %r2, %r2 |
| 8315 | .word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1> |
| 8316 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8317 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8318 | .word 0xc1bfde00 ! 107: STDFA_R stda %f0, [%r0, %r31] |
| 8319 | .word 0x91948012 ! 108: WRPR_PIL_R wrpr %r18, %r18, %pil |
| 8320 | splash_lsu_8_79: |
| 8321 | nop |
| 8322 | ta T_CHANGE_HPRIV |
| 8323 | set 0xf499e51d, %r2 |
| 8324 | mov 0x5, %r1 |
| 8325 | sllx %r1, 32, %r1 |
| 8326 | or %r1, %r2, %r2 |
| 8327 | .word 0x2ac84001 ! 1: BRNZ brnz,a,pt %r1,<label_0x84001> |
| 8328 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8329 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8330 | .word 0xe1bfc2c0 ! 110: STDFA_R stda %f16, [%r0, %r31] |
| 8331 | bl skip_8_80 |
| 8332 | fbule skip_8_80 |
| 8333 | .align 128 |
| 8334 | skip_8_80: |
| 8335 | .word 0x24ca0001 ! 111: BRLEZ brlez,a,pt %r8,<label_0xa0001> |
| 8336 | .word 0xc1bfde00 ! 112: STDFA_R stda %f0, [%r0, %r31] |
| 8337 | rd %tick, %r28 |
| 8338 | #if (MAX_THREADS == 8) |
| 8339 | sethi %hi(0x33800), %r27 |
| 8340 | #else |
| 8341 | sethi %hi(0x30000), %r27 |
| 8342 | #endif |
| 8343 | andn %r28, %r27, %r28 |
| 8344 | ta T_CHANGE_HPRIV |
| 8345 | stxa %r28, [%g0] 0x73 |
| 8346 | intvec_8_81: |
| 8347 | .word 0xa7b404d4 ! 113: FCMPNE32 fcmpne32 %d16, %d20, %r19 |
| 8348 | .word 0xc1bfe080 ! 114: STDFA_I stda %f0, [0x0080, %r31] |
| 8349 | nop |
| 8350 | mov 0x80, %g3 |
| 8351 | .word 0x36800001 ! 1: BGE bge,a <label_0x1> |
| 8352 | stxa %g3, [%g3] 0x57 |
| 8353 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 8354 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 8355 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 8356 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 8357 | jmptr_8_82: |
| 8358 | nop |
| 8359 | best_set_reg(0xe0a00000, %r20, %r27) |
| 8360 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 8361 | splash_tba_8_83: |
| 8362 | nop |
| 8363 | ta T_CHANGE_PRIV |
| 8364 | setx 0x00000000003a0000, %r11, %r12 |
| 8365 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 8366 | .word 0x9191800d ! 118: WRPR_PIL_R wrpr %r6, %r13, %pil |
| 8367 | #if (defined SPC || defined CMP) |
| 8368 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_8_85)+48, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 8369 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_8_85)&0xffffffff) + 16, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 8370 | xir_8_85: |
| 8371 | #else |
| 8372 | #if (defined FC) |
| 8373 | !! Generate XIR via RESET_GEN register |
| 8374 | ta T_CHANGE_HPRIV |
| 8375 | rdpr %pstate, %r18 |
| 8376 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 8377 | wrpr %r18, %pstate |
| 8378 | #ifndef XIR_RND_CORES |
| 8379 | ldxa [%g0] 0x63, %o1 |
| 8380 | mov 1, %r18 |
| 8381 | sllx %r18, %o1, %r18 |
| 8382 | #endif |
| 8383 | mov 0x30, %r19 |
| 8384 | setx 0x8900000808, %r16, %r17 |
| 8385 | mov 0x2, %r16 |
| 8386 | xir_8_85: |
| 8387 | stxa %r18, [%r19] 0x41 |
| 8388 | stx %r16, [%r17] |
| 8389 | #endif |
| 8390 | #endif |
| 8391 | .word 0xa980e138 ! 119: WR_SET_SOFTINT_I wr %r3, 0x0138, %set_softint |
| 8392 | cwp_8_86: |
| 8393 | set user_data_start, %o7 |
| 8394 | .word 0x93902000 ! 120: WRPR_CWP_I wrpr %r0, 0x0000, %cwp |
| 8395 | nop |
| 8396 | mov 0x80, %g3 |
| 8397 | stxa %r9, [%r0] ASI_LSU_CONTROL |
| 8398 | stxa %g3, [%g3] 0x57 |
| 8399 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 8400 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 8401 | nop |
| 8402 | ta T_CHANGE_HPRIV ! macro |
| 8403 | donret_8_87: |
| 8404 | rd %pc, %r12 |
| 8405 | mov HIGHVA_HIGHNUM, %r10 |
| 8406 | sllx %r10, 32, %r10 |
| 8407 | or %r12, %r10, %r12 |
| 8408 | add %r12, (donretarg_8_87-donret_8_87), %r12 |
| 8409 | add %r12, 0x4, %r11 ! seq tnpc |
| 8410 | andn %r11, %r10, %r11 ! low VA tnpc |
| 8411 | wrpr %g0, 0x2, %tl |
| 8412 | wrpr %g0, %r12, %tpc |
| 8413 | wrpr %g0, %r11, %tnpc |
| 8414 | set (0x007cab00 | (0x88 << 24)), %r13 |
| 8415 | and %r12, 0xfff, %r14 |
| 8416 | sllx %r14, 32, %r14 |
| 8417 | or %r13, %r14, %r20 |
| 8418 | wrpr %r20, %g0, %tstate |
| 8419 | wrhpr %g0, 0x19ef, %htstate |
| 8420 | ta T_CHANGE_NONPRIV ! rand=0 (8) |
| 8421 | ldx [%r11+%r0], %g1 |
| 8422 | done |
| 8423 | donretarg_8_87: |
| 8424 | .word 0xe66fe156 ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x0156] |
| 8425 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 8426 | .word 0x9345c000 ! 124: RD_TICK_CMPR_REG rd %-, %r9 |
| 8427 | .word 0xe19fdf20 ! 125: LDDFA_R ldda [%r31, %r0], %f16 |
| 8428 | nop |
| 8429 | ta T_CHANGE_HPRIV |
| 8430 | mov 0x8+1, %r10 |
| 8431 | set sync_thr_counter5, %r23 |
| 8432 | #ifndef SPC |
| 8433 | ldxa [%g0]0x63, %o1 |
| 8434 | and %o1, 0x38, %o1 |
| 8435 | add %o1, %r23, %r23 |
| 8436 | sllx %o1, 5, %o3 !(CID*256) |
| 8437 | #endif |
| 8438 | cas [%r23],%g0,%r10 !lock |
| 8439 | brnz %r10, cwq_8_89 |
| 8440 | rd %asi, %r12 |
| 8441 | wr %g0, 0x40, %asi |
| 8442 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 8443 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 8444 | cmp %l1, 1 |
| 8445 | bne cwq_8_89 |
| 8446 | set CWQ_BASE, %l6 |
| 8447 | #ifndef SPC |
| 8448 | add %l6, %o3, %l6 |
| 8449 | #endif |
| 8450 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 8451 | best_set_reg(0x20610090, %l1, %l2) !# Control Word |
| 8452 | sllx %l2, 32, %l2 |
| 8453 | stx %l2, [%l6 + 0x0] |
| 8454 | membar #Sync |
| 8455 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 8456 | sub %l2, 0x40, %l2 |
| 8457 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 8458 | wr %r12, %g0, %asi |
| 8459 | st %g0, [%r23] |
| 8460 | cwq_8_89: |
| 8461 | ta T_CHANGE_NONHPRIV |
| 8462 | .word 0x99414000 ! 126: RDPC rd %pc, %r12 |
| 8463 | .word 0x95a00169 ! 127: FABSq dis not found |
| 8464 | |
| 8465 | #if (defined SPC || defined CMP) |
| 8466 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_8_91)+0, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 8467 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_8_91)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x8),1,3,,,,,1) |
| 8468 | xir_8_91: |
| 8469 | #else |
| 8470 | #if (defined FC) |
| 8471 | !! Generate XIR via RESET_GEN register |
| 8472 | ta T_CHANGE_HPRIV |
| 8473 | rdpr %pstate, %r18 |
| 8474 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 8475 | wrpr %r18, %pstate |
| 8476 | #ifndef XIR_RND_CORES |
| 8477 | ldxa [%g0] 0x63, %o1 |
| 8478 | mov 1, %r18 |
| 8479 | sllx %r18, %o1, %r18 |
| 8480 | #endif |
| 8481 | mov 0x30, %r19 |
| 8482 | setx 0x8900000808, %r16, %r17 |
| 8483 | mov 0x2, %r16 |
| 8484 | xir_8_91: |
| 8485 | stxa %r18, [%r19] 0x41 |
| 8486 | stx %r16, [%r17] |
| 8487 | #endif |
| 8488 | #endif |
| 8489 | .word 0xa9846abb ! 128: WR_SET_SOFTINT_I wr %r17, 0x0abb, %set_softint |
| 8490 | memptr_8_92: |
| 8491 | set 0x60740000, %r31 |
| 8492 | .word 0x8584beb0 ! 129: WRCCR_I wr %r18, 0x1eb0, %ccr |
| 8493 | rd %tick, %r28 |
| 8494 | #if (MAX_THREADS == 8) |
| 8495 | sethi %hi(0x33800), %r27 |
| 8496 | #else |
| 8497 | sethi %hi(0x30000), %r27 |
| 8498 | #endif |
| 8499 | andn %r28, %r27, %r28 |
| 8500 | ta T_CHANGE_HPRIV |
| 8501 | stxa %r28, [%g0] 0x73 |
| 8502 | intvec_8_93: |
| 8503 | .word 0x9f803ec7 ! 130: SIR sir 0x1ec7 |
| 8504 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 8505 | memptr_8_95: |
| 8506 | set 0x60140000, %r31 |
| 8507 | .word 0x8584eb63 ! 132: WRCCR_I wr %r19, 0x0b63, %ccr |
| 8508 | splash_hpstate_8_96: |
| 8509 | .word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1> |
| 8510 | .word 0x81982c2e ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x0c2e, %hpstate |
| 8511 | jmptr_8_97: |
| 8512 | nop |
| 8513 | best_set_reg(0xe0a00000, %r20, %r27) |
| 8514 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 8515 | bgu skip_8_98 |
| 8516 | stxa %r7, [%r0] ASI_LSU_CONTROL |
| 8517 | .word 0x87ac0a4a ! 1: FCMPd fcmpd %fcc<n>, %f16, %f10 |
| 8518 | stxa %r19, [%r0] ASI_LSU_CONTROL |
| 8519 | .align 128 |
| 8520 | skip_8_98: |
| 8521 | .word 0xc36fe183 ! 135: PREFETCH_I prefetch [%r31 + 0x0183], #one_read |
| 8522 | .word 0x8d90268f ! 136: WRPR_PSTATE_I wrpr %r0, 0x068f, %pstate |
| 8523 | .word 0xa5a00162 ! 137: FABSq dis not found |
| 8524 | |
| 8525 | nop |
| 8526 | ta T_CHANGE_HPRIV |
| 8527 | mov 0x8, %r10 |
| 8528 | set sync_thr_counter6, %r23 |
| 8529 | #ifndef SPC |
| 8530 | ldxa [%g0]0x63, %o1 |
| 8531 | and %o1, 0x38, %o1 |
| 8532 | add %o1, %r23, %r23 |
| 8533 | #endif |
| 8534 | cas [%r23],%g0,%r10 !lock |
| 8535 | brnz %r10, sma_8_101 |
| 8536 | rd %asi, %r12 |
| 8537 | wr %g0, 0x40, %asi |
| 8538 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8539 | set 0x000a1fff, %g1 |
| 8540 | stxa %g1, [%g0 + 0x80] %asi |
| 8541 | wr %r12, %g0, %asi |
| 8542 | st %g0, [%r23] |
| 8543 | sma_8_101: |
| 8544 | ta T_CHANGE_NONHPRIV |
| 8545 | .word 0xe1e7e00c ! 138: CASA_R casa [%r31] %asi, %r12, %r16 |
| 8546 | .word 0x93b400e3 ! 139: EDGE16LN edge16ln %r16, %r3, %r9 |
| 8547 | splash_lsu_8_103: |
| 8548 | nop |
| 8549 | ta T_CHANGE_HPRIV |
| 8550 | set 0xeb246eb6, %r2 |
| 8551 | mov 0x2, %r1 |
| 8552 | sllx %r1, 32, %r1 |
| 8553 | or %r1, %r2, %r2 |
| 8554 | .word 0x2a800001 ! 1: BCS bcs,a <label_0x1> |
| 8555 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8556 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8557 | .word 0x91690005 ! 141: SDIVX_R sdivx %r4, %r5, %r8 |
| 8558 | .word 0xe19fe1a0 ! 142: LDDFA_I ldda [%r31, 0x01a0], %f16 |
| 8559 | .word 0x9191400c ! 143: WRPR_PIL_R wrpr %r5, %r12, %pil |
| 8560 | splash_hpstate_8_105: |
| 8561 | ta T_CHANGE_NONHPRIV |
| 8562 | .word 0x81982f4f ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x0f4f, %hpstate |
| 8563 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 8564 | nop |
| 8565 | ta T_CHANGE_HPRIV |
| 8566 | mov 0x8, %r10 |
| 8567 | set sync_thr_counter6, %r23 |
| 8568 | #ifndef SPC |
| 8569 | ldxa [%g0]0x63, %o1 |
| 8570 | and %o1, 0x38, %o1 |
| 8571 | add %o1, %r23, %r23 |
| 8572 | #endif |
| 8573 | cas [%r23],%g0,%r10 !lock |
| 8574 | brnz %r10, sma_8_107 |
| 8575 | rd %asi, %r12 |
| 8576 | wr %g0, 0x40, %asi |
| 8577 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8578 | set 0x000a1fff, %g1 |
| 8579 | stxa %g1, [%g0 + 0x80] %asi |
| 8580 | wr %r12, %g0, %asi |
| 8581 | st %g0, [%r23] |
| 8582 | sma_8_107: |
| 8583 | ta T_CHANGE_NONHPRIV |
| 8584 | .word 0xd1e7e009 ! 146: CASA_R casa [%r31] %asi, %r9, %r8 |
| 8585 | fpinit_8_108: |
| 8586 | nop |
| 8587 | setx fp_data_quads, %r19, %r20 |
| 8588 | ldd [%r20], %f0 |
| 8589 | ldd [%r20+8], %f4 |
| 8590 | ld [%r20+16], %fsr |
| 8591 | ld [%r20+24], %r19 |
| 8592 | wr %r19, %g0, %gsr |
| 8593 | .word 0x87a80a44 ! 147: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 8594 | intveclr_8_109: |
| 8595 | nop |
| 8596 | ta T_CHANGE_HPRIV |
| 8597 | setx 0x0c1fd3e3cd6f6159, %r1, %r28 |
| 8598 | stxa %r28, [%g0] 0x72 |
| 8599 | ta T_CHANGE_NONHPRIV |
| 8600 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 8601 | brcommon3_8_110: |
| 8602 | nop |
| 8603 | setx common_target, %r12, %r27 |
| 8604 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 8605 | ba,a .+12 |
| 8606 | .word 0xd06fe1b0 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x01b0] |
| 8607 | ba,a .+8 |
| 8608 | jmpl %r27+0, %r27 |
| 8609 | .word 0xd11fc00d ! 149: LDDF_R ldd [%r31, %r13], %f8 |
| 8610 | .word 0x2c800001 ! 1: BNEG bneg,a <label_0x1> |
| 8611 | .word 0x8d902841 ! 150: WRPR_PSTATE_I wrpr %r0, 0x0841, %pstate |
| 8612 | nop |
| 8613 | nop |
| 8614 | ta T_CHANGE_PRIV |
| 8615 | wrpr %g0, %g0, %gl |
| 8616 | nop |
| 8617 | nop |
| 8618 | .text |
| 8619 | setx join_lbl_0_0, %g1, %g2 |
| 8620 | jmp %g2 |
| 8621 | nop |
| 8622 | fork_lbl_0_3: |
| 8623 | ta T_CHANGE_NONHPRIV |
| 8624 | .word 0xe877e062 ! 1: STX_I stx %r20, [%r31 + 0x0062] |
| 8625 | br_longdelay4_4_0: |
| 8626 | nop |
| 8627 | not %g0, %r27 |
| 8628 | jmpl %r27+0, %r27 |
| 8629 | .word 0x9d902002 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0002, %wstate |
| 8630 | .word 0xe93fe1a2 ! 3: STDF_I std %f20, [0x01a2, %r31] |
| 8631 | fpinit_4_1: |
| 8632 | nop |
| 8633 | setx fp_data_quads, %r19, %r20 |
| 8634 | ldd [%r20], %f0 |
| 8635 | ldd [%r20+8], %f4 |
| 8636 | ld [%r20+16], %fsr |
| 8637 | ld [%r20+24], %r19 |
| 8638 | wr %r19, %g0, %gsr |
| 8639 | .word 0x8db00484 ! 4: FCMPLE32 fcmple32 %d0, %d4, %r6 |
| 8640 | splash_lsu_4_2: |
| 8641 | nop |
| 8642 | ta T_CHANGE_HPRIV |
| 8643 | set 0xdbcc1111, %r2 |
| 8644 | mov 0x2, %r1 |
| 8645 | sllx %r1, 32, %r1 |
| 8646 | or %r1, %r2, %r2 |
| 8647 | .word 0x26cd0001 ! 1: BRLZ brlz,a,pt %r20,<label_0xd0001> |
| 8648 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8649 | ta T_CHANGE_NONHPRIV |
| 8650 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8651 | splash_hpstate_4_3: |
| 8652 | .word 0x81983596 ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x1596, %hpstate |
| 8653 | memptr_4_4: |
| 8654 | set 0x60140000, %r31 |
| 8655 | .word 0x85852ada ! 7: WRCCR_I wr %r20, 0x0ada, %ccr |
| 8656 | nop |
| 8657 | mov 0x80, %g3 |
| 8658 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 8659 | stxa %g3, [%g3] 0x5f |
| 8660 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 8661 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 8662 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 8663 | .word 0xc19fe1a0 ! 9: LDDFA_I ldda [%r31, 0x01a0], %f0 |
| 8664 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 8665 | .word 0xc1bfc2c0 ! 11: STDFA_R stda %f0, [%r0, %r31] |
| 8666 | dvapa_4_6: |
| 8667 | nop |
| 8668 | ta T_CHANGE_HPRIV |
| 8669 | mov 0xff1, %r20 |
| 8670 | mov 0x13, %r19 |
| 8671 | sllx %r20, 23, %r20 |
| 8672 | or %r19, %r20, %r19 |
| 8673 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 8674 | mov 0x38, %r18 |
| 8675 | stxa %r31, [%r18]0x58 |
| 8676 | ta T_CHANGE_NONHPRIV |
| 8677 | .word 0xe1bfe0c0 ! 12: STDFA_I stda %f16, [0x00c0, %r31] |
| 8678 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 8679 | jmptr_4_7: |
| 8680 | nop |
| 8681 | best_set_reg(0xe1200000, %r20, %r27) |
| 8682 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 8683 | pmu_4_8: |
| 8684 | nop |
| 8685 | ta T_CHANGE_PRIV |
| 8686 | setx 0xffffffb2ffffffa2, %g1, %g7 |
| 8687 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 8688 | jmptr_4_9: |
| 8689 | nop |
| 8690 | best_set_reg(0xe1200000, %r20, %r27) |
| 8691 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 8692 | nop |
| 8693 | ta T_CHANGE_HPRIV |
| 8694 | mov 0x4, %r10 |
| 8695 | set sync_thr_counter6, %r23 |
| 8696 | #ifndef SPC |
| 8697 | ldxa [%g0]0x63, %o1 |
| 8698 | and %o1, 0x38, %o1 |
| 8699 | add %o1, %r23, %r23 |
| 8700 | #endif |
| 8701 | cas [%r23],%g0,%r10 !lock |
| 8702 | brnz %r10, sma_4_10 |
| 8703 | rd %asi, %r12 |
| 8704 | wr %g0, 0x40, %asi |
| 8705 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8706 | set 0x000a1fff, %g1 |
| 8707 | stxa %g1, [%g0 + 0x80] %asi |
| 8708 | wr %r12, %g0, %asi |
| 8709 | st %g0, [%r23] |
| 8710 | sma_4_10: |
| 8711 | ta T_CHANGE_NONHPRIV |
| 8712 | .word 0xe9e7e012 ! 17: CASA_R casa [%r31] %asi, %r18, %r20 |
| 8713 | .word 0x87802083 ! 18: WRASI_I wr %r0, 0x0083, %asi |
| 8714 | splash_lsu_4_11: |
| 8715 | nop |
| 8716 | ta T_CHANGE_HPRIV |
| 8717 | set 0xff6ddb18, %r2 |
| 8718 | mov 0x4, %r1 |
| 8719 | sllx %r1, 32, %r1 |
| 8720 | or %r1, %r2, %r2 |
| 8721 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8722 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8723 | .word 0xe93fe0b4 ! 20: STDF_I std %f20, [0x00b4, %r31] |
| 8724 | brcommon1_4_12: |
| 8725 | nop |
| 8726 | setx common_target, %r12, %r27 |
| 8727 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 8728 | ba,a .+12 |
| 8729 | .word 0xa9b7c7cc ! 1: PDIST pdistn %d62, %d12, %d20 |
| 8730 | ba,a .+8 |
| 8731 | jmpl %r27+0, %r27 |
| 8732 | .word 0xa970317a ! 21: POPC_I popc 0x117a, %r20 |
| 8733 | splash_lsu_4_13: |
| 8734 | nop |
| 8735 | ta T_CHANGE_HPRIV |
| 8736 | set 0x4db7d8f2, %r2 |
| 8737 | mov 0x6, %r1 |
| 8738 | sllx %r1, 32, %r1 |
| 8739 | or %r1, %r2, %r2 |
| 8740 | .word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1> |
| 8741 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8742 | ta T_CHANGE_NONHPRIV |
| 8743 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8744 | .word 0xe19fd920 ! 23: LDDFA_R ldda [%r31, %r0], %f16 |
| 8745 | .word 0xe1bfde00 ! 24: STDFA_R stda %f16, [%r0, %r31] |
| 8746 | pmu_4_14: |
| 8747 | nop |
| 8748 | ta T_CHANGE_PRIV |
| 8749 | setx 0xffffffb0ffffffaa, %g1, %g7 |
| 8750 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 8751 | rd %tick, %r28 |
| 8752 | #if (MAX_THREADS == 8) |
| 8753 | sethi %hi(0x33800), %r27 |
| 8754 | #else |
| 8755 | sethi %hi(0x30000), %r27 |
| 8756 | #endif |
| 8757 | andn %r28, %r27, %r28 |
| 8758 | ta T_CHANGE_HPRIV |
| 8759 | stxa %r28, [%g0] 0x73 |
| 8760 | .word 0xa5b284d3 ! 1: FCMPNE32 fcmpne32 %d10, %d50, %r18 |
| 8761 | intvec_4_15: |
| 8762 | .word 0x99b304d4 ! 26: FCMPNE32 fcmpne32 %d12, %d20, %r12 |
| 8763 | .word 0x91924004 ! 27: WRPR_PIL_R wrpr %r9, %r4, %pil |
| 8764 | nop |
| 8765 | mov 0x80, %g3 |
| 8766 | stxa %r11, [%r0] ASI_LSU_CONTROL |
| 8767 | stxa %g3, [%g3] 0x57 |
| 8768 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 8769 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 8770 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 8771 | #if (defined SPC || defined CMP) |
| 8772 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_4_17)+32, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 8773 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_4_17)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 8774 | xir_4_17: |
| 8775 | #else |
| 8776 | #if (defined FC) |
| 8777 | !! Generate XIR via RESET_GEN register |
| 8778 | ta T_CHANGE_HPRIV |
| 8779 | rdpr %pstate, %r18 |
| 8780 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 8781 | wrpr %r18, %pstate |
| 8782 | #ifndef XIR_RND_CORES |
| 8783 | ldxa [%g0] 0x63, %o1 |
| 8784 | mov 1, %r18 |
| 8785 | sllx %r18, %o1, %r18 |
| 8786 | #endif |
| 8787 | mov 0x30, %r19 |
| 8788 | setx 0x8900000808, %r16, %r17 |
| 8789 | mov 0x2, %r16 |
| 8790 | xir_4_17: |
| 8791 | stxa %r18, [%r19] 0x41 |
| 8792 | stx %r16, [%r17] |
| 8793 | #endif |
| 8794 | #endif |
| 8795 | .word 0xa981e7d2 ! 29: WR_SET_SOFTINT_I wr %r7, 0x07d2, %set_softint |
| 8796 | .word 0x99a00161 ! 30: FABSq dis not found |
| 8797 | |
| 8798 | .word 0xa9a00173 ! 31: FABSq dis not found |
| 8799 | |
| 8800 | tagged_4_20: |
| 8801 | tsubcctv %r2, 0x1fb3, %r20 |
| 8802 | .word 0xd807e05c ! 32: LDUW_I lduw [%r31 + 0x005c], %r12 |
| 8803 | mondo_4_21: |
| 8804 | nop |
| 8805 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 8806 | stxa %r7, [%r0+0x3c0] %asi |
| 8807 | .word 0x9d950012 ! 33: WRPR_WSTATE_R wrpr %r20, %r18, %wstate |
| 8808 | .word 0xb181000a ! 34: WR_STICK_REG_R wr %r4, %r10, %- |
| 8809 | nop |
| 8810 | ta T_CHANGE_HPRIV |
| 8811 | mov 0x4, %r10 |
| 8812 | set sync_thr_counter6, %r23 |
| 8813 | #ifndef SPC |
| 8814 | ldxa [%g0]0x63, %o1 |
| 8815 | and %o1, 0x38, %o1 |
| 8816 | add %o1, %r23, %r23 |
| 8817 | #endif |
| 8818 | cas [%r23],%g0,%r10 !lock |
| 8819 | brnz %r10, sma_4_22 |
| 8820 | rd %asi, %r12 |
| 8821 | wr %g0, 0x40, %asi |
| 8822 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8823 | set 0x001e1fff, %g1 |
| 8824 | stxa %g1, [%g0 + 0x80] %asi |
| 8825 | wr %r12, %g0, %asi |
| 8826 | st %g0, [%r23] |
| 8827 | sma_4_22: |
| 8828 | ta T_CHANGE_NONHPRIV |
| 8829 | .word 0xd9e7e008 ! 35: CASA_R casa [%r31] %asi, %r8, %r12 |
| 8830 | nop |
| 8831 | ta T_CHANGE_HPRIV |
| 8832 | mov 0x4, %r10 |
| 8833 | set sync_thr_counter6, %r23 |
| 8834 | #ifndef SPC |
| 8835 | ldxa [%g0]0x63, %o1 |
| 8836 | and %o1, 0x38, %o1 |
| 8837 | add %o1, %r23, %r23 |
| 8838 | #endif |
| 8839 | cas [%r23],%g0,%r10 !lock |
| 8840 | brnz %r10, sma_4_23 |
| 8841 | rd %asi, %r12 |
| 8842 | wr %g0, 0x40, %asi |
| 8843 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 8844 | set 0x00061fff, %g1 |
| 8845 | stxa %g1, [%g0 + 0x80] %asi |
| 8846 | wr %r12, %g0, %asi |
| 8847 | st %g0, [%r23] |
| 8848 | sma_4_23: |
| 8849 | ta T_CHANGE_NONHPRIV |
| 8850 | .word 0xd9e7e012 ! 36: CASA_R casa [%r31] %asi, %r18, %r12 |
| 8851 | splash_tba_4_24: |
| 8852 | nop |
| 8853 | ta T_CHANGE_PRIV |
| 8854 | set 0x120000, %r12 |
| 8855 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 8856 | splash_lsu_4_25: |
| 8857 | nop |
| 8858 | ta T_CHANGE_HPRIV |
| 8859 | set 0xbc467e9a, %r2 |
| 8860 | mov 0x1, %r1 |
| 8861 | sllx %r1, 32, %r1 |
| 8862 | or %r1, %r2, %r2 |
| 8863 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 8864 | ta T_CHANGE_NONHPRIV |
| 8865 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 8866 | #if (defined SPC || defined CMP1) |
| 8867 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_26) + 32, 16, 16)) -> intp(1,0,15,,,,,1) |
| 8868 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_4_26)&0xffffffff) + 48, 16, 16)) -> intp(3,0,8,,,,,1) |
| 8869 | #else |
| 8870 | set 0xf230b67c, %r28 |
| 8871 | #if (MAX_THREADS == 8) |
| 8872 | and %r28, 0x7ff, %r28 |
| 8873 | #endif |
| 8874 | stxa %r28, [%g0] 0x73 |
| 8875 | #endif |
| 8876 | .word 0xa3b1c4d2 ! 1: FCMPNE32 fcmpne32 %d38, %d18, %r17 |
| 8877 | intvec_4_26: |
| 8878 | .word 0xa7b0c4c1 ! 39: FCMPNE32 fcmpne32 %d34, %d32, %r19 |
| 8879 | .word 0xd727e1c4 ! 40: STF_I st %f11, [0x01c4, %r31] |
| 8880 | .word 0xd627e0d0 ! 41: STW_I stw %r11, [%r31 + 0x00d0] |
| 8881 | jmptr_4_27: |
| 8882 | nop |
| 8883 | best_set_reg(0xe1200000, %r20, %r27) |
| 8884 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 8885 | splash_tba_4_28: |
| 8886 | nop |
| 8887 | ta T_CHANGE_PRIV |
| 8888 | set 0x120000, %r12 |
| 8889 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 8890 | set 0x3803, %l3 |
| 8891 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 8892 | .word 0x93b307d3 ! 44: PDIST pdistn %d12, %d50, %d40 |
| 8893 | pmu_4_29: |
| 8894 | nop |
| 8895 | setx 0xffffffb9ffffffa9, %g1, %g7 |
| 8896 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 8897 | brcommon3_4_30: |
| 8898 | nop |
| 8899 | setx common_target, %r12, %r27 |
| 8900 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 8901 | ba,a .+12 |
| 8902 | .word 0xe3e7c02d ! 1: CASA_I casa [%r31] 0x 1, %r13, %r17 |
| 8903 | ba,a .+8 |
| 8904 | jmpl %r27+0, %r27 |
| 8905 | .word 0xe23fe0b0 ! 46: STD_I std %r17, [%r31 + 0x00b0] |
| 8906 | brcommon3_4_31: |
| 8907 | nop |
| 8908 | setx common_target, %r12, %r27 |
| 8909 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 8910 | ba,a .+12 |
| 8911 | .word 0xe26fe120 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x0120] |
| 8912 | ba,a .+8 |
| 8913 | jmpl %r27+0, %r27 |
| 8914 | stxa %r20, [%r0] ASI_LSU_CONTROL |
| 8915 | .word 0x95aac831 ! 47: FMOVGE fmovs %fcc1, %f17, %f10 |
| 8916 | brcommon3_4_32: |
| 8917 | nop |
| 8918 | setx common_target, %r12, %r27 |
| 8919 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 8920 | ba,a .+12 |
| 8921 | .word 0xd737e0b0 ! 1: STQF_I - %f11, [0x00b0, %r31] |
| 8922 | ba,a .+8 |
| 8923 | jmpl %r27+0, %r27 |
| 8924 | .word 0xd697c02c ! 48: LDUHA_R lduha [%r31, %r12] 0x01, %r11 |
| 8925 | nop |
| 8926 | mov 0x80, %g3 |
| 8927 | .word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1> |
| 8928 | stxa %g3, [%g3] 0x5f |
| 8929 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 8930 | nop |
| 8931 | ta T_CHANGE_HPRIV ! macro |
| 8932 | donret_4_33: |
| 8933 | rd %pc, %r12 |
| 8934 | mov HIGHVA_HIGHNUM, %r10 |
| 8935 | sllx %r10, 32, %r10 |
| 8936 | or %r12, %r10, %r12 |
| 8937 | add %r12, (donretarg_4_33-donret_4_33), %r12 |
| 8938 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 8939 | andn %r11, %r10, %r11 ! low VA tnpc |
| 8940 | wrpr %g0, 0x1, %tl |
| 8941 | wrpr %g0, %r12, %tpc |
| 8942 | wrpr %g0, %r11, %tnpc |
| 8943 | set (0x00ef8200 | (22 << 24)), %r13 |
| 8944 | and %r12, 0xfff, %r14 |
| 8945 | sllx %r14, 32, %r14 |
| 8946 | or %r13, %r14, %r20 |
| 8947 | wrpr %r20, %g0, %tstate |
| 8948 | wrhpr %g0, 0x5c4, %htstate |
| 8949 | ta T_CHANGE_NONHPRIV ! rand=1 (4) |
| 8950 | ldx [%r11+%r0], %g1 |
| 8951 | done |
| 8952 | donretarg_4_33: |
| 8953 | .word 0x2d400001 ! 50: FBPG fbg,a,pn %fcc0, <label_0x1> |
| 8954 | #if (defined SPC || defined CMP1) |
| 8955 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_34) + 16, 16, 16)) -> intp(0,0,9,,,,,1) |
| 8956 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_4_34)&0xffffffff) + 16, 16, 16)) -> intp(0,0,10,,,,,1) |
| 8957 | #else |
| 8958 | set 0x6d8059fd, %r28 |
| 8959 | #if (MAX_THREADS == 8) |
| 8960 | and %r28, 0x7ff, %r28 |
| 8961 | #endif |
| 8962 | stxa %r28, [%g0] 0x73 |
| 8963 | #endif |
| 8964 | intvec_4_34: |
| 8965 | .word 0x39400001 ! 51: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 8966 | .word 0xe927e03c ! 52: STF_I st %f20, [0x003c, %r31] |
| 8967 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 8968 | splash_tba_4_35: |
| 8969 | nop |
| 8970 | ta T_CHANGE_PRIV |
| 8971 | setx 0x0000000400380000, %r11, %r12 |
| 8972 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 8973 | .word 0xa1a509d0 ! 55: FDIVd fdivd %f20, %f16, %f16 |
| 8974 | ibp_4_37: |
| 8975 | nop |
| 8976 | ta T_CHANGE_HPRIV |
| 8977 | mov 8, %r18 |
| 8978 | rd %asi, %r12 |
| 8979 | wr %r0, 0x41, %asi |
| 8980 | set sync_thr_counter4, %r23 |
| 8981 | #ifndef SPC |
| 8982 | ldxa [%g0]0x63, %r8 |
| 8983 | and %r8, 0x38, %r8 ! Core ID |
| 8984 | add %r8, %r23, %r23 |
| 8985 | #else |
| 8986 | mov 0, %r8 |
| 8987 | #endif |
| 8988 | mov 0x4, %r16 |
| 8989 | ibp_startwait4_37: |
| 8990 | cas [%r23],%g0,%r16 !lock |
| 8991 | brz,a %r16, continue_ibp_4_37 |
| 8992 | mov (~0x4&0xf), %r16 |
| 8993 | ld [%r23], %r16 |
| 8994 | ibp_wait4_37: |
| 8995 | brnz %r16, ibp_wait4_37 |
| 8996 | ld [%r23], %r16 |
| 8997 | ba ibp_startwait4_37 |
| 8998 | mov 0x4, %r16 |
| 8999 | continue_ibp_4_37: |
| 9000 | sllx %r16, %r8, %r16 !Mask for my core only |
| 9001 | ldxa [0x58]%asi, %r17 !Running_status |
| 9002 | wait_for_stat_4_37: |
| 9003 | ldxa [0x50]%asi, %r13 !Running_rw |
| 9004 | cmp %r13, %r17 |
| 9005 | bne,a %xcc, wait_for_stat_4_37 |
| 9006 | ldxa [0x58]%asi, %r17 !Running_status |
| 9007 | stxa %r16, [0x68]%asi !Park (W1C) |
| 9008 | ldxa [0x50]%asi, %r14 !Running_rw |
| 9009 | wait_for_ibp_4_37: |
| 9010 | ldxa [0x58]%asi, %r17 !Running_status |
| 9011 | cmp %r14, %r17 |
| 9012 | bne,a %xcc, wait_for_ibp_4_37 |
| 9013 | ldxa [0x50]%asi, %r14 !Running_rw |
| 9014 | ibp_doit4_37: |
| 9015 | best_set_reg(0x00000040bec00be4,%r19, %r20) |
| 9016 | stxa %r20, [%r18]0x42 |
| 9017 | stxa %r16, [0x60] %asi !Unpark (W1S) |
| 9018 | st %g0, [%r23] !clear lock |
| 9019 | wr %r0, %r12, %asi !restore %asi |
| 9020 | ta T_CHANGE_NONHPRIV |
| 9021 | .word 0x87ad0a4c ! 56: FCMPd fcmpd %fcc<n>, %f20, %f12 |
| 9022 | brcommon3_4_38: |
| 9023 | nop |
| 9024 | setx common_target, %r12, %r27 |
| 9025 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 9026 | ba,a .+12 |
| 9027 | .word 0xe937e170 ! 1: STQF_I - %f20, [0x0170, %r31] |
| 9028 | ba,a .+8 |
| 9029 | jmpl %r27+0, %r27 |
| 9030 | .word 0xc32fc012 ! 57: STXFSR_R st-sfr %f1, [%r18, %r31] |
| 9031 | ibp_4_39: |
| 9032 | nop |
| 9033 | ta T_CHANGE_HPRIV |
| 9034 | mov 8, %r18 |
| 9035 | rd %asi, %r12 |
| 9036 | wr %r0, 0x41, %asi |
| 9037 | set sync_thr_counter4, %r23 |
| 9038 | #ifndef SPC |
| 9039 | ldxa [%g0]0x63, %r8 |
| 9040 | and %r8, 0x38, %r8 ! Core ID |
| 9041 | add %r8, %r23, %r23 |
| 9042 | #else |
| 9043 | mov 0, %r8 |
| 9044 | #endif |
| 9045 | mov 0x4, %r16 |
| 9046 | ibp_startwait4_39: |
| 9047 | cas [%r23],%g0,%r16 !lock |
| 9048 | brz,a %r16, continue_ibp_4_39 |
| 9049 | mov (~0x4&0xf), %r16 |
| 9050 | ld [%r23], %r16 |
| 9051 | ibp_wait4_39: |
| 9052 | brnz %r16, ibp_wait4_39 |
| 9053 | ld [%r23], %r16 |
| 9054 | ba ibp_startwait4_39 |
| 9055 | mov 0x4, %r16 |
| 9056 | continue_ibp_4_39: |
| 9057 | sllx %r16, %r8, %r16 !Mask for my core only |
| 9058 | ldxa [0x58]%asi, %r17 !Running_status |
| 9059 | wait_for_stat_4_39: |
| 9060 | ldxa [0x50]%asi, %r13 !Running_rw |
| 9061 | cmp %r13, %r17 |
| 9062 | bne,a %xcc, wait_for_stat_4_39 |
| 9063 | ldxa [0x58]%asi, %r17 !Running_status |
| 9064 | stxa %r16, [0x68]%asi !Park (W1C) |
| 9065 | ldxa [0x50]%asi, %r14 !Running_rw |
| 9066 | wait_for_ibp_4_39: |
| 9067 | ldxa [0x58]%asi, %r17 !Running_status |
| 9068 | cmp %r14, %r17 |
| 9069 | bne,a %xcc, wait_for_ibp_4_39 |
| 9070 | ldxa [0x50]%asi, %r14 !Running_rw |
| 9071 | ibp_doit4_39: |
| 9072 | best_set_reg(0x00000040ddcbe4b9,%r19, %r20) |
| 9073 | stxa %r20, [%r18]0x42 |
| 9074 | stxa %r16, [0x60] %asi !Unpark (W1S) |
| 9075 | st %g0, [%r23] !clear lock |
| 9076 | wr %r0, %r12, %asi !restore %asi |
| 9077 | ta T_CHANGE_NONHPRIV |
| 9078 | .word 0x97b34492 ! 58: FCMPLE32 fcmple32 %d44, %d18, %r11 |
| 9079 | nop |
| 9080 | ta T_CHANGE_HPRIV ! macro |
| 9081 | donret_4_40: |
| 9082 | rd %pc, %r12 |
| 9083 | mov HIGHVA_HIGHNUM, %r10 |
| 9084 | sllx %r10, 32, %r10 |
| 9085 | or %r12, %r10, %r12 |
| 9086 | add %r12, (donretarg_4_40-donret_4_40+4), %r12 |
| 9087 | add %r12, 0x4, %r11 ! seq tnpc |
| 9088 | andn %r12, %r10, %r12 ! low VA tpc |
| 9089 | wrpr %g0, 0x2, %tl |
| 9090 | wrpr %g0, %r12, %tpc |
| 9091 | wrpr %g0, %r11, %tnpc |
| 9092 | set (0x00bc0c00 | (0x89 << 24)), %r13 |
| 9093 | and %r12, 0xfff, %r14 |
| 9094 | sllx %r14, 32, %r14 |
| 9095 | or %r13, %r14, %r20 |
| 9096 | wrpr %r20, %g0, %tstate |
| 9097 | wrhpr %g0, 0xd1c, %htstate |
| 9098 | ta T_CHANGE_NONPRIV ! rand=0 (4) |
| 9099 | ldx [%r12+%r0], %g1 |
| 9100 | retry |
| 9101 | donretarg_4_40: |
| 9102 | .word 0x20800001 ! 59: BN bn,a <label_0x1> |
| 9103 | memptr_4_41: |
| 9104 | set 0x60140000, %r31 |
| 9105 | .word 0x85852e02 ! 60: WRCCR_I wr %r20, 0x0e02, %ccr |
| 9106 | nop |
| 9107 | mov 0x80, %g3 |
| 9108 | stxa %r11, [%r0] ASI_LSU_CONTROL |
| 9109 | stxa %g3, [%g3] 0x5f |
| 9110 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 9111 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 9112 | .word 0xa953c000 ! 62: RDPR_FQ <illegal instruction> |
| 9113 | fbul skip_4_42 |
| 9114 | fbuge,a,pn %fcc0, skip_4_42 |
| 9115 | .align 1024 |
| 9116 | skip_4_42: |
| 9117 | .word 0x24cc8001 ! 63: BRLEZ brlez,a,pt %r18,<label_0xc8001> |
| 9118 | brgez,pt %r8, skip_4_43 |
| 9119 | stxa %r12, [%r0] ASI_LSU_CONTROL |
| 9120 | be,a skip_4_43 |
| 9121 | stxa %r9, [%r0] ASI_LSU_CONTROL |
| 9122 | .align 1024 |
| 9123 | skip_4_43: |
| 9124 | .word 0xc32fc000 ! 64: STXFSR_R st-sfr %f1, [%r0, %r31] |
| 9125 | .word 0xc19fde00 ! 65: LDDFA_R ldda [%r31, %r0], %f0 |
| 9126 | nop |
| 9127 | ta T_CHANGE_HPRIV |
| 9128 | mov 0x4+1, %r10 |
| 9129 | set sync_thr_counter5, %r23 |
| 9130 | #ifndef SPC |
| 9131 | ldxa [%g0]0x63, %o1 |
| 9132 | and %o1, 0x38, %o1 |
| 9133 | add %o1, %r23, %r23 |
| 9134 | sllx %o1, 5, %o3 !(CID*256) |
| 9135 | #endif |
| 9136 | cas [%r23],%g0,%r10 !lock |
| 9137 | brnz %r10, cwq_4_44 |
| 9138 | rd %asi, %r12 |
| 9139 | wr %g0, 0x40, %asi |
| 9140 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 9141 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 9142 | cmp %l1, 1 |
| 9143 | bne cwq_4_44 |
| 9144 | set CWQ_BASE, %l6 |
| 9145 | #ifndef SPC |
| 9146 | add %l6, %o3, %l6 |
| 9147 | #endif |
| 9148 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 9149 | best_set_reg(0x206100d0, %l1, %l2) !# Control Word |
| 9150 | sllx %l2, 32, %l2 |
| 9151 | stx %l2, [%l6 + 0x0] |
| 9152 | membar #Sync |
| 9153 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 9154 | sub %l2, 0x40, %l2 |
| 9155 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 9156 | wr %r12, %g0, %asi |
| 9157 | st %g0, [%r23] |
| 9158 | cwq_4_44: |
| 9159 | ta T_CHANGE_NONHPRIV |
| 9160 | .word 0x91414000 ! 66: RDPC rd %pc, %r8 |
| 9161 | mondo_4_45: |
| 9162 | nop |
| 9163 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 9164 | ta T_CHANGE_PRIV |
| 9165 | stxa %r16, [%r0+0x3e8] %asi |
| 9166 | .word 0x9d950014 ! 67: WRPR_WSTATE_R wrpr %r20, %r20, %wstate |
| 9167 | .word 0x93a00172 ! 68: FABSq dis not found |
| 9168 | |
| 9169 | .word 0x9191c004 ! 69: WRPR_PIL_R wrpr %r7, %r4, %pil |
| 9170 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 9171 | #if (defined SPC || defined CMP) |
| 9172 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_4_49)+24, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9173 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_4_49)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9174 | xir_4_49: |
| 9175 | #else |
| 9176 | #if (defined FC) |
| 9177 | !! Generate XIR via RESET_GEN register |
| 9178 | ta T_CHANGE_HPRIV |
| 9179 | rdpr %pstate, %r18 |
| 9180 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 9181 | wrpr %r18, %pstate |
| 9182 | #ifndef XIR_RND_CORES |
| 9183 | ldxa [%g0] 0x63, %o1 |
| 9184 | mov 1, %r18 |
| 9185 | sllx %r18, %o1, %r18 |
| 9186 | #endif |
| 9187 | mov 0x30, %r19 |
| 9188 | setx 0x8900000808, %r16, %r17 |
| 9189 | mov 0x2, %r16 |
| 9190 | xir_4_49: |
| 9191 | stxa %r18, [%r19] 0x41 |
| 9192 | stx %r16, [%r17] |
| 9193 | #endif |
| 9194 | #endif |
| 9195 | .word 0xa980a5e0 ! 71: WR_SET_SOFTINT_I wr %r2, 0x05e0, %set_softint |
| 9196 | #if (defined SPC || defined CMP1) |
| 9197 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_50) + 24, 16, 16)) -> intp(4,0,8,,,,,1) |
| 9198 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_4_50)&0xffffffff) + 16, 16, 16)) -> intp(2,0,12,,,,,1) |
| 9199 | #else |
| 9200 | set 0xc1309bcf, %r28 |
| 9201 | #if (MAX_THREADS == 8) |
| 9202 | and %r28, 0x7ff, %r28 |
| 9203 | #endif |
| 9204 | stxa %r28, [%g0] 0x73 |
| 9205 | #endif |
| 9206 | .word 0xa5a1c9d1 ! 1: FDIVd fdivd %f38, %f48, %f18 |
| 9207 | intvec_4_50: |
| 9208 | .word 0x39400001 ! 72: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 9209 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 9210 | nop |
| 9211 | mov 0x80, %g3 |
| 9212 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 9213 | stxa %g3, [%g3] 0x5f |
| 9214 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 9215 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 9216 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 9217 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 9218 | nop |
| 9219 | ta T_CHANGE_HPRIV |
| 9220 | mov 0x4, %r10 |
| 9221 | set sync_thr_counter6, %r23 |
| 9222 | #ifndef SPC |
| 9223 | ldxa [%g0]0x63, %o1 |
| 9224 | and %o1, 0x38, %o1 |
| 9225 | add %o1, %r23, %r23 |
| 9226 | #endif |
| 9227 | cas [%r23],%g0,%r10 !lock |
| 9228 | brnz %r10, sma_4_52 |
| 9229 | rd %asi, %r12 |
| 9230 | wr %g0, 0x40, %asi |
| 9231 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9232 | set 0x000e1fff, %g1 |
| 9233 | stxa %g1, [%g0 + 0x80] %asi |
| 9234 | wr %r12, %g0, %asi |
| 9235 | st %g0, [%r23] |
| 9236 | sma_4_52: |
| 9237 | ta T_CHANGE_NONHPRIV |
| 9238 | .word 0xe5e7e00b ! 75: CASA_R casa [%r31] %asi, %r11, %r18 |
| 9239 | .word 0x91910005 ! 76: WRPR_PIL_R wrpr %r4, %r5, %pil |
| 9240 | pmu_4_54: |
| 9241 | nop |
| 9242 | setx 0xffffffb4ffffffa5, %g1, %g7 |
| 9243 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 9244 | fpinit_4_55: |
| 9245 | nop |
| 9246 | setx fp_data_quads, %r19, %r20 |
| 9247 | ldd [%r20], %f0 |
| 9248 | ldd [%r20+8], %f4 |
| 9249 | ld [%r20+16], %fsr |
| 9250 | ld [%r20+24], %r19 |
| 9251 | wr %r19, %g0, %gsr |
| 9252 | .word 0x8db00484 ! 78: FCMPLE32 fcmple32 %d0, %d4, %r6 |
| 9253 | jmptr_4_56: |
| 9254 | nop |
| 9255 | best_set_reg(0xe1200000, %r20, %r27) |
| 9256 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 9257 | nop |
| 9258 | mov 0x80, %g3 |
| 9259 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 9260 | stxa %g3, [%g3] 0x57 |
| 9261 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 9262 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 9263 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 9264 | .word 0x95b100f4 ! 81: EDGE16LN edge16ln %r4, %r20, %r10 |
| 9265 | #if (defined SPC || defined CMP1) |
| 9266 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_58) + 40, 16, 16)) -> intp(2,0,26,,,,,1) |
| 9267 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_4_58)&0xffffffff) + 48, 16, 16)) -> intp(0,0,15,,,,,1) |
| 9268 | #else |
| 9269 | set 0x576099fd, %r28 |
| 9270 | #if (MAX_THREADS == 8) |
| 9271 | and %r28, 0x7ff, %r28 |
| 9272 | #endif |
| 9273 | stxa %r28, [%g0] 0x73 |
| 9274 | #endif |
| 9275 | .word 0x9f80250d ! 1: SIR sir 0x050d |
| 9276 | intvec_4_58: |
| 9277 | .word 0x39400001 ! 82: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 9278 | nop |
| 9279 | ta T_CHANGE_HPRIV |
| 9280 | mov 0x4, %r10 |
| 9281 | set sync_thr_counter6, %r23 |
| 9282 | #ifndef SPC |
| 9283 | ldxa [%g0]0x63, %o1 |
| 9284 | and %o1, 0x38, %o1 |
| 9285 | add %o1, %r23, %r23 |
| 9286 | #endif |
| 9287 | cas [%r23],%g0,%r10 !lock |
| 9288 | brnz %r10, sma_4_59 |
| 9289 | rd %asi, %r12 |
| 9290 | wr %g0, 0x40, %asi |
| 9291 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9292 | set 0x00161fff, %g1 |
| 9293 | stxa %g1, [%g0 + 0x80] %asi |
| 9294 | wr %r12, %g0, %asi |
| 9295 | st %g0, [%r23] |
| 9296 | sma_4_59: |
| 9297 | ta T_CHANGE_NONHPRIV |
| 9298 | .word 0xe5e7e010 ! 83: CASA_R casa [%r31] %asi, %r16, %r18 |
| 9299 | fpinit_4_60: |
| 9300 | nop |
| 9301 | setx fp_data_quads, %r19, %r20 |
| 9302 | ldd [%r20], %f0 |
| 9303 | ldd [%r20+8], %f4 |
| 9304 | ld [%r20+16], %fsr |
| 9305 | ld [%r20+24], %r19 |
| 9306 | wr %r19, %g0, %gsr |
| 9307 | .word 0x89a009a4 ! 84: FDIVs fdivs %f0, %f4, %f4 |
| 9308 | .word 0x87802004 ! 85: WRASI_I wr %r0, 0x0004, %asi |
| 9309 | .word 0xc19fdc00 ! 86: LDDFA_R ldda [%r31, %r0], %f0 |
| 9310 | splash_lsu_4_61: |
| 9311 | nop |
| 9312 | ta T_CHANGE_HPRIV |
| 9313 | set 0x8fa3bbf5, %r2 |
| 9314 | mov 0x6, %r1 |
| 9315 | sllx %r1, 32, %r1 |
| 9316 | or %r1, %r2, %r2 |
| 9317 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9318 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9319 | splash_lsu_4_62: |
| 9320 | nop |
| 9321 | ta T_CHANGE_HPRIV |
| 9322 | set 0xcc708111, %r2 |
| 9323 | mov 0x1, %r1 |
| 9324 | sllx %r1, 32, %r1 |
| 9325 | or %r1, %r2, %r2 |
| 9326 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9327 | ta T_CHANGE_NONHPRIV |
| 9328 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9329 | splash_cmpr_4_63: |
| 9330 | mov 0, %r18 |
| 9331 | sllx %r18, 63, %r18 |
| 9332 | rd %tick, %r17 |
| 9333 | add %r17, 0x80, %r17 |
| 9334 | or %r17, %r18, %r17 |
| 9335 | ta T_CHANGE_HPRIV |
| 9336 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 9337 | .word 0xaf800011 ! 89: WR_TICK_CMPR_REG_R wr %r0, %r17, %- |
| 9338 | nop |
| 9339 | mov 0x80, %g3 |
| 9340 | .word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 9341 | stxa %g3, [%g3] 0x5f |
| 9342 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 9343 | splash_tba_4_64: |
| 9344 | nop |
| 9345 | ta T_CHANGE_PRIV |
| 9346 | set 0x120000, %r12 |
| 9347 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 9348 | dvapa_4_65: |
| 9349 | nop |
| 9350 | ta T_CHANGE_HPRIV |
| 9351 | mov 0xc09, %r20 |
| 9352 | mov 0x1d, %r19 |
| 9353 | sllx %r20, 23, %r20 |
| 9354 | or %r19, %r20, %r19 |
| 9355 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 9356 | mov 0x38, %r18 |
| 9357 | stxa %r31, [%r18]0x58 |
| 9358 | ta T_CHANGE_NONHPRIV |
| 9359 | .word 0xe497c02c ! 92: LDUHA_R lduha [%r31, %r12] 0x01, %r18 |
| 9360 | splash_lsu_4_66: |
| 9361 | nop |
| 9362 | ta T_CHANGE_HPRIV |
| 9363 | set 0x31b66568, %r2 |
| 9364 | mov 0x3, %r1 |
| 9365 | sllx %r1, 32, %r1 |
| 9366 | or %r1, %r2, %r2 |
| 9367 | .word 0x2ac84001 ! 1: BRNZ brnz,a,pt %r1,<label_0x84001> |
| 9368 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9369 | ta T_CHANGE_NONHPRIV |
| 9370 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9371 | ibp_4_67: |
| 9372 | nop |
| 9373 | ta T_CHANGE_HPRIV |
| 9374 | mov 8, %r18 |
| 9375 | rd %asi, %r12 |
| 9376 | wr %r0, 0x41, %asi |
| 9377 | set sync_thr_counter4, %r23 |
| 9378 | #ifndef SPC |
| 9379 | ldxa [%g0]0x63, %r8 |
| 9380 | and %r8, 0x38, %r8 ! Core ID |
| 9381 | add %r8, %r23, %r23 |
| 9382 | #else |
| 9383 | mov 0, %r8 |
| 9384 | #endif |
| 9385 | mov 0x4, %r16 |
| 9386 | ibp_startwait4_67: |
| 9387 | cas [%r23],%g0,%r16 !lock |
| 9388 | brz,a %r16, continue_ibp_4_67 |
| 9389 | mov (~0x4&0xf), %r16 |
| 9390 | ld [%r23], %r16 |
| 9391 | ibp_wait4_67: |
| 9392 | brnz %r16, ibp_wait4_67 |
| 9393 | ld [%r23], %r16 |
| 9394 | ba ibp_startwait4_67 |
| 9395 | mov 0x4, %r16 |
| 9396 | continue_ibp_4_67: |
| 9397 | sllx %r16, %r8, %r16 !Mask for my core only |
| 9398 | ldxa [0x58]%asi, %r17 !Running_status |
| 9399 | wait_for_stat_4_67: |
| 9400 | ldxa [0x50]%asi, %r13 !Running_rw |
| 9401 | cmp %r13, %r17 |
| 9402 | bne,a %xcc, wait_for_stat_4_67 |
| 9403 | ldxa [0x58]%asi, %r17 !Running_status |
| 9404 | stxa %r16, [0x68]%asi !Park (W1C) |
| 9405 | ldxa [0x50]%asi, %r14 !Running_rw |
| 9406 | wait_for_ibp_4_67: |
| 9407 | ldxa [0x58]%asi, %r17 !Running_status |
| 9408 | cmp %r14, %r17 |
| 9409 | bne,a %xcc, wait_for_ibp_4_67 |
| 9410 | ldxa [0x50]%asi, %r14 !Running_rw |
| 9411 | ibp_doit4_67: |
| 9412 | best_set_reg(0x00000040fbe4b944,%r19, %r20) |
| 9413 | stxa %r20, [%r18]0x42 |
| 9414 | stxa %r16, [0x60] %asi !Unpark (W1S) |
| 9415 | st %g0, [%r23] !clear lock |
| 9416 | wr %r0, %r12, %asi !restore %asi |
| 9417 | .word 0xe51fc012 ! 94: LDDF_R ldd [%r31, %r18], %f18 |
| 9418 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 9419 | nop |
| 9420 | ta T_CHANGE_HPRIV |
| 9421 | mov 0x4, %r10 |
| 9422 | set sync_thr_counter6, %r23 |
| 9423 | #ifndef SPC |
| 9424 | ldxa [%g0]0x63, %o1 |
| 9425 | and %o1, 0x38, %o1 |
| 9426 | add %o1, %r23, %r23 |
| 9427 | #endif |
| 9428 | cas [%r23],%g0,%r10 !lock |
| 9429 | brnz %r10, sma_4_68 |
| 9430 | rd %asi, %r12 |
| 9431 | wr %g0, 0x40, %asi |
| 9432 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9433 | set 0x00161fff, %g1 |
| 9434 | stxa %g1, [%g0 + 0x80] %asi |
| 9435 | wr %r12, %g0, %asi |
| 9436 | st %g0, [%r23] |
| 9437 | sma_4_68: |
| 9438 | ta T_CHANGE_NONHPRIV |
| 9439 | .word 0xe5e7e011 ! 96: CASA_R casa [%r31] %asi, %r17, %r18 |
| 9440 | #if (defined SPC || defined CMP) |
| 9441 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_4_69)+56, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9442 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_4_69)&0xffffffff) + 32, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9443 | xir_4_69: |
| 9444 | #else |
| 9445 | #if (defined FC) |
| 9446 | !! Generate XIR via RESET_GEN register |
| 9447 | ta T_CHANGE_HPRIV |
| 9448 | rdpr %pstate, %r18 |
| 9449 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 9450 | wrpr %r18, %pstate |
| 9451 | #ifndef XIR_RND_CORES |
| 9452 | ldxa [%g0] 0x63, %o1 |
| 9453 | mov 1, %r18 |
| 9454 | sllx %r18, %o1, %r18 |
| 9455 | #endif |
| 9456 | mov 0x30, %r19 |
| 9457 | setx 0x8900000808, %r16, %r17 |
| 9458 | mov 0x2, %r16 |
| 9459 | xir_4_69: |
| 9460 | stxa %r18, [%r19] 0x41 |
| 9461 | stx %r16, [%r17] |
| 9462 | #endif |
| 9463 | #endif |
| 9464 | .word 0xa984a8ac ! 97: WR_SET_SOFTINT_I wr %r18, 0x08ac, %set_softint |
| 9465 | #if (defined SPC || defined CMP1) |
| 9466 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_70) + 56, 16, 16)) -> intp(5,0,21,,,,,1) |
| 9467 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_4_70)&0xffffffff) + 0, 16, 16)) -> intp(6,0,30,,,,,1) |
| 9468 | #else |
| 9469 | set 0x26a04df1, %r28 |
| 9470 | #if (MAX_THREADS == 8) |
| 9471 | and %r28, 0x7ff, %r28 |
| 9472 | #endif |
| 9473 | stxa %r28, [%g0] 0x73 |
| 9474 | #endif |
| 9475 | intvec_4_70: |
| 9476 | .word 0xc36ca28f ! 98: PREFETCH_I prefetch [%r18 + 0x028f], #one_read |
| 9477 | fpinit_4_71: |
| 9478 | nop |
| 9479 | setx fp_data_quads, %r19, %r20 |
| 9480 | ldd [%r20], %f0 |
| 9481 | ldd [%r20+8], %f4 |
| 9482 | ld [%r20+16], %fsr |
| 9483 | ld [%r20+24], %r19 |
| 9484 | wr %r19, %g0, %gsr |
| 9485 | .word 0x87a80a44 ! 99: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 9486 | splash_lsu_4_72: |
| 9487 | nop |
| 9488 | ta T_CHANGE_HPRIV |
| 9489 | set 0x5c75e76c, %r2 |
| 9490 | mov 0x5, %r1 |
| 9491 | sllx %r1, 32, %r1 |
| 9492 | or %r1, %r2, %r2 |
| 9493 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9494 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9495 | .word 0x93b0c0eb ! 101: EDGE16LN edge16ln %r3, %r11, %r9 |
| 9496 | nop |
| 9497 | ta T_CHANGE_HPRIV |
| 9498 | mov 0x4, %r10 |
| 9499 | set sync_thr_counter6, %r23 |
| 9500 | #ifndef SPC |
| 9501 | ldxa [%g0]0x63, %o1 |
| 9502 | and %o1, 0x38, %o1 |
| 9503 | add %o1, %r23, %r23 |
| 9504 | #endif |
| 9505 | cas [%r23],%g0,%r10 !lock |
| 9506 | brnz %r10, sma_4_74 |
| 9507 | rd %asi, %r12 |
| 9508 | wr %g0, 0x40, %asi |
| 9509 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9510 | set 0x001a1fff, %g1 |
| 9511 | stxa %g1, [%g0 + 0x80] %asi |
| 9512 | wr %r12, %g0, %asi |
| 9513 | st %g0, [%r23] |
| 9514 | sma_4_74: |
| 9515 | ta T_CHANGE_NONHPRIV |
| 9516 | .word 0xd7e7e010 ! 102: CASA_R casa [%r31] %asi, %r16, %r11 |
| 9517 | nop |
| 9518 | mov 0x80, %g3 |
| 9519 | .word 0x22c98001 ! 1: BRZ brz,a,pt %r6,<label_0x98001> |
| 9520 | stxa %g3, [%g3] 0x57 |
| 9521 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 9522 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 9523 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 9524 | .word 0xe19fd960 ! 105: LDDFA_R ldda [%r31, %r0], %f16 |
| 9525 | splash_lsu_4_77: |
| 9526 | nop |
| 9527 | ta T_CHANGE_HPRIV |
| 9528 | set 0xb60e30ae, %r2 |
| 9529 | mov 0x4, %r1 |
| 9530 | sllx %r1, 32, %r1 |
| 9531 | or %r1, %r2, %r2 |
| 9532 | .word 0x35400001 ! 1: FBPUE fbue,a,pn %fcc0, <label_0x1> |
| 9533 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9534 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9535 | .word 0xc1bfde00 ! 107: STDFA_R stda %f0, [%r0, %r31] |
| 9536 | .word 0x91918009 ! 108: WRPR_PIL_R wrpr %r6, %r9, %pil |
| 9537 | splash_lsu_4_79: |
| 9538 | nop |
| 9539 | ta T_CHANGE_HPRIV |
| 9540 | set 0x25aad3df, %r2 |
| 9541 | mov 0x7, %r1 |
| 9542 | sllx %r1, 32, %r1 |
| 9543 | or %r1, %r2, %r2 |
| 9544 | .word 0x24c84001 ! 1: BRLEZ brlez,a,pt %r1,<label_0x84001> |
| 9545 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9546 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9547 | .word 0xe1bfd960 ! 110: STDFA_R stda %f16, [%r0, %r31] |
| 9548 | fblg skip_4_80 |
| 9549 | fbule skip_4_80 |
| 9550 | .align 128 |
| 9551 | skip_4_80: |
| 9552 | .word 0x87ac4a49 ! 111: FCMPd fcmpd %fcc<n>, %f48, %f40 |
| 9553 | .word 0xc1bfde00 ! 112: STDFA_R stda %f0, [%r0, %r31] |
| 9554 | rd %tick, %r28 |
| 9555 | #if (MAX_THREADS == 8) |
| 9556 | sethi %hi(0x33800), %r27 |
| 9557 | #else |
| 9558 | sethi %hi(0x30000), %r27 |
| 9559 | #endif |
| 9560 | andn %r28, %r27, %r28 |
| 9561 | ta T_CHANGE_HPRIV |
| 9562 | stxa %r28, [%g0] 0x73 |
| 9563 | intvec_4_81: |
| 9564 | .word 0x39400001 ! 113: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 9565 | .word 0xc1bfe120 ! 114: STDFA_I stda %f0, [0x0120, %r31] |
| 9566 | nop |
| 9567 | mov 0x80, %g3 |
| 9568 | .word 0x22800001 ! 1: BE be,a <label_0x1> |
| 9569 | stxa %g3, [%g3] 0x5f |
| 9570 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 9571 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 9572 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 9573 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 9574 | jmptr_4_82: |
| 9575 | nop |
| 9576 | best_set_reg(0xe1200000, %r20, %r27) |
| 9577 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 9578 | splash_tba_4_83: |
| 9579 | nop |
| 9580 | ta T_CHANGE_PRIV |
| 9581 | setx 0x0000000400380000, %r11, %r12 |
| 9582 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 9583 | .word 0x9191c001 ! 118: WRPR_PIL_R wrpr %r7, %r1, %pil |
| 9584 | #if (defined SPC || defined CMP) |
| 9585 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_4_85)+24, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9586 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_4_85)&0xffffffff) + 0, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9587 | xir_4_85: |
| 9588 | #else |
| 9589 | #if (defined FC) |
| 9590 | !! Generate XIR via RESET_GEN register |
| 9591 | ta T_CHANGE_HPRIV |
| 9592 | rdpr %pstate, %r18 |
| 9593 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 9594 | wrpr %r18, %pstate |
| 9595 | #ifndef XIR_RND_CORES |
| 9596 | ldxa [%g0] 0x63, %o1 |
| 9597 | mov 1, %r18 |
| 9598 | sllx %r18, %o1, %r18 |
| 9599 | #endif |
| 9600 | mov 0x30, %r19 |
| 9601 | setx 0x8900000808, %r16, %r17 |
| 9602 | mov 0x2, %r16 |
| 9603 | xir_4_85: |
| 9604 | stxa %r18, [%r19] 0x41 |
| 9605 | stx %r16, [%r17] |
| 9606 | #endif |
| 9607 | #endif |
| 9608 | .word 0xa9817564 ! 119: WR_SET_SOFTINT_I wr %r5, 0x1564, %set_softint |
| 9609 | cwp_4_86: |
| 9610 | set user_data_start, %o7 |
| 9611 | .word 0x93902006 ! 120: WRPR_CWP_I wrpr %r0, 0x0006, %cwp |
| 9612 | nop |
| 9613 | mov 0x80, %g3 |
| 9614 | stxa %r8, [%r0] ASI_LSU_CONTROL |
| 9615 | stxa %g3, [%g3] 0x57 |
| 9616 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 9617 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 9618 | nop |
| 9619 | ta T_CHANGE_HPRIV ! macro |
| 9620 | donret_4_87: |
| 9621 | rd %pc, %r12 |
| 9622 | mov HIGHVA_HIGHNUM, %r10 |
| 9623 | sllx %r10, 32, %r10 |
| 9624 | or %r12, %r10, %r12 |
| 9625 | add %r12, (donretarg_4_87-donret_4_87), %r12 |
| 9626 | add %r12, 0x4, %r11 ! seq tnpc |
| 9627 | andn %r11, %r10, %r11 ! low VA tnpc |
| 9628 | wrpr %g0, 0x1, %tl |
| 9629 | wrpr %g0, %r12, %tpc |
| 9630 | wrpr %g0, %r11, %tnpc |
| 9631 | set (0x00378100 | (22 << 24)), %r13 |
| 9632 | and %r12, 0xfff, %r14 |
| 9633 | sllx %r14, 32, %r14 |
| 9634 | or %r13, %r14, %r20 |
| 9635 | wrpr %r20, %g0, %tstate |
| 9636 | wrhpr %g0, 0x40d, %htstate |
| 9637 | ta T_CHANGE_NONPRIV ! rand=0 (4) |
| 9638 | ldx [%r11+%r0], %g1 |
| 9639 | done |
| 9640 | donretarg_4_87: |
| 9641 | .word 0xe66fe08f ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x008f] |
| 9642 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 9643 | .word 0xa545c000 ! 124: RD_TICK_CMPR_REG rd %-, %r18 |
| 9644 | .word 0xc19fc3e0 ! 125: LDDFA_R ldda [%r31, %r0], %f0 |
| 9645 | nop |
| 9646 | ta T_CHANGE_HPRIV |
| 9647 | mov 0x4+1, %r10 |
| 9648 | set sync_thr_counter5, %r23 |
| 9649 | #ifndef SPC |
| 9650 | ldxa [%g0]0x63, %o1 |
| 9651 | and %o1, 0x38, %o1 |
| 9652 | add %o1, %r23, %r23 |
| 9653 | sllx %o1, 5, %o3 !(CID*256) |
| 9654 | #endif |
| 9655 | cas [%r23],%g0,%r10 !lock |
| 9656 | brnz %r10, cwq_4_89 |
| 9657 | rd %asi, %r12 |
| 9658 | wr %g0, 0x40, %asi |
| 9659 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 9660 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 9661 | cmp %l1, 1 |
| 9662 | bne cwq_4_89 |
| 9663 | set CWQ_BASE, %l6 |
| 9664 | #ifndef SPC |
| 9665 | add %l6, %o3, %l6 |
| 9666 | #endif |
| 9667 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 9668 | best_set_reg(0x20610070, %l1, %l2) !# Control Word |
| 9669 | sllx %l2, 32, %l2 |
| 9670 | stx %l2, [%l6 + 0x0] |
| 9671 | membar #Sync |
| 9672 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 9673 | sub %l2, 0x40, %l2 |
| 9674 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 9675 | wr %r12, %g0, %asi |
| 9676 | st %g0, [%r23] |
| 9677 | cwq_4_89: |
| 9678 | ta T_CHANGE_NONHPRIV |
| 9679 | .word 0xa3414000 ! 126: RDPC rd %pc, %r17 |
| 9680 | .word 0xa5a0016b ! 127: FABSq dis not found |
| 9681 | |
| 9682 | #if (defined SPC || defined CMP) |
| 9683 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_4_91)+48, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9684 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_4_91)&0xffffffff) + 8, 16, 16)) -> intp(mask2tid(0x4),1,3,,,,,1) |
| 9685 | xir_4_91: |
| 9686 | #else |
| 9687 | #if (defined FC) |
| 9688 | !! Generate XIR via RESET_GEN register |
| 9689 | ta T_CHANGE_HPRIV |
| 9690 | rdpr %pstate, %r18 |
| 9691 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 9692 | wrpr %r18, %pstate |
| 9693 | #ifndef XIR_RND_CORES |
| 9694 | ldxa [%g0] 0x63, %o1 |
| 9695 | mov 1, %r18 |
| 9696 | sllx %r18, %o1, %r18 |
| 9697 | #endif |
| 9698 | mov 0x30, %r19 |
| 9699 | setx 0x8900000808, %r16, %r17 |
| 9700 | mov 0x2, %r16 |
| 9701 | xir_4_91: |
| 9702 | stxa %r18, [%r19] 0x41 |
| 9703 | stx %r16, [%r17] |
| 9704 | #endif |
| 9705 | #endif |
| 9706 | .word 0xa984b933 ! 128: WR_SET_SOFTINT_I wr %r18, 0x1933, %set_softint |
| 9707 | memptr_4_92: |
| 9708 | set 0x60740000, %r31 |
| 9709 | .word 0x8581b570 ! 129: WRCCR_I wr %r6, 0x1570, %ccr |
| 9710 | rd %tick, %r28 |
| 9711 | #if (MAX_THREADS == 8) |
| 9712 | sethi %hi(0x33800), %r27 |
| 9713 | #else |
| 9714 | sethi %hi(0x30000), %r27 |
| 9715 | #endif |
| 9716 | andn %r28, %r27, %r28 |
| 9717 | ta T_CHANGE_HPRIV |
| 9718 | stxa %r28, [%g0] 0x73 |
| 9719 | intvec_4_93: |
| 9720 | .word 0xc3693d99 ! 130: PREFETCH_I prefetch [%r4 + 0xfffffd99], #one_read |
| 9721 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 9722 | memptr_4_95: |
| 9723 | set 0x60140000, %r31 |
| 9724 | .word 0x858171f1 ! 132: WRCCR_I wr %r5, 0x11f1, %ccr |
| 9725 | splash_hpstate_4_96: |
| 9726 | .word 0x34800001 ! 1: BG bg,a <label_0x1> |
| 9727 | .word 0x8198259f ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x059f, %hpstate |
| 9728 | jmptr_4_97: |
| 9729 | nop |
| 9730 | best_set_reg(0xe1200000, %r20, %r27) |
| 9731 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 9732 | bne skip_4_98 |
| 9733 | stxa %r13, [%r0] ASI_LSU_CONTROL |
| 9734 | .word 0x87ad0a53 ! 1: FCMPd fcmpd %fcc<n>, %f20, %f50 |
| 9735 | stxa %r17, [%r0] ASI_LSU_CONTROL |
| 9736 | .align 128 |
| 9737 | skip_4_98: |
| 9738 | .word 0xc36fe024 ! 135: PREFETCH_I prefetch [%r31 + 0x0024], #one_read |
| 9739 | .word 0x8d903683 ! 136: WRPR_PSTATE_I wrpr %r0, 0x1683, %pstate |
| 9740 | .word 0xa1a00163 ! 137: FABSq dis not found |
| 9741 | |
| 9742 | nop |
| 9743 | ta T_CHANGE_HPRIV |
| 9744 | mov 0x4, %r10 |
| 9745 | set sync_thr_counter6, %r23 |
| 9746 | #ifndef SPC |
| 9747 | ldxa [%g0]0x63, %o1 |
| 9748 | and %o1, 0x38, %o1 |
| 9749 | add %o1, %r23, %r23 |
| 9750 | #endif |
| 9751 | cas [%r23],%g0,%r10 !lock |
| 9752 | brnz %r10, sma_4_101 |
| 9753 | rd %asi, %r12 |
| 9754 | wr %g0, 0x40, %asi |
| 9755 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9756 | set 0x000e1fff, %g1 |
| 9757 | stxa %g1, [%g0 + 0x80] %asi |
| 9758 | wr %r12, %g0, %asi |
| 9759 | st %g0, [%r23] |
| 9760 | sma_4_101: |
| 9761 | ta T_CHANGE_NONHPRIV |
| 9762 | .word 0xe1e7e010 ! 138: CASA_R casa [%r31] %asi, %r16, %r16 |
| 9763 | .word 0x91b1c0e8 ! 139: EDGE16LN edge16ln %r7, %r8, %r8 |
| 9764 | splash_lsu_4_103: |
| 9765 | nop |
| 9766 | ta T_CHANGE_HPRIV |
| 9767 | set 0xc11d10b1, %r2 |
| 9768 | mov 0x2, %r1 |
| 9769 | sllx %r1, 32, %r1 |
| 9770 | or %r1, %r2, %r2 |
| 9771 | .word 0x3d400001 ! 1: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9772 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9773 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9774 | .word 0x9768c013 ! 141: SDIVX_R sdivx %r3, %r19, %r11 |
| 9775 | .word 0xc19fe0e0 ! 142: LDDFA_I ldda [%r31, 0x00e0], %f0 |
| 9776 | .word 0x9194c006 ! 143: WRPR_PIL_R wrpr %r19, %r6, %pil |
| 9777 | splash_hpstate_4_105: |
| 9778 | ta T_CHANGE_NONHPRIV |
| 9779 | .word 0x81982ec7 ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x0ec7, %hpstate |
| 9780 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 9781 | nop |
| 9782 | ta T_CHANGE_HPRIV |
| 9783 | mov 0x4, %r10 |
| 9784 | set sync_thr_counter6, %r23 |
| 9785 | #ifndef SPC |
| 9786 | ldxa [%g0]0x63, %o1 |
| 9787 | and %o1, 0x38, %o1 |
| 9788 | add %o1, %r23, %r23 |
| 9789 | #endif |
| 9790 | cas [%r23],%g0,%r10 !lock |
| 9791 | brnz %r10, sma_4_107 |
| 9792 | rd %asi, %r12 |
| 9793 | wr %g0, 0x40, %asi |
| 9794 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9795 | set 0x000e1fff, %g1 |
| 9796 | stxa %g1, [%g0 + 0x80] %asi |
| 9797 | wr %r12, %g0, %asi |
| 9798 | st %g0, [%r23] |
| 9799 | sma_4_107: |
| 9800 | ta T_CHANGE_NONHPRIV |
| 9801 | .word 0xd1e7e00d ! 146: CASA_R casa [%r31] %asi, %r13, %r8 |
| 9802 | fpinit_4_108: |
| 9803 | nop |
| 9804 | setx fp_data_quads, %r19, %r20 |
| 9805 | ldd [%r20], %f0 |
| 9806 | ldd [%r20+8], %f4 |
| 9807 | ld [%r20+16], %fsr |
| 9808 | ld [%r20+24], %r19 |
| 9809 | wr %r19, %g0, %gsr |
| 9810 | .word 0x8da009c4 ! 147: FDIVd fdivd %f0, %f4, %f6 |
| 9811 | intveclr_4_109: |
| 9812 | nop |
| 9813 | ta T_CHANGE_HPRIV |
| 9814 | setx 0x79541440b0840665, %r1, %r28 |
| 9815 | stxa %r28, [%g0] 0x72 |
| 9816 | ta T_CHANGE_NONHPRIV |
| 9817 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 9818 | brcommon3_4_110: |
| 9819 | nop |
| 9820 | setx common_target, %r12, %r27 |
| 9821 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 9822 | ba,a .+12 |
| 9823 | .word 0xd06fe0a0 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x00a0] |
| 9824 | ba,a .+8 |
| 9825 | jmpl %r27+0, %r27 |
| 9826 | .word 0xd11fe060 ! 149: LDDF_I ldd [%r31, 0x0060], %f8 |
| 9827 | .word 0x2cc8c001 ! 1: BRGZ brgz,a,pt %r3,<label_0x8c001> |
| 9828 | .word 0x8d902d27 ! 150: WRPR_PSTATE_I wrpr %r0, 0x0d27, %pstate |
| 9829 | nop |
| 9830 | nop |
| 9831 | ta T_CHANGE_PRIV |
| 9832 | wrpr %g0, %g0, %gl |
| 9833 | nop |
| 9834 | nop |
| 9835 | .text |
| 9836 | setx join_lbl_0_0, %g1, %g2 |
| 9837 | jmp %g2 |
| 9838 | nop |
| 9839 | fork_lbl_0_2: |
| 9840 | ta T_CHANGE_NONHPRIV |
| 9841 | .word 0xe877e070 ! 1: STX_I stx %r20, [%r31 + 0x0070] |
| 9842 | br_longdelay4_2_0: |
| 9843 | nop |
| 9844 | not %g0, %r27 |
| 9845 | jmpl %r27+0, %r27 |
| 9846 | .word 0x9d902003 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0003, %wstate |
| 9847 | .word 0xe93fe0e0 ! 3: STDF_I std %f20, [0x00e0, %r31] |
| 9848 | fpinit_2_1: |
| 9849 | nop |
| 9850 | setx fp_data_quads, %r19, %r20 |
| 9851 | ldd [%r20], %f0 |
| 9852 | ldd [%r20+8], %f4 |
| 9853 | ld [%r20+16], %fsr |
| 9854 | ld [%r20+24], %r19 |
| 9855 | wr %r19, %g0, %gsr |
| 9856 | .word 0x8da009a4 ! 4: FDIVs fdivs %f0, %f4, %f6 |
| 9857 | splash_lsu_2_2: |
| 9858 | nop |
| 9859 | ta T_CHANGE_HPRIV |
| 9860 | set 0xfef774a6, %r2 |
| 9861 | mov 0x5, %r1 |
| 9862 | sllx %r1, 32, %r1 |
| 9863 | or %r1, %r2, %r2 |
| 9864 | .word 0x3a800001 ! 1: BCC bcc,a <label_0x1> |
| 9865 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9866 | ta T_CHANGE_NONHPRIV |
| 9867 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9868 | splash_hpstate_2_3: |
| 9869 | .word 0x81983499 ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x1499, %hpstate |
| 9870 | memptr_2_4: |
| 9871 | set 0x60140000, %r31 |
| 9872 | .word 0x858129ec ! 7: WRCCR_I wr %r4, 0x09ec, %ccr |
| 9873 | nop |
| 9874 | mov 0x80, %g3 |
| 9875 | .word 0x2ec90001 ! 1: BRGEZ brgez,a,pt %r4,<label_0x90001> |
| 9876 | stxa %g3, [%g3] 0x57 |
| 9877 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 9878 | .word 0xc19fe180 ! 9: LDDFA_I ldda [%r31, 0x0180], %f0 |
| 9879 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 9880 | .word 0xe1bfdc00 ! 11: STDFA_R stda %f16, [%r0, %r31] |
| 9881 | dvapa_2_6: |
| 9882 | nop |
| 9883 | ta T_CHANGE_HPRIV |
| 9884 | mov 0xf67, %r20 |
| 9885 | mov 0x0, %r19 |
| 9886 | sllx %r20, 23, %r20 |
| 9887 | or %r19, %r20, %r19 |
| 9888 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 9889 | mov 0x38, %r18 |
| 9890 | stxa %r31, [%r18]0x58 |
| 9891 | ta T_CHANGE_NONHPRIV |
| 9892 | .word 0xe1bfe120 ! 12: STDFA_I stda %f16, [0x0120, %r31] |
| 9893 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 9894 | jmptr_2_7: |
| 9895 | nop |
| 9896 | best_set_reg(0xe1a00000, %r20, %r27) |
| 9897 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 9898 | pmu_2_8: |
| 9899 | nop |
| 9900 | ta T_CHANGE_PRIV |
| 9901 | setx 0xffffffb2ffffffa1, %g1, %g7 |
| 9902 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 9903 | jmptr_2_9: |
| 9904 | nop |
| 9905 | best_set_reg(0xe1a00000, %r20, %r27) |
| 9906 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 9907 | nop |
| 9908 | ta T_CHANGE_HPRIV |
| 9909 | mov 0x2, %r10 |
| 9910 | set sync_thr_counter6, %r23 |
| 9911 | #ifndef SPC |
| 9912 | ldxa [%g0]0x63, %o1 |
| 9913 | and %o1, 0x38, %o1 |
| 9914 | add %o1, %r23, %r23 |
| 9915 | #endif |
| 9916 | cas [%r23],%g0,%r10 !lock |
| 9917 | brnz %r10, sma_2_10 |
| 9918 | rd %asi, %r12 |
| 9919 | wr %g0, 0x40, %asi |
| 9920 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 9921 | set 0x001a1fff, %g1 |
| 9922 | stxa %g1, [%g0 + 0x80] %asi |
| 9923 | wr %r12, %g0, %asi |
| 9924 | st %g0, [%r23] |
| 9925 | sma_2_10: |
| 9926 | ta T_CHANGE_NONHPRIV |
| 9927 | .word 0xe9e7e00b ! 17: CASA_R casa [%r31] %asi, %r11, %r20 |
| 9928 | .word 0x87802014 ! 18: WRASI_I wr %r0, 0x0014, %asi |
| 9929 | splash_lsu_2_11: |
| 9930 | nop |
| 9931 | ta T_CHANGE_HPRIV |
| 9932 | set 0x948ea2c5, %r2 |
| 9933 | mov 0x1, %r1 |
| 9934 | sllx %r1, 32, %r1 |
| 9935 | or %r1, %r2, %r2 |
| 9936 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9937 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9938 | .word 0xe93fe0a7 ! 20: STDF_I std %f20, [0x00a7, %r31] |
| 9939 | brcommon1_2_12: |
| 9940 | nop |
| 9941 | setx common_target, %r12, %r27 |
| 9942 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 9943 | ba,a .+12 |
| 9944 | .word 0xa9b7c7d2 ! 1: PDIST pdistn %d62, %d18, %d20 |
| 9945 | ba,a .+8 |
| 9946 | jmpl %r27+0, %r27 |
| 9947 | .word 0xc3e98027 ! 21: PREFETCHA_R prefetcha [%r6, %r7] 0x01, #one_read |
| 9948 | splash_lsu_2_13: |
| 9949 | nop |
| 9950 | ta T_CHANGE_HPRIV |
| 9951 | set 0x52a56155, %r2 |
| 9952 | mov 0x5, %r1 |
| 9953 | sllx %r1, 32, %r1 |
| 9954 | or %r1, %r2, %r2 |
| 9955 | .word 0x22800001 ! 1: BE be,a <label_0x1> |
| 9956 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 9957 | ta T_CHANGE_NONHPRIV |
| 9958 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 9959 | .word 0xc19fdb60 ! 23: LDDFA_R ldda [%r31, %r0], %f0 |
| 9960 | .word 0xc1bfc2c0 ! 24: STDFA_R stda %f0, [%r0, %r31] |
| 9961 | pmu_2_14: |
| 9962 | nop |
| 9963 | ta T_CHANGE_PRIV |
| 9964 | setx 0xffffffb3ffffffa2, %g1, %g7 |
| 9965 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 9966 | rd %tick, %r28 |
| 9967 | #if (MAX_THREADS == 8) |
| 9968 | sethi %hi(0x33800), %r27 |
| 9969 | #else |
| 9970 | sethi %hi(0x30000), %r27 |
| 9971 | #endif |
| 9972 | andn %r28, %r27, %r28 |
| 9973 | ta T_CHANGE_HPRIV |
| 9974 | stxa %r28, [%g0] 0x73 |
| 9975 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 9976 | intvec_2_15: |
| 9977 | .word 0xc36c20c9 ! 26: PREFETCH_I prefetch [%r16 + 0x00c9], #one_read |
| 9978 | .word 0x91934008 ! 27: WRPR_PIL_R wrpr %r13, %r8, %pil |
| 9979 | nop |
| 9980 | mov 0x80, %g3 |
| 9981 | stxa %r20, [%r0] ASI_LSU_CONTROL |
| 9982 | stxa %g3, [%g3] 0x57 |
| 9983 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 9984 | #if (defined SPC || defined CMP) |
| 9985 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_2_17)+56, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 9986 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_2_17)&0xffffffff) + 32, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 9987 | xir_2_17: |
| 9988 | #else |
| 9989 | #if (defined FC) |
| 9990 | !! Generate XIR via RESET_GEN register |
| 9991 | ta T_CHANGE_HPRIV |
| 9992 | rdpr %pstate, %r18 |
| 9993 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 9994 | wrpr %r18, %pstate |
| 9995 | #ifndef XIR_RND_CORES |
| 9996 | ldxa [%g0] 0x63, %o1 |
| 9997 | mov 1, %r18 |
| 9998 | sllx %r18, %o1, %r18 |
| 9999 | #endif |
| 10000 | mov 0x30, %r19 |
| 10001 | setx 0x8900000808, %r16, %r17 |
| 10002 | mov 0x2, %r16 |
| 10003 | xir_2_17: |
| 10004 | stxa %r18, [%r19] 0x41 |
| 10005 | stx %r16, [%r17] |
| 10006 | #endif |
| 10007 | #endif |
| 10008 | .word 0xa980bf53 ! 29: WR_SET_SOFTINT_I wr %r2, 0x1f53, %set_softint |
| 10009 | .word 0x99a00168 ! 30: FABSq dis not found |
| 10010 | |
| 10011 | .word 0xa7a0016b ! 31: FABSq dis not found |
| 10012 | |
| 10013 | tagged_2_20: |
| 10014 | tsubcctv %r18, 0x176d, %r20 |
| 10015 | .word 0xd807e1ec ! 32: LDUW_I lduw [%r31 + 0x01ec], %r12 |
| 10016 | mondo_2_21: |
| 10017 | nop |
| 10018 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 10019 | stxa %r5, [%r0+0x3e8] %asi |
| 10020 | .word 0x9d91800b ! 33: WRPR_WSTATE_R wrpr %r6, %r11, %wstate |
| 10021 | .word 0xb1804012 ! 34: WR_STICK_REG_R wr %r1, %r18, %- |
| 10022 | nop |
| 10023 | ta T_CHANGE_HPRIV |
| 10024 | mov 0x2, %r10 |
| 10025 | set sync_thr_counter6, %r23 |
| 10026 | #ifndef SPC |
| 10027 | ldxa [%g0]0x63, %o1 |
| 10028 | and %o1, 0x38, %o1 |
| 10029 | add %o1, %r23, %r23 |
| 10030 | #endif |
| 10031 | cas [%r23],%g0,%r10 !lock |
| 10032 | brnz %r10, sma_2_22 |
| 10033 | rd %asi, %r12 |
| 10034 | wr %g0, 0x40, %asi |
| 10035 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10036 | set 0x00061fff, %g1 |
| 10037 | stxa %g1, [%g0 + 0x80] %asi |
| 10038 | wr %r12, %g0, %asi |
| 10039 | st %g0, [%r23] |
| 10040 | sma_2_22: |
| 10041 | ta T_CHANGE_NONHPRIV |
| 10042 | .word 0xd9e7e010 ! 35: CASA_R casa [%r31] %asi, %r16, %r12 |
| 10043 | nop |
| 10044 | ta T_CHANGE_HPRIV |
| 10045 | mov 0x2, %r10 |
| 10046 | set sync_thr_counter6, %r23 |
| 10047 | #ifndef SPC |
| 10048 | ldxa [%g0]0x63, %o1 |
| 10049 | and %o1, 0x38, %o1 |
| 10050 | add %o1, %r23, %r23 |
| 10051 | #endif |
| 10052 | cas [%r23],%g0,%r10 !lock |
| 10053 | brnz %r10, sma_2_23 |
| 10054 | rd %asi, %r12 |
| 10055 | wr %g0, 0x40, %asi |
| 10056 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10057 | set 0x00061fff, %g1 |
| 10058 | stxa %g1, [%g0 + 0x80] %asi |
| 10059 | wr %r12, %g0, %asi |
| 10060 | st %g0, [%r23] |
| 10061 | sma_2_23: |
| 10062 | ta T_CHANGE_NONHPRIV |
| 10063 | .word 0xd9e7e012 ! 36: CASA_R casa [%r31] %asi, %r18, %r12 |
| 10064 | splash_tba_2_24: |
| 10065 | nop |
| 10066 | ta T_CHANGE_PRIV |
| 10067 | set 0x120000, %r12 |
| 10068 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 10069 | splash_lsu_2_25: |
| 10070 | nop |
| 10071 | ta T_CHANGE_HPRIV |
| 10072 | set 0x439ff524, %r2 |
| 10073 | mov 0x3, %r1 |
| 10074 | sllx %r1, 32, %r1 |
| 10075 | or %r1, %r2, %r2 |
| 10076 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10077 | ta T_CHANGE_NONHPRIV |
| 10078 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10079 | #if (defined SPC || defined CMP1) |
| 10080 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_26) + 48, 16, 16)) -> intp(2,0,4,,,,,1) |
| 10081 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_26)&0xffffffff) + 0, 16, 16)) -> intp(3,0,5,,,,,1) |
| 10082 | #else |
| 10083 | set 0x63109a34, %r28 |
| 10084 | #if (MAX_THREADS == 8) |
| 10085 | and %r28, 0x7ff, %r28 |
| 10086 | #endif |
| 10087 | stxa %r28, [%g0] 0x73 |
| 10088 | #endif |
| 10089 | .word 0xc36d38ad ! 1: PREFETCH_I prefetch [%r20 + 0xfffff8ad], #one_read |
| 10090 | intvec_2_26: |
| 10091 | .word 0x97a189d3 ! 39: FDIVd fdivd %f6, %f50, %f42 |
| 10092 | .word 0xd727e192 ! 40: STF_I st %f11, [0x0192, %r31] |
| 10093 | .word 0xd627e1f8 ! 41: STW_I stw %r11, [%r31 + 0x01f8] |
| 10094 | jmptr_2_27: |
| 10095 | nop |
| 10096 | best_set_reg(0xe1a00000, %r20, %r27) |
| 10097 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 10098 | splash_tba_2_28: |
| 10099 | nop |
| 10100 | ta T_CHANGE_PRIV |
| 10101 | set 0x120000, %r12 |
| 10102 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 10103 | set 0x25f0, %l3 |
| 10104 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 10105 | .word 0x97b147d4 ! 44: PDIST pdistn %d36, %d20, %d42 |
| 10106 | pmu_2_29: |
| 10107 | nop |
| 10108 | setx 0xffffffb1ffffffa7, %g1, %g7 |
| 10109 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 10110 | brcommon3_2_30: |
| 10111 | nop |
| 10112 | setx common_target, %r12, %r27 |
| 10113 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 10114 | ba,a .+12 |
| 10115 | .word 0xe3e7c030 ! 1: CASA_I casa [%r31] 0x 1, %r16, %r17 |
| 10116 | ba,a .+8 |
| 10117 | jmpl %r27+0, %r27 |
| 10118 | .word 0xe31fc010 ! 46: LDDF_R ldd [%r31, %r16], %f17 |
| 10119 | brcommon3_2_31: |
| 10120 | nop |
| 10121 | setx common_target, %r12, %r27 |
| 10122 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 10123 | ba,a .+12 |
| 10124 | .word 0xe26fe150 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x0150] |
| 10125 | ba,a .+8 |
| 10126 | jmpl %r27+0, %r27 |
| 10127 | stxa %r14, [%r0] ASI_LSU_CONTROL |
| 10128 | .word 0xa9aac82c ! 47: FMOVGE fmovs %fcc1, %f12, %f20 |
| 10129 | brcommon3_2_32: |
| 10130 | nop |
| 10131 | setx common_target, %r12, %r27 |
| 10132 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 10133 | ba,a .+12 |
| 10134 | .word 0xd737e050 ! 1: STQF_I - %f11, [0x0050, %r31] |
| 10135 | ba,a .+8 |
| 10136 | jmpl %r27+0, %r27 |
| 10137 | .word 0xd7e7e012 ! 48: CASA_R casa [%r31] %asi, %r18, %r11 |
| 10138 | nop |
| 10139 | mov 0x80, %g3 |
| 10140 | .word 0x33400001 ! 1: FBPE fbe,a,pn %fcc0, <label_0x1> |
| 10141 | stxa %g3, [%g3] 0x57 |
| 10142 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 10143 | nop |
| 10144 | ta T_CHANGE_HPRIV ! macro |
| 10145 | donret_2_33: |
| 10146 | rd %pc, %r12 |
| 10147 | mov HIGHVA_HIGHNUM, %r10 |
| 10148 | sllx %r10, 32, %r10 |
| 10149 | or %r12, %r10, %r12 |
| 10150 | add %r12, (donretarg_2_33-donret_2_33), %r12 |
| 10151 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 10152 | andn %r11, %r10, %r11 ! low VA tnpc |
| 10153 | wrpr %g0, 0x1, %tl |
| 10154 | wrpr %g0, %r12, %tpc |
| 10155 | wrpr %g0, %r11, %tnpc |
| 10156 | set (0x00134900 | (0x4f << 24)), %r13 |
| 10157 | and %r12, 0xfff, %r14 |
| 10158 | sllx %r14, 32, %r14 |
| 10159 | or %r13, %r14, %r20 |
| 10160 | wrpr %r20, %g0, %tstate |
| 10161 | wrhpr %g0, 0x1b93, %htstate |
| 10162 | ta T_CHANGE_NONHPRIV ! rand=1 (2) |
| 10163 | ldx [%r11+%r0], %g1 |
| 10164 | done |
| 10165 | donretarg_2_33: |
| 10166 | .word 0x2eca8001 ! 50: BRGEZ brgez,a,pt %r10,<label_0xa8001> |
| 10167 | #if (defined SPC || defined CMP1) |
| 10168 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_34) + 32, 16, 16)) -> intp(5,0,4,,,,,1) |
| 10169 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_34)&0xffffffff) + 40, 16, 16)) -> intp(4,0,21,,,,,1) |
| 10170 | #else |
| 10171 | set 0x15c0c6cb, %r28 |
| 10172 | #if (MAX_THREADS == 8) |
| 10173 | and %r28, 0x7ff, %r28 |
| 10174 | #endif |
| 10175 | stxa %r28, [%g0] 0x73 |
| 10176 | #endif |
| 10177 | intvec_2_34: |
| 10178 | .word 0x9f802760 ! 51: SIR sir 0x0760 |
| 10179 | .word 0xe927e0f0 ! 52: STF_I st %f20, [0x00f0, %r31] |
| 10180 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 10181 | splash_tba_2_35: |
| 10182 | nop |
| 10183 | ta T_CHANGE_PRIV |
| 10184 | setx 0x00000004003a0000, %r11, %r12 |
| 10185 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 10186 | .word 0x87acca4b ! 55: FCMPd fcmpd %fcc<n>, %f50, %f42 |
| 10187 | ibp_2_37: |
| 10188 | nop |
| 10189 | ta T_CHANGE_NONHPRIV |
| 10190 | .word 0xa3a509d3 ! 56: FDIVd fdivd %f20, %f50, %f48 |
| 10191 | brcommon3_2_38: |
| 10192 | nop |
| 10193 | setx common_target, %r12, %r27 |
| 10194 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 10195 | ba,a .+12 |
| 10196 | .word 0xe937e000 ! 1: STQF_I - %f20, [0x0000, %r31] |
| 10197 | ba,a .+8 |
| 10198 | jmpl %r27+0, %r27 |
| 10199 | .word 0xe8bfc032 ! 57: STDA_R stda %r20, [%r31 + %r18] 0x01 |
| 10200 | ibp_2_39: |
| 10201 | nop |
| 10202 | ta T_CHANGE_NONHPRIV |
| 10203 | .word 0xa1702168 ! 58: POPC_I popc 0x0168, %r16 |
| 10204 | nop |
| 10205 | ta T_CHANGE_HPRIV ! macro |
| 10206 | donret_2_40: |
| 10207 | rd %pc, %r12 |
| 10208 | mov HIGHVA_HIGHNUM, %r10 |
| 10209 | sllx %r10, 32, %r10 |
| 10210 | or %r12, %r10, %r12 |
| 10211 | add %r12, (donretarg_2_40-donret_2_40+4), %r12 |
| 10212 | add %r12, 0x4, %r11 ! seq tnpc |
| 10213 | andn %r12, %r10, %r12 ! low VA tpc |
| 10214 | wrpr %g0, 0x2, %tl |
| 10215 | wrpr %g0, %r12, %tpc |
| 10216 | wrpr %g0, %r11, %tnpc |
| 10217 | set (0x0004a500 | (0x83 << 24)), %r13 |
| 10218 | and %r12, 0xfff, %r14 |
| 10219 | sllx %r14, 32, %r14 |
| 10220 | or %r13, %r14, %r20 |
| 10221 | wrpr %r20, %g0, %tstate |
| 10222 | wrhpr %g0, 0x1e75, %htstate |
| 10223 | ta T_CHANGE_NONPRIV ! rand=0 (2) |
| 10224 | ldx [%r12+%r0], %g1 |
| 10225 | retry |
| 10226 | donretarg_2_40: |
| 10227 | .word 0x2c800001 ! 59: BNEG bneg,a <label_0x1> |
| 10228 | memptr_2_41: |
| 10229 | set 0x60140000, %r31 |
| 10230 | .word 0x8580a03e ! 60: WRCCR_I wr %r2, 0x003e, %ccr |
| 10231 | nop |
| 10232 | mov 0x80, %g3 |
| 10233 | stxa %r20, [%r0] ASI_LSU_CONTROL |
| 10234 | stxa %g3, [%g3] 0x5f |
| 10235 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 10236 | .word 0x9153c000 ! 62: RDPR_FQ <illegal instruction> |
| 10237 | bg skip_2_42 |
| 10238 | .word 0x9f803aa7 ! 1: SIR sir 0x1aa7 |
| 10239 | .align 1024 |
| 10240 | skip_2_42: |
| 10241 | .word 0x99b444d4 ! 63: FCMPNE32 fcmpne32 %d48, %d20, %r12 |
| 10242 | be,a skip_2_43 |
| 10243 | stxa %r6, [%r0] ASI_LSU_CONTROL |
| 10244 | bn,a skip_2_43 |
| 10245 | stxa %r10, [%r0] ASI_LSU_CONTROL |
| 10246 | .align 1024 |
| 10247 | skip_2_43: |
| 10248 | .word 0xd9e7c020 ! 64: CASA_I casa [%r31] 0x 1, %r0, %r12 |
| 10249 | .word 0xc19fde00 ! 65: LDDFA_R ldda [%r31, %r0], %f0 |
| 10250 | nop |
| 10251 | ta T_CHANGE_HPRIV |
| 10252 | mov 0x2+1, %r10 |
| 10253 | set sync_thr_counter5, %r23 |
| 10254 | #ifndef SPC |
| 10255 | ldxa [%g0]0x63, %o1 |
| 10256 | and %o1, 0x38, %o1 |
| 10257 | add %o1, %r23, %r23 |
| 10258 | sllx %o1, 5, %o3 !(CID*256) |
| 10259 | #endif |
| 10260 | cas [%r23],%g0,%r10 !lock |
| 10261 | brnz %r10, cwq_2_44 |
| 10262 | rd %asi, %r12 |
| 10263 | wr %g0, 0x40, %asi |
| 10264 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 10265 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 10266 | cmp %l1, 1 |
| 10267 | bne cwq_2_44 |
| 10268 | set CWQ_BASE, %l6 |
| 10269 | #ifndef SPC |
| 10270 | add %l6, %o3, %l6 |
| 10271 | #endif |
| 10272 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 10273 | best_set_reg(0x206100d0, %l1, %l2) !# Control Word |
| 10274 | sllx %l2, 32, %l2 |
| 10275 | stx %l2, [%l6 + 0x0] |
| 10276 | membar #Sync |
| 10277 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 10278 | sub %l2, 0x40, %l2 |
| 10279 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 10280 | wr %r12, %g0, %asi |
| 10281 | st %g0, [%r23] |
| 10282 | cwq_2_44: |
| 10283 | ta T_CHANGE_NONHPRIV |
| 10284 | .word 0xa1414000 ! 66: RDPC rd %pc, %r16 |
| 10285 | mondo_2_45: |
| 10286 | nop |
| 10287 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 10288 | ta T_CHANGE_PRIV |
| 10289 | stxa %r16, [%r0+0x3d0] %asi |
| 10290 | .word 0x9d904012 ! 67: WRPR_WSTATE_R wrpr %r1, %r18, %wstate |
| 10291 | .word 0x97a00162 ! 68: FABSq dis not found |
| 10292 | |
| 10293 | .word 0x9192c00c ! 69: WRPR_PIL_R wrpr %r11, %r12, %pil |
| 10294 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 10295 | #if (defined SPC || defined CMP) |
| 10296 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_2_49)+40, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10297 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_2_49)&0xffffffff) + 40, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10298 | xir_2_49: |
| 10299 | #else |
| 10300 | #if (defined FC) |
| 10301 | !! Generate XIR via RESET_GEN register |
| 10302 | ta T_CHANGE_HPRIV |
| 10303 | rdpr %pstate, %r18 |
| 10304 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 10305 | wrpr %r18, %pstate |
| 10306 | #ifndef XIR_RND_CORES |
| 10307 | ldxa [%g0] 0x63, %o1 |
| 10308 | mov 1, %r18 |
| 10309 | sllx %r18, %o1, %r18 |
| 10310 | #endif |
| 10311 | mov 0x30, %r19 |
| 10312 | setx 0x8900000808, %r16, %r17 |
| 10313 | mov 0x2, %r16 |
| 10314 | xir_2_49: |
| 10315 | stxa %r18, [%r19] 0x41 |
| 10316 | stx %r16, [%r17] |
| 10317 | #endif |
| 10318 | #endif |
| 10319 | .word 0xa984af84 ! 71: WR_SET_SOFTINT_I wr %r18, 0x0f84, %set_softint |
| 10320 | #if (defined SPC || defined CMP1) |
| 10321 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_50) + 56, 16, 16)) -> intp(6,0,12,,,,,1) |
| 10322 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_50)&0xffffffff) + 24, 16, 16)) -> intp(0,0,21,,,,,1) |
| 10323 | #else |
| 10324 | set 0x6170306c, %r28 |
| 10325 | #if (MAX_THREADS == 8) |
| 10326 | and %r28, 0x7ff, %r28 |
| 10327 | #endif |
| 10328 | stxa %r28, [%g0] 0x73 |
| 10329 | #endif |
| 10330 | .word 0xa1a1c9d0 ! 1: FDIVd fdivd %f38, %f16, %f16 |
| 10331 | intvec_2_50: |
| 10332 | .word 0xa5b144c7 ! 72: FCMPNE32 fcmpne32 %d36, %d38, %r18 |
| 10333 | invtsb_2_51: |
| 10334 | nop |
| 10335 | ta T_CHANGE_HPRIV |
| 10336 | rd %asi, %r21 |
| 10337 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 10338 | mov 1, %r20 |
| 10339 | sllx %r20, 63, %r20 |
| 10340 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 10341 | xor %r22 ,%r20, %r22 |
| 10342 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 10343 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 10344 | xor %r22 ,%r20, %r22 |
| 10345 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 10346 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 10347 | xor %r22 ,%r20, %r22 |
| 10348 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 10349 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 10350 | xor %r22 ,%r20, %r22 |
| 10351 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 10352 | wr %r21, %r0, %asi |
| 10353 | ta T_CHANGE_NONHPRIV |
| 10354 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 10355 | nop |
| 10356 | mov 0x80, %g3 |
| 10357 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 10358 | stxa %g3, [%g3] 0x57 |
| 10359 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 10360 | nop |
| 10361 | ta T_CHANGE_HPRIV |
| 10362 | mov 0x2, %r10 |
| 10363 | set sync_thr_counter6, %r23 |
| 10364 | #ifndef SPC |
| 10365 | ldxa [%g0]0x63, %o1 |
| 10366 | and %o1, 0x38, %o1 |
| 10367 | add %o1, %r23, %r23 |
| 10368 | #endif |
| 10369 | cas [%r23],%g0,%r10 !lock |
| 10370 | brnz %r10, sma_2_52 |
| 10371 | rd %asi, %r12 |
| 10372 | wr %g0, 0x40, %asi |
| 10373 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10374 | set 0x00021fff, %g1 |
| 10375 | stxa %g1, [%g0 + 0x80] %asi |
| 10376 | wr %r12, %g0, %asi |
| 10377 | st %g0, [%r23] |
| 10378 | sma_2_52: |
| 10379 | ta T_CHANGE_NONHPRIV |
| 10380 | .word 0xe5e7e009 ! 75: CASA_R casa [%r31] %asi, %r9, %r18 |
| 10381 | .word 0x91920009 ! 76: WRPR_PIL_R wrpr %r8, %r9, %pil |
| 10382 | pmu_2_54: |
| 10383 | nop |
| 10384 | setx 0xffffffb7ffffffae, %g1, %g7 |
| 10385 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 10386 | fpinit_2_55: |
| 10387 | nop |
| 10388 | setx fp_data_quads, %r19, %r20 |
| 10389 | ldd [%r20], %f0 |
| 10390 | ldd [%r20+8], %f4 |
| 10391 | ld [%r20+16], %fsr |
| 10392 | ld [%r20+24], %r19 |
| 10393 | wr %r19, %g0, %gsr |
| 10394 | .word 0xc3e82b59 ! 78: PREFETCHA_I prefetcha [%r0, + 0x0b59] %asi, #one_read |
| 10395 | jmptr_2_56: |
| 10396 | nop |
| 10397 | best_set_reg(0xe1a00000, %r20, %r27) |
| 10398 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 10399 | nop |
| 10400 | mov 0x80, %g3 |
| 10401 | stxa %r12, [%r0] ASI_LSU_CONTROL |
| 10402 | stxa %g3, [%g3] 0x5f |
| 10403 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 10404 | .word 0xa1b180e1 ! 81: EDGE16LN edge16ln %r6, %r1, %r16 |
| 10405 | #if (defined SPC || defined CMP1) |
| 10406 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_58) + 24, 16, 16)) -> intp(3,0,6,,,,,1) |
| 10407 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_58)&0xffffffff) + 8, 16, 16)) -> intp(3,0,30,,,,,1) |
| 10408 | #else |
| 10409 | set 0xd7400f77, %r28 |
| 10410 | #if (MAX_THREADS == 8) |
| 10411 | and %r28, 0x7ff, %r28 |
| 10412 | #endif |
| 10413 | stxa %r28, [%g0] 0x73 |
| 10414 | #endif |
| 10415 | .word 0xa3b344d1 ! 1: FCMPNE32 fcmpne32 %d44, %d48, %r17 |
| 10416 | intvec_2_58: |
| 10417 | .word 0x9f802142 ! 82: SIR sir 0x0142 |
| 10418 | nop |
| 10419 | ta T_CHANGE_HPRIV |
| 10420 | mov 0x2, %r10 |
| 10421 | set sync_thr_counter6, %r23 |
| 10422 | #ifndef SPC |
| 10423 | ldxa [%g0]0x63, %o1 |
| 10424 | and %o1, 0x38, %o1 |
| 10425 | add %o1, %r23, %r23 |
| 10426 | #endif |
| 10427 | cas [%r23],%g0,%r10 !lock |
| 10428 | brnz %r10, sma_2_59 |
| 10429 | rd %asi, %r12 |
| 10430 | wr %g0, 0x40, %asi |
| 10431 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10432 | set 0x00061fff, %g1 |
| 10433 | stxa %g1, [%g0 + 0x80] %asi |
| 10434 | wr %r12, %g0, %asi |
| 10435 | st %g0, [%r23] |
| 10436 | sma_2_59: |
| 10437 | ta T_CHANGE_NONHPRIV |
| 10438 | .word 0xe5e7e012 ! 83: CASA_R casa [%r31] %asi, %r18, %r18 |
| 10439 | fpinit_2_60: |
| 10440 | nop |
| 10441 | setx fp_data_quads, %r19, %r20 |
| 10442 | ldd [%r20], %f0 |
| 10443 | ldd [%r20+8], %f4 |
| 10444 | ld [%r20+16], %fsr |
| 10445 | ld [%r20+24], %r19 |
| 10446 | wr %r19, %g0, %gsr |
| 10447 | .word 0x87a80a44 ! 84: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 10448 | .word 0x8780201c ! 85: WRASI_I wr %r0, 0x001c, %asi |
| 10449 | .word 0xc19fda00 ! 86: LDDFA_R ldda [%r31, %r0], %f0 |
| 10450 | splash_lsu_2_61: |
| 10451 | nop |
| 10452 | ta T_CHANGE_HPRIV |
| 10453 | set 0xc151a1f6, %r2 |
| 10454 | mov 0x4, %r1 |
| 10455 | sllx %r1, 32, %r1 |
| 10456 | or %r1, %r2, %r2 |
| 10457 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10458 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10459 | splash_lsu_2_62: |
| 10460 | nop |
| 10461 | ta T_CHANGE_HPRIV |
| 10462 | set 0x3318d4f9, %r2 |
| 10463 | mov 0x3, %r1 |
| 10464 | sllx %r1, 32, %r1 |
| 10465 | or %r1, %r2, %r2 |
| 10466 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10467 | ta T_CHANGE_NONHPRIV |
| 10468 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10469 | splash_cmpr_2_63: |
| 10470 | mov 0, %r18 |
| 10471 | sllx %r18, 63, %r18 |
| 10472 | rd %tick, %r17 |
| 10473 | add %r17, 0x70, %r17 |
| 10474 | or %r17, %r18, %r17 |
| 10475 | ta T_CHANGE_HPRIV |
| 10476 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 10477 | .word 0xaf800011 ! 89: WR_TICK_CMPR_REG_R wr %r0, %r17, %- |
| 10478 | nop |
| 10479 | mov 0x80, %g3 |
| 10480 | .word 0x36800001 ! 1: BGE bge,a <label_0x1> |
| 10481 | stxa %g3, [%g3] 0x5f |
| 10482 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 10483 | splash_tba_2_64: |
| 10484 | nop |
| 10485 | ta T_CHANGE_PRIV |
| 10486 | set 0x120000, %r12 |
| 10487 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 10488 | dvapa_2_65: |
| 10489 | nop |
| 10490 | ta T_CHANGE_HPRIV |
| 10491 | mov 0x9b1, %r20 |
| 10492 | mov 0x19, %r19 |
| 10493 | sllx %r20, 23, %r20 |
| 10494 | or %r19, %r20, %r19 |
| 10495 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 10496 | mov 0x38, %r18 |
| 10497 | stxa %r31, [%r18]0x58 |
| 10498 | ta T_CHANGE_NONHPRIV |
| 10499 | .word 0xe49fe170 ! 92: LDDA_I ldda [%r31, + 0x0170] %asi, %r18 |
| 10500 | splash_lsu_2_66: |
| 10501 | nop |
| 10502 | ta T_CHANGE_HPRIV |
| 10503 | set 0x049a5c83, %r2 |
| 10504 | mov 0x4, %r1 |
| 10505 | sllx %r1, 32, %r1 |
| 10506 | or %r1, %r2, %r2 |
| 10507 | .word 0x30800001 ! 1: BA ba,a <label_0x1> |
| 10508 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10509 | ta T_CHANGE_NONHPRIV |
| 10510 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10511 | ibp_2_67: |
| 10512 | nop |
| 10513 | .word 0xe43fe100 ! 94: STD_I std %r18, [%r31 + 0x0100] |
| 10514 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 10515 | nop |
| 10516 | ta T_CHANGE_HPRIV |
| 10517 | mov 0x2, %r10 |
| 10518 | set sync_thr_counter6, %r23 |
| 10519 | #ifndef SPC |
| 10520 | ldxa [%g0]0x63, %o1 |
| 10521 | and %o1, 0x38, %o1 |
| 10522 | add %o1, %r23, %r23 |
| 10523 | #endif |
| 10524 | cas [%r23],%g0,%r10 !lock |
| 10525 | brnz %r10, sma_2_68 |
| 10526 | rd %asi, %r12 |
| 10527 | wr %g0, 0x40, %asi |
| 10528 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10529 | set 0x001e1fff, %g1 |
| 10530 | stxa %g1, [%g0 + 0x80] %asi |
| 10531 | wr %r12, %g0, %asi |
| 10532 | st %g0, [%r23] |
| 10533 | sma_2_68: |
| 10534 | ta T_CHANGE_NONHPRIV |
| 10535 | .word 0xe5e7e014 ! 96: CASA_R casa [%r31] %asi, %r20, %r18 |
| 10536 | #if (defined SPC || defined CMP) |
| 10537 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_2_69)+16, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10538 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_2_69)&0xffffffff) + 32, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10539 | xir_2_69: |
| 10540 | #else |
| 10541 | #if (defined FC) |
| 10542 | !! Generate XIR via RESET_GEN register |
| 10543 | ta T_CHANGE_HPRIV |
| 10544 | rdpr %pstate, %r18 |
| 10545 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 10546 | wrpr %r18, %pstate |
| 10547 | #ifndef XIR_RND_CORES |
| 10548 | ldxa [%g0] 0x63, %o1 |
| 10549 | mov 1, %r18 |
| 10550 | sllx %r18, %o1, %r18 |
| 10551 | #endif |
| 10552 | mov 0x30, %r19 |
| 10553 | setx 0x8900000808, %r16, %r17 |
| 10554 | mov 0x2, %r16 |
| 10555 | xir_2_69: |
| 10556 | stxa %r18, [%r19] 0x41 |
| 10557 | stx %r16, [%r17] |
| 10558 | #endif |
| 10559 | #endif |
| 10560 | .word 0xa9812027 ! 97: WR_SET_SOFTINT_I wr %r4, 0x0027, %set_softint |
| 10561 | #if (defined SPC || defined CMP1) |
| 10562 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_70) + 0, 16, 16)) -> intp(7,0,30,,,,,1) |
| 10563 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_2_70)&0xffffffff) + 48, 16, 16)) -> intp(5,0,2,,,,,1) |
| 10564 | #else |
| 10565 | set 0x2bd03365, %r28 |
| 10566 | #if (MAX_THREADS == 8) |
| 10567 | and %r28, 0x7ff, %r28 |
| 10568 | #endif |
| 10569 | stxa %r28, [%g0] 0x73 |
| 10570 | #endif |
| 10571 | intvec_2_70: |
| 10572 | .word 0x39400001 ! 98: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 10573 | fpinit_2_71: |
| 10574 | nop |
| 10575 | setx fp_data_quads, %r19, %r20 |
| 10576 | ldd [%r20], %f0 |
| 10577 | ldd [%r20+8], %f4 |
| 10578 | ld [%r20+16], %fsr |
| 10579 | ld [%r20+24], %r19 |
| 10580 | wr %r19, %g0, %gsr |
| 10581 | .word 0xc3e8228f ! 99: PREFETCHA_I prefetcha [%r0, + 0x028f] %asi, #one_read |
| 10582 | splash_lsu_2_72: |
| 10583 | nop |
| 10584 | ta T_CHANGE_HPRIV |
| 10585 | set 0x22ab22ae, %r2 |
| 10586 | mov 0x4, %r1 |
| 10587 | sllx %r1, 32, %r1 |
| 10588 | or %r1, %r2, %r2 |
| 10589 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10590 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10591 | .word 0x95b340f3 ! 101: EDGE16LN edge16ln %r13, %r19, %r10 |
| 10592 | nop |
| 10593 | ta T_CHANGE_HPRIV |
| 10594 | mov 0x2, %r10 |
| 10595 | set sync_thr_counter6, %r23 |
| 10596 | #ifndef SPC |
| 10597 | ldxa [%g0]0x63, %o1 |
| 10598 | and %o1, 0x38, %o1 |
| 10599 | add %o1, %r23, %r23 |
| 10600 | #endif |
| 10601 | cas [%r23],%g0,%r10 !lock |
| 10602 | brnz %r10, sma_2_74 |
| 10603 | rd %asi, %r12 |
| 10604 | wr %g0, 0x40, %asi |
| 10605 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10606 | set 0x00061fff, %g1 |
| 10607 | stxa %g1, [%g0 + 0x80] %asi |
| 10608 | wr %r12, %g0, %asi |
| 10609 | st %g0, [%r23] |
| 10610 | sma_2_74: |
| 10611 | ta T_CHANGE_NONHPRIV |
| 10612 | .word 0xd7e7e012 ! 102: CASA_R casa [%r31] %asi, %r18, %r11 |
| 10613 | nop |
| 10614 | mov 0x80, %g3 |
| 10615 | .word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1> |
| 10616 | stxa %g3, [%g3] 0x57 |
| 10617 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 10618 | invtsb_2_75: |
| 10619 | nop |
| 10620 | ta T_CHANGE_HPRIV |
| 10621 | rd %asi, %r21 |
| 10622 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 10623 | mov 1, %r20 |
| 10624 | sllx %r20, 63, %r20 |
| 10625 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 10626 | xor %r22 ,%r20, %r22 |
| 10627 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 10628 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 10629 | xor %r22 ,%r20, %r22 |
| 10630 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 10631 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 10632 | xor %r22 ,%r20, %r22 |
| 10633 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 10634 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 10635 | xor %r22 ,%r20, %r22 |
| 10636 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 10637 | wr %r21, %r0, %asi |
| 10638 | ta T_CHANGE_NONHPRIV |
| 10639 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 10640 | .word 0xc1bfe0a0 ! 105: STDFA_I stda %f0, [0x00a0, %r31] |
| 10641 | splash_lsu_2_77: |
| 10642 | nop |
| 10643 | ta T_CHANGE_HPRIV |
| 10644 | set 0x6d282347, %r2 |
| 10645 | mov 0x4, %r1 |
| 10646 | sllx %r1, 32, %r1 |
| 10647 | or %r1, %r2, %r2 |
| 10648 | .word 0x20800001 ! 1: BN bn,a <label_0x1> |
| 10649 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10650 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10651 | .word 0xc1bfd920 ! 107: STDFA_R stda %f0, [%r0, %r31] |
| 10652 | .word 0x91948007 ! 108: WRPR_PIL_R wrpr %r18, %r7, %pil |
| 10653 | splash_lsu_2_79: |
| 10654 | nop |
| 10655 | ta T_CHANGE_HPRIV |
| 10656 | set 0xa5561caf, %r2 |
| 10657 | mov 0x1, %r1 |
| 10658 | sllx %r1, 32, %r1 |
| 10659 | or %r1, %r2, %r2 |
| 10660 | .word 0x22c88001 ! 1: BRZ brz,a,pt %r2,<label_0x88001> |
| 10661 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10662 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10663 | .word 0xc1bfdb60 ! 110: STDFA_R stda %f0, [%r0, %r31] |
| 10664 | fbl,a,pn %fcc0, skip_2_80 |
| 10665 | bge,a skip_2_80 |
| 10666 | .align 128 |
| 10667 | skip_2_80: |
| 10668 | .word 0x9f802c50 ! 111: SIR sir 0x0c50 |
| 10669 | .word 0xc1bfd960 ! 112: STDFA_R stda %f0, [%r0, %r31] |
| 10670 | rd %tick, %r28 |
| 10671 | #if (MAX_THREADS == 8) |
| 10672 | sethi %hi(0x33800), %r27 |
| 10673 | #else |
| 10674 | sethi %hi(0x30000), %r27 |
| 10675 | #endif |
| 10676 | andn %r28, %r27, %r28 |
| 10677 | ta T_CHANGE_HPRIV |
| 10678 | stxa %r28, [%g0] 0x73 |
| 10679 | intvec_2_81: |
| 10680 | .word 0x9f802298 ! 113: SIR sir 0x0298 |
| 10681 | .word 0xe1bfe000 ! 114: STDFA_I stda %f16, [0x0000, %r31] |
| 10682 | nop |
| 10683 | mov 0x80, %g3 |
| 10684 | .word 0x22800001 ! 1: BE be,a <label_0x1> |
| 10685 | stxa %g3, [%g3] 0x57 |
| 10686 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 10687 | jmptr_2_82: |
| 10688 | nop |
| 10689 | best_set_reg(0xe1a00000, %r20, %r27) |
| 10690 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 10691 | splash_tba_2_83: |
| 10692 | nop |
| 10693 | ta T_CHANGE_PRIV |
| 10694 | setx 0x00000004003a0000, %r11, %r12 |
| 10695 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 10696 | .word 0x91940006 ! 118: WRPR_PIL_R wrpr %r16, %r6, %pil |
| 10697 | #if (defined SPC || defined CMP) |
| 10698 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_2_85)+56, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10699 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_2_85)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10700 | xir_2_85: |
| 10701 | #else |
| 10702 | #if (defined FC) |
| 10703 | !! Generate XIR via RESET_GEN register |
| 10704 | ta T_CHANGE_HPRIV |
| 10705 | rdpr %pstate, %r18 |
| 10706 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 10707 | wrpr %r18, %pstate |
| 10708 | #ifndef XIR_RND_CORES |
| 10709 | ldxa [%g0] 0x63, %o1 |
| 10710 | mov 1, %r18 |
| 10711 | sllx %r18, %o1, %r18 |
| 10712 | #endif |
| 10713 | mov 0x30, %r19 |
| 10714 | setx 0x8900000808, %r16, %r17 |
| 10715 | mov 0x2, %r16 |
| 10716 | xir_2_85: |
| 10717 | stxa %r18, [%r19] 0x41 |
| 10718 | stx %r16, [%r17] |
| 10719 | #endif |
| 10720 | #endif |
| 10721 | .word 0xa9817281 ! 119: WR_SET_SOFTINT_I wr %r5, 0x1281, %set_softint |
| 10722 | cwp_2_86: |
| 10723 | set user_data_start, %o7 |
| 10724 | .word 0x93902002 ! 120: WRPR_CWP_I wrpr %r0, 0x0002, %cwp |
| 10725 | nop |
| 10726 | mov 0x80, %g3 |
| 10727 | stxa %r15, [%r0] ASI_LSU_CONTROL |
| 10728 | stxa %g3, [%g3] 0x57 |
| 10729 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 10730 | nop |
| 10731 | ta T_CHANGE_HPRIV ! macro |
| 10732 | donret_2_87: |
| 10733 | rd %pc, %r12 |
| 10734 | mov HIGHVA_HIGHNUM, %r10 |
| 10735 | sllx %r10, 32, %r10 |
| 10736 | or %r12, %r10, %r12 |
| 10737 | add %r12, (donretarg_2_87-donret_2_87), %r12 |
| 10738 | add %r12, 0x4, %r11 ! seq tnpc |
| 10739 | andn %r11, %r10, %r11 ! low VA tnpc |
| 10740 | wrpr %g0, 0x2, %tl |
| 10741 | wrpr %g0, %r12, %tpc |
| 10742 | wrpr %g0, %r11, %tnpc |
| 10743 | set (0x0005df00 | (0x88 << 24)), %r13 |
| 10744 | and %r12, 0xfff, %r14 |
| 10745 | sllx %r14, 32, %r14 |
| 10746 | or %r13, %r14, %r20 |
| 10747 | wrpr %r20, %g0, %tstate |
| 10748 | wrhpr %g0, 0x9d, %htstate |
| 10749 | ta T_CHANGE_NONPRIV ! rand=0 (2) |
| 10750 | ldx [%r11+%r0], %g1 |
| 10751 | done |
| 10752 | donretarg_2_87: |
| 10753 | .word 0xe66fe089 ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x0089] |
| 10754 | invtsb_2_88: |
| 10755 | nop |
| 10756 | ta T_CHANGE_HPRIV |
| 10757 | rd %asi, %r21 |
| 10758 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 10759 | mov 1, %r20 |
| 10760 | sllx %r20, 63, %r20 |
| 10761 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 10762 | xor %r22 ,%r20, %r22 |
| 10763 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 10764 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 10765 | xor %r22 ,%r20, %r22 |
| 10766 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 10767 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 10768 | xor %r22 ,%r20, %r22 |
| 10769 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 10770 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 10771 | xor %r22 ,%r20, %r22 |
| 10772 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 10773 | wr %r21, %r0, %asi |
| 10774 | ta T_CHANGE_NONHPRIV |
| 10775 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 10776 | .word 0xa145c000 ! 124: RD_TICK_CMPR_REG rd %-, %r16 |
| 10777 | .word 0xc19fc2c0 ! 125: LDDFA_R ldda [%r31, %r0], %f0 |
| 10778 | nop |
| 10779 | ta T_CHANGE_HPRIV |
| 10780 | mov 0x2+1, %r10 |
| 10781 | set sync_thr_counter5, %r23 |
| 10782 | #ifndef SPC |
| 10783 | ldxa [%g0]0x63, %o1 |
| 10784 | and %o1, 0x38, %o1 |
| 10785 | add %o1, %r23, %r23 |
| 10786 | sllx %o1, 5, %o3 !(CID*256) |
| 10787 | #endif |
| 10788 | cas [%r23],%g0,%r10 !lock |
| 10789 | brnz %r10, cwq_2_89 |
| 10790 | rd %asi, %r12 |
| 10791 | wr %g0, 0x40, %asi |
| 10792 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 10793 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 10794 | cmp %l1, 1 |
| 10795 | bne cwq_2_89 |
| 10796 | set CWQ_BASE, %l6 |
| 10797 | #ifndef SPC |
| 10798 | add %l6, %o3, %l6 |
| 10799 | #endif |
| 10800 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 10801 | best_set_reg(0x206100e0, %l1, %l2) !# Control Word |
| 10802 | sllx %l2, 32, %l2 |
| 10803 | stx %l2, [%l6 + 0x0] |
| 10804 | membar #Sync |
| 10805 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 10806 | sub %l2, 0x40, %l2 |
| 10807 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 10808 | wr %r12, %g0, %asi |
| 10809 | st %g0, [%r23] |
| 10810 | cwq_2_89: |
| 10811 | ta T_CHANGE_NONHPRIV |
| 10812 | .word 0xa9414000 ! 126: RDPC rd %pc, %r20 |
| 10813 | .word 0xa1a00173 ! 127: FABSq dis not found |
| 10814 | |
| 10815 | #if (defined SPC || defined CMP) |
| 10816 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_2_91)+56, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10817 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_2_91)&0xffffffff) + 8, 16, 16)) -> intp(mask2tid(0x2),1,3,,,,,1) |
| 10818 | xir_2_91: |
| 10819 | #else |
| 10820 | #if (defined FC) |
| 10821 | !! Generate XIR via RESET_GEN register |
| 10822 | ta T_CHANGE_HPRIV |
| 10823 | rdpr %pstate, %r18 |
| 10824 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 10825 | wrpr %r18, %pstate |
| 10826 | #ifndef XIR_RND_CORES |
| 10827 | ldxa [%g0] 0x63, %o1 |
| 10828 | mov 1, %r18 |
| 10829 | sllx %r18, %o1, %r18 |
| 10830 | #endif |
| 10831 | mov 0x30, %r19 |
| 10832 | setx 0x8900000808, %r16, %r17 |
| 10833 | mov 0x2, %r16 |
| 10834 | xir_2_91: |
| 10835 | stxa %r18, [%r19] 0x41 |
| 10836 | stx %r16, [%r17] |
| 10837 | #endif |
| 10838 | #endif |
| 10839 | .word 0xa984fff1 ! 128: WR_SET_SOFTINT_I wr %r19, 0x1ff1, %set_softint |
| 10840 | memptr_2_92: |
| 10841 | set 0x60340000, %r31 |
| 10842 | .word 0x8584b933 ! 129: WRCCR_I wr %r18, 0x1933, %ccr |
| 10843 | rd %tick, %r28 |
| 10844 | #if (MAX_THREADS == 8) |
| 10845 | sethi %hi(0x33800), %r27 |
| 10846 | #else |
| 10847 | sethi %hi(0x30000), %r27 |
| 10848 | #endif |
| 10849 | andn %r28, %r27, %r28 |
| 10850 | ta T_CHANGE_HPRIV |
| 10851 | stxa %r28, [%g0] 0x73 |
| 10852 | intvec_2_93: |
| 10853 | .word 0x39400001 ! 130: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 10854 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 10855 | memptr_2_95: |
| 10856 | set 0x60740000, %r31 |
| 10857 | .word 0x8584a86b ! 132: WRCCR_I wr %r18, 0x086b, %ccr |
| 10858 | splash_hpstate_2_96: |
| 10859 | .word 0x2ecd0001 ! 1: BRGEZ brgez,a,pt %r20,<label_0xd0001> |
| 10860 | .word 0x819834d6 ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x14d6, %hpstate |
| 10861 | jmptr_2_97: |
| 10862 | nop |
| 10863 | best_set_reg(0xe1a00000, %r20, %r27) |
| 10864 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 10865 | bne,a skip_2_98 |
| 10866 | stxa %r18, [%r0] ASI_LSU_CONTROL |
| 10867 | brlez,a,pt %r19, skip_2_98 |
| 10868 | stxa %r8, [%r0] ASI_LSU_CONTROL |
| 10869 | .align 128 |
| 10870 | skip_2_98: |
| 10871 | .word 0xd23fc000 ! 135: STD_R std %r9, [%r31 + %r0] |
| 10872 | .word 0x8d903db3 ! 136: WRPR_PSTATE_I wrpr %r0, 0x1db3, %pstate |
| 10873 | .word 0x9ba00170 ! 137: FABSq dis not found |
| 10874 | |
| 10875 | nop |
| 10876 | ta T_CHANGE_HPRIV |
| 10877 | mov 0x2, %r10 |
| 10878 | set sync_thr_counter6, %r23 |
| 10879 | #ifndef SPC |
| 10880 | ldxa [%g0]0x63, %o1 |
| 10881 | and %o1, 0x38, %o1 |
| 10882 | add %o1, %r23, %r23 |
| 10883 | #endif |
| 10884 | cas [%r23],%g0,%r10 !lock |
| 10885 | brnz %r10, sma_2_101 |
| 10886 | rd %asi, %r12 |
| 10887 | wr %g0, 0x40, %asi |
| 10888 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10889 | set 0x001e1fff, %g1 |
| 10890 | stxa %g1, [%g0 + 0x80] %asi |
| 10891 | wr %r12, %g0, %asi |
| 10892 | st %g0, [%r23] |
| 10893 | sma_2_101: |
| 10894 | ta T_CHANGE_NONHPRIV |
| 10895 | .word 0xe1e7e011 ! 138: CASA_R casa [%r31] %asi, %r17, %r16 |
| 10896 | .word 0x95b300f2 ! 139: EDGE16LN edge16ln %r12, %r18, %r10 |
| 10897 | splash_lsu_2_103: |
| 10898 | nop |
| 10899 | ta T_CHANGE_HPRIV |
| 10900 | set 0xb6b0d0f0, %r2 |
| 10901 | mov 0x3, %r1 |
| 10902 | sllx %r1, 32, %r1 |
| 10903 | or %r1, %r2, %r2 |
| 10904 | .word 0x24800001 ! 1: BLE ble,a <label_0x1> |
| 10905 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10906 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 10907 | .word 0x93688013 ! 141: SDIVX_R sdivx %r2, %r19, %r9 |
| 10908 | .word 0xe19fe020 ! 142: LDDFA_I ldda [%r31, 0x0020], %f16 |
| 10909 | .word 0x91924004 ! 143: WRPR_PIL_R wrpr %r9, %r4, %pil |
| 10910 | splash_hpstate_2_105: |
| 10911 | ta T_CHANGE_NONHPRIV |
| 10912 | .word 0x81982de7 ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x0de7, %hpstate |
| 10913 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 10914 | nop |
| 10915 | ta T_CHANGE_HPRIV |
| 10916 | mov 0x2, %r10 |
| 10917 | set sync_thr_counter6, %r23 |
| 10918 | #ifndef SPC |
| 10919 | ldxa [%g0]0x63, %o1 |
| 10920 | and %o1, 0x38, %o1 |
| 10921 | add %o1, %r23, %r23 |
| 10922 | #endif |
| 10923 | cas [%r23],%g0,%r10 !lock |
| 10924 | brnz %r10, sma_2_107 |
| 10925 | rd %asi, %r12 |
| 10926 | wr %g0, 0x40, %asi |
| 10927 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 10928 | set 0x000a1fff, %g1 |
| 10929 | stxa %g1, [%g0 + 0x80] %asi |
| 10930 | wr %r12, %g0, %asi |
| 10931 | st %g0, [%r23] |
| 10932 | sma_2_107: |
| 10933 | ta T_CHANGE_NONHPRIV |
| 10934 | .word 0xd1e7e00b ! 146: CASA_R casa [%r31] %asi, %r11, %r8 |
| 10935 | fpinit_2_108: |
| 10936 | nop |
| 10937 | setx fp_data_quads, %r19, %r20 |
| 10938 | ldd [%r20], %f0 |
| 10939 | ldd [%r20+8], %f4 |
| 10940 | ld [%r20+16], %fsr |
| 10941 | ld [%r20+24], %r19 |
| 10942 | wr %r19, %g0, %gsr |
| 10943 | .word 0x87a80a44 ! 147: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 10944 | intveclr_2_109: |
| 10945 | nop |
| 10946 | ta T_CHANGE_HPRIV |
| 10947 | setx 0x75dfc8e8302f2b6e, %r1, %r28 |
| 10948 | stxa %r28, [%g0] 0x72 |
| 10949 | ta T_CHANGE_NONHPRIV |
| 10950 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 10951 | brcommon3_2_110: |
| 10952 | nop |
| 10953 | setx common_target, %r12, %r27 |
| 10954 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 10955 | ba,a .+12 |
| 10956 | .word 0xd06fe020 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x0020] |
| 10957 | ba,a .+8 |
| 10958 | jmpl %r27+0, %r27 |
| 10959 | .word 0xd097c029 ! 149: LDUHA_R lduha [%r31, %r9] 0x01, %r8 |
| 10960 | .word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 10961 | .word 0x8d903a7b ! 150: WRPR_PSTATE_I wrpr %r0, 0x1a7b, %pstate |
| 10962 | nop |
| 10963 | nop |
| 10964 | ta T_CHANGE_PRIV |
| 10965 | wrpr %g0, %g0, %gl |
| 10966 | nop |
| 10967 | nop |
| 10968 | .text |
| 10969 | setx join_lbl_0_0, %g1, %g2 |
| 10970 | jmp %g2 |
| 10971 | nop |
| 10972 | fork_lbl_0_1: |
| 10973 | ta T_CHANGE_NONHPRIV |
| 10974 | .word 0xe877e0f9 ! 1: STX_I stx %r20, [%r31 + 0x00f9] |
| 10975 | br_longdelay4_1_0: |
| 10976 | nop |
| 10977 | not %g0, %r27 |
| 10978 | jmpl %r27+0, %r27 |
| 10979 | .word 0x9d902003 ! 2: WRPR_WSTATE_I wrpr %r0, 0x0003, %wstate |
| 10980 | .word 0xe93fe1d9 ! 3: STDF_I std %f20, [0x01d9, %r31] |
| 10981 | fpinit_1_1: |
| 10982 | nop |
| 10983 | setx fp_data_quads, %r19, %r20 |
| 10984 | ldd [%r20], %f0 |
| 10985 | ldd [%r20+8], %f4 |
| 10986 | ld [%r20+16], %fsr |
| 10987 | ld [%r20+24], %r19 |
| 10988 | wr %r19, %g0, %gsr |
| 10989 | .word 0x87a80a44 ! 4: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 10990 | splash_lsu_1_2: |
| 10991 | nop |
| 10992 | ta T_CHANGE_HPRIV |
| 10993 | set 0x033656e3, %r2 |
| 10994 | mov 0x3, %r1 |
| 10995 | sllx %r1, 32, %r1 |
| 10996 | or %r1, %r2, %r2 |
| 10997 | .word 0x2acc0001 ! 1: BRNZ brnz,a,pt %r16,<label_0xc0001> |
| 10998 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 10999 | ta T_CHANGE_NONHPRIV |
| 11000 | .word 0x3d400001 ! 5: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11001 | splash_hpstate_1_3: |
| 11002 | .word 0x81982f66 ! 6: WRHPR_HPSTATE_I wrhpr %r0, 0x0f66, %hpstate |
| 11003 | memptr_1_4: |
| 11004 | set 0x60540000, %r31 |
| 11005 | .word 0x8580bf76 ! 7: WRCCR_I wr %r2, 0x1f76, %ccr |
| 11006 | nop |
| 11007 | mov 0x80, %g3 |
| 11008 | .word 0x22cc4001 ! 1: BRZ brz,a,pt %r17,<label_0xc4001> |
| 11009 | stxa %g3, [%g3] 0x57 |
| 11010 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 11011 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 11012 | .word 0xe85fc000 ! 8: LDX_R ldx [%r31 + %r0], %r20 |
| 11013 | .word 0xe19fe1c0 ! 9: LDDFA_I ldda [%r31, 0x01c0], %f16 |
| 11014 | .word 0x89800011 ! 10: WRTICK_R wr %r0, %r17, %tick |
| 11015 | .word 0xc1bfda00 ! 11: STDFA_R stda %f0, [%r0, %r31] |
| 11016 | dvapa_1_6: |
| 11017 | nop |
| 11018 | ta T_CHANGE_HPRIV |
| 11019 | mov 0x85c, %r20 |
| 11020 | mov 0x1b, %r19 |
| 11021 | sllx %r20, 23, %r20 |
| 11022 | or %r19, %r20, %r19 |
| 11023 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 11024 | mov 0x38, %r18 |
| 11025 | stxa %r31, [%r18]0x58 |
| 11026 | ta T_CHANGE_NONHPRIV |
| 11027 | .word 0xc19fe120 ! 12: LDDFA_I ldda [%r31, 0x0120], %f0 |
| 11028 | .word 0x3c800001 ! 13: BPOS bpos,a <label_0x1> |
| 11029 | jmptr_1_7: |
| 11030 | nop |
| 11031 | best_set_reg(0xe0200000, %r20, %r27) |
| 11032 | .word 0xb7c6c000 ! 14: JMPL_R jmpl %r27 + %r0, %r27 |
| 11033 | pmu_1_8: |
| 11034 | nop |
| 11035 | ta T_CHANGE_PRIV |
| 11036 | setx 0xffffffbaffffffac, %g1, %g7 |
| 11037 | .word 0xa3800007 ! 15: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 11038 | jmptr_1_9: |
| 11039 | nop |
| 11040 | best_set_reg(0xe0200000, %r20, %r27) |
| 11041 | .word 0xb7c6c000 ! 16: JMPL_R jmpl %r27 + %r0, %r27 |
| 11042 | nop |
| 11043 | ta T_CHANGE_HPRIV |
| 11044 | mov 0x1, %r10 |
| 11045 | set sync_thr_counter6, %r23 |
| 11046 | #ifndef SPC |
| 11047 | ldxa [%g0]0x63, %o1 |
| 11048 | and %o1, 0x38, %o1 |
| 11049 | add %o1, %r23, %r23 |
| 11050 | #endif |
| 11051 | cas [%r23],%g0,%r10 !lock |
| 11052 | brnz %r10, sma_1_10 |
| 11053 | rd %asi, %r12 |
| 11054 | wr %g0, 0x40, %asi |
| 11055 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11056 | set 0x000a1fff, %g1 |
| 11057 | stxa %g1, [%g0 + 0x80] %asi |
| 11058 | wr %r12, %g0, %asi |
| 11059 | st %g0, [%r23] |
| 11060 | sma_1_10: |
| 11061 | ta T_CHANGE_NONHPRIV |
| 11062 | .word 0xe9e7e00b ! 17: CASA_R casa [%r31] %asi, %r11, %r20 |
| 11063 | .word 0x87802082 ! 18: WRASI_I wr %r0, 0x0082, %asi |
| 11064 | splash_lsu_1_11: |
| 11065 | nop |
| 11066 | ta T_CHANGE_HPRIV |
| 11067 | set 0x159c14d4, %r2 |
| 11068 | mov 0x5, %r1 |
| 11069 | sllx %r1, 32, %r1 |
| 11070 | or %r1, %r2, %r2 |
| 11071 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11072 | .word 0x3d400001 ! 19: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11073 | .word 0xe93fe192 ! 20: STDF_I std %f20, [0x0192, %r31] |
| 11074 | brcommon1_1_12: |
| 11075 | nop |
| 11076 | setx common_target, %r12, %r27 |
| 11077 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 11078 | ba,a .+12 |
| 11079 | .word 0xa9b7c7d1 ! 1: PDIST pdistn %d62, %d48, %d20 |
| 11080 | ba,a .+8 |
| 11081 | jmpl %r27+0, %r27 |
| 11082 | .word 0x91a049d3 ! 21: FDIVd fdivd %f32, %f50, %f8 |
| 11083 | splash_lsu_1_13: |
| 11084 | nop |
| 11085 | ta T_CHANGE_HPRIV |
| 11086 | set 0x8a30f39a, %r2 |
| 11087 | mov 0x1, %r1 |
| 11088 | sllx %r1, 32, %r1 |
| 11089 | or %r1, %r2, %r2 |
| 11090 | .word 0x3f400001 ! 1: FBPO fbo,a,pn %fcc0, <label_0x1> |
| 11091 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11092 | ta T_CHANGE_NONHPRIV |
| 11093 | .word 0x3d400001 ! 22: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11094 | .word 0xe19fde00 ! 23: LDDFA_R ldda [%r31, %r0], %f16 |
| 11095 | .word 0xc1bfd920 ! 24: STDFA_R stda %f0, [%r0, %r31] |
| 11096 | pmu_1_14: |
| 11097 | nop |
| 11098 | ta T_CHANGE_PRIV |
| 11099 | setx 0xffffffbbffffffa1, %g1, %g7 |
| 11100 | .word 0xa3800007 ! 25: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 11101 | rd %tick, %r28 |
| 11102 | #if (MAX_THREADS == 8) |
| 11103 | sethi %hi(0x33800), %r27 |
| 11104 | #else |
| 11105 | sethi %hi(0x30000), %r27 |
| 11106 | #endif |
| 11107 | andn %r28, %r27, %r28 |
| 11108 | ta T_CHANGE_HPRIV |
| 11109 | stxa %r28, [%g0] 0x73 |
| 11110 | .word 0x9f803e4d ! 1: SIR sir 0x1e4d |
| 11111 | intvec_1_15: |
| 11112 | .word 0xc36b366e ! 26: PREFETCH_I prefetch [%r12 + 0xfffff66e], #one_read |
| 11113 | .word 0x91948013 ! 27: WRPR_PIL_R wrpr %r18, %r19, %pil |
| 11114 | nop |
| 11115 | mov 0x80, %g3 |
| 11116 | stxa %g3, [%g3] 0x5f |
| 11117 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 11118 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11119 | .word 0xd85fc000 ! 28: LDX_R ldx [%r31 + %r0], %r12 |
| 11120 | #if (defined SPC || defined CMP) |
| 11121 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_1_17)+0, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11122 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_1_17)&0xffffffff) + 56, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11123 | xir_1_17: |
| 11124 | #else |
| 11125 | #if (defined FC) |
| 11126 | !! Generate XIR via RESET_GEN register |
| 11127 | ta T_CHANGE_HPRIV |
| 11128 | rdpr %pstate, %r18 |
| 11129 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 11130 | wrpr %r18, %pstate |
| 11131 | #ifndef XIR_RND_CORES |
| 11132 | ldxa [%g0] 0x63, %o1 |
| 11133 | mov 1, %r18 |
| 11134 | sllx %r18, %o1, %r18 |
| 11135 | #endif |
| 11136 | mov 0x30, %r19 |
| 11137 | setx 0x8900000808, %r16, %r17 |
| 11138 | mov 0x2, %r16 |
| 11139 | xir_1_17: |
| 11140 | stxa %r18, [%r19] 0x41 |
| 11141 | stx %r16, [%r17] |
| 11142 | #endif |
| 11143 | #endif |
| 11144 | .word 0xa981befc ! 29: WR_SET_SOFTINT_I wr %r6, 0x1efc, %set_softint |
| 11145 | .word 0x93a00165 ! 30: FABSq dis not found |
| 11146 | |
| 11147 | .word 0x99a0016a ! 31: FABSq dis not found |
| 11148 | |
| 11149 | tagged_1_20: |
| 11150 | tsubcctv %r4, 0x102f, %r20 |
| 11151 | .word 0xd807e110 ! 32: LDUW_I lduw [%r31 + 0x0110], %r12 |
| 11152 | mondo_1_21: |
| 11153 | nop |
| 11154 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 11155 | stxa %r18, [%r0+0x3c8] %asi |
| 11156 | .word 0x9d914001 ! 33: WRPR_WSTATE_R wrpr %r5, %r1, %wstate |
| 11157 | .word 0xb1848002 ! 34: WR_STICK_REG_R wr %r18, %r2, %- |
| 11158 | nop |
| 11159 | ta T_CHANGE_HPRIV |
| 11160 | mov 0x1, %r10 |
| 11161 | set sync_thr_counter6, %r23 |
| 11162 | #ifndef SPC |
| 11163 | ldxa [%g0]0x63, %o1 |
| 11164 | and %o1, 0x38, %o1 |
| 11165 | add %o1, %r23, %r23 |
| 11166 | #endif |
| 11167 | cas [%r23],%g0,%r10 !lock |
| 11168 | brnz %r10, sma_1_22 |
| 11169 | rd %asi, %r12 |
| 11170 | wr %g0, 0x40, %asi |
| 11171 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11172 | set 0x00061fff, %g1 |
| 11173 | stxa %g1, [%g0 + 0x80] %asi |
| 11174 | wr %r12, %g0, %asi |
| 11175 | st %g0, [%r23] |
| 11176 | sma_1_22: |
| 11177 | ta T_CHANGE_NONHPRIV |
| 11178 | .word 0xd9e7e008 ! 35: CASA_R casa [%r31] %asi, %r8, %r12 |
| 11179 | nop |
| 11180 | ta T_CHANGE_HPRIV |
| 11181 | mov 0x1, %r10 |
| 11182 | set sync_thr_counter6, %r23 |
| 11183 | #ifndef SPC |
| 11184 | ldxa [%g0]0x63, %o1 |
| 11185 | and %o1, 0x38, %o1 |
| 11186 | add %o1, %r23, %r23 |
| 11187 | #endif |
| 11188 | cas [%r23],%g0,%r10 !lock |
| 11189 | brnz %r10, sma_1_23 |
| 11190 | rd %asi, %r12 |
| 11191 | wr %g0, 0x40, %asi |
| 11192 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11193 | set 0x001e1fff, %g1 |
| 11194 | stxa %g1, [%g0 + 0x80] %asi |
| 11195 | wr %r12, %g0, %asi |
| 11196 | st %g0, [%r23] |
| 11197 | sma_1_23: |
| 11198 | ta T_CHANGE_NONHPRIV |
| 11199 | .word 0xd9e7e00c ! 36: CASA_R casa [%r31] %asi, %r12, %r12 |
| 11200 | splash_tba_1_24: |
| 11201 | nop |
| 11202 | ta T_CHANGE_PRIV |
| 11203 | set 0x120000, %r12 |
| 11204 | .word 0x8b90000c ! 37: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 11205 | splash_lsu_1_25: |
| 11206 | nop |
| 11207 | ta T_CHANGE_HPRIV |
| 11208 | set 0xd2da4b5f, %r2 |
| 11209 | mov 0x1, %r1 |
| 11210 | sllx %r1, 32, %r1 |
| 11211 | or %r1, %r2, %r2 |
| 11212 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11213 | ta T_CHANGE_NONHPRIV |
| 11214 | .word 0x3d400001 ! 38: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11215 | #if (defined SPC || defined CMP1) |
| 11216 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_26) + 16, 16, 16)) -> intp(6,0,31,,,,,1) |
| 11217 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_26)&0xffffffff) + 48, 16, 16)) -> intp(0,0,30,,,,,1) |
| 11218 | #else |
| 11219 | set 0x7b40069e, %r28 |
| 11220 | #if (MAX_THREADS == 8) |
| 11221 | and %r28, 0x7ff, %r28 |
| 11222 | #endif |
| 11223 | stxa %r28, [%g0] 0x73 |
| 11224 | #endif |
| 11225 | .word 0x93b484cc ! 1: FCMPNE32 fcmpne32 %d18, %d12, %r9 |
| 11226 | intvec_1_26: |
| 11227 | .word 0x9f8021ae ! 39: SIR sir 0x01ae |
| 11228 | .word 0xd727e0b4 ! 40: STF_I st %f11, [0x00b4, %r31] |
| 11229 | .word 0xd627e1c0 ! 41: STW_I stw %r11, [%r31 + 0x01c0] |
| 11230 | jmptr_1_27: |
| 11231 | nop |
| 11232 | best_set_reg(0xe0200000, %r20, %r27) |
| 11233 | .word 0xb7c6c000 ! 42: JMPL_R jmpl %r27 + %r0, %r27 |
| 11234 | splash_tba_1_28: |
| 11235 | nop |
| 11236 | ta T_CHANGE_PRIV |
| 11237 | set 0x120000, %r12 |
| 11238 | .word 0x8b90000c ! 43: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 11239 | set 0x774, %l3 |
| 11240 | stxa %l3, [%g0] ASI_SPARC_PWR_MGMT |
| 11241 | .word 0xa3b187d1 ! 44: PDIST pdistn %d6, %d48, %d48 |
| 11242 | pmu_1_29: |
| 11243 | nop |
| 11244 | setx 0xffffffbfffffffac, %g1, %g7 |
| 11245 | .word 0xa3800007 ! 45: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 11246 | brcommon3_1_30: |
| 11247 | nop |
| 11248 | setx common_target, %r12, %r27 |
| 11249 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 11250 | ba,a .+12 |
| 11251 | .word 0xe3e7c02b ! 1: CASA_I casa [%r31] 0x 1, %r11, %r17 |
| 11252 | ba,a .+8 |
| 11253 | jmpl %r27+0, %r27 |
| 11254 | .word 0xe33fc011 ! 46: STDF_R std %f17, [%r17, %r31] |
| 11255 | brcommon3_1_31: |
| 11256 | nop |
| 11257 | setx common_target, %r12, %r27 |
| 11258 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 11259 | ba,a .+12 |
| 11260 | .word 0xe26fe1d0 ! 1: LDSTUB_I ldstub %r17, [%r31 + 0x01d0] |
| 11261 | ba,a .+8 |
| 11262 | jmpl %r27+0, %r27 |
| 11263 | stxa %r6, [%r0] ASI_LSU_CONTROL |
| 11264 | .word 0x97aac833 ! 47: FMOVGE fmovs %fcc1, %f19, %f11 |
| 11265 | brcommon3_1_32: |
| 11266 | nop |
| 11267 | setx common_target, %r12, %r27 |
| 11268 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 11269 | ba,a .+12 |
| 11270 | .word 0xd737e1f0 ! 1: STQF_I - %f11, [0x01f0, %r31] |
| 11271 | ba,a .+8 |
| 11272 | jmpl %r27+0, %r27 |
| 11273 | .word 0xd6dfc034 ! 48: LDXA_R ldxa [%r31, %r20] 0x01, %r11 |
| 11274 | nop |
| 11275 | mov 0x80, %g3 |
| 11276 | .word 0x23400001 ! 1: FBPNE fbne,a,pn %fcc0, <label_0x1> |
| 11277 | stxa %g3, [%g3] 0x5f |
| 11278 | .word 0xd65fc000 ! 49: LDX_R ldx [%r31 + %r0], %r11 |
| 11279 | nop |
| 11280 | ta T_CHANGE_HPRIV ! macro |
| 11281 | donret_1_33: |
| 11282 | rd %pc, %r12 |
| 11283 | mov HIGHVA_HIGHNUM, %r10 |
| 11284 | sllx %r10, 32, %r10 |
| 11285 | or %r12, %r10, %r12 |
| 11286 | add %r12, (donretarg_1_33-donret_1_33), %r12 |
| 11287 | add %r12, 0x8, %r11 ! nonseq tnpc |
| 11288 | andn %r11, %r10, %r11 ! low VA tnpc |
| 11289 | wrpr %g0, 0x2, %tl |
| 11290 | wrpr %g0, %r12, %tpc |
| 11291 | wrpr %g0, %r11, %tnpc |
| 11292 | set (0x00f4d400 | (0x58 << 24)), %r13 |
| 11293 | and %r12, 0xfff, %r14 |
| 11294 | sllx %r14, 32, %r14 |
| 11295 | or %r13, %r14, %r20 |
| 11296 | wrpr %r20, %g0, %tstate |
| 11297 | wrhpr %g0, 0x187, %htstate |
| 11298 | ta T_CHANGE_NONHPRIV ! rand=1 (1) |
| 11299 | ldx [%r11+%r0], %g1 |
| 11300 | done |
| 11301 | donretarg_1_33: |
| 11302 | .word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 11303 | #if (defined SPC || defined CMP1) |
| 11304 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_34) + 16, 16, 16)) -> intp(0,0,28,,,,,1) |
| 11305 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_34)&0xffffffff) + 16, 16, 16)) -> intp(1,0,28,,,,,1) |
| 11306 | #else |
| 11307 | set 0x26002252, %r28 |
| 11308 | #if (MAX_THREADS == 8) |
| 11309 | and %r28, 0x7ff, %r28 |
| 11310 | #endif |
| 11311 | stxa %r28, [%g0] 0x73 |
| 11312 | #endif |
| 11313 | intvec_1_34: |
| 11314 | .word 0x9f803bc1 ! 51: SIR sir 0x1bc1 |
| 11315 | .word 0xe927e114 ! 52: STF_I st %f20, [0x0114, %r31] |
| 11316 | .word 0xe8bfc020 ! 53: STDA_R stda %r20, [%r31 + %r0] 0x01 |
| 11317 | splash_tba_1_35: |
| 11318 | nop |
| 11319 | ta T_CHANGE_PRIV |
| 11320 | setx 0x0000000000380000, %r11, %r12 |
| 11321 | .word 0x8b90000c ! 54: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 11322 | .word 0xa1a489cc ! 55: FDIVd fdivd %f18, %f12, %f16 |
| 11323 | ibp_1_37: |
| 11324 | nop |
| 11325 | ta T_CHANGE_NONHPRIV |
| 11326 | .word 0xa970355c ! 56: POPC_I popc 0x155c, %r20 |
| 11327 | brcommon3_1_38: |
| 11328 | nop |
| 11329 | setx common_target, %r12, %r27 |
| 11330 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 11331 | ba,a .+12 |
| 11332 | .word 0xe937e060 ! 1: STQF_I - %f20, [0x0060, %r31] |
| 11333 | ba,a .+8 |
| 11334 | jmpl %r27+0, %r27 |
| 11335 | .word 0xe89fc02a ! 57: LDDA_R ldda [%r31, %r10] 0x01, %r20 |
| 11336 | ibp_1_39: |
| 11337 | nop |
| 11338 | ta T_CHANGE_NONHPRIV |
| 11339 | .word 0xc3ecc031 ! 58: PREFETCHA_R prefetcha [%r19, %r17] 0x01, #one_read |
| 11340 | nop |
| 11341 | ta T_CHANGE_HPRIV ! macro |
| 11342 | donret_1_40: |
| 11343 | rd %pc, %r12 |
| 11344 | mov HIGHVA_HIGHNUM, %r10 |
| 11345 | sllx %r10, 32, %r10 |
| 11346 | or %r12, %r10, %r12 |
| 11347 | add %r12, (donretarg_1_40-donret_1_40+4), %r12 |
| 11348 | add %r12, 0x4, %r11 ! seq tnpc |
| 11349 | andn %r12, %r10, %r12 ! low VA tpc |
| 11350 | wrpr %g0, 0x1, %tl |
| 11351 | wrpr %g0, %r12, %tpc |
| 11352 | wrpr %g0, %r11, %tnpc |
| 11353 | set (0x00bdcb00 | (0x80 << 24)), %r13 |
| 11354 | and %r12, 0xfff, %r14 |
| 11355 | sllx %r14, 32, %r14 |
| 11356 | or %r13, %r14, %r20 |
| 11357 | wrpr %r20, %g0, %tstate |
| 11358 | wrhpr %g0, 0xe85, %htstate |
| 11359 | ta T_CHANGE_NONPRIV ! rand=0 (1) |
| 11360 | ldx [%r12+%r0], %g1 |
| 11361 | retry |
| 11362 | donretarg_1_40: |
| 11363 | .word 0x27400001 ! 59: FBPUL fbul,a,pn %fcc0, <label_0x1> |
| 11364 | memptr_1_41: |
| 11365 | set 0x60140000, %r31 |
| 11366 | .word 0x8584a4cf ! 60: WRCCR_I wr %r18, 0x04cf, %ccr |
| 11367 | nop |
| 11368 | mov 0x80, %g3 |
| 11369 | stxa %g3, [%g3] 0x5f |
| 11370 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11371 | .word 0xe05fc000 ! 61: LDX_R ldx [%r31 + %r0], %r16 |
| 11372 | .word 0x9753c000 ! 62: RDPR_FQ <illegal instruction> |
| 11373 | .word 0x39400001 ! 63: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 11374 | .word 0xd83fc000 ! 64: STD_R std %r12, [%r31 + %r0] |
| 11375 | .word 0xc19fdf20 ! 65: LDDFA_R ldda [%r31, %r0], %f0 |
| 11376 | nop |
| 11377 | ta T_CHANGE_HPRIV |
| 11378 | mov 0x1+1, %r10 |
| 11379 | set sync_thr_counter5, %r23 |
| 11380 | #ifndef SPC |
| 11381 | ldxa [%g0]0x63, %o1 |
| 11382 | and %o1, 0x38, %o1 |
| 11383 | add %o1, %r23, %r23 |
| 11384 | sllx %o1, 5, %o3 !(CID*256) |
| 11385 | #endif |
| 11386 | cas [%r23],%g0,%r10 !lock |
| 11387 | brnz %r10, cwq_1_44 |
| 11388 | rd %asi, %r12 |
| 11389 | wr %g0, 0x40, %asi |
| 11390 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 11391 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 11392 | cmp %l1, 1 |
| 11393 | bne cwq_1_44 |
| 11394 | set CWQ_BASE, %l6 |
| 11395 | #ifndef SPC |
| 11396 | add %l6, %o3, %l6 |
| 11397 | #endif |
| 11398 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 11399 | best_set_reg(0x20610070, %l1, %l2) !# Control Word |
| 11400 | sllx %l2, 32, %l2 |
| 11401 | stx %l2, [%l6 + 0x0] |
| 11402 | membar #Sync |
| 11403 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 11404 | sub %l2, 0x40, %l2 |
| 11405 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 11406 | wr %r12, %g0, %asi |
| 11407 | st %g0, [%r23] |
| 11408 | cwq_1_44: |
| 11409 | ta T_CHANGE_NONHPRIV |
| 11410 | .word 0xa1414000 ! 66: RDPC rd %pc, %r16 |
| 11411 | mondo_1_45: |
| 11412 | nop |
| 11413 | .word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi |
| 11414 | ta T_CHANGE_PRIV |
| 11415 | stxa %r20, [%r0+0x3d0] %asi |
| 11416 | .word 0x9d92c002 ! 67: WRPR_WSTATE_R wrpr %r11, %r2, %wstate |
| 11417 | .word 0xa7a00172 ! 68: FABSq dis not found |
| 11418 | |
| 11419 | .word 0x91948009 ! 69: WRPR_PIL_R wrpr %r18, %r9, %pil |
| 11420 | .word 0x89800011 ! 70: WRTICK_R wr %r0, %r17, %tick |
| 11421 | #if (defined SPC || defined CMP) |
| 11422 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_1_49)+32, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11423 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_1_49)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11424 | xir_1_49: |
| 11425 | #else |
| 11426 | #if (defined FC) |
| 11427 | !! Generate XIR via RESET_GEN register |
| 11428 | ta T_CHANGE_HPRIV |
| 11429 | rdpr %pstate, %r18 |
| 11430 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 11431 | wrpr %r18, %pstate |
| 11432 | #ifndef XIR_RND_CORES |
| 11433 | ldxa [%g0] 0x63, %o1 |
| 11434 | mov 1, %r18 |
| 11435 | sllx %r18, %o1, %r18 |
| 11436 | #endif |
| 11437 | mov 0x30, %r19 |
| 11438 | setx 0x8900000808, %r16, %r17 |
| 11439 | mov 0x2, %r16 |
| 11440 | xir_1_49: |
| 11441 | stxa %r18, [%r19] 0x41 |
| 11442 | stx %r16, [%r17] |
| 11443 | #endif |
| 11444 | #endif |
| 11445 | .word 0xa9823fa9 ! 71: WR_SET_SOFTINT_I wr %r8, 0x1fa9, %set_softint |
| 11446 | #if (defined SPC || defined CMP1) |
| 11447 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_50) + 16, 16, 16)) -> intp(5,0,13,,,,,1) |
| 11448 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_50)&0xffffffff) + 8, 16, 16)) -> intp(6,0,1,,,,,1) |
| 11449 | #else |
| 11450 | set 0x4bd067d0, %r28 |
| 11451 | #if (MAX_THREADS == 8) |
| 11452 | and %r28, 0x7ff, %r28 |
| 11453 | #endif |
| 11454 | stxa %r28, [%g0] 0x73 |
| 11455 | #endif |
| 11456 | .word 0xa3a1c9c6 ! 1: FDIVd fdivd %f38, %f6, %f48 |
| 11457 | intvec_1_50: |
| 11458 | .word 0xc368ab59 ! 72: PREFETCH_I prefetch [%r2 + 0x0b59], #one_read |
| 11459 | invtsb_1_51: |
| 11460 | nop |
| 11461 | ta T_CHANGE_HPRIV |
| 11462 | rd %asi, %r21 |
| 11463 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 11464 | mov 1, %r20 |
| 11465 | sllx %r20, 63, %r20 |
| 11466 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 11467 | xor %r22 ,%r20, %r22 |
| 11468 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 11469 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 11470 | xor %r22 ,%r20, %r22 |
| 11471 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 11472 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 11473 | xor %r22 ,%r20, %r22 |
| 11474 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 11475 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 11476 | xor %r22 ,%r20, %r22 |
| 11477 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 11478 | wr %r21, %r0, %asi |
| 11479 | ta T_CHANGE_NONHPRIV |
| 11480 | .word 0x29800001 ! 73: FBL fbl,a <label_0x1> |
| 11481 | nop |
| 11482 | mov 0x80, %g3 |
| 11483 | stxa %g3, [%g3] 0x57 |
| 11484 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11485 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 11486 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 11487 | .word 0xe45fc000 ! 74: LDX_R ldx [%r31 + %r0], %r18 |
| 11488 | nop |
| 11489 | ta T_CHANGE_HPRIV |
| 11490 | mov 0x1, %r10 |
| 11491 | set sync_thr_counter6, %r23 |
| 11492 | #ifndef SPC |
| 11493 | ldxa [%g0]0x63, %o1 |
| 11494 | and %o1, 0x38, %o1 |
| 11495 | add %o1, %r23, %r23 |
| 11496 | #endif |
| 11497 | cas [%r23],%g0,%r10 !lock |
| 11498 | brnz %r10, sma_1_52 |
| 11499 | rd %asi, %r12 |
| 11500 | wr %g0, 0x40, %asi |
| 11501 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11502 | set 0x00161fff, %g1 |
| 11503 | stxa %g1, [%g0 + 0x80] %asi |
| 11504 | wr %r12, %g0, %asi |
| 11505 | st %g0, [%r23] |
| 11506 | sma_1_52: |
| 11507 | ta T_CHANGE_NONHPRIV |
| 11508 | .word 0xe5e7e00d ! 75: CASA_R casa [%r31] %asi, %r13, %r18 |
| 11509 | .word 0x91930005 ! 76: WRPR_PIL_R wrpr %r12, %r5, %pil |
| 11510 | pmu_1_54: |
| 11511 | nop |
| 11512 | setx 0xffffffb1ffffffaf, %g1, %g7 |
| 11513 | .word 0xa3800007 ! 77: WR_PERF_COUNTER_R wr %r0, %r7, %- |
| 11514 | fpinit_1_55: |
| 11515 | nop |
| 11516 | setx fp_data_quads, %r19, %r20 |
| 11517 | ldd [%r20], %f0 |
| 11518 | ldd [%r20+8], %f4 |
| 11519 | ld [%r20+16], %fsr |
| 11520 | ld [%r20+24], %r19 |
| 11521 | wr %r19, %g0, %gsr |
| 11522 | .word 0x8da009a4 ! 78: FDIVs fdivs %f0, %f4, %f6 |
| 11523 | jmptr_1_56: |
| 11524 | nop |
| 11525 | best_set_reg(0xe0200000, %r20, %r27) |
| 11526 | .word 0xb7c6c000 ! 79: JMPL_R jmpl %r27 + %r0, %r27 |
| 11527 | nop |
| 11528 | mov 0x80, %g3 |
| 11529 | stxa %g3, [%g3] 0x5f |
| 11530 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 11531 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11532 | .word 0xe45fc000 ! 80: LDX_R ldx [%r31 + %r0], %r18 |
| 11533 | .word 0x97b0c0f4 ! 81: EDGE16LN edge16ln %r3, %r20, %r11 |
| 11534 | #if (defined SPC || defined CMP1) |
| 11535 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_58) + 48, 16, 16)) -> intp(7,0,28,,,,,1) |
| 11536 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_58)&0xffffffff) + 56, 16, 16)) -> intp(2,0,22,,,,,1) |
| 11537 | #else |
| 11538 | set 0x6070da41, %r28 |
| 11539 | #if (MAX_THREADS == 8) |
| 11540 | and %r28, 0x7ff, %r28 |
| 11541 | #endif |
| 11542 | stxa %r28, [%g0] 0x73 |
| 11543 | #endif |
| 11544 | .word 0x97a109d0 ! 1: FDIVd fdivd %f4, %f16, %f42 |
| 11545 | intvec_1_58: |
| 11546 | .word 0xa5a309d4 ! 82: FDIVd fdivd %f12, %f20, %f18 |
| 11547 | nop |
| 11548 | ta T_CHANGE_HPRIV |
| 11549 | mov 0x1, %r10 |
| 11550 | set sync_thr_counter6, %r23 |
| 11551 | #ifndef SPC |
| 11552 | ldxa [%g0]0x63, %o1 |
| 11553 | and %o1, 0x38, %o1 |
| 11554 | add %o1, %r23, %r23 |
| 11555 | #endif |
| 11556 | cas [%r23],%g0,%r10 !lock |
| 11557 | brnz %r10, sma_1_59 |
| 11558 | rd %asi, %r12 |
| 11559 | wr %g0, 0x40, %asi |
| 11560 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11561 | set 0x001a1fff, %g1 |
| 11562 | stxa %g1, [%g0 + 0x80] %asi |
| 11563 | wr %r12, %g0, %asi |
| 11564 | st %g0, [%r23] |
| 11565 | sma_1_59: |
| 11566 | ta T_CHANGE_NONHPRIV |
| 11567 | .word 0xe5e7e00c ! 83: CASA_R casa [%r31] %asi, %r12, %r18 |
| 11568 | fpinit_1_60: |
| 11569 | nop |
| 11570 | setx fp_data_quads, %r19, %r20 |
| 11571 | ldd [%r20], %f0 |
| 11572 | ldd [%r20+8], %f4 |
| 11573 | ld [%r20+16], %fsr |
| 11574 | ld [%r20+24], %r19 |
| 11575 | wr %r19, %g0, %gsr |
| 11576 | .word 0x89a009c4 ! 84: FDIVd fdivd %f0, %f4, %f4 |
| 11577 | .word 0x87802055 ! 85: WRASI_I wr %r0, 0x0055, %asi |
| 11578 | .word 0xc19fdb60 ! 86: LDDFA_R ldda [%r31, %r0], %f0 |
| 11579 | splash_lsu_1_61: |
| 11580 | nop |
| 11581 | ta T_CHANGE_HPRIV |
| 11582 | set 0x3d323ffe, %r2 |
| 11583 | mov 0x4, %r1 |
| 11584 | sllx %r1, 32, %r1 |
| 11585 | or %r1, %r2, %r2 |
| 11586 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11587 | .word 0x3d400001 ! 87: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11588 | splash_lsu_1_62: |
| 11589 | nop |
| 11590 | ta T_CHANGE_HPRIV |
| 11591 | set 0x06827127, %r2 |
| 11592 | mov 0x1, %r1 |
| 11593 | sllx %r1, 32, %r1 |
| 11594 | or %r1, %r2, %r2 |
| 11595 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11596 | ta T_CHANGE_NONHPRIV |
| 11597 | .word 0x3d400001 ! 88: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11598 | splash_cmpr_1_63: |
| 11599 | mov 1, %r18 |
| 11600 | sllx %r18, 63, %r18 |
| 11601 | rd %tick, %r17 |
| 11602 | add %r17, 0x60, %r17 |
| 11603 | or %r17, %r18, %r17 |
| 11604 | ta T_CHANGE_HPRIV |
| 11605 | wrhpr %r17, %g0, %hsys_tick_cmpr |
| 11606 | .word 0xaf800011 ! 89: WR_TICK_CMPR_REG_R wr %r0, %r17, %- |
| 11607 | nop |
| 11608 | mov 0x80, %g3 |
| 11609 | .word 0x30800001 ! 1: BA ba,a <label_0x1> |
| 11610 | stxa %g3, [%g3] 0x5f |
| 11611 | .word 0xe45fc000 ! 90: LDX_R ldx [%r31 + %r0], %r18 |
| 11612 | splash_tba_1_64: |
| 11613 | nop |
| 11614 | ta T_CHANGE_PRIV |
| 11615 | set 0x120000, %r12 |
| 11616 | .word 0x8b90000c ! 91: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 11617 | dvapa_1_65: |
| 11618 | nop |
| 11619 | ta T_CHANGE_HPRIV |
| 11620 | mov 0xa45, %r20 |
| 11621 | mov 0x2, %r19 |
| 11622 | sllx %r20, 23, %r20 |
| 11623 | or %r19, %r20, %r19 |
| 11624 | stxa %r19, [%g0] ASI_LSU_CONTROL |
| 11625 | mov 0x38, %r18 |
| 11626 | stxa %r31, [%r18]0x58 |
| 11627 | ta T_CHANGE_NONHPRIV |
| 11628 | .word 0xe43fe150 ! 92: STD_I std %r18, [%r31 + 0x0150] |
| 11629 | splash_lsu_1_66: |
| 11630 | nop |
| 11631 | ta T_CHANGE_HPRIV |
| 11632 | set 0x50c879f9, %r2 |
| 11633 | mov 0x4, %r1 |
| 11634 | sllx %r1, 32, %r1 |
| 11635 | or %r1, %r2, %r2 |
| 11636 | .word 0x3c800001 ! 1: BPOS bpos,a <label_0x1> |
| 11637 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11638 | ta T_CHANGE_NONHPRIV |
| 11639 | .word 0x3d400001 ! 93: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11640 | ibp_1_67: |
| 11641 | nop |
| 11642 | .word 0xe51fe120 ! 94: LDDF_I ldd [%r31, 0x0120], %f18 |
| 11643 | .word 0xe527c000 ! 95: STF_R st %f18, [%r0, %r31] |
| 11644 | nop |
| 11645 | ta T_CHANGE_HPRIV |
| 11646 | mov 0x1, %r10 |
| 11647 | set sync_thr_counter6, %r23 |
| 11648 | #ifndef SPC |
| 11649 | ldxa [%g0]0x63, %o1 |
| 11650 | and %o1, 0x38, %o1 |
| 11651 | add %o1, %r23, %r23 |
| 11652 | #endif |
| 11653 | cas [%r23],%g0,%r10 !lock |
| 11654 | brnz %r10, sma_1_68 |
| 11655 | rd %asi, %r12 |
| 11656 | wr %g0, 0x40, %asi |
| 11657 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11658 | set 0x001a1fff, %g1 |
| 11659 | stxa %g1, [%g0 + 0x80] %asi |
| 11660 | wr %r12, %g0, %asi |
| 11661 | st %g0, [%r23] |
| 11662 | sma_1_68: |
| 11663 | ta T_CHANGE_NONHPRIV |
| 11664 | .word 0xe5e7e00d ! 96: CASA_R casa [%r31] %asi, %r13, %r18 |
| 11665 | #if (defined SPC || defined CMP) |
| 11666 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_1_69)+0, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11667 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_1_69)&0xffffffff) + 48, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11668 | xir_1_69: |
| 11669 | #else |
| 11670 | #if (defined FC) |
| 11671 | !! Generate XIR via RESET_GEN register |
| 11672 | ta T_CHANGE_HPRIV |
| 11673 | rdpr %pstate, %r18 |
| 11674 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 11675 | wrpr %r18, %pstate |
| 11676 | #ifndef XIR_RND_CORES |
| 11677 | ldxa [%g0] 0x63, %o1 |
| 11678 | mov 1, %r18 |
| 11679 | sllx %r18, %o1, %r18 |
| 11680 | #endif |
| 11681 | mov 0x30, %r19 |
| 11682 | setx 0x8900000808, %r16, %r17 |
| 11683 | mov 0x2, %r16 |
| 11684 | xir_1_69: |
| 11685 | stxa %r18, [%r19] 0x41 |
| 11686 | stx %r16, [%r17] |
| 11687 | #endif |
| 11688 | #endif |
| 11689 | .word 0xa9822444 ! 97: WR_SET_SOFTINT_I wr %r8, 0x0444, %set_softint |
| 11690 | #if (defined SPC || defined CMP1) |
| 11691 | !$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_70) + 8, 16, 16)) -> intp(3,0,3,,,,,1) |
| 11692 | !$EV trig_pc_d(1, expr((@VA(.MAIN.intvec_1_70)&0xffffffff) + 8, 16, 16)) -> intp(3,0,25,,,,,1) |
| 11693 | #else |
| 11694 | set 0x3a00b98e, %r28 |
| 11695 | #if (MAX_THREADS == 8) |
| 11696 | and %r28, 0x7ff, %r28 |
| 11697 | #endif |
| 11698 | stxa %r28, [%g0] 0x73 |
| 11699 | #endif |
| 11700 | intvec_1_70: |
| 11701 | .word 0x39400001 ! 98: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 11702 | fpinit_1_71: |
| 11703 | nop |
| 11704 | setx fp_data_quads, %r19, %r20 |
| 11705 | ldd [%r20], %f0 |
| 11706 | ldd [%r20+8], %f4 |
| 11707 | ld [%r20+16], %fsr |
| 11708 | ld [%r20+24], %r19 |
| 11709 | wr %r19, %g0, %gsr |
| 11710 | .word 0x87a80a44 ! 99: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 11711 | splash_lsu_1_72: |
| 11712 | nop |
| 11713 | ta T_CHANGE_HPRIV |
| 11714 | set 0x50bd6621, %r2 |
| 11715 | mov 0x7, %r1 |
| 11716 | sllx %r1, 32, %r1 |
| 11717 | or %r1, %r2, %r2 |
| 11718 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11719 | .word 0x3d400001 ! 100: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11720 | .word 0x97b100e5 ! 101: EDGE16LN edge16ln %r4, %r5, %r11 |
| 11721 | nop |
| 11722 | ta T_CHANGE_HPRIV |
| 11723 | mov 0x1, %r10 |
| 11724 | set sync_thr_counter6, %r23 |
| 11725 | #ifndef SPC |
| 11726 | ldxa [%g0]0x63, %o1 |
| 11727 | and %o1, 0x38, %o1 |
| 11728 | add %o1, %r23, %r23 |
| 11729 | #endif |
| 11730 | cas [%r23],%g0,%r10 !lock |
| 11731 | brnz %r10, sma_1_74 |
| 11732 | rd %asi, %r12 |
| 11733 | wr %g0, 0x40, %asi |
| 11734 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 11735 | set 0x00121fff, %g1 |
| 11736 | stxa %g1, [%g0 + 0x80] %asi |
| 11737 | wr %r12, %g0, %asi |
| 11738 | st %g0, [%r23] |
| 11739 | sma_1_74: |
| 11740 | ta T_CHANGE_NONHPRIV |
| 11741 | .word 0xd7e7e00b ! 102: CASA_R casa [%r31] %asi, %r11, %r11 |
| 11742 | nop |
| 11743 | mov 0x80, %g3 |
| 11744 | .word 0x21400001 ! 1: FBPN fbn,a,pn %fcc0, <label_0x1> |
| 11745 | stxa %g3, [%g3] 0x5f |
| 11746 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11747 | .word 0xd65fc000 ! 103: LDX_R ldx [%r31 + %r0], %r11 |
| 11748 | invtsb_1_75: |
| 11749 | nop |
| 11750 | ta T_CHANGE_HPRIV |
| 11751 | rd %asi, %r21 |
| 11752 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 11753 | mov 1, %r20 |
| 11754 | sllx %r20, 63, %r20 |
| 11755 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 11756 | xor %r22 ,%r20, %r22 |
| 11757 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 11758 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 11759 | xor %r22 ,%r20, %r22 |
| 11760 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 11761 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 11762 | xor %r22 ,%r20, %r22 |
| 11763 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 11764 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 11765 | xor %r22 ,%r20, %r22 |
| 11766 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 11767 | wr %r21, %r0, %asi |
| 11768 | ta T_CHANGE_NONHPRIV |
| 11769 | .word 0x29800001 ! 104: FBL fbl,a <label_0x1> |
| 11770 | .word 0xe19fe0e0 ! 105: LDDFA_I ldda [%r31, 0x00e0], %f16 |
| 11771 | splash_lsu_1_77: |
| 11772 | nop |
| 11773 | ta T_CHANGE_HPRIV |
| 11774 | set 0x3f9d9c6d, %r2 |
| 11775 | mov 0x6, %r1 |
| 11776 | sllx %r1, 32, %r1 |
| 11777 | or %r1, %r2, %r2 |
| 11778 | .word 0x3e800001 ! 1: BVC bvc,a <label_0x1> |
| 11779 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11780 | .word 0x3d400001 ! 106: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11781 | .word 0xc1bfda00 ! 107: STDFA_R stda %f0, [%r0, %r31] |
| 11782 | .word 0x91940007 ! 108: WRPR_PIL_R wrpr %r16, %r7, %pil |
| 11783 | splash_lsu_1_79: |
| 11784 | nop |
| 11785 | ta T_CHANGE_HPRIV |
| 11786 | set 0x30003bcb, %r2 |
| 11787 | mov 0x4, %r1 |
| 11788 | sllx %r1, 32, %r1 |
| 11789 | or %r1, %r2, %r2 |
| 11790 | .word 0x2cccc001 ! 1: BRGZ brgz,a,pt %r19,<label_0xcc001> |
| 11791 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 11792 | .word 0x3d400001 ! 109: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 11793 | .word 0xe1bfc2c0 ! 110: STDFA_R stda %f16, [%r0, %r31] |
| 11794 | .word 0x39400001 ! 111: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 11795 | .word 0xe1bfd960 ! 112: STDFA_R stda %f16, [%r0, %r31] |
| 11796 | rd %tick, %r28 |
| 11797 | #if (MAX_THREADS == 8) |
| 11798 | sethi %hi(0x33800), %r27 |
| 11799 | #else |
| 11800 | sethi %hi(0x30000), %r27 |
| 11801 | #endif |
| 11802 | andn %r28, %r27, %r28 |
| 11803 | ta T_CHANGE_HPRIV |
| 11804 | stxa %r28, [%g0] 0x73 |
| 11805 | intvec_1_81: |
| 11806 | .word 0x39400001 ! 113: FBPUGE fbuge,a,pn %fcc0, <label_0x1> |
| 11807 | .word 0xe1bfe1c0 ! 114: STDFA_I stda %f16, [0x01c0, %r31] |
| 11808 | nop |
| 11809 | mov 0x80, %g3 |
| 11810 | .word 0x3f400001 ! 1: FBPO fbo,a,pn %fcc0, <label_0x1> |
| 11811 | stxa %g3, [%g3] 0x57 |
| 11812 | .word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31 |
| 11813 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11814 | .word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate |
| 11815 | .word 0xe65fc000 ! 115: LDX_R ldx [%r31 + %r0], %r19 |
| 11816 | jmptr_1_82: |
| 11817 | nop |
| 11818 | best_set_reg(0xe0200000, %r20, %r27) |
| 11819 | .word 0xb7c6c000 ! 116: JMPL_R jmpl %r27 + %r0, %r27 |
| 11820 | splash_tba_1_83: |
| 11821 | nop |
| 11822 | ta T_CHANGE_PRIV |
| 11823 | setx 0x0000000000380000, %r11, %r12 |
| 11824 | .word 0x8b90000c ! 117: WRPR_TBA_R wrpr %r0, %r12, %tba |
| 11825 | .word 0x9190c00d ! 118: WRPR_PIL_R wrpr %r3, %r13, %pil |
| 11826 | #if (defined SPC || defined CMP) |
| 11827 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_1_85)+40, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11828 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_1_85)&0xffffffff) + 40, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11829 | xir_1_85: |
| 11830 | #else |
| 11831 | #if (defined FC) |
| 11832 | !! Generate XIR via RESET_GEN register |
| 11833 | ta T_CHANGE_HPRIV |
| 11834 | rdpr %pstate, %r18 |
| 11835 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 11836 | wrpr %r18, %pstate |
| 11837 | #ifndef XIR_RND_CORES |
| 11838 | ldxa [%g0] 0x63, %o1 |
| 11839 | mov 1, %r18 |
| 11840 | sllx %r18, %o1, %r18 |
| 11841 | #endif |
| 11842 | mov 0x30, %r19 |
| 11843 | setx 0x8900000808, %r16, %r17 |
| 11844 | mov 0x2, %r16 |
| 11845 | xir_1_85: |
| 11846 | stxa %r18, [%r19] 0x41 |
| 11847 | stx %r16, [%r17] |
| 11848 | #endif |
| 11849 | #endif |
| 11850 | .word 0xa981624f ! 119: WR_SET_SOFTINT_I wr %r5, 0x024f, %set_softint |
| 11851 | cwp_1_86: |
| 11852 | set user_data_start, %o7 |
| 11853 | .word 0x93902000 ! 120: WRPR_CWP_I wrpr %r0, 0x0000, %cwp |
| 11854 | nop |
| 11855 | mov 0x80, %g3 |
| 11856 | stxa %g3, [%g3] 0x57 |
| 11857 | .word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31 |
| 11858 | .word 0xe65fc000 ! 121: LDX_R ldx [%r31 + %r0], %r19 |
| 11859 | nop |
| 11860 | ta T_CHANGE_HPRIV ! macro |
| 11861 | donret_1_87: |
| 11862 | rd %pc, %r12 |
| 11863 | mov HIGHVA_HIGHNUM, %r10 |
| 11864 | sllx %r10, 32, %r10 |
| 11865 | or %r12, %r10, %r12 |
| 11866 | add %r12, (donretarg_1_87-donret_1_87), %r12 |
| 11867 | add %r12, 0x4, %r11 ! seq tnpc |
| 11868 | andn %r11, %r10, %r11 ! low VA tnpc |
| 11869 | wrpr %g0, 0x1, %tl |
| 11870 | wrpr %g0, %r12, %tpc |
| 11871 | wrpr %g0, %r11, %tnpc |
| 11872 | set (0x008c7200 | (28 << 24)), %r13 |
| 11873 | and %r12, 0xfff, %r14 |
| 11874 | sllx %r14, 32, %r14 |
| 11875 | or %r13, %r14, %r20 |
| 11876 | wrpr %r20, %g0, %tstate |
| 11877 | wrhpr %g0, 0x1495, %htstate |
| 11878 | ta T_CHANGE_NONPRIV ! rand=0 (1) |
| 11879 | ldx [%r11+%r0], %g1 |
| 11880 | done |
| 11881 | donretarg_1_87: |
| 11882 | .word 0xe66fe0ed ! 122: LDSTUB_I ldstub %r19, [%r31 + 0x00ed] |
| 11883 | invtsb_1_88: |
| 11884 | nop |
| 11885 | ta T_CHANGE_HPRIV |
| 11886 | rd %asi, %r21 |
| 11887 | wr %r0,ASI_MMU_REAL_RANGE, %asi |
| 11888 | mov 1, %r20 |
| 11889 | sllx %r20, 63, %r20 |
| 11890 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %r22 |
| 11891 | xor %r22 ,%r20, %r22 |
| 11892 | stxa %r22, [ASI_MMU_REAL_RANGE_0] %asi |
| 11893 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %r22 |
| 11894 | xor %r22 ,%r20, %r22 |
| 11895 | stxa %r22, [ASI_MMU_REAL_RANGE_1] %asi |
| 11896 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %r22 |
| 11897 | xor %r22 ,%r20, %r22 |
| 11898 | stxa %r22, [ASI_MMU_REAL_RANGE_2] %asi |
| 11899 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %r22 |
| 11900 | xor %r22 ,%r20, %r22 |
| 11901 | stxa %r22, [ASI_MMU_REAL_RANGE_3] %asi |
| 11902 | wr %r21, %r0, %asi |
| 11903 | ta T_CHANGE_NONHPRIV |
| 11904 | .word 0x29800001 ! 123: FBL fbl,a <label_0x1> |
| 11905 | .word 0xa945c000 ! 124: RD_TICK_CMPR_REG rd %-, %r20 |
| 11906 | .word 0xc19fc2c0 ! 125: LDDFA_R ldda [%r31, %r0], %f0 |
| 11907 | nop |
| 11908 | ta T_CHANGE_HPRIV |
| 11909 | mov 0x1+1, %r10 |
| 11910 | set sync_thr_counter5, %r23 |
| 11911 | #ifndef SPC |
| 11912 | ldxa [%g0]0x63, %o1 |
| 11913 | and %o1, 0x38, %o1 |
| 11914 | add %o1, %r23, %r23 |
| 11915 | sllx %o1, 5, %o3 !(CID*256) |
| 11916 | #endif |
| 11917 | cas [%r23],%g0,%r10 !lock |
| 11918 | brnz %r10, cwq_1_89 |
| 11919 | rd %asi, %r12 |
| 11920 | wr %g0, 0x40, %asi |
| 11921 | ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1 |
| 11922 | and %l1, 0x3, %l1 ! Check if busy/enabled .. |
| 11923 | cmp %l1, 1 |
| 11924 | bne cwq_1_89 |
| 11925 | set CWQ_BASE, %l6 |
| 11926 | #ifndef SPC |
| 11927 | add %l6, %o3, %l6 |
| 11928 | #endif |
| 11929 | stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi |
| 11930 | best_set_reg(0x206100c0, %l1, %l2) !# Control Word |
| 11931 | sllx %l2, 32, %l2 |
| 11932 | stx %l2, [%l6 + 0x0] |
| 11933 | membar #Sync |
| 11934 | ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2 |
| 11935 | sub %l2, 0x40, %l2 |
| 11936 | stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi |
| 11937 | wr %r12, %g0, %asi |
| 11938 | st %g0, [%r23] |
| 11939 | cwq_1_89: |
| 11940 | ta T_CHANGE_NONHPRIV |
| 11941 | .word 0xa9414000 ! 126: RDPC rd %pc, %r20 |
| 11942 | .word 0xa3a00172 ! 127: FABSq dis not found |
| 11943 | |
| 11944 | #if (defined SPC || defined CMP) |
| 11945 | !$EV trig_pc_d(1, expr(@VA(.MAIN.xir_1_91)+0, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11946 | !$EV trig_pc_d(1, expr((@VA(.MAIN.xir_1_91)&0xffffffff) + 24, 16, 16)) -> intp(mask2tid(0x1),1,3,,,,,1) |
| 11947 | xir_1_91: |
| 11948 | #else |
| 11949 | #if (defined FC) |
| 11950 | !! Generate XIR via RESET_GEN register |
| 11951 | ta T_CHANGE_HPRIV |
| 11952 | rdpr %pstate, %r18 |
| 11953 | andn %r18, 0x208, %r18 ! Reset pstate.am,cle |
| 11954 | wrpr %r18, %pstate |
| 11955 | #ifndef XIR_RND_CORES |
| 11956 | ldxa [%g0] 0x63, %o1 |
| 11957 | mov 1, %r18 |
| 11958 | sllx %r18, %o1, %r18 |
| 11959 | #endif |
| 11960 | mov 0x30, %r19 |
| 11961 | setx 0x8900000808, %r16, %r17 |
| 11962 | mov 0x2, %r16 |
| 11963 | xir_1_91: |
| 11964 | stxa %r18, [%r19] 0x41 |
| 11965 | stx %r16, [%r17] |
| 11966 | #endif |
| 11967 | #endif |
| 11968 | .word 0xa984e2ab ! 128: WR_SET_SOFTINT_I wr %r19, 0x02ab, %set_softint |
| 11969 | memptr_1_92: |
| 11970 | set 0x60140000, %r31 |
| 11971 | .word 0x85817d21 ! 129: WRCCR_I wr %r5, 0x1d21, %ccr |
| 11972 | rd %tick, %r28 |
| 11973 | #if (MAX_THREADS == 8) |
| 11974 | sethi %hi(0x33800), %r27 |
| 11975 | #else |
| 11976 | sethi %hi(0x30000), %r27 |
| 11977 | #endif |
| 11978 | andn %r28, %r27, %r28 |
| 11979 | ta T_CHANGE_HPRIV |
| 11980 | stxa %r28, [%g0] 0x73 |
| 11981 | intvec_1_93: |
| 11982 | .word 0x9f8024bb ! 130: SIR sir 0x04bb |
| 11983 | .word 0x89800011 ! 131: WRTICK_R wr %r0, %r17, %tick |
| 11984 | memptr_1_95: |
| 11985 | set 0x60340000, %r31 |
| 11986 | .word 0x8584ab62 ! 132: WRCCR_I wr %r18, 0x0b62, %ccr |
| 11987 | splash_hpstate_1_96: |
| 11988 | .word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1> |
| 11989 | .word 0x81983cc8 ! 133: WRHPR_HPSTATE_I wrhpr %r0, 0x1cc8, %hpstate |
| 11990 | jmptr_1_97: |
| 11991 | nop |
| 11992 | best_set_reg(0xe0200000, %r20, %r27) |
| 11993 | .word 0xb7c6c000 ! 134: JMPL_R jmpl %r27 + %r0, %r27 |
| 11994 | .word 0xd23fc000 ! 135: STD_R std %r9, [%r31 + %r0] |
| 11995 | .word 0x8d903d91 ! 136: WRPR_PSTATE_I wrpr %r0, 0x1d91, %pstate |
| 11996 | .word 0xa1a00172 ! 137: FABSq dis not found |
| 11997 | |
| 11998 | nop |
| 11999 | ta T_CHANGE_HPRIV |
| 12000 | mov 0x1, %r10 |
| 12001 | set sync_thr_counter6, %r23 |
| 12002 | #ifndef SPC |
| 12003 | ldxa [%g0]0x63, %o1 |
| 12004 | and %o1, 0x38, %o1 |
| 12005 | add %o1, %r23, %r23 |
| 12006 | #endif |
| 12007 | cas [%r23],%g0,%r10 !lock |
| 12008 | brnz %r10, sma_1_101 |
| 12009 | rd %asi, %r12 |
| 12010 | wr %g0, 0x40, %asi |
| 12011 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 12012 | set 0x00121fff, %g1 |
| 12013 | stxa %g1, [%g0 + 0x80] %asi |
| 12014 | wr %r12, %g0, %asi |
| 12015 | st %g0, [%r23] |
| 12016 | sma_1_101: |
| 12017 | ta T_CHANGE_NONHPRIV |
| 12018 | .word 0xe1e7e00b ! 138: CASA_R casa [%r31] %asi, %r11, %r16 |
| 12019 | .word 0x95b500e5 ! 139: EDGE16LN edge16ln %r20, %r5, %r10 |
| 12020 | splash_lsu_1_103: |
| 12021 | nop |
| 12022 | ta T_CHANGE_HPRIV |
| 12023 | set 0x9ad0ae4e, %r2 |
| 12024 | mov 0x7, %r1 |
| 12025 | sllx %r1, 32, %r1 |
| 12026 | or %r1, %r2, %r2 |
| 12027 | .word 0x38800001 ! 1: BGU bgu,a <label_0x1> |
| 12028 | stxa %r2, [%r0] ASI_LSU_CONTROL |
| 12029 | .word 0x3d400001 ! 140: FBPULE fbule,a,pn %fcc0, <label_0x1> |
| 12030 | .word 0x91688004 ! 141: SDIVX_R sdivx %r2, %r4, %r8 |
| 12031 | .word 0xe19fe0e0 ! 142: LDDFA_I ldda [%r31, 0x00e0], %f16 |
| 12032 | .word 0x9190c013 ! 143: WRPR_PIL_R wrpr %r3, %r19, %pil |
| 12033 | splash_hpstate_1_105: |
| 12034 | ta T_CHANGE_NONHPRIV |
| 12035 | .word 0x8198355d ! 144: WRHPR_HPSTATE_I wrhpr %r0, 0x155d, %hpstate |
| 12036 | .word 0x89800011 ! 145: WRTICK_R wr %r0, %r17, %tick |
| 12037 | nop |
| 12038 | ta T_CHANGE_HPRIV |
| 12039 | mov 0x1, %r10 |
| 12040 | set sync_thr_counter6, %r23 |
| 12041 | #ifndef SPC |
| 12042 | ldxa [%g0]0x63, %o1 |
| 12043 | and %o1, 0x38, %o1 |
| 12044 | add %o1, %r23, %r23 |
| 12045 | #endif |
| 12046 | cas [%r23],%g0,%r10 !lock |
| 12047 | brnz %r10, sma_1_107 |
| 12048 | rd %asi, %r12 |
| 12049 | wr %g0, 0x40, %asi |
| 12050 | ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0 |
| 12051 | set 0x000e1fff, %g1 |
| 12052 | stxa %g1, [%g0 + 0x80] %asi |
| 12053 | wr %r12, %g0, %asi |
| 12054 | st %g0, [%r23] |
| 12055 | sma_1_107: |
| 12056 | ta T_CHANGE_NONHPRIV |
| 12057 | .word 0xd1e7e014 ! 146: CASA_R casa [%r31] %asi, %r20, %r8 |
| 12058 | fpinit_1_108: |
| 12059 | nop |
| 12060 | setx fp_data_quads, %r19, %r20 |
| 12061 | ldd [%r20], %f0 |
| 12062 | ldd [%r20+8], %f4 |
| 12063 | ld [%r20+16], %fsr |
| 12064 | ld [%r20+24], %r19 |
| 12065 | wr %r19, %g0, %gsr |
| 12066 | .word 0x87a80a44 ! 147: FCMPd fcmpd %fcc<n>, %f0, %f4 |
| 12067 | intveclr_1_109: |
| 12068 | nop |
| 12069 | ta T_CHANGE_HPRIV |
| 12070 | setx 0xe2a00a3be4aedb34, %r1, %r28 |
| 12071 | stxa %r28, [%g0] 0x72 |
| 12072 | ta T_CHANGE_NONHPRIV |
| 12073 | .word 0x25400001 ! 148: FBPLG fblg,a,pn %fcc0, <label_0x1> |
| 12074 | brcommon3_1_110: |
| 12075 | nop |
| 12076 | setx common_target, %r12, %r27 |
| 12077 | lduw [%r27], %r12 ! Load common dest into dcache .. |
| 12078 | ba,a .+12 |
| 12079 | .word 0xd06fe0a0 ! 1: LDSTUB_I ldstub %r8, [%r31 + 0x00a0] |
| 12080 | ba,a .+8 |
| 12081 | jmpl %r27+0, %r27 |
| 12082 | .word 0xd0dfc033 ! 149: LDXA_R ldxa [%r31, %r19] 0x01, %r8 |
| 12083 | .word 0x2c800001 ! 1: BNEG bneg,a <label_0x1> |
| 12084 | .word 0x8d9025a2 ! 150: WRPR_PSTATE_I wrpr %r0, 0x05a2, %pstate |
| 12085 | nop |
| 12086 | nop |
| 12087 | ta T_CHANGE_PRIV |
| 12088 | wrpr %g0, %g0, %gl |
| 12089 | nop |
| 12090 | nop |
| 12091 | |
| 12092 | join_lbl_0_0: |
| 12093 | SECTION .MAIN |
| 12094 | .text |
| 12095 | diag_finish: |
| 12096 | nop |
| 12097 | nop |
| 12098 | nop |
| 12099 | ta T_CHANGE_HPRIV |
| 12100 | #if (MULTIPASS > 0) |
| 12101 | multipass_check: |
| 12102 | rd %asi, %r12 |
| 12103 | wr %g0, ASI_SCRATCHPAD, %asi |
| 12104 | ldxa [0x38]%asi, %r10 |
| 12105 | cmp %r10, MULTIPASS |
| 12106 | inc %r10 |
| 12107 | stxa %r10, [0x38]%asi |
| 12108 | wr %g0, %r12, %asi |
| 12109 | bne fork_threads |
| 12110 | wrpr %g0, %g0, %gl |
| 12111 | #endif |
| 12112 | finish_diag: |
| 12113 | best_set_reg(HV_TRAP_BASE_PA, %r1, %r2) |
| 12114 | wrhpr %g2, %g0, %htba |
| 12115 | ta T_GOOD_TRAP |
| 12116 | nop |
| 12117 | nop |
| 12118 | nop |
| 12119 | .data |
| 12120 | .xword 0x0 |
| 12121 | ! fp data rs1, rs2, fsr, gsr quads .. |
| 12122 | .global fp_data_quads |
| 12123 | fp_data_quads: |
| 12124 | .xword 0x0044000000000000 |
| 12125 | .xword 0x4028000000000000 |
| 12126 | .xword 0x0fc0400400000000 |
| 12127 | .xword 0x0000000000000000 |
| 12128 | .xword 0x0041000000000000 |
| 12129 | .xword 0x4022000000000000 |
| 12130 | .xword 0x0600800000000000 |
| 12131 | .xword 0x0000000000000000 |
| 12132 | .xword 0x0220000000000000 |
| 12133 | .xword 0x4140000000000000 |
| 12134 | .xword 0x4fc0400400000000 |
| 12135 | .xword 0x0000000000000000 |
| 12136 | .xword 0x4090000000000000 |
| 12137 | .xword 0x0090000000000000 |
| 12138 | .xword 0x0f80400800000000 |
| 12139 | .xword 0x0a00000000000000 |
| 12140 | .align 128 |
| 12141 | .global user_data_start |
| 12142 | .data |
| 12143 | user_data_start: |
| 12144 | |
| 12145 | .xword 0x1a9fcdbccb744441 |
| 12146 | .xword 0x4923ec55eedfcf9f |
| 12147 | .xword 0xfbbb08c72ed164de |
| 12148 | .xword 0x20429ff47e90168b |
| 12149 | .xword 0x3886d3e2a255a739 |
| 12150 | .xword 0xaf23ee6397c7b60d |
| 12151 | .xword 0xa476b6763a3c0ce8 |
| 12152 | .xword 0xe0cd8702efe7b278 |
| 12153 | .xword 0x163b56ed2d12f839 |
| 12154 | .xword 0x5a2edf8d3dfea00d |
| 12155 | .xword 0x1ee8424a2171d871 |
| 12156 | .xword 0xe18b417eb294bd0b |
| 12157 | .xword 0xa5347aac98e5fe0a |
| 12158 | .xword 0x11afac6c3cb2aa9c |
| 12159 | .xword 0x507b636e47637eef |
| 12160 | .xword 0xcc378d0384f0c06e |
| 12161 | .xword 0xc5debcfb70fbd82d |
| 12162 | .xword 0x849d586ba730fab6 |
| 12163 | .xword 0x8a300f33efaac39b |
| 12164 | .xword 0x2270a2ed622d0b32 |
| 12165 | .xword 0x371510847a4a61f0 |
| 12166 | .xword 0xd624f896339d6ead |
| 12167 | .xword 0x6c1353f2cfb2fa2d |
| 12168 | .xword 0x95860f0799cf27bf |
| 12169 | .xword 0xd8b3baa08b005259 |
| 12170 | .xword 0x8e0ed9532e7e1c93 |
| 12171 | .xword 0xc3cb7add8bade322 |
| 12172 | .xword 0x253fe33f260f8b77 |
| 12173 | .xword 0x7a49492329de07ac |
| 12174 | .xword 0xd272e2796796129b |
| 12175 | .xword 0x6dfd521b71914b68 |
| 12176 | .xword 0xf2175d942d7baf8d |
| 12177 | .xword 0xbe09c31f44ac6683 |
| 12178 | .xword 0xff70d6ae04648ec9 |
| 12179 | .xword 0xc1348b7b4c451d02 |
| 12180 | .xword 0x3980c6605e45e8e5 |
| 12181 | .xword 0x300fe8eb12825f99 |
| 12182 | .xword 0x5ca6345e393cf75e |
| 12183 | .xword 0x7313b928b19f7ba3 |
| 12184 | .xword 0x155a447046672759 |
| 12185 | .xword 0xaeb3ec1eb07339e2 |
| 12186 | .xword 0xd685ead0b7e368e0 |
| 12187 | .xword 0x14f2a13b1e2c3ffd |
| 12188 | .xword 0x582fd1fa2b468f64 |
| 12189 | .xword 0x80e09d5e6cf80b0c |
| 12190 | .xword 0x53856a0145ce5e8b |
| 12191 | .xword 0x585a51b852eae910 |
| 12192 | .xword 0x8de40adac185235e |
| 12193 | .xword 0xc27142ae74249342 |
| 12194 | .xword 0x38d07e6bd85419ae |
| 12195 | .xword 0x5cd170af657eeeae |
| 12196 | .xword 0xdd8aaea13e2c253e |
| 12197 | .xword 0x230472994e6100da |
| 12198 | .xword 0x4fdc3ec62f93316e |
| 12199 | .xword 0xa4a643de54360d84 |
| 12200 | .xword 0x3c4e28f572c27383 |
| 12201 | .xword 0xfb80b2175556c750 |
| 12202 | .xword 0x98028e49b524ecd2 |
| 12203 | .xword 0x047178845ad7fa94 |
| 12204 | .xword 0xf57bb7da5032c59a |
| 12205 | .xword 0x03683a0f63254881 |
| 12206 | .xword 0xff3aa9d32d5a45d4 |
| 12207 | .xword 0xb87427630f48b0da |
| 12208 | .xword 0xbb7345ece1b3e5ed |
| 12209 | .xword 0xcc478d30b2917c7b |
| 12210 | .xword 0xaec8accaff9deac2 |
| 12211 | .xword 0xf5f3efbcbc642a97 |
| 12212 | .xword 0x444f0378fc3de47c |
| 12213 | .xword 0xf7c261549401ce9c |
| 12214 | .xword 0xbd1a7499846e062d |
| 12215 | .xword 0xbdcf09f4b6224bca |
| 12216 | .xword 0xa27b81769dde4a32 |
| 12217 | .xword 0xafcf9b3372281cc4 |
| 12218 | .xword 0x2705923e3642b9ab |
| 12219 | .xword 0xb33e8f44604d794d |
| 12220 | .xword 0x4fd3a51767a1d76b |
| 12221 | .xword 0x8ed43fb339f085b7 |
| 12222 | .xword 0xf5eb37c6f8d94a78 |
| 12223 | .xword 0xdb8a4c77679f0f3d |
| 12224 | .xword 0x6a0b94d4ebe4093b |
| 12225 | .xword 0xab66fa80d966c67c |
| 12226 | .xword 0xbbbb1a058cee7376 |
| 12227 | .xword 0x15397cd2012f4031 |
| 12228 | .xword 0x32e9a6a5b2be349f |
| 12229 | .xword 0x21f6adf329db1d89 |
| 12230 | .xword 0xc3c1827b0add6772 |
| 12231 | .xword 0xde504da7578ca5ac |
| 12232 | .xword 0xa370e072b23e1ee3 |
| 12233 | .xword 0xfc76a2690e04fdb7 |
| 12234 | .xword 0x577a4e6fc826009c |
| 12235 | .xword 0x15619b7f12f184fd |
| 12236 | .xword 0x35dffc70c560d787 |
| 12237 | .xword 0x3310bc007c2b5884 |
| 12238 | .xword 0x606e9f12a60954e1 |
| 12239 | .xword 0xacca9430b06be826 |
| 12240 | .xword 0xf55b4acd5cecd641 |
| 12241 | .xword 0x90e240d1947832fa |
| 12242 | .xword 0x41d24ae881d27473 |
| 12243 | .xword 0xe77b90997e64f1cf |
| 12244 | .xword 0x8ca17084ecb9427e |
| 12245 | .xword 0x6cfbe9e942e92e44 |
| 12246 | .xword 0xf00b2429c6870d29 |
| 12247 | .xword 0xc6137efef07cd453 |
| 12248 | .xword 0xd0e3a8474c37c07d |
| 12249 | .xword 0x78a8e9533350b669 |
| 12250 | .xword 0x4d34befee1fbb684 |
| 12251 | .xword 0xd98ff30c3cef51ca |
| 12252 | .xword 0xcf45ae3249ed6df9 |
| 12253 | .xword 0x0c65e29d5175c334 |
| 12254 | .xword 0x560f855a159bb5e3 |
| 12255 | .xword 0x2d80d9126ad50bc3 |
| 12256 | .xword 0xc66377d65035c67f |
| 12257 | .xword 0x9439dc10104d63e3 |
| 12258 | .xword 0x96d9a6068f140e7b |
| 12259 | .xword 0xed129f7f68c9202d |
| 12260 | .xword 0x1aecd029290d3242 |
| 12261 | .xword 0x21493c12bd397904 |
| 12262 | .xword 0x3c2bf43b88776a11 |
| 12263 | .xword 0x32d286731926ca92 |
| 12264 | .xword 0x656f7c332c5eb998 |
| 12265 | .xword 0xebfdcc8db1d5a241 |
| 12266 | .xword 0x578746b1413100d5 |
| 12267 | .xword 0x0e0b5015c4c89e77 |
| 12268 | .xword 0xffac5848f6408a16 |
| 12269 | .xword 0xe166aac10cefca43 |
| 12270 | .xword 0x3d2e43fbd2df2738 |
| 12271 | .xword 0xe16c6956e071be15 |
| 12272 | .xword 0xb78a8ef9a05aed4b |
| 12273 | .xword 0x46940738e1bfdca4 |
| 12274 | .xword 0x98017aab9a76376e |
| 12275 | .xword 0xf7f3ef35c97f0257 |
| 12276 | .xword 0x851ee65f3d1285ad |
| 12277 | .xword 0xe84a1a235249bd73 |
| 12278 | .xword 0x0e37f98e22d4c4c3 |
| 12279 | .xword 0xd905e6e46f445cf9 |
| 12280 | .xword 0xcd2b79e26e0e5b6b |
| 12281 | .xword 0x9da676bdf94862f2 |
| 12282 | .xword 0x3c08a7bb5f169110 |
| 12283 | .xword 0x9de8d6a4bc02ddac |
| 12284 | .xword 0xbfb5f5862ad0b44e |
| 12285 | .xword 0x420c290d8fae585a |
| 12286 | .xword 0x5f709cda70c260d3 |
| 12287 | .xword 0x7752c2d97bc67b23 |
| 12288 | .xword 0xd8e1c095ea66e49e |
| 12289 | .xword 0x8e6c3211e1f34e61 |
| 12290 | .xword 0x2b8aa7367442a711 |
| 12291 | .xword 0x4e7108f695e5e57c |
| 12292 | .xword 0x0e8289117267293a |
| 12293 | .xword 0xc1d058a0aa576d09 |
| 12294 | .xword 0xe2c849885d09d9c0 |
| 12295 | .xword 0xed65b0e3c444e7ec |
| 12296 | .xword 0x6555ce37eb921ee7 |
| 12297 | .xword 0xc7048648605820a4 |
| 12298 | .xword 0x8b0b3eb51aab99d0 |
| 12299 | .xword 0x5b3cd6f26e730a53 |
| 12300 | .xword 0x14f3cd7ccad05ab7 |
| 12301 | .xword 0x52118e647416b63b |
| 12302 | .xword 0x19e8e2ea0333398c |
| 12303 | .xword 0x95e93de286eea266 |
| 12304 | .xword 0x3c28d5baaeebd835 |
| 12305 | .xword 0x2b256ec247ce638d |
| 12306 | .xword 0xbf19167401a1de1e |
| 12307 | .xword 0x69a60f814a665b95 |
| 12308 | .xword 0x17f08f9af05e8f00 |
| 12309 | .xword 0x3589078da5c7fdfb |
| 12310 | .xword 0xf8d254ae3bb304f3 |
| 12311 | .xword 0xf0b43cab159b815c |
| 12312 | .xword 0x9a9c2681c62f6bd9 |
| 12313 | .xword 0x959c40fdee70c7d6 |
| 12314 | .xword 0x8d49bdd2e798b205 |
| 12315 | .xword 0x059cd24b354ba281 |
| 12316 | .xword 0x328a90b2948c9323 |
| 12317 | .xword 0x299a87834a1027d0 |
| 12318 | .xword 0x06ad35655f229098 |
| 12319 | .xword 0xb884b15c07f1a436 |
| 12320 | .xword 0xa88ed2b8154a181d |
| 12321 | .xword 0x4cdbe53550fc4850 |
| 12322 | .xword 0xcfe377c2ffa02a19 |
| 12323 | .xword 0xc253f64c905b731f |
| 12324 | .xword 0x55e47d709614c9fe |
| 12325 | .xword 0x444fb17650ed589f |
| 12326 | .xword 0xdf07316098ab8779 |
| 12327 | .xword 0x0140b08be865b1ca |
| 12328 | .xword 0xfd62cb6eb43aa5c6 |
| 12329 | .xword 0x25d839742723e870 |
| 12330 | .xword 0xca7cb3b45c45ccfc |
| 12331 | .xword 0xec14c84e4f5831ca |
| 12332 | .xword 0xa798e5b2f958fc68 |
| 12333 | .xword 0x17df5b06d84c617e |
| 12334 | .xword 0x8309d8baa56a2317 |
| 12335 | .xword 0xd7b7b5502b67aa1d |
| 12336 | .xword 0x61f12f7687a0be2d |
| 12337 | .xword 0xb71e396af0a32673 |
| 12338 | .xword 0xd25e5e814be9669d |
| 12339 | .xword 0x11350756d6ddc42c |
| 12340 | .xword 0x732d97cb1cb43af2 |
| 12341 | .xword 0xa156c5da7188f25a |
| 12342 | .xword 0x4a4b95f42a9b8530 |
| 12343 | .xword 0x1a297206b38dbe48 |
| 12344 | .xword 0x7b672c319e2bef1f |
| 12345 | .xword 0xc11a35d859077356 |
| 12346 | .xword 0xc375edb9662a1cb1 |
| 12347 | .xword 0x0f2086ba51dbd5cc |
| 12348 | .xword 0x91cfa3e544b7b78e |
| 12349 | .xword 0xb84fb610b52ef434 |
| 12350 | .xword 0xbca8efb241b160f1 |
| 12351 | .xword 0xca663d2ac7473011 |
| 12352 | .xword 0xe93f3120469e8112 |
| 12353 | .xword 0xabd69d5abb7103d4 |
| 12354 | .xword 0x6594f24e17ce53e2 |
| 12355 | .xword 0x5a7ebe82b1aec098 |
| 12356 | .xword 0x3715207a785441ef |
| 12357 | .xword 0xb5ee0a442e407947 |
| 12358 | .xword 0xba601cb3b235ddd7 |
| 12359 | .xword 0x16d21aa2d30cc403 |
| 12360 | .xword 0x39a93410b14aab05 |
| 12361 | .xword 0x1415af03b3f786ca |
| 12362 | .xword 0x5cdb60ec2b51566a |
| 12363 | .xword 0xaa578e11ffe504cb |
| 12364 | .xword 0x7de23561356d28ef |
| 12365 | .xword 0x117867d304c3c2fb |
| 12366 | .xword 0xac187a968225b70a |
| 12367 | .xword 0x650cd654e110b2e9 |
| 12368 | .xword 0xecf4fffe3b731976 |
| 12369 | .xword 0xd2ceb5e6ceba6932 |
| 12370 | .xword 0xb1e5d7c6a3612674 |
| 12371 | .xword 0xe237ae0855757020 |
| 12372 | .xword 0x6aa8fb35c7c53f81 |
| 12373 | .xword 0xfaa7612a272ee5d6 |
| 12374 | .xword 0xd5350b9261c7e420 |
| 12375 | .xword 0xdeafc78deac2be95 |
| 12376 | .xword 0xec86a2c454a9a5a5 |
| 12377 | .xword 0xf8aaa91872a3f3da |
| 12378 | .xword 0x9a1a80092dcb6503 |
| 12379 | .xword 0x6d2028318f4a7ff4 |
| 12380 | .xword 0x9ceefd873f6d29b6 |
| 12381 | .xword 0x7ac73ee26366fa67 |
| 12382 | .xword 0x613a4b4eaf7e2e39 |
| 12383 | .xword 0x45b7b2e7a19a3146 |
| 12384 | .xword 0x18b8a6d96d27c88c |
| 12385 | .xword 0x972e77dcf47f1162 |
| 12386 | .xword 0x6908f6fc5b867cac |
| 12387 | .xword 0x1f78f5643815d992 |
| 12388 | .xword 0x4f32eb242c10bfb4 |
| 12389 | .xword 0xd1b789fb7b5b4c5c |
| 12390 | .xword 0x8128b361fa5fec9b |
| 12391 | .xword 0x3ab2aed430248fbe |
| 12392 | .xword 0x34071061814d5df6 |
| 12393 | .xword 0xbddced5cf24baa48 |
| 12394 | .xword 0x1dd8b3e383c2f273 |
| 12395 | .xword 0xf6374cb5ea9221b3 |
| 12396 | .xword 0x9bfbe162823f7119 |
| 12397 | .xword 0x8c53aeab623ab477 |
| 12398 | .xword 0x5c768c5918c6ebcf |
| 12399 | .xword 0xb973ba49a1ed7d6d |
| 12400 | .xword 0xaa1cf7ea9f688887 |
| 12401 | |
| 12402 | SECTION .HTRAPS |
| 12403 | .text |
| 12404 | .global restore_range_regs |
| 12405 | restore_range_regs: |
| 12406 | wr %g0, ASI_MMU_REAL_RANGE, %asi |
| 12407 | mov 1, %g1 |
| 12408 | sllx %g1, 63, %g1 |
| 12409 | ldxa [ASI_MMU_REAL_RANGE_0] %asi, %g2 |
| 12410 | or %g2 ,%g1, %g2 |
| 12411 | stxa %g2, [ASI_MMU_REAL_RANGE_0] %asi |
| 12412 | ldxa [ASI_MMU_REAL_RANGE_1] %asi, %g2 |
| 12413 | or %g2 ,%g1, %g2 |
| 12414 | stxa %g2, [ASI_MMU_REAL_RANGE_1] %asi |
| 12415 | ldxa [ASI_MMU_REAL_RANGE_2] %asi, %g2 |
| 12416 | or %g2 ,%g1, %g2 |
| 12417 | stxa %g2, [ASI_MMU_REAL_RANGE_2] %asi |
| 12418 | ldxa [ASI_MMU_REAL_RANGE_3] %asi, %g2 |
| 12419 | or %g2 ,%g1, %g2 |
| 12420 | stxa %g2, [ASI_MMU_REAL_RANGE_3] %asi |
| 12421 | retry |
| 12422 | |
| 12423 | .global wdog_2_ext |
| 12424 | # 10 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_extensions.s" |
| 12425 | SECTION .HTRAPS |
| 12426 | .global wdog_2_ext |
| 12427 | .global retry_with_base_tba |
| 12428 | .global resolve_bad_tte |
| 12429 | |
| 12430 | .text |
| 12431 | resolve_bad_tte: |
| 12432 | !if pc[13:5]==0, then assume not a relocated handler |
| 12433 | rdpr %tpc, %r4 |
| 12434 | andn %r4, 0xf, %r5 |
| 12435 | sllx %r5, 49, %r5 |
| 12436 | brnz,a %r5, retry_with_base_tba |
| 12437 | !assume %r27 is where we came from .. |
| 12438 | fdivd %f0, %f4, %f12 |
| 12439 | jmpl %r27+8, %r0 |
| 12440 | fdivs %f0, %f4, %f12 |
| 12441 | retry_with_base_tba: |
| 12442 | best_set_reg(TRAP_BASE_VA, %r3, %r5) |
| 12443 | cmp %r4, %r5 |
| 12444 | bz htrap_5_ext_done |
| 12445 | set 0x7fff, %r3 |
| 12446 | and %r4, %r3, %r4 |
| 12447 | or %r5, %r4, %r4 |
| 12448 | wrpr %r4, %tpc |
| 12449 | rdpr %tnpc, %r4 |
| 12450 | and %r4, %r3, %r4 |
| 12451 | or %r5, %r4, %r4 |
| 12452 | wrpr %r4, %tnpc |
| 12453 | retry |
| 12454 | |
| 12455 | htrap_5_ext: |
| 12456 | rd %pc, %l2 |
| 12457 | inc %l3 |
| 12458 | add %l2, htrap_5_ext_done-htrap_5_ext, %l2 |
| 12459 | rdpr %tl, %l3 |
| 12460 | rdpr %tstate, %l4 |
| 12461 | rdhpr %htstate, %l5 |
| 12462 | or %l5, 0x4, %l5 |
| 12463 | inc %l3 |
| 12464 | wrpr %l3, %tl |
| 12465 | wrpr %l2, %tpc |
| 12466 | add %l2, 4, %l2 |
| 12467 | wrpr %l2, %tnpc |
| 12468 | wrpr %l4, %tstate |
| 12469 | wrhpr %l5, %htstate |
| 12470 | retry |
| 12471 | htrap_5_ext_done: |
| 12472 | done |
| 12473 | |
| 12474 | wdog_2_ext: |
| 12475 | mov 0x1f, %l1 |
| 12476 | stxa %l1, [%g0] ASI_LSU_CTL_REG |
| 12477 | ! If TT != 2, then goto trap handler |
| 12478 | rdpr %tt, %l1 |
| 12479 | cmp %l1, 0x2 |
| 12480 | bne wdog_2_goto_handler |
| 12481 | nop |
| 12482 | ! else done |
| 12483 | done |
| 12484 | wdog_2_goto_handler: |
| 12485 | rdhpr %htstate, %l3 |
| 12486 | and %l3, 0x4, %l3 ! If previously in hpriv mode, go to hpriv |
| 12487 | brnz,a %l3, wdog_2_goto_handler_1 |
| 12488 | rdhpr %htba, %l3 |
| 12489 | srlx %l1, 7, %l3 ! Send priv sw traps to priv mode .. |
| 12490 | cmp %l3, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap .. |
| 12491 | be,a wdog_2_goto_handler_1 |
| 12492 | rdpr %tba, %l3 |
| 12493 | rdhpr %htba, %l3 |
| 12494 | wdog_2_goto_handler_1: |
| 12495 | sllx %l1, 5, %l1 |
| 12496 | add %l1, %l3, %l3 |
| 12497 | jmp %l3 |
| 12498 | nop |
| 12499 | # 86 "/import/n2-aus-random/N2/sandbox-24x7/somePerson/SIMRUN/DIAG/include/tlu_custom_trap_extensions.s" |
| 12500 | ! Red mode other reset handler |
| 12501 | ! Get htba, and tt and make trap address |
| 12502 | ! Jump to trap handler .. |
| 12503 | |
| 12504 | SECTION .RED_SEC |
| 12505 | .global red_other_ext |
| 12506 | .global wdog_red_ext |
| 12507 | .text |
| 12508 | red_other_ext: |
| 12509 | ! IF TL=6, shift stack by one .. |
| 12510 | rdpr %tl, %l1 |
| 12511 | cmp %l1, 6 |
| 12512 | be start_tsa_shift |
| 12513 | nop |
| 12514 | |
| 12515 | continue_red_other: |
| 12516 | mov 0x1f, %l1 |
| 12517 | stxa %l1, [%g0] ASI_LSU_CTL_REG |
| 12518 | |
| 12519 | rdpr %tt, %l1 |
| 12520 | |
| 12521 | rdhpr %htstate, %l2 |
| 12522 | and %l2, 0x4, %l2 ! If previously in hpriv mode, go to hpriv |
| 12523 | brnz,a %l2, red_goto_handler |
| 12524 | rdhpr %htba, %l2 |
| 12525 | srlx %l1, 7, %l2 ! Send priv sw traps to priv mode .. |
| 12526 | cmp %l2, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap .. |
| 12527 | be,a red_goto_handler |
| 12528 | rdpr %tba, %l2 |
| 12529 | rdhpr %htba, %l2 |
| 12530 | red_goto_handler: |
| 12531 | |
| 12532 | sllx %l1, 5, %l1 |
| 12533 | add %l1, %l2, %l2 |
| 12534 | rdhpr %hpstate, %l1 |
| 12535 | jmp %l2 |
| 12536 | wrhpr %l1, 0x20, %hpstate |
| 12537 | nop |
| 12538 | |
| 12539 | wdog_red_ext: |
| 12540 | ! Shift stack down by 1 ... |
| 12541 | rdpr %tl, %l1 |
| 12542 | cmp %l1, 6 |
| 12543 | bl wdog_end |
| 12544 | start_tsa_shift: |
| 12545 | mov 0x2, %l2 |
| 12546 | |
| 12547 | tsa_shift: |
| 12548 | wrpr %l2, %tl |
| 12549 | rdpr %tt, %l3 |
| 12550 | rdpr %tpc, %l4 |
| 12551 | rdpr %tnpc, %l5 |
| 12552 | rdpr %tstate, %l6 |
| 12553 | rdhpr %htstate, %l7 |
| 12554 | dec %l2 |
| 12555 | wrpr %l2, %tl |
| 12556 | wrpr %l3, %tt |
| 12557 | wrpr %l4, %tpc |
| 12558 | wrpr %l5, %tnpc |
| 12559 | wrpr %l6, %tstate |
| 12560 | wrhpr %l7, %htstate |
| 12561 | add %l2, 2, %l2 |
| 12562 | cmp %l2, %l1 |
| 12563 | ble tsa_shift |
| 12564 | nop |
| 12565 | tsa_shift_done: |
| 12566 | dec %l1 |
| 12567 | wrpr %l1, %tl |
| 12568 | |
| 12569 | wdog_end: |
| 12570 | ! If TT != 2, then goto trap handler |
| 12571 | rdpr %tt, %l1 |
| 12572 | |
| 12573 | cmp %l1, 0x2 |
| 12574 | bne continue_red_other |
| 12575 | nop |
| 12576 | ! else done |
| 12577 | mov 0x1f, %l1 |
| 12578 | stxa %l1, [%g0] ASI_LSU_CTL_REG |
| 12579 | done |
| 12580 | # 1111 "diag.j.pp" |
| 12581 | |
| 12582 | SECTION .CWQ_DATA DATA_VA =0x4000 |
| 12583 | attr_data { |
| 12584 | Name = .CWQ_DATA |
| 12585 | hypervisor |
| 12586 | } |
| 12587 | |
| 12588 | .data |
| 12589 | .align 16 |
| 12590 | .global msg |
| 12591 | msg: |
| 12592 | .xword 0xad32fa52374cc6ba |
| 12593 | .xword 0x4cbf52280549003a |
| 12594 | |
| 12595 | .align 16 |
| 12596 | .global results |
| 12597 | results: |
| 12598 | .xword 0xDEADBEEFDEADBEEF |
| 12599 | .xword 0xDEADBEEFDEADBEEF |
| 12600 | !# CWQ data area |
| 12601 | !# CWQ_BASE for core N is CWQ_BASE+(N*256) |
| 12602 | !# CWQ_LAST for core N is CWQ_LAST+(N*256) |
| 12603 | .align 64 |
| 12604 | .global CWQ_BASE |
| 12605 | CWQ_BASE: |
| 12606 | .xword 0xAAAAAAAAAAAAAAA |
| 12607 | .xword 0xAAAAAAAAAAAAAAA |
| 12608 | .xword 0xAAAAAAAAAAAAAAA |
| 12609 | .xword 0xAAAAAAAAAAAAAAA |
| 12610 | .xword 0xAAAAAAAAAAAAAAA |
| 12611 | .xword 0xAAAAAAAAAAAAAAA |
| 12612 | .xword 0xAAAAAAAAAAAAAAA |
| 12613 | .xword 0xAAAAAAAAAAAAAAA |
| 12614 | .xword 0xAAAAAAAAAAAAAAA |
| 12615 | .xword 0xAAAAAAAAAAAAAAA |
| 12616 | .xword 0xAAAAAAAAAAAAAAA |
| 12617 | .xword 0xAAAAAAAAAAAAAAA |
| 12618 | .xword 0xAAAAAAAAAAAAAAA |
| 12619 | .xword 0xAAAAAAAAAAAAAAA |
| 12620 | .xword 0xAAAAAAAAAAAAAAA |
| 12621 | .xword 0xAAAAAAAAAAAAAAA |
| 12622 | .xword 0xAAAAAAAAAAAAAAA |
| 12623 | .xword 0xAAAAAAAAAAAAAAA |
| 12624 | .xword 0xAAAAAAAAAAAAAAA |
| 12625 | .xword 0xAAAAAAAAAAAAAAA |
| 12626 | .xword 0xAAAAAAAAAAAAAAA |
| 12627 | .xword 0xAAAAAAAAAAAAAAA |
| 12628 | .xword 0xAAAAAAAAAAAAAAA |
| 12629 | .xword 0xAAAAAAAAAAAAAAA |
| 12630 | .global CWQ_LAST |
| 12631 | .align 64 |
| 12632 | CWQ_LAST: |
| 12633 | .word 0x0 |
| 12634 | .align 64 |
| 12635 | cwq_base1: |
| 12636 | .xword 0xAAAAAAAAAAAAAAA |
| 12637 | .xword 0xAAAAAAAAAAAAAAA |
| 12638 | .xword 0xAAAAAAAAAAAAAAA |
| 12639 | .xword 0xAAAAAAAAAAAAAAA |
| 12640 | .xword 0xAAAAAAAAAAAAAAA |
| 12641 | .xword 0xAAAAAAAAAAAAAAA |
| 12642 | .xword 0xAAAAAAAAAAAAAAA |
| 12643 | .xword 0xAAAAAAAAAAAAAAA |
| 12644 | .xword 0xAAAAAAAAAAAAAAA |
| 12645 | .xword 0xAAAAAAAAAAAAAAA |
| 12646 | .xword 0xAAAAAAAAAAAAAAA |
| 12647 | .xword 0xAAAAAAAAAAAAAAA |
| 12648 | .xword 0xAAAAAAAAAAAAAAA |
| 12649 | .xword 0xAAAAAAAAAAAAAAA |
| 12650 | .xword 0xAAAAAAAAAAAAAAA |
| 12651 | .xword 0xAAAAAAAAAAAAAAA |
| 12652 | .xword 0xAAAAAAAAAAAAAAA |
| 12653 | .xword 0xAAAAAAAAAAAAAAA |
| 12654 | .xword 0xAAAAAAAAAAAAAAA |
| 12655 | .xword 0xAAAAAAAAAAAAAAA |
| 12656 | .xword 0xAAAAAAAAAAAAAAA |
| 12657 | .xword 0xAAAAAAAAAAAAAAA |
| 12658 | .xword 0xAAAAAAAAAAAAAAA |
| 12659 | .xword 0xAAAAAAAAAAAAAAA |
| 12660 | .align 64 |
| 12661 | cwq_last1: |
| 12662 | .word 0x0 |
| 12663 | .align 64 |
| 12664 | .xword 0xAAAAAAAAAAAAAAA |
| 12665 | .xword 0xAAAAAAAAAAAAAAA |
| 12666 | .xword 0xAAAAAAAAAAAAAAA |
| 12667 | .xword 0xAAAAAAAAAAAAAAA |
| 12668 | .xword 0xAAAAAAAAAAAAAAA |
| 12669 | .xword 0xAAAAAAAAAAAAAAA |
| 12670 | .xword 0xAAAAAAAAAAAAAAA |
| 12671 | .xword 0xAAAAAAAAAAAAAAA |
| 12672 | .xword 0xAAAAAAAAAAAAAAA |
| 12673 | .xword 0xAAAAAAAAAAAAAAA |
| 12674 | .xword 0xAAAAAAAAAAAAAAA |
| 12675 | .xword 0xAAAAAAAAAAAAAAA |
| 12676 | .xword 0xAAAAAAAAAAAAAAA |
| 12677 | .xword 0xAAAAAAAAAAAAAAA |
| 12678 | .xword 0xAAAAAAAAAAAAAAA |
| 12679 | .xword 0xAAAAAAAAAAAAAAA |
| 12680 | .xword 0xAAAAAAAAAAAAAAA |
| 12681 | .xword 0xAAAAAAAAAAAAAAA |
| 12682 | .xword 0xAAAAAAAAAAAAAAA |
| 12683 | .xword 0xAAAAAAAAAAAAAAA |
| 12684 | .xword 0xAAAAAAAAAAAAAAA |
| 12685 | .xword 0xAAAAAAAAAAAAAAA |
| 12686 | .xword 0xAAAAAAAAAAAAAAA |
| 12687 | .xword 0xAAAAAAAAAAAAAAA |
| 12688 | .align 64 |
| 12689 | .word 0x0 |
| 12690 | .align 64 |
| 12691 | .xword 0xAAAAAAAAAAAAAAA |
| 12692 | .xword 0xAAAAAAAAAAAAAAA |
| 12693 | .xword 0xAAAAAAAAAAAAAAA |
| 12694 | .xword 0xAAAAAAAAAAAAAAA |
| 12695 | .xword 0xAAAAAAAAAAAAAAA |
| 12696 | .xword 0xAAAAAAAAAAAAAAA |
| 12697 | .xword 0xAAAAAAAAAAAAAAA |
| 12698 | .xword 0xAAAAAAAAAAAAAAA |
| 12699 | .xword 0xAAAAAAAAAAAAAAA |
| 12700 | .xword 0xAAAAAAAAAAAAAAA |
| 12701 | .xword 0xAAAAAAAAAAAAAAA |
| 12702 | .xword 0xAAAAAAAAAAAAAAA |
| 12703 | .xword 0xAAAAAAAAAAAAAAA |
| 12704 | .xword 0xAAAAAAAAAAAAAAA |
| 12705 | .xword 0xAAAAAAAAAAAAAAA |
| 12706 | .xword 0xAAAAAAAAAAAAAAA |
| 12707 | .xword 0xAAAAAAAAAAAAAAA |
| 12708 | .xword 0xAAAAAAAAAAAAAAA |
| 12709 | .xword 0xAAAAAAAAAAAAAAA |
| 12710 | .xword 0xAAAAAAAAAAAAAAA |
| 12711 | .xword 0xAAAAAAAAAAAAAAA |
| 12712 | .xword 0xAAAAAAAAAAAAAAA |
| 12713 | .xword 0xAAAAAAAAAAAAAAA |
| 12714 | .xword 0xAAAAAAAAAAAAAAA |
| 12715 | .align 64 |
| 12716 | .word 0x0 |
| 12717 | .align 64 |
| 12718 | .xword 0xAAAAAAAAAAAAAAA |
| 12719 | .xword 0xAAAAAAAAAAAAAAA |
| 12720 | .xword 0xAAAAAAAAAAAAAAA |
| 12721 | .xword 0xAAAAAAAAAAAAAAA |
| 12722 | .xword 0xAAAAAAAAAAAAAAA |
| 12723 | .xword 0xAAAAAAAAAAAAAAA |
| 12724 | .xword 0xAAAAAAAAAAAAAAA |
| 12725 | .xword 0xAAAAAAAAAAAAAAA |
| 12726 | .xword 0xAAAAAAAAAAAAAAA |
| 12727 | .xword 0xAAAAAAAAAAAAAAA |
| 12728 | .xword 0xAAAAAAAAAAAAAAA |
| 12729 | .xword 0xAAAAAAAAAAAAAAA |
| 12730 | .xword 0xAAAAAAAAAAAAAAA |
| 12731 | .xword 0xAAAAAAAAAAAAAAA |
| 12732 | .xword 0xAAAAAAAAAAAAAAA |
| 12733 | .xword 0xAAAAAAAAAAAAAAA |
| 12734 | .xword 0xAAAAAAAAAAAAAAA |
| 12735 | .xword 0xAAAAAAAAAAAAAAA |
| 12736 | .xword 0xAAAAAAAAAAAAAAA |
| 12737 | .xword 0xAAAAAAAAAAAAAAA |
| 12738 | .xword 0xAAAAAAAAAAAAAAA |
| 12739 | .xword 0xAAAAAAAAAAAAAAA |
| 12740 | .xword 0xAAAAAAAAAAAAAAA |
| 12741 | .xword 0xAAAAAAAAAAAAAAA |
| 12742 | .align 64 |
| 12743 | .word 0x0 |
| 12744 | .align 64 |
| 12745 | .xword 0xAAAAAAAAAAAAAAA |
| 12746 | .xword 0xAAAAAAAAAAAAAAA |
| 12747 | .xword 0xAAAAAAAAAAAAAAA |
| 12748 | .xword 0xAAAAAAAAAAAAAAA |
| 12749 | .xword 0xAAAAAAAAAAAAAAA |
| 12750 | .xword 0xAAAAAAAAAAAAAAA |
| 12751 | .xword 0xAAAAAAAAAAAAAAA |
| 12752 | .xword 0xAAAAAAAAAAAAAAA |
| 12753 | .xword 0xAAAAAAAAAAAAAAA |
| 12754 | .xword 0xAAAAAAAAAAAAAAA |
| 12755 | .xword 0xAAAAAAAAAAAAAAA |
| 12756 | .xword 0xAAAAAAAAAAAAAAA |
| 12757 | .xword 0xAAAAAAAAAAAAAAA |
| 12758 | .xword 0xAAAAAAAAAAAAAAA |
| 12759 | .xword 0xAAAAAAAAAAAAAAA |
| 12760 | .xword 0xAAAAAAAAAAAAAAA |
| 12761 | .xword 0xAAAAAAAAAAAAAAA |
| 12762 | .xword 0xAAAAAAAAAAAAAAA |
| 12763 | .xword 0xAAAAAAAAAAAAAAA |
| 12764 | .xword 0xAAAAAAAAAAAAAAA |
| 12765 | .xword 0xAAAAAAAAAAAAAAA |
| 12766 | .xword 0xAAAAAAAAAAAAAAA |
| 12767 | .xword 0xAAAAAAAAAAAAAAA |
| 12768 | .xword 0xAAAAAAAAAAAAAAA |
| 12769 | .align 64 |
| 12770 | .word 0x0 |
| 12771 | .align 64 |
| 12772 | .xword 0xAAAAAAAAAAAAAAA |
| 12773 | .xword 0xAAAAAAAAAAAAAAA |
| 12774 | .xword 0xAAAAAAAAAAAAAAA |
| 12775 | .xword 0xAAAAAAAAAAAAAAA |
| 12776 | .xword 0xAAAAAAAAAAAAAAA |
| 12777 | .xword 0xAAAAAAAAAAAAAAA |
| 12778 | .xword 0xAAAAAAAAAAAAAAA |
| 12779 | .xword 0xAAAAAAAAAAAAAAA |
| 12780 | .xword 0xAAAAAAAAAAAAAAA |
| 12781 | .xword 0xAAAAAAAAAAAAAAA |
| 12782 | .xword 0xAAAAAAAAAAAAAAA |
| 12783 | .xword 0xAAAAAAAAAAAAAAA |
| 12784 | .xword 0xAAAAAAAAAAAAAAA |
| 12785 | .xword 0xAAAAAAAAAAAAAAA |
| 12786 | .xword 0xAAAAAAAAAAAAAAA |
| 12787 | .xword 0xAAAAAAAAAAAAAAA |
| 12788 | .xword 0xAAAAAAAAAAAAAAA |
| 12789 | .xword 0xAAAAAAAAAAAAAAA |
| 12790 | .xword 0xAAAAAAAAAAAAAAA |
| 12791 | .xword 0xAAAAAAAAAAAAAAA |
| 12792 | .xword 0xAAAAAAAAAAAAAAA |
| 12793 | .xword 0xAAAAAAAAAAAAAAA |
| 12794 | .xword 0xAAAAAAAAAAAAAAA |
| 12795 | .xword 0xAAAAAAAAAAAAAAA |
| 12796 | .align 64 |
| 12797 | .word 0x0 |
| 12798 | .align 64 |
| 12799 | .xword 0xAAAAAAAAAAAAAAA |
| 12800 | .xword 0xAAAAAAAAAAAAAAA |
| 12801 | .xword 0xAAAAAAAAAAAAAAA |
| 12802 | .xword 0xAAAAAAAAAAAAAAA |
| 12803 | .xword 0xAAAAAAAAAAAAAAA |
| 12804 | .xword 0xAAAAAAAAAAAAAAA |
| 12805 | .xword 0xAAAAAAAAAAAAAAA |
| 12806 | .xword 0xAAAAAAAAAAAAAAA |
| 12807 | .xword 0xAAAAAAAAAAAAAAA |
| 12808 | .xword 0xAAAAAAAAAAAAAAA |
| 12809 | .xword 0xAAAAAAAAAAAAAAA |
| 12810 | .xword 0xAAAAAAAAAAAAAAA |
| 12811 | .xword 0xAAAAAAAAAAAAAAA |
| 12812 | .xword 0xAAAAAAAAAAAAAAA |
| 12813 | .xword 0xAAAAAAAAAAAAAAA |
| 12814 | .xword 0xAAAAAAAAAAAAAAA |
| 12815 | .xword 0xAAAAAAAAAAAAAAA |
| 12816 | .xword 0xAAAAAAAAAAAAAAA |
| 12817 | .xword 0xAAAAAAAAAAAAAAA |
| 12818 | .xword 0xAAAAAAAAAAAAAAA |
| 12819 | .xword 0xAAAAAAAAAAAAAAA |
| 12820 | .xword 0xAAAAAAAAAAAAAAA |
| 12821 | .xword 0xAAAAAAAAAAAAAAA |
| 12822 | .xword 0xAAAAAAAAAAAAAAA |
| 12823 | .align 64 |
| 12824 | .word 0x0 |
| 12825 | |
| 12826 | |
| 12827 | |
| 12828 | SECTION .MyHTRAPS_0 TEXT_VA = 0x0000000000280000, DATA_VA = 0x00000000002c0000 |
| 12829 | attr_text { |
| 12830 | Name = .MyHTRAPS_0, |
| 12831 | RA = 0x0000000000280000, |
| 12832 | PA = ra2pa(0x0000000000280000,0), |
| 12833 | part_0_ctx_zero_tsb_config_3, |
| 12834 | part_0_ctx_nonzero_tsb_config_3, |
| 12835 | TTE_G = 1, |
| 12836 | TTE_Context = 0, |
| 12837 | TTE_V = 1, |
| 12838 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 12839 | TTE_NFO = 0, |
| 12840 | TTE_IE = 0, |
| 12841 | TTE_Soft2 = 0, |
| 12842 | TTE_Diag = 0, |
| 12843 | TTE_Soft = 0, |
| 12844 | TTE_L = 0, |
| 12845 | TTE_CP = 0, |
| 12846 | TTE_CV = 1, |
| 12847 | TTE_E = 0, |
| 12848 | TTE_P = 1, |
| 12849 | TTE_W = 0, |
| 12850 | TTE_X = 0 |
| 12851 | } |
| 12852 | |
| 12853 | |
| 12854 | attr_data { |
| 12855 | Name = .MyHTRAPS_0, |
| 12856 | RA = 0x00000000002c0000, |
| 12857 | PA = ra2pa(0x00000000002c0000,0), |
| 12858 | part_0_ctx_zero_tsb_config_3, |
| 12859 | part_0_ctx_nonzero_tsb_config_3, |
| 12860 | TTE_G = 1, |
| 12861 | TTE_Context = 0, |
| 12862 | TTE_V = 1, |
| 12863 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 12864 | TTE_NFO = 0, |
| 12865 | TTE_IE = 0, |
| 12866 | TTE_Soft2 = 0, |
| 12867 | TTE_Diag = 0, |
| 12868 | TTE_Soft = 0, |
| 12869 | TTE_L = 0, |
| 12870 | TTE_CP = 0, |
| 12871 | TTE_CV = 0, |
| 12872 | TTE_E = 0, |
| 12873 | TTE_P = 1, |
| 12874 | TTE_W = 0 |
| 12875 | } |
| 12876 | |
| 12877 | .text |
| 12878 | #include "htraps.s" |
| 12879 | #include "tlu_htraps_ext.s" |
| 12880 | |
| 12881 | |
| 12882 | |
| 12883 | SECTION .MyHTRAPS_1 TEXT_VA = 0x00000000002a0000, DATA_VA = 0x00000000002e0000 |
| 12884 | attr_text { |
| 12885 | Name = .MyHTRAPS_1, |
| 12886 | RA = 0x00000000002a0000, |
| 12887 | PA = ra2pa(0x00000000002a0000,0), |
| 12888 | part_0_ctx_zero_tsb_config_3, |
| 12889 | part_0_ctx_nonzero_tsb_config_3, |
| 12890 | TTE_G = 1, |
| 12891 | TTE_Context = 0, |
| 12892 | TTE_V = 1, |
| 12893 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 12894 | TTE_NFO = 0, |
| 12895 | TTE_IE = 0, |
| 12896 | TTE_Soft2 = 0, |
| 12897 | TTE_Diag = 0, |
| 12898 | TTE_Soft = 0, |
| 12899 | TTE_L = 0, |
| 12900 | TTE_CP = 0, |
| 12901 | TTE_CV = 0, |
| 12902 | TTE_E = 1, |
| 12903 | TTE_P = 1, |
| 12904 | TTE_W = 0, |
| 12905 | TTE_X = 0 |
| 12906 | } |
| 12907 | |
| 12908 | |
| 12909 | attr_data { |
| 12910 | Name = .MyHTRAPS_1, |
| 12911 | RA = 0x00000000002e0000, |
| 12912 | PA = ra2pa(0x00000000002e0000,0), |
| 12913 | part_0_ctx_zero_tsb_config_3, |
| 12914 | part_0_ctx_nonzero_tsb_config_3, |
| 12915 | TTE_G = 1, |
| 12916 | TTE_Context = 0, |
| 12917 | TTE_V = 1, |
| 12918 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 12919 | TTE_NFO = 0, |
| 12920 | TTE_IE = 0, |
| 12921 | TTE_Soft2 = 0, |
| 12922 | TTE_Diag = 0, |
| 12923 | TTE_Soft = 0, |
| 12924 | TTE_L = 0, |
| 12925 | TTE_CP = 1, |
| 12926 | TTE_CV = 0, |
| 12927 | TTE_E = 0, |
| 12928 | TTE_P = 1, |
| 12929 | TTE_W = 0 |
| 12930 | } |
| 12931 | |
| 12932 | .text |
| 12933 | #include "htraps.s" |
| 12934 | #include "tlu_htraps_ext.s" |
| 12935 | |
| 12936 | |
| 12937 | |
| 12938 | SECTION .MyHTRAPS_2 TEXT_VA = 0x0000000200280000, DATA_VA = 0x00000002002c0000 |
| 12939 | attr_text { |
| 12940 | Name = .MyHTRAPS_2, |
| 12941 | RA = 0x0000000200280000, |
| 12942 | PA = ra2pa(0x0000000200280000,0), |
| 12943 | part_0_ctx_zero_tsb_config_3, |
| 12944 | part_0_ctx_nonzero_tsb_config_3, |
| 12945 | TTE_G = 1, |
| 12946 | TTE_Context = 0, |
| 12947 | TTE_V = 1, |
| 12948 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 12949 | TTE_NFO = 0, |
| 12950 | TTE_IE = 0, |
| 12951 | TTE_Soft2 = 0, |
| 12952 | TTE_Diag = 0, |
| 12953 | TTE_Soft = 0, |
| 12954 | TTE_L = 0, |
| 12955 | TTE_CP = 0, |
| 12956 | TTE_CV = 1, |
| 12957 | TTE_E = 1, |
| 12958 | TTE_P = 1, |
| 12959 | TTE_W = 0, |
| 12960 | TTE_X = 0 |
| 12961 | } |
| 12962 | |
| 12963 | |
| 12964 | attr_data { |
| 12965 | Name = .MyHTRAPS_2, |
| 12966 | RA = 0x00000002002c0000, |
| 12967 | PA = ra2pa(0x00000002002c0000,0), |
| 12968 | part_0_ctx_zero_tsb_config_3, |
| 12969 | part_0_ctx_nonzero_tsb_config_3, |
| 12970 | TTE_G = 1, |
| 12971 | TTE_Context = 0, |
| 12972 | TTE_V = 1, |
| 12973 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 12974 | TTE_NFO = 0, |
| 12975 | TTE_IE = 0, |
| 12976 | TTE_Soft2 = 0, |
| 12977 | TTE_Diag = 0, |
| 12978 | TTE_Soft = 0, |
| 12979 | TTE_L = 0, |
| 12980 | TTE_CP = 0, |
| 12981 | TTE_CV = 0, |
| 12982 | TTE_E = 0, |
| 12983 | TTE_P = 1, |
| 12984 | TTE_W = 0 |
| 12985 | } |
| 12986 | |
| 12987 | .text |
| 12988 | #include "htraps.s" |
| 12989 | #include "tlu_htraps_ext.s" |
| 12990 | |
| 12991 | |
| 12992 | |
| 12993 | SECTION .MyHTRAPS_3 TEXT_VA = 0x00000002002a0000, DATA_VA = 0x00000002002e0000 |
| 12994 | attr_text { |
| 12995 | Name = .MyHTRAPS_3, |
| 12996 | RA = 0x00000002002a0000, |
| 12997 | PA = ra2pa(0x00000002002a0000,0), |
| 12998 | part_0_ctx_zero_tsb_config_3, |
| 12999 | part_0_ctx_nonzero_tsb_config_3, |
| 13000 | TTE_G = 1, |
| 13001 | TTE_Context = 0, |
| 13002 | TTE_V = 1, |
| 13003 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13004 | TTE_NFO = 0, |
| 13005 | TTE_IE = 0, |
| 13006 | TTE_Soft2 = 0, |
| 13007 | TTE_Diag = 0, |
| 13008 | TTE_Soft = 0, |
| 13009 | TTE_L = 0, |
| 13010 | TTE_CP = 1, |
| 13011 | TTE_CV = 0, |
| 13012 | TTE_E = 0, |
| 13013 | TTE_P = 1, |
| 13014 | TTE_W = 0, |
| 13015 | TTE_X = 0 |
| 13016 | } |
| 13017 | |
| 13018 | |
| 13019 | attr_data { |
| 13020 | Name = .MyHTRAPS_3, |
| 13021 | RA = 0x00000002002e0000, |
| 13022 | PA = ra2pa(0x00000002002e0000,0), |
| 13023 | part_0_ctx_zero_tsb_config_3, |
| 13024 | part_0_ctx_nonzero_tsb_config_3, |
| 13025 | TTE_G = 1, |
| 13026 | TTE_Context = 0, |
| 13027 | TTE_V = 1, |
| 13028 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13029 | TTE_NFO = 0, |
| 13030 | TTE_IE = 0, |
| 13031 | TTE_Soft2 = 0, |
| 13032 | TTE_Diag = 0, |
| 13033 | TTE_Soft = 0, |
| 13034 | TTE_L = 0, |
| 13035 | TTE_CP = 0, |
| 13036 | TTE_CV = 0, |
| 13037 | TTE_E = 0, |
| 13038 | TTE_P = 1, |
| 13039 | TTE_W = 0 |
| 13040 | } |
| 13041 | |
| 13042 | .text |
| 13043 | #include "htraps.s" |
| 13044 | #include "tlu_htraps_ext.s" |
| 13045 | |
| 13046 | |
| 13047 | |
| 13048 | |
| 13049 | |
| 13050 | SECTION .MyTRAPS_0 TEXT_VA = 0x0000000000380000, DATA_VA = 0x00000000003c0000 |
| 13051 | attr_text { |
| 13052 | Name = .MyTRAPS_0, |
| 13053 | RA = 0x0000000000380000, |
| 13054 | PA = ra2pa(0x0000000000380000,0), |
| 13055 | part_0_ctx_zero_tsb_config_3, |
| 13056 | part_0_ctx_nonzero_tsb_config_3, |
| 13057 | TTE_G = 1, |
| 13058 | TTE_Context = 0, |
| 13059 | TTE_V = 1, |
| 13060 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13061 | TTE_NFO = 1, |
| 13062 | TTE_IE = 0, |
| 13063 | TTE_Soft2 = 0, |
| 13064 | TTE_Diag = 0, |
| 13065 | TTE_Soft = 0, |
| 13066 | TTE_L = 0, |
| 13067 | TTE_CP = 1, |
| 13068 | TTE_CV = 0, |
| 13069 | TTE_E = 1, |
| 13070 | TTE_P = 1, |
| 13071 | TTE_W = 1, |
| 13072 | TTE_X = 0 |
| 13073 | } |
| 13074 | |
| 13075 | |
| 13076 | attr_data { |
| 13077 | Name = .MyTRAPS_0, |
| 13078 | RA = 0x00000000003c0000, |
| 13079 | PA = ra2pa(0x00000000003c0000,0), |
| 13080 | part_0_ctx_zero_tsb_config_3, |
| 13081 | part_0_ctx_nonzero_tsb_config_3, |
| 13082 | TTE_G = 1, |
| 13083 | TTE_Context = 0, |
| 13084 | TTE_V = 1, |
| 13085 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13086 | TTE_NFO = 0, |
| 13087 | TTE_IE = 1, |
| 13088 | TTE_Soft2 = 0, |
| 13089 | TTE_Diag = 0, |
| 13090 | TTE_Soft = 0, |
| 13091 | TTE_L = 0, |
| 13092 | TTE_CP = 0, |
| 13093 | TTE_CV = 1, |
| 13094 | TTE_E = 0, |
| 13095 | TTE_P = 1, |
| 13096 | TTE_W = 1 |
| 13097 | } |
| 13098 | |
| 13099 | #include "traps.s" |
| 13100 | |
| 13101 | |
| 13102 | |
| 13103 | SECTION .MyTRAPS_1 TEXT_VA = 0x00000000003a0000, DATA_VA = 0x00000000003e0000 |
| 13104 | attr_text { |
| 13105 | Name = .MyTRAPS_1, |
| 13106 | RA = 0x00000000003a0000, |
| 13107 | PA = ra2pa(0x00000000003a0000,0), |
| 13108 | part_0_ctx_zero_tsb_config_3, |
| 13109 | part_0_ctx_nonzero_tsb_config_3, |
| 13110 | TTE_G = 1, |
| 13111 | TTE_Context = 0, |
| 13112 | TTE_V = 1, |
| 13113 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13114 | TTE_NFO = 1, |
| 13115 | TTE_IE = 1, |
| 13116 | TTE_Soft2 = 0, |
| 13117 | TTE_Diag = 0, |
| 13118 | TTE_Soft = 0, |
| 13119 | TTE_L = 0, |
| 13120 | TTE_CP = 0, |
| 13121 | TTE_CV = 1, |
| 13122 | TTE_E = 1, |
| 13123 | TTE_P = 0, |
| 13124 | TTE_W = 1, |
| 13125 | TTE_X = 1 |
| 13126 | } |
| 13127 | |
| 13128 | |
| 13129 | attr_data { |
| 13130 | Name = .MyTRAPS_1, |
| 13131 | RA = 0x00000000003e0000, |
| 13132 | PA = ra2pa(0x00000000003e0000,0), |
| 13133 | part_0_ctx_zero_tsb_config_3, |
| 13134 | part_0_ctx_nonzero_tsb_config_3, |
| 13135 | TTE_G = 1, |
| 13136 | TTE_Context = 0, |
| 13137 | TTE_V = 1, |
| 13138 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13139 | TTE_NFO = 0, |
| 13140 | TTE_IE = 1, |
| 13141 | TTE_Soft2 = 0, |
| 13142 | TTE_Diag = 0, |
| 13143 | TTE_Soft = 0, |
| 13144 | TTE_L = 0, |
| 13145 | TTE_CP = 0, |
| 13146 | TTE_CV = 0, |
| 13147 | TTE_E = 0, |
| 13148 | TTE_P = 1, |
| 13149 | TTE_W = 1 |
| 13150 | } |
| 13151 | |
| 13152 | #include "traps.s" |
| 13153 | |
| 13154 | |
| 13155 | |
| 13156 | SECTION .MyTRAPS_2 TEXT_VA = 0x0000000400380000, DATA_VA = 0x00000004003c0000 |
| 13157 | attr_text { |
| 13158 | Name = .MyTRAPS_2, |
| 13159 | RA = 0x0000000400380000, |
| 13160 | PA = ra2pa(0x0000000400380000,0), |
| 13161 | part_0_ctx_zero_tsb_config_3, |
| 13162 | part_0_ctx_nonzero_tsb_config_3, |
| 13163 | TTE_G = 1, |
| 13164 | TTE_Context = 0, |
| 13165 | TTE_V = 1, |
| 13166 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13167 | TTE_NFO = 0, |
| 13168 | TTE_IE = 1, |
| 13169 | TTE_Soft2 = 0, |
| 13170 | TTE_Diag = 0, |
| 13171 | TTE_Soft = 0, |
| 13172 | TTE_L = 0, |
| 13173 | TTE_CP = 0, |
| 13174 | TTE_CV = 0, |
| 13175 | TTE_E = 1, |
| 13176 | TTE_P = 1, |
| 13177 | TTE_W = 0, |
| 13178 | TTE_X = 1 |
| 13179 | } |
| 13180 | |
| 13181 | |
| 13182 | attr_data { |
| 13183 | Name = .MyTRAPS_2, |
| 13184 | RA = 0x00000004003c0000, |
| 13185 | PA = ra2pa(0x00000004003c0000,0), |
| 13186 | part_0_ctx_zero_tsb_config_3, |
| 13187 | part_0_ctx_nonzero_tsb_config_3, |
| 13188 | TTE_G = 1, |
| 13189 | TTE_Context = 0, |
| 13190 | TTE_V = 1, |
| 13191 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13192 | TTE_NFO = 1, |
| 13193 | TTE_IE = 0, |
| 13194 | TTE_Soft2 = 0, |
| 13195 | TTE_Diag = 0, |
| 13196 | TTE_Soft = 0, |
| 13197 | TTE_L = 0, |
| 13198 | TTE_CP = 1, |
| 13199 | TTE_CV = 0, |
| 13200 | TTE_E = 0, |
| 13201 | TTE_P = 1, |
| 13202 | TTE_W = 0 |
| 13203 | } |
| 13204 | |
| 13205 | #include "traps.s" |
| 13206 | |
| 13207 | |
| 13208 | |
| 13209 | SECTION .MyTRAPS_3 TEXT_VA = 0x00000004003a0000, DATA_VA = 0x00000004003e0000 |
| 13210 | attr_text { |
| 13211 | Name = .MyTRAPS_3, |
| 13212 | RA = 0x00000004003a0000, |
| 13213 | PA = ra2pa(0x00000004003a0000,0), |
| 13214 | part_0_ctx_zero_tsb_config_3, |
| 13215 | part_0_ctx_nonzero_tsb_config_3, |
| 13216 | TTE_G = 1, |
| 13217 | TTE_Context = 0, |
| 13218 | TTE_V = 1, |
| 13219 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13220 | TTE_NFO = 1, |
| 13221 | TTE_IE = 1, |
| 13222 | TTE_Soft2 = 0, |
| 13223 | TTE_Diag = 0, |
| 13224 | TTE_Soft = 0, |
| 13225 | TTE_L = 0, |
| 13226 | TTE_CP = 0, |
| 13227 | TTE_CV = 1, |
| 13228 | TTE_E = 1, |
| 13229 | TTE_P = 1, |
| 13230 | TTE_W = 0, |
| 13231 | TTE_X = 0 |
| 13232 | } |
| 13233 | |
| 13234 | |
| 13235 | attr_data { |
| 13236 | Name = .MyTRAPS_3, |
| 13237 | RA = 0x00000004003e0000, |
| 13238 | PA = ra2pa(0x00000004003e0000,0), |
| 13239 | part_0_ctx_zero_tsb_config_3, |
| 13240 | part_0_ctx_nonzero_tsb_config_3, |
| 13241 | TTE_G = 1, |
| 13242 | TTE_Context = 0, |
| 13243 | TTE_V = 1, |
| 13244 | TTE_Size = PART0_Z_PAGE_SIZE_3, |
| 13245 | TTE_NFO = 0, |
| 13246 | TTE_IE = 0, |
| 13247 | TTE_Soft2 = 0, |
| 13248 | TTE_Diag = 0, |
| 13249 | TTE_Soft = 0, |
| 13250 | TTE_L = 0, |
| 13251 | TTE_CP = 0, |
| 13252 | TTE_CV = 1, |
| 13253 | TTE_E = 0, |
| 13254 | TTE_P = 1, |
| 13255 | TTE_W = 1 |
| 13256 | } |
| 13257 | |
| 13258 | #include "traps.s" |
| 13259 | |
| 13260 | |
| 13261 | |
| 13262 | |
| 13263 | |
| 13264 | SECTION .MyDATA_0 TEXT_VA = 0x00000000e0140000, DATA_VA = 0x0000000060140000 |
| 13265 | attr_text { |
| 13266 | Name = .MyDATA_0, |
| 13267 | RA = 0x0000000170100000, |
| 13268 | PA = ra2pa(0x0000000170100000,0), |
| 13269 | part_0_ctx_zero_tsb_config_0, |
| 13270 | part_0_ctx_nonzero_tsb_config_0, |
| 13271 | TTE_G = 1, |
| 13272 | TTE_Context = PCONTEXT, |
| 13273 | TTE_V = 1, |
| 13274 | TTE_Size = 3, |
| 13275 | TTE_NFO = 1, |
| 13276 | TTE_IE = 1, |
| 13277 | TTE_Soft2 = 0, |
| 13278 | TTE_Diag = 0, |
| 13279 | TTE_Soft = 0, |
| 13280 | TTE_L = 0, |
| 13281 | TTE_CP = 1, |
| 13282 | TTE_CV = 0, |
| 13283 | TTE_E = 0, |
| 13284 | TTE_P = 1, |
| 13285 | TTE_W = 1 |
| 13286 | } |
| 13287 | |
| 13288 | |
| 13289 | attr_data { |
| 13290 | Name = .MyDATA_0, |
| 13291 | RA = 0x0000000170100000, |
| 13292 | PA = ra2pa(0x0000000170100000,0), |
| 13293 | part_0_ctx_zero_tsb_config_1, |
| 13294 | part_0_ctx_nonzero_tsb_config_1, |
| 13295 | TTE_G = 1, |
| 13296 | TTE_Context = SCONTEXT, |
| 13297 | TTE_V = 1, |
| 13298 | TTE_Size = 1, |
| 13299 | TTE_NFO = 1, |
| 13300 | TTE_IE = 1, |
| 13301 | TTE_Soft2 = 0, |
| 13302 | TTE_Diag = 0, |
| 13303 | TTE_Soft = 0, |
| 13304 | TTE_L = 0, |
| 13305 | TTE_CP = 1, |
| 13306 | TTE_CV = 1, |
| 13307 | TTE_E = 1, |
| 13308 | TTE_P = 1, |
| 13309 | TTE_W = 0, |
| 13310 | tsbonly |
| 13311 | } |
| 13312 | |
| 13313 | |
| 13314 | attr_data { |
| 13315 | Name = .MyDATA_0, |
| 13316 | hypervisor |
| 13317 | } |
| 13318 | |
| 13319 | |
| 13320 | attr_text { |
| 13321 | Name = .MyDATA_0, |
| 13322 | hypervisor |
| 13323 | } |
| 13324 | |
| 13325 | .data |
| 13326 | .xword 0xa38d13a20b95e5f4 |
| 13327 | .xword 0x557e7377aafec941 |
| 13328 | .xword 0x0c7ef84e756889be |
| 13329 | .xword 0xd76879f41caa3471 |
| 13330 | .xword 0xb54e327cafa94eb8 |
| 13331 | .xword 0x9dac092b410807bd |
| 13332 | .xword 0x7239b753894db7ae |
| 13333 | .xword 0x71eb5bbdc644d2af |
| 13334 | .xword 0x5f29b5b5b4aa36cc |
| 13335 | .xword 0xf0319ae3892d74c1 |
| 13336 | .xword 0x96c618e7558989cc |
| 13337 | .xword 0xf5607b4e37067744 |
| 13338 | .xword 0x25bd5af8f34960a4 |
| 13339 | .xword 0x1ce3de35679586dc |
| 13340 | .xword 0xc9c6c39d336cf851 |
| 13341 | .xword 0x9c537ef8f4e21060 |
| 13342 | .xword 0xb908db9b3b50342e |
| 13343 | .xword 0x614f963a42a2b679 |
| 13344 | .xword 0xde1ad59dfc433477 |
| 13345 | .xword 0x524c209b0a5c3f4b |
| 13346 | .xword 0x8373e8040ee0b268 |
| 13347 | .xword 0xc1643619d63ca83d |
| 13348 | .xword 0xe9ab0bcc13c49271 |
| 13349 | .xword 0xce8391ddcbddc6fb |
| 13350 | .xword 0x8fcb1bdf9c8cddc4 |
| 13351 | .xword 0x90640ce675195134 |
| 13352 | .xword 0xe20abed543cf55d9 |
| 13353 | .xword 0xead60c2e95bee339 |
| 13354 | .xword 0x4b5231519be58a0e |
| 13355 | .xword 0xb8cbc60e99409221 |
| 13356 | .xword 0x4d4f5f2e91541aa3 |
| 13357 | .xword 0x160c57852c8e8e78 |
| 13358 | |
| 13359 | |
| 13360 | |
| 13361 | SECTION .MyDATA_1 TEXT_VA = 0x00000000e0340000, DATA_VA = 0x0000000060340000 |
| 13362 | attr_text { |
| 13363 | Name = .MyDATA_1, |
| 13364 | RA = 0x0000000170300000, |
| 13365 | PA = ra2pa(0x0000000170300000,0), |
| 13366 | part_0_ctx_zero_tsb_config_0, |
| 13367 | part_0_ctx_nonzero_tsb_config_0, |
| 13368 | TTE_G = 1, |
| 13369 | TTE_Context = PCONTEXT, |
| 13370 | TTE_V = 1, |
| 13371 | TTE_Size = 3, |
| 13372 | TTE_NFO = 1, |
| 13373 | TTE_IE = 0, |
| 13374 | TTE_Soft2 = 0, |
| 13375 | TTE_Diag = 0, |
| 13376 | TTE_Soft = 0, |
| 13377 | TTE_L = 0, |
| 13378 | TTE_CP = 0, |
| 13379 | TTE_CV = 0, |
| 13380 | TTE_E = 0, |
| 13381 | TTE_P = 1, |
| 13382 | TTE_W = 1 |
| 13383 | } |
| 13384 | |
| 13385 | |
| 13386 | attr_data { |
| 13387 | Name = .MyDATA_1, |
| 13388 | RA = 0x0000000170300000, |
| 13389 | PA = ra2pa(0x0000000170300000,0), |
| 13390 | part_0_ctx_zero_tsb_config_1, |
| 13391 | part_0_ctx_nonzero_tsb_config_1, |
| 13392 | TTE_G = 1, |
| 13393 | TTE_Context = SCONTEXT, |
| 13394 | TTE_V = 1, |
| 13395 | TTE_Size = 1, |
| 13396 | TTE_NFO = 1, |
| 13397 | TTE_IE = 0, |
| 13398 | TTE_Soft2 = 0, |
| 13399 | TTE_Diag = 0, |
| 13400 | TTE_Soft = 0, |
| 13401 | TTE_L = 0, |
| 13402 | TTE_CP = 1, |
| 13403 | TTE_CV = 1, |
| 13404 | TTE_E = 1, |
| 13405 | TTE_P = 1, |
| 13406 | TTE_W = 0, |
| 13407 | tsbonly |
| 13408 | } |
| 13409 | |
| 13410 | |
| 13411 | attr_data { |
| 13412 | Name = .MyDATA_1, |
| 13413 | hypervisor |
| 13414 | } |
| 13415 | |
| 13416 | |
| 13417 | attr_text { |
| 13418 | Name = .MyDATA_1, |
| 13419 | hypervisor |
| 13420 | } |
| 13421 | |
| 13422 | .data |
| 13423 | .xword 0xf468945bf19f6f3b |
| 13424 | .xword 0xfb93b56df5cbb74c |
| 13425 | .xword 0x345077d9766dbd71 |
| 13426 | .xword 0xf409994e4f4d5e30 |
| 13427 | .xword 0xedd976e4cb683205 |
| 13428 | .xword 0xc72ff9168ba8779d |
| 13429 | .xword 0x306a533008a1ce45 |
| 13430 | .xword 0x7d58f852be33459b |
| 13431 | .xword 0x072b9f251a9a59d8 |
| 13432 | .xword 0xe3efcf69fc28e6a6 |
| 13433 | .xword 0x1387e26f86831fd1 |
| 13434 | .xword 0xef7cb6b12b90164e |
| 13435 | .xword 0x6d3783891b2e2556 |
| 13436 | .xword 0x9532f579b3eac6f6 |
| 13437 | .xword 0x344f3413effcad20 |
| 13438 | .xword 0xe2caab67e7f7326e |
| 13439 | .xword 0x34c1bf90c0f1189d |
| 13440 | .xword 0x6fc230a26502b7b4 |
| 13441 | .xword 0xa35b82ce5217eaa0 |
| 13442 | .xword 0x0f2cda06708f2cf8 |
| 13443 | .xword 0x34edb2b23713f62d |
| 13444 | .xword 0x09c2b13f2e0595f0 |
| 13445 | .xword 0x8cadf4ce12ca788f |
| 13446 | .xword 0x1f7646d4870d47d8 |
| 13447 | .xword 0xc059ad64690318ee |
| 13448 | .xword 0x00aaa979cdebe07e |
| 13449 | .xword 0x6088f613ccad13f0 |
| 13450 | .xword 0x99d9e793ded44214 |
| 13451 | .xword 0x3587201e133646b5 |
| 13452 | .xword 0x8262571d093ca289 |
| 13453 | .xword 0x5748a9215048a8c6 |
| 13454 | .xword 0x224ed4cbd2519a52 |
| 13455 | |
| 13456 | |
| 13457 | |
| 13458 | SECTION .MyDATA_2 TEXT_VA = 0x00000000e0540000, DATA_VA = 0x0000000060540000 |
| 13459 | attr_text { |
| 13460 | Name = .MyDATA_2, |
| 13461 | RA = 0x0000000170500000, |
| 13462 | PA = ra2pa(0x0000000170500000,0), |
| 13463 | part_0_ctx_zero_tsb_config_0, |
| 13464 | part_0_ctx_nonzero_tsb_config_0, |
| 13465 | TTE_G = 1, |
| 13466 | TTE_Context = PCONTEXT, |
| 13467 | TTE_V = 1, |
| 13468 | TTE_Size = 3, |
| 13469 | TTE_NFO = 0, |
| 13470 | TTE_IE = 0, |
| 13471 | TTE_Soft2 = 0, |
| 13472 | TTE_Diag = 0, |
| 13473 | TTE_Soft = 0, |
| 13474 | TTE_L = 0, |
| 13475 | TTE_CP = 1, |
| 13476 | TTE_CV = 0, |
| 13477 | TTE_E = 1, |
| 13478 | TTE_P = 1, |
| 13479 | TTE_W = 0 |
| 13480 | } |
| 13481 | |
| 13482 | |
| 13483 | attr_data { |
| 13484 | Name = .MyDATA_2, |
| 13485 | RA = 0x0000000170500000, |
| 13486 | PA = ra2pa(0x0000000170500000,0), |
| 13487 | part_0_ctx_zero_tsb_config_1, |
| 13488 | part_0_ctx_nonzero_tsb_config_1, |
| 13489 | TTE_G = 1, |
| 13490 | TTE_Context = SCONTEXT, |
| 13491 | TTE_V = 1, |
| 13492 | TTE_Size = 5, |
| 13493 | TTE_NFO = 0, |
| 13494 | TTE_IE = 0, |
| 13495 | TTE_Soft2 = 0, |
| 13496 | TTE_Diag = 0, |
| 13497 | TTE_Soft = 0, |
| 13498 | TTE_L = 0, |
| 13499 | TTE_CP = 0, |
| 13500 | TTE_CV = 0, |
| 13501 | TTE_E = 1, |
| 13502 | TTE_P = 0, |
| 13503 | TTE_W = 0, |
| 13504 | tsbonly |
| 13505 | } |
| 13506 | |
| 13507 | |
| 13508 | attr_data { |
| 13509 | Name = .MyDATA_2, |
| 13510 | hypervisor |
| 13511 | } |
| 13512 | |
| 13513 | |
| 13514 | attr_text { |
| 13515 | Name = .MyDATA_2, |
| 13516 | hypervisor |
| 13517 | } |
| 13518 | |
| 13519 | .data |
| 13520 | .xword 0x2aff6c5c76d32178 |
| 13521 | .xword 0xb0cfa9d0e05722c0 |
| 13522 | .xword 0x4fff8753836fb6d8 |
| 13523 | .xword 0xeb492644f76d76ec |
| 13524 | .xword 0xe8e66bf07e8d29dc |
| 13525 | .xword 0x76b67f236fc26d5a |
| 13526 | .xword 0x33c0d559c7f16d60 |
| 13527 | .xword 0x663ea2a90beac5eb |
| 13528 | .xword 0x678ff0017b3bff1d |
| 13529 | .xword 0x9c154b418fd5f3b3 |
| 13530 | .xword 0x666832badc990800 |
| 13531 | .xword 0x43743edef6c79633 |
| 13532 | .xword 0xe1bbf091f9063fd8 |
| 13533 | .xword 0xbd232fe84eeb6cf9 |
| 13534 | .xword 0xfc9e269673852b97 |
| 13535 | .xword 0xdeaffb9ae77925ef |
| 13536 | .xword 0x62bfe0089792a3e9 |
| 13537 | .xword 0x0a0ebb0b6864e3b5 |
| 13538 | .xword 0xbd639dbbc07eac10 |
| 13539 | .xword 0x3da5b9bb5c98fc1e |
| 13540 | .xword 0x862c853feb8953a3 |
| 13541 | .xword 0x59a618b187550f91 |
| 13542 | .xword 0x3790c7c1f57bfc29 |
| 13543 | .xword 0x20103280fcff1b9d |
| 13544 | .xword 0x296e7d458ac00541 |
| 13545 | .xword 0x7bfa448d694a7445 |
| 13546 | .xword 0xd56c00ac96766058 |
| 13547 | .xword 0xc85b2192a36cd731 |
| 13548 | .xword 0x1b4119a700cba578 |
| 13549 | .xword 0x2a3d00892c04c61a |
| 13550 | .xword 0x65885026ab6f6a28 |
| 13551 | .xword 0xc303371ec71debba |
| 13552 | |
| 13553 | |
| 13554 | |
| 13555 | SECTION .MyDATA_3 TEXT_VA = 0x00000000e0740000, DATA_VA = 0x0000000060740000 |
| 13556 | attr_text { |
| 13557 | Name = .MyDATA_3, |
| 13558 | RA = 0x0000000170700000, |
| 13559 | PA = ra2pa(0x0000000170700000,0), |
| 13560 | part_0_ctx_zero_tsb_config_0, |
| 13561 | part_0_ctx_nonzero_tsb_config_0, |
| 13562 | TTE_G = 1, |
| 13563 | TTE_Context = PCONTEXT, |
| 13564 | TTE_V = 1, |
| 13565 | TTE_Size = 0, |
| 13566 | TTE_NFO = 0, |
| 13567 | TTE_IE = 0, |
| 13568 | TTE_Soft2 = 0, |
| 13569 | TTE_Diag = 0, |
| 13570 | TTE_Soft = 0, |
| 13571 | TTE_L = 0, |
| 13572 | TTE_CP = 0, |
| 13573 | TTE_CV = 0, |
| 13574 | TTE_E = 0, |
| 13575 | TTE_P = 0, |
| 13576 | TTE_W = 0 |
| 13577 | } |
| 13578 | |
| 13579 | |
| 13580 | attr_data { |
| 13581 | Name = .MyDATA_3, |
| 13582 | RA = 0x0000000170700000, |
| 13583 | PA = ra2pa(0x0000000170700000,0), |
| 13584 | part_0_ctx_zero_tsb_config_1, |
| 13585 | part_0_ctx_nonzero_tsb_config_1, |
| 13586 | TTE_G = 1, |
| 13587 | TTE_Context = SCONTEXT, |
| 13588 | TTE_V = 1, |
| 13589 | TTE_Size = 1, |
| 13590 | TTE_NFO = 1, |
| 13591 | TTE_IE = 0, |
| 13592 | TTE_Soft2 = 0, |
| 13593 | TTE_Diag = 0, |
| 13594 | TTE_Soft = 0, |
| 13595 | TTE_L = 0, |
| 13596 | TTE_CP = 0, |
| 13597 | TTE_CV = 0, |
| 13598 | TTE_E = 0, |
| 13599 | TTE_P = 1, |
| 13600 | TTE_W = 0, |
| 13601 | tsbonly |
| 13602 | } |
| 13603 | |
| 13604 | |
| 13605 | attr_data { |
| 13606 | Name = .MyDATA_3, |
| 13607 | hypervisor |
| 13608 | } |
| 13609 | |
| 13610 | |
| 13611 | attr_text { |
| 13612 | Name = .MyDATA_3, |
| 13613 | hypervisor |
| 13614 | } |
| 13615 | |
| 13616 | .data |
| 13617 | .xword 0x769e7c0636c03b5d |
| 13618 | .xword 0x1a8ba01a06a805a5 |
| 13619 | .xword 0x4bed03ec5eda3a4c |
| 13620 | .xword 0x46ec812540882e7c |
| 13621 | .xword 0xb86e91598998e104 |
| 13622 | .xword 0x6ac53040e3892977 |
| 13623 | .xword 0x3f4c61a4f9df43a1 |
| 13624 | .xword 0xc81b1305eb470d46 |
| 13625 | .xword 0xfa2250f2f799ab72 |
| 13626 | .xword 0xffb9a2e1c3c84d85 |
| 13627 | .xword 0x37c242b4a99c43f7 |
| 13628 | .xword 0x79552f42be2aac42 |
| 13629 | .xword 0xdf9f273386b6cb6d |
| 13630 | .xword 0x7d15d141e1c5e4bd |
| 13631 | .xword 0xa02bb41eb4fdac1a |
| 13632 | .xword 0x6379ae5a70dceb3e |
| 13633 | .xword 0x8284c1824081c9fa |
| 13634 | .xword 0xb21e9033768f4869 |
| 13635 | .xword 0x86517c8fff76dbe0 |
| 13636 | .xword 0xb9936f0ae784b0da |
| 13637 | .xword 0x063b7334cdbe093f |
| 13638 | .xword 0x373cd21b8c5379a4 |
| 13639 | .xword 0x4c637c14f356d971 |
| 13640 | .xword 0xf00078bfbe613ba2 |
| 13641 | .xword 0xf7998f9af29e18ed |
| 13642 | .xword 0xbd34058ae405b425 |
| 13643 | .xword 0xd6f488c77f46a9da |
| 13644 | .xword 0x864bfe5fd8584dbf |
| 13645 | .xword 0x6f2c4b93307a9d51 |
| 13646 | .xword 0x7b5a2cfd1e02b1fc |
| 13647 | .xword 0x5c8fd69a501bc7d5 |
| 13648 | .xword 0xdc98896c5504327d |
| 13649 | |
| 13650 | |
| 13651 | |
| 13652 | |
| 13653 | |
| 13654 | SECTION .MyTEXT_0 TEXT_VA = 0x00000000e0200000 |
| 13655 | attr_text { |
| 13656 | Name = .MyTEXT_0, |
| 13657 | RA = 0x00000000e0200000, |
| 13658 | PA = ra2pa(0x00000000e0200000,0), |
| 13659 | part_0_ctx_zero_tsb_config_1, |
| 13660 | part_0_ctx_nonzero_tsb_config_1, |
| 13661 | TTE_G = 1, |
| 13662 | TTE_Context = PCONTEXT, |
| 13663 | TTE_V = 1, |
| 13664 | TTE_Size = 3, |
| 13665 | TTE_NFO = 0, |
| 13666 | TTE_IE = 1, |
| 13667 | TTE_Soft2 = 0, |
| 13668 | TTE_Diag = 0, |
| 13669 | TTE_Soft = 0, |
| 13670 | TTE_L = 0, |
| 13671 | TTE_CP = 1, |
| 13672 | TTE_CV = 1, |
| 13673 | TTE_E = 0, |
| 13674 | TTE_P = 1, |
| 13675 | TTE_W = 1 |
| 13676 | } |
| 13677 | |
| 13678 | .text |
| 13679 | nuff_said_0: |
| 13680 | fdivd %f0, %f4, %f6 |
| 13681 | mov HIGHVA_HIGHNUM, %r11 |
| 13682 | sllx %r11, 32, %r11 |
| 13683 | or %r27, %r11, %r27 |
| 13684 | jmpl %r27+8, %r0 |
| 13685 | jmpl %r27+8, %r0 |
| 13686 | jmpl %r27+8, %r0 |
| 13687 | jmpl %r27+8, %r0 |
| 13688 | fdivs %f0, %f4, %f6 |
| 13689 | |
| 13690 | |
| 13691 | |
| 13692 | SECTION .MyTEXT_1 TEXT_VA = 0x00000000e0a00000 |
| 13693 | attr_text { |
| 13694 | Name = .MyTEXT_1, |
| 13695 | RA = 0x00000000e0a00000, |
| 13696 | PA = ra2pa(0x00000000e0a00000,0), |
| 13697 | part_0_ctx_zero_tsb_config_1, |
| 13698 | part_0_ctx_nonzero_tsb_config_1, |
| 13699 | TTE_G = 1, |
| 13700 | TTE_Context = PCONTEXT, |
| 13701 | TTE_V = 1, |
| 13702 | TTE_Size = 3, |
| 13703 | TTE_NFO = 0, |
| 13704 | TTE_IE = 1, |
| 13705 | TTE_Soft2 = 0, |
| 13706 | TTE_Diag = 0, |
| 13707 | TTE_Soft = 0, |
| 13708 | TTE_L = 0, |
| 13709 | TTE_CP = 1, |
| 13710 | TTE_CV = 1, |
| 13711 | TTE_E = 0, |
| 13712 | TTE_P = 1, |
| 13713 | TTE_W = 1 |
| 13714 | } |
| 13715 | |
| 13716 | .text |
| 13717 | nuff_said_1: |
| 13718 | fdivs %f0, %f4, %f8 |
| 13719 | mov HIGHVA_HIGHNUM, %r11 |
| 13720 | sllx %r11, 32, %r11 |
| 13721 | or %r27, %r11, %r27 |
| 13722 | jmpl %r27+8, %r0 |
| 13723 | jmpl %r27+8, %r0 |
| 13724 | jmpl %r27+8, %r0 |
| 13725 | jmpl %r27+8, %r0 |
| 13726 | fdivd %f0, %f4, %f6 |
| 13727 | |
| 13728 | |
| 13729 | |
| 13730 | SECTION .MyTEXT_2 TEXT_VA = 0x00000000e1200000 |
| 13731 | attr_text { |
| 13732 | Name = .MyTEXT_2, |
| 13733 | RA = 0x00000000e1200000, |
| 13734 | PA = ra2pa(0x00000000e1200000,0), |
| 13735 | part_0_ctx_zero_tsb_config_1, |
| 13736 | part_0_ctx_nonzero_tsb_config_1, |
| 13737 | TTE_G = 1, |
| 13738 | TTE_Context = PCONTEXT, |
| 13739 | TTE_V = 1, |
| 13740 | TTE_Size = 1, |
| 13741 | TTE_NFO = 0, |
| 13742 | TTE_IE = 0, |
| 13743 | TTE_Soft2 = 0, |
| 13744 | TTE_Diag = 0, |
| 13745 | TTE_Soft = 0, |
| 13746 | TTE_L = 0, |
| 13747 | TTE_CP = 0, |
| 13748 | TTE_CV = 1, |
| 13749 | TTE_E = 1, |
| 13750 | TTE_P = 1, |
| 13751 | TTE_W = 1 |
| 13752 | } |
| 13753 | |
| 13754 | .text |
| 13755 | nuff_said_2: |
| 13756 | fdivd %f0, %f4, %f8 |
| 13757 | mov HIGHVA_HIGHNUM, %r11 |
| 13758 | sllx %r11, 32, %r11 |
| 13759 | or %r27, %r11, %r27 |
| 13760 | jmpl %r27+8, %r0 |
| 13761 | jmpl %r27+8, %r0 |
| 13762 | jmpl %r27+8, %r0 |
| 13763 | jmpl %r27+8, %r0 |
| 13764 | fdivs %f0, %f4, %f8 |
| 13765 | |
| 13766 | |
| 13767 | |
| 13768 | SECTION .MyTEXT_3 TEXT_VA = 0x00000000e1a00000 |
| 13769 | attr_text { |
| 13770 | Name = .MyTEXT_3, |
| 13771 | RA = 0x00000000e1a00000, |
| 13772 | PA = ra2pa(0x00000000e1a00000,0), |
| 13773 | part_0_ctx_zero_tsb_config_1, |
| 13774 | part_0_ctx_nonzero_tsb_config_1, |
| 13775 | TTE_G = 1, |
| 13776 | TTE_Context = PCONTEXT, |
| 13777 | TTE_V = 1, |
| 13778 | TTE_Size = 5, |
| 13779 | TTE_NFO = 0, |
| 13780 | TTE_IE = 0, |
| 13781 | TTE_Soft2 = 0, |
| 13782 | TTE_Diag = 0, |
| 13783 | TTE_Soft = 0, |
| 13784 | TTE_L = 0, |
| 13785 | TTE_CP = 1, |
| 13786 | TTE_CV = 1, |
| 13787 | TTE_E = 1, |
| 13788 | TTE_P = 0, |
| 13789 | TTE_W = 0 |
| 13790 | } |
| 13791 | |
| 13792 | .text |
| 13793 | nuff_said_3: |
| 13794 | fdivs %f0, %f4, %f6 |
| 13795 | mov HIGHVA_HIGHNUM, %r11 |
| 13796 | sllx %r11, 32, %r11 |
| 13797 | or %r27, %r11, %r27 |
| 13798 | jmpl %r27+8, %r0 |
| 13799 | jmpl %r27+8, %r0 |
| 13800 | jmpl %r27+8, %r0 |
| 13801 | jmpl %r27+8, %r0 |
| 13802 | fdivd %f0, %f4, %f4 |
| 13803 | |
| 13804 | |
| 13805 | |
| 13806 | |
| 13807 | |
| 13808 | SECTION .VaHOLE_0 TEXT_VA = 0x00007fffffffe000 |
| 13809 | attr_text { |
| 13810 | Name = .VaHOLE_0, |
| 13811 | RA = 0x00000000ffffe000, |
| 13812 | PA = ra2pa(0x00000000ffffe000,0), |
| 13813 | part_0_ctx_zero_tsb_config_1, |
| 13814 | part_0_ctx_nonzero_tsb_config_1, |
| 13815 | TTE_G = 1, |
| 13816 | TTE_Context = PCONTEXT, |
| 13817 | TTE_V = 1, |
| 13818 | TTE_Size = 1, |
| 13819 | TTE_NFO = 0, |
| 13820 | TTE_IE = 1, |
| 13821 | TTE_Soft2 = 0, |
| 13822 | TTE_Diag = 0, |
| 13823 | TTE_Soft = 0, |
| 13824 | TTE_L = 0, |
| 13825 | TTE_CP = 1, |
| 13826 | TTE_CV = 1, |
| 13827 | TTE_E = 1, |
| 13828 | TTE_P = 0, |
| 13829 | TTE_W = 0, |
| 13830 | TTE_X = 1 |
| 13831 | } |
| 13832 | |
| 13833 | .text |
| 13834 | .global vahole_target0 |
| 13835 | .text |
| 13836 | .global vahole_target1 |
| 13837 | .text |
| 13838 | .global vahole_target2 |
| 13839 | .text |
| 13840 | .global vahole_target3 |
| 13841 | nop |
| 13842 | .align 4096 |
| 13843 | nop |
| 13844 | .align 2048 |
| 13845 | nop |
| 13846 | .align 1024 |
| 13847 | nop |
| 13848 | .align 512 |
| 13849 | nop |
| 13850 | .align 256 |
| 13851 | nop |
| 13852 | .align 128 |
| 13853 | nop |
| 13854 | .align 64 |
| 13855 | nop |
| 13856 | nop |
| 13857 | .align 16 |
| 13858 | nop;nop;nop |
| 13859 | vahole_target0: nop;nop |
| 13860 | vahole_target1: nop |
| 13861 | vahole_target2: nop;nop;nop |
| 13862 | vahole_target3: nop;nop;nop |
| 13863 | |
| 13864 | |
| 13865 | |
| 13866 | |
| 13867 | |
| 13868 | SECTION .VaHOLEL_0 TEXT_VA = 0x00000000ffffe000 |
| 13869 | attr_text { |
| 13870 | Name = .VaHOLEL_0, |
| 13871 | RA = 0x00000000ffffe000, |
| 13872 | PA = ra2pa(0x00000000ffffe000,0), |
| 13873 | part_0_ctx_zero_tsb_config_0, |
| 13874 | part_0_ctx_nonzero_tsb_config_0, |
| 13875 | TTE_G = 1, |
| 13876 | TTE_Context = PCONTEXT, |
| 13877 | TTE_V = 1, |
| 13878 | TTE_Size = 5, |
| 13879 | TTE_NFO = 0, |
| 13880 | TTE_IE = 1, |
| 13881 | TTE_Soft2 = 0, |
| 13882 | TTE_Diag = 0, |
| 13883 | TTE_Soft = 0, |
| 13884 | TTE_L = 0, |
| 13885 | TTE_CP = 1, |
| 13886 | TTE_CV = 0, |
| 13887 | TTE_E = 0, |
| 13888 | TTE_P = 0, |
| 13889 | TTE_W = 0, |
| 13890 | TTE_X = 1, |
| 13891 | tsbonly |
| 13892 | } |
| 13893 | |
| 13894 | .text |
| 13895 | nop |
| 13896 | |
| 13897 | |
| 13898 | |
| 13899 | |
| 13900 | |
| 13901 | SECTION .ZERO_0 TEXT_VA = 0x0000000000000000 |
| 13902 | attr_text { |
| 13903 | Name = .ZERO_0, |
| 13904 | RA = 0x0000000000000000, |
| 13905 | PA = ra2pa(0x0000000000000000,0), |
| 13906 | part_0_ctx_zero_tsb_config_1, |
| 13907 | part_0_ctx_nonzero_tsb_config_1, |
| 13908 | TTE_G = 1, |
| 13909 | TTE_Context = 0x44, |
| 13910 | TTE_V = 1, |
| 13911 | TTE_Size = 5, |
| 13912 | TTE_NFO = 0, |
| 13913 | TTE_IE = 1, |
| 13914 | TTE_Soft2 = 0, |
| 13915 | TTE_Diag = 0, |
| 13916 | TTE_Soft = 0, |
| 13917 | TTE_L = 0, |
| 13918 | TTE_CP = 0, |
| 13919 | TTE_CV = 0, |
| 13920 | TTE_E = 0, |
| 13921 | TTE_P = 0, |
| 13922 | TTE_W = 1, |
| 13923 | TTE_X = 1 |
| 13924 | } |
| 13925 | |
| 13926 | |
| 13927 | .text |
| 13928 | mov HIGHVA_HIGHNUM, %r11 |
| 13929 | sllx %r11, 32, %r11 |
| 13930 | or %r27, %r11, %r27 |
| 13931 | jmpl %r27+8, %r0 |
| 13932 | nop |
| 13933 | nop |
| 13934 | jmpl %r27+8, %r0 |
| 13935 | nop |
| 13936 | |
| 13937 | Power_On_Reset: |
| 13938 | setx HRedmode_Reset_Handler, %g1, %g2 |
| 13939 | jmp %g2 |
| 13940 | nop |
| 13941 | .align 32 |
| 13942 | |
| 13943 | Watchdog_Reset: |
| 13944 | setx wdog_red_ext, %g1, %g2 |
| 13945 | jmp %g2 |
| 13946 | nop |
| 13947 | .align 32 |
| 13948 | |
| 13949 | External_Reset: |
| 13950 | My_External_Reset |
| 13951 | |
| 13952 | .align 32 |
| 13953 | |
| 13954 | Software_Initiated_Reset: |
| 13955 | setx Software_Reset_Handler, %g1, %g2 |
| 13956 | jmp %g2 |
| 13957 | nop |
| 13958 | |
| 13959 | .align 32 |
| 13960 | |
| 13961 | RED_Mode_Other_Reset: |
| 13962 | ! IF TL=6, shift stack by one .. |
| 13963 | rdpr %tl, %l1 |
| 13964 | cmp %l1, 6 |
| 13965 | be start_tsa_shift |
| 13966 | nop |
| 13967 | |
| 13968 | continue_red_other: |
| 13969 | mov 0x1f, %l1 |
| 13970 | stxa %l1, [%g0] ASI_LSU_CTL_REG |
| 13971 | |
| 13972 | rdpr %tt, %l1 |
| 13973 | |
| 13974 | rdhpr %htstate, %l2 |
| 13975 | and %l2, 0x4, %l2 ! If previously in hpriv mode, go to hpriv |
| 13976 | brnz,a %l2, red_goto_handler |
| 13977 | rdhpr %htba, %l2 |
| 13978 | srlx %l1, 7, %l2 ! Send priv sw traps to priv mode .. |
| 13979 | cmp %l2, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap .. |
| 13980 | be,a red_goto_handler |
| 13981 | rdpr %tba, %l2 |
| 13982 | rdhpr %htba, %l2 |
| 13983 | red_goto_handler: |
| 13984 | |
| 13985 | sllx %l1, 5, %l1 |
| 13986 | add %l1, %l2, %l2 |
| 13987 | rdhpr %hpstate, %l1 |
| 13988 | jmp %l2 |
| 13989 | wrhpr %l1, 0x20, %hpstate |
| 13990 | nop |
| 13991 | |
| 13992 | wdog_red_ext: |
| 13993 | ! Shift stack down by 1 ... |
| 13994 | rdpr %tl, %l1 |
| 13995 | cmp %l1, 6 |
| 13996 | bl wdog_end |
| 13997 | start_tsa_shift: |
| 13998 | mov 0x2, %l2 |
| 13999 | |
| 14000 | tsa_shift: |
| 14001 | wrpr %l2, %tl |
| 14002 | rdpr %tt, %l3 |
| 14003 | rdpr %tpc, %l4 |
| 14004 | rdpr %tnpc, %l5 |
| 14005 | rdpr %tstate, %l6 |
| 14006 | rdhpr %htstate, %l7 |
| 14007 | dec %l2 |
| 14008 | wrpr %l2, %tl |
| 14009 | wrpr %l3, %tt |
| 14010 | wrpr %l4, %tpc |
| 14011 | wrpr %l5, %tnpc |
| 14012 | wrpr %l6, %tstate |
| 14013 | wrhpr %l7, %htstate |
| 14014 | add %l2, 2, %l2 |
| 14015 | cmp %l2, %l1 |
| 14016 | ble tsa_shift |
| 14017 | nop |
| 14018 | tsa_shift_done: |
| 14019 | dec %l1 |
| 14020 | wrpr %l1, %tl |
| 14021 | |
| 14022 | wdog_end: |
| 14023 | ! If TT != 2, then goto trap handler |
| 14024 | rdpr %tt, %l1 |
| 14025 | |
| 14026 | cmp %l1, 0x2 |
| 14027 | bne continue_red_other |
| 14028 | nop |
| 14029 | ! else done |
| 14030 | mov 0x1f, %l1 |
| 14031 | stxa %l1, [%g0] ASI_LSU_CTL_REG |
| 14032 | done |
| 14033 | |
| 14034 | |
| 14035 | |
| 14036 | |
| 14037 | |
| 14038 | SECTION .VaHOLE_PA_0 TEXT_VA = 0x000000ffffffe000 |
| 14039 | attr_text { |
| 14040 | Name = .VAHOLE_PA_0, |
| 14041 | hypervisor |
| 14042 | } |
| 14043 | |
| 14044 | nop |
| 14045 | .align 4096 |
| 14046 | nop |
| 14047 | .align 2048 |
| 14048 | nop |
| 14049 | .align 1024 |
| 14050 | nop |
| 14051 | .align 512 |
| 14052 | nop |
| 14053 | .align 256 |
| 14054 | nop |
| 14055 | .align 128 |
| 14056 | nop |
| 14057 | .align 64 |
| 14058 | nop |
| 14059 | nop |
| 14060 | .align 16 |
| 14061 | nop;nop;nop |
| 14062 | nop |
| 14063 | nop |
| 14064 | jmpl %r27+8, %r0 |
| 14065 | nop |
| 14066 | nop |
| 14067 | nop |
| 14068 | jmpl %r27+8, %r0 |
| 14069 | nop |
| 14070 | |
| 14071 | |
| 14072 | |
| 14073 | |
| 14074 | |
| 14075 | SECTION .MASKEDHOLE_0 TEXT_VA = 0x0000000100000000 |
| 14076 | attr_text { |
| 14077 | Name = .MASKEDHOLE_0, |
| 14078 | RA = 0x0000000000000000, |
| 14079 | PA = ra2pa(0x0000000000000000,0), |
| 14080 | part_0_ctx_zero_tsb_config_3, |
| 14081 | part_0_ctx_nonzero_tsb_config_3, |
| 14082 | TTE_G = 1, |
| 14083 | TTE_Context = 0x44, |
| 14084 | TTE_V = 1, |
| 14085 | TTE_Size = 1, |
| 14086 | TTE_NFO = 0, |
| 14087 | TTE_IE = 1, |
| 14088 | TTE_Soft2 = 0, |
| 14089 | TTE_Diag = 0, |
| 14090 | TTE_Soft = 0, |
| 14091 | TTE_L = 0, |
| 14092 | TTE_CP = 0, |
| 14093 | TTE_CV = 0, |
| 14094 | TTE_E = 0, |
| 14095 | TTE_P = 0, |
| 14096 | TTE_W = 0, |
| 14097 | TTE_X = 1, |
| 14098 | tsbonly |
| 14099 | } |
| 14100 | |
| 14101 | |
| 14102 | attr_text { |
| 14103 | Name = .MASKEDHOLE_0, |
| 14104 | hypervisor |
| 14105 | } |
| 14106 | |
| 14107 | mov HIGHVA_HIGHNUM, %r11 |
| 14108 | sllx %r11, 32, %r11 |
| 14109 | or %r27, %r11, %r27 |
| 14110 | jmpl %r27+8, %r0 |
| 14111 | nop |
| 14112 | |
| 14113 | |
| 14114 | |
| 14115 | #if 0 |
| 14116 | #endif |