| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: tlu_simulint.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | #define CREGS_PIL 0 |
| 40 | |
| 41 | #define H_HT0_Trap_Level_Zero_0x5f |
| 42 | #define My_HT0_Trap_Level_Zero_0x5f \ |
| 43 | rdhpr %hpstate, %l3;\ |
| 44 | and %l3, 0xfa, %l3;\ |
| 45 | wrhpr %l3, 0, %htstate;\ |
| 46 | retry |
| 47 | |
| 48 | #define H_HT0_Trap_Instruction_0 |
| 49 | #define My_HT0_Trap_Instruction_0 \ |
| 50 | rdpr %tpc, %g2;\ |
| 51 | rdpr %tnpc, %g3;\ |
| 52 | wrpr %g0, 1, %tl;\ |
| 53 | wrhpr %g0, 1, %htstate;\ |
| 54 | wrpr %g2, 0, %tpc;\ |
| 55 | wrpr %g3, 0, %tnpc;\ |
| 56 | not %g0, %g1;\ |
| 57 | mov CETER_VA, %g4;\ |
| 58 | stxa %g1, [%g4]0x4c;\ |
| 59 | done; |
| 60 | |
| 61 | #define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler |
| 62 | |
| 63 | #include "tlu_custom_intr_handlers.s" |
| 64 | #include "hboot.s" |
| 65 | |
| 66 | /************************************************************************ |
| 67 | Test case code start |
| 68 | ************************************************************************/ |
| 69 | |
| 70 | .text |
| 71 | .global main |
| 72 | |
| 73 | main: /* test begin */ |
| 74 | |
| 75 | ta T_CHANGE_HPRIV |
| 76 | |
| 77 | ta T_CHANGE_TO_TL1 |
| 78 | |
| 79 | disable_intr: |
| 80 | rdpr %pstate, %g1 |
| 81 | andn %g1, 2, %g1 |
| 82 | wrpr %g1, %pstate |
| 83 | mov CETER_VA, %g4 |
| 84 | stxa %g0, [%g4]0x4c |
| 85 | |
| 86 | setup_interrupts: |
| 87 | |
| 88 | mov 0xf, %g2 |
| 89 | sllx %g2, 32, %g3 |
| 90 | or %g2, %g3, %g2 |
| 91 | not %g2, %g2 |
| 92 | wr %g2, %g0, %pic |
| 93 | set 0x1ff8bfff, %g2 |
| 94 | wr %g2, %g0, %pcr |
| 95 | sllx %o1, 8, %g1 |
| 96 | or %o1, %g1, %g1 |
| 97 | inc %g1 |
| 98 | stxa %g1, [%g0] 0x73 |
| 99 | wr %g0, ASI_QUEUE, %asi |
| 100 | sllx %g1, 8, %g2 |
| 101 | stxa %g2, [ASI_CPU_MONDO_QUEUE_HEAD] %asi |
| 102 | stxa %g2, [ASI_DEVICE_QUEUE_HEAD] %asi |
| 103 | stxa %g2, [ASI_RES_ERROR_QUEUE_HEAD] %asi |
| 104 | stxa %g2, [ASI_NONRES_ERROR_QUEUE_HEAD] %asi |
| 105 | inc %g1 |
| 106 | sllx %g1, 8, %g2 |
| 107 | stxa %g2, [ASI_CPU_MONDO_QUEUE_TAIL] %asi |
| 108 | stxa %g2, [ASI_DEVICE_QUEUE_TAIL] %asi |
| 109 | stxa %g2, [ASI_RES_ERROR_QUEUE_TAIL] %asi |
| 110 | stxa %g2, [ASI_NONRES_ERROR_QUEUE_TAIL] %asi |
| 111 | |
| 112 | not %g0, %g1 |
| 113 | |
| 114 | wr %g1, %g0, %softint |
| 115 | wrhpr %g1, %hintp |
| 116 | |
| 117 | set (1<<31|1<<17|1), %g1 |
| 118 | stxa %g1, [%g0] ASI_ERROR_INJECT |
| 119 | stx %g0, [%g0] |
| 120 | stxa %g0, [%g0] ASI_ERROR_INJECT |
| 121 | |
| 122 | ta 0x30 |
| 123 | |
| 124 | mov 0x0f, %g1 |
| 125 | endloop: |
| 126 | brnz %g1, endloop |
| 127 | dec %g1 |
| 128 | |
| 129 | EXIT_GOOD /* test finish */ |
| 130 | |
| 131 | /************************************************************************ |
| 132 | Test case data start |
| 133 | ************************************************************************/ |
| 134 | .data |
| 135 | |
| 136 | user_data_start: |
| 137 | .word 0xD6B3479D |
| 138 | .word 0xDB28926C |
| 139 | .end |
| 140 | |
| 141 | |