| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_dimm_cfg_1c2r.diaglist |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #ifndef SYSNAME |
| 36 | # ifdef FC8 |
| 37 | // // FC8 parameters |
| 38 | # define SYSNAME fc8 |
| 39 | # define sys(x) mss_fc8_ ## x |
| 40 | # else |
| 41 | // // FC1 parameters |
| 42 | # define SYSNAME fc1 |
| 43 | # define sys(x) mss_fc1_ ## x |
| 44 | # endif |
| 45 | #endif |
| 46 | // |
| 47 | #ifdef SETMODREL |
| 48 | # define MODREL_1c2r -vcs_rel_name=fc1_dimm8_2rank_sng |
| 49 | #else |
| 50 | # define MODREL_1c2r |
| 51 | #endif |
| 52 | // |
| 53 | //============================================================================== |
| 54 | // |
| 55 | <sys(dimmCfg_1c2r) name=sys(dimmCfg_1c2r)> |
| 56 | // |
| 57 | //============================================================================== |
| 58 | |
| 59 | <sys(build_dimmCfg_1c2r) sys=SYSNAME -sunv_run -vcs_build -zeroIn_build -config_rtl=ZIN_USE_CORE_CHECKERS -vcs_build_args=+define+DEBUG_PIPE -vcs_build_args=+define+FBDIMM_NUM_8 -vcs_build_args=+define+SNG_CHANNEL -vcs_build_args=+define+STACK_DIMM> |
| 60 | |
| 61 | // |
| 62 | //============================================================================== |
| 63 | // |
| 64 | <runargs -vcs_run -sas -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DPART_0_BASE=0x80000000 -vcs_run_args=+l2esr_mon_off -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+noDebugChecks -max_cycle=+10000000 -vcs_run_args=+TIMEOUT=250000 -rtl_timeout=100000000 -vcs_run_args=+th_timeout=100000000 -vcs_run_args=+skt_timeout=100000000 -tg_seed=1 -midas_args=-DDISABLE_ALL_CACHES -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+STACK_DIMM -drm_freeram=2000 -drm_freeswap=2000 -drm_type=rgrs -regress MODREL_1c2r -nosaslog -midas_args=-DHBOOT_HV_ONLY -vcs_run_args=+err_chkrs_off -vcs_run_args=+PEU_TEST> |
| 65 | // |
| 66 | //============================================================================== |
| 67 | // |
| 68 | indra_mcu_1c2r_Dma0Cac1Mcu1Tog0_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu1Tog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+STACK_DIMM -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_512 |
| 69 | indra_mcu_1c2r_Dma0Cac1Mcu1Tog1_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu1Tog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G |
| 70 | indra_mcu_1c2r_Dma0Cac1Mcu1Tog2_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu1Tog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+STACK_DIMM -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G |
| 71 | indra_mcu_1c2r_Dma0Cac1Mcu1Tog3_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu1Tog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_2G |
| 72 | indra_mcu_1c2r_Dma0Cac1Mcu2Tog0_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu2Tog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_2G |
| 73 | indra_mcu_1c2r_Dma0Cac1Mcu2Tog1_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu2Tog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+STACK_DIMM -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G |
| 74 | indra_mcu_1c2r_Dma0Cac1Mcu2Tog2_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu2Tog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G |
| 75 | indra_mcu_1c2r_Dma0Cac1Mcu2Tog3_rand_0 indra_mcu_1c2r_Dma0Cac1Mcu2Tog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_512 |
| 76 | indra_mcu_1c2r_Dma0Cac1McurTog0_rand_0 indra_mcu_1c2r_Dma0Cac1McurTog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_512 |
| 77 | indra_mcu_1c2r_Dma0Cac1McurTog1_rand_0 indra_mcu_1c2r_Dma0Cac1McurTog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G |
| 78 | indra_mcu_1c2r_Dma0Cac1McurTog2_rand_0 indra_mcu_1c2r_Dma0Cac1McurTog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+STACK_DIMM -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_2G |
| 79 | indra_mcu_1c2r_Dma0Cac1McurTog3_rand_0 indra_mcu_1c2r_Dma0Cac1McurTog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+STACK_DIMM -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G |
| 80 | // |
| 81 | // ========================================================================================= |
| 82 | // |
| 83 | </runargs> |
| 84 | // |
| 85 | // ========================================================================================= |
| 86 | // |
| 87 | <runargs -vcs_run -sas -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DPART_0_BASE=0x80000000 -vcs_run_args=+l2esr_mon_off -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+noDebugChecks -max_cycle=+10000000 -vcs_run_args=+TIMEOUT=250000 -rtl_timeout=100000000 -vcs_run_args=+th_timeout=100000000 -vcs_run_args=+skt_timeout=100000000 -tg_seed=1 -midas_args=-DDISABLE_ALL_CACHES -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+STACK_DIMM -drm_freeram=2000 -drm_freeswap=2000 -drm_type=rgrs -regress MODREL_1c2r> |
| 88 | // |
| 89 | // ========================================================================================= |
| 90 | // |
| 91 | // 18 diags generated from MPGen |
| 92 | // |
| 93 | mpgen_1ch_hi_2g_2r_4fb mpgen_1ch_hi_2g_2r_4fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+4_FBDIMMS |
| 94 | mpgen_1ch_hi_2g_2r_2fb mpgen_1ch_hi_2g_2r_2fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+2_FBDIMMS |
| 95 | mpgen_1ch_hi_2g_2r_1fb mpgen_1ch_hi_2g_2r_1fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+1_FBDIMM |
| 96 | mpgen_1ch_hi_1g_2r_4fb mpgen_1ch_hi_1g_2r_4fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+4_FBDIMMS |
| 97 | mpgen_1ch_hi_1g_2r_2fb mpgen_1ch_hi_1g_2r_2fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+2_FBDIMMS |
| 98 | mpgen_1ch_hi_1g_2r_1fb mpgen_1ch_hi_1g_2r_1fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+1_FBDIMM |
| 99 | mpgen_1ch_hi_0g_2r_4fb mpgen_1ch_hi_0g_2r_4fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+4_FBDIMMS |
| 100 | mpgen_1ch_hi_0g_2r_2fb mpgen_1ch_hi_0g_2r_2fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+2_FBDIMMS |
| 101 | mpgen_1ch_hi_0g_2r_1fb mpgen_1ch_hi_0g_2r_1fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+1_FBDIMM |
| 102 | mpgen_1ch_lo_2g_2r_4fb mpgen_1ch_lo_2g_2r_4fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+4_FBDIMMS |
| 103 | mpgen_1ch_lo_2g_2r_2fb mpgen_1ch_lo_2g_2r_2fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+2_FBDIMMS |
| 104 | mpgen_1ch_lo_2g_2r_1fb mpgen_1ch_lo_2g_2r_1fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+1_FBDIMM |
| 105 | mpgen_1ch_lo_1g_2r_4fb mpgen_1ch_lo_1g_2r_4fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+4_FBDIMMS |
| 106 | mpgen_1ch_lo_1g_2r_2fb mpgen_1ch_lo_1g_2r_2fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+2_FBDIMMS |
| 107 | mpgen_1ch_lo_1g_2r_1fb mpgen_1ch_lo_1g_2r_1fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+1_FBDIMM |
| 108 | mpgen_1ch_lo_0g_2r_4fb mpgen_1ch_lo_0g_2r_4fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+4_FBDIMMS |
| 109 | mpgen_1ch_lo_0g_2r_2fb mpgen_1ch_lo_0g_2r_2fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+2_FBDIMMS |
| 110 | mpgen_1ch_lo_0g_2r_1fb mpgen_1ch_lo_0g_2r_1fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+1_FBDIMM |
| 111 | |
| 112 | </runargs> |
| 113 | |
| 114 | </sys(build_dimmCfg_1c2r)> |
| 115 | |
| 116 | </sys(dimmCfg_1c2r)> |
| 117 | |
| 118 | //============================================================================== |