| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pm_spu.diaglist |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | <sys(spu_pm) name=sys(spu_pm)> |
| 36 | <sys(pm_all)> |
| 37 | |
| 38 | <sys(pm_spu)> |
| 39 | |
| 40 | <runargs -vcs_run_args=+show_delta -vcs_run_args=+show_memop -vcs_run_args=+8_FBDIMMS -midas_args=-DPART_0_BASE=0x200000000 -sas -midas_args=-allow_tsb_conflicts -fast_boot> |
| 41 | |
| 42 | //Core0_2bank |
| 43 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> |
| 44 | n2_pm_spu_Core0_Bank1 n2_sput0.s |
| 45 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 46 | n2_pm_spu_Core0_Bank1_DM n2_sput0.s |
| 47 | </runargs> |
| 48 | </runargs> |
| 49 | |
| 50 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=2 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> |
| 51 | n2_pm_spu_Core0_Bank2 n2_sput0.s |
| 52 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 53 | n2_pm_spu_Core0_Bank2_DM n2_sput0.s |
| 54 | </runargs> |
| 55 | </runargs> |
| 56 | |
| 57 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=4 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> |
| 58 | n2_pm_spu_Core0_Bank4 n2_sput0.s |
| 59 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 60 | n2_pm_spu_Core0_Bank4_DM n2_sput0.s |
| 61 | </runargs> |
| 62 | </runargs> |
| 63 | |
| 64 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=8 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> |
| 65 | n2_pm_spu_Core0_Bank8 n2_sput0.s |
| 66 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 67 | n2_pm_spu_Core0_Bank8_DM n2_sput0.s |
| 68 | </runargs> |
| 69 | </runargs> |
| 70 | |
| 71 | //Core0_4bank |
| 72 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> |
| 73 | n2_pm_spu_Core0_Bank3 n2_sput0.s |
| 74 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 75 | n2_pm_spu_Core0_Bank3_DM n2_sput0.s |
| 76 | </runargs> |
| 77 | </runargs> |
| 78 | |
| 79 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=c -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> |
| 80 | n2_pm_spu_Core0_Bankc n2_sput0.s |
| 81 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 82 | n2_pm_spu_Core0_Bankc_DM n2_sput0.s |
| 83 | </runargs> |
| 84 | </runargs> |
| 85 | |
| 86 | //Core1_2bank |
| 87 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 88 | n2_pm_spu_Core1_Bank1 sput8.s |
| 89 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 90 | n2_pm_spu_Core1_Bank1_DM sput8.s |
| 91 | </runargs> |
| 92 | </runargs> |
| 93 | |
| 94 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=2 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 95 | n2_pm_spu_Core1_Bank2 sput8.s |
| 96 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 97 | n2_pm_spu_Core1_Bank2_DM sput8.s |
| 98 | </runargs> |
| 99 | </runargs> |
| 100 | |
| 101 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=4 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 102 | n2_pm_spu_Core1_Bank4 sput8.s |
| 103 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 104 | n2_pm_spu_Core1_Bank4_DM sput8.s |
| 105 | </runargs> |
| 106 | </runargs> |
| 107 | |
| 108 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=8 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 109 | n2_pm_spu_Core1_Bank8 sput8.s |
| 110 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 111 | n2_pm_spu_Core1_Bank8_DM sput8.s |
| 112 | </runargs> |
| 113 | </runargs> |
| 114 | |
| 115 | //Core1_4bank |
| 116 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 117 | n2_pm_spu_Core1_Bank3 sput8.s |
| 118 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 119 | n2_pm_spu_Core1_Bank3_DM sput8.s |
| 120 | </runargs> |
| 121 | </runargs> |
| 122 | |
| 123 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=c -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 124 | n2_pm_spu_Core1_Bankc sput8.s |
| 125 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 126 | n2_pm_spu_Core1_Bankc_DM sput8.s |
| 127 | </runargs> |
| 128 | </runargs> |
| 129 | |
| 130 | //Core1_8bank |
| 131 | <runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x100 -finish_mask=100> |
| 132 | n2_pm_spu_Core1_Bank sput8.s |
| 133 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 134 | n2_pm_spu_Core1_Bank_DM sput8.s |
| 135 | </runargs> |
| 136 | </runargs> |
| 137 | |
| 138 | </runargs> |
| 139 | |
| 140 | </sys(pm_spu)> |
| 141 | |
| 142 | |
| 143 | </sys(pm_all)> |
| 144 | </sys(spu_pm)> |
| 145 | |