| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ilu_peu_cov.if.vrhpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #ifndef __ILU_PEU_COV_IF_VRH__ |
| 36 | #define __ILU_PEU_COV_IF_VRH__ |
| 37 | |
| 38 | #include <vera_defines.vrh> |
| 39 | |
| 40 | #define INPUT_EDGE PSAMPLE |
| 41 | #define INPUT_SKEW #-1 |
| 42 | |
| 43 | // define PEU tb_top.cpu.peu |
| 44 | #define ILU tb_top.cpu.dmu.ilu |
| 45 | // #define PSR tb_top.cpu.psr |
| 46 | // #define PEU_REGISTERS tb_top.cpu.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp |
| 47 | |
| 48 | |
| 49 | |
| 50 | interface dmu_ilu_coverage_ifc |
| 51 | { |
| 52 | //------------------------------------------------------------------------ |
| 53 | // Clock and Reset Signals |
| 54 | //------------------------------------------------------------------------ |
| 55 | // input cmp_diag_done PSAMPLE; |
| 56 | // input ilu_clk CLOCK verilog_node "`ILU.l1clk";// inputclock 375 MHz |
| 57 | // input ilu_clk CLOCK verilog_node "iol2clk";// inputclock 375 MHz |
| 58 | // input iol2clk CLOCK; |
| 59 | // input ilu_clk CLOCK; // verilog_node "iol2clk";// inputclock 375 MHz |
| 60 | // input ilu_clk CLOCK verilog_node "`TOP.cpu.dmu.iol2clk";// inputclock 375 MHz |
| 61 | input ilu_clk CLOCK verilog_node "tb_top.cpu.dmu.iol2clk";// inputclock 375 MHz |
| 62 | |
| 63 | // input peu_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.pc_clk"; |
| 64 | input j2d_por_l INPUT_EDGE INPUT_SKEW verilog_node "`PEU.rst_por_"; |
| 65 | input j2d_rst_l INPUT_EDGE INPUT_SKEW verilog_node "`PEU.rst_wmr_"; |
| 66 | // input [15:0] d2p_req_id INPUT_EDGE INPUT_SKEW verilog_node "`ILU.d2p_req_id"; |
| 67 | // input [15:0] d2p_req_id INPUT_EDGE INPUT_SKEW verilog_node "`PEU.d2p_req_id"; |
| 68 | input [2:0] d2p_req_id_1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.dmu.d2p_req_id[2:0]"; |
| 69 | input [4:0] d2p_req_id_2 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.dmu.d2p_req_id[7:3]"; |
| 70 | input [7:0] d2p_req_id_3 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.dmu.d2p_req_id[15:8]"; |
| 71 | |
| 72 | //------------------------------------------------------------------------ |
| 73 | // data path - |
| 74 | // note: k2y_buf_addr_vld_monitor & y2k_buf_addr_vld_monitor are added |
| 75 | // for the use in DMU-ILU monitor only |
| 76 | //------------------------------------------------------------------------ |
| 77 | input k2y_buf_addr_vld_monitor INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_buf_addr_vld_monitor"; |
| 78 | input [7:0] k2y_buf_addr INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_buf_addr";// read pointer to IDB |
| 79 | input [127:0] y2k_buf_data INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_data";// 16-byte data |
| 80 | input [3:0] y2k_buf_dpar INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_dpar";// data parity |
| 81 | input y2k_buf_addr_vld_monitor INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_addr_vld_monitor"; |
| 82 | input [7:0] y2k_buf_addr INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_addr";// read address to DOU |
| 83 | input [127:0] k2y_buf_data INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_buf_data";// payload |
| 84 | input [3:0] k2y_buf_dpar INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_buf_dpar";// word parity for the payload |
| 85 | |
| 86 | //------------------------------------------------------------------------ |
| 87 | // record interface to TMU |
| 88 | //------------------------------------------------------------------------ |
| 89 | input k2y_rcd_deq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_rcd_deq";// ingress record fifo dequeue |
| 90 | //DMU is 116 bits wide so add 10'b0 to LSB when hooking up to DMUXtr in ilu_peu_top.vcon |
| 91 | // input [125:0] y2k_rcd INPUT_EDGE INPUT_SKEW verilog_node "{`ILU.y2k_rcd,10'h0}";// ingress PEC record |
| 92 | input [115:0] y2k_rcd INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rcd";// ingress PEC record |
| 93 | input y2k_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rcd_enq";// ingress PEC record enqueue |
| 94 | // input [125:0] k2y_rcd INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_rcd";// egress PEC rcd |
| 95 | input [123:0] k2y_rcd INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_rcd";// egress PEC rcd |
| 96 | input k2y_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_rcd_enq";// egress enqueue for PEC rcd |
| 97 | input y2k_rcd_deq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rcd_deq";// egress rcd fifo dequeue |
| 98 | |
| 99 | //------------------------------------------------------------------------ |
| 100 | // release interface with TMU |
| 101 | //------------------------------------------------------------------------ |
| 102 | input [8:0] k2y_rel_rcd INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_rel_rcd";// ingress 1 PCIE FC data credit (16-byte data) w/ d_ptr |
| 103 | input k2y_rel_enq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_rel_enq"; // ingress enqueue for release record |
| 104 | input [8:0] y2k_rel_rcd INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rel_rcd";// egress release rcd |
| 105 | input y2k_rel_enq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rel_enq";// egress enqueue for release rcd |
| 106 | |
| 107 | //------------------------------------------------------------------------ |
| 108 | // DOU DMA Rd Cpl Buffer status rcd interface with CLU |
| 109 | //------------------------------------------------------------------------ |
| 110 | input [4:0] k2y_dou_dptr INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_dou_dptr"; |
| 111 | input k2y_dou_err INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_dou_err"; |
| 112 | input k2y_dou_vld INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_dou_vld"; |
| 113 | |
| 114 | //------------------------------------------------------------------------ |
| 115 | input ccu_serdes_dtm INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.dmu.ccu_serdes_dtm"; |
| 116 | // INput [1:0] dmu_psr_rate_scale_rx_b0sds0 INPUT_EDGE INPUT_SKEW verilog_node "`PSR.dmu_psr_rate_scale_rx_b0sds0[1:0]"; |
| 117 | input [1:0] dmu_psr_rate_scale_rx_b0sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b0sds0[1:0]"; |
| 118 | input [1:0] dmu_psr_rate_scale_rx_b0sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b0sds1[1:0]"; |
| 119 | input [1:0] dmu_psr_rate_scale_rx_b1sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b1sds0[1:0]"; |
| 120 | input [1:0] dmu_psr_rate_scale_rx_b1sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b1sds1[1:0]"; |
| 121 | input [1:0] dmu_psr_rate_scale_rx_b2sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b2sds0[1:0]"; |
| 122 | input [1:0] dmu_psr_rate_scale_rx_b2sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b2sds1[1:0]"; |
| 123 | input [1:0] dmu_psr_rate_scale_rx_b3sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b3sds0[1:0]"; |
| 124 | input [1:0] dmu_psr_rate_scale_rx_b3sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_rx_b3sds1[1:0]"; |
| 125 | input [1:0] dmu_psr_rate_scale_tx_b0sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b0sds0[1:0]"; |
| 126 | input [1:0] dmu_psr_rate_scale_tx_b0sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b0sds1[1:0]"; |
| 127 | input [1:0] dmu_psr_rate_scale_tx_b1sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b1sds0[1:0]"; |
| 128 | input [1:0] dmu_psr_rate_scale_tx_b1sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b1sds1[1:0]"; |
| 129 | input [1:0] dmu_psr_rate_scale_tx_b2sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b2sds0[1:0]"; |
| 130 | input [1:0] dmu_psr_rate_scale_tx_b2sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b2sds1[1:0]"; |
| 131 | input [1:0] dmu_psr_rate_scale_tx_b3sds0 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b3sds0[1:0]"; |
| 132 | input [1:0] dmu_psr_rate_scale_tx_b3sds1 INPUT_EDGE INPUT_SKEW verilog_node "tb_top.cpu.psr.dmu_psr_rate_scale_tx_b3sds1[1:0]"; |
| 133 | //------------------------------------------------------------------------ |
| 134 | |
| 135 | //------------------------------------------------------------------------ |
| 136 | // DMU misc. interface |
| 137 | //------------------------------------------------------------------------ |
| 138 | input [2:0] y2k_mps INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_mps";// max. payld size to CMU |
| 139 | input y2k_int_l INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_int_l";// interrupt req to IMU |
| 140 | input p2d_drain INPUT_EDGE INPUT_SKEW verilog_node "`ILU.p2d_drain"; // drain req to ILU |
| 141 | |
| 142 | //------------------------------------------------------------------------ |
| 143 | // CSR ring to DMU |
| 144 | //------------------------------------------------------------------------ |
| 145 | input [31:0] k2y_csr_ring_out INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_csr_ring_out"; |
| 146 | input [31:0] y2k_csr_ring_in INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_csr_ring_in"; |
| 147 | |
| 148 | //------------------------------------------------------------------------ |
| 149 | // debug ports |
| 150 | //------------------------------------------------------------------------ |
| 151 | input [5:0] k2y_dbg_sel_a INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_dbg_sel_a"; |
| 152 | input [5:0] k2y_dbg_sel_b INPUT_EDGE INPUT_SKEW verilog_node "`ILU.k2y_dbg_sel_b"; |
| 153 | input [7:0] y2k_dbg_a INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_dbg_a"; |
| 154 | input [7:0] y2k_dbg_b INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_dbg_b"; |
| 155 | |
| 156 | //------------------------------------------------------------------------ |
| 157 | // ILU to PEU interface |
| 158 | //------------------------------------------------------------------------ |
| 159 | input p2d_ue_int INPUT_EDGE INPUT_SKEW verilog_node "`PEU.p2d_ue_int"; |
| 160 | input p2d_ce_int INPUT_EDGE INPUT_SKEW verilog_node "`PEU.p2d_ce_int"; |
| 161 | input p2d_oe_int INPUT_EDGE INPUT_SKEW verilog_node "`PEU.p2d_oe_int"; |
| 162 | |
| 163 | } // end of interface if_ILU_PEU |
| 164 | |
| 165 | |
| 166 | |
| 167 | interface if_ILU_PEU_PCIE_coverage { |
| 168 | //Clock |
| 169 | input refclk CLOCK verilog_node "`TOP.PCIE_Clock_250";// inputclock 250 MHz |
| 170 | // Denali Clocks |
| 171 | input DEN_CLK_TX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.DEN_CLK_TX"; |
| 172 | input DEN_CLK_RX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.DEN_CLK_RX"; |
| 173 | |
| 174 | // Misc Port in FNXPCIEXactor |
| 175 | input DEN_RESET INPUT_EDGE INPUT_SKEW verilog_node "`TOP.DEN_RESET"; |
| 176 | |
| 177 | //The Recieve Detect signals were used in FNX , Included here but not connected to N2 |
| 178 | input RCV_DET_MODE INPUT_EDGE INPUT_SKEW;//1bit |
| 179 | |
| 180 | |
| 181 | // input [7:0] RCV_DET_LANES PRZ INPUT_SKEW verilog_node "`TOP.TX_P"; //8bit |
| 182 | |
| 183 | |
| 184 | } // end of interface if_ILU_PEU |
| 185 | |
| 186 | |
| 187 | |
| 188 | interface peu_registers_coverage_ifc |
| 189 | { |
| 190 | //------------------------------------------------------------------------ |
| 191 | // Clock and Reset Signals |
| 192 | //------------------------------------------------------------------------ |
| 193 | input peu_clk CLOCK verilog_node "`PEU.peu_ptl.l2t_clk"; |
| 194 | |
| 195 | // peu debug select b register |
| 196 | // input [2:0] peu_debug_select_a_block INPUT_EDGE INPUT_SKEW verilog_node "`PEU_REGISTERS.tlu_dbg_sel_a.tlu_dbg_sel_a_block_hw_read[2:0]"; |
| 197 | input [2:0] peu_debug_select_a_block INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_block_hw_read[2:0]"; |
| 198 | input [2:0] peu_debug_select_a_module INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_module_hw_read[2:0]"; |
| 199 | input [2:0] peu_debug_select_a_signal INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_signal_hw_read[2:0]"; |
| 200 | |
| 201 | |
| 202 | // peu debug select a register |
| 203 | input [2:0] peu_debug_select_b_block INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_block_hw_read[2:0]"; |
| 204 | input [2:0] peu_debug_select_b_module INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_module_hw_read[2:0]"; |
| 205 | input [2:0] peu_debug_select_b_signal INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_signal_hw_read[2:0]"; |
| 206 | |
| 207 | // peu control register |
| 208 | input [7:0] peu_control_reg_los_tim INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_l0s_tim_hw_read[7:0]"; |
| 209 | input peu_control_reg_npwr_en INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_npwr_en_hw_read"; |
| 210 | input [2:0] peu_control_reg_cto_sel INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_cto_sel_hw_read[2:0]"; |
| 211 | input [15:0 ] peu_control_reg_config INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_config_hw_read[15:0]"; |
| 212 | |
| 213 | // peu pme turn off register |
| 214 | input peu_trn_off_reg_pto INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.trn_off.trn_off_pto_hw_read"; |
| 215 | |
| 216 | // peu Ingress Credits Initial register |
| 217 | input [7:0] peu_ici_reg_nhc INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_nhc_hw_read[7:0]"; |
| 218 | input [7:0] peu_ici_reg_phc INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_phc_hw_read[7:0]"; |
| 219 | input [7:0] peu_ici_reg_pdc INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_pdc_hw_read[7:0]"; |
| 220 | |
| 221 | // peu performance counter select register |
| 222 | input [7:0] peu_prfc_reg_sel0 INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_sel0_hw_read[7:0]"; |
| 223 | input [7:0] peu_prfc_reg_sel1 INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_sel1_hw_read[7:0]"; |
| 224 | input [1:0] peu_prfc_reg_sel2 INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_sel2_hw_read[1:0]"; |
| 225 | |
| 226 | // peu device control register |
| 227 | input [2:0] peu_device_control_reg_mps INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.dev_ctl.dev_ctl_mps_hw_read[2:0]"; |
| 228 | |
| 229 | // peu diagnostic register |
| 230 | input [63:0] ilu_diagnos_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_csrbus_read_data[63:0]"; |
| 231 | // input [63:0] ilu_diagnos_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`tb_top.cpu.dmu.ilu.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_csrbus_read_data[63:0]"; |
| 232 | input [1:0] ilu_diagnos_rate_scale_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_rate_scale_hw_read[1:0]"; |
| 233 | input ilu_diagnos_ehi_trig_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_ehi_trig_hw_read"; |
| 234 | input ilu_diagnos_edi_trig_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_edi_trig_hw_read"; |
| 235 | input [3:0] ilu_diagnos_ehi_par_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_ehi_par_hw_read[3:0]"; |
| 236 | input [3:0] ilu_diagnos_edi_par_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_edi_par_hw_read[3:0]"; |
| 237 | input ilu_diagnos_enrx0_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx0_hw_read"; |
| 238 | input ilu_diagnos_enrx1_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx1_hw_read"; |
| 239 | input ilu_diagnos_enrx2_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx2_hw_read"; |
| 240 | input ilu_diagnos_enrx3_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx3_hw_read"; |
| 241 | input ilu_diagnos_enrx4_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx4_hw_read"; |
| 242 | input ilu_diagnos_enrx5_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx5_hw_read"; |
| 243 | input ilu_diagnos_enrx6_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx6_hw_read"; |
| 244 | input ilu_diagnos_enrx7_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enrx7_hw_read"; |
| 245 | input ilu_diagnos_entx0_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx0_hw_read"; |
| 246 | input ilu_diagnos_entx1_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx1_hw_read"; |
| 247 | input ilu_diagnos_entx2_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx2_hw_read"; |
| 248 | input ilu_diagnos_entx3_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx3_hw_read"; |
| 249 | input ilu_diagnos_entx4_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx4_hw_read"; |
| 250 | input ilu_diagnos_entx5_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx5_hw_read"; |
| 251 | input ilu_diagnos_entx6_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx6_hw_read"; |
| 252 | input ilu_diagnos_entx7_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_entx7_hw_read"; |
| 253 | input ilu_diagnos_enpll0_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enpll0_hw_read"; |
| 254 | input ilu_diagnos_enpll1_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_diagnos_enpll1_hw_read"; |
| 255 | |
| 256 | // peu link control register |
| 257 | input peu_link_control_reg_extended_sync INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[7]"; |
| 258 | input peu_link_control_reg_common_clock INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[6]"; |
| 259 | input peu_link_control_reg_retrain INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[5]"; |
| 260 | input peu_link_control_reg_disable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[4]"; |
| 261 | input peu_link_control_reg_rcb INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[3]"; |
| 262 | input [1:0] peu_link_control_reg_aspm INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_hw_read[1:0]"; |
| 263 | |
| 264 | // peu link status register |
| 265 | input peu_link_status_reg_slot_clock INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_hw_read[12]"; |
| 266 | input peu_link_status_reg_train INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_hw_read[11]"; |
| 267 | input peu_link_status_reg_error INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_hw_read[10]"; |
| 268 | input [5:0] peu_link_status_reg_width INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_hw_read[9:4]"; |
| 269 | input [3:0] peu_link_status_reg_speed INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_hw_read[3:0]"; |
| 270 | |
| 271 | |
| 272 | // peu slot capability register ?????????? to add |
| 273 | // input peu_link_status_reg_slot_clock INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_sts_hw_read[12]"; |
| 274 | input [1:0] peu_slot_cap_register_spls INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.rio.spl_rcd[9:8]"; |
| 275 | input [7:0] peu_slot_cap_register_splv INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.rio.spl_rcd[7:0]"; |
| 276 | |
| 277 | // peu dlpl dll control register |
| 278 | input [7:0] peu_dlpl_dll_control_reg_ack_freq INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_ack_freq_hw_read[7:0]"; |
| 279 | input peu_dlpl_dll_control_reg_flow_disable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_csrbus_read_data[4]"; |
| 280 | input peu_dlpl_dll_control_reg_other_message_req INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_other_message_request_hw_read"; |
| 281 | input peu_dlpl_dll_control_reg_ack_nak_disable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_ack_nak_disable_hw_read"; |
| 282 | input peu_dlpl_dll_control_reg_data_link_en INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_data_link_enable_hw_read"; |
| 283 | |
| 284 | // peu dlpl macl / pcs control register |
| 285 | input [7:0] peu_dlpl_macl_control_reg_link_num INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_link_num_hw_read[7:0]"; |
| 286 | input [7:0] peu_dlpl_macl_control_reg_nfts INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_n_fts_hw_read[7:0]"; |
| 287 | input [5:0] peu_dlpl_macl_control_reg_link_capable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_link_capable_hw_read[5:0]"; |
| 288 | input peu_dlpl_macl_control_reg_fast_link_mode INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_fast_link_mode_hw_read"; |
| 289 | input peu_dlpl_macl_control_reg_elastic_buffer_disable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_elastical_buffer_disable_hw_read"; |
| 290 | input peu_dlpl_macl_control_reg_scramble_disable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_scramble_disable_hw_read"; |
| 291 | input peu_dlpl_macl_control_reg_reset_assert INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_reset_assert_hw_read"; |
| 292 | |
| 293 | |
| 294 | // peu dlpl lane skew control register |
| 295 | input peu_dlpl_lane_skew_reg_deskew_disable INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lane_skew.lane_skew_deskew_disable_hw_read"; |
| 296 | |
| 297 | |
| 298 | // peu dlpl symbol number register |
| 299 | input [2:0] peu_dlpl_sym_num_reg_skip INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_num.symbol_num_skip_symbols_hw_read[2:0]"; |
| 300 | input [3:0] peu_dlpl_sym_num_reg_ts1 INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_num.symbol_num_ts1_symbols_hw_read[3:0]"; |
| 301 | |
| 302 | // peu dlpl symbol timer register |
| 303 | input [10:0] peu_dlpl_sym_timer_reg_skip_interval INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_timer.symbol_timer_skip_interval_hw_read[10:0]"; |
| 304 | |
| 305 | |
| 306 | |
| 307 | |
| 308 | |
| 309 | |
| 310 | |
| 311 | |
| 312 | // peu link bit error counter I register |
| 313 | input peu_link_bit_error_counter_I_reg_ber_en INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_ber_count_en_ext_read_data"; |
| 314 | input peu_link_bit_error_counter_I_reg_ber_clr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_ber_count_clr_ext_read_data"; |
| 315 | |
| 316 | input [7:0] peu_link_bit_error_counter_I_reg_cnt_bad_dllp INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_cnt_bad_dllp_ext_read_data[7:0]"; |
| 317 | input [7:0] peu_link_bit_error_counter_I_reg_cnt_bad_tlp INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_cnt_bad_tlp_ext_read_data[7:0]"; |
| 318 | input [9:0] peu_link_bit_error_counter_I_reg_cnt_pre INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.lnk_bit_err_cnt_1_cnt_pre_ext_read_data[9:0]"; |
| 319 | |
| 320 | // peu link bit error counter II register |
| 321 | input [63:0] peu_link_bit_error_counter_II_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_bit_err_cnt_2_ext_read_data[63:0]"; |
| 322 | |
| 323 | // peu serdes pll control register |
| 324 | input [63:0] serdes_pll_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_pll_csrbus_read_data[63:0]"; |
| 325 | input [1:0] serdes_pll_lb_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_pll_lb_hw_read[1:0]"; |
| 326 | input [3:0] serdes_pll_mpy_hw_read INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_pll_mpy_hw_read[3:0]"; |
| 327 | |
| 328 | |
| 329 | // peu serdes receiver lane control register |
| 330 | input peu_ser_receiver_lane_ctl0_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_0[0]"; |
| 331 | input peu_ser_receiver_lane_ctl1_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_1[0]"; |
| 332 | input peu_ser_receiver_lane_ctl2_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_2[0]"; |
| 333 | input peu_ser_receiver_lane_ctl3_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_3[0]"; |
| 334 | input peu_ser_receiver_lane_ctl4_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_4[0]"; |
| 335 | input peu_ser_receiver_lane_ctl5_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_5[0]"; |
| 336 | input peu_ser_receiver_lane_ctl6_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_6[0]"; |
| 337 | input peu_ser_receiver_lane_ctl7_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_hw_read_7[0]"; |
| 338 | |
| 339 | |
| 340 | |
| 341 | // peu serdes transmitter lane control register |
| 342 | input peu_ser_xmitter_ctl_lane0_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_0[1]"; |
| 343 | input peu_ser_xmitter_ctl_lane1_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_1[1]"; |
| 344 | input peu_ser_xmitter_ctl_lane2_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_2[1]"; |
| 345 | input peu_ser_xmitter_ctl_lane3_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_3[1]"; |
| 346 | input peu_ser_xmitter_ctl_lane4_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_4[1]"; |
| 347 | input peu_ser_xmitter_ctl_lane5_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_5[1]"; |
| 348 | input peu_ser_xmitter_ctl_lane6_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_6[1]"; |
| 349 | input peu_ser_xmitter_ctl_lane7_reg_invert_polarity INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_7[1]"; |
| 350 | |
| 351 | |
| 352 | // peu serdes transmitter lane control register |
| 353 | input peu_ser_xmitter_ctl_lane0_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_0[0]"; |
| 354 | input peu_ser_xmitter_ctl_lane1_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_1[0]"; |
| 355 | input peu_ser_xmitter_ctl_lane2_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_2[0]"; |
| 356 | input peu_ser_xmitter_ctl_lane3_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_3[0]"; |
| 357 | input peu_ser_xmitter_ctl_lane4_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_4[0]"; |
| 358 | input peu_ser_xmitter_ctl_lane5_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_5[0]"; |
| 359 | input peu_ser_xmitter_ctl_lane6_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_6[0]"; |
| 360 | input peu_ser_xmitter_ctl_lane7_reg_entest INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_hw_read_7[0]"; |
| 361 | |
| 362 | //----------------------- |
| 363 | // register connections for above registers but with full register range |
| 364 | //----------------------- |
| 365 | |
| 366 | // debug_select_a |
| 367 | // input [8:0] peu_debug_select_a_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_csrbus_read_data[8:0]"; |
| 368 | input [63:0] peu_debug_select_a_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a.tlu_dbg_sel_a_csrbus_read_data[63:0]"; |
| 369 | |
| 370 | // input [8:0] peu_debug_select_b_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_csrbus_read_data[8:0]"; |
| 371 | input [63:0] peu_debug_select_b_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_b.tlu_dbg_sel_b_csrbus_read_data[63:0]"; |
| 372 | |
| 373 | // peu control register |
| 374 | // input [31:0] peu_control_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_csrbus_read_data[31:0]"; |
| 375 | input [63:0] peu_control_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_csrbus_read_data[63:0]"; |
| 376 | |
| 377 | // peu pme turn off register |
| 378 | input [63:0] peu_trn_off_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.trn_off.trn_off_csrbus_read_data[63:0] "; |
| 379 | |
| 380 | // peu Ingress Credits Initial register |
| 381 | // input [59:0] peu_ici_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_csrbus_read_data[59:0]"; |
| 382 | input [63:0] peu_ici_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_csrbus_read_data[63:0]"; |
| 383 | |
| 384 | // peu performance counter select register |
| 385 | // input [17:0] peu_prfc_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_csrbus_read_data[17:0]"; |
| 386 | input [63:0] peu_prfc_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_prfc.tlu_prfc_csrbus_read_data[63:0]"; |
| 387 | |
| 388 | // peu device control register |
| 389 | input [63:0] peu_device_control_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.dev_ctl.dev_ctl_csrbus_read_data[63:0]"; |
| 390 | |
| 391 | // peu link control register |
| 392 | input [63:0] peu_link_control_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_ctl.lnk_ctl_csrbus_read_data[63:0]"; |
| 393 | |
| 394 | // peu link status register |
| 395 | input [63:0] peu_link_status_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_sts.lnk_sts_csrbus_read_data[63:0]"; |
| 396 | |
| 397 | |
| 398 | // peu slot capability register |
| 399 | input [9:0] peu_slot_cap_register INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.rio.spl_rcd[9:0]"; |
| 400 | |
| 401 | // peu dlpl dll control register |
| 402 | input [63:0] peu_dlpl_dll_control_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_cfg.link_cfg_csrbus_read_data[63:0]"; |
| 403 | |
| 404 | // peu dlpl macl / pcs control register |
| 405 | input [63:0] peu_dlpl_macl_control_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.link_ctl.link_ctl_csrbus_read_data[63:0]"; |
| 406 | |
| 407 | |
| 408 | // peu dlpl lane skew control register |
| 409 | input [63:0] peu_dlpl_lane_skew_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lane_skew.lane_skew_csrbus_read_data"; |
| 410 | |
| 411 | |
| 412 | // peu dlpl symbol number register |
| 413 | input [63:0] peu_dlpl_sym_num_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_num.symbol_num_csrbus_read_data[63:0]"; |
| 414 | |
| 415 | // peu dlpl symbol timer register |
| 416 | input [63:0] peu_dlpl_sym_timer_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.symbol_timer.symbol_timer_csrbus_read_data[63:0]"; |
| 417 | |
| 418 | |
| 419 | input [63:0] peu_dlpl_core_status_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.core_status.core_status_csrbus_read_data[63:0]"; |
| 420 | |
| 421 | // peu link bit error counter I register |
| 422 | input [1:0] peu_link_bit_error_counter_I_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.lnk_bit_err_cnt_1_ext_read_data[63:62]"; |
| 423 | |
| 424 | // peu serdes receiver lane control register |
| 425 | input [63:0] peu_ser_receiver_lane_ctl0_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_csrbus_read_data_0[63:0]"; |
| 426 | |
| 427 | |
| 428 | // peu serdes transmitter lane control register |
| 429 | input [63:0] peu_ser_xmitter_ctl_lane0_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_0[63:0]"; |
| 430 | input [63:0] peu_ser_xmitter_ctl_lane1_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_1[63:0]"; |
| 431 | input [63:0] peu_ser_xmitter_ctl_lane2_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_2[63:0]"; |
| 432 | input [63:0] peu_ser_xmitter_ctl_lane3_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_3[63:0]"; |
| 433 | input [63:0] peu_ser_xmitter_ctl_lane4_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_4[63:0]"; |
| 434 | input [63:0] peu_ser_xmitter_ctl_lane5_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_5[63:0]"; |
| 435 | input [63:0] peu_ser_xmitter_ctl_lane6_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_6[63:0]"; |
| 436 | input [63:0] peu_ser_xmitter_ctl_lane7_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_csrbus_read_data_7[63:0]"; |
| 437 | |
| 438 | // peu serdes receiver lane status 0 - 7 register: |
| 439 | input [63:0] peu_ser_receiver_status_lane0_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_0[63:0]"; |
| 440 | input [63:0] peu_ser_receiver_status_lane1_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_1[63:0]"; |
| 441 | input [63:0] peu_ser_receiver_status_lane2_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_2[63:0]"; |
| 442 | input [63:0] peu_ser_receiver_status_lane3_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_3[63:0]"; |
| 443 | input [63:0] peu_ser_receiver_status_lane4_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_4[63:0]"; |
| 444 | input [63:0] peu_ser_receiver_status_lane5_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_5[63:0]"; |
| 445 | input [63:0] peu_ser_receiver_status_lane6_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_6[63:0]"; |
| 446 | input [63:0] peu_ser_receiver_status_lane7_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_csrbus_read_data_7[63:0]"; |
| 447 | |
| 448 | // peu serdes xmitter lane status 0 - 7 register: |
| 449 | input [63:0] peu_ser_xmitter_status_lane0_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_0[63:0]"; |
| 450 | input [63:0] peu_ser_xmitter_status_lane1_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_1[63:0]"; |
| 451 | input [63:0] peu_ser_xmitter_status_lane2_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_2[63:0]"; |
| 452 | input [63:0] peu_ser_xmitter_status_lane3_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_3[63:0]"; |
| 453 | input [63:0] peu_ser_xmitter_status_lane4_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_4[63:0]"; |
| 454 | input [63:0] peu_ser_xmitter_status_lane5_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_5[63:0]"; |
| 455 | input [63:0] peu_ser_xmitter_status_lane6_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_6[63:0]"; |
| 456 | input [63:0] peu_ser_xmitter_status_lane7_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_csrbus_read_data_7[63:0]"; |
| 457 | |
| 458 | |
| 459 | //------------------------------------------------------------------------ |
| 460 | // peu ras |
| 461 | //------------------------------------------------------------------------ |
| 462 | |
| 463 | |
| 464 | // peu_oe_log_en register |
| 465 | input peu_oe_log_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_log.oe_log_w_ld"; |
| 466 | input [23:0] peu_oe_log_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_log.oe_log_en_hw_read[23:0]"; |
| 467 | |
| 468 | |
| 469 | // peu_oe_int_en register |
| 470 | input peu_oe_int_en_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_int_en.oe_int_en_w_ld"; |
| 471 | input [63:0] peu_oe_int_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_int_en.oe_int_en_hw_read[63:0]"; |
| 472 | |
| 473 | // peu_oe_err register |
| 474 | input peu_oe_err_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_w_ld"; |
| 475 | input peu_oe_err_rw1c INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.rw1c_alias"; |
| 476 | input peu_oe_err_rw1s INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.rw1s_alias"; |
| 477 | input [63:0] peu_oe_err_hw_set INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_hw_set[63:0]"; |
| 478 | input [63:0] peu_oe_err_csrbus_wr_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.csrbus_wr_data[63:0]"; |
| 479 | input [63:0] peu_oe_err_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_csrbus_read_data[63:0]"; |
| 480 | |
| 481 | |
| 482 | // peu_ue_log_en register |
| 483 | input peu_ue_log_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_log.ue_log_w_ld"; |
| 484 | // input [23:0] peu_ue_log_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_log.ue_log_en_hw_read[23:0]"; |
| 485 | input [63:0] peu_ue_log_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_log.ue_log_csrbus_read_data[63:0]"; |
| 486 | |
| 487 | |
| 488 | // peu_ue_int_en register |
| 489 | input peu_ue_int_en_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_w_ld"; |
| 490 | // input [63:0] peu_ue_int_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_hw_read[63:0]"; |
| 491 | input [63:0] peu_ue_int_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_csrbus_read_data[63:0]"; |
| 492 | |
| 493 | // peu_ue_err register |
| 494 | input peu_ue_err_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_w_ld"; |
| 495 | input peu_ue_err_rw1c INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.rw1c_alias"; |
| 496 | input peu_ue_err_rw1s INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.rw1s_alias"; |
| 497 | input [63:0] peu_ue_err_hw_set INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_hw_set[63:0]"; |
| 498 | input [63:0] peu_ue_err_csrbus_wr_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.csrbus_wr_data[63:0]"; |
| 499 | input [63:0] peu_ue_err_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_csrbus_read_data[63:0]"; |
| 500 | |
| 501 | // peu_ce_log_en register |
| 502 | input peu_ce_log_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_log.ce_log_w_ld"; |
| 503 | // input [23:0] peu_ce_log_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_log.ce_log_en_hw_read[23:0]"; |
| 504 | input [63:0] peu_ce_log_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_log.ce_log_csrbus_read_data[23:0]"; |
| 505 | |
| 506 | |
| 507 | // peu_ce_int_en register |
| 508 | input peu_ce_int_en_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_w_ld"; |
| 509 | // input [63:0] peu_ce_int_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_hw_read[63:0]"; |
| 510 | input [63:0] peu_ce_int_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_csrbus_read_data[63:0]"; |
| 511 | |
| 512 | // peu_ce_err register |
| 513 | input peu_ce_err_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_w_ld"; |
| 514 | input peu_ce_err_rw1c INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.rw1c_alias"; |
| 515 | input peu_ce_err_rw1s INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.rw1s_alias"; |
| 516 | input [63:0] peu_ce_err_hw_set INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_hw_set[63:0]"; |
| 517 | input [63:0] peu_ce_err_csrbus_wr_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.csrbus_wr_data[63:0]"; |
| 518 | input [63:0] peu_ce_err_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_csrbus_read_data[63:0]"; |
| 519 | |
| 520 | // peu dlpl event_log_en register |
| 521 | input peu_event_log_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_log_en.event_err_log_en_w_ld"; |
| 522 | input [63:0] peu_event_log_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_log_en.event_err_log_en_csrbus_read_data[63:0]"; |
| 523 | |
| 524 | |
| 525 | // peu dlpl event_int_en register |
| 526 | input peu_event_int_en_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_int_en.event_err_int_en_w_ld"; |
| 527 | input [63:0] peu_event_int_en_reg INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_int_en.event_err_int_en_csrbus_read_data[63:0]"; |
| 528 | |
| 529 | |
| 530 | // peu dlpl event_err status register |
| 531 | input peu_event_w_ld INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_w_ld"; |
| 532 | input peu_event_rw1c INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.rw1c_alias"; |
| 533 | input peu_event_rw1s INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.rw1s_alias"; |
| 534 | input [63:0] peu_event_hw_set INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_hw_set[63:0]"; |
| 535 | input [63:0] peu_event_csrbus_wr_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.csrbus_wr_data[63:0]"; |
| 536 | input [63:0] peu_event_csrbus_read_data INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_csrbus_read_data[63:0]"; |
| 537 | |
| 538 | // peu error event_log_en register |
| 539 | input ilu_error_log_enable_reg INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_log_en.ilu_log_en_ihb_pe_hw_read"; |
| 540 | |
| 541 | // peu error interrupt register : |
| 542 | input ilu_error_interrupt_p_reg INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_int_en.ilu_int_en_ihb_pe_p_hw_read"; |
| 543 | input ilu_error_interrupt_s_reg INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_int_en.ilu_int_en_ihb_pe_s_hw_read"; |
| 544 | |
| 545 | // peu error status register : |
| 546 | input ilu_error_status_p_reg INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_log_err.ilu_log_err_ihb_pe_p_hw_read"; |
| 547 | input ilu_error_status_s_reg INPUT_EDGE INPUT_SKEW verilog_node "`ILU.cib.csr.dmu_ilu_cib_default_grp.ilu_log_err.ilu_log_err_ihb_pe_s_hw_read"; |
| 548 | |
| 549 | |
| 550 | } // end of interface peu_registers_coverage_ifc |
| 551 | |
| 552 | interface ilu_peu_coverage_ihb_rd_coverage_group |
| 553 | { |
| 554 | input d2p_ihb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ihb_clk"; |
| 555 | input d2p_ihb_rd INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ihb_rd"; |
| 556 | input [5:0] d2p_ihb_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ihb_addr"; |
| 557 | } |
| 558 | |
| 559 | interface ilu_peu_coverage_ihb_wr_coverage_group |
| 560 | { |
| 561 | input d2p_ihb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ihb_clk"; |
| 562 | input it2ih_we INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.it2ih_we"; |
| 563 | input [5:0] it2ih_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.it2ih_addr"; |
| 564 | } |
| 565 | |
| 566 | interface ilu_peu_coverage_idb_rd_coverage_group |
| 567 | { |
| 568 | input d2p_idb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_idb_clk"; |
| 569 | input d2p_idb_rd INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_idb_rd"; |
| 570 | input [7:0] d2p_idb_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_idb_addr"; |
| 571 | } |
| 572 | |
| 573 | interface ilu_peu_coverage_idb_wr_coverage_group |
| 574 | { |
| 575 | input d2p_idb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_idb_clk"; |
| 576 | input it2id_we INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.it2id_we"; |
| 577 | input [7:0] it2id_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.it2id_addr"; |
| 578 | } |
| 579 | |
| 580 | interface ilu_peu_coverage_ehb_rd_coverage_group |
| 581 | { |
| 582 | input d2p_ehb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ehb_clk"; |
| 583 | input et2eh_rd INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.et2eh_rd"; |
| 584 | input [5:0] et2eh_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.et2eh_addr"; |
| 585 | } |
| 586 | |
| 587 | interface ilu_peu_coverage_ehb_wr_coverage_group |
| 588 | { |
| 589 | input d2p_ehb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ehb_clk"; |
| 590 | input d2p_ehb_we INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ehb_we"; |
| 591 | input [5:0] d2p_ehb_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_ehb_addr"; |
| 592 | } |
| 593 | |
| 594 | interface ilu_peu_coverage_edb_rd_coverage_group |
| 595 | { |
| 596 | input d2p_edb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_edb_clk"; |
| 597 | input et2ed_rd INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.et2ed_rd"; |
| 598 | input [7:0] et2ed_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.et2ed_addr"; |
| 599 | } |
| 600 | |
| 601 | interface ilu_peu_coverage_edb_wr_coverage_group |
| 602 | { |
| 603 | input d2p_edb_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_edb_clk"; |
| 604 | input d2p_edb_we INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_edb_we"; |
| 605 | input [7:0] d2p_edb_addr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.d2p_edb_addr"; |
| 606 | } |
| 607 | |
| 608 | interface ilu_peu_coverage_pmc_state_coverage_group |
| 609 | { |
| 610 | input clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.clk"; |
| 611 | input [3:0] lpm2ctb_pmc_state INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_ptl.pmc.lpm.lpm2ctb_pmc_state"; |
| 612 | } |
| 613 | |
| 614 | interface ilu_peu_coverage_fcsm_state_coverage_group |
| 615 | { |
| 616 | input core_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_rtlh.u_rtlh_fc.u_rtlh_fc_arb.core_clk"; |
| 617 | input [3:0] fc_state INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_rtlh.u_rtlh_fc.u_rtlh_fc_arb.fc_state"; |
| 618 | } |
| 619 | |
| 620 | interface ilu_peu_coverage_ltssm_state_coverage_group |
| 621 | { |
| 622 | input core_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xmlh.u_xmlh_ltssm.core_clk"; |
| 623 | input [4:0] lts_state INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xmlh.u_xmlh_ltssm.lts_state"; |
| 624 | } |
| 625 | |
| 626 | interface ilu_peu_coverage_replay_times_coverage_group |
| 627 | { |
| 628 | input core_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.core_clk"; |
| 629 | input [1:0] replay_num INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.replay_num"; |
| 630 | } |
| 631 | |
| 632 | interface ilu_peu_coverage_retry_buf_rd_coverage_group |
| 633 | { |
| 634 | input core_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.core_clk"; |
| 635 | input xdlh_rbuf_rd INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.xdlh_rbuf_rd"; |
| 636 | input [7:0] rbuf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.rbuf_raddr"; |
| 637 | } |
| 638 | |
| 639 | interface ilu_peu_coverage_retry_buf_wr_coverage_group |
| 640 | { |
| 641 | input core_clk INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.core_clk"; |
| 642 | input xdlh_retryram_we INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.xdlh_retryram_we"; |
| 643 | input [7:0] rbuf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`PEU.peu_plp.plp_dlpl.u_xdlh.u_xdlh_retrybuf.rbuf_waddr"; |
| 644 | } |
| 645 | |
| 646 | |
| 647 | #endif |