| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: peu_register_coverage_sample.vrhpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #inc "ilu_peu_cov_inc.pal" |
| 36 | |
| 37 | |
| 38 | bit [63:0] peu_trn_off_reg_var = 64'b0; |
| 39 | |
| 40 | coverage_group peu_trn_off_reg_coverage_group |
| 41 | { |
| 42 | sample_event = wait_var(peu_trn_off_reg_var); |
| 43 | |
| 44 | |
| 45 | sample peu_registers_coverage_ifc.peu_trn_off_reg_pto |
| 46 | { |
| 47 | state peu_trn_off_reg_pto (1) ; |
| 48 | } |
| 49 | |
| 50 | } |
| 51 | |
| 52 | bit [63:0] peu_ici_reg_var = 64'b0; |
| 53 | |
| 54 | coverage_group peu_ici_reg_coverage_group |
| 55 | { |
| 56 | sample_event = wait_var(peu_ici_reg_var); |
| 57 | |
| 58 | sample peu_registers_coverage_ifc.peu_ici_reg_nhc[7:0] { |
| 59 | . &toggle( 8 ); |
| 60 | cov_weight = 1; |
| 61 | } |
| 62 | |
| 63 | sample peu_registers_coverage_ifc.peu_ici_reg_phc[7:0] { |
| 64 | . &toggle( 8 ); |
| 65 | cov_weight = 1; |
| 66 | } |
| 67 | sample peu_registers_coverage_ifc.peu_ici_reg_pdc[7:0] { |
| 68 | . &toggle( 8 ); |
| 69 | cov_weight = 1; |
| 70 | } |
| 71 | |
| 72 | |
| 73 | } |
| 74 | |
| 75 | bit [63:0] peu_prfc_reg_var = 64'b0; |
| 76 | |
| 77 | coverage_group peu_prfc_reg_coverage_group |
| 78 | { |
| 79 | sample_event = wait_var(peu_prfc_reg_var); |
| 80 | |
| 81 | sample peu_registers_coverage_ifc.peu_prfc_reg_sel0[7:0] { |
| 82 | . &toggle( 8 ); |
| 83 | cov_weight = 1; |
| 84 | } |
| 85 | |
| 86 | sample peu_registers_coverage_ifc.peu_prfc_reg_sel1[7:0] { |
| 87 | . &toggle( 8 ); |
| 88 | cov_weight = 1; |
| 89 | } |
| 90 | |
| 91 | sample peu_registers_coverage_ifc.peu_prfc_reg_sel2[1:0] { |
| 92 | . &toggle( 2 ); |
| 93 | cov_weight = 1; |
| 94 | } |
| 95 | |
| 96 | |
| 97 | |
| 98 | } |
| 99 | |
| 100 | bit [63:0] peu_device_control_reg_var = 64'b0; |
| 101 | |
| 102 | coverage_group peu_device_control_reg_coverage_group |
| 103 | { |
| 104 | sample_event = wait_var(peu_device_control_reg_var); |
| 105 | |
| 106 | sample peu_registers_coverage_ifc.peu_device_control_reg_mps[2:0] { |
| 107 | . &toggle( 3 ); |
| 108 | cov_weight = 1; |
| 109 | } |
| 110 | |
| 111 | } |
| 112 | |
| 113 | bit [63:0] peu_diagnostic_reg_var = 64'b0; |
| 114 | |
| 115 | coverage_group peu_diagnostic_reg_coverage_group |
| 116 | { |
| 117 | sample_event = wait_var(peu_diagnostic_reg_var); |
| 118 | |
| 119 | sample peu_registers_coverage_ifc.ilu_diagnos_rate_scale_hw_read[1:0] { |
| 120 | . &toggle( 2 ); |
| 121 | cov_weight = 1; |
| 122 | } |
| 123 | sample peu_registers_coverage_ifc.ilu_diagnos_ehi_trig_hw_read { |
| 124 | . &toggle( 1 ); |
| 125 | cov_weight = 1; |
| 126 | } |
| 127 | sample peu_registers_coverage_ifc.ilu_diagnos_edi_trig_hw_read { |
| 128 | . &toggle( 1 ); |
| 129 | cov_weight = 1; |
| 130 | } |
| 131 | sample peu_registers_coverage_ifc.ilu_diagnos_ehi_par_hw_read[3:0] { |
| 132 | . &toggle( 4 ); |
| 133 | cov_weight = 1; |
| 134 | } |
| 135 | sample peu_registers_coverage_ifc.ilu_diagnos_edi_par_hw_read[3:0] { |
| 136 | . &toggle( 4 ); |
| 137 | cov_weight = 1; |
| 138 | } |
| 139 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx0_hw_read { |
| 140 | . &toggle( 1 ); |
| 141 | cov_weight = 1; |
| 142 | } |
| 143 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx1_hw_read { |
| 144 | . &toggle( 1 ); |
| 145 | cov_weight = 1; |
| 146 | } |
| 147 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx2_hw_read { |
| 148 | . &toggle( 1 ); |
| 149 | cov_weight = 1; |
| 150 | } |
| 151 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx3_hw_read { |
| 152 | . &toggle( 1 ); |
| 153 | cov_weight = 1; |
| 154 | } |
| 155 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx4_hw_read { |
| 156 | . &toggle( 1 ); |
| 157 | cov_weight = 1; |
| 158 | } |
| 159 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx5_hw_read { |
| 160 | . &toggle( 1 ); |
| 161 | cov_weight = 1; |
| 162 | } |
| 163 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx6_hw_read { |
| 164 | . &toggle( 1 ); |
| 165 | cov_weight = 1; |
| 166 | } |
| 167 | sample peu_registers_coverage_ifc.ilu_diagnos_enrx7_hw_read { |
| 168 | . &toggle( 1 ); |
| 169 | cov_weight = 1; |
| 170 | } |
| 171 | sample peu_registers_coverage_ifc.ilu_diagnos_entx0_hw_read { |
| 172 | . &toggle( 1 ); |
| 173 | cov_weight = 1; |
| 174 | } |
| 175 | sample peu_registers_coverage_ifc.ilu_diagnos_entx1_hw_read { |
| 176 | . &toggle( 1 ); |
| 177 | cov_weight = 1; |
| 178 | } |
| 179 | sample peu_registers_coverage_ifc.ilu_diagnos_entx2_hw_read { |
| 180 | . &toggle( 1 ); |
| 181 | cov_weight = 1; |
| 182 | } |
| 183 | sample peu_registers_coverage_ifc.ilu_diagnos_entx3_hw_read { |
| 184 | . &toggle( 1 ); |
| 185 | cov_weight = 1; |
| 186 | } |
| 187 | sample peu_registers_coverage_ifc.ilu_diagnos_entx4_hw_read { |
| 188 | . &toggle( 1 ); |
| 189 | cov_weight = 1; |
| 190 | } |
| 191 | sample peu_registers_coverage_ifc.ilu_diagnos_entx5_hw_read { |
| 192 | . &toggle( 1 ); |
| 193 | cov_weight = 1; |
| 194 | } |
| 195 | sample peu_registers_coverage_ifc.ilu_diagnos_entx6_hw_read { |
| 196 | . &toggle( 1 ); |
| 197 | cov_weight = 1; |
| 198 | } |
| 199 | sample peu_registers_coverage_ifc.ilu_diagnos_entx7_hw_read { |
| 200 | . &toggle( 1 ); |
| 201 | cov_weight = 1; |
| 202 | } |
| 203 | sample peu_registers_coverage_ifc.ilu_diagnos_enpll0_hw_read { |
| 204 | . &toggle( 1 ); |
| 205 | cov_weight = 1; |
| 206 | } |
| 207 | sample peu_registers_coverage_ifc.ilu_diagnos_enpll1_hw_read { |
| 208 | . &toggle( 1 ); |
| 209 | cov_weight = 1; |
| 210 | } |
| 211 | |
| 212 | } |
| 213 | |
| 214 | bit [63:0] peu_link_control_reg_var = 64'b0; |
| 215 | |
| 216 | coverage_group peu_link_control_reg_coverage_group |
| 217 | { |
| 218 | sample_event = wait_var(peu_link_control_reg_var); |
| 219 | |
| 220 | sample peu_registers_coverage_ifc.peu_link_control_reg_extended_sync |
| 221 | { |
| 222 | state peu_link_control_reg_extended_sync (1) ; |
| 223 | } |
| 224 | sample peu_registers_coverage_ifc.peu_link_control_reg_common_clock |
| 225 | { |
| 226 | state peu_link_control_reg_common_clock (1) ; |
| 227 | } |
| 228 | sample peu_registers_coverage_ifc.peu_link_control_reg_retrain |
| 229 | { |
| 230 | state peu_link_control_reg_retrain (1) ; |
| 231 | } |
| 232 | sample peu_registers_coverage_ifc.peu_link_control_reg_disable |
| 233 | { |
| 234 | state peu_link_control_reg_disable (1) ; |
| 235 | } |
| 236 | sample peu_registers_coverage_ifc.peu_link_control_reg_rcb |
| 237 | { |
| 238 | state peu_link_control_reg_rcb (1) ; |
| 239 | } |
| 240 | sample peu_registers_coverage_ifc.peu_link_control_reg_aspm[1:0] { |
| 241 | . &toggle( 2 ); |
| 242 | cov_weight = 1; |
| 243 | } |
| 244 | |
| 245 | |
| 246 | } |
| 247 | |
| 248 | bit [63:0] peu_link_status_reg_var = 64'b0; |
| 249 | |
| 250 | coverage_group peu_link_status_reg_coverage_group |
| 251 | { |
| 252 | sample_event = wait_var(peu_link_status_reg_var); |
| 253 | |
| 254 | sample peu_registers_coverage_ifc.peu_link_status_reg_slot_clock |
| 255 | { |
| 256 | state peu_link_status_reg_slot_clock (1) ; |
| 257 | } |
| 258 | sample peu_registers_coverage_ifc.peu_link_status_reg_train |
| 259 | { |
| 260 | state peu_link_status_reg_train (1) ; |
| 261 | } |
| 262 | sample peu_registers_coverage_ifc.peu_link_status_reg_error |
| 263 | { |
| 264 | state peu_link_status_reg_error (1) ; |
| 265 | } |
| 266 | sample peu_registers_coverage_ifc.peu_link_status_reg_width[5:0] { |
| 267 | . &toggle( 6 ); |
| 268 | cov_weight = 1; |
| 269 | } |
| 270 | sample peu_registers_coverage_ifc.peu_link_status_reg_speed[3:0] { |
| 271 | . &toggle( 4 ); |
| 272 | cov_weight = 1; |
| 273 | } |
| 274 | |
| 275 | } |
| 276 | |
| 277 | bit [9:0] peu_slot_cap_register_var = 10'b0; |
| 278 | |
| 279 | coverage_group peu_slot_cap_register_coverage_group |
| 280 | { |
| 281 | sample_event = wait_var(peu_slot_cap_register_var); |
| 282 | |
| 283 | sample peu_registers_coverage_ifc.peu_slot_cap_register_spls[1:0] { |
| 284 | . &toggle( 2 ); |
| 285 | cov_weight = 1; |
| 286 | } |
| 287 | |
| 288 | sample peu_registers_coverage_ifc.peu_slot_cap_register_splv[7:0] { |
| 289 | . &toggle( 8 ); |
| 290 | cov_weight = 1; |
| 291 | } |
| 292 | |
| 293 | } |
| 294 | |
| 295 | bit [63:0] peu_dlpl_dll_control_reg_var = 64'b0; |
| 296 | |
| 297 | coverage_group peu_dlpl_dll_control_reg_coverage_group |
| 298 | { |
| 299 | sample_event = wait_var(peu_dlpl_dll_control_reg_var); |
| 300 | |
| 301 | |
| 302 | sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_ack_freq[7:0] { |
| 303 | . &toggle( 8 ); |
| 304 | cov_weight = 1; |
| 305 | } |
| 306 | |
| 307 | sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_flow_disable |
| 308 | { |
| 309 | state peu_dlpl_dll_control_reg_flow_disable (1) ; |
| 310 | } |
| 311 | sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_other_message_req |
| 312 | { |
| 313 | state peu_dlpl_dll_control_reg_other_message_req (1) ; |
| 314 | } |
| 315 | sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_ack_nak_disable |
| 316 | { |
| 317 | state peu_dlpl_dll_control_reg_ack_nak_disable (1) ; |
| 318 | } |
| 319 | sample peu_registers_coverage_ifc.peu_dlpl_dll_control_reg_data_link_en |
| 320 | { |
| 321 | state peu_dlpl_dll_control_reg_data_link_en (1) ; |
| 322 | } |
| 323 | |
| 324 | |
| 325 | } |
| 326 | |
| 327 | bit [63:0] peu_dlpl_macl_control_reg_var = 64'b0; |
| 328 | |
| 329 | coverage_group peu_dlpl_macl_control_reg_coverage_group |
| 330 | { |
| 331 | sample_event = wait_var(peu_dlpl_macl_control_reg_var); |
| 332 | |
| 333 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_link_num[7:0] { |
| 334 | . &toggle( 8 ); |
| 335 | cov_weight = 1; |
| 336 | } |
| 337 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_nfts[7:0] { |
| 338 | . &toggle( 8 ); |
| 339 | cov_weight = 1; |
| 340 | } |
| 341 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_link_capable[3:0] { |
| 342 | . &toggle( 4 ); |
| 343 | cov_weight = 1; |
| 344 | } |
| 345 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_fast_link_mode |
| 346 | { |
| 347 | state peu_dlpl_macl_control_reg_fast_link_mode (1) ; |
| 348 | } |
| 349 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_elastic_buffer_disable |
| 350 | { |
| 351 | state peu_dlpl_macl_control_reg_elastic_buffer_disable (1) ; |
| 352 | } |
| 353 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_scramble_disable |
| 354 | { |
| 355 | state peu_dlpl_macl_control_reg_scramble_disable (1) ; |
| 356 | } |
| 357 | sample peu_registers_coverage_ifc.peu_dlpl_macl_control_reg_reset_assert |
| 358 | { |
| 359 | state peu_dlpl_macl_control_reg_reset_assert (1) ; |
| 360 | } |
| 361 | |
| 362 | } |
| 363 | |
| 364 | bit [63:0] peu_dlpl_lane_skew_reg_var = 64'b0; |
| 365 | |
| 366 | coverage_group peu_dlpl_lane_skew_reg_coverage_group |
| 367 | { |
| 368 | sample_event = wait_var(peu_dlpl_lane_skew_reg_var); |
| 369 | |
| 370 | sample peu_registers_coverage_ifc.peu_dlpl_lane_skew_reg_deskew_disable |
| 371 | { |
| 372 | state peu_dlpl_lane_skew_reg_deskew_disable (1) ; |
| 373 | } |
| 374 | |
| 375 | } |
| 376 | |
| 377 | bit [63:0] peu_dlpl_sym_num_reg_var = 64'b0; |
| 378 | |
| 379 | coverage_group peu_dlpl_sym_num_reg_coverage_group |
| 380 | { |
| 381 | sample_event = wait_var(peu_dlpl_sym_num_reg_var); |
| 382 | |
| 383 | sample peu_registers_coverage_ifc.peu_dlpl_sym_num_reg_skip[2:0] { |
| 384 | . &toggle( 3 ); |
| 385 | cov_weight = 1; |
| 386 | } |
| 387 | sample peu_registers_coverage_ifc.peu_dlpl_sym_num_reg_ts1[3:0] { |
| 388 | . &toggle( 4 ); |
| 389 | cov_weight = 1; |
| 390 | } |
| 391 | |
| 392 | } |
| 393 | |
| 394 | bit [63:0] peu_dlpl_sym_timer_reg_var = 64'b0; |
| 395 | |
| 396 | coverage_group peu_dlpl_sym_timer_reg_coverage_group |
| 397 | { |
| 398 | sample_event = wait_var(peu_dlpl_sym_timer_reg_var); |
| 399 | |
| 400 | sample peu_registers_coverage_ifc.peu_dlpl_sym_timer_reg_skip_interval[10:0] { |
| 401 | . &toggle( 11 ); |
| 402 | cov_weight = 1; |
| 403 | } |
| 404 | |
| 405 | } |
| 406 | |
| 407 | |
| 408 | bit [63:0] peu_link_bit_error_counter_I_reg_var = 64'b0; |
| 409 | |
| 410 | coverage_group peu_link_bit_error_counter_I_reg_coverage_group |
| 411 | { |
| 412 | sample_event = wait_var(peu_link_bit_error_counter_I_reg_var); |
| 413 | |
| 414 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_ber_en |
| 415 | { |
| 416 | state peu_link_bit_error_counter_I_reg_ber_en (1) ; |
| 417 | } |
| 418 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_ber_clr |
| 419 | { |
| 420 | state peu_link_bit_error_counter_I_reg_ber_clr (1) ; |
| 421 | } |
| 422 | |
| 423 | } |
| 424 | |
| 425 | |
| 426 | bit [63:0] serdes_pll_csrbus_read_data_var = 64'b0; |
| 427 | |
| 428 | coverage_group serdes_pll_csrbus_read_data_coverage_group |
| 429 | { |
| 430 | sample_event = wait_var(serdes_pll_csrbus_read_data_var); |
| 431 | |
| 432 | sample peu_registers_coverage_ifc.serdes_pll_lb_hw_read[1:0] { |
| 433 | . &toggle( 2 ); |
| 434 | cov_weight = 1; |
| 435 | } |
| 436 | |
| 437 | sample peu_registers_coverage_ifc.serdes_pll_mpy_hw_read[3:0] |
| 438 | { |
| 439 | state serdes_pll_mpy_250_clock (4'b0001) ; |
| 440 | state serdes_pll_mpy_125_clock (4'b0101) ; |
| 441 | state serdes_pll_mpy_100_clock (4'b0111) ; |
| 442 | } |
| 443 | } |
| 444 | |
| 445 | bit [63:0] peu_ser_receiver_lane_ctl0_reg_var = 64'b0; |
| 446 | |
| 447 | coverage_group peu_ser_receiver_lane_ctl0_reg_coverage_group |
| 448 | { |
| 449 | sample_event = wait_var(peu_ser_receiver_lane_ctl0_reg_var); |
| 450 | |
| 451 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg_entest |
| 452 | { |
| 453 | state peu_ser_receiver_lane_ctl0_reg_entest (1) ; |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | bit [63:0] peu_ser_receiver_lane_ctl1_reg_var = 64'b0; |
| 458 | |
| 459 | coverage_group peu_ser_receiver_lane_ctl1_reg_coverage_group |
| 460 | { |
| 461 | sample_event = wait_var(peu_ser_receiver_lane_ctl1_reg_var); |
| 462 | |
| 463 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl1_reg_entest |
| 464 | { |
| 465 | state peu_ser_receiver_lane_ctl1_reg_entest (1) ; |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | bit [63:0] peu_ser_receiver_lane_ctl2_reg_var = 64'b0; |
| 470 | |
| 471 | coverage_group peu_ser_receiver_lane_ctl2_reg_coverage_group |
| 472 | { |
| 473 | sample_event = wait_var(peu_ser_receiver_lane_ctl2_reg_var); |
| 474 | |
| 475 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl2_reg_entest |
| 476 | { |
| 477 | state peu_ser_receiver_lane_ctl2_reg_entest (1) ; |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | bit [63:0] peu_ser_receiver_lane_ctl3_reg_var = 64'b0; |
| 482 | |
| 483 | coverage_group peu_ser_receiver_lane_ctl3_reg_coverage_group |
| 484 | { |
| 485 | sample_event = wait_var(peu_ser_receiver_lane_ctl3_reg_var); |
| 486 | |
| 487 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl3_reg_entest |
| 488 | { |
| 489 | state peu_ser_receiver_lane_ctl3_reg_entest (1) ; |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | |
| 494 | bit [63:0] peu_ser_receiver_lane_ctl4_reg_var = 64'b0; |
| 495 | |
| 496 | coverage_group peu_ser_receiver_lane_ctl4_reg_coverage_group |
| 497 | { |
| 498 | sample_event = wait_var(peu_ser_receiver_lane_ctl4_reg_var); |
| 499 | |
| 500 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl4_reg_entest |
| 501 | { |
| 502 | state peu_ser_receiver_lane_ctl4_reg_entest (1) ; |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | bit [63:0] peu_ser_receiver_lane_ctl5_reg_var = 64'b0; |
| 507 | |
| 508 | coverage_group peu_ser_receiver_lane_ctl5_reg_coverage_group |
| 509 | { |
| 510 | sample_event = wait_var(peu_ser_receiver_lane_ctl5_reg_var); |
| 511 | |
| 512 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl5_reg_entest |
| 513 | { |
| 514 | state peu_ser_receiver_lane_ctl5_reg_entest (1) ; |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | |
| 519 | bit [63:0] peu_ser_receiver_lane_ctl6_reg_var = 64'b0; |
| 520 | |
| 521 | coverage_group peu_ser_receiver_lane_ctl6_reg_coverage_group |
| 522 | { |
| 523 | sample_event = wait_var(peu_ser_receiver_lane_ctl6_reg_var); |
| 524 | |
| 525 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl6_reg_entest |
| 526 | { |
| 527 | state peu_ser_receiver_lane_ctl6_reg_entest (1) ; |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | bit [63:0] peu_ser_receiver_lane_ctl7_reg_var = 64'b0; |
| 532 | |
| 533 | coverage_group peu_ser_receiver_lane_ctl7_reg_coverage_group |
| 534 | { |
| 535 | sample_event = wait_var(peu_ser_receiver_lane_ctl7_reg_var); |
| 536 | |
| 537 | sample peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl7_reg_entest |
| 538 | { |
| 539 | state peu_ser_receiver_lane_ctl7_reg_entest (1) ; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | |
| 544 | bit [63:0] peu_ser_xmitter_ctl_lane0_reg_var = 64'b0; |
| 545 | |
| 546 | coverage_group peu_ser_xmitter_ctl_lane0_reg_coverage_group |
| 547 | { |
| 548 | sample_event = wait_var(peu_ser_xmitter_ctl_lane0_reg_var); |
| 549 | |
| 550 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane0_reg_invert_polarity |
| 551 | { |
| 552 | state peu_ser_xmitter_ctl_lane0_reg_invert_polarity (1) ; |
| 553 | } |
| 554 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane0_reg_entest |
| 555 | { |
| 556 | state peu_ser_xmitter_ctl_lane0_reg_entest (1) ; |
| 557 | } |
| 558 | |
| 559 | } |
| 560 | |
| 561 | bit [63:0] peu_ser_xmitter_ctl_lane1_reg_var = 64'b0; |
| 562 | |
| 563 | coverage_group peu_ser_xmitter_ctl_lane1_reg_coverage_group |
| 564 | { |
| 565 | sample_event = wait_var(peu_ser_xmitter_ctl_lane1_reg_var); |
| 566 | |
| 567 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane1_reg_invert_polarity |
| 568 | { |
| 569 | state peu_ser_xmitter_ctl_lane1_reg_invert_polarity (1) ; |
| 570 | } |
| 571 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane1_reg_entest |
| 572 | { |
| 573 | state peu_ser_xmitter_ctl_lane1_reg_entest (1) ; |
| 574 | } |
| 575 | |
| 576 | } |
| 577 | |
| 578 | bit [63:0] peu_ser_xmitter_ctl_lane2_reg_var = 64'b0; |
| 579 | |
| 580 | coverage_group peu_ser_xmitter_ctl_lane2_reg_coverage_group |
| 581 | { |
| 582 | sample_event = wait_var(peu_ser_xmitter_ctl_lane2_reg_var); |
| 583 | |
| 584 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane2_reg_invert_polarity |
| 585 | { |
| 586 | state peu_ser_xmitter_ctl_lane2_reg_invert_polarity (1) ; |
| 587 | } |
| 588 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane2_reg_entest |
| 589 | { |
| 590 | state peu_ser_xmitter_ctl_lane2_reg_entest (1) ; |
| 591 | } |
| 592 | |
| 593 | } |
| 594 | |
| 595 | bit [63:0] peu_ser_xmitter_ctl_lane3_reg_var = 64'b0; |
| 596 | |
| 597 | coverage_group peu_ser_xmitter_ctl_lane3_reg_coverage_group |
| 598 | { |
| 599 | sample_event = wait_var(peu_ser_xmitter_ctl_lane3_reg_var); |
| 600 | |
| 601 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane3_reg_invert_polarity |
| 602 | { |
| 603 | state peu_ser_xmitter_ctl_lane3_reg_invert_polarity (1) ; |
| 604 | } |
| 605 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane3_reg_entest |
| 606 | { |
| 607 | state peu_ser_xmitter_ctl_lane3_reg_entest (1) ; |
| 608 | } |
| 609 | |
| 610 | } |
| 611 | |
| 612 | bit [63:0] peu_ser_xmitter_ctl_lane4_reg_var = 64'b0; |
| 613 | |
| 614 | coverage_group peu_ser_xmitter_ctl_lane4_reg_coverage_group |
| 615 | { |
| 616 | sample_event = wait_var(peu_ser_xmitter_ctl_lane4_reg_var); |
| 617 | |
| 618 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane4_reg_invert_polarity |
| 619 | { |
| 620 | state peu_ser_xmitter_ctl_lane4_reg_invert_polarity (1) ; |
| 621 | } |
| 622 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane4_reg_entest |
| 623 | { |
| 624 | state peu_ser_xmitter_ctl_lane4_reg_entest (1) ; |
| 625 | } |
| 626 | |
| 627 | } |
| 628 | |
| 629 | bit [63:0] peu_ser_xmitter_ctl_lane5_reg_var = 64'b0; |
| 630 | |
| 631 | coverage_group peu_ser_xmitter_ctl_lane5_reg_coverage_group |
| 632 | { |
| 633 | sample_event = wait_var(peu_ser_xmitter_ctl_lane5_reg_var); |
| 634 | |
| 635 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane5_reg_invert_polarity |
| 636 | { |
| 637 | state peu_ser_xmitter_ctl_lane5_reg_invert_polarity (1) ; |
| 638 | } |
| 639 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane5_reg_entest |
| 640 | { |
| 641 | state peu_ser_xmitter_ctl_lane5_reg_entest (1) ; |
| 642 | } |
| 643 | |
| 644 | } |
| 645 | |
| 646 | bit [63:0] peu_ser_xmitter_ctl_lane6_reg_var = 64'b0; |
| 647 | |
| 648 | coverage_group peu_ser_xmitter_ctl_lane6_reg_coverage_group |
| 649 | { |
| 650 | sample_event = wait_var(peu_ser_xmitter_ctl_lane6_reg_var); |
| 651 | |
| 652 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane6_reg_invert_polarity |
| 653 | { |
| 654 | state peu_ser_xmitter_ctl_lane6_reg_invert_polarity (1) ; |
| 655 | } |
| 656 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane6_reg_entest |
| 657 | { |
| 658 | state peu_ser_xmitter_ctl_lane6_reg_entest (1) ; |
| 659 | } |
| 660 | |
| 661 | } |
| 662 | |
| 663 | bit [63:0] peu_ser_xmitter_ctl_lane7_reg_var = 64'b0; |
| 664 | |
| 665 | coverage_group peu_ser_xmitter_ctl_lane7_reg_coverage_group |
| 666 | { |
| 667 | sample_event = wait_var(peu_ser_xmitter_ctl_lane7_reg_var); |
| 668 | |
| 669 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane7_reg_invert_polarity |
| 670 | { |
| 671 | state peu_ser_xmitter_ctl_lane7_reg_invert_polarity (1) ; |
| 672 | } |
| 673 | sample peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane7_reg_entest |
| 674 | { |
| 675 | state peu_ser_xmitter_ctl_lane7_reg_entest (1) ; |
| 676 | } |
| 677 | |
| 678 | } |
| 679 | |
| 680 | |
| 681 | bit [63:0] peu_ser_receiver_status_lane0_reg_var = 64'b0; |
| 682 | coverage_group peu_ser_receiver_status_lane0_reg_coverage_group |
| 683 | { |
| 684 | sample_event = wait_var(peu_ser_receiver_status_lane0_reg_var); |
| 685 | |
| 686 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[0] |
| 687 | { |
| 688 | state peu_ser_receiver_status_lane0_reg_0 (0) ; |
| 689 | } |
| 690 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[1] |
| 691 | { |
| 692 | state peu_ser_receiver_status_lane0_reg_1 (1) ; |
| 693 | } |
| 694 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[2] |
| 695 | { |
| 696 | state peu_ser_receiver_status_lane0_reg_2 (2) ; |
| 697 | } |
| 698 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[3] |
| 699 | { |
| 700 | state peu_ser_receiver_status_lane0_reg_3 (3) ; |
| 701 | } |
| 702 | |
| 703 | } |
| 704 | |
| 705 | bit [63:0] peu_ser_receiver_status_lane1_reg_var = 64'b0; |
| 706 | coverage_group peu_ser_receiver_status_lane1_reg_coverage_group |
| 707 | { |
| 708 | sample_event = wait_var(peu_ser_receiver_status_lane1_reg_var); |
| 709 | |
| 710 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[0] |
| 711 | { |
| 712 | state peu_ser_receiver_status_lane1_reg_0 (0) ; |
| 713 | } |
| 714 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[1] |
| 715 | { |
| 716 | state peu_ser_receiver_status_lane1_reg_1 (1) ; |
| 717 | } |
| 718 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[2] |
| 719 | { |
| 720 | state peu_ser_receiver_status_lane1_reg_2 (2) ; |
| 721 | } |
| 722 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[3] |
| 723 | { |
| 724 | state peu_ser_receiver_status_lane1_reg_3 (3) ; |
| 725 | } |
| 726 | |
| 727 | } |
| 728 | bit [63:0] peu_ser_receiver_status_lane2_reg_var = 64'b0; |
| 729 | coverage_group peu_ser_receiver_status_lane2_reg_coverage_group |
| 730 | { |
| 731 | sample_event = wait_var(peu_ser_receiver_status_lane2_reg_var); |
| 732 | |
| 733 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[0] |
| 734 | { |
| 735 | state peu_ser_receiver_status_lane2_reg_0 (0) ; |
| 736 | } |
| 737 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[1] |
| 738 | { |
| 739 | state peu_ser_receiver_status_lane2_reg_1 (1) ; |
| 740 | } |
| 741 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[2] |
| 742 | { |
| 743 | state peu_ser_receiver_status_lane2_reg_2 (2) ; |
| 744 | } |
| 745 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[3] |
| 746 | { |
| 747 | state peu_ser_receiver_status_lane2_reg_3 (3) ; |
| 748 | } |
| 749 | |
| 750 | } |
| 751 | bit [63:0] peu_ser_receiver_status_lane3_reg_var = 64'b0; |
| 752 | coverage_group peu_ser_receiver_status_lane3_reg_coverage_group |
| 753 | { |
| 754 | sample_event = wait_var(peu_ser_receiver_status_lane3_reg_var); |
| 755 | |
| 756 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[0] |
| 757 | { |
| 758 | state peu_ser_receiver_status_lane3_reg_0 (0) ; |
| 759 | } |
| 760 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[1] |
| 761 | { |
| 762 | state peu_ser_receiver_status_lane3_reg_1 (1) ; |
| 763 | } |
| 764 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[2] |
| 765 | { |
| 766 | state peu_ser_receiver_status_lane3_reg_2 (2) ; |
| 767 | } |
| 768 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[3] |
| 769 | { |
| 770 | state peu_ser_receiver_status_lane3_reg_3 (3) ; |
| 771 | } |
| 772 | |
| 773 | } |
| 774 | bit [63:0] peu_ser_receiver_status_lane4_reg_var = 64'b0; |
| 775 | coverage_group peu_ser_receiver_status_lane4_reg_coverage_group |
| 776 | { |
| 777 | sample_event = wait_var(peu_ser_receiver_status_lane4_reg_var); |
| 778 | |
| 779 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[0] |
| 780 | { |
| 781 | state peu_ser_receiver_status_lane4_reg_0 (0) ; |
| 782 | } |
| 783 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[1] |
| 784 | { |
| 785 | state peu_ser_receiver_status_lane4_reg_1 (1) ; |
| 786 | } |
| 787 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[2] |
| 788 | { |
| 789 | state peu_ser_receiver_status_lane4_reg_2 (2) ; |
| 790 | } |
| 791 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[3] |
| 792 | { |
| 793 | state peu_ser_receiver_status_lane4_reg_3 (3) ; |
| 794 | } |
| 795 | |
| 796 | } |
| 797 | bit [63:0] peu_ser_receiver_status_lane5_reg_var = 64'b0; |
| 798 | coverage_group peu_ser_receiver_status_lane5_reg_coverage_group |
| 799 | { |
| 800 | sample_event = wait_var(peu_ser_receiver_status_lane5_reg_var); |
| 801 | |
| 802 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[0] |
| 803 | { |
| 804 | state peu_ser_receiver_status_lane5_reg_0 (0) ; |
| 805 | } |
| 806 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[1] |
| 807 | { |
| 808 | state peu_ser_receiver_status_lane5_reg_1 (1) ; |
| 809 | } |
| 810 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[2] |
| 811 | { |
| 812 | state peu_ser_receiver_status_lane5_reg_2 (2) ; |
| 813 | } |
| 814 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[3] |
| 815 | { |
| 816 | state peu_ser_receiver_status_lane5_reg_3 (3) ; |
| 817 | } |
| 818 | |
| 819 | } |
| 820 | bit [63:0] peu_ser_receiver_status_lane6_reg_var = 64'b0; |
| 821 | coverage_group peu_ser_receiver_status_lane6_reg_coverage_group |
| 822 | { |
| 823 | sample_event = wait_var(peu_ser_receiver_status_lane6_reg_var); |
| 824 | |
| 825 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[0] |
| 826 | { |
| 827 | state peu_ser_receiver_status_lane6_reg_0 (0) ; |
| 828 | } |
| 829 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[1] |
| 830 | { |
| 831 | state peu_ser_receiver_status_lane6_reg_1 (1) ; |
| 832 | } |
| 833 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[2] |
| 834 | { |
| 835 | state peu_ser_receiver_status_lane6_reg_2 (2) ; |
| 836 | } |
| 837 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[3] |
| 838 | { |
| 839 | state peu_ser_receiver_status_lane6_reg_3 (3) ; |
| 840 | } |
| 841 | |
| 842 | } |
| 843 | bit [63:0] peu_ser_receiver_status_lane7_reg_var = 64'b0; |
| 844 | coverage_group peu_ser_receiver_status_lane7_reg_coverage_group |
| 845 | { |
| 846 | sample_event = wait_var(peu_ser_receiver_status_lane7_reg_var); |
| 847 | |
| 848 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[0] |
| 849 | { |
| 850 | state peu_ser_receiver_status_lane7_reg_0 (0) ; |
| 851 | } |
| 852 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[1] |
| 853 | { |
| 854 | state peu_ser_receiver_status_lane7_reg_1 (1) ; |
| 855 | } |
| 856 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[2] |
| 857 | { |
| 858 | state peu_ser_receiver_status_lane7_reg_2 (2) ; |
| 859 | } |
| 860 | sample peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[3] |
| 861 | { |
| 862 | state peu_ser_receiver_status_lane7_reg_3 (3) ; |
| 863 | } |
| 864 | |
| 865 | } |
| 866 | |
| 867 | |
| 868 | // ser xmitter status lane 0 - 7 |
| 869 | |
| 870 | bit [63:0] peu_ser_xmitter_status_lane0_reg_var = 64'b0; |
| 871 | coverage_group peu_ser_xmitter_status_lane0_reg_coverage_group |
| 872 | { |
| 873 | sample_event = wait_var(peu_ser_xmitter_status_lane0_reg_var); |
| 874 | |
| 875 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane0_reg[0] |
| 876 | { |
| 877 | state peu_ser_xmitter_status_lane0_reg_0 (0) ; |
| 878 | } |
| 879 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane0_reg[1] |
| 880 | { |
| 881 | state peu_ser_xmitter_status_lane0_reg_1 (1) ; |
| 882 | } |
| 883 | |
| 884 | } |
| 885 | |
| 886 | bit [63:0] peu_ser_xmitter_status_lane1_reg_var = 64'b0; |
| 887 | coverage_group peu_ser_xmitter_status_lane1_reg_coverage_group |
| 888 | { |
| 889 | sample_event = wait_var(peu_ser_xmitter_status_lane1_reg_var); |
| 890 | |
| 891 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane1_reg[0] |
| 892 | { |
| 893 | state peu_ser_xmitter_status_lane1_reg_0 (0) ; |
| 894 | } |
| 895 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane1_reg[1] |
| 896 | { |
| 897 | state peu_ser_xmitter_status_lane1_reg_1 (1) ; |
| 898 | } |
| 899 | |
| 900 | } |
| 901 | |
| 902 | bit [63:0] peu_ser_xmitter_status_lane2_reg_var = 64'b0; |
| 903 | coverage_group peu_ser_xmitter_status_lane2_reg_coverage_group |
| 904 | { |
| 905 | sample_event = wait_var(peu_ser_xmitter_status_lane2_reg_var); |
| 906 | |
| 907 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane2_reg[0] |
| 908 | { |
| 909 | state peu_ser_xmitter_status_lane2_reg_0 (0) ; |
| 910 | } |
| 911 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane2_reg[1] |
| 912 | { |
| 913 | state peu_ser_xmitter_status_lane2_reg_1 (1) ; |
| 914 | } |
| 915 | |
| 916 | } |
| 917 | |
| 918 | bit [63:0] peu_ser_xmitter_status_lane3_reg_var = 64'b0; |
| 919 | coverage_group peu_ser_xmitter_status_lane3_reg_coverage_group |
| 920 | { |
| 921 | sample_event = wait_var(peu_ser_xmitter_status_lane3_reg_var); |
| 922 | |
| 923 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane3_reg[0] |
| 924 | { |
| 925 | state peu_ser_xmitter_status_lane3_reg_0 (0) ; |
| 926 | } |
| 927 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane3_reg[1] |
| 928 | { |
| 929 | state peu_ser_xmitter_status_lane3_reg_1 (1) ; |
| 930 | } |
| 931 | |
| 932 | } |
| 933 | |
| 934 | bit [63:0] peu_ser_xmitter_status_lane4_reg_var = 64'b0; |
| 935 | coverage_group peu_ser_xmitter_status_lane4_reg_coverage_group |
| 936 | { |
| 937 | sample_event = wait_var(peu_ser_xmitter_status_lane4_reg_var); |
| 938 | |
| 939 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane4_reg[0] |
| 940 | { |
| 941 | state peu_ser_xmitter_status_lane4_reg_0 (0) ; |
| 942 | } |
| 943 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane4_reg[1] |
| 944 | { |
| 945 | state peu_ser_xmitter_status_lane4_reg_1 (1) ; |
| 946 | } |
| 947 | |
| 948 | } |
| 949 | |
| 950 | bit [63:0] peu_ser_xmitter_status_lane5_reg_var = 64'b0; |
| 951 | coverage_group peu_ser_xmitter_status_lane5_reg_coverage_group |
| 952 | { |
| 953 | sample_event = wait_var(peu_ser_xmitter_status_lane5_reg_var); |
| 954 | |
| 955 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane5_reg[0] |
| 956 | { |
| 957 | state peu_ser_xmitter_status_lane5_reg_0 (0) ; |
| 958 | } |
| 959 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane5_reg[1] |
| 960 | { |
| 961 | state peu_ser_xmitter_status_lane5_reg_1 (1) ; |
| 962 | } |
| 963 | |
| 964 | } |
| 965 | |
| 966 | bit [63:0] peu_ser_xmitter_status_lane6_reg_var = 64'b0; |
| 967 | coverage_group peu_ser_xmitter_status_lane6_reg_coverage_group |
| 968 | { |
| 969 | sample_event = wait_var(peu_ser_xmitter_status_lane6_reg_var); |
| 970 | |
| 971 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane6_reg[0] |
| 972 | { |
| 973 | state peu_ser_xmitter_status_lane6_reg_0 (0) ; |
| 974 | } |
| 975 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane6_reg[1] |
| 976 | { |
| 977 | state peu_ser_xmitter_status_lane6_reg_1 (1) ; |
| 978 | } |
| 979 | |
| 980 | } |
| 981 | |
| 982 | bit [63:0] peu_ser_xmitter_status_lane7_reg_var = 64'b0; |
| 983 | coverage_group peu_ser_xmitter_status_lane7_reg_coverage_group |
| 984 | { |
| 985 | sample_event = wait_var(peu_ser_xmitter_status_lane7_reg_var); |
| 986 | |
| 987 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane7_reg[0] |
| 988 | { |
| 989 | state peu_ser_xmitter_status_lane7_reg_0 (0) ; |
| 990 | } |
| 991 | sample peu_registers_coverage_ifc.peu_ser_xmitter_status_lane7_reg[1] |
| 992 | { |
| 993 | state peu_ser_xmitter_status_lane7_reg_1 (1) ; |
| 994 | } |
| 995 | |
| 996 | } |
| 997 | |