| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ccx_pcx_qfull_sample.vrhpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | wildcard state allcores_bank0(64'hXXXXXXXX_XXXXXXff); |
| 36 | wildcard state allcores_bank1(64'hXXXXXXXX_XXXXffXX); |
| 37 | wildcard state allcores_bank2(64'hXXXXXXXX_XXffXXXX); |
| 38 | wildcard state allcores_bank3(64'hXXXXXXXX_ffXXXXXX); |
| 39 | wildcard state allcores_bank4(64'hXXXXXXff_XXXXXXXX); |
| 40 | wildcard state allcores_bank5(64'hXXXXffXX_XXXXXXXX); |
| 41 | wildcard state allcores_bank6(64'hXXffXXXX_XXXXXXXX); |
| 42 | wildcard state allcores_bank7(64'hffXXXXXX_XXXXXXXX); |
| 43 | |
| 44 | wildcard state core0_bank0({56'hXXXXXXXX_XXXXXX, 8'bxxxxxxx1}); |
| 45 | wildcard state core1_bank0({56'hXXXXXXXX_XXXXXX, 8'bxxxxxx1x}); |
| 46 | wildcard state core2_bank0({56'hXXXXXXXX_XXXXXX, 8'bxxxxx1xx}); |
| 47 | wildcard state core3_bank0({56'hXXXXXXXX_XXXXXX, 8'bxxxx1xxx}); |
| 48 | wildcard state core4_bank0({56'hXXXXXXXX_XXXXXX, 8'bxxx1xxxx}); |
| 49 | wildcard state core5_bank0({56'hXXXXXXXX_XXXXXX, 8'bxx1xxxxx}); |
| 50 | wildcard state core6_bank0({56'hXXXXXXXX_XXXXXX, 8'bx1xxxxxx}); |
| 51 | wildcard state core7_bank0({56'hXXXXXXXX_XXXXXX, 8'b1xxxxxxx}); |
| 52 | |
| 53 | wildcard state core0_bank1({48'hXXXXXXXX_XXXX, 8'bxxxxxxx1, 8'hXX}); |
| 54 | wildcard state core1_bank1({48'hXXXXXXXX_XXXX, 8'bxxxxxx1x, 8'hXX}); |
| 55 | wildcard state core2_bank1({48'hXXXXXXXX_XXXX, 8'bxxxxx1xx, 8'hXX}); |
| 56 | wildcard state core3_bank1({48'hXXXXXXXX_XXXX, 8'bxxxx1xxx, 8'hXX}); |
| 57 | wildcard state core4_bank1({48'hXXXXXXXX_XXXX, 8'bxxx1xxxx, 8'hXX}); |
| 58 | wildcard state core5_bank1({48'hXXXXXXXX_XXXX, 8'bxx1xxxxx, 8'hXX}); |
| 59 | wildcard state core6_bank1({48'hXXXXXXXX_XXXX, 8'bx1xxxxxx, 8'hXX}); |
| 60 | wildcard state core7_bank1({48'hXXXXXXXX_XXXX, 8'b1xxxxxxx, 8'hXX}); |
| 61 | |
| 62 | wildcard state core0_bank2({40'hXXXXXXXX_XX, 8'bxxxxxxx1, 16'hXXXX}); |
| 63 | wildcard state core1_bank2({40'hXXXXXXXX_XX, 8'bxxxxxx1x, 16'hXXXX}); |
| 64 | wildcard state core2_bank2({40'hXXXXXXXX_XX, 8'bxxxxx1xx, 16'hXXXX}); |
| 65 | wildcard state core3_bank2({40'hXXXXXXXX_XX, 8'bxxxx1xxx, 16'hXXXX}); |
| 66 | wildcard state core4_bank2({40'hXXXXXXXX_XX, 8'bxxx1xxxx, 16'hXXXX}); |
| 67 | wildcard state core5_bank2({40'hXXXXXXXX_XX, 8'bxx1xxxxx, 16'hXXXX}); |
| 68 | wildcard state core6_bank2({40'hXXXXXXXX_XX, 8'bx1xxxxxx, 16'hXXXX}); |
| 69 | wildcard state core7_bank2({40'hXXXXXXXX_XX, 8'b1xxxxxxx, 16'hXXXX}); |
| 70 | |
| 71 | wildcard state core0_bank3({32'hXXXXXXXX, 8'bxxxxxxx1, 24'hXXXXXX}); |
| 72 | wildcard state core1_bank3({32'hXXXXXXXX, 8'bxxxxxx1x, 24'hXXXXXX}); |
| 73 | wildcard state core2_bank3({32'hXXXXXXXX, 8'bxxxxx1xx, 24'hXXXXXX}); |
| 74 | wildcard state core3_bank3({32'hXXXXXXXX, 8'bxxxx1xxx, 24'hXXXXXX}); |
| 75 | wildcard state core4_bank3({32'hXXXXXXXX, 8'bxxx1xxxx, 24'hXXXXXX}); |
| 76 | wildcard state core5_bank3({32'hXXXXXXXX, 8'bxx1xxxxx, 24'hXXXXXX}); |
| 77 | wildcard state core6_bank3({32'hXXXXXXXX, 8'bx1xxxxxx, 24'hXXXXXX}); |
| 78 | wildcard state core7_bank3({32'hXXXXXXXX, 8'b1xxxxxxx, 24'hXXXXXX}); |
| 79 | |
| 80 | |
| 81 | wildcard state core0_bank4({24'hXXXXXX, 8'bxxxxxxx1, 32'hXXXXXXXX}); |
| 82 | wildcard state core1_bank4({24'hXXXXXX, 8'bxxxxxx1x, 32'hXXXXXXXX}); |
| 83 | wildcard state core2_bank4({24'hXXXXXX, 8'bxxxxx1xx, 32'hXXXXXXXX}); |
| 84 | wildcard state core3_bank4({24'hXXXXXX, 8'bxxxx1xxx, 32'hXXXXXXXX}); |
| 85 | wildcard state core4_bank4({24'hXXXXXX, 8'bxxx1xxxx, 32'hXXXXXXXX}); |
| 86 | wildcard state core5_bank4({24'hXXXXXX, 8'bxx1xxxxx, 32'hXXXXXXXX}); |
| 87 | wildcard state core6_bank4({24'hXXXXXX, 8'bx1xxxxxx, 32'hXXXXXXXX}); |
| 88 | wildcard state core7_bank4({24'hXXXXXX, 8'b1xxxxxxx, 32'hXXXXXXXX}); |
| 89 | |
| 90 | wildcard state core0_bank5({16'hXXXX, 8'bxxxxxxx1, 40'hXX_XXXXXXXX}); |
| 91 | wildcard state core1_bank5({16'hXXXX, 8'bxxxxxx1x, 40'hXX_XXXXXXXX}); |
| 92 | wildcard state core2_bank5({16'hXXXX, 8'bxxxxx1xx, 40'hXX_XXXXXXXX}); |
| 93 | wildcard state core3_bank5({16'hXXXX, 8'bxxxx1xxx, 40'hXX_XXXXXXXX}); |
| 94 | wildcard state core4_bank5({16'hXXXX, 8'bxxx1xxxx, 40'hXX_XXXXXXXX}); |
| 95 | wildcard state core5_bank5({16'hXXXX, 8'bxx1xxxxx, 40'hXX_XXXXXXXX}); |
| 96 | wildcard state core6_bank5({16'hXXXX, 8'bx1xxxxxx, 40'hXX_XXXXXXXX}); |
| 97 | wildcard state core7_bank5({16'hXXXX, 8'b1xxxxxxx, 40'hXX_XXXXXXXX}); |
| 98 | |
| 99 | wildcard state core0_bank6({8'hXX, 8'bxxxxxxx1, 48'hXXXX_XXXXXXXX}); |
| 100 | wildcard state core1_bank6({8'hXX, 8'bxxxxxx1x, 48'hXXXX_XXXXXXXX}); |
| 101 | wildcard state core2_bank6({8'hXX, 8'bxxxxx1xx, 48'hXXXX_XXXXXXXX}); |
| 102 | wildcard state core3_bank6({8'hXX, 8'bxxxx1xxx, 48'hXXXX_XXXXXXXX}); |
| 103 | wildcard state core4_bank6({8'hXX, 8'bxxx1xxxx, 48'hXXXX_XXXXXXXX}); |
| 104 | wildcard state core5_bank6({8'hXX, 8'bxx1xxxxx, 48'hXXXX_XXXXXXXX}); |
| 105 | wildcard state core6_bank6({8'hXX, 8'bx1xxxxxx, 48'hXXXX_XXXXXXXX}); |
| 106 | wildcard state core7_bank6({8'hXX, 8'b1xxxxxxx, 48'hXXXX_XXXXXXXX}); |
| 107 | |
| 108 | |
| 109 | wildcard state core0_bank7({8'bxxxxxxx1, 56'hXXXXXX}); |
| 110 | wildcard state core1_bank7({8'bxxxxxx1x, 56'hXXXXXX}); |
| 111 | wildcard state core2_bank7({8'bxxxxx1xx, 56'hXXXXXX}); |
| 112 | wildcard state core3_bank7({8'bxxxx1xxx, 56'hXXXXXX}); |
| 113 | wildcard state core4_bank7({8'bxxx1xxxx, 56'hXXXXXX}); |
| 114 | wildcard state core5_bank7({8'bxx1xxxxx, 56'hXXXXXX}); |
| 115 | wildcard state core6_bank7({8'bx1xxxxxx, 56'hXXXXXX}); |
| 116 | wildcard state core7_bank7({8'b1xxxxxxx, 56'hXXXXXX}); |
| 117 | // } |