| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ccx_pcx_req_sample.vrhpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | state allcores_bank0(128'h01010101_01010101_00000000_00000000); |
| 36 | state allcores_bank1(128'h02020202_02020202_00000000_00000000); |
| 37 | state allcores_bank2(128'h04040404_04040404_00000000_00000000); |
| 38 | state allcores_bank3(128'h08080808_08080808_00000000_00000000); |
| 39 | state allcores_bank4(128'h10101010_10101010_00000000_00000000); |
| 40 | state allcores_bank5(128'h20202020_20202020_00000000_00000000); |
| 41 | state allcores_bank6(128'h40404040_40404040_00000000_00000000); |
| 42 | state allcores_bank7(128'h80808080_80808080_00000000_00000000); |
| 43 | |
| 44 | // 2-packet requests |
| 45 | |
| 46 | state allcores_bank0_atom(128'h01010101_01010101_01010101_01010101); |
| 47 | state allcores_bank1_atom(128'h02020202_02020202_02020202_02020202); |
| 48 | state allcores_bank2_atom(128'h04040404_04040404_04040404_04040404); |
| 49 | state allcores_bank3_atom(128'h08080808_08080808_08080808_08080808); |
| 50 | state allcores_bank4_atom(128'h10101010_10101010_10101010_10101010); |
| 51 | state allcores_bank5_atom(128'h20202020_20202020_20202020_20202020); |
| 52 | state allcores_bank6_atom(128'h40404040_40404040_40404040_40404040); |
| 53 | state allcores_bank7_atom(128'h80808080_80808080_80808080_80808080); |
| 54 | |
| 55 | /* |
| 56 | wildcard state core0_bank0({32'hXXXXXXX1, 8'bxxxxxxx0}); |
| 57 | wildcard state core0_bank1({32'hXXXXXXX2, 8'bxxxxxxx0}); |
| 58 | wildcard state core0_bank2({32'hXXXXXXX4, 8'bxxxxxxx0}); |
| 59 | wildcard state core0_bank3({32'hXXXXXXX8, 8'bxxxxxxx0}); |
| 60 | |
| 61 | wildcard state core1_bank0({32'hXXXXXX1X, 8'bxxxxxx0x}); |
| 62 | wildcard state core1_bank1({32'hXXXXXX2X, 8'bxxxxxx0x}); |
| 63 | wildcard state core1_bank2({32'hXXXXXX4X, 8'bxxxxxx0x}); |
| 64 | wildcard state core1_bank3({32'hXXXXXX8X, 8'bxxxxxx0x}); |
| 65 | |
| 66 | wildcard state core2_bank0({32'hXXXXX1XX, 8'bxxxxx0xx}); |
| 67 | wildcard state core2_bank1({32'hXXXXX2XX, 8'bxxxxx0xx}); |
| 68 | wildcard state core2_bank2({32'hXXXXX4XX, 8'bxxxxx0xx}); |
| 69 | wildcard state core2_bank3({32'hXXXXX8XX, 8'bxxxxx0xx}); |
| 70 | |
| 71 | wildcard state core3_bank0({32'hXXXX1XXX, 8'bxxxx0xxx}); |
| 72 | wildcard state core3_bank1({32'hXXXX2XXX, 8'bxxxx0xxx}); |
| 73 | wildcard state core3_bank2({32'hXXXX4XXX, 8'bxxxx0xxx}); |
| 74 | wildcard state core3_bank3({32'hXXXX8XXX, 8'bxxxx0xxx}); |
| 75 | |
| 76 | wildcard state core4_bank0({32'hXXX1XXXX, 8'bxxx0xxxx}); |
| 77 | wildcard state core4_bank1({32'hXXX2XXXX, 8'bxxx0xxxx}); |
| 78 | wildcard state core4_bank2({32'hXXX4XXXX, 8'bxxx0xxxx}); |
| 79 | wildcard state core4_bank3({32'hXXX8XXXX, 8'bxxx0xxxx}); |
| 80 | |
| 81 | wildcard state core5_bank0({32'hXX1XXXXX, 8'bxx0xxxxx}); |
| 82 | wildcard state core5_bank1({32'hXX2XXXXX, 8'bxx0xxxxx}); |
| 83 | wildcard state core5_bank2({32'hXX4XXXXX, 8'bxx0xxxxx}); |
| 84 | wildcard state core5_bank3({32'hXX8XXXXX, 8'bxx0xxxxx}); |
| 85 | |
| 86 | wildcard state core6_bank0({32'hX1XXXXXX, 8'bx0xxxxxx}); |
| 87 | wildcard state core6_bank1({32'hX2XXXXXX, 8'bx0xxxxxx}); |
| 88 | wildcard state core6_bank2({32'hX4XXXXXX, 8'bx0xxxxxx}); |
| 89 | wildcard state core6_bank3({32'hX8XXXXXX, 8'bx0xxxxxx}); |
| 90 | |
| 91 | wildcard state core7_bank0({32'h1XXXXXXX, 8'b0xxxxxxx}); |
| 92 | wildcard state core7_bank1({32'h2XXXXXXX, 8'b0xxxxxxx}); |
| 93 | wildcard state core7_bank2({32'h4XXXXXXX, 8'b0xxxxxxx}); |
| 94 | wildcard state core7_bank3({32'h8XXXXXXX, 8'b0xxxxxxx}); |
| 95 | */ |
| 96 | /* |
| 97 | wildcard state core0_bank0_atom({32'hXXXXXXX1, 8'bxxxxxxx1}); |
| 98 | wildcard state core0_bank1_atom({32'hXXXXXXX2, 8'bxxxxxxx1}); |
| 99 | wildcard state core0_bank2_atom({32'hXXXXXXX4, 8'bxxxxxxx1}); |
| 100 | wildcard state core0_bank3_atom({32'hXXXXXXX8, 8'bxxxxxxx1}); |
| 101 | |
| 102 | wildcard state core1_bank0_atom({32'hXXXXXX1X, 8'bxxxxxx1x}); |
| 103 | wildcard state core1_bank1_atom({32'hXXXXXX2X, 8'bxxxxxx1x}); |
| 104 | wildcard state core1_bank2_atom({32'hXXXXXX4X, 8'bxxxxxx1x}); |
| 105 | wildcard state core1_bank3_atom({32'hXXXXXX8X, 8'bxxxxxx1x}); |
| 106 | |
| 107 | wildcard state core2_bank0_atom({32'hXXXXX1XX, 8'bxxxxx1xx}); |
| 108 | wildcard state core2_bank1_atom({32'hXXXXX2XX, 8'bxxxxx1xx}); |
| 109 | wildcard state core2_bank2_atom({32'hXXXXX4XX, 8'bxxxxx1xx}); |
| 110 | wildcard state core2_bank3_atom({32'hXXXXX8XX, 8'bxxxxx1xx}); |
| 111 | |
| 112 | wildcard state core3_bank0_atom({32'hXXXX1XXX, 8'bxxxx1xxx}); |
| 113 | wildcard state core3_bank1_atom({32'hXXXX2XXX, 8'bxxxx1xxx}); |
| 114 | wildcard state core3_bank2_atom({32'hXXXX4XXX, 8'bxxxx1xxx}); |
| 115 | wildcard state core3_bank3_atom({32'hXXXX8XXX, 8'bxxxx1xxx}); |
| 116 | |
| 117 | wildcard state core4_bank0_atom({32'hXXX1XXXX, 8'bxxx1xxxx}); |
| 118 | wildcard state core4_bank1_atom({32'hXXX2XXXX, 8'bxxx1xxxx}); |
| 119 | wildcard state core4_bank2_atom({32'hXXX4XXXX, 8'bxxx1xxxx}); |
| 120 | wildcard state core4_bank3_atom({32'hXXX8XXXX, 8'bxxx1xxxx}); |
| 121 | |
| 122 | wildcard state core5_bank0_atom({32'hXX1XXXXX, 8'bxx1xxxxx}); |
| 123 | wildcard state core5_bank1_atom({32'hXX2XXXXX, 8'bxx1xxxxx}); |
| 124 | wildcard state core5_bank2_atom({32'hXX4XXXXX, 8'bxx1xxxxx}); |
| 125 | wildcard state core5_bank3_atom({32'hXX8XXXXX, 8'bxx1xxxxx}); |
| 126 | |
| 127 | wildcard state core6_bank0_atom({32'hX1XXXXXX, 8'bx1xxxxxx}); |
| 128 | wildcard state core6_bank1_atom({32'hX2XXXXXX, 8'bx1xxxxxx}); |
| 129 | wildcard state core6_bank2_atom({32'hX4XXXXXX, 8'bx1xxxxxx}); |
| 130 | wildcard state core6_bank3_atom({32'hX8XXXXXX, 8'bx1xxxxxx}); |
| 131 | |
| 132 | wildcard state core7_bank0_atom({32'h1XXXXXXX, 8'b1xxxxxxx}); |
| 133 | wildcard state core7_bank1_atom({32'h2XXXXXXX, 8'b1xxxxxxx}); |
| 134 | wildcard state core7_bank2_atom({32'h4XXXXXXX, 8'b1xxxxxxx}); |
| 135 | wildcard state core7_bank3_atom({32'h8XXXXXXX, 8'b1xxxxxxx}); |
| 136 | */ |
| 137 | // } |