| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2_two_simultaneous_errors_sample.vrhpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | wildcard state LDAC_and_LDWC ({1'b1, 1'bx, 1'b1, 17'bx}); |
| 36 | wildcard state LDAC_and_LDWU ({1'b1, 2'bx, 1'b1, 16'bx}); |
| 37 | wildcard state LDAC_and_LTC ({1'b1, 7'bx, 1'b1, 11'bx}); |
| 38 | wildcard state LDAC_and_LVC ({1'b1, 16'bx, 1'b1, 2'bx}); |
| 39 | |
| 40 | wildcard state LDAU_and_LDWC ({1'bx, 1'b1, 1'b1, 17'bx}); |
| 41 | wildcard state LDAU_and_LDWU ({1'bx, 1'b1, 1'bx, 1'b1, 16'bx}); |
| 42 | wildcard state LDAU_and_LTC ({1'bx, 1'b1, 6'bx, 1'b1, 11'bx}); |
| 43 | wildcard state LDAU_and_LVC ({1'bx, 1'b1, 15'bx, 1'b1, 2'bx}); |
| 44 | |
| 45 | wildcard state LDRC_and_LDWC ({2'bx, 1'b1, 1'bx, 1'b1, 15'bx}); |
| 46 | wildcard state LDRC_and_LDWU ({3'bx, 1'b1, 1'b1, 15'bx}); |
| 47 | wildcard state LDRC_and_LTC ({4'bx, 1'b1, 3'bx, 1'b1, 11'bx}); |
| 48 | wildcard state LDRC_and_LVC ({4'bx, 1'b1, 14'bx, 1'b1}); |
| 49 | |
| 50 | wildcard state LDRU_and_LDWC ({2'bx, 1'b1, 2'bx, 1'b1, 14'bx}); |
| 51 | wildcard state LDRU_and_LDWU ({3'bx, 1'b1, 1'bx, 1'b1, 14'bx}); |
| 52 | wildcard state LDRU_and_LTC ({5'bx, 1'b1, 2'bx, 1'b1, 11'bx}); |
| 53 | wildcard state LDRU_and_LVC ({5'bx, 1'b1, 11'bx, 1'b1, 2'bx}); |
| 54 | |
| 55 | wildcard state LDSC_and_LDWC ({2'bx, 1'b1, 3'bx, 1'b1, 13'bx}); |
| 56 | wildcard state LDSC_and_LDWU ({3'bx, 1'b1, 2'bx, 1'b1, 13'bx}); |
| 57 | wildcard state LDSC_and_LTC ({6'bx, 1'b1, 1'bx, 1'b1, 11'bx}); |
| 58 | wildcard state LDSC_and_LVC ({6'bx, 1'b1, 10'bx, 1'b1, 2'bx}); |
| 59 | |
| 60 | wildcard state LDSU_and_LDWC ({2'bx, 1'b1, 4'bx, 1'b1, 12'bx}); |
| 61 | wildcard state LDSU_and_LDWU ({3'bx, 1'b1, 3'bx, 1'b1, 12'bx}); |
| 62 | wildcard state LDSU_and_LTC ({7'bx, 1'b1, 1'b1, 11'bx}); |
| 63 | wildcard state LDSU_and_LVC ({7'bx, 1'b1, 9'bx, 1'b1, 2'bx}); |
| 64 | |
| 65 | wildcard state DAC_and_LDWC ({2'bx, 1'b1, 1'bx, 7'bx, 1'b1, 8'bx}); |
| 66 | wildcard state DAC_and_LDWU ({3'bx, 1'b1, 7'bx, 1'b1, 8'bx}); |
| 67 | wildcard state DAC_and_LTC ({8'bx, 1'b1, 2'bx, 1'b1, 8'bx}); |
| 68 | wildcard state DAC_and_LVC ({11'bx, 1'b1, 5'bx, 1'b1, 2'bx}); |
| 69 | |
| 70 | wildcard state DAU_and_LDWC ({2'bx, 1'b1, 1'bx, 8'bx, 1'b1, 7'bx}); |
| 71 | wildcard state DAU_and_LDWU ({3'bx, 1'b1, 8'bx, 1'b1, 7'bx}); |
| 72 | wildcard state DAU_and_LTC ({8'bx, 1'b1, 3'bx, 1'b1, 7'bx}); |
| 73 | wildcard state DAU_and_LVC ({12'bx, 1'b1, 4'bx, 1'b1, 2'bx}); |
| 74 | |
| 75 | wildcard state DRC_and_LDWC ({2'bx, 1'b1, 1'bx, 9'bx, 1'b1, 6'bx}); |
| 76 | wildcard state DRC_and_LDWU ({3'bx, 1'b1, 9'bx, 1'b1, 6'bx}); |
| 77 | wildcard state DRC_and_LTC ({8'bx, 1'b1, 4'bx, 1'b1, 6'bx}); |
| 78 | wildcard state DRC_and_LVC ({13'bx, 1'b1, 3'bx, 1'b1, 2'bx}); |
| 79 | |
| 80 | wildcard state DRU_and_LDWC ({2'bx, 1'b1, 1'bx, 10'bx, 1'b1, 5'bx}); |
| 81 | wildcard state DRU_and_LDWU ({3'bx, 1'b1, 10'bx, 1'b1, 5'bx}); |
| 82 | wildcard state DRU_and_LTC ({8'bx, 1'b1, 5'bx, 1'b1, 5'bx}); |
| 83 | wildcard state DRU_and_LVC ({14'bx, 1'b1, 2'bx, 1'b1, 2'bx}); |
| 84 | |
| 85 | wildcard state DSC_and_LDWC ({2'bx, 1'b1, 1'bx, 11'bx, 1'b1, 4'bx}); |
| 86 | wildcard state DSC_and_LDWU ({3'bx, 1'b1, 11'bx, 1'b1, 4'bx}); |
| 87 | wildcard state DSC_and_LTC ({8'bx, 1'b1, 6'bx, 1'b1, 4'bx}); |
| 88 | wildcard state DSC_and_LVC ({15'bx, 1'b1, 1'bx, 1'b1, 2'bx}); |
| 89 | |
| 90 | wildcard state DSU_and_LDWC ({2'bx, 1'b1, 1'bx, 12'bx, 1'b1, 3'bx}); |
| 91 | wildcard state DSU_and_LDWU ({3'bx, 1'b1, 12'bx, 1'b1, 3'bx}); |
| 92 | wildcard state DSU_and_LTC ({8'bx, 1'b1, 7'bx, 1'b1, 3'bx}); |
| 93 | wildcard state DSU_and_LVC ({16'bx, 1'b1, 1'b1, 2'bx}); |
| 94 | |
| 95 | wildcard state NDSP_and_LDWC ({2'bx, 1'b1, 15'bx, 1'b1, 1'bx}); |
| 96 | wildcard state NDSP_and_LDWU ({3'bx, 1'b1, 14'bx, 1'b1, 1'bx}); |
| 97 | wildcard state NDSP_and_LTC ({8'bx, 1'b1, 9'bx, 1'b1, 1'bx}); |
| 98 | wildcard state NDSP_and_LVC ({17'bx, 1'b1, 1'b1, 1'bx}); |
| 99 | |
| 100 | wildcard state NDDM_and_LDWC ({2'bx, 1'b1, 15'bx, 1'bx, 1'b1}); |
| 101 | wildcard state NDDM_and_LDWU ({3'bx, 1'b1, 14'bx, 1'bx, 1'b1}); |
| 102 | wildcard state NDDM_and_LTC ({8'bx, 1'b1, 9'bx, 1'bx, 1'b1}); |
| 103 | wildcard state NDDM_and_LVC ({17'bx, 1'b1, 1'bx, 1'b1}); |
| 104 | |
| 105 | wildcard state LTC_and_LDWC ({2'bx, 1'b1, 1'bx, 4'bx, 1'b1, 11'bx}); |
| 106 | wildcard state LTC_and_LDWU ({3'bx, 1'b1, 4'bx, 1'b1, 11'bx}); |
| 107 | wildcard state LTC_and_LVC ({8'bx, 1'b1, 8'bx, 1'b1, 2'bx}); |
| 108 | |
| 109 | wildcard state LVC_and_LDWC ({2'bx, 1'b1, 14'bx, 1'b1, 2'bx}); |
| 110 | wildcard state LVC_and_LDWU ({3'bx, 1'b1, 13'bx, 1'b1, 2'bx}); |
| 111 | |
| 112 | |