| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ios_ras_chkr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define TB_RST ~(tb_top.cpu.l2t0.rst_wmr_) |
| 36 | |
| 37 | module ios_ras_chkr; |
| 38 | |
| 39 | |
| 40 | reg no_ras_chk ; |
| 41 | initial begin // { |
| 42 | @(posedge tb_top.cpu.ncu.iol2clk) ; |
| 43 | if ($test$plusargs("ios_0in_ras_chk_off")) |
| 44 | no_ras_chk <= 1; |
| 45 | else |
| 46 | no_ras_chk <= 0; |
| 47 | end //} |
| 48 | |
| 49 | // 0in disable_checker -name *ios_ras* no_ras_chk |
| 50 | |
| 51 | /* 0in |
| 52 | never |
| 53 | -var |(tb_top.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_esr) |
| 54 | -clock tb_top.cpu.ncu.iol2clk |
| 55 | -name ios_ras_ncu_esr_chk |
| 56 | -reset `TB_RST |
| 57 | */ |
| 58 | |
| 59 | /* 0in |
| 60 | never |
| 61 | -var |(tb_top.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_per) |
| 62 | -clock tb_top.cpu.ncu.iol2clk |
| 63 | -name ios_ras_ncu_per_chk |
| 64 | -reset `TB_RST |
| 65 | */ |
| 66 | |
| 67 | |
| 68 | // SIU-NIU, SIU-DMU and SIU-NCU Interfaces: Errror bits should never be on for non-error diags |
| 69 | /* 0in |
| 70 | never |
| 71 | -var ((|(dmu_sii_data[82:80]) & dmu_sii_hdr_vld) | (|(sio_dmu_data[82:80]) & sio_dmu_hdr_vld) | (|(niu_sii_data[82:80]) & niu_sii_hdr_vld) | (|(sio_niu_data[82:80]) & sio_niu_hdr_vld) | (|(sii_ncu_data[31:28]) & $0in_delay(ncu_sii_gnt, 1))) |
| 72 | -module cpu |
| 73 | -clock tb_top.cpu.sii.iol2clk |
| 74 | -name ios_ras_io_err_bit_chk |
| 75 | -reset `TB_RST |
| 76 | */ |
| 77 | |
| 78 | |
| 79 | // SIU-L2 Interface: Errror bits should never be on for non-error diags |
| 80 | /* 0in |
| 81 | never |
| 82 | -var ((sii_l2t0_req[28] & sii_l2t0_req_vld) | (sii_l2t1_req[28] & sii_l2t1_req_vld) | (sii_l2t2_req[28] & sii_l2t2_req_vld) | (sii_l2t3_req[28] & sii_l2t3_req_vld) | (sii_l2t4_req[28] & sii_l2t4_req_vld) | (sii_l2t5_req[28] & sii_l2t5_req_vld) | (sii_l2t6_req[28] & sii_l2t6_req_vld) | (sii_l2t7_req[28] & sii_l2t7_req_vld) | ((l2b0_sio_data[24] | l2b0_sio_data[21]) & l2b0_sio_ctag_vld) | ((l2b1_sio_data[24] | l2b1_sio_data[21]) & l2b1_sio_ctag_vld) | ((l2b2_sio_data[24] | l2b2_sio_data[21]) & l2b2_sio_ctag_vld) | ((l2b3_sio_data[24] | l2b3_sio_data[21]) & l2b3_sio_ctag_vld) | ((l2b4_sio_data[24] | l2b4_sio_data[21]) & l2b4_sio_ctag_vld) | ((l2b5_sio_data[24] | l2b5_sio_data[21]) & l2b5_sio_ctag_vld) | ((l2b6_sio_data[24] | l2b6_sio_data[21]) & l2b6_sio_ctag_vld) | ((l2b7_sio_data[24] | l2b7_sio_data[21]) & l2b7_sio_ctag_vld)) |
| 83 | -module cpu |
| 84 | -clock tb_top.cpu.sii.l2clk |
| 85 | -name ios_ras_l2_err_bit_chk |
| 86 | -reset `TB_RST |
| 87 | */ |
| 88 | |
| 89 | // CPX Pkt Errror bits should never be on for non-error diags |
| 90 | /* 0in |
| 91 | never |
| 92 | -var |ncu_cpx_data_ca[139:138] |
| 93 | -module cpu |
| 94 | -clock tb_top.cpu.ncu.iol2clk |
| 95 | -name ios_ras_cpx_err_bit_chk |
| 96 | -reset `TB_RST |
| 97 | */ |
| 98 | |
| 99 | // All blocks to NCU: Errror bits should never be on for non-error diags |
| 100 | /* 0in |
| 101 | never |
| 102 | -var (dmu_ncu_ctag_ce | dmu_ncu_ctag_ue | dmu_ncu_d_pe | dmu_ncu_ie | dmu_ncu_ncucr_pe | dmu_ncu_siicr_pe | niu_ncu_ctag_ce | niu_ncu_ctag_ue | niu_ncu_d_pe | sii_ncu_dmua_pe | sii_ncu_dmuctag_ce | sii_ncu_dmuctag_ue | sii_ncu_dmud_pe | sii_ncu_niuctag_ce | sii_ncu_niuctag_ue | sii_ncu_niud_pe | sii_ncu_niua_pe | sio_ncu_ctag_ce | sio_ncu_ctag_ue | mcu0_ncu_ecc | mcu0_ncu_fbr | mcu1_ncu_ecc | mcu1_ncu_fbr | mcu2_ncu_ecc | mcu2_ncu_fbr | mcu3_ncu_ecc | mcu3_ncu_fbr) |
| 103 | -module cpu |
| 104 | -clock tb_top.cpu.ncu.iol2clk |
| 105 | -name ios_ras_err_report_chk |
| 106 | -reset `TB_RST |
| 107 | */ |
| 108 | |
| 109 | |
| 110 | |
| 111 | |
| 112 | /***************************************************/ |
| 113 | |
| 114 | |
| 115 | |
| 116 | // Hunter's FC checkers |
| 117 | |
| 118 | // Testfail status bus |
| 119 | |
| 120 | // MCU0 FSR0 RX |
| 121 | |
| 122 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.stsrx0[0] -val `CPU.mcu0.fbd0.frdbuf0.fsr_stsrx_testfail |
| 123 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 124 | |
| 125 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.stsrx1[0] -val `CPU.mcu0.fbd0.frdbuf1.fsr_stsrx_testfail |
| 126 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 127 | |
| 128 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.stsrx2[0] -val `CPU.mcu0.fbd0.frdbuf2.fsr_stsrx_testfail |
| 129 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 130 | |
| 131 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.stsrx3[0] -val `CPU.mcu0.fbd0.frdbuf3.fsr_stsrx_testfail |
| 132 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 133 | |
| 134 | /* 0in value -var `CPU.fsr_left.fsr0_a8.stsrx0[0] -val `CPU.mcu0.fbd0.frdbuf4.fsr_stsrx_testfail |
| 135 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 136 | |
| 137 | /* 0in value -var `CPU.fsr_left.fsr0_a8.stsrx1[0] -val `CPU.mcu0.fbd0.frdbuf5.fsr_stsrx_testfail |
| 138 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 139 | |
| 140 | /* 0in value -var `CPU.fsr_left.fsr0_a8.stsrx2[0] -val `CPU.mcu0.fbd0.frdbuf6.fsr_stsrx_testfail |
| 141 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 142 | |
| 143 | /* 0in value -var `CPU.fsr_left.fsr0_a8.stsrx3[0] -val `CPU.mcu0.fbd0.frdbuf7.fsr_stsrx_testfail |
| 144 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 145 | |
| 146 | /* 0in value -var `CPU.fsr_left.fsr0_a8.stsrx4[0] -val `CPU.mcu0.fbd0.frdbuf8.fsr_stsrx_testfail |
| 147 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 148 | |
| 149 | /* 0in value -var `CPU.fsr_left.fsr0_a8.stsrx5[0] -val `CPU.mcu0.fbd0.frdbuf9.fsr_stsrx_testfail |
| 150 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 151 | |
| 152 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.stsrx0[0] -val `CPU.mcu0.fbd0.frdbuf10.fsr_stsrx_testfail |
| 153 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 154 | |
| 155 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.stsrx1[0] -val `CPU.mcu0.fbd0.frdbuf11.fsr_stsrx_testfail |
| 156 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 157 | |
| 158 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.stsrx2[0] -val `CPU.mcu0.fbd0.frdbuf12.fsr_stsrx_testfail |
| 159 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 160 | |
| 161 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.stsrx3[0] -val `CPU.mcu0.fbd0.frdbuf13.fsr_stsrx_testfail |
| 162 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 163 | |
| 164 | // MCU0 FSR1 RX |
| 165 | |
| 166 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.stsrx0[0] -val `CPU.mcu0.fbd1.frdbuf0.fsr_stsrx_testfail |
| 167 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 168 | |
| 169 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.stsrx1[0] -val `CPU.mcu0.fbd1.frdbuf1.fsr_stsrx_testfail |
| 170 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 171 | |
| 172 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.stsrx2[0] -val `CPU.mcu0.fbd1.frdbuf2.fsr_stsrx_testfail |
| 173 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 174 | |
| 175 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.stsrx3[0] -val `CPU.mcu0.fbd1.frdbuf3.fsr_stsrx_testfail |
| 176 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 177 | |
| 178 | /* 0in value -var `CPU.fsr_left.fsr1_a8.stsrx0[0] -val `CPU.mcu0.fbd1.frdbuf4.fsr_stsrx_testfail |
| 179 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 180 | |
| 181 | /* 0in value -var `CPU.fsr_left.fsr1_a8.stsrx1[0] -val `CPU.mcu0.fbd1.frdbuf5.fsr_stsrx_testfail |
| 182 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 183 | |
| 184 | /* 0in value -var `CPU.fsr_left.fsr1_a8.stsrx2[0] -val `CPU.mcu0.fbd1.frdbuf6.fsr_stsrx_testfail |
| 185 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 186 | |
| 187 | /* 0in value -var `CPU.fsr_left.fsr1_a8.stsrx3[0] -val `CPU.mcu0.fbd1.frdbuf7.fsr_stsrx_testfail |
| 188 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 189 | |
| 190 | /* 0in value -var `CPU.fsr_left.fsr1_a8.stsrx4[0] -val `CPU.mcu0.fbd1.frdbuf8.fsr_stsrx_testfail |
| 191 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 192 | |
| 193 | /* 0in value -var `CPU.fsr_left.fsr1_a8.stsrx5[0] -val `CPU.mcu0.fbd1.frdbuf9.fsr_stsrx_testfail |
| 194 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 195 | |
| 196 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.stsrx0[0] -val `CPU.mcu0.fbd1.frdbuf10.fsr_stsrx_testfail |
| 197 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 198 | |
| 199 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.stsrx1[0] -val `CPU.mcu0.fbd1.frdbuf11.fsr_stsrx_testfail |
| 200 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 201 | |
| 202 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.stsrx2[0] -val `CPU.mcu0.fbd1.frdbuf12.fsr_stsrx_testfail |
| 203 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 204 | |
| 205 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.stsrx3[0] -val `CPU.mcu0.fbd1.frdbuf13.fsr_stsrx_testfail |
| 206 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 207 | |
| 208 | // MCU1 FSR2 RX |
| 209 | |
| 210 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.stsrx0[0] -val `CPU.mcu1.fbd0.frdbuf0.fsr_stsrx_testfail |
| 211 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 212 | |
| 213 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.stsrx1[0] -val `CPU.mcu1.fbd0.frdbuf1.fsr_stsrx_testfail |
| 214 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 215 | |
| 216 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.stsrx2[0] -val `CPU.mcu1.fbd0.frdbuf2.fsr_stsrx_testfail |
| 217 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 218 | |
| 219 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.stsrx3[0] -val `CPU.mcu1.fbd0.frdbuf3.fsr_stsrx_testfail |
| 220 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 221 | |
| 222 | /* 0in value -var `CPU.fsr_left.fsr2_a8.stsrx0[0] -val `CPU.mcu1.fbd0.frdbuf4.fsr_stsrx_testfail |
| 223 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 224 | |
| 225 | /* 0in value -var `CPU.fsr_left.fsr2_a8.stsrx1[0] -val `CPU.mcu1.fbd0.frdbuf5.fsr_stsrx_testfail |
| 226 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 227 | |
| 228 | /* 0in value -var `CPU.fsr_left.fsr2_a8.stsrx2[0] -val `CPU.mcu1.fbd0.frdbuf6.fsr_stsrx_testfail |
| 229 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 230 | |
| 231 | /* 0in value -var `CPU.fsr_left.fsr2_a8.stsrx3[0] -val `CPU.mcu1.fbd0.frdbuf7.fsr_stsrx_testfail |
| 232 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 233 | |
| 234 | /* 0in value -var `CPU.fsr_left.fsr2_a8.stsrx4[0] -val `CPU.mcu1.fbd0.frdbuf8.fsr_stsrx_testfail |
| 235 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 236 | |
| 237 | /* 0in value -var `CPU.fsr_left.fsr2_a8.stsrx5[0] -val `CPU.mcu1.fbd0.frdbuf9.fsr_stsrx_testfail |
| 238 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 239 | |
| 240 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.stsrx0[0] -val `CPU.mcu1.fbd0.frdbuf10.fsr_stsrx_testfail |
| 241 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 242 | |
| 243 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.stsrx1[0] -val `CPU.mcu1.fbd0.frdbuf11.fsr_stsrx_testfail |
| 244 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 245 | |
| 246 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.stsrx2[0] -val `CPU.mcu1.fbd0.frdbuf12.fsr_stsrx_testfail |
| 247 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 248 | |
| 249 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.stsrx3[0] -val `CPU.mcu1.fbd0.frdbuf13.fsr_stsrx_testfail |
| 250 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 251 | |
| 252 | // MCU1 FSR3 RX |
| 253 | |
| 254 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.stsrx0[0] -val `CPU.mcu1.fbd1.frdbuf0.fsr_stsrx_testfail |
| 255 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 256 | |
| 257 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.stsrx1[0] -val `CPU.mcu1.fbd1.frdbuf1.fsr_stsrx_testfail |
| 258 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 259 | |
| 260 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.stsrx2[0] -val `CPU.mcu1.fbd1.frdbuf2.fsr_stsrx_testfail |
| 261 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 262 | |
| 263 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.stsrx3[0] -val `CPU.mcu1.fbd1.frdbuf3.fsr_stsrx_testfail |
| 264 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 265 | |
| 266 | /* 0in value -var `CPU.fsr_left.fsr3_a8.stsrx0[0] -val `CPU.mcu1.fbd1.frdbuf4.fsr_stsrx_testfail |
| 267 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 268 | |
| 269 | /* 0in value -var `CPU.fsr_left.fsr3_a8.stsrx1[0] -val `CPU.mcu1.fbd1.frdbuf5.fsr_stsrx_testfail |
| 270 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 271 | |
| 272 | /* 0in value -var `CPU.fsr_left.fsr3_a8.stsrx2[0] -val `CPU.mcu1.fbd1.frdbuf6.fsr_stsrx_testfail |
| 273 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 274 | |
| 275 | /* 0in value -var `CPU.fsr_left.fsr3_a8.stsrx3[0] -val `CPU.mcu1.fbd1.frdbuf7.fsr_stsrx_testfail |
| 276 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 277 | |
| 278 | /* 0in value -var `CPU.fsr_left.fsr3_a8.stsrx4[0] -val `CPU.mcu1.fbd1.frdbuf8.fsr_stsrx_testfail |
| 279 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 280 | |
| 281 | /* 0in value -var `CPU.fsr_left.fsr3_a8.stsrx5[0] -val `CPU.mcu1.fbd1.frdbuf9.fsr_stsrx_testfail |
| 282 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 283 | |
| 284 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.stsrx0[0] -val `CPU.mcu1.fbd1.frdbuf10.fsr_stsrx_testfail |
| 285 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 286 | |
| 287 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.stsrx1[0] -val `CPU.mcu1.fbd1.frdbuf11.fsr_stsrx_testfail |
| 288 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 289 | |
| 290 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.stsrx2[0] -val `CPU.mcu1.fbd1.frdbuf12.fsr_stsrx_testfail |
| 291 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 292 | |
| 293 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.stsrx3[0] -val `CPU.mcu1.fbd1.frdbuf13.fsr_stsrx_testfail |
| 294 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 295 | |
| 296 | |
| 297 | // MCU2 FSR4 RX |
| 298 | |
| 299 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.stsrx0[0] -val `CPU.mcu2.fbd0.frdbuf0.fsr_stsrx_testfail |
| 300 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 301 | |
| 302 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.stsrx1[0] -val `CPU.mcu2.fbd0.frdbuf1.fsr_stsrx_testfail |
| 303 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 304 | |
| 305 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.stsrx2[0] -val `CPU.mcu2.fbd0.frdbuf2.fsr_stsrx_testfail |
| 306 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 307 | |
| 308 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.stsrx3[0] -val `CPU.mcu2.fbd0.frdbuf3.fsr_stsrx_testfail |
| 309 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 310 | |
| 311 | /* 0in value -var `CPU.fsr_right.fsr4_a8.stsrx0[0] -val `CPU.mcu2.fbd0.frdbuf4.fsr_stsrx_testfail |
| 312 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 313 | |
| 314 | /* 0in value -var `CPU.fsr_right.fsr4_a8.stsrx1[0] -val `CPU.mcu2.fbd0.frdbuf5.fsr_stsrx_testfail |
| 315 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 316 | |
| 317 | /* 0in value -var `CPU.fsr_right.fsr4_a8.stsrx2[0] -val `CPU.mcu2.fbd0.frdbuf6.fsr_stsrx_testfail |
| 318 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 319 | |
| 320 | /* 0in value -var `CPU.fsr_right.fsr4_a8.stsrx3[0] -val `CPU.mcu2.fbd0.frdbuf7.fsr_stsrx_testfail |
| 321 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 322 | |
| 323 | /* 0in value -var `CPU.fsr_right.fsr4_a8.stsrx4[0] -val `CPU.mcu2.fbd0.frdbuf8.fsr_stsrx_testfail |
| 324 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 325 | |
| 326 | /* 0in value -var `CPU.fsr_right.fsr4_a8.stsrx5[0] -val `CPU.mcu2.fbd0.frdbuf9.fsr_stsrx_testfail |
| 327 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 328 | |
| 329 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.stsrx0[0] -val `CPU.mcu2.fbd0.frdbuf10.fsr_stsrx_testfail |
| 330 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 331 | |
| 332 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.stsrx1[0] -val `CPU.mcu2.fbd0.frdbuf11.fsr_stsrx_testfail |
| 333 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 334 | |
| 335 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.stsrx2[0] -val `CPU.mcu2.fbd0.frdbuf12.fsr_stsrx_testfail |
| 336 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 337 | |
| 338 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.stsrx3[0] -val `CPU.mcu2.fbd0.frdbuf13.fsr_stsrx_testfail |
| 339 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 340 | |
| 341 | |
| 342 | // MCU2 FSR5 RX |
| 343 | |
| 344 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.stsrx0[0] -val `CPU.mcu2.fbd1.frdbuf0.fsr_stsrx_testfail |
| 345 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 346 | |
| 347 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.stsrx1[0] -val `CPU.mcu2.fbd1.frdbuf1.fsr_stsrx_testfail |
| 348 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 349 | |
| 350 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.stsrx2[0] -val `CPU.mcu2.fbd1.frdbuf2.fsr_stsrx_testfail |
| 351 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 352 | |
| 353 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.stsrx3[0] -val `CPU.mcu2.fbd1.frdbuf3.fsr_stsrx_testfail |
| 354 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 355 | |
| 356 | /* 0in value -var `CPU.fsr_right.fsr5_a8.stsrx0[0] -val `CPU.mcu2.fbd1.frdbuf4.fsr_stsrx_testfail |
| 357 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 358 | |
| 359 | /* 0in value -var `CPU.fsr_right.fsr5_a8.stsrx1[0] -val `CPU.mcu2.fbd1.frdbuf5.fsr_stsrx_testfail |
| 360 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 361 | |
| 362 | /* 0in value -var `CPU.fsr_right.fsr5_a8.stsrx2[0] -val `CPU.mcu2.fbd1.frdbuf6.fsr_stsrx_testfail |
| 363 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 364 | |
| 365 | /* 0in value -var `CPU.fsr_right.fsr5_a8.stsrx3[0] -val `CPU.mcu2.fbd1.frdbuf7.fsr_stsrx_testfail |
| 366 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 367 | |
| 368 | /* 0in value -var `CPU.fsr_right.fsr5_a8.stsrx4[0] -val `CPU.mcu2.fbd1.frdbuf8.fsr_stsrx_testfail |
| 369 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 370 | |
| 371 | /* 0in value -var `CPU.fsr_right.fsr5_a8.stsrx5[0] -val `CPU.mcu2.fbd1.frdbuf9.fsr_stsrx_testfail |
| 372 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 373 | |
| 374 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.stsrx0[0] -val `CPU.mcu2.fbd1.frdbuf10.fsr_stsrx_testfail |
| 375 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 376 | |
| 377 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.stsrx1[0] -val `CPU.mcu2.fbd1.frdbuf11.fsr_stsrx_testfail |
| 378 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 379 | |
| 380 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.stsrx2[0] -val `CPU.mcu2.fbd1.frdbuf12.fsr_stsrx_testfail |
| 381 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 382 | |
| 383 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.stsrx3[0] -val `CPU.mcu2.fbd1.frdbuf13.fsr_stsrx_testfail |
| 384 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 385 | |
| 386 | // MCU3 FSR6 RX |
| 387 | |
| 388 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.stsrx0[0] -val `CPU.mcu3.fbd0.frdbuf0.fsr_stsrx_testfail |
| 389 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 390 | |
| 391 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.stsrx1[0] -val `CPU.mcu3.fbd0.frdbuf1.fsr_stsrx_testfail |
| 392 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 393 | |
| 394 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.stsrx2[0] -val `CPU.mcu3.fbd0.frdbuf2.fsr_stsrx_testfail |
| 395 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 396 | |
| 397 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.stsrx3[0] -val `CPU.mcu3.fbd0.frdbuf3.fsr_stsrx_testfail |
| 398 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 399 | |
| 400 | /* 0in value -var `CPU.fsr_right.fsr6_a8.stsrx0[0] -val `CPU.mcu3.fbd0.frdbuf4.fsr_stsrx_testfail |
| 401 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 402 | |
| 403 | /* 0in value -var `CPU.fsr_right.fsr6_a8.stsrx1[0] -val `CPU.mcu3.fbd0.frdbuf5.fsr_stsrx_testfail |
| 404 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 405 | |
| 406 | /* 0in value -var `CPU.fsr_right.fsr6_a8.stsrx2[0] -val `CPU.mcu3.fbd0.frdbuf6.fsr_stsrx_testfail |
| 407 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 408 | |
| 409 | /* 0in value -var `CPU.fsr_right.fsr6_a8.stsrx3[0] -val `CPU.mcu3.fbd0.frdbuf7.fsr_stsrx_testfail |
| 410 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 411 | |
| 412 | /* 0in value -var `CPU.fsr_right.fsr6_a8.stsrx4[0] -val `CPU.mcu3.fbd0.frdbuf8.fsr_stsrx_testfail |
| 413 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 414 | |
| 415 | /* 0in value -var `CPU.fsr_right.fsr6_a8.stsrx5[0] -val `CPU.mcu3.fbd0.frdbuf9.fsr_stsrx_testfail |
| 416 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 417 | |
| 418 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.stsrx0[0] -val `CPU.mcu3.fbd0.frdbuf10.fsr_stsrx_testfail |
| 419 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 420 | |
| 421 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.stsrx1[0] -val `CPU.mcu3.fbd0.frdbuf11.fsr_stsrx_testfail |
| 422 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 423 | |
| 424 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.stsrx2[0] -val `CPU.mcu3.fbd0.frdbuf12.fsr_stsrx_testfail |
| 425 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 426 | |
| 427 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.stsrx3[0] -val `CPU.mcu3.fbd0.frdbuf13.fsr_stsrx_testfail |
| 428 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 429 | |
| 430 | |
| 431 | // MCU3 FSR7 RX |
| 432 | |
| 433 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.stsrx0[0] -val `CPU.mcu3.fbd1.frdbuf0.fsr_stsrx_testfail |
| 434 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 435 | |
| 436 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.stsrx1[0] -val `CPU.mcu3.fbd1.frdbuf1.fsr_stsrx_testfail |
| 437 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 438 | |
| 439 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.stsrx2[0] -val `CPU.mcu3.fbd1.frdbuf2.fsr_stsrx_testfail |
| 440 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 441 | |
| 442 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.stsrx3[0] -val `CPU.mcu3.fbd1.frdbuf3.fsr_stsrx_testfail |
| 443 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 444 | |
| 445 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.stsrx0[0] -val `CPU.mcu3.fbd1.frdbuf4.fsr_stsrx_testfail |
| 446 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 447 | |
| 448 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.stsrx1[0] -val `CPU.mcu3.fbd1.frdbuf5.fsr_stsrx_testfail |
| 449 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 450 | |
| 451 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.stsrx2[0] -val `CPU.mcu3.fbd1.frdbuf6.fsr_stsrx_testfail |
| 452 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 453 | |
| 454 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.stsrx3[0] -val `CPU.mcu3.fbd1.frdbuf7.fsr_stsrx_testfail |
| 455 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 456 | |
| 457 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.stsrx4[0] -val `CPU.mcu3.fbd1.frdbuf8.fsr_stsrx_testfail |
| 458 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 459 | |
| 460 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.stsrx5[0] -val `CPU.mcu3.fbd1.frdbuf9.fsr_stsrx_testfail |
| 461 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 462 | |
| 463 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.stsrx0[0] -val `CPU.mcu3.fbd1.frdbuf10.fsr_stsrx_testfail |
| 464 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 465 | |
| 466 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.stsrx1[0] -val `CPU.mcu3.fbd1.frdbuf11.fsr_stsrx_testfail |
| 467 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 468 | |
| 469 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.stsrx2[0] -val `CPU.mcu3.fbd1.frdbuf12.fsr_stsrx_testfail |
| 470 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 471 | |
| 472 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.stsrx3[0] -val `CPU.mcu3.fbd1.frdbuf13.fsr_stsrx_testfail |
| 473 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 474 | |
| 475 | // MCU0 FSR0 TX |
| 476 | |
| 477 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.ststx0[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[0] |
| 478 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 479 | |
| 480 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.ststx1[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[1] |
| 481 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 482 | |
| 483 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.ststx2[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[2] |
| 484 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 485 | |
| 486 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.ststx3[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[3] |
| 487 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 488 | |
| 489 | /* 0in value -var `CPU.fsr_left.fsr0_a8.ststx0[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[4] |
| 490 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 491 | |
| 492 | /* 0in value -var `CPU.fsr_left.fsr0_a8.ststx1[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[5] |
| 493 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 494 | |
| 495 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.ststx0[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[6] |
| 496 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 497 | |
| 498 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.ststx1[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[7] |
| 499 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 500 | |
| 501 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.ststx2[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[8] |
| 502 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 503 | |
| 504 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.ststx3[0] -val `CPU.mcu0.fbdic.fsr0_mcu_ststx_testfail[9] |
| 505 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 506 | |
| 507 | |
| 508 | // MCU0 FSR1 TX |
| 509 | |
| 510 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.ststx0[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[0] |
| 511 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 512 | |
| 513 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.ststx1[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[1] |
| 514 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 515 | |
| 516 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.ststx2[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[2] |
| 517 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 518 | |
| 519 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.ststx3[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[3] |
| 520 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 521 | |
| 522 | /* 0in value -var `CPU.fsr_left.fsr1_a8.ststx0[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[4] |
| 523 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 524 | |
| 525 | /* 0in value -var `CPU.fsr_left.fsr1_a8.ststx1[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[5] |
| 526 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 527 | |
| 528 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.ststx0[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[6] |
| 529 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 530 | |
| 531 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.ststx1[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[7] |
| 532 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 533 | |
| 534 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.ststx2[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[8] |
| 535 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 536 | |
| 537 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.ststx3[0] -val `CPU.mcu0.fbdic.fsr1_mcu_ststx_testfail[9] |
| 538 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 539 | |
| 540 | |
| 541 | // MCU1 FSR2 TX |
| 542 | |
| 543 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.ststx0[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[0] |
| 544 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 545 | |
| 546 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.ststx1[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[1] |
| 547 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 548 | |
| 549 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.ststx2[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[2] |
| 550 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 551 | |
| 552 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.ststx3[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[3] |
| 553 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 554 | |
| 555 | /* 0in value -var `CPU.fsr_left.fsr2_a8.ststx0[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[4] |
| 556 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 557 | |
| 558 | /* 0in value -var `CPU.fsr_left.fsr2_a8.ststx1[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[5] |
| 559 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 560 | |
| 561 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.ststx0[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[6] |
| 562 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 563 | |
| 564 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.ststx1[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[7] |
| 565 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 566 | |
| 567 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.ststx2[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[8] |
| 568 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 569 | |
| 570 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.ststx3[0] -val `CPU.mcu1.fbdic.fsr0_mcu_ststx_testfail[9] |
| 571 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 572 | |
| 573 | |
| 574 | // MCU1 FSR3 TX |
| 575 | |
| 576 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.ststx0[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[0] |
| 577 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 578 | |
| 579 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.ststx1[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[1] |
| 580 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 581 | |
| 582 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.ststx2[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[2] |
| 583 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 584 | |
| 585 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.ststx3[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[3] |
| 586 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 587 | |
| 588 | /* 0in value -var `CPU.fsr_left.fsr3_a8.ststx0[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[4] |
| 589 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 590 | |
| 591 | /* 0in value -var `CPU.fsr_left.fsr3_a8.ststx1[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[5] |
| 592 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 593 | |
| 594 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.ststx0[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[6] |
| 595 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 596 | |
| 597 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.ststx1[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[7] |
| 598 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 599 | |
| 600 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.ststx2[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[8] |
| 601 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 602 | |
| 603 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.ststx3[0] -val `CPU.mcu1.fbdic.fsr1_mcu_ststx_testfail[9] |
| 604 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 605 | |
| 606 | |
| 607 | // MCU2 FSR4 TX |
| 608 | |
| 609 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.ststx0[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[0] |
| 610 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 611 | |
| 612 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.ststx1[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[1] |
| 613 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 614 | |
| 615 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.ststx2[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[2] |
| 616 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 617 | |
| 618 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.ststx3[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[3] |
| 619 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 620 | |
| 621 | /* 0in value -var `CPU.fsr_right.fsr4_a8.ststx0[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[4] |
| 622 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 623 | |
| 624 | /* 0in value -var `CPU.fsr_right.fsr4_a8.ststx1[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[5] |
| 625 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 626 | |
| 627 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.ststx0[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[6] |
| 628 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 629 | |
| 630 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.ststx1[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[7] |
| 631 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 632 | |
| 633 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.ststx2[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[8] |
| 634 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 635 | |
| 636 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.ststx3[0] -val `CPU.mcu2.fbdic.fsr0_mcu_ststx_testfail[9] |
| 637 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 638 | |
| 639 | |
| 640 | // MCU2 FSR5 TX |
| 641 | |
| 642 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.ststx0[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[0] |
| 643 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 644 | |
| 645 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.ststx1[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[1] |
| 646 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 647 | |
| 648 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.ststx2[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[2] |
| 649 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 650 | |
| 651 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.ststx3[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[3] |
| 652 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 653 | |
| 654 | /* 0in value -var `CPU.fsr_right.fsr5_a8.ststx0[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[4] |
| 655 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 656 | |
| 657 | /* 0in value -var `CPU.fsr_right.fsr5_a8.ststx1[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[5] |
| 658 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 659 | |
| 660 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.ststx0[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[6] |
| 661 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 662 | |
| 663 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.ststx1[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[7] |
| 664 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 665 | |
| 666 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.ststx2[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[8] |
| 667 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 668 | |
| 669 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.ststx3[0] -val `CPU.mcu2.fbdic.fsr1_mcu_ststx_testfail[9] |
| 670 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 671 | |
| 672 | |
| 673 | // MCU3 FSR6 TX |
| 674 | |
| 675 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.ststx0[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[0] |
| 676 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 677 | |
| 678 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.ststx1[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[1] |
| 679 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 680 | |
| 681 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.ststx2[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[2] |
| 682 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 683 | |
| 684 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.ststx3[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[3] |
| 685 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 686 | |
| 687 | /* 0in value -var `CPU.fsr_right.fsr6_a8.ststx0[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[4] |
| 688 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 689 | |
| 690 | /* 0in value -var `CPU.fsr_right.fsr6_a8.ststx1[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[5] |
| 691 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 692 | |
| 693 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.ststx0[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[6] |
| 694 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 695 | |
| 696 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.ststx1[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[7] |
| 697 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 698 | |
| 699 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.ststx2[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[8] |
| 700 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 701 | |
| 702 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.ststx3[0] -val `CPU.mcu3.fbdic.fsr0_mcu_ststx_testfail[9] |
| 703 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 704 | |
| 705 | |
| 706 | // MCU3 FSR7 TX |
| 707 | |
| 708 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.ststx0[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[0] |
| 709 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 710 | |
| 711 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.ststx1[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[1] |
| 712 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 713 | |
| 714 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.ststx2[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[2] |
| 715 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 716 | |
| 717 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.ststx3[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[3] |
| 718 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 719 | |
| 720 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.ststx0[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[4] |
| 721 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 722 | |
| 723 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.ststx1[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[5] |
| 724 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 725 | |
| 726 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.ststx0[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[6] |
| 727 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 728 | |
| 729 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.ststx1[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[7] |
| 730 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 731 | |
| 732 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.ststx2[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[8] |
| 733 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 734 | |
| 735 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.ststx3[0] -val `CPU.mcu3.fbdic.fsr1_mcu_ststx_testfail[9] |
| 736 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 737 | |
| 738 | |
| 739 | // Serdes Transmitter Receiver Differential Pair Inversion |
| 740 | |
| 741 | // Now for MCU0: FRS0: Lets do RX first 4 ports (INVPAIR) |
| 742 | |
| 743 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[0] |
| 744 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 745 | |
| 746 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[1] |
| 747 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 748 | |
| 749 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[2] |
| 750 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 751 | |
| 752 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[3] |
| 753 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 754 | |
| 755 | |
| 756 | // Now for TX first 4 ports (INVPAIR) |
| 757 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[28] |
| 758 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 759 | |
| 760 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[29] |
| 761 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 762 | |
| 763 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[30] |
| 764 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 765 | |
| 766 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[31] |
| 767 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 768 | |
| 769 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 770 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[4] |
| 771 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 772 | |
| 773 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[5] |
| 774 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 775 | |
| 776 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[6] |
| 777 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 778 | |
| 779 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[7] |
| 780 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 781 | |
| 782 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx4[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[8] |
| 783 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 784 | |
| 785 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx5[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[9] |
| 786 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 787 | |
| 788 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[32] |
| 789 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 790 | |
| 791 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[33] |
| 792 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 793 | |
| 794 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 795 | |
| 796 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[10] |
| 797 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 798 | |
| 799 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[11] |
| 800 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 801 | |
| 802 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[12] |
| 803 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 804 | |
| 805 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[13] |
| 806 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 807 | |
| 808 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[34] |
| 809 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 810 | |
| 811 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[35] |
| 812 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 813 | |
| 814 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[36] |
| 815 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 816 | |
| 817 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[37] |
| 818 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 819 | |
| 820 | // Now for FSR1 |
| 821 | // first serdes macro: rx ports 0-3, tx ports 0-3 |
| 822 | |
| 823 | |
| 824 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[14] |
| 825 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 826 | |
| 827 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[15] |
| 828 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 829 | |
| 830 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[16] |
| 831 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 832 | |
| 833 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[17] |
| 834 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 835 | |
| 836 | |
| 837 | // Now for TX first 4 ports (INVPAIR) |
| 838 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[38] |
| 839 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 840 | |
| 841 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[39] |
| 842 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 843 | |
| 844 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[40] |
| 845 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 846 | |
| 847 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[41] |
| 848 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 849 | |
| 850 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 851 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[18] |
| 852 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 853 | |
| 854 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[19] |
| 855 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 856 | |
| 857 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[20] |
| 858 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 859 | |
| 860 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[21] |
| 861 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 862 | |
| 863 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx4[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[22] |
| 864 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 865 | |
| 866 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx5[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[23] |
| 867 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 868 | |
| 869 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[42] |
| 870 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 871 | |
| 872 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[43] |
| 873 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 874 | |
| 875 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 876 | |
| 877 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[24] |
| 878 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 879 | |
| 880 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[25] |
| 881 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 882 | |
| 883 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[26] |
| 884 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 885 | |
| 886 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[27] |
| 887 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 888 | |
| 889 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[44] |
| 890 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 891 | |
| 892 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[45] |
| 893 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 894 | |
| 895 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[46] |
| 896 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 897 | |
| 898 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[7] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_invert[47] |
| 899 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 900 | |
| 901 | // MCU 1 ******* |
| 902 | |
| 903 | // Now for MCU1: FRS2: Lets do RX first 4 ports (INVPAIR) |
| 904 | |
| 905 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[0] |
| 906 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 907 | |
| 908 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[1] |
| 909 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 910 | |
| 911 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[2] |
| 912 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 913 | |
| 914 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[3] |
| 915 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 916 | |
| 917 | |
| 918 | // Now for TX first 4 ports (INVPAIR) |
| 919 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[28] |
| 920 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 921 | |
| 922 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[29] |
| 923 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 924 | |
| 925 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[30] |
| 926 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 927 | |
| 928 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[31] |
| 929 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 930 | |
| 931 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 932 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[4] |
| 933 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 934 | |
| 935 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[5] |
| 936 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 937 | |
| 938 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[6] |
| 939 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 940 | |
| 941 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[7] |
| 942 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 943 | |
| 944 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx4[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[8] |
| 945 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 946 | |
| 947 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx5[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[9] |
| 948 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 949 | |
| 950 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[32] |
| 951 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 952 | |
| 953 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[33] |
| 954 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 955 | |
| 956 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 957 | |
| 958 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[10] |
| 959 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 960 | |
| 961 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[11] |
| 962 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 963 | |
| 964 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[12] |
| 965 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 966 | |
| 967 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[13] |
| 968 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 969 | |
| 970 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[34] |
| 971 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 972 | |
| 973 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[35] |
| 974 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 975 | |
| 976 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[36] |
| 977 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 978 | |
| 979 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[37] |
| 980 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 981 | |
| 982 | // Now for FSR3 |
| 983 | // first serdes macro: rx ports 0-3, tx ports 0-3 |
| 984 | |
| 985 | |
| 986 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[14] |
| 987 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 988 | |
| 989 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[15] |
| 990 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 991 | |
| 992 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[16] |
| 993 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 994 | |
| 995 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[17] |
| 996 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 997 | |
| 998 | |
| 999 | // Now for TX first 4 ports (INVPAIR) |
| 1000 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[38] |
| 1001 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1002 | |
| 1003 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[39] |
| 1004 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1005 | |
| 1006 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[40] |
| 1007 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1008 | |
| 1009 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[41] |
| 1010 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1011 | |
| 1012 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 1013 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[18] |
| 1014 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1015 | |
| 1016 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[19] |
| 1017 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1018 | |
| 1019 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[20] |
| 1020 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1021 | |
| 1022 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[21] |
| 1023 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1024 | |
| 1025 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx4[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[22] |
| 1026 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1027 | |
| 1028 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx5[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[23] |
| 1029 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1030 | |
| 1031 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[42] |
| 1032 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1033 | |
| 1034 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[43] |
| 1035 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1036 | |
| 1037 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 1038 | |
| 1039 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[24] |
| 1040 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1041 | |
| 1042 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[25] |
| 1043 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1044 | |
| 1045 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[26] |
| 1046 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1047 | |
| 1048 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[27] |
| 1049 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1050 | |
| 1051 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[44] |
| 1052 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1053 | |
| 1054 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[45] |
| 1055 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1056 | |
| 1057 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[46] |
| 1058 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1059 | |
| 1060 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[7] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_invert[47] |
| 1061 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1062 | |
| 1063 | |
| 1064 | // MCU 2 ******* |
| 1065 | |
| 1066 | // Now for MCU2: FRS4: Lets do RX first 4 ports (INVPAIR) |
| 1067 | |
| 1068 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[0] |
| 1069 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1070 | |
| 1071 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[1] |
| 1072 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1073 | |
| 1074 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[2] |
| 1075 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1076 | |
| 1077 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[3] |
| 1078 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1079 | |
| 1080 | |
| 1081 | // Now for TX first 4 ports (INVPAIR) |
| 1082 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[28] |
| 1083 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1084 | |
| 1085 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[29] |
| 1086 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1087 | |
| 1088 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[30] |
| 1089 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1090 | |
| 1091 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[31] |
| 1092 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1093 | |
| 1094 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 1095 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[4] |
| 1096 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1097 | |
| 1098 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[5] |
| 1099 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1100 | |
| 1101 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[6] |
| 1102 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1103 | |
| 1104 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[7] |
| 1105 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1106 | |
| 1107 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx4[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[8] |
| 1108 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1109 | |
| 1110 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx5[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[9] |
| 1111 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1112 | |
| 1113 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[32] |
| 1114 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1115 | |
| 1116 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[33] |
| 1117 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1118 | |
| 1119 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 1120 | |
| 1121 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[10] |
| 1122 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1123 | |
| 1124 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[11] |
| 1125 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1126 | |
| 1127 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[12] |
| 1128 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1129 | |
| 1130 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[13] |
| 1131 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1132 | |
| 1133 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[34] |
| 1134 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1135 | |
| 1136 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[35] |
| 1137 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1138 | |
| 1139 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[36] |
| 1140 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1141 | |
| 1142 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[37] |
| 1143 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1144 | |
| 1145 | // Now for FSR5 |
| 1146 | // first serdes macro: rx ports 0-3, tx ports 0-3 |
| 1147 | |
| 1148 | |
| 1149 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[14] |
| 1150 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1151 | |
| 1152 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[15] |
| 1153 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1154 | |
| 1155 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[16] |
| 1156 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1157 | |
| 1158 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[17] |
| 1159 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1160 | |
| 1161 | |
| 1162 | // Now for TX first 4 ports (INVPAIR) |
| 1163 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[38] |
| 1164 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1165 | |
| 1166 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[39] |
| 1167 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1168 | |
| 1169 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[40] |
| 1170 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1171 | |
| 1172 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[41] |
| 1173 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1174 | |
| 1175 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 1176 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[18] |
| 1177 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1178 | |
| 1179 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[19] |
| 1180 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1181 | |
| 1182 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[20] |
| 1183 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1184 | |
| 1185 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[21] |
| 1186 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1187 | |
| 1188 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx4[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[22] |
| 1189 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1190 | |
| 1191 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx5[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[23] |
| 1192 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1193 | |
| 1194 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[42] |
| 1195 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1196 | |
| 1197 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[43] |
| 1198 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1199 | |
| 1200 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 1201 | |
| 1202 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[24] |
| 1203 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1204 | |
| 1205 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[25] |
| 1206 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1207 | |
| 1208 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[26] |
| 1209 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1210 | |
| 1211 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[27] |
| 1212 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1213 | |
| 1214 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[44] |
| 1215 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1216 | |
| 1217 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[45] |
| 1218 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1219 | |
| 1220 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[46] |
| 1221 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1222 | |
| 1223 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[7] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_invert[47] |
| 1224 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1225 | |
| 1226 | |
| 1227 | // MCU 3 ******* |
| 1228 | |
| 1229 | // Now for MCU3: FRS2: Lets do RX first 4 ports (INVPAIR) |
| 1230 | |
| 1231 | // FSR6 |
| 1232 | |
| 1233 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[0] |
| 1234 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1235 | |
| 1236 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[1] |
| 1237 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1238 | |
| 1239 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[2] |
| 1240 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1241 | |
| 1242 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[3] |
| 1243 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1244 | |
| 1245 | |
| 1246 | // Now for TX first 4 ports (INVPAIR) |
| 1247 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[28] |
| 1248 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1249 | |
| 1250 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[29] |
| 1251 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1252 | |
| 1253 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[30] |
| 1254 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1255 | |
| 1256 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[31] |
| 1257 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1258 | |
| 1259 | |
| 1260 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 1261 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[4] |
| 1262 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1263 | |
| 1264 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[5] |
| 1265 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1266 | |
| 1267 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[6] |
| 1268 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1269 | |
| 1270 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[7] |
| 1271 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1272 | |
| 1273 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx4[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[8] |
| 1274 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1275 | |
| 1276 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx5[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[9] |
| 1277 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1278 | |
| 1279 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[32] |
| 1280 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1281 | |
| 1282 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[33] |
| 1283 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1284 | |
| 1285 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 1286 | |
| 1287 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[10] |
| 1288 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1289 | |
| 1290 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[11] |
| 1291 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1292 | |
| 1293 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[12] |
| 1294 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1295 | |
| 1296 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[13] |
| 1297 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1298 | |
| 1299 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[34] |
| 1300 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1301 | |
| 1302 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[35] |
| 1303 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1304 | |
| 1305 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[36] |
| 1306 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1307 | |
| 1308 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[37] |
| 1309 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1310 | |
| 1311 | |
| 1312 | // Now for FSR7 |
| 1313 | // first serdes macro: rx ports 0-3, tx ports 0-3 |
| 1314 | |
| 1315 | |
| 1316 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[14] |
| 1317 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1318 | |
| 1319 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[15] |
| 1320 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1321 | |
| 1322 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[16] |
| 1323 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1324 | |
| 1325 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[17] |
| 1326 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1327 | |
| 1328 | |
| 1329 | // Now for TX first 4 ports (INVPAIR) |
| 1330 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[38] |
| 1331 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1332 | |
| 1333 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[39] |
| 1334 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1335 | |
| 1336 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[40] |
| 1337 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1338 | |
| 1339 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[41] |
| 1340 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1341 | |
| 1342 | |
| 1343 | // second serdes macro: RX ports 4-9, TX ports 4-5 (INVPAIR) |
| 1344 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[18] |
| 1345 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1346 | |
| 1347 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[19] |
| 1348 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1349 | |
| 1350 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[20] |
| 1351 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1352 | |
| 1353 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[21] |
| 1354 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1355 | |
| 1356 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx4[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[22] |
| 1357 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1358 | |
| 1359 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx5[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[23] |
| 1360 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1361 | |
| 1362 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[42] |
| 1363 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1364 | |
| 1365 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[43] |
| 1366 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1367 | |
| 1368 | |
| 1369 | // Now third serdes macro: RX ports 10-13, TX ports 6-9 |
| 1370 | |
| 1371 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[24] |
| 1372 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1373 | |
| 1374 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[25] |
| 1375 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1376 | |
| 1377 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[26] |
| 1378 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1379 | |
| 1380 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[27] |
| 1381 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1382 | |
| 1383 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[44] |
| 1384 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1385 | |
| 1386 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[45] |
| 1387 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1388 | |
| 1389 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[46] |
| 1390 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1391 | |
| 1392 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[7] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_invert[47] |
| 1393 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1394 | |
| 1395 | |
| 1396 | // Serdes Test Config Register |
| 1397 | |
| 1398 | // MCU0 FSR0 |
| 1399 | |
| 1400 | |
| 1401 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.testcfg[10:0] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1402 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1403 | |
| 1404 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.testcfg[14:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1405 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1406 | |
| 1407 | /* 0in value -var `CPU.fsr_left.fsr0_a8.testcfg[10:0] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1408 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1409 | |
| 1410 | /* 0in value -var `CPU.fsr_left.fsr0_a8.testcfg[14:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1411 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1412 | |
| 1413 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.testcfg[10:0] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1414 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1415 | |
| 1416 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.testcfg[14:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1417 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1418 | |
| 1419 | // MCU0 FSR1 |
| 1420 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.testcfg[10:0] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1421 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1422 | |
| 1423 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.testcfg[14:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1424 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1425 | |
| 1426 | /* 0in value -var `CPU.fsr_left.fsr1_a8.testcfg[10:0] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1427 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1428 | |
| 1429 | /* 0in value -var `CPU.fsr_left.fsr1_a8.testcfg[14:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1430 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1431 | |
| 1432 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.testcfg[10:0] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1433 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1434 | |
| 1435 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.testcfg[14:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1436 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1437 | |
| 1438 | |
| 1439 | // MCU1 FSR2 |
| 1440 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.testcfg[10:0] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1441 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1442 | |
| 1443 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.testcfg[14:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1444 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1445 | |
| 1446 | /* 0in value -var `CPU.fsr_left.fsr2_a8.testcfg[10:0] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1447 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1448 | |
| 1449 | /* 0in value -var `CPU.fsr_left.fsr2_a8.testcfg[14:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1450 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1451 | |
| 1452 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.testcfg[10:0] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1453 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1454 | |
| 1455 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.testcfg[14:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1456 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1457 | |
| 1458 | // MCU1 FSR3 |
| 1459 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.testcfg[10:0] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1460 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1461 | |
| 1462 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.testcfg[14:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1463 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1464 | |
| 1465 | /* 0in value -var `CPU.fsr_left.fsr3_a8.testcfg[10:0] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1466 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1467 | |
| 1468 | /* 0in value -var `CPU.fsr_left.fsr3_a8.testcfg[14:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1469 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1470 | |
| 1471 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.testcfg[10:0] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1472 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1473 | |
| 1474 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.testcfg[14:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1475 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 1476 | |
| 1477 | |
| 1478 | // MCU2 FSR4 |
| 1479 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.testcfg[10:0] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1480 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1481 | |
| 1482 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.testcfg[14:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1483 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1484 | |
| 1485 | /* 0in value -var `CPU.fsr_right.fsr4_a8.testcfg[10:0] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1486 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1487 | |
| 1488 | /* 0in value -var `CPU.fsr_right.fsr4_a8.testcfg[14:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1489 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1490 | |
| 1491 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.testcfg[10:0] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[10:0] |
| 1492 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1493 | |
| 1494 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.testcfg[14:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[13:11] |
| 1495 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1496 | |
| 1497 | // MCU2 FSR5 |
| 1498 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.testcfg[10:0] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1499 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1500 | |
| 1501 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.testcfg[14:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1502 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1503 | |
| 1504 | /* 0in value -var `CPU.fsr_right.fsr5_a8.testcfg[10:0] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1505 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1506 | |
| 1507 | /* 0in value -var `CPU.fsr_right.fsr5_a8.testcfg[14:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1508 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1509 | |
| 1510 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.testcfg[10:0] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1511 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1512 | |
| 1513 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.testcfg[14:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1514 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 1515 | |
| 1516 | // MCU3 FSR6 |
| 1517 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.testcfg[10:0] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1518 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1519 | |
| 1520 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.testcfg[14:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1521 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1522 | |
| 1523 | /* 0in value -var `CPU.fsr_right.fsr6_a8.testcfg[10:0] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1524 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1525 | |
| 1526 | /* 0in value -var `CPU.fsr_right.fsr6_a8.testcfg[14:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1527 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1528 | |
| 1529 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.testcfg[10:0] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1530 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1531 | |
| 1532 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.testcfg[14:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1533 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1534 | |
| 1535 | // MCU3 FSR7 |
| 1536 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.testcfg[10:0] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1537 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1538 | |
| 1539 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.testcfg[14:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1540 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1541 | |
| 1542 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.testcfg[10:0] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1543 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1544 | |
| 1545 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.testcfg[14:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1546 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1547 | |
| 1548 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.testcfg[10:0] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[24:14] |
| 1549 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1550 | |
| 1551 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.testcfg[14:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[27:25] |
| 1552 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 1553 | |
| 1554 | // hunter |
| 1555 | |
| 1556 | // Mcu SERDES Configuration Bus [29:0] |
| 1557 | |
| 1558 | // MCU0 FSR0 SERDES 0 PLL |
| 1559 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgpll[9:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 1560 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1561 | |
| 1562 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgpll[4:1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 1563 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1564 | |
| 1565 | // MCU0 FSR0 SERDES 0 Lane 0 RX |
| 1566 | |
| 1567 | |
| 1568 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx0[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1569 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1570 | |
| 1571 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx0[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1572 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1573 | |
| 1574 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx0[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1575 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1576 | |
| 1577 | // MCU0 FSR0 SERDES 0 Lane 0 TX |
| 1578 | |
| 1579 | |
| 1580 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1581 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1582 | |
| 1583 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1584 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1585 | |
| 1586 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1587 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1588 | |
| 1589 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1590 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1591 | |
| 1592 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1593 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1594 | |
| 1595 | |
| 1596 | // MCU0 FSR0 SERDES 0 Lane 1 RX |
| 1597 | |
| 1598 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx1[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1599 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1600 | |
| 1601 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx1[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1602 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1603 | |
| 1604 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx1[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1605 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1606 | |
| 1607 | // MCU0 FSR0 SERDES 0 Lane 0 TX |
| 1608 | |
| 1609 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1610 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1611 | |
| 1612 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1613 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1614 | |
| 1615 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1616 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1617 | |
| 1618 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1619 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1620 | |
| 1621 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1622 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1623 | |
| 1624 | |
| 1625 | // MCU0 FSR0 SERDES 0 Lane 2 RX |
| 1626 | |
| 1627 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx2[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1628 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1629 | |
| 1630 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx2[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1631 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1632 | |
| 1633 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx2[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1634 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1635 | |
| 1636 | // MCU0 FSR0 SERDES 0 Lane 2 TX |
| 1637 | |
| 1638 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1639 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1640 | |
| 1641 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1642 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1643 | |
| 1644 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1645 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1646 | |
| 1647 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1648 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1649 | |
| 1650 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1651 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1652 | |
| 1653 | // MCU0 FSR0 SERDES 0 Lane 3 RX |
| 1654 | |
| 1655 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx3[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1656 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1657 | |
| 1658 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx3[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1659 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1660 | |
| 1661 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx3[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1662 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1663 | |
| 1664 | // MCU0 FSR0 SERDES 0 Lane 3 TX |
| 1665 | |
| 1666 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1667 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1668 | |
| 1669 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1670 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1671 | |
| 1672 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1673 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1674 | |
| 1675 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1676 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1677 | |
| 1678 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1679 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1680 | |
| 1681 | // MCU0 FSR0 SERDES 1 PLL |
| 1682 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgpll[9:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 1683 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1684 | |
| 1685 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgpll[4:1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 1686 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1687 | |
| 1688 | // MCU0 FSR0 SERDES 1 Lane 0 RX |
| 1689 | |
| 1690 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx0[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1691 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1692 | |
| 1693 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx0[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1694 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1695 | |
| 1696 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx0[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1697 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1698 | |
| 1699 | // MCU0 FSR0 SERDES 1 Lane 1 RX |
| 1700 | |
| 1701 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx1[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1702 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1703 | |
| 1704 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx1[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1705 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1706 | |
| 1707 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx1[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1708 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1709 | |
| 1710 | // MCU0 FSR0 SERDES 1 Lane 2 RX |
| 1711 | |
| 1712 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx2[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1713 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1714 | |
| 1715 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx2[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1716 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1717 | |
| 1718 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx2[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1719 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1720 | |
| 1721 | // MCU0 FSR0 SERDES 1 Lane 3 RX |
| 1722 | |
| 1723 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx3[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1724 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1725 | |
| 1726 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx3[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1727 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1728 | |
| 1729 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx3[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1730 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1731 | |
| 1732 | // MCU0 FSR0 SERDES 1 Lane 4 RX |
| 1733 | |
| 1734 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx4[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1735 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1736 | |
| 1737 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx4[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1738 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1739 | |
| 1740 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx4[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1741 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1742 | |
| 1743 | // MCU0 FSR0 SERDES 1 Lane 5 RX |
| 1744 | |
| 1745 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx5[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1746 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1747 | |
| 1748 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx5[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1749 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1750 | |
| 1751 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx5[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1752 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1753 | |
| 1754 | // MCU0 FSR0 SERDES 1 Lane 0 TX |
| 1755 | |
| 1756 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1757 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1758 | |
| 1759 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1760 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1761 | |
| 1762 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1763 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1764 | |
| 1765 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1766 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1767 | |
| 1768 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1769 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1770 | |
| 1771 | |
| 1772 | // MCU0 FSR0 SERDES 1 Lane 1 TX |
| 1773 | |
| 1774 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1775 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1776 | |
| 1777 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1778 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1779 | |
| 1780 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1781 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1782 | |
| 1783 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1784 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1785 | |
| 1786 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1787 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1788 | |
| 1789 | // MCU0 FSR0 SERDES 2 PLL |
| 1790 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgpll[9:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 1791 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1792 | |
| 1793 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgpll[4:1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 1794 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1795 | |
| 1796 | // MCU0 FSR0 SERDES 2 Lane 0 RX |
| 1797 | |
| 1798 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx0[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1799 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1800 | |
| 1801 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx0[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1802 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1803 | |
| 1804 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx0[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1805 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1806 | |
| 1807 | // MCU0 FSR0 SERDES 2 Lane 0 TX |
| 1808 | |
| 1809 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1810 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1811 | |
| 1812 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1813 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1814 | |
| 1815 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1816 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1817 | |
| 1818 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1819 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1820 | |
| 1821 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1822 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1823 | |
| 1824 | |
| 1825 | // MCU0 FSR0 SERDES 2 Lane 1 RX |
| 1826 | |
| 1827 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx1[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1828 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1829 | |
| 1830 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx1[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1831 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1832 | |
| 1833 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx1[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1834 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1835 | |
| 1836 | // MCU0 FSR0 SERDES 2 Lane 1 TX |
| 1837 | |
| 1838 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1839 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1840 | |
| 1841 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1842 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1843 | |
| 1844 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1845 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1846 | |
| 1847 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1848 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1849 | |
| 1850 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1851 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1852 | |
| 1853 | |
| 1854 | // MCU0 FSR0 SERDES 2 Lane 2 RX |
| 1855 | |
| 1856 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx2[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1857 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1858 | |
| 1859 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx2[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1860 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1861 | |
| 1862 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx2[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1863 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1864 | |
| 1865 | // MCU0 FSR0 SERDES 2 Lane 2 TX |
| 1866 | |
| 1867 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1868 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1869 | |
| 1870 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1871 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1872 | |
| 1873 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1874 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1875 | |
| 1876 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1877 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1878 | |
| 1879 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1880 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1881 | |
| 1882 | // MCU0 FSR0 SERDES 2 Lane 3 RX |
| 1883 | |
| 1884 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx3[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1885 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1886 | |
| 1887 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx3[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1888 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1889 | |
| 1890 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx3[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1891 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1892 | |
| 1893 | // MCU0 FSR0 SERDES 2 Lane 3 TX |
| 1894 | |
| 1895 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1896 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1897 | |
| 1898 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1899 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1900 | |
| 1901 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1902 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1903 | |
| 1904 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1905 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1906 | |
| 1907 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1908 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1909 | |
| 1910 | |
| 1911 | // MCU0 FSR1 SERDES 0 PLL |
| 1912 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgpll[9:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 1913 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1914 | |
| 1915 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgpll[4:1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 1916 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1917 | |
| 1918 | // MCU0 FSR1 SERDES 0 Lane 0 RX |
| 1919 | |
| 1920 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx0[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1921 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1922 | |
| 1923 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx0[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1924 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1925 | |
| 1926 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx0[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1927 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1928 | |
| 1929 | // MCU0 FSR1 SERDES 0 Lane 0 TX |
| 1930 | |
| 1931 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1932 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1933 | |
| 1934 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1935 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1936 | |
| 1937 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1938 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1939 | |
| 1940 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1941 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1942 | |
| 1943 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1944 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1945 | |
| 1946 | |
| 1947 | // MCU0 FSR1 SERDES 0 Lane 1 RX |
| 1948 | |
| 1949 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx1[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1950 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1951 | |
| 1952 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx1[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1953 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1954 | |
| 1955 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx1[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1956 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1957 | |
| 1958 | // MCU0 FSR1 SERDES 0 Lane 0 TX |
| 1959 | |
| 1960 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1961 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1962 | |
| 1963 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1964 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1965 | |
| 1966 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1967 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1968 | |
| 1969 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1970 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1971 | |
| 1972 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 1973 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1974 | |
| 1975 | |
| 1976 | // MCU0 FSR1 SERDES 0 Lane 2 RX |
| 1977 | |
| 1978 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx2[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 1979 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1980 | |
| 1981 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx2[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 1982 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1983 | |
| 1984 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx2[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 1985 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1986 | |
| 1987 | // MCU0 FSR1 SERDES 0 Lane 2 TX |
| 1988 | |
| 1989 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 1990 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1991 | |
| 1992 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 1993 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1994 | |
| 1995 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 1996 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 1997 | |
| 1998 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 1999 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2000 | |
| 2001 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2002 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2003 | |
| 2004 | // MCU0 FSR1 SERDES 0 Lane 3 RX |
| 2005 | |
| 2006 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx3[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2007 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2008 | |
| 2009 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx3[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2010 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2011 | |
| 2012 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx3[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2013 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2014 | |
| 2015 | // MCU0 FSR1 SERDES 0 Lane 3 TX |
| 2016 | |
| 2017 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2018 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2019 | |
| 2020 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2021 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2022 | |
| 2023 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2024 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2025 | |
| 2026 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2027 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2028 | |
| 2029 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2030 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2031 | |
| 2032 | // MCU0 FSR1 SERDES 1 PLL |
| 2033 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgpll[9:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2034 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2035 | |
| 2036 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgpll[4:1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2037 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2038 | |
| 2039 | // MCU0 FSR1 SERDES 1 Lane 0 RX |
| 2040 | |
| 2041 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx0[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2042 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2043 | |
| 2044 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx0[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2045 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2046 | |
| 2047 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx0[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2048 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2049 | |
| 2050 | // MCU0 FSR1 SERDES 1 Lane 1 RX |
| 2051 | |
| 2052 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx1[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2053 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2054 | |
| 2055 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx1[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2056 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2057 | |
| 2058 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx1[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2059 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2060 | |
| 2061 | // MCU0 FSR1 SERDES 1 Lane 2 RX |
| 2062 | |
| 2063 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx2[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2064 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2065 | |
| 2066 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx2[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2067 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2068 | |
| 2069 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx2[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2070 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2071 | |
| 2072 | // MCU0 FSR1 SERDES 1 Lane 3 RX |
| 2073 | |
| 2074 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx3[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2075 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2076 | |
| 2077 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx3[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2078 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2079 | |
| 2080 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx3[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2081 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2082 | |
| 2083 | // MCU0 FSR1 SERDES 1 Lane 4 RX |
| 2084 | |
| 2085 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx4[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2086 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2087 | |
| 2088 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx4[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2089 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2090 | |
| 2091 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx4[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2092 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2093 | |
| 2094 | // MCU0 FSR1 SERDES 1 Lane 5 RX |
| 2095 | |
| 2096 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx5[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2097 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2098 | |
| 2099 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx5[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2100 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2101 | |
| 2102 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx5[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2103 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2104 | |
| 2105 | // MCU0 FSR1 SERDES 1 Lane 0 TX |
| 2106 | |
| 2107 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2108 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2109 | |
| 2110 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2111 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2112 | |
| 2113 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2114 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2115 | |
| 2116 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2117 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2118 | |
| 2119 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2120 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2121 | |
| 2122 | |
| 2123 | // MCU0 FSR1 SERDES 1 Lane 1 TX |
| 2124 | |
| 2125 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2126 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2127 | |
| 2128 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2129 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2130 | |
| 2131 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2132 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2133 | |
| 2134 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2135 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2136 | |
| 2137 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2138 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2139 | |
| 2140 | // MCU0 FSR1 SERDES 2 PLL |
| 2141 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgpll[9:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2142 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2143 | |
| 2144 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgpll[4:1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2145 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2146 | |
| 2147 | // MCU0 FSR1 SERDES 2 Lane 0 RX |
| 2148 | |
| 2149 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx0[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2150 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2151 | |
| 2152 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx0[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2153 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2154 | |
| 2155 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx0[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2156 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2157 | |
| 2158 | // MCU0 FSR1 SERDES 2 Lane 0 TX |
| 2159 | |
| 2160 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2161 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2162 | |
| 2163 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2164 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2165 | |
| 2166 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2167 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2168 | |
| 2169 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2170 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2171 | |
| 2172 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2173 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2174 | |
| 2175 | |
| 2176 | // MCU0 FSR1 SERDES 2 Lane 1 RX |
| 2177 | |
| 2178 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx1[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2179 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2180 | |
| 2181 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx1[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2182 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2183 | |
| 2184 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx1[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2185 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2186 | |
| 2187 | // MCU0 FSR1 SERDES 2 Lane 1 TX |
| 2188 | |
| 2189 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2190 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2191 | |
| 2192 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2193 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2194 | |
| 2195 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2196 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2197 | |
| 2198 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2199 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2200 | |
| 2201 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2202 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2203 | |
| 2204 | |
| 2205 | // MCU0 FSR1 SERDES 2 Lane 2 RX |
| 2206 | |
| 2207 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx2[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2208 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2209 | |
| 2210 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx2[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2211 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2212 | |
| 2213 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx2[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2214 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2215 | |
| 2216 | // MCU0 FSR1 SERDES 2 Lane 2 TX |
| 2217 | |
| 2218 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2219 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2220 | |
| 2221 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2222 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2223 | |
| 2224 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2225 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2226 | |
| 2227 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2228 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2229 | |
| 2230 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2231 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2232 | |
| 2233 | // MCU0 FSR1 SERDES 2 Lane 3 RX |
| 2234 | |
| 2235 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx3[22:19] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2236 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2237 | |
| 2238 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx3[18:16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2239 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2240 | |
| 2241 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx3[10:8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2242 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2243 | |
| 2244 | // MCU0 FSR1 SERDES 2 Lane 3 TX |
| 2245 | |
| 2246 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[16] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[19] |
| 2247 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2248 | |
| 2249 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[15:12] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2250 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2251 | |
| 2252 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[11:9] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2253 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2254 | |
| 2255 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[8] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[27] |
| 2256 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2257 | |
| 2258 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[6:5] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2259 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 2260 | |
| 2261 | // MCU1 FSR2 SERDES 0 PLL |
| 2262 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgpll[9:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2263 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2264 | |
| 2265 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgpll[4:1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2266 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2267 | |
| 2268 | // MCU1 FSR2 SERDES 0 Lane 0 RX |
| 2269 | |
| 2270 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx0[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2271 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2272 | |
| 2273 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx0[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2274 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2275 | |
| 2276 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx0[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2277 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2278 | |
| 2279 | // MCU1 FSR2 SERDES 0 Lane 0 TX |
| 2280 | |
| 2281 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2282 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2283 | |
| 2284 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2285 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2286 | |
| 2287 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2288 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2289 | |
| 2290 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2291 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2292 | |
| 2293 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2294 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2295 | |
| 2296 | |
| 2297 | // MCU1 FSR2 SERDES 0 Lane 1 RX |
| 2298 | |
| 2299 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx1[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2300 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2301 | |
| 2302 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx1[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2303 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2304 | |
| 2305 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx1[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2306 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2307 | |
| 2308 | // MCU1 FSR2 SERDES 0 Lane 0 TX |
| 2309 | |
| 2310 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2311 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2312 | |
| 2313 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2314 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2315 | |
| 2316 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2317 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2318 | |
| 2319 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2320 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2321 | |
| 2322 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2323 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2324 | |
| 2325 | |
| 2326 | // MCU1 FSR2 SERDES 0 Lane 2 RX |
| 2327 | |
| 2328 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx2[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2329 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2330 | |
| 2331 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx2[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2332 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2333 | |
| 2334 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx2[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2335 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2336 | |
| 2337 | // MCU1 FSR2 SERDES 0 Lane 2 TX |
| 2338 | |
| 2339 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2340 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2341 | |
| 2342 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2343 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2344 | |
| 2345 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2346 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2347 | |
| 2348 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2349 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2350 | |
| 2351 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2352 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2353 | |
| 2354 | // MCU1 FSR2 SERDES 0 Lane 3 RX |
| 2355 | |
| 2356 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx3[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2357 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2358 | |
| 2359 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx3[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2360 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2361 | |
| 2362 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx3[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2363 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2364 | |
| 2365 | // MCU1 FSR2 SERDES 0 Lane 3 TX |
| 2366 | |
| 2367 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2368 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2369 | |
| 2370 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2371 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2372 | |
| 2373 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2374 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2375 | |
| 2376 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2377 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2378 | |
| 2379 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2380 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2381 | |
| 2382 | // MCU1 FSR2 SERDES 1 PLL |
| 2383 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgpll[9:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2384 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2385 | |
| 2386 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgpll[4:1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2387 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2388 | |
| 2389 | // MCU1 FSR2 SERDES 1 Lane 0 RX |
| 2390 | |
| 2391 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx0[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2392 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2393 | |
| 2394 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx0[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2395 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2396 | |
| 2397 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx0[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2398 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2399 | |
| 2400 | // MCU1 FSR2 SERDES 1 Lane 1 RX |
| 2401 | |
| 2402 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx1[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2403 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2404 | |
| 2405 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx1[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2406 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2407 | |
| 2408 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx1[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2409 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2410 | |
| 2411 | // MCU1 FSR2 SERDES 1 Lane 2 RX |
| 2412 | |
| 2413 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx2[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2414 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2415 | |
| 2416 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx2[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2417 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2418 | |
| 2419 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx2[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2420 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2421 | |
| 2422 | // MCU1 FSR2 SERDES 1 Lane 3 RX |
| 2423 | |
| 2424 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx3[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2425 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2426 | |
| 2427 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx3[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2428 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2429 | |
| 2430 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx3[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2431 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2432 | |
| 2433 | // MCU1 FSR2 SERDES 1 Lane 4 RX |
| 2434 | |
| 2435 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx4[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2436 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2437 | |
| 2438 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx4[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2439 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2440 | |
| 2441 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx4[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2442 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2443 | |
| 2444 | // MCU1 FSR2 SERDES 1 Lane 5 RX |
| 2445 | |
| 2446 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx5[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2447 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2448 | |
| 2449 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx5[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2450 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2451 | |
| 2452 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx5[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2453 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2454 | |
| 2455 | // MCU1 FSR2 SERDES 1 Lane 0 TX |
| 2456 | |
| 2457 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2458 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2459 | |
| 2460 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2461 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2462 | |
| 2463 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2464 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2465 | |
| 2466 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2467 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2468 | |
| 2469 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2470 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2471 | |
| 2472 | |
| 2473 | // MCU1 FSR2 SERDES 1 Lane 1 TX |
| 2474 | |
| 2475 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2476 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2477 | |
| 2478 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2479 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2480 | |
| 2481 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2482 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2483 | |
| 2484 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2485 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2486 | |
| 2487 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2488 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2489 | |
| 2490 | // MCU1 FSR2 SERDES 2 PLL |
| 2491 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgpll[9:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2492 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2493 | |
| 2494 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgpll[4:1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2495 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2496 | |
| 2497 | // MCU1 FSR2 SERDES 2 Lane 0 RX |
| 2498 | |
| 2499 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx0[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2500 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2501 | |
| 2502 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx0[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2503 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2504 | |
| 2505 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx0[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2506 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2507 | |
| 2508 | // MCU1 FSR2 SERDES 2 Lane 0 TX |
| 2509 | |
| 2510 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2511 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2512 | |
| 2513 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2514 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2515 | |
| 2516 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2517 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2518 | |
| 2519 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2520 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2521 | |
| 2522 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2523 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2524 | |
| 2525 | |
| 2526 | // MCU1 FSR2 SERDES 2 Lane 1 RX |
| 2527 | |
| 2528 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx1[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2529 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2530 | |
| 2531 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx1[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2532 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2533 | |
| 2534 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx1[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2535 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2536 | |
| 2537 | // MCU1 FSR2 SERDES 2 Lane 1 TX |
| 2538 | |
| 2539 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2540 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2541 | |
| 2542 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2543 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2544 | |
| 2545 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2546 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2547 | |
| 2548 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2549 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2550 | |
| 2551 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2552 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2553 | |
| 2554 | |
| 2555 | // MCU1 FSR2 SERDES 2 Lane 2 RX |
| 2556 | |
| 2557 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx2[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2558 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2559 | |
| 2560 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx2[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2561 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2562 | |
| 2563 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx2[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2564 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2565 | |
| 2566 | // MCU1 FSR2 SERDES 2 Lane 2 TX |
| 2567 | |
| 2568 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2569 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2570 | |
| 2571 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2572 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2573 | |
| 2574 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2575 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2576 | |
| 2577 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2578 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2579 | |
| 2580 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2581 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2582 | |
| 2583 | // MCU1 FSR2 SERDES 2 Lane 3 RX |
| 2584 | |
| 2585 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx3[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2586 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2587 | |
| 2588 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx3[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2589 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2590 | |
| 2591 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx3[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2592 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2593 | |
| 2594 | // MCU1 FSR2 SERDES 2 Lane 3 TX |
| 2595 | |
| 2596 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2597 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2598 | |
| 2599 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2600 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2601 | |
| 2602 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2603 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2604 | |
| 2605 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2606 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2607 | |
| 2608 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2609 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2610 | |
| 2611 | |
| 2612 | // MCU1 FSR3 SERDES 0 PLL |
| 2613 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgpll[9:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2614 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2615 | |
| 2616 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgpll[4:1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2617 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2618 | |
| 2619 | // MCU1 FSR3 SERDES 0 Lane 0 RX |
| 2620 | |
| 2621 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx0[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2622 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2623 | |
| 2624 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx0[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2625 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2626 | |
| 2627 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx0[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2628 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2629 | |
| 2630 | // MCU1 FSR3 SERDES 0 Lane 0 TX |
| 2631 | |
| 2632 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2633 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2634 | |
| 2635 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2636 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2637 | |
| 2638 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2639 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2640 | |
| 2641 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2642 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2643 | |
| 2644 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2645 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2646 | |
| 2647 | |
| 2648 | // MCU1 FSR3 SERDES 0 Lane 1 RX |
| 2649 | |
| 2650 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx1[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2651 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2652 | |
| 2653 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx1[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2654 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2655 | |
| 2656 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx1[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2657 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2658 | |
| 2659 | // MCU1 FSR3 SERDES 0 Lane 0 TX |
| 2660 | |
| 2661 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2662 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2663 | |
| 2664 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2665 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2666 | |
| 2667 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2668 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2669 | |
| 2670 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2671 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2672 | |
| 2673 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2674 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2675 | |
| 2676 | |
| 2677 | // MCU1 FSR3 SERDES 0 Lane 2 RX |
| 2678 | |
| 2679 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx2[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2680 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2681 | |
| 2682 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx2[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2683 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2684 | |
| 2685 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx2[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2686 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2687 | |
| 2688 | // MCU1 FSR3 SERDES 0 Lane 2 TX |
| 2689 | |
| 2690 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2691 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2692 | |
| 2693 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2694 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2695 | |
| 2696 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2697 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2698 | |
| 2699 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2700 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2701 | |
| 2702 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2703 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2704 | |
| 2705 | // MCU1 FSR3 SERDES 0 Lane 3 RX |
| 2706 | |
| 2707 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx3[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2708 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2709 | |
| 2710 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx3[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2711 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2712 | |
| 2713 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx3[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2714 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2715 | |
| 2716 | // MCU1 FSR3 SERDES 0 Lane 3 TX |
| 2717 | |
| 2718 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2719 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2720 | |
| 2721 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2722 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2723 | |
| 2724 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2725 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2726 | |
| 2727 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2728 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2729 | |
| 2730 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2731 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2732 | |
| 2733 | // MCU1 FSR3 SERDES 1 PLL |
| 2734 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgpll[9:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2735 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2736 | |
| 2737 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgpll[4:1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2738 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2739 | |
| 2740 | // MCU1 FSR3 SERDES 1 Lane 0 RX |
| 2741 | |
| 2742 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx0[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2743 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2744 | |
| 2745 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx0[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2746 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2747 | |
| 2748 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx0[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2749 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2750 | |
| 2751 | // MCU1 FSR3 SERDES 1 Lane 1 RX |
| 2752 | |
| 2753 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx1[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2754 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2755 | |
| 2756 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx1[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2757 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2758 | |
| 2759 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx1[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2760 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2761 | |
| 2762 | // MCU1 FSR3 SERDES 1 Lane 2 RX |
| 2763 | |
| 2764 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx2[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2765 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2766 | |
| 2767 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx2[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2768 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2769 | |
| 2770 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx2[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2771 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2772 | |
| 2773 | // MCU1 FSR3 SERDES 1 Lane 3 RX |
| 2774 | |
| 2775 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx3[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2776 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2777 | |
| 2778 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx3[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2779 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2780 | |
| 2781 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx3[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2782 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2783 | |
| 2784 | // MCU1 FSR3 SERDES 1 Lane 4 RX |
| 2785 | |
| 2786 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx4[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2787 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2788 | |
| 2789 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx4[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2790 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2791 | |
| 2792 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx4[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2793 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2794 | |
| 2795 | // MCU1 FSR3 SERDES 1 Lane 5 RX |
| 2796 | |
| 2797 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx5[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2798 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2799 | |
| 2800 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx5[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2801 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2802 | |
| 2803 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx5[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2804 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2805 | |
| 2806 | // MCU1 FSR3 SERDES 1 Lane 0 TX |
| 2807 | |
| 2808 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2809 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2810 | |
| 2811 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2812 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2813 | |
| 2814 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2815 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2816 | |
| 2817 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2818 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2819 | |
| 2820 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2821 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2822 | |
| 2823 | |
| 2824 | // MCU1 FSR3 SERDES 1 Lane 1 TX |
| 2825 | |
| 2826 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2827 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2828 | |
| 2829 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2830 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2831 | |
| 2832 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2833 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2834 | |
| 2835 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2836 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2837 | |
| 2838 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2839 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2840 | |
| 2841 | // MCU1 FSR3 SERDES 2 PLL |
| 2842 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgpll[9:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2843 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2844 | |
| 2845 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgpll[4:1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2846 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2847 | |
| 2848 | // MCU1 FSR3 SERDES 2 Lane 0 RX |
| 2849 | |
| 2850 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx0[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2851 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2852 | |
| 2853 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx0[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2854 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2855 | |
| 2856 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx0[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2857 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2858 | |
| 2859 | // MCU1 FSR3 SERDES 2 Lane 0 TX |
| 2860 | |
| 2861 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2862 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2863 | |
| 2864 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2865 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2866 | |
| 2867 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2868 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2869 | |
| 2870 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2871 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2872 | |
| 2873 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2874 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2875 | |
| 2876 | |
| 2877 | // MCU1 FSR3 SERDES 2 Lane 1 RX |
| 2878 | |
| 2879 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx1[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2880 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2881 | |
| 2882 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx1[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2883 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2884 | |
| 2885 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx1[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2886 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2887 | |
| 2888 | // MCU1 FSR3 SERDES 2 Lane 1 TX |
| 2889 | |
| 2890 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2891 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2892 | |
| 2893 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2894 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2895 | |
| 2896 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2897 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2898 | |
| 2899 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2900 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2901 | |
| 2902 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2903 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2904 | |
| 2905 | |
| 2906 | // MCU1 FSR3 SERDES 2 Lane 2 RX |
| 2907 | |
| 2908 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx2[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2909 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2910 | |
| 2911 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx2[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2912 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2913 | |
| 2914 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx2[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2915 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2916 | |
| 2917 | // MCU1 FSR3 SERDES 2 Lane 2 TX |
| 2918 | |
| 2919 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2920 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2921 | |
| 2922 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2923 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2924 | |
| 2925 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2926 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2927 | |
| 2928 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2929 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2930 | |
| 2931 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2932 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2933 | |
| 2934 | // MCU1 FSR3 SERDES 2 Lane 3 RX |
| 2935 | |
| 2936 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx3[22:19] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2937 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2938 | |
| 2939 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx3[18:16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2940 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2941 | |
| 2942 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx3[10:8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2943 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2944 | |
| 2945 | // MCU1 FSR3 SERDES 2 Lane 3 TX |
| 2946 | |
| 2947 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[16] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[19] |
| 2948 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2949 | |
| 2950 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[15:12] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2951 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2952 | |
| 2953 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[11:9] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2954 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2955 | |
| 2956 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[8] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[27] |
| 2957 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2958 | |
| 2959 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[6:5] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2960 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 2961 | |
| 2962 | |
| 2963 | // MCU2 FSR4 SERDES 0 PLL |
| 2964 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgpll[9:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 2965 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2966 | |
| 2967 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgpll[4:1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 2968 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2969 | |
| 2970 | // MCU2 FSR4 SERDES 0 Lane 0 RX |
| 2971 | |
| 2972 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx0[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 2973 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2974 | |
| 2975 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx0[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 2976 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2977 | |
| 2978 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx0[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 2979 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2980 | |
| 2981 | // MCU2 FSR4 SERDES 0 Lane 0 TX |
| 2982 | |
| 2983 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 2984 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2985 | |
| 2986 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 2987 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2988 | |
| 2989 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 2990 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2991 | |
| 2992 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 2993 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2994 | |
| 2995 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 2996 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 2997 | |
| 2998 | |
| 2999 | // MCU2 FSR4 SERDES 0 Lane 1 RX |
| 3000 | |
| 3001 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx1[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3002 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3003 | |
| 3004 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx1[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3005 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3006 | |
| 3007 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx1[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3008 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3009 | |
| 3010 | // MCU2 FSR4 SERDES 0 Lane 0 TX |
| 3011 | |
| 3012 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3013 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3014 | |
| 3015 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3016 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3017 | |
| 3018 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3019 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3020 | |
| 3021 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3022 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3023 | |
| 3024 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3025 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3026 | |
| 3027 | |
| 3028 | // MCU2 FSR4 SERDES 0 Lane 2 RX |
| 3029 | |
| 3030 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx2[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3031 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3032 | |
| 3033 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx2[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3034 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3035 | |
| 3036 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx2[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3037 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3038 | |
| 3039 | // MCU2 FSR4 SERDES 0 Lane 2 TX |
| 3040 | |
| 3041 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3042 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3043 | |
| 3044 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3045 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3046 | |
| 3047 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3048 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3049 | |
| 3050 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3051 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3052 | |
| 3053 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3054 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3055 | |
| 3056 | // MCU2 FSR4 SERDES 0 Lane 3 RX |
| 3057 | |
| 3058 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx3[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3059 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3060 | |
| 3061 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx3[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3062 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3063 | |
| 3064 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx3[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3065 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3066 | |
| 3067 | // MCU2 FSR4 SERDES 0 Lane 3 TX |
| 3068 | |
| 3069 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3070 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3071 | |
| 3072 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3073 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3074 | |
| 3075 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3076 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3077 | |
| 3078 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3079 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3080 | |
| 3081 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3082 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3083 | |
| 3084 | // MCU2 FSR4 SERDES 1 PLL |
| 3085 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgpll[9:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3086 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3087 | |
| 3088 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgpll[4:1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3089 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3090 | |
| 3091 | // MCU2 FSR4 SERDES 1 Lane 0 RX |
| 3092 | |
| 3093 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx0[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3094 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3095 | |
| 3096 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx0[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3097 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3098 | |
| 3099 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx0[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3100 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3101 | |
| 3102 | // MCU2 FSR4 SERDES 1 Lane 1 RX |
| 3103 | |
| 3104 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx1[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3105 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3106 | |
| 3107 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx1[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3108 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3109 | |
| 3110 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx1[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3111 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3112 | |
| 3113 | // MCU2 FSR4 SERDES 1 Lane 2 RX |
| 3114 | |
| 3115 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx2[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3116 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3117 | |
| 3118 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx2[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3119 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3120 | |
| 3121 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx2[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3122 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3123 | |
| 3124 | // MCU2 FSR4 SERDES 1 Lane 3 RX |
| 3125 | |
| 3126 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx3[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3127 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3128 | |
| 3129 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx3[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3130 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3131 | |
| 3132 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx3[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3133 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3134 | |
| 3135 | // MCU2 FSR4 SERDES 1 Lane 4 RX |
| 3136 | |
| 3137 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx4[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3138 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3139 | |
| 3140 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx4[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3141 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3142 | |
| 3143 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx4[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3144 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3145 | |
| 3146 | // MCU2 FSR4 SERDES 1 Lane 5 RX |
| 3147 | |
| 3148 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx5[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3149 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3150 | |
| 3151 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx5[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3152 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3153 | |
| 3154 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx5[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3155 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3156 | |
| 3157 | // MCU2 FSR4 SERDES 1 Lane 0 TX |
| 3158 | |
| 3159 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3160 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3161 | |
| 3162 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3163 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3164 | |
| 3165 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3166 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3167 | |
| 3168 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3169 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3170 | |
| 3171 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3172 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3173 | |
| 3174 | |
| 3175 | // MCU2 FSR4 SERDES 1 Lane 1 TX |
| 3176 | |
| 3177 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3178 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3179 | |
| 3180 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3181 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3182 | |
| 3183 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3184 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3185 | |
| 3186 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3187 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3188 | |
| 3189 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3190 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3191 | |
| 3192 | // MCU2 FSR4 SERDES 2 PLL |
| 3193 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgpll[9:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3194 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3195 | |
| 3196 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgpll[4:1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3197 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3198 | |
| 3199 | // MCU2 FSR4 SERDES 2 Lane 0 RX |
| 3200 | |
| 3201 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx0[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3202 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3203 | |
| 3204 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx0[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3205 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3206 | |
| 3207 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx0[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3208 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3209 | |
| 3210 | // MCU2 FSR4 SERDES 2 Lane 0 TX |
| 3211 | |
| 3212 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3213 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3214 | |
| 3215 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3216 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3217 | |
| 3218 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3219 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3220 | |
| 3221 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3222 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3223 | |
| 3224 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3225 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3226 | |
| 3227 | |
| 3228 | // MCU2 FSR4 SERDES 2 Lane 1 RX |
| 3229 | |
| 3230 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx1[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3231 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3232 | |
| 3233 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx1[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3234 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3235 | |
| 3236 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx1[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3237 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3238 | |
| 3239 | // MCU2 FSR4 SERDES 2 Lane 1 TX |
| 3240 | |
| 3241 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3242 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3243 | |
| 3244 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3245 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3246 | |
| 3247 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3248 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3249 | |
| 3250 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3251 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3252 | |
| 3253 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3254 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3255 | |
| 3256 | |
| 3257 | // MCU2 FSR4 SERDES 2 Lane 2 RX |
| 3258 | |
| 3259 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx2[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3260 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3261 | |
| 3262 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx2[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3263 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3264 | |
| 3265 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx2[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3266 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3267 | |
| 3268 | // MCU2 FSR4 SERDES 2 Lane 2 TX |
| 3269 | |
| 3270 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3271 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3272 | |
| 3273 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3274 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3275 | |
| 3276 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3277 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3278 | |
| 3279 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3280 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3281 | |
| 3282 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3283 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3284 | |
| 3285 | // MCU2 FSR4 SERDES 2 Lane 3 RX |
| 3286 | |
| 3287 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx3[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3288 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3289 | |
| 3290 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx3[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3291 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3292 | |
| 3293 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx3[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3294 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3295 | |
| 3296 | // MCU2 FSR4 SERDES 2 Lane 3 TX |
| 3297 | |
| 3298 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3299 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3300 | |
| 3301 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3302 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3303 | |
| 3304 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3305 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3306 | |
| 3307 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3308 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3309 | |
| 3310 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3311 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3312 | |
| 3313 | |
| 3314 | // MCU2 FSR5 SERDES 0 PLL |
| 3315 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgpll[9:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3316 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3317 | |
| 3318 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgpll[4:1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3319 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3320 | |
| 3321 | // MCU2 FSR5 SERDES 0 Lane 0 RX |
| 3322 | |
| 3323 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx0[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3324 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3325 | |
| 3326 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx0[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3327 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3328 | |
| 3329 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx0[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3330 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3331 | |
| 3332 | // MCU2 FSR5 SERDES 0 Lane 0 TX |
| 3333 | |
| 3334 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3335 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3336 | |
| 3337 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3338 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3339 | |
| 3340 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3341 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3342 | |
| 3343 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3344 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3345 | |
| 3346 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3347 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3348 | |
| 3349 | |
| 3350 | // MCU2 FSR5 SERDES 0 Lane 1 RX |
| 3351 | |
| 3352 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx1[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3353 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3354 | |
| 3355 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx1[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3356 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3357 | |
| 3358 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx1[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3359 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3360 | |
| 3361 | // MCU2 FSR5 SERDES 0 Lane 0 TX |
| 3362 | |
| 3363 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3364 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3365 | |
| 3366 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3367 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3368 | |
| 3369 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3370 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3371 | |
| 3372 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3373 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3374 | |
| 3375 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3376 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3377 | |
| 3378 | |
| 3379 | // MCU2 FSR5 SERDES 0 Lane 2 RX |
| 3380 | |
| 3381 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx2[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3382 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3383 | |
| 3384 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx2[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3385 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3386 | |
| 3387 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx2[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3388 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3389 | |
| 3390 | // MCU2 FSR5 SERDES 0 Lane 2 TX |
| 3391 | |
| 3392 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3393 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3394 | |
| 3395 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3396 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3397 | |
| 3398 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3399 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3400 | |
| 3401 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3402 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3403 | |
| 3404 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3405 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3406 | |
| 3407 | // MCU2 FSR5 SERDES 0 Lane 3 RX |
| 3408 | |
| 3409 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx3[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3410 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3411 | |
| 3412 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx3[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3413 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3414 | |
| 3415 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx3[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3416 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3417 | |
| 3418 | // MCU2 FSR5 SERDES 0 Lane 3 TX |
| 3419 | |
| 3420 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3421 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3422 | |
| 3423 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3424 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3425 | |
| 3426 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3427 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3428 | |
| 3429 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3430 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3431 | |
| 3432 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3433 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3434 | |
| 3435 | // MCU2 FSR5 SERDES 1 PLL |
| 3436 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgpll[9:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3437 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3438 | |
| 3439 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgpll[4:1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3440 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3441 | |
| 3442 | // MCU2 FSR5 SERDES 1 Lane 0 RX |
| 3443 | |
| 3444 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx0[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3445 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3446 | |
| 3447 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx0[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3448 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3449 | |
| 3450 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx0[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3451 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3452 | |
| 3453 | // MCU2 FSR5 SERDES 1 Lane 1 RX |
| 3454 | |
| 3455 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx1[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3456 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3457 | |
| 3458 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx1[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3459 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3460 | |
| 3461 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx1[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3462 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3463 | |
| 3464 | // MCU2 FSR5 SERDES 1 Lane 2 RX |
| 3465 | |
| 3466 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx2[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3467 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3468 | |
| 3469 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx2[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3470 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3471 | |
| 3472 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx2[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3473 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3474 | |
| 3475 | // MCU2 FSR5 SERDES 1 Lane 3 RX |
| 3476 | |
| 3477 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx3[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3478 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3479 | |
| 3480 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx3[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3481 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3482 | |
| 3483 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx3[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3484 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3485 | |
| 3486 | // MCU2 FSR5 SERDES 1 Lane 4 RX |
| 3487 | |
| 3488 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx4[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3489 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3490 | |
| 3491 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx4[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3492 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3493 | |
| 3494 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx4[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3495 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3496 | |
| 3497 | // MCU2 FSR5 SERDES 1 Lane 5 RX |
| 3498 | |
| 3499 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx5[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3500 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3501 | |
| 3502 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx5[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3503 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3504 | |
| 3505 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx5[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3506 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3507 | |
| 3508 | // MCU2 FSR5 SERDES 1 Lane 0 TX |
| 3509 | |
| 3510 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3511 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3512 | |
| 3513 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3514 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3515 | |
| 3516 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3517 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3518 | |
| 3519 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3520 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3521 | |
| 3522 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3523 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3524 | |
| 3525 | |
| 3526 | // MCU2 FSR5 SERDES 1 Lane 1 TX |
| 3527 | |
| 3528 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3529 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3530 | |
| 3531 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3532 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3533 | |
| 3534 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3535 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3536 | |
| 3537 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3538 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3539 | |
| 3540 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3541 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3542 | |
| 3543 | // MCU2 FSR5 SERDES 2 PLL |
| 3544 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgpll[9:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3545 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3546 | |
| 3547 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgpll[4:1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3548 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3549 | |
| 3550 | // MCU2 FSR5 SERDES 2 Lane 0 RX |
| 3551 | |
| 3552 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx0[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3553 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3554 | |
| 3555 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx0[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3556 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3557 | |
| 3558 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx0[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3559 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3560 | |
| 3561 | // MCU2 FSR5 SERDES 2 Lane 0 TX |
| 3562 | |
| 3563 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3564 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3565 | |
| 3566 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3567 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3568 | |
| 3569 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3570 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3571 | |
| 3572 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3573 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3574 | |
| 3575 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3576 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3577 | |
| 3578 | |
| 3579 | // MCU2 FSR5 SERDES 2 Lane 1 RX |
| 3580 | |
| 3581 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx1[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3582 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3583 | |
| 3584 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx1[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3585 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3586 | |
| 3587 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx1[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3588 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3589 | |
| 3590 | // MCU2 FSR5 SERDES 2 Lane 1 TX |
| 3591 | |
| 3592 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3593 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3594 | |
| 3595 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3596 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3597 | |
| 3598 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3599 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3600 | |
| 3601 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3602 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3603 | |
| 3604 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3605 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3606 | |
| 3607 | |
| 3608 | // MCU2 FSR5 SERDES 2 Lane 2 RX |
| 3609 | |
| 3610 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx2[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3611 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3612 | |
| 3613 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx2[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3614 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3615 | |
| 3616 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx2[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3617 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3618 | |
| 3619 | // MCU2 FSR5 SERDES 2 Lane 2 TX |
| 3620 | |
| 3621 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3622 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3623 | |
| 3624 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3625 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3626 | |
| 3627 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3628 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3629 | |
| 3630 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3631 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3632 | |
| 3633 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3634 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3635 | |
| 3636 | // MCU2 FSR5 SERDES 2 Lane 3 RX |
| 3637 | |
| 3638 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx3[22:19] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3639 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3640 | |
| 3641 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx3[18:16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3642 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3643 | |
| 3644 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx3[10:8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3645 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3646 | |
| 3647 | // MCU2 FSR5 SERDES 2 Lane 3 TX |
| 3648 | |
| 3649 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[16] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[19] |
| 3650 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3651 | |
| 3652 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[15:12] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3653 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3654 | |
| 3655 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[11:9] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3656 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3657 | |
| 3658 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[8] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[27] |
| 3659 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3660 | |
| 3661 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[6:5] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3662 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 3663 | |
| 3664 | |
| 3665 | // MCU3 FSR6 SERDES 0 PLL |
| 3666 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgpll[9:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3667 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3668 | |
| 3669 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgpll[4:1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3670 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3671 | |
| 3672 | // MCU3 FSR6 SERDES 0 Lane 0 RX |
| 3673 | |
| 3674 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx0[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3675 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3676 | |
| 3677 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx0[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3678 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3679 | |
| 3680 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx0[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3681 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3682 | |
| 3683 | // MCU3 FSR6 SERDES 0 Lane 0 TX |
| 3684 | |
| 3685 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3686 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3687 | |
| 3688 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3689 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3690 | |
| 3691 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3692 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3693 | |
| 3694 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3695 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3696 | |
| 3697 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3698 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3699 | |
| 3700 | |
| 3701 | // MCU3 FSR6 SERDES 0 Lane 1 RX |
| 3702 | |
| 3703 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx1[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3704 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3705 | |
| 3706 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx1[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3707 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3708 | |
| 3709 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx1[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3710 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3711 | |
| 3712 | // MCU3 FSR6 SERDES 0 Lane 0 TX |
| 3713 | |
| 3714 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3715 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3716 | |
| 3717 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3718 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3719 | |
| 3720 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3721 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3722 | |
| 3723 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3724 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3725 | |
| 3726 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3727 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3728 | |
| 3729 | |
| 3730 | // MCU3 FSR6 SERDES 0 Lane 2 RX |
| 3731 | |
| 3732 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx2[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3733 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3734 | |
| 3735 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx2[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3736 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3737 | |
| 3738 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx2[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3739 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3740 | |
| 3741 | // MCU3 FSR6 SERDES 0 Lane 2 TX |
| 3742 | |
| 3743 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3744 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3745 | |
| 3746 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3747 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3748 | |
| 3749 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3750 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3751 | |
| 3752 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3753 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3754 | |
| 3755 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3756 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3757 | |
| 3758 | // MCU3 FSR6 SERDES 0 Lane 3 RX |
| 3759 | |
| 3760 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx3[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3761 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3762 | |
| 3763 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx3[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3764 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3765 | |
| 3766 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx3[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3767 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3768 | |
| 3769 | // MCU3 FSR6 SERDES 0 Lane 3 TX |
| 3770 | |
| 3771 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3772 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3773 | |
| 3774 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3775 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3776 | |
| 3777 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3778 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3779 | |
| 3780 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3781 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3782 | |
| 3783 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3784 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3785 | |
| 3786 | // MCU3 FSR6 SERDES 1 PLL |
| 3787 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgpll[9:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3788 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3789 | |
| 3790 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgpll[4:1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3791 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3792 | |
| 3793 | // MCU3 FSR6 SERDES 1 Lane 0 RX |
| 3794 | |
| 3795 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx0[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3796 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3797 | |
| 3798 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx0[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3799 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3800 | |
| 3801 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx0[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3802 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3803 | |
| 3804 | // MCU3 FSR6 SERDES 1 Lane 1 RX |
| 3805 | |
| 3806 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx1[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3807 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3808 | |
| 3809 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx1[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3810 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3811 | |
| 3812 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx1[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3813 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3814 | |
| 3815 | // MCU3 FSR6 SERDES 1 Lane 2 RX |
| 3816 | |
| 3817 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx2[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3818 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3819 | |
| 3820 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx2[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3821 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3822 | |
| 3823 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx2[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3824 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3825 | |
| 3826 | // MCU3 FSR6 SERDES 1 Lane 3 RX |
| 3827 | |
| 3828 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx3[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3829 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3830 | |
| 3831 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx3[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3832 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3833 | |
| 3834 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx3[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3835 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3836 | |
| 3837 | // MCU3 FSR6 SERDES 1 Lane 4 RX |
| 3838 | |
| 3839 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx4[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3840 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3841 | |
| 3842 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx4[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3843 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3844 | |
| 3845 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx4[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3846 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3847 | |
| 3848 | // MCU3 FSR6 SERDES 1 Lane 5 RX |
| 3849 | |
| 3850 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx5[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3851 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3852 | |
| 3853 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx5[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3854 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3855 | |
| 3856 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx5[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3857 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3858 | |
| 3859 | // MCU3 FSR6 SERDES 1 Lane 0 TX |
| 3860 | |
| 3861 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3862 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3863 | |
| 3864 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3865 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3866 | |
| 3867 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3868 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3869 | |
| 3870 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3871 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3872 | |
| 3873 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3874 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3875 | |
| 3876 | |
| 3877 | // MCU3 FSR6 SERDES 1 Lane 1 TX |
| 3878 | |
| 3879 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3880 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3881 | |
| 3882 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3883 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3884 | |
| 3885 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3886 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3887 | |
| 3888 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3889 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3890 | |
| 3891 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3892 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3893 | |
| 3894 | // MCU3 FSR6 SERDES 2 PLL |
| 3895 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgpll[9:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 3896 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3897 | |
| 3898 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgpll[4:1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 3899 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3900 | |
| 3901 | // MCU3 FSR6 SERDES 2 Lane 0 RX |
| 3902 | |
| 3903 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx0[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3904 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3905 | |
| 3906 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx0[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3907 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3908 | |
| 3909 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx0[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3910 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3911 | |
| 3912 | // MCU3 FSR6 SERDES 2 Lane 0 TX |
| 3913 | |
| 3914 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3915 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3916 | |
| 3917 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3918 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3919 | |
| 3920 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3921 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3922 | |
| 3923 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3924 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3925 | |
| 3926 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3927 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3928 | |
| 3929 | |
| 3930 | // MCU3 FSR6 SERDES 2 Lane 1 RX |
| 3931 | |
| 3932 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx1[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3933 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3934 | |
| 3935 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx1[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3936 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3937 | |
| 3938 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx1[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3939 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3940 | |
| 3941 | // MCU3 FSR6 SERDES 2 Lane 1 TX |
| 3942 | |
| 3943 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3944 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3945 | |
| 3946 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3947 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3948 | |
| 3949 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3950 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3951 | |
| 3952 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3953 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3954 | |
| 3955 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3956 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3957 | |
| 3958 | |
| 3959 | // MCU3 FSR6 SERDES 2 Lane 2 RX |
| 3960 | |
| 3961 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx2[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3962 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3963 | |
| 3964 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx2[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3965 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3966 | |
| 3967 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx2[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3968 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3969 | |
| 3970 | // MCU3 FSR6 SERDES 2 Lane 2 TX |
| 3971 | |
| 3972 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 3973 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3974 | |
| 3975 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 3976 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3977 | |
| 3978 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 3979 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3980 | |
| 3981 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 3982 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3983 | |
| 3984 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 3985 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3986 | |
| 3987 | // MCU3 FSR6 SERDES 2 Lane 3 RX |
| 3988 | |
| 3989 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx3[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 3990 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3991 | |
| 3992 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx3[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 3993 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3994 | |
| 3995 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx3[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 3996 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 3997 | |
| 3998 | // MCU3 FSR6 SERDES 2 Lane 3 TX |
| 3999 | |
| 4000 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4001 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4002 | |
| 4003 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4004 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4005 | |
| 4006 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4007 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4008 | |
| 4009 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4010 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4011 | |
| 4012 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4013 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4014 | |
| 4015 | |
| 4016 | // MCU3 FSR7 SERDES 0 PLL |
| 4017 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgpll[9:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 4018 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4019 | |
| 4020 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgpll[4:1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 4021 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4022 | |
| 4023 | // MCU3 FSR7 SERDES 0 Lane 0 RX |
| 4024 | |
| 4025 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx0[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4026 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4027 | |
| 4028 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx0[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4029 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4030 | |
| 4031 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx0[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4032 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4033 | |
| 4034 | // MCU3 FSR7 SERDES 0 Lane 0 TX |
| 4035 | |
| 4036 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4037 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4038 | |
| 4039 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4040 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4041 | |
| 4042 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4043 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4044 | |
| 4045 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4046 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4047 | |
| 4048 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4049 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4050 | |
| 4051 | |
| 4052 | // MCU3 FSR7 SERDES 0 Lane 1 RX |
| 4053 | |
| 4054 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx1[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4055 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4056 | |
| 4057 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx1[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4058 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4059 | |
| 4060 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx1[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4061 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4062 | |
| 4063 | // MCU3 FSR7 SERDES 0 Lane 0 TX |
| 4064 | |
| 4065 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4066 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4067 | |
| 4068 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4069 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4070 | |
| 4071 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4072 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4073 | |
| 4074 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4075 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4076 | |
| 4077 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4078 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4079 | |
| 4080 | |
| 4081 | // MCU3 FSR7 SERDES 0 Lane 2 RX |
| 4082 | |
| 4083 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx2[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4084 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4085 | |
| 4086 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx2[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4087 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4088 | |
| 4089 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx2[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4090 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4091 | |
| 4092 | // MCU3 FSR7 SERDES 0 Lane 2 TX |
| 4093 | |
| 4094 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4095 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4096 | |
| 4097 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4098 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4099 | |
| 4100 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4101 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4102 | |
| 4103 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4104 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4105 | |
| 4106 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4107 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4108 | |
| 4109 | // MCU3 FSR7 SERDES 0 Lane 3 RX |
| 4110 | |
| 4111 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx3[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4112 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4113 | |
| 4114 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx3[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4115 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4116 | |
| 4117 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx3[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4118 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4119 | |
| 4120 | // MCU3 FSR7 SERDES 0 Lane 3 TX |
| 4121 | |
| 4122 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4123 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4124 | |
| 4125 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4126 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4127 | |
| 4128 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4129 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4130 | |
| 4131 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4132 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4133 | |
| 4134 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4135 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4136 | |
| 4137 | // MCU3 FSR7 SERDES 1 PLL |
| 4138 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgpll[9:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 4139 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4140 | |
| 4141 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgpll[4:1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 4142 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4143 | |
| 4144 | // MCU3 FSR7 SERDES 1 Lane 0 RX |
| 4145 | |
| 4146 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx0[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4147 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4148 | |
| 4149 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx0[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4150 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4151 | |
| 4152 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx0[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4153 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4154 | |
| 4155 | // MCU3 FSR7 SERDES 1 Lane 1 RX |
| 4156 | |
| 4157 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx1[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4158 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4159 | |
| 4160 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx1[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4161 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4162 | |
| 4163 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx1[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4164 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4165 | |
| 4166 | // MCU3 FSR7 SERDES 1 Lane 2 RX |
| 4167 | |
| 4168 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx2[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4169 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4170 | |
| 4171 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx2[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4172 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4173 | |
| 4174 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx2[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4175 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4176 | |
| 4177 | // MCU3 FSR7 SERDES 1 Lane 3 RX |
| 4178 | |
| 4179 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx3[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4180 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4181 | |
| 4182 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx3[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4183 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4184 | |
| 4185 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx3[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4186 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4187 | |
| 4188 | // MCU3 FSR7 SERDES 1 Lane 4 RX |
| 4189 | |
| 4190 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx4[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4191 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4192 | |
| 4193 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx4[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4194 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4195 | |
| 4196 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx4[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4197 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4198 | |
| 4199 | // MCU3 FSR7 SERDES 1 Lane 5 RX |
| 4200 | |
| 4201 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx5[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4202 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4203 | |
| 4204 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx5[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4205 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4206 | |
| 4207 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx5[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4208 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4209 | |
| 4210 | // MCU3 FSR7 SERDES 1 Lane 0 TX |
| 4211 | |
| 4212 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4213 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4214 | |
| 4215 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4216 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4217 | |
| 4218 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4219 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4220 | |
| 4221 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4222 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4223 | |
| 4224 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4225 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4226 | |
| 4227 | |
| 4228 | // MCU3 FSR7 SERDES 1 Lane 1 TX |
| 4229 | |
| 4230 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4231 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4232 | |
| 4233 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4234 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4235 | |
| 4236 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4237 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4238 | |
| 4239 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4240 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4241 | |
| 4242 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4243 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4244 | |
| 4245 | // MCU3 FSR7 SERDES 2 PLL |
| 4246 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgpll[9:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[1:0] |
| 4247 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4248 | |
| 4249 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgpll[4:1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[5:2] |
| 4250 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4251 | |
| 4252 | // MCU3 FSR7 SERDES 2 Lane 0 RX |
| 4253 | |
| 4254 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx0[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4255 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4256 | |
| 4257 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx0[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4258 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4259 | |
| 4260 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx0[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4261 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4262 | |
| 4263 | // MCU3 FSR7 SERDES 2 Lane 0 TX |
| 4264 | |
| 4265 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4266 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4267 | |
| 4268 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4269 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4270 | |
| 4271 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4272 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4273 | |
| 4274 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4275 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4276 | |
| 4277 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4278 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4279 | |
| 4280 | |
| 4281 | // MCU3 FSR7 SERDES 2 Lane 1 RX |
| 4282 | |
| 4283 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx1[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4284 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4285 | |
| 4286 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx1[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4287 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4288 | |
| 4289 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx1[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4290 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4291 | |
| 4292 | // MCU3 FSR7 SERDES 2 Lane 1 TX |
| 4293 | |
| 4294 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4295 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4296 | |
| 4297 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4298 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4299 | |
| 4300 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4301 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4302 | |
| 4303 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4304 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4305 | |
| 4306 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4307 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4308 | |
| 4309 | |
| 4310 | // MCU3 FSR7 SERDES 2 Lane 2 RX |
| 4311 | |
| 4312 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx2[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4313 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4314 | |
| 4315 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx2[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4316 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4317 | |
| 4318 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx2[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4319 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4320 | |
| 4321 | // MCU3 FSR7 SERDES 2 Lane 2 TX |
| 4322 | |
| 4323 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4324 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4325 | |
| 4326 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4327 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4328 | |
| 4329 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4330 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4331 | |
| 4332 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4333 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4334 | |
| 4335 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4336 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4337 | |
| 4338 | // MCU3 FSR7 SERDES 2 Lane 3 RX |
| 4339 | |
| 4340 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx3[22:19] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[11:8] |
| 4341 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4342 | |
| 4343 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx3[18:16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[14:12] |
| 4344 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4345 | |
| 4346 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx3[10:8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[18:16] |
| 4347 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4348 | |
| 4349 | // MCU3 FSR7 SERDES 2 Lane 3 TX |
| 4350 | |
| 4351 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[16] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[19] |
| 4352 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4353 | |
| 4354 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[15:12] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[23:20] |
| 4355 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4356 | |
| 4357 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[11:9] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[26:24] |
| 4358 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4359 | |
| 4360 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[8] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[27] |
| 4361 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4362 | |
| 4363 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[6:5] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_config[29:28] |
| 4364 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4365 | |
| 4366 | // Additional for ENTEST |
| 4367 | |
| 4368 | // MCU0 FSR0 SERDES 0 RX |
| 4369 | |
| 4370 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4371 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4372 | |
| 4373 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4374 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4375 | |
| 4376 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4377 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4378 | |
| 4379 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgrx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4380 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4381 | |
| 4382 | // MCU0 FSR0 SERDES 0 TX |
| 4383 | |
| 4384 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4385 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4386 | |
| 4387 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4388 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4389 | |
| 4390 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4391 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4392 | |
| 4393 | /* 0in value -var `CPU.fsr_left.fsr0_b8_0.cfgtx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4394 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4395 | |
| 4396 | // MCU0 FSR0 SERDES 1 RX |
| 4397 | |
| 4398 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4399 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4400 | |
| 4401 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4402 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4403 | |
| 4404 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4405 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4406 | |
| 4407 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4408 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4409 | |
| 4410 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx4[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4411 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4412 | |
| 4413 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgrx5[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4414 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4415 | |
| 4416 | // MCU0 FSR0 SERDES 1 TX |
| 4417 | |
| 4418 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4419 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4420 | |
| 4421 | /* 0in value -var `CPU.fsr_left.fsr0_a8.cfgtx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4422 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4423 | |
| 4424 | // MCU0 FSR0 SERDES 2 RX |
| 4425 | |
| 4426 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4427 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4428 | |
| 4429 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4430 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4431 | |
| 4432 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4433 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4434 | |
| 4435 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgrx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4436 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4437 | |
| 4438 | // MCU0 FSR0 SERDES 2 TX |
| 4439 | |
| 4440 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4441 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4442 | |
| 4443 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4444 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4445 | |
| 4446 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4447 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4448 | |
| 4449 | /* 0in value -var `CPU.fsr_left.fsr0_b8_1.cfgtx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4450 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4451 | |
| 4452 | |
| 4453 | // MCU0 FSR1 SERDES 0 RX |
| 4454 | |
| 4455 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4456 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4457 | |
| 4458 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4459 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4460 | |
| 4461 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4462 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4463 | |
| 4464 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgrx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4465 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4466 | |
| 4467 | // MCU0 FSR1 SERDES 0 TX |
| 4468 | |
| 4469 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4470 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4471 | |
| 4472 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4473 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4474 | |
| 4475 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4476 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4477 | |
| 4478 | /* 0in value -var `CPU.fsr_left.fsr1_b8_0.cfgtx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4479 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4480 | |
| 4481 | // MCU0 FSR1 SERDES 1 RX |
| 4482 | |
| 4483 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4484 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4485 | |
| 4486 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4487 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4488 | |
| 4489 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4490 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4491 | |
| 4492 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4493 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4494 | |
| 4495 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx4[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4496 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4497 | |
| 4498 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgrx5[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4499 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4500 | |
| 4501 | // MCU0 FSR1 SERDES 1 TX |
| 4502 | |
| 4503 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4504 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4505 | |
| 4506 | /* 0in value -var `CPU.fsr_left.fsr1_a8.cfgtx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4507 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4508 | |
| 4509 | // MCU0 FSR1 SERDES 2 RX |
| 4510 | |
| 4511 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4512 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4513 | |
| 4514 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4515 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4516 | |
| 4517 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4518 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4519 | |
| 4520 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgrx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4521 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4522 | |
| 4523 | // MCU0 FSR1 SERDES 2 TX |
| 4524 | |
| 4525 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx0[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4526 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4527 | |
| 4528 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx1[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4529 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4530 | |
| 4531 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx2[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4532 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4533 | |
| 4534 | /* 0in value -var `CPU.fsr_left.fsr1_b8_1.cfgtx3[1] -val `CPU.mcu0.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4535 | -active 1'b1 -clock `CPU.mcu0.dr_gclk -reset tb_top.reset */ |
| 4536 | |
| 4537 | |
| 4538 | // MCU1 FSR2 SERDES 0 RX |
| 4539 | |
| 4540 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4541 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4542 | |
| 4543 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4544 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4545 | |
| 4546 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4547 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4548 | |
| 4549 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgrx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4550 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4551 | |
| 4552 | // MCU1 FSR2 SERDES 0 TX |
| 4553 | |
| 4554 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4555 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4556 | |
| 4557 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4558 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4559 | |
| 4560 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4561 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4562 | |
| 4563 | /* 0in value -var `CPU.fsr_left.fsr2_b8_0.cfgtx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4564 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4565 | |
| 4566 | // MCU1 FSR2 SERDES 1 RX |
| 4567 | |
| 4568 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4569 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4570 | |
| 4571 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4572 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4573 | |
| 4574 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4575 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4576 | |
| 4577 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4578 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4579 | |
| 4580 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx4[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4581 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4582 | |
| 4583 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgrx5[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4584 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4585 | |
| 4586 | // MCU1 FSR2 SERDES 1 TX |
| 4587 | |
| 4588 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4589 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4590 | |
| 4591 | /* 0in value -var `CPU.fsr_left.fsr2_a8.cfgtx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4592 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4593 | |
| 4594 | // MCU1 FSR2 SERDES 2 RX |
| 4595 | |
| 4596 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4597 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4598 | |
| 4599 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4600 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4601 | |
| 4602 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4603 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4604 | |
| 4605 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgrx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4606 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4607 | |
| 4608 | // MCU1 FSR2 SERDES 2 TX |
| 4609 | |
| 4610 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4611 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4612 | |
| 4613 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4614 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4615 | |
| 4616 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4617 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4618 | |
| 4619 | /* 0in value -var `CPU.fsr_left.fsr2_b8_1.cfgtx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4620 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4621 | |
| 4622 | |
| 4623 | // MCU1 FSR3 SERDES 0 RX |
| 4624 | |
| 4625 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4626 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4627 | |
| 4628 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4629 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4630 | |
| 4631 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4632 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4633 | |
| 4634 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgrx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4635 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4636 | |
| 4637 | // MCU1 FSR3 SERDES 0 TX |
| 4638 | |
| 4639 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4640 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4641 | |
| 4642 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4643 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4644 | |
| 4645 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4646 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4647 | |
| 4648 | /* 0in value -var `CPU.fsr_left.fsr3_b8_0.cfgtx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4649 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4650 | |
| 4651 | // MCU1 FSR3 SERDES 1 RX |
| 4652 | |
| 4653 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4654 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4655 | |
| 4656 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4657 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4658 | |
| 4659 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4660 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4661 | |
| 4662 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4663 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4664 | |
| 4665 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx4[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4666 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4667 | |
| 4668 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgrx5[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4669 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4670 | |
| 4671 | // MCU1 FSR3 SERDES 1 TX |
| 4672 | |
| 4673 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4674 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4675 | |
| 4676 | /* 0in value -var `CPU.fsr_left.fsr3_a8.cfgtx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4677 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4678 | |
| 4679 | // MCU1 FSR3 SERDES 2 RX |
| 4680 | |
| 4681 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4682 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4683 | |
| 4684 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4685 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4686 | |
| 4687 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4688 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4689 | |
| 4690 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgrx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4691 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4692 | |
| 4693 | // MCU1 FSR3 SERDES 2 TX |
| 4694 | |
| 4695 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx0[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4696 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4697 | |
| 4698 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx1[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4699 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4700 | |
| 4701 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx2[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4702 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4703 | |
| 4704 | /* 0in value -var `CPU.fsr_left.fsr3_b8_1.cfgtx3[1] -val `CPU.mcu1.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4705 | -active 1'b1 -clock `CPU.mcu1.dr_gclk -reset tb_top.reset */ |
| 4706 | |
| 4707 | |
| 4708 | // MCU2 FSR4 SERDES 0 RX |
| 4709 | |
| 4710 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4711 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4712 | |
| 4713 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4714 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4715 | |
| 4716 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4717 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4718 | |
| 4719 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgrx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4720 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4721 | |
| 4722 | // MCU2 FSR4 SERDES 0 TX |
| 4723 | |
| 4724 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4725 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4726 | |
| 4727 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4728 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4729 | |
| 4730 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4731 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4732 | |
| 4733 | /* 0in value -var `CPU.fsr_right.fsr4_b8_0.cfgtx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4734 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4735 | |
| 4736 | // MCU2 FSR4 SERDES 1 RX |
| 4737 | |
| 4738 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4739 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4740 | |
| 4741 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4742 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4743 | |
| 4744 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4745 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4746 | |
| 4747 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4748 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4749 | |
| 4750 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx4[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4751 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4752 | |
| 4753 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgrx5[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4754 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4755 | |
| 4756 | // MCU2 FSR4 SERDES 1 TX |
| 4757 | |
| 4758 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4759 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4760 | |
| 4761 | /* 0in value -var `CPU.fsr_right.fsr4_a8.cfgtx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4762 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4763 | |
| 4764 | // MCU2 FSR4 SERDES 2 RX |
| 4765 | |
| 4766 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4767 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4768 | |
| 4769 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4770 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4771 | |
| 4772 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4773 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4774 | |
| 4775 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgrx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4776 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4777 | |
| 4778 | // MCU2 FSR4 SERDES 2 TX |
| 4779 | |
| 4780 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4781 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4782 | |
| 4783 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4784 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4785 | |
| 4786 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4787 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4788 | |
| 4789 | /* 0in value -var `CPU.fsr_right.fsr4_b8_1.cfgtx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4790 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4791 | |
| 4792 | |
| 4793 | // MCU2 FSR5 SERDES 0 RX |
| 4794 | |
| 4795 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4796 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4797 | |
| 4798 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4799 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4800 | |
| 4801 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4802 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4803 | |
| 4804 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgrx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4805 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4806 | |
| 4807 | // MCU2 FSR5 SERDES 0 TX |
| 4808 | |
| 4809 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4810 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4811 | |
| 4812 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4813 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4814 | |
| 4815 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4816 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4817 | |
| 4818 | /* 0in value -var `CPU.fsr_right.fsr5_b8_0.cfgtx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4819 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4820 | |
| 4821 | // MCU2 FSR5 SERDES 1 RX |
| 4822 | |
| 4823 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4824 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4825 | |
| 4826 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4827 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4828 | |
| 4829 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4830 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4831 | |
| 4832 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4833 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4834 | |
| 4835 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx4[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4836 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4837 | |
| 4838 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgrx5[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4839 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4840 | |
| 4841 | // MCU2 FSR5 SERDES 1 TX |
| 4842 | |
| 4843 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4844 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4845 | |
| 4846 | /* 0in value -var `CPU.fsr_right.fsr5_a8.cfgtx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4847 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4848 | |
| 4849 | // MCU2 FSR5 SERDES 2 RX |
| 4850 | |
| 4851 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4852 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4853 | |
| 4854 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4855 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4856 | |
| 4857 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4858 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4859 | |
| 4860 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgrx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4861 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4862 | |
| 4863 | // MCU2 FSR5 SERDES 2 TX |
| 4864 | |
| 4865 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx0[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4866 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4867 | |
| 4868 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx1[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4869 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4870 | |
| 4871 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx2[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4872 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4873 | |
| 4874 | /* 0in value -var `CPU.fsr_right.fsr5_b8_1.cfgtx3[1] -val `CPU.mcu2.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4875 | -active 1'b1 -clock `CPU.mcu2.dr_gclk -reset tb_top.reset */ |
| 4876 | |
| 4877 | |
| 4878 | // MCU3 FSR6 SERDES 0 RX |
| 4879 | |
| 4880 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4881 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4882 | |
| 4883 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4884 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4885 | |
| 4886 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4887 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4888 | |
| 4889 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgrx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4890 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4891 | |
| 4892 | // MCU3 FSR6 SERDES 0 TX |
| 4893 | |
| 4894 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4895 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4896 | |
| 4897 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4898 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4899 | |
| 4900 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4901 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4902 | |
| 4903 | /* 0in value -var `CPU.fsr_right.fsr6_b8_0.cfgtx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4904 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4905 | |
| 4906 | // MCU3 FSR6 SERDES 1 RX |
| 4907 | |
| 4908 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4909 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4910 | |
| 4911 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4912 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4913 | |
| 4914 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4915 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4916 | |
| 4917 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4918 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4919 | |
| 4920 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx4[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4921 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4922 | |
| 4923 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgrx5[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4924 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4925 | |
| 4926 | // MCU3 FSR6 SERDES 1 TX |
| 4927 | |
| 4928 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4929 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4930 | |
| 4931 | /* 0in value -var `CPU.fsr_right.fsr6_a8.cfgtx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4932 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4933 | |
| 4934 | // MCU3 FSR6 SERDES 2 RX |
| 4935 | |
| 4936 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4937 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4938 | |
| 4939 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4940 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4941 | |
| 4942 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4943 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4944 | |
| 4945 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgrx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[28] |
| 4946 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4947 | |
| 4948 | // MCU3 FSR6 SERDES 2 TX |
| 4949 | |
| 4950 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4951 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4952 | |
| 4953 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4954 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4955 | |
| 4956 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4957 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4958 | |
| 4959 | /* 0in value -var `CPU.fsr_right.fsr6_b8_1.cfgtx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[30] |
| 4960 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4961 | |
| 4962 | |
| 4963 | // MCU3 FSR7 SERDES 0 RX |
| 4964 | |
| 4965 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4966 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4967 | |
| 4968 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4969 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4970 | |
| 4971 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4972 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4973 | |
| 4974 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgrx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4975 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4976 | |
| 4977 | // MCU3 FSR7 SERDES 0 TX |
| 4978 | |
| 4979 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4980 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4981 | |
| 4982 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4983 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4984 | |
| 4985 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4986 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4987 | |
| 4988 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_0.cfgtx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 4989 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4990 | |
| 4991 | // MCU3 FSR7 SERDES 1 RX |
| 4992 | |
| 4993 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4994 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4995 | |
| 4996 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 4997 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 4998 | |
| 4999 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5000 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5001 | |
| 5002 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5003 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5004 | |
| 5005 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx4[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5006 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5007 | |
| 5008 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgrx5[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5009 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5010 | |
| 5011 | // MCU3 FSR7 SERDES 1 TX |
| 5012 | |
| 5013 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 5014 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5015 | |
| 5016 | /* 0in value -var `CPU.fsr_bottom.fsr7_a8.cfgtx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 5017 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5018 | |
| 5019 | // MCU3 FSR7 SERDES 2 RX |
| 5020 | |
| 5021 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5022 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5023 | |
| 5024 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5025 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5026 | |
| 5027 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5028 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5029 | |
| 5030 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgrx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[29] |
| 5031 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5032 | |
| 5033 | // MCU3 FSR7 SERDES 2 TX |
| 5034 | |
| 5035 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx0[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 5036 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5037 | |
| 5038 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx1[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 5039 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5040 | |
| 5041 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx2[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 5042 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5043 | |
| 5044 | /* 0in value -var `CPU.fsr_bottom.fsr7_b8_1.cfgtx3[1] -val `CPU.mcu3.fbdic.fbdtm.fbdic_sds_testcfg[31] |
| 5045 | -active 1'b1 -clock `CPU.mcu3.dr_gclk -reset tb_top.reset */ |
| 5046 | |
| 5047 | |
| 5048 | // SERDES0 |
| 5049 | |
| 5050 | // .cfgrx0 |
| 5051 | |
| 5052 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_0[15:14] |
| 5053 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5054 | |
| 5055 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_0[13:10] |
| 5056 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5057 | |
| 5058 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_0[9:7] |
| 5059 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5060 | |
| 5061 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_0[6:5] |
| 5062 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5063 | |
| 5064 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[12] -val `CPU.peu.peu_psr_rx_lane_ctl_0[1] |
| 5065 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5066 | |
| 5067 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_0[4:2] |
| 5068 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5069 | |
| 5070 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[7] -val `CPU.peu.peu_psr_invpair_b0sds0 |
| 5071 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5072 | |
| 5073 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5074 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5075 | |
| 5076 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[1] -val `CPU.peu.peu_psr_rx_lane_ctl_0[0] |
| 5077 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5078 | |
| 5079 | /* 0in value -var `CPU.psr.serdes_0.cfgrx0[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b0_sds0 |
| 5080 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5081 | |
| 5082 | // .cfgrx1 |
| 5083 | |
| 5084 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_1[15:14] |
| 5085 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5086 | |
| 5087 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_1[13:10] |
| 5088 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5089 | |
| 5090 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_1[9:7] |
| 5091 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5092 | |
| 5093 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_1[6:5] |
| 5094 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5095 | |
| 5096 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[12] -val `CPU.peu.peu_psr_rx_lane_ctl_1[1] |
| 5097 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5098 | |
| 5099 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_1[4:2] |
| 5100 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5101 | |
| 5102 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[7] -val `CPU.peu.peu_psr_invpair_b1sds0 |
| 5103 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5104 | |
| 5105 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5106 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5107 | |
| 5108 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[1] -val `CPU.peu.peu_psr_rx_lane_ctl_1[0] |
| 5109 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5110 | |
| 5111 | /* 0in value -var `CPU.psr.serdes_0.cfgrx1[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b1_sds0 |
| 5112 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5113 | |
| 5114 | // .cfgrx2 |
| 5115 | |
| 5116 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_2[15:14] |
| 5117 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5118 | |
| 5119 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_2[13:10] |
| 5120 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5121 | |
| 5122 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_2[9:7] |
| 5123 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5124 | |
| 5125 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_2[6:5] |
| 5126 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5127 | |
| 5128 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[12] -val `CPU.peu.peu_psr_rx_lane_ctl_2[1] |
| 5129 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5130 | |
| 5131 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_2[4:2] |
| 5132 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5133 | |
| 5134 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[7] -val `CPU.peu.peu_psr_invpair_b2sds0 |
| 5135 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5136 | |
| 5137 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5138 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5139 | |
| 5140 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[1] -val `CPU.peu.peu_psr_rx_lane_ctl_2[0] |
| 5141 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5142 | |
| 5143 | /* 0in value -var `CPU.psr.serdes_0.cfgrx2[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b2_sds0 |
| 5144 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5145 | |
| 5146 | // .cfgrx3 |
| 5147 | |
| 5148 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_3[15:14] |
| 5149 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5150 | |
| 5151 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_3[13:10] |
| 5152 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5153 | |
| 5154 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_3[9:7] |
| 5155 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5156 | |
| 5157 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_3[6:5] |
| 5158 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5159 | |
| 5160 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[12] -val `CPU.peu.peu_psr_rx_lane_ctl_3[1] |
| 5161 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5162 | |
| 5163 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_3[4:2] |
| 5164 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5165 | |
| 5166 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[7] -val `CPU.peu.peu_psr_invpair_b3sds0 |
| 5167 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5168 | |
| 5169 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5170 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5171 | |
| 5172 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[1] -val `CPU.peu.peu_psr_rx_lane_ctl_3[0] |
| 5173 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5174 | |
| 5175 | /* 0in value -var `CPU.psr.serdes_0.cfgrx3[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b3_sds0 |
| 5176 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5177 | |
| 5178 | // .cfgtx0 |
| 5179 | |
| 5180 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[22:21] -val `CPU.peu.peu_psr_rdtct_b0sds0[1:0] |
| 5181 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5182 | |
| 5183 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[20] -val `CPU.peu.peu_psr_enidl_b0sds0 |
| 5184 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5185 | |
| 5186 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[17] -val `CPU.peu.peu_psr_bstx_b0sds0 |
| 5187 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5188 | |
| 5189 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_0[9:6] |
| 5190 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5191 | |
| 5192 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_0[5:3] |
| 5193 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5194 | |
| 5195 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[8] -val `CPU.peu.peu_psr_tx_lane_ctl_0[2] |
| 5196 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5197 | |
| 5198 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[7] -val `CPU.peu.peu_psr_tx_lane_ctl_0[1] |
| 5199 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5200 | |
| 5201 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5202 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5203 | |
| 5204 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[1] -val `CPU.peu.peu_psr_rx_lane_ctl_0[0] |
| 5205 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5206 | |
| 5207 | /* 0in value -var `CPU.psr.serdes_0.cfgtx0[0] -val `CPU.dmu.dmu_psr_tx_en_b0_sds0 |
| 5208 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5209 | |
| 5210 | // .cfgtx1 |
| 5211 | |
| 5212 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[22:21] -val `CPU.peu.peu_psr_rdtct_b1sds0[1:0] |
| 5213 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5214 | |
| 5215 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[20] -val `CPU.peu.peu_psr_enidl_b1sds0 |
| 5216 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5217 | |
| 5218 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[17] -val `CPU.peu.peu_psr_bstx_b1sds0 |
| 5219 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5220 | |
| 5221 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_1[9:6] |
| 5222 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5223 | |
| 5224 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_1[5:3] |
| 5225 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5226 | |
| 5227 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[8] -val `CPU.peu.peu_psr_tx_lane_ctl_1[2] |
| 5228 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5229 | |
| 5230 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[7] -val `CPU.peu.peu_psr_tx_lane_ctl_1[1] |
| 5231 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5232 | |
| 5233 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5234 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5235 | |
| 5236 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[1] -val `CPU.peu.peu_psr_rx_lane_ctl_1[0] |
| 5237 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5238 | |
| 5239 | /* 0in value -var `CPU.psr.serdes_0.cfgtx1[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b1_sds0 |
| 5240 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5241 | |
| 5242 | // .cfgtx2 |
| 5243 | |
| 5244 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[22:21] -val `CPU.peu.peu_psr_rdtct_b2sds0[1:0] |
| 5245 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5246 | |
| 5247 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[20] -val `CPU.peu.peu_psr_enidl_b2sds0 |
| 5248 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5249 | |
| 5250 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[17] -val `CPU.peu.peu_psr_bstx_b2sds0 |
| 5251 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5252 | |
| 5253 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_2[9:6] |
| 5254 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5255 | |
| 5256 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_2[5:3] |
| 5257 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5258 | |
| 5259 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[8] -val `CPU.peu.peu_psr_tx_lane_ctl_2[2] |
| 5260 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5261 | |
| 5262 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[7] -val `CPU.peu.peu_psr_tx_lane_ctl_2[1] |
| 5263 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5264 | |
| 5265 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5266 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5267 | |
| 5268 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[1] -val `CPU.peu.peu_psr_rx_lane_ctl_2[0] |
| 5269 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5270 | |
| 5271 | /* 0in value -var `CPU.psr.serdes_0.cfgtx2[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b2_sds0 |
| 5272 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5273 | |
| 5274 | // .cfgtx3 |
| 5275 | |
| 5276 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[22:21] -val `CPU.peu.peu_psr_rdtct_b3sds0[1:0] |
| 5277 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5278 | |
| 5279 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[20] -val `CPU.peu.peu_psr_enidl_b3sds0 |
| 5280 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5281 | |
| 5282 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[17] -val `CPU.peu.peu_psr_bstx_b3sds0 |
| 5283 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5284 | |
| 5285 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_3[9:6] |
| 5286 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5287 | |
| 5288 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_3[5:3] |
| 5289 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5290 | |
| 5291 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[8] -val `CPU.peu.peu_psr_tx_lane_ctl_3[2] |
| 5292 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5293 | |
| 5294 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[7] -val `CPU.peu.peu_psr_tx_lane_ctl_3[1] |
| 5295 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5296 | |
| 5297 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5298 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5299 | |
| 5300 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[1] -val `CPU.peu.peu_psr_rx_lane_ctl_3[0] |
| 5301 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5302 | |
| 5303 | /* 0in value -var `CPU.psr.serdes_0.cfgtx3[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b3_sds0 |
| 5304 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5305 | |
| 5306 | |
| 5307 | // .stspll Hunter may not have the correct clock for this |
| 5308 | |
| 5309 | /* 0in value -var `CPU.psr.serdes_0.stspll[0] -val `CPU.peu.psr_peu_lock_sds0 |
| 5310 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5311 | |
| 5312 | |
| 5313 | |
| 5314 | /* 0in value -var `CPU.psr.serdes_0.stsrx0[0] -val `CPU.peu.psr_peu_rx_tstfail_b0sds0 |
| 5315 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5316 | |
| 5317 | /* 0in value -var `CPU.psr.serdes_0.stsrx0[1] -val `CPU.peu.psr_peu_sync_b0sds0 |
| 5318 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5319 | |
| 5320 | /* 0in value -var `CPU.psr.serdes_0.stsrx0[3] -val `CPU.peu.psr_peu_losdtct_b0sds0 |
| 5321 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5322 | |
| 5323 | /* 0in value -var `CPU.psr.serdes_0.stsrx0[4] -val `CPU.peu.psr_peu_bsrxp_b0sds0 |
| 5324 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5325 | |
| 5326 | /* 0in value -var `CPU.psr.serdes_0.stsrx0[5] -val `CPU.peu.psr_peu_bsrxn_b0sds0 |
| 5327 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5328 | |
| 5329 | |
| 5330 | |
| 5331 | /* 0in value -var `CPU.psr.serdes_0.stsrx1[0] -val `CPU.peu.psr_peu_rx_tstfail_b1sds0 |
| 5332 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5333 | |
| 5334 | /* 0in value -var `CPU.psr.serdes_0.stsrx1[1] -val `CPU.peu.psr_peu_sync_b1sds0 |
| 5335 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5336 | |
| 5337 | /* 0in value -var `CPU.psr.serdes_0.stsrx1[3] -val `CPU.peu.psr_peu_losdtct_b1sds0 |
| 5338 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5339 | |
| 5340 | /* 0in value -var `CPU.psr.serdes_0.stsrx1[4] -val `CPU.peu.psr_peu_bsrxp_b1sds0 |
| 5341 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5342 | |
| 5343 | /* 0in value -var `CPU.psr.serdes_0.stsrx1[5] -val `CPU.peu.psr_peu_bsrxn_b1sds0 |
| 5344 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5345 | |
| 5346 | |
| 5347 | |
| 5348 | |
| 5349 | /* 0in value -var `CPU.psr.serdes_0.stsrx2[0] -val `CPU.peu.psr_peu_rx_tstfail_b2sds0 |
| 5350 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5351 | |
| 5352 | /* 0in value -var `CPU.psr.serdes_0.stsrx2[1] -val `CPU.peu.psr_peu_sync_b2sds0 |
| 5353 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5354 | |
| 5355 | /* 0in value -var `CPU.psr.serdes_0.stsrx2[3] -val `CPU.peu.psr_peu_losdtct_b2sds0 |
| 5356 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5357 | |
| 5358 | /* 0in value -var `CPU.psr.serdes_0.stsrx2[4] -val `CPU.peu.psr_peu_bsrxp_b2sds0 |
| 5359 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5360 | |
| 5361 | /* 0in value -var `CPU.psr.serdes_0.stsrx2[5] -val `CPU.peu.psr_peu_bsrxn_b2sds0 |
| 5362 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5363 | |
| 5364 | |
| 5365 | |
| 5366 | /* 0in value -var `CPU.psr.serdes_0.stsrx3[0] -val `CPU.peu.psr_peu_rx_tstfail_b3sds0 |
| 5367 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5368 | |
| 5369 | /* 0in value -var `CPU.psr.serdes_0.stsrx3[1] -val `CPU.peu.psr_peu_sync_b3sds0 |
| 5370 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5371 | |
| 5372 | /* 0in value -var `CPU.psr.serdes_0.stsrx3[3] -val `CPU.peu.psr_peu_losdtct_b3sds0 |
| 5373 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5374 | |
| 5375 | /* 0in value -var `CPU.psr.serdes_0.stsrx3[4] -val `CPU.peu.psr_peu_bsrxp_b3sds0 |
| 5376 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5377 | |
| 5378 | /* 0in value -var `CPU.psr.serdes_0.stsrx3[5] -val `CPU.peu.psr_peu_bsrxn_b3sds0 |
| 5379 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5380 | |
| 5381 | |
| 5382 | |
| 5383 | /* 0in value -var `CPU.psr.serdes_0.ststx0[0] -val `CPU.peu.psr_peu_tx_tstfail_b0sds0 |
| 5384 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5385 | |
| 5386 | /* 0in value -var `CPU.psr.serdes_0.ststx0[1] -val `CPU.peu.psr_peu_rdtcip_b0sds0 |
| 5387 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5388 | |
| 5389 | |
| 5390 | |
| 5391 | /* 0in value -var `CPU.psr.serdes_0.ststx1[0] -val `CPU.peu.psr_peu_tx_tstfail_b1sds0 |
| 5392 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5393 | |
| 5394 | /* 0in value -var `CPU.psr.serdes_0.ststx1[1] -val `CPU.peu.psr_peu_rdtcip_b1sds0 |
| 5395 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5396 | |
| 5397 | |
| 5398 | |
| 5399 | /* 0in value -var `CPU.psr.serdes_0.ststx2[0] -val `CPU.peu.psr_peu_tx_tstfail_b2sds0 |
| 5400 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5401 | |
| 5402 | /* 0in value -var `CPU.psr.serdes_0.ststx2[1] -val `CPU.peu.psr_peu_rdtcip_b2sds0 |
| 5403 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5404 | |
| 5405 | |
| 5406 | |
| 5407 | /* 0in value -var `CPU.psr.serdes_0.ststx3[0] -val `CPU.peu.psr_peu_tx_tstfail_b3sds0 |
| 5408 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5409 | |
| 5410 | /* 0in value -var `CPU.psr.serdes_0.ststx3[1] -val `CPU.peu.psr_peu_rdtcip_b3sds0 |
| 5411 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5412 | |
| 5413 | |
| 5414 | |
| 5415 | |
| 5416 | |
| 5417 | |
| 5418 | // SERDES1 |
| 5419 | |
| 5420 | // .cfgrx0 |
| 5421 | |
| 5422 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_4[15:14] |
| 5423 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5424 | |
| 5425 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_4[13:10] |
| 5426 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5427 | |
| 5428 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_4[9:7] |
| 5429 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5430 | |
| 5431 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_4[6:5] |
| 5432 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5433 | |
| 5434 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[12] -val `CPU.peu.peu_psr_rx_lane_ctl_4[1] |
| 5435 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5436 | |
| 5437 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_4[4:2] |
| 5438 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5439 | |
| 5440 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[7] -val `CPU.peu.peu_psr_invpair_b0sds1 |
| 5441 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5442 | |
| 5443 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5444 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5445 | |
| 5446 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[1] -val `CPU.peu.peu_psr_rx_lane_ctl_4[0] |
| 5447 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5448 | |
| 5449 | /* 0in value -var `CPU.psr.serdes_1.cfgrx0[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b0_sds1 |
| 5450 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5451 | |
| 5452 | // .cfgrx1 |
| 5453 | |
| 5454 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_5[15:14] |
| 5455 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5456 | |
| 5457 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_5[13:10] |
| 5458 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5459 | |
| 5460 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_5[9:7] |
| 5461 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5462 | |
| 5463 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_5[6:5] |
| 5464 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5465 | |
| 5466 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[12] -val `CPU.peu.peu_psr_rx_lane_ctl_5[1] |
| 5467 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5468 | |
| 5469 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_5[4:2] |
| 5470 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5471 | |
| 5472 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[7] -val `CPU.peu.peu_psr_invpair_b1sds1 |
| 5473 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5474 | |
| 5475 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5476 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5477 | |
| 5478 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[1] -val `CPU.peu.peu_psr_rx_lane_ctl_5[0] |
| 5479 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5480 | |
| 5481 | /* 0in value -var `CPU.psr.serdes_1.cfgrx1[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b1_sds1 |
| 5482 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5483 | |
| 5484 | // .cfgrx2 |
| 5485 | |
| 5486 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_6[15:14] |
| 5487 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5488 | |
| 5489 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_6[13:10] |
| 5490 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5491 | |
| 5492 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_6[9:7] |
| 5493 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5494 | |
| 5495 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_6[6:5] |
| 5496 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5497 | |
| 5498 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[12] -val `CPU.peu.peu_psr_rx_lane_ctl_6[1] |
| 5499 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5500 | |
| 5501 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_6[4:2] |
| 5502 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5503 | |
| 5504 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[7] -val `CPU.peu.peu_psr_invpair_b2sds1 |
| 5505 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5506 | |
| 5507 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5508 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5509 | |
| 5510 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[1] -val `CPU.peu.peu_psr_rx_lane_ctl_6[0] |
| 5511 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5512 | |
| 5513 | /* 0in value -var `CPU.psr.serdes_1.cfgrx2[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b2_sds1 |
| 5514 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5515 | |
| 5516 | // .cfgrx3 |
| 5517 | |
| 5518 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[25:24] -val `CPU.peu.peu_psr_rx_lane_ctl_7[15:14] |
| 5519 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5520 | |
| 5521 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[22:19] -val `CPU.peu.peu_psr_rx_lane_ctl_7[13:10] |
| 5522 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5523 | |
| 5524 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[18:16] -val `CPU.peu.peu_psr_rx_lane_ctl_7[9:7] |
| 5525 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5526 | |
| 5527 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[15:14] -val `CPU.peu.peu_psr_rx_lane_ctl_7[6:5] |
| 5528 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5529 | |
| 5530 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[12] -val `CPU.peu.peu_psr_rx_lane_ctl_7[1] |
| 5531 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5532 | |
| 5533 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[10:8] -val `CPU.peu.peu_psr_rx_lane_ctl_7[4:2] |
| 5534 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5535 | |
| 5536 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[7] -val `CPU.peu.peu_psr_invpair_b3sds1 |
| 5537 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5538 | |
| 5539 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5540 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5541 | |
| 5542 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[1] -val `CPU.peu.peu_psr_rx_lane_ctl_7[0] |
| 5543 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5544 | |
| 5545 | /* 0in value -var `CPU.psr.serdes_1.cfgrx3[0] -val `CPU.dmu.ilu.cib.dmu_psr_rx_en_b3_sds1 |
| 5546 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5547 | |
| 5548 | // .cfgtx0 |
| 5549 | |
| 5550 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[22:21] -val `CPU.peu.peu_psr_rdtct_b0sds1[1:0] |
| 5551 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5552 | |
| 5553 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[20] -val `CPU.peu.peu_psr_enidl_b0sds1 |
| 5554 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5555 | |
| 5556 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[17] -val `CPU.peu.peu_psr_bstx_b0sds1 |
| 5557 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5558 | |
| 5559 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_4[9:6] |
| 5560 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5561 | |
| 5562 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_4[5:3] |
| 5563 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5564 | |
| 5565 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[8] -val `CPU.peu.peu_psr_tx_lane_ctl_4[2] |
| 5566 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5567 | |
| 5568 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[7] -val `CPU.peu.peu_psr_tx_lane_ctl_4[1] |
| 5569 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5570 | |
| 5571 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5572 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5573 | |
| 5574 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[1] -val `CPU.peu.peu_psr_rx_lane_ctl_4[0] |
| 5575 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5576 | |
| 5577 | /* 0in value -var `CPU.psr.serdes_1.cfgtx0[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b0_sds1 |
| 5578 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5579 | |
| 5580 | // .cfgtx1 |
| 5581 | |
| 5582 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[22:21] -val `CPU.peu.peu_psr_rdtct_b1sds1[1:0] |
| 5583 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5584 | |
| 5585 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[20] -val `CPU.peu.peu_psr_enidl_b1sds1 |
| 5586 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5587 | |
| 5588 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[17] -val `CPU.peu.peu_psr_bstx_b1sds1 |
| 5589 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5590 | |
| 5591 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_5[9:6] |
| 5592 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5593 | |
| 5594 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_5[5:3] |
| 5595 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5596 | |
| 5597 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[8] -val `CPU.peu.peu_psr_tx_lane_ctl_5[2] |
| 5598 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5599 | |
| 5600 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[7] -val `CPU.peu.peu_psr_tx_lane_ctl_5[1] |
| 5601 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5602 | |
| 5603 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5604 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5605 | |
| 5606 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[1] -val `CPU.peu.peu_psr_rx_lane_ctl_5[0] |
| 5607 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5608 | |
| 5609 | /* 0in value -var `CPU.psr.serdes_1.cfgtx1[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b1_sds1 |
| 5610 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5611 | |
| 5612 | // .cfgtx2 |
| 5613 | |
| 5614 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[22:21] -val `CPU.peu.peu_psr_rdtct_b2sds1[1:0] |
| 5615 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5616 | |
| 5617 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[20] -val `CPU.peu.peu_psr_enidl_b2sds1 |
| 5618 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5619 | |
| 5620 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[17] -val `CPU.peu.peu_psr_bstx_b2sds1 |
| 5621 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5622 | |
| 5623 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_6[9:6] |
| 5624 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5625 | |
| 5626 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_6[5:3] |
| 5627 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5628 | |
| 5629 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[8] -val `CPU.peu.peu_psr_tx_lane_ctl_6[2] |
| 5630 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5631 | |
| 5632 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[7] -val `CPU.peu.peu_psr_tx_lane_ctl_6[1] |
| 5633 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5634 | |
| 5635 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5636 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5637 | |
| 5638 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[1] -val `CPU.peu.peu_psr_rx_lane_ctl_6[0] |
| 5639 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5640 | |
| 5641 | /* 0in value -var `CPU.psr.serdes_1.cfgtx2[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b2_sds1 |
| 5642 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5643 | |
| 5644 | // .cfgtx3 |
| 5645 | |
| 5646 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[22:21] -val `CPU.peu.peu_psr_rdtct_b3sds1[1:0] |
| 5647 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5648 | |
| 5649 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[20] -val `CPU.peu.peu_psr_enidl_b3sds1 |
| 5650 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5651 | |
| 5652 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[17] -val `CPU.peu.peu_psr_bstx_b3sds1 |
| 5653 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5654 | |
| 5655 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[15:12] -val `CPU.peu.peu_psr_tx_lane_ctl_7[9:6] |
| 5656 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5657 | |
| 5658 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[11:9] -val `CPU.peu.peu_psr_tx_lane_ctl_7[5:3] |
| 5659 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5660 | |
| 5661 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[8] -val `CPU.peu.peu_psr_tx_lane_ctl_7[2] |
| 5662 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5663 | |
| 5664 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[7] -val `CPU.peu.peu_psr_tx_lane_ctl_7[1] |
| 5665 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5666 | |
| 5667 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[6:5] -val `CPU.dmu.ilu.cib.ilu_diagnos_rate_scale_hw_read[1:0] |
| 5668 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5669 | |
| 5670 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[1] -val `CPU.peu.peu_psr_rx_lane_ctl_7[0] |
| 5671 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5672 | |
| 5673 | /* 0in value -var `CPU.psr.serdes_1.cfgtx3[0] -val `CPU.dmu.ilu.cib.dmu_psr_tx_en_b3_sds1 |
| 5674 | -active 1'b1 -clock `CPU.dmu.iol2clk -reset tb_top.reset */ |
| 5675 | |
| 5676 | |
| 5677 | // .stspll Hunter may not have the correct clock for this |
| 5678 | |
| 5679 | /* 0in value -var `CPU.psr.serdes_1.stspll[0] -val `CPU.peu.psr_peu_lock_sds1 |
| 5680 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5681 | |
| 5682 | |
| 5683 | |
| 5684 | /* 0in value -var `CPU.psr.serdes_1.stsrx0[0] -val `CPU.peu.psr_peu_rx_tstfail_b0sds1 |
| 5685 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5686 | |
| 5687 | /* 0in value -var `CPU.psr.serdes_1.stsrx0[1] -val `CPU.peu.psr_peu_sync_b0sds1 |
| 5688 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5689 | |
| 5690 | /* 0in value -var `CPU.psr.serdes_1.stsrx0[3] -val `CPU.peu.psr_peu_losdtct_b0sds1 |
| 5691 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5692 | |
| 5693 | /* 0in value -var `CPU.psr.serdes_1.stsrx0[4] -val `CPU.peu.psr_peu_bsrxp_b0sds1 |
| 5694 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5695 | |
| 5696 | /* 0in value -var `CPU.psr.serdes_1.stsrx0[5] -val `CPU.peu.psr_peu_bsrxn_b0sds1 |
| 5697 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5698 | |
| 5699 | |
| 5700 | |
| 5701 | /* 0in value -var `CPU.psr.serdes_1.stsrx1[0] -val `CPU.peu.psr_peu_rx_tstfail_b1sds1 |
| 5702 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5703 | |
| 5704 | /* 0in value -var `CPU.psr.serdes_1.stsrx1[1] -val `CPU.peu.psr_peu_sync_b1sds1 |
| 5705 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5706 | |
| 5707 | /* 0in value -var `CPU.psr.serdes_1.stsrx1[3] -val `CPU.peu.psr_peu_losdtct_b1sds1 |
| 5708 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5709 | |
| 5710 | /* 0in value -var `CPU.psr.serdes_1.stsrx1[4] -val `CPU.peu.psr_peu_bsrxp_b1sds1 |
| 5711 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5712 | |
| 5713 | /* 0in value -var `CPU.psr.serdes_1.stsrx1[5] -val `CPU.peu.psr_peu_bsrxn_b1sds1 |
| 5714 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5715 | |
| 5716 | |
| 5717 | |
| 5718 | |
| 5719 | /* 0in value -var `CPU.psr.serdes_1.stsrx2[0] -val `CPU.peu.psr_peu_rx_tstfail_b2sds1 |
| 5720 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5721 | |
| 5722 | /* 0in value -var `CPU.psr.serdes_1.stsrx2[1] -val `CPU.peu.psr_peu_sync_b2sds1 |
| 5723 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5724 | |
| 5725 | /* 0in value -var `CPU.psr.serdes_1.stsrx2[3] -val `CPU.peu.psr_peu_losdtct_b2sds1 |
| 5726 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5727 | |
| 5728 | /* 0in value -var `CPU.psr.serdes_1.stsrx2[4] -val `CPU.peu.psr_peu_bsrxp_b2sds1 |
| 5729 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5730 | |
| 5731 | /* 0in value -var `CPU.psr.serdes_1.stsrx2[5] -val `CPU.peu.psr_peu_bsrxn_b2sds1 |
| 5732 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5733 | |
| 5734 | |
| 5735 | |
| 5736 | /* 0in value -var `CPU.psr.serdes_1.stsrx3[0] -val `CPU.peu.psr_peu_rx_tstfail_b3sds1 |
| 5737 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5738 | |
| 5739 | /* 0in value -var `CPU.psr.serdes_1.stsrx3[1] -val `CPU.peu.psr_peu_sync_b3sds1 |
| 5740 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5741 | |
| 5742 | /* 0in value -var `CPU.psr.serdes_1.stsrx3[3] -val `CPU.peu.psr_peu_losdtct_b3sds1 |
| 5743 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5744 | |
| 5745 | /* 0in value -var `CPU.psr.serdes_1.stsrx3[4] -val `CPU.peu.psr_peu_bsrxp_b3sds1 |
| 5746 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5747 | |
| 5748 | /* 0in value -var `CPU.psr.serdes_1.stsrx3[5] -val `CPU.peu.psr_peu_bsrxn_b3sds1 |
| 5749 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5750 | |
| 5751 | |
| 5752 | |
| 5753 | /* 0in value -var `CPU.psr.serdes_1.ststx0[0] -val `CPU.peu.psr_peu_tx_tstfail_b0sds1 |
| 5754 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5755 | |
| 5756 | /* 0in value -var `CPU.psr.serdes_1.ststx0[1] -val `CPU.peu.psr_peu_rdtcip_b0sds1 |
| 5757 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5758 | |
| 5759 | |
| 5760 | |
| 5761 | /* 0in value -var `CPU.psr.serdes_1.ststx1[0] -val `CPU.peu.psr_peu_tx_tstfail_b1sds1 |
| 5762 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5763 | |
| 5764 | /* 0in value -var `CPU.psr.serdes_1.ststx1[1] -val `CPU.peu.psr_peu_rdtcip_b1sds1 |
| 5765 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5766 | |
| 5767 | |
| 5768 | |
| 5769 | /* 0in value -var `CPU.psr.serdes_1.ststx2[0] -val `CPU.peu.psr_peu_tx_tstfail_b2sds1 |
| 5770 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5771 | |
| 5772 | /* 0in value -var `CPU.psr.serdes_1.ststx2[1] -val `CPU.peu.psr_peu_rdtcip_b2sds1 |
| 5773 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5774 | |
| 5775 | |
| 5776 | |
| 5777 | /* 0in value -var `CPU.psr.serdes_1.ststx3[0] -val `CPU.peu.psr_peu_tx_tstfail_b3sds1 |
| 5778 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5779 | |
| 5780 | /* 0in value -var `CPU.psr.serdes_1.ststx3[1] -val `CPU.peu.psr_peu_rdtcip_b3sds1 |
| 5781 | -active 1'b1 -clock `CPU.peu.pcl2clk -reset tb_top.reset */ |
| 5782 | |
| 5783 | |
| 5784 | // Hunter Niu Serdes ( esr_0_location_ID_31 is serdes 0) (esr_1_location_ID_29 is serdes 1) |
| 5785 | |
| 5786 | |
| 5787 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgpll[11:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_PLL.this_config_reg[11:0] |
| 5788 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5789 | |
| 5790 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.testcfg[14:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TEST.this_config_reg[14:0] |
| 5791 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5792 | |
| 5793 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgrx0[25:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_0.this_config_reg[25:0] |
| 5794 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5795 | |
| 5796 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgrx1[25:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_1.this_config_reg[25:0] |
| 5797 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5798 | |
| 5799 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgrx2[25:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_2.this_config_reg[25:0] |
| 5800 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5801 | |
| 5802 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgrx3[25:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_3.this_config_reg[25:0] |
| 5803 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5804 | |
| 5805 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgtx0[22:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_0.this_config_reg[22:0] |
| 5806 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5807 | |
| 5808 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgtx1[22:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_1.this_config_reg[22:0] |
| 5809 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5810 | |
| 5811 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgtx2[22:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_2.this_config_reg[22:0] |
| 5812 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5813 | |
| 5814 | /* 0in value -var `CPU.esr.esr_0_location_ID_31.cfgtx3[22:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_3.this_config_reg[22:0] |
| 5815 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_0.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5816 | |
| 5817 | |
| 5818 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgpll[11:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_PLL.this_config_reg[11:0] |
| 5819 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5820 | |
| 5821 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.testcfg[14:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_TEST.this_config_reg[14:0] |
| 5822 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5823 | |
| 5824 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgrx0[25:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_RX_0.this_config_reg[25:0] |
| 5825 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5826 | |
| 5827 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgrx1[25:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_RX_1.this_config_reg[25:0] |
| 5828 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5829 | |
| 5830 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgrx2[25:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_RX_2.this_config_reg[25:0] |
| 5831 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5832 | |
| 5833 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgrx3[25:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_RX_3.this_config_reg[25:0] |
| 5834 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5835 | |
| 5836 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgtx0[22:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_TX_0.this_config_reg[22:0] |
| 5837 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5838 | |
| 5839 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgtx1[22:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_TX_1.this_config_reg[22:0] |
| 5840 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5841 | |
| 5842 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgtx2[22:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_TX_2.this_config_reg[22:0] |
| 5843 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5844 | |
| 5845 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.cfgtx3[22:0] -val `CPU.mac.hedwig.hedwig_1.I_P2REGS.I_P2REGS_CFG_STS_TX_3.this_config_reg[22:0] |
| 5846 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5847 | |
| 5848 | // RX Status Registers |
| 5849 | |
| 5850 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.stsrx0[7:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_0.this_status_reg[7:0] |
| 5851 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5852 | |
| 5853 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.stsrx1[7:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_1.this_status_reg[7:0] |
| 5854 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5855 | |
| 5856 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.stsrx2[7:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_2.this_status_reg[7:0] |
| 5857 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5858 | |
| 5859 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.stsrx3[7:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_RX_3.this_status_reg[7:0] |
| 5860 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5861 | |
| 5862 | // TX Status Registers |
| 5863 | |
| 5864 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.ststx0[1:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_0.this_status_reg[1:0] |
| 5865 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5866 | |
| 5867 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.ststx1[1:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_1.this_status_reg[1:0] |
| 5868 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5869 | |
| 5870 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.ststx2[1:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_2.this_status_reg[1:0] |
| 5871 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5872 | |
| 5873 | /* 0in value -var `CPU.esr.esr_1_location_ID_29.ststx3[1:0] -val `CPU.mac.hedwig.hedwig_0.I_P2REGS.I_P2REGS_CFG_STS_TX_3.this_status_reg[1:0] |
| 5874 | -active 1'b1 -clock `CPU.mac.hedwig.hedwig_1.I_P2REGS.IO_MDCLK -reset tb_top.reset */ |
| 5875 | |
| 5876 | endmodule |