| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2_mcu_intf_chkr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifdef FC_BENCH |
| 36 | `define TB_TOP tb_top |
| 37 | `else |
| 38 | `ifdef CCM |
| 39 | `define TB_TOP tb_top |
| 40 | `else |
| 41 | `define TB_TOP l2sat_top |
| 42 | `endif |
| 43 | `endif |
| 44 | |
| 45 | |
| 46 | module l2_mcu_intf_chkr(); |
| 47 | |
| 48 | reg[1:0] l2t0_data_vld_count; |
| 49 | reg[1:0] l2t1_data_vld_count; |
| 50 | reg[1:0] l2t2_data_vld_count; |
| 51 | reg[1:0] l2t3_data_vld_count; |
| 52 | reg[1:0] l2t4_data_vld_count; |
| 53 | reg[1:0] l2t5_data_vld_count; |
| 54 | reg[1:0] l2t6_data_vld_count; |
| 55 | reg[1:0] l2t7_data_vld_count; |
| 56 | |
| 57 | initial begin |
| 58 | l2t0_data_vld_count = 2'b0; |
| 59 | l2t1_data_vld_count = 2'b0; |
| 60 | l2t2_data_vld_count = 2'b0; |
| 61 | l2t3_data_vld_count = 2'b0; |
| 62 | l2t4_data_vld_count = 2'b0; |
| 63 | l2t5_data_vld_count = 2'b0; |
| 64 | l2t6_data_vld_count = 2'b0; |
| 65 | l2t7_data_vld_count = 2'b0; |
| 66 | end |
| 67 | |
| 68 | |
| 69 | always@ (posedge `TB_TOP.cpu.l2clk) |
| 70 | begin |
| 71 | if(`TB_TOP.cpu.l2t0.mcu_l2t_data_vld_r0) |
| 72 | l2t0_data_vld_count = (l2t0_data_vld_count + 1)%4; |
| 73 | if(`TB_TOP.cpu.l2t1.mcu_l2t_data_vld_r0) |
| 74 | l2t1_data_vld_count = (l2t1_data_vld_count + 1)%4; |
| 75 | if(`TB_TOP.cpu.l2t2.mcu_l2t_data_vld_r0) |
| 76 | l2t2_data_vld_count = (l2t2_data_vld_count + 1)%4; |
| 77 | if(`TB_TOP.cpu.l2t3.mcu_l2t_data_vld_r0) |
| 78 | l2t3_data_vld_count = (l2t3_data_vld_count + 1)%4; |
| 79 | if(`TB_TOP.cpu.l2t4.mcu_l2t_data_vld_r0) |
| 80 | l2t4_data_vld_count = (l2t4_data_vld_count + 1)%4; |
| 81 | if(`TB_TOP.cpu.l2t5.mcu_l2t_data_vld_r0) |
| 82 | l2t5_data_vld_count = (l2t5_data_vld_count + 1)%4; |
| 83 | if(`TB_TOP.cpu.l2t6.mcu_l2t_data_vld_r0) |
| 84 | l2t6_data_vld_count = (l2t6_data_vld_count + 1)%4; |
| 85 | if(`TB_TOP.cpu.l2t7.mcu_l2t_data_vld_r0) |
| 86 | l2t7_data_vld_count = (l2t7_data_vld_count + 1)%4; |
| 87 | end |
| 88 | |
| 89 | |
| 90 | |
| 91 | // 0in set_clock -default l2clk -module cpu |
| 92 | |
| 93 | |
| 94 | // This directive ensures that each req is followed by an ack |
| 95 | /* 0in req_ack -req l2t_mcu_rd_req -ack mcu_l2t_rd_ack |
| 96 | -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 97 | */ |
| 98 | |
| 99 | /* 0in req_ack -req l2t_mcu_wr_req -ack mcu_l2t_wr_ack |
| 100 | -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 101 | */ |
| 102 | |
| 103 | // This directive ensures that there is at most 8 outstanding request ids |
| 104 | // and each ack matches with the corresponding req. |
| 105 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t0.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t0.l2t_mcu_rd_req_id |
| 106 | -ret (`TB_TOP.cpu.l2t0.mcu_l2t_data_vld_r0 & (l2t0_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t0.mcu_l2t_rd_req_id_r0 |
| 107 | -max_ids 8 |
| 108 | -max_count_per_id 1 |
| 109 | -known_ids on |
| 110 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 111 | */ |
| 112 | |
| 113 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t1.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t1.l2t_mcu_rd_req_id |
| 114 | -ret (`TB_TOP.cpu.l2t1.mcu_l2t_data_vld_r0 & (l2t1_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t1.mcu_l2t_rd_req_id_r0 |
| 115 | -max_ids 8 |
| 116 | -max_count_per_id 1 |
| 117 | -known_ids on |
| 118 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 119 | */ |
| 120 | |
| 121 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t2.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t2.l2t_mcu_rd_req_id |
| 122 | -ret (`TB_TOP.cpu.l2t2.mcu_l2t_data_vld_r0 & (l2t2_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t2.mcu_l2t_rd_req_id_r0 |
| 123 | -max_ids 8 |
| 124 | -max_count_per_id 1 |
| 125 | -known_ids on |
| 126 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 127 | */ |
| 128 | |
| 129 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t3.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t3.l2t_mcu_rd_req_id |
| 130 | -ret (`TB_TOP.cpu.l2t3.mcu_l2t_data_vld_r0 & (l2t3_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t3.mcu_l2t_rd_req_id_r0 |
| 131 | -max_ids 8 |
| 132 | -max_count_per_id 1 |
| 133 | -known_ids on |
| 134 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 135 | */ |
| 136 | |
| 137 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t4.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t4.l2t_mcu_rd_req_id |
| 138 | -ret (`TB_TOP.cpu.l2t4.mcu_l2t_data_vld_r0 & (l2t4_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t4.mcu_l2t_rd_req_id_r0 |
| 139 | -max_ids 8 |
| 140 | -max_count_per_id 1 |
| 141 | -known_ids on |
| 142 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 143 | */ |
| 144 | |
| 145 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t5.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t5.l2t_mcu_rd_req_id |
| 146 | -ret (`TB_TOP.cpu.l2t5.mcu_l2t_data_vld_r0 & (l2t5_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t5.mcu_l2t_rd_req_id_r0 |
| 147 | -max_ids 8 |
| 148 | -max_count_per_id 1 |
| 149 | -known_ids on |
| 150 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 151 | */ |
| 152 | |
| 153 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t6.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t6.l2t_mcu_rd_req_id |
| 154 | -ret (`TB_TOP.cpu.l2t6.mcu_l2t_data_vld_r0 & (l2t6_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t6.mcu_l2t_rd_req_id_r0 |
| 155 | -max_ids 8 |
| 156 | -max_count_per_id 1 |
| 157 | -known_ids on |
| 158 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 159 | */ |
| 160 | |
| 161 | /* 0in outstanding_id -req `TB_TOP.cpu.l2t7.l2t_mcu_rd_req -req_id `TB_TOP.cpu.l2t7.l2t_mcu_rd_req_id |
| 162 | -ret (`TB_TOP.cpu.l2t7.mcu_l2t_data_vld_r0 & (l2t7_data_vld_count == 3)) -ret_id `TB_TOP.cpu.l2t7.mcu_l2t_rd_req_id_r0 |
| 163 | -max_ids 8 |
| 164 | -max_count_per_id 1 |
| 165 | -known_ids on |
| 166 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 167 | */ |
| 168 | |
| 169 | // This directive ensures that the write data vld signals is asserted 6 clock |
| 170 | // cycles after receiving the write ack. |
| 171 | |
| 172 | /*0in assert_follower -leader `TB_TOP.cpu.mcu0_l2t0_wr_ack -follower `TB_TOP.cpu.l2b0.evict_l2b_mcu_data_vld_r5 -min 6 -max 6 |
| 173 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 174 | */ |
| 175 | |
| 176 | /*0in assert_follower -leader `TB_TOP.cpu.mcu0_l2t1_wr_ack -follower `TB_TOP.cpu.l2b1.evict_l2b_mcu_data_vld_r5 -min 8 -max 8 |
| 177 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 178 | */ |
| 179 | |
| 180 | /*0in assert_follower -leader `TB_TOP.cpu.mcu1_l2t2_wr_ack -follower `TB_TOP.cpu.l2b2.evict_l2b_mcu_data_vld_r5 -min 6 -max 6 |
| 181 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 182 | */ |
| 183 | |
| 184 | /*0in assert_follower -leader `TB_TOP.cpu.mcu1_l2t3_wr_ack -follower `TB_TOP.cpu.l2b3.evict_l2b_mcu_data_vld_r5 -min 8 -max 8 |
| 185 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 186 | */ |
| 187 | |
| 188 | /*0in assert_follower -leader `TB_TOP.cpu.mcu2_l2t4_wr_ack -follower `TB_TOP.cpu.l2b4.evict_l2b_mcu_data_vld_r5 -min 6 -max 6 |
| 189 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 190 | */ |
| 191 | |
| 192 | /*0in assert_follower -leader `TB_TOP.cpu.mcu2_l2t5_wr_ack -follower `TB_TOP.cpu.l2b5.evict_l2b_mcu_data_vld_r5 -min 8 -max 8 |
| 193 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 194 | */ |
| 195 | |
| 196 | /*0in assert_follower -leader `TB_TOP.cpu.mcu3_l2t6_wr_ack -follower `TB_TOP.cpu.l2b6.evict_l2b_mcu_data_vld_r5 -min 6 -max 6 |
| 197 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 198 | */ |
| 199 | |
| 200 | /*0in assert_follower -leader `TB_TOP.cpu.mcu3_l2t7_wr_ack -follower `TB_TOP.cpu.l2b7.evict_l2b_mcu_data_vld_r5 -min 8 -max 8 |
| 201 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 202 | */ |
| 203 | |
| 204 | |
| 205 | // This direcitive ensures that the write data is sent in 8 cycles. |
| 206 | /*0in assert_follower -leader evict_l2b_mcu_data_vld_r5 -follower ~evict_l2b_mcu_data_vld_r5 |
| 207 | -min 8 -max 8 |
| 208 | -module l2b -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 209 | */ |
| 210 | |
| 211 | //Check that the control signals are known and driven all the time |
| 212 | |
| 213 | /* 0in known_driven -var l2t_mcu_rd_req -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 214 | */ |
| 215 | /* 0in known_driven -var l2t_mcu_wr_req -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 216 | */ |
| 217 | /* 0in known_driven -var mcu_l2t_rd_ack -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 218 | */ |
| 219 | /* 0in known_driven -var mcu_l2t_wr_ack -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 220 | */ |
| 221 | /* 0in known_driven -var evict_l2b_mcu_data_vld_r5 -module l2b -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 222 | */ |
| 223 | /* 0in known_driven -var mcu_l2t_data_vld_r0 -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 224 | */ |
| 225 | |
| 226 | // This directive ensures that the address is asserted during the requests |
| 227 | /* 0in known_driven -var {l2t_mcu_addr, l2t_mcu_addr_5} |
| 228 | -active (l2t_mcu_rd_req | l2t_mcu_wr_req) |
| 229 | -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 230 | */ |
| 231 | |
| 232 | // This directive ensures that the req_id is asserted during a read request |
| 233 | /* 0in known_driven -var l2t_mcu_rd_req_id |
| 234 | -active l2t_mcu_rd_req |
| 235 | -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 236 | */ |
| 237 | |
| 238 | // This directive ensures that the chunk_id and req_id is asserted during the |
| 239 | // read data return cycles. |
| 240 | /* 0in known_driven -var {mcu_l2t_chunk_id_r0, mcu_l2t_rd_req_id_r0} |
| 241 | -active mcu_l2t_data_vld_r0 |
| 242 | -module l2t -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 243 | */ |
| 244 | |
| 245 | // This directive ensures that the read data and the corresponding ecc are |
| 246 | // asserted 3 cycles after the valid signal. |
| 247 | |
| 248 | /* 0in known_driven -var {`TB_TOP.cpu.l2b0.mcu_l2b_data_r2, `TB_TOP.cpu.l2b0.mcu_l2b_ecc_r2} |
| 249 | -active $0in_delay(`TB_TOP.cpu.l2t0.mcu_l2t_data_vld_r0, 3) |
| 250 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 251 | */ |
| 252 | |
| 253 | /* 0in known_driven -var {`TB_TOP.cpu.l2b1.mcu_l2b_data_r2, `TB_TOP.cpu.l2b1.mcu_l2b_ecc_r2} |
| 254 | -active $0in_delay(`TB_TOP.cpu.l2t1.mcu_l2t_data_vld_r0, 3) |
| 255 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 256 | */ |
| 257 | |
| 258 | /* 0in known_driven -var {`TB_TOP.cpu.l2b2.mcu_l2b_data_r2, `TB_TOP.cpu.l2b2.mcu_l2b_ecc_r2} |
| 259 | -active $0in_delay(`TB_TOP.cpu.l2t2.mcu_l2t_data_vld_r0, 3) |
| 260 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 261 | */ |
| 262 | |
| 263 | /* 0in known_driven -var {`TB_TOP.cpu.l2b3.mcu_l2b_data_r2, `TB_TOP.cpu.l2b3.mcu_l2b_ecc_r2} |
| 264 | -active $0in_delay(`TB_TOP.cpu.l2t3.mcu_l2t_data_vld_r0, 3) |
| 265 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 266 | */ |
| 267 | |
| 268 | /* 0in known_driven -var {`TB_TOP.cpu.l2b4.mcu_l2b_data_r2, `TB_TOP.cpu.l2b4.mcu_l2b_ecc_r2} |
| 269 | -active $0in_delay(`TB_TOP.cpu.l2t4.mcu_l2t_data_vld_r0, 3) |
| 270 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 271 | */ |
| 272 | |
| 273 | /* 0in known_driven -var {`TB_TOP.cpu.l2b5.mcu_l2b_data_r2, `TB_TOP.cpu.l2b5.mcu_l2b_ecc_r2} |
| 274 | -active $0in_delay(`TB_TOP.cpu.l2t5.mcu_l2t_data_vld_r0, 3) |
| 275 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 276 | */ |
| 277 | |
| 278 | /* 0in known_driven -var {`TB_TOP.cpu.l2b6.mcu_l2b_data_r2, `TB_TOP.cpu.l2b6.mcu_l2b_ecc_r2} |
| 279 | -active $0in_delay(`TB_TOP.cpu.l2t6.mcu_l2t_data_vld_r0, 3) |
| 280 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 281 | */ |
| 282 | |
| 283 | /* 0in known_driven -var {`TB_TOP.cpu.l2b7.mcu_l2b_data_r2, `TB_TOP.cpu.l2b7.mcu_l2b_ecc_r2} |
| 284 | -active $0in_delay(`TB_TOP.cpu.l2t7.mcu_l2t_data_vld_r0, 3) |
| 285 | -clock `TB_TOP.cpu.l2clk -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 286 | */ |
| 287 | |
| 288 | // This directive ensures that the write data and write data ecc are asserted |
| 289 | // while the valid signal is asserted. |
| 290 | /* 0in known_driven -var {evict_l2b_mcu_wr_data_r5, l2b_evict_l2b_mcu_data_mecc_r5} |
| 291 | -active evict_l2b_mcu_data_vld_r5 |
| 292 | -module l2b -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 293 | */ |
| 294 | |
| 295 | endmodule //l2_mcu_intf_chkr |
| 296 | |
| 297 | |