| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2_siu_chkr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define DMU 1'b1 |
| 36 | `define NIU 1'b0 |
| 37 | |
| 38 | //Inbound |
| 39 | `define DMU_RDD_ord_npt 7'b0101001 |
| 40 | `define DMU_WR8_ord_pst 7'b0111010 |
| 41 | `define DMU_WRI_ord_pst 7'b0111100 |
| 42 | `define NIU_RDD_ord_npt 7'b0100001 |
| 43 | `define NIU_RDD_byp_npt 7'b0000001 |
| 44 | `define NIU_WRI_ord_npt 7'b0100100 |
| 45 | `define NIU_WRI_byp_npt 7'b0000100 |
| 46 | `define NIU_WRI_ord_pst 7'b0110100 |
| 47 | `define NIU_WRI_byp_pst 7'b0010100 |
| 48 | `define TCU_WR 7'b1000001 |
| 49 | `define TCU_RD 7'b1000010 |
| 50 | |
| 51 | `define SII_L2_WRI 3'b100 |
| 52 | `define SII_L2_WR8 3'b010 |
| 53 | `define SII_L2_RDD 3'b001 |
| 54 | |
| 55 | `define SII_L2_0_O sii_l2t0_req[30] |
| 56 | `define SII_L2_0_P sii_l2t0_req[29] |
| 57 | `define SII_L2_0_S sii_l2t0_req[27] |
| 58 | |
| 59 | `define SII_L2_0_VLD sii_l2t0_req_vld |
| 60 | |
| 61 | `define SII_L2_0_TT sii_l2t0_req[26:24] |
| 62 | |
| 63 | `define SII_L2_0_CMD {sii_l2t0_req[31:29], sii_l2t0_req[27:24]} |
| 64 | |
| 65 | `define PA_LOW6_0 sii_l2t0_req[5:0] |
| 66 | `define PA_LOW3_0 sii_l2t0_req[2:0] |
| 67 | |
| 68 | `define BYTE_MASK_0 sii_l2t0_req[15:8] |
| 69 | `define SII_L2_1_O sii_l2t1_req[30] |
| 70 | `define SII_L2_1_P sii_l2t1_req[29] |
| 71 | `define SII_L2_1_S sii_l2t1_req[27] |
| 72 | |
| 73 | `define SII_L2_1_VLD sii_l2t1_req_vld |
| 74 | |
| 75 | `define SII_L2_1_TT sii_l2t1_req[26:24] |
| 76 | |
| 77 | `define SII_L2_1_CMD {sii_l2t1_req[31:29], sii_l2t1_req[27:24]} |
| 78 | |
| 79 | `define PA_LOW6_1 sii_l2t1_req[5:0] |
| 80 | `define PA_LOW3_1 sii_l2t1_req[2:0] |
| 81 | |
| 82 | `define BYTE_MASK_1 sii_l2t1_req[15:8] |
| 83 | `define SII_L2_2_O sii_l2t2_req[30] |
| 84 | `define SII_L2_2_P sii_l2t2_req[29] |
| 85 | `define SII_L2_2_S sii_l2t2_req[27] |
| 86 | |
| 87 | `define SII_L2_2_VLD sii_l2t2_req_vld |
| 88 | |
| 89 | `define SII_L2_2_TT sii_l2t2_req[26:24] |
| 90 | |
| 91 | `define SII_L2_2_CMD {sii_l2t2_req[31:29], sii_l2t2_req[27:24]} |
| 92 | |
| 93 | `define PA_LOW6_2 sii_l2t2_req[5:0] |
| 94 | `define PA_LOW3_2 sii_l2t2_req[2:0] |
| 95 | |
| 96 | `define BYTE_MASK_2 sii_l2t2_req[15:8] |
| 97 | `define SII_L2_3_O sii_l2t3_req[30] |
| 98 | `define SII_L2_3_P sii_l2t3_req[29] |
| 99 | `define SII_L2_3_S sii_l2t3_req[27] |
| 100 | |
| 101 | `define SII_L2_3_VLD sii_l2t3_req_vld |
| 102 | |
| 103 | `define SII_L2_3_TT sii_l2t3_req[26:24] |
| 104 | |
| 105 | `define SII_L2_3_CMD {sii_l2t3_req[31:29], sii_l2t3_req[27:24]} |
| 106 | |
| 107 | `define PA_LOW6_3 sii_l2t3_req[5:0] |
| 108 | `define PA_LOW3_3 sii_l2t3_req[2:0] |
| 109 | |
| 110 | `define BYTE_MASK_3 sii_l2t3_req[15:8] |
| 111 | `define SII_L2_4_O sii_l2t4_req[30] |
| 112 | `define SII_L2_4_P sii_l2t4_req[29] |
| 113 | `define SII_L2_4_S sii_l2t4_req[27] |
| 114 | |
| 115 | `define SII_L2_4_VLD sii_l2t4_req_vld |
| 116 | |
| 117 | `define SII_L2_4_TT sii_l2t4_req[26:24] |
| 118 | |
| 119 | `define SII_L2_4_CMD {sii_l2t4_req[31:29], sii_l2t4_req[27:24]} |
| 120 | |
| 121 | `define PA_LOW6_4 sii_l2t4_req[5:0] |
| 122 | `define PA_LOW3_4 sii_l2t4_req[2:0] |
| 123 | |
| 124 | `define BYTE_MASK_4 sii_l2t4_req[15:8] |
| 125 | `define SII_L2_5_O sii_l2t5_req[30] |
| 126 | `define SII_L2_5_P sii_l2t5_req[29] |
| 127 | `define SII_L2_5_S sii_l2t5_req[27] |
| 128 | |
| 129 | `define SII_L2_5_VLD sii_l2t5_req_vld |
| 130 | |
| 131 | `define SII_L2_5_TT sii_l2t5_req[26:24] |
| 132 | |
| 133 | `define SII_L2_5_CMD {sii_l2t5_req[31:29], sii_l2t5_req[27:24]} |
| 134 | |
| 135 | `define PA_LOW6_5 sii_l2t5_req[5:0] |
| 136 | `define PA_LOW3_5 sii_l2t5_req[2:0] |
| 137 | |
| 138 | `define BYTE_MASK_5 sii_l2t5_req[15:8] |
| 139 | `define SII_L2_6_O sii_l2t6_req[30] |
| 140 | `define SII_L2_6_P sii_l2t6_req[29] |
| 141 | `define SII_L2_6_S sii_l2t6_req[27] |
| 142 | |
| 143 | `define SII_L2_6_VLD sii_l2t6_req_vld |
| 144 | |
| 145 | `define SII_L2_6_TT sii_l2t6_req[26:24] |
| 146 | |
| 147 | `define SII_L2_6_CMD {sii_l2t6_req[31:29], sii_l2t6_req[27:24]} |
| 148 | |
| 149 | `define PA_LOW6_6 sii_l2t6_req[5:0] |
| 150 | `define PA_LOW3_6 sii_l2t6_req[2:0] |
| 151 | |
| 152 | `define BYTE_MASK_6 sii_l2t6_req[15:8] |
| 153 | `define SII_L2_7_O sii_l2t7_req[30] |
| 154 | `define SII_L2_7_P sii_l2t7_req[29] |
| 155 | `define SII_L2_7_S sii_l2t7_req[27] |
| 156 | |
| 157 | `define SII_L2_7_VLD sii_l2t7_req_vld |
| 158 | |
| 159 | `define SII_L2_7_TT sii_l2t7_req[26:24] |
| 160 | |
| 161 | `define SII_L2_7_CMD {sii_l2t7_req[31:29], sii_l2t7_req[27:24]} |
| 162 | |
| 163 | `define PA_LOW6_7 sii_l2t7_req[5:0] |
| 164 | `define PA_LOW3_7 sii_l2t7_req[2:0] |
| 165 | |
| 166 | `define BYTE_MASK_7 sii_l2t7_req[15:8] |
| 167 | |
| 168 | |
| 169 | |
| 170 | //Outbound |
| 171 | `define L2_DMU_RDD_ord_npt 7'b1010001 |
| 172 | `define L2_DMU_WR8_ord_pst 7'b1110000 |
| 173 | `define L2_DMU_WRI_pst_ord 7'b1110000 |
| 174 | |
| 175 | `define L2_NIU_RDD_ord_npt 7'b1000001 |
| 176 | `define L2_NIU_RDD_byp_npt 7'b0000001 |
| 177 | `define L2_NIU_WRI_ord_npt 7'b1000000 |
| 178 | `define L2_NIU_WRI_byp_npt 7'b0000000 |
| 179 | `define L2_NIU_WRI_ord_pst 7'b1100000 |
| 180 | `define L2_NIU_WRI_byp_pst 7'b0100000 |
| 181 | |
| 182 | |
| 183 | `define L2_SIO_RDD 1'b1 |
| 184 | `define L2_SIO_WRI 1'b0 |
| 185 | |
| 186 | |
| 187 | `define L2_0_SIO_O l2b0_sio_data[23] |
| 188 | `define L2_0_SIO_P l2b0_sio_data[22] |
| 189 | `define L2_0_SIO_S l2b0_sio_data[20] |
| 190 | |
| 191 | `define L2_0_SIO_VLD l2b0_sio_ctag_vld |
| 192 | `define L2_0_SIO_TT l2b0_sio_data[16] |
| 193 | |
| 194 | `define CBA_0 l2b0_sio_data[19:17] |
| 195 | |
| 196 | `define L2_0_SIO_CMD {l2b0_sio_data[23:22], l2b0_sio_data[20:16]} |
| 197 | `define L2_1_SIO_O l2b1_sio_data[23] |
| 198 | `define L2_1_SIO_P l2b1_sio_data[22] |
| 199 | `define L2_1_SIO_S l2b1_sio_data[20] |
| 200 | |
| 201 | `define L2_1_SIO_VLD l2b1_sio_ctag_vld |
| 202 | `define L2_1_SIO_TT l2b1_sio_data[16] |
| 203 | |
| 204 | `define CBA_1 l2b1_sio_data[19:17] |
| 205 | |
| 206 | `define L2_1_SIO_CMD {l2b1_sio_data[23:22], l2b1_sio_data[20:16]} |
| 207 | `define L2_2_SIO_O l2b2_sio_data[23] |
| 208 | `define L2_2_SIO_P l2b2_sio_data[22] |
| 209 | `define L2_2_SIO_S l2b2_sio_data[20] |
| 210 | |
| 211 | `define L2_2_SIO_VLD l2b2_sio_ctag_vld |
| 212 | `define L2_2_SIO_TT l2b2_sio_data[16] |
| 213 | |
| 214 | `define CBA_2 l2b2_sio_data[19:17] |
| 215 | |
| 216 | `define L2_2_SIO_CMD {l2b2_sio_data[23:22], l2b2_sio_data[20:16]} |
| 217 | `define L2_3_SIO_O l2b3_sio_data[23] |
| 218 | `define L2_3_SIO_P l2b3_sio_data[22] |
| 219 | `define L2_3_SIO_S l2b3_sio_data[20] |
| 220 | |
| 221 | `define L2_3_SIO_VLD l2b3_sio_ctag_vld |
| 222 | `define L2_3_SIO_TT l2b3_sio_data[16] |
| 223 | |
| 224 | `define CBA_3 l2b3_sio_data[19:17] |
| 225 | |
| 226 | `define L2_3_SIO_CMD {l2b3_sio_data[23:22], l2b3_sio_data[20:16]} |
| 227 | `define L2_4_SIO_O l2b4_sio_data[23] |
| 228 | `define L2_4_SIO_P l2b4_sio_data[22] |
| 229 | `define L2_4_SIO_S l2b4_sio_data[20] |
| 230 | |
| 231 | `define L2_4_SIO_VLD l2b4_sio_ctag_vld |
| 232 | `define L2_4_SIO_TT l2b4_sio_data[16] |
| 233 | |
| 234 | `define CBA_4 l2b4_sio_data[19:17] |
| 235 | |
| 236 | `define L2_4_SIO_CMD {l2b4_sio_data[23:22], l2b4_sio_data[20:16]} |
| 237 | `define L2_5_SIO_O l2b5_sio_data[23] |
| 238 | `define L2_5_SIO_P l2b5_sio_data[22] |
| 239 | `define L2_5_SIO_S l2b5_sio_data[20] |
| 240 | |
| 241 | `define L2_5_SIO_VLD l2b5_sio_ctag_vld |
| 242 | `define L2_5_SIO_TT l2b5_sio_data[16] |
| 243 | |
| 244 | `define CBA_5 l2b5_sio_data[19:17] |
| 245 | |
| 246 | `define L2_5_SIO_CMD {l2b5_sio_data[23:22], l2b5_sio_data[20:16]} |
| 247 | `define L2_6_SIO_O l2b6_sio_data[23] |
| 248 | `define L2_6_SIO_P l2b6_sio_data[22] |
| 249 | `define L2_6_SIO_S l2b6_sio_data[20] |
| 250 | |
| 251 | `define L2_6_SIO_VLD l2b6_sio_ctag_vld |
| 252 | `define L2_6_SIO_TT l2b6_sio_data[16] |
| 253 | |
| 254 | `define CBA_6 l2b6_sio_data[19:17] |
| 255 | |
| 256 | `define L2_6_SIO_CMD {l2b6_sio_data[23:22], l2b6_sio_data[20:16]} |
| 257 | `define L2_7_SIO_O l2b7_sio_data[23] |
| 258 | `define L2_7_SIO_P l2b7_sio_data[22] |
| 259 | `define L2_7_SIO_S l2b7_sio_data[20] |
| 260 | |
| 261 | `define L2_7_SIO_VLD l2b7_sio_ctag_vld |
| 262 | `define L2_7_SIO_TT l2b7_sio_data[16] |
| 263 | |
| 264 | `define CBA_7 l2b7_sio_data[19:17] |
| 265 | |
| 266 | `define L2_7_SIO_CMD {l2b7_sio_data[23:22], l2b7_sio_data[20:16]} |
| 267 | |
| 268 | |
| 269 | |
| 270 | module sii_l2_chkr(); |
| 271 | |
| 272 | |
| 273 | `ifdef X_GUARD |
| 274 | `endif |
| 275 | |
| 276 | |
| 277 | reg no_iqdq_chk; |
| 278 | initial begin // { |
| 279 | `ifdef FC_BENCH |
| 280 | @(posedge tb_top.cpu.sii.l2clk) ; |
| 281 | `else |
| 282 | @(posedge siu_top.cpu.sii.l2clk) ; |
| 283 | `endif |
| 284 | if ($test$plusargs("siul2_iqdq_chk_off")) |
| 285 | no_iqdq_chk <= 1; |
| 286 | else |
| 287 | no_iqdq_chk <= 0; |
| 288 | end //} |
| 289 | |
| 290 | // 0in disable_checker -name *req_assert* no_iqdq_chk |
| 291 | |
| 292 | |
| 293 | /* SII to L2 transactions */ |
| 294 | |
| 295 | /* 0in value -var `SII_L2_0_CMD -casex |
| 296 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 297 | -active `SII_L2_0_VLD |
| 298 | -clock l2clk |
| 299 | -module cpu |
| 300 | -name sii_l2_0_hdr_cmd_vld |
| 301 | -message "Bad value for sii_l2_0 header" |
| 302 | */ |
| 303 | /* 0in value -var `SII_L2_1_CMD -casex |
| 304 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 305 | -active `SII_L2_1_VLD |
| 306 | -clock l2clk |
| 307 | -module cpu |
| 308 | -name sii_l2_1_hdr_cmd_vld |
| 309 | -message "Bad value for sii_l2_1 header" |
| 310 | */ |
| 311 | /* 0in value -var `SII_L2_2_CMD -casex |
| 312 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 313 | -active `SII_L2_2_VLD |
| 314 | -clock l2clk |
| 315 | -module cpu |
| 316 | -name sii_l2_2_hdr_cmd_vld |
| 317 | -message "Bad value for sii_l2_2 header" |
| 318 | */ |
| 319 | /* 0in value -var `SII_L2_3_CMD -casex |
| 320 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 321 | -active `SII_L2_3_VLD |
| 322 | -clock l2clk |
| 323 | -module cpu |
| 324 | -name sii_l2_3_hdr_cmd_vld |
| 325 | -message "Bad value for sii_l2_3 header" |
| 326 | */ |
| 327 | /* 0in value -var `SII_L2_4_CMD -casex |
| 328 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 329 | -active `SII_L2_4_VLD |
| 330 | -clock l2clk |
| 331 | -module cpu |
| 332 | -name sii_l2_4_hdr_cmd_vld |
| 333 | -message "Bad value for sii_l2_4 header" |
| 334 | */ |
| 335 | /* 0in value -var `SII_L2_5_CMD -casex |
| 336 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 337 | -active `SII_L2_5_VLD |
| 338 | -clock l2clk |
| 339 | -module cpu |
| 340 | -name sii_l2_5_hdr_cmd_vld |
| 341 | -message "Bad value for sii_l2_5 header" |
| 342 | */ |
| 343 | /* 0in value -var `SII_L2_6_CMD -casex |
| 344 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 345 | -active `SII_L2_6_VLD |
| 346 | -clock l2clk |
| 347 | -module cpu |
| 348 | -name sii_l2_6_hdr_cmd_vld |
| 349 | -message "Bad value for sii_l2_6 header" |
| 350 | */ |
| 351 | /* 0in value -var `SII_L2_7_CMD -casex |
| 352 | -val `DMU_RDD_ord_npt `DMU_WR8_ord_pst `DMU_WRI_ord_pst `NIU_RDD_ord_npt `NIU_RDD_byp_npt `NIU_WRI_ord_npt `NIU_WRI_byp_npt `NIU_WRI_ord_pst `NIU_WRI_byp_pst `TCU_RD `TCU_WR |
| 353 | -active `SII_L2_7_VLD |
| 354 | -clock l2clk |
| 355 | -module cpu |
| 356 | -name sii_l2_7_hdr_cmd_vld |
| 357 | -message "Bad value for sii_l2_7 header" |
| 358 | */ |
| 359 | |
| 360 | |
| 361 | /*************************** |
| 362 | WRI |
| 363 | 1. If from DMU O=1; P=1 |
| 364 | 2. PA[5:0] are zeros |
| 365 | 3. |
| 366 | ***************************/ |
| 367 | // 1. |
| 368 | /* 0in value -var ({`SII_L2_0_O,`SII_L2_0_P}) |
| 369 | -val 2'b11 |
| 370 | -active (`SII_L2_0_VLD & (`SII_L2_0_TT==`SII_L2_WRI) & (`SII_L2_0_S==`DMU)) |
| 371 | -module cpu |
| 372 | -clock l2clk |
| 373 | -name sii_l2_0_WRI_P_O_chk |
| 374 | */ |
| 375 | /* 0in value -var ({`SII_L2_1_O,`SII_L2_1_P}) |
| 376 | -val 2'b11 |
| 377 | -active (`SII_L2_1_VLD & (`SII_L2_1_TT==`SII_L2_WRI) & (`SII_L2_1_S==`DMU)) |
| 378 | -module cpu |
| 379 | -clock l2clk |
| 380 | -name sii_l2_1_WRI_P_O_chk |
| 381 | */ |
| 382 | /* 0in value -var ({`SII_L2_2_O,`SII_L2_2_P}) |
| 383 | -val 2'b11 |
| 384 | -active (`SII_L2_2_VLD & (`SII_L2_2_TT==`SII_L2_WRI) & (`SII_L2_2_S==`DMU)) |
| 385 | -module cpu |
| 386 | -clock l2clk |
| 387 | -name sii_l2_2_WRI_P_O_chk |
| 388 | */ |
| 389 | /* 0in value -var ({`SII_L2_3_O,`SII_L2_3_P}) |
| 390 | -val 2'b11 |
| 391 | -active (`SII_L2_3_VLD & (`SII_L2_3_TT==`SII_L2_WRI) & (`SII_L2_3_S==`DMU)) |
| 392 | -module cpu |
| 393 | -clock l2clk |
| 394 | -name sii_l2_3_WRI_P_O_chk |
| 395 | */ |
| 396 | /* 0in value -var ({`SII_L2_4_O,`SII_L2_4_P}) |
| 397 | -val 2'b11 |
| 398 | -active (`SII_L2_4_VLD & (`SII_L2_4_TT==`SII_L2_WRI) & (`SII_L2_4_S==`DMU)) |
| 399 | -module cpu |
| 400 | -clock l2clk |
| 401 | -name sii_l2_4_WRI_P_O_chk |
| 402 | */ |
| 403 | /* 0in value -var ({`SII_L2_5_O,`SII_L2_5_P}) |
| 404 | -val 2'b11 |
| 405 | -active (`SII_L2_5_VLD & (`SII_L2_5_TT==`SII_L2_WRI) & (`SII_L2_5_S==`DMU)) |
| 406 | -module cpu |
| 407 | -clock l2clk |
| 408 | -name sii_l2_5_WRI_P_O_chk |
| 409 | */ |
| 410 | /* 0in value -var ({`SII_L2_6_O,`SII_L2_6_P}) |
| 411 | -val 2'b11 |
| 412 | -active (`SII_L2_6_VLD & (`SII_L2_6_TT==`SII_L2_WRI) & (`SII_L2_6_S==`DMU)) |
| 413 | -module cpu |
| 414 | -clock l2clk |
| 415 | -name sii_l2_6_WRI_P_O_chk |
| 416 | */ |
| 417 | /* 0in value -var ({`SII_L2_7_O,`SII_L2_7_P}) |
| 418 | -val 2'b11 |
| 419 | -active (`SII_L2_7_VLD & (`SII_L2_7_TT==`SII_L2_WRI) & (`SII_L2_7_S==`DMU)) |
| 420 | -module cpu |
| 421 | -clock l2clk |
| 422 | -name sii_l2_7_WRI_P_O_chk |
| 423 | */ |
| 424 | |
| 425 | // 2. |
| 426 | /* 0in value -var `PA_LOW6_0 |
| 427 | -val 6'b000000 |
| 428 | -active $0in_delay((`SII_L2_0_VLD & (`SII_L2_0_CMD==`SII_L2_WRI)), 1) |
| 429 | -module cpu |
| 430 | -clock l2clk |
| 431 | -name sii_l2_0_WRI_PA_align_chk |
| 432 | */ |
| 433 | /* 0in value -var `PA_LOW6_1 |
| 434 | -val 6'b000000 |
| 435 | -active $0in_delay((`SII_L2_1_VLD & (`SII_L2_1_CMD==`SII_L2_WRI)), 1) |
| 436 | -module cpu |
| 437 | -clock l2clk |
| 438 | -name sii_l2_1_WRI_PA_align_chk |
| 439 | */ |
| 440 | /* 0in value -var `PA_LOW6_2 |
| 441 | -val 6'b000000 |
| 442 | -active $0in_delay((`SII_L2_2_VLD & (`SII_L2_2_CMD==`SII_L2_WRI)), 1) |
| 443 | -module cpu |
| 444 | -clock l2clk |
| 445 | -name sii_l2_2_WRI_PA_align_chk |
| 446 | */ |
| 447 | /* 0in value -var `PA_LOW6_3 |
| 448 | -val 6'b000000 |
| 449 | -active $0in_delay((`SII_L2_3_VLD & (`SII_L2_3_CMD==`SII_L2_WRI)), 1) |
| 450 | -module cpu |
| 451 | -clock l2clk |
| 452 | -name sii_l2_3_WRI_PA_align_chk |
| 453 | */ |
| 454 | /* 0in value -var `PA_LOW6_4 |
| 455 | -val 6'b000000 |
| 456 | -active $0in_delay((`SII_L2_4_VLD & (`SII_L2_4_CMD==`SII_L2_WRI)), 1) |
| 457 | -module cpu |
| 458 | -clock l2clk |
| 459 | -name sii_l2_4_WRI_PA_align_chk |
| 460 | */ |
| 461 | /* 0in value -var `PA_LOW6_5 |
| 462 | -val 6'b000000 |
| 463 | -active $0in_delay((`SII_L2_5_VLD & (`SII_L2_5_CMD==`SII_L2_WRI)), 1) |
| 464 | -module cpu |
| 465 | -clock l2clk |
| 466 | -name sii_l2_5_WRI_PA_align_chk |
| 467 | */ |
| 468 | /* 0in value -var `PA_LOW6_6 |
| 469 | -val 6'b000000 |
| 470 | -active $0in_delay((`SII_L2_6_VLD & (`SII_L2_6_CMD==`SII_L2_WRI)), 1) |
| 471 | -module cpu |
| 472 | -clock l2clk |
| 473 | -name sii_l2_6_WRI_PA_align_chk |
| 474 | */ |
| 475 | /* 0in value -var `PA_LOW6_7 |
| 476 | -val 6'b000000 |
| 477 | -active $0in_delay((`SII_L2_7_VLD & (`SII_L2_7_CMD==`SII_L2_WRI)), 1) |
| 478 | -module cpu |
| 479 | -clock l2clk |
| 480 | -name sii_l2_7_WRI_PA_align_chk |
| 481 | */ |
| 482 | |
| 483 | |
| 484 | /********************************* |
| 485 | WR8 |
| 486 | 1. O=1; P=1; S=1 |
| 487 | 2. PA[2:0] are zeros |
| 488 | 3. At least one Byte_mask = 1 |
| 489 | **********************************/ |
| 490 | // 1. |
| 491 | /* 0in value -var ({`SII_L2_0_O,`SII_L2_0_P, `SII_L2_0_S}) |
| 492 | -val 3'b111 |
| 493 | -active (`SII_L2_0_VLD & (`SII_L2_0_CMD==`SII_L2_WR8)) |
| 494 | -module cpu |
| 495 | -clock l2clk |
| 496 | -name sii_l2_0_WR8_O_P_S_chk |
| 497 | */ |
| 498 | /* 0in value -var ({`SII_L2_1_O,`SII_L2_1_P, `SII_L2_1_S}) |
| 499 | -val 3'b111 |
| 500 | -active (`SII_L2_1_VLD & (`SII_L2_1_CMD==`SII_L2_WR8)) |
| 501 | -module cpu |
| 502 | -clock l2clk |
| 503 | -name sii_l2_1_WR8_O_P_S_chk |
| 504 | */ |
| 505 | /* 0in value -var ({`SII_L2_2_O,`SII_L2_2_P, `SII_L2_2_S}) |
| 506 | -val 3'b111 |
| 507 | -active (`SII_L2_2_VLD & (`SII_L2_2_CMD==`SII_L2_WR8)) |
| 508 | -module cpu |
| 509 | -clock l2clk |
| 510 | -name sii_l2_2_WR8_O_P_S_chk |
| 511 | */ |
| 512 | /* 0in value -var ({`SII_L2_3_O,`SII_L2_3_P, `SII_L2_3_S}) |
| 513 | -val 3'b111 |
| 514 | -active (`SII_L2_3_VLD & (`SII_L2_3_CMD==`SII_L2_WR8)) |
| 515 | -module cpu |
| 516 | -clock l2clk |
| 517 | -name sii_l2_3_WR8_O_P_S_chk |
| 518 | */ |
| 519 | /* 0in value -var ({`SII_L2_4_O,`SII_L2_4_P, `SII_L2_4_S}) |
| 520 | -val 3'b111 |
| 521 | -active (`SII_L2_4_VLD & (`SII_L2_4_CMD==`SII_L2_WR8)) |
| 522 | -module cpu |
| 523 | -clock l2clk |
| 524 | -name sii_l2_4_WR8_O_P_S_chk |
| 525 | */ |
| 526 | /* 0in value -var ({`SII_L2_5_O,`SII_L2_5_P, `SII_L2_5_S}) |
| 527 | -val 3'b111 |
| 528 | -active (`SII_L2_5_VLD & (`SII_L2_5_CMD==`SII_L2_WR8)) |
| 529 | -module cpu |
| 530 | -clock l2clk |
| 531 | -name sii_l2_5_WR8_O_P_S_chk |
| 532 | */ |
| 533 | /* 0in value -var ({`SII_L2_6_O,`SII_L2_6_P, `SII_L2_6_S}) |
| 534 | -val 3'b111 |
| 535 | -active (`SII_L2_6_VLD & (`SII_L2_6_CMD==`SII_L2_WR8)) |
| 536 | -module cpu |
| 537 | -clock l2clk |
| 538 | -name sii_l2_6_WR8_O_P_S_chk |
| 539 | */ |
| 540 | /* 0in value -var ({`SII_L2_7_O,`SII_L2_7_P, `SII_L2_7_S}) |
| 541 | -val 3'b111 |
| 542 | -active (`SII_L2_7_VLD & (`SII_L2_7_CMD==`SII_L2_WR8)) |
| 543 | -module cpu |
| 544 | -clock l2clk |
| 545 | -name sii_l2_7_WR8_O_P_S_chk |
| 546 | */ |
| 547 | |
| 548 | |
| 549 | // 2. |
| 550 | /* 0in value -var `PA_LOW3_0 |
| 551 | -val 3'b000 |
| 552 | -active (`SII_L2_0_VLD & (`SII_L2_0_CMD==`SII_L2_WR8)) |
| 553 | -module cpu |
| 554 | -clock l2clk |
| 555 | -name sii_l2_0_WR8_PA_align_chk |
| 556 | */ |
| 557 | /* 0in value -var `PA_LOW3_1 |
| 558 | -val 3'b000 |
| 559 | -active (`SII_L2_1_VLD & (`SII_L2_1_CMD==`SII_L2_WR8)) |
| 560 | -module cpu |
| 561 | -clock l2clk |
| 562 | -name sii_l2_1_WR8_PA_align_chk |
| 563 | */ |
| 564 | /* 0in value -var `PA_LOW3_2 |
| 565 | -val 3'b000 |
| 566 | -active (`SII_L2_2_VLD & (`SII_L2_2_CMD==`SII_L2_WR8)) |
| 567 | -module cpu |
| 568 | -clock l2clk |
| 569 | -name sii_l2_2_WR8_PA_align_chk |
| 570 | */ |
| 571 | /* 0in value -var `PA_LOW3_3 |
| 572 | -val 3'b000 |
| 573 | -active (`SII_L2_3_VLD & (`SII_L2_3_CMD==`SII_L2_WR8)) |
| 574 | -module cpu |
| 575 | -clock l2clk |
| 576 | -name sii_l2_3_WR8_PA_align_chk |
| 577 | */ |
| 578 | /* 0in value -var `PA_LOW3_4 |
| 579 | -val 3'b000 |
| 580 | -active (`SII_L2_4_VLD & (`SII_L2_4_CMD==`SII_L2_WR8)) |
| 581 | -module cpu |
| 582 | -clock l2clk |
| 583 | -name sii_l2_4_WR8_PA_align_chk |
| 584 | */ |
| 585 | /* 0in value -var `PA_LOW3_5 |
| 586 | -val 3'b000 |
| 587 | -active (`SII_L2_5_VLD & (`SII_L2_5_CMD==`SII_L2_WR8)) |
| 588 | -module cpu |
| 589 | -clock l2clk |
| 590 | -name sii_l2_5_WR8_PA_align_chk |
| 591 | */ |
| 592 | /* 0in value -var `PA_LOW3_6 |
| 593 | -val 3'b000 |
| 594 | -active (`SII_L2_6_VLD & (`SII_L2_6_CMD==`SII_L2_WR8)) |
| 595 | -module cpu |
| 596 | -clock l2clk |
| 597 | -name sii_l2_6_WR8_PA_align_chk |
| 598 | */ |
| 599 | /* 0in value -var `PA_LOW3_7 |
| 600 | -val 3'b000 |
| 601 | -active (`SII_L2_7_VLD & (`SII_L2_7_CMD==`SII_L2_WR8)) |
| 602 | -module cpu |
| 603 | -clock l2clk |
| 604 | -name sii_l2_7_WR8_PA_align_chk |
| 605 | */ |
| 606 | |
| 607 | // 3. |
| 608 | /* 0in never |
| 609 | -var (`BYTE_MASK_0 == 8'b00000000) |
| 610 | -active (`SII_L2_0_VLD & (`SII_L2_0_CMD==`SII_L2_WR8)) |
| 611 | -module cpu |
| 612 | -clock l2clk |
| 613 | -name sii_l2_0_WR8_Bytemask_chk |
| 614 | */ |
| 615 | /* 0in never |
| 616 | -var (`BYTE_MASK_1 == 8'b00000000) |
| 617 | -active (`SII_L2_1_VLD & (`SII_L2_1_CMD==`SII_L2_WR8)) |
| 618 | -module cpu |
| 619 | -clock l2clk |
| 620 | -name sii_l2_1_WR8_Bytemask_chk |
| 621 | */ |
| 622 | /* 0in never |
| 623 | -var (`BYTE_MASK_2 == 8'b00000000) |
| 624 | -active (`SII_L2_2_VLD & (`SII_L2_2_CMD==`SII_L2_WR8)) |
| 625 | -module cpu |
| 626 | -clock l2clk |
| 627 | -name sii_l2_2_WR8_Bytemask_chk |
| 628 | */ |
| 629 | /* 0in never |
| 630 | -var (`BYTE_MASK_3 == 8'b00000000) |
| 631 | -active (`SII_L2_3_VLD & (`SII_L2_3_CMD==`SII_L2_WR8)) |
| 632 | -module cpu |
| 633 | -clock l2clk |
| 634 | -name sii_l2_3_WR8_Bytemask_chk |
| 635 | */ |
| 636 | /* 0in never |
| 637 | -var (`BYTE_MASK_4 == 8'b00000000) |
| 638 | -active (`SII_L2_4_VLD & (`SII_L2_4_CMD==`SII_L2_WR8)) |
| 639 | -module cpu |
| 640 | -clock l2clk |
| 641 | -name sii_l2_4_WR8_Bytemask_chk |
| 642 | */ |
| 643 | /* 0in never |
| 644 | -var (`BYTE_MASK_5 == 8'b00000000) |
| 645 | -active (`SII_L2_5_VLD & (`SII_L2_5_CMD==`SII_L2_WR8)) |
| 646 | -module cpu |
| 647 | -clock l2clk |
| 648 | -name sii_l2_5_WR8_Bytemask_chk |
| 649 | */ |
| 650 | /* 0in never |
| 651 | -var (`BYTE_MASK_6 == 8'b00000000) |
| 652 | -active (`SII_L2_6_VLD & (`SII_L2_6_CMD==`SII_L2_WR8)) |
| 653 | -module cpu |
| 654 | -clock l2clk |
| 655 | -name sii_l2_6_WR8_Bytemask_chk |
| 656 | */ |
| 657 | /* 0in never |
| 658 | -var (`BYTE_MASK_7 == 8'b00000000) |
| 659 | -active (`SII_L2_7_VLD & (`SII_L2_7_CMD==`SII_L2_WR8)) |
| 660 | -module cpu |
| 661 | -clock l2clk |
| 662 | -name sii_l2_7_WR8_Bytemask_chk |
| 663 | */ |
| 664 | |
| 665 | /*************************** |
| 666 | RDD |
| 667 | 1. P always 0 |
| 668 | 2. If from DMU O=1 |
| 669 | 3. PA[2:0] are zeros |
| 670 | 4. |
| 671 | ***************************/ |
| 672 | |
| 673 | // 1. |
| 674 | /* 0in value -var `SII_L2_0_P |
| 675 | -val 1'b0 |
| 676 | -active (`SII_L2_0_VLD & (`SII_L2_0_TT==`SII_L2_RDD)) |
| 677 | -module cpu |
| 678 | -clock l2clk |
| 679 | -name sii_l2_0_RDD_P_chk |
| 680 | */ |
| 681 | /* 0in value -var `SII_L2_1_P |
| 682 | -val 1'b0 |
| 683 | -active (`SII_L2_1_VLD & (`SII_L2_1_TT==`SII_L2_RDD)) |
| 684 | -module cpu |
| 685 | -clock l2clk |
| 686 | -name sii_l2_1_RDD_P_chk |
| 687 | */ |
| 688 | /* 0in value -var `SII_L2_2_P |
| 689 | -val 1'b0 |
| 690 | -active (`SII_L2_2_VLD & (`SII_L2_2_TT==`SII_L2_RDD)) |
| 691 | -module cpu |
| 692 | -clock l2clk |
| 693 | -name sii_l2_2_RDD_P_chk |
| 694 | */ |
| 695 | /* 0in value -var `SII_L2_3_P |
| 696 | -val 1'b0 |
| 697 | -active (`SII_L2_3_VLD & (`SII_L2_3_TT==`SII_L2_RDD)) |
| 698 | -module cpu |
| 699 | -clock l2clk |
| 700 | -name sii_l2_3_RDD_P_chk |
| 701 | */ |
| 702 | /* 0in value -var `SII_L2_4_P |
| 703 | -val 1'b0 |
| 704 | -active (`SII_L2_4_VLD & (`SII_L2_4_TT==`SII_L2_RDD)) |
| 705 | -module cpu |
| 706 | -clock l2clk |
| 707 | -name sii_l2_4_RDD_P_chk |
| 708 | */ |
| 709 | /* 0in value -var `SII_L2_5_P |
| 710 | -val 1'b0 |
| 711 | -active (`SII_L2_5_VLD & (`SII_L2_5_TT==`SII_L2_RDD)) |
| 712 | -module cpu |
| 713 | -clock l2clk |
| 714 | -name sii_l2_5_RDD_P_chk |
| 715 | */ |
| 716 | /* 0in value -var `SII_L2_6_P |
| 717 | -val 1'b0 |
| 718 | -active (`SII_L2_6_VLD & (`SII_L2_6_TT==`SII_L2_RDD)) |
| 719 | -module cpu |
| 720 | -clock l2clk |
| 721 | -name sii_l2_6_RDD_P_chk |
| 722 | */ |
| 723 | /* 0in value -var `SII_L2_7_P |
| 724 | -val 1'b0 |
| 725 | -active (`SII_L2_7_VLD & (`SII_L2_7_TT==`SII_L2_RDD)) |
| 726 | -module cpu |
| 727 | -clock l2clk |
| 728 | -name sii_l2_7_RDD_P_chk |
| 729 | */ |
| 730 | |
| 731 | |
| 732 | // 2. |
| 733 | /* 0in value -var `SII_L2_0_O |
| 734 | -val 1'b1 |
| 735 | -active (`SII_L2_0_VLD & (`SII_L2_0_TT==`SII_L2_RDD) & (`SII_L2_0_S==`DMU)) |
| 736 | -module cpu |
| 737 | -clock l2clk |
| 738 | -name sii_l2_0_RDD_O_chk |
| 739 | */ |
| 740 | /* 0in value -var `SII_L2_1_O |
| 741 | -val 1'b1 |
| 742 | -active (`SII_L2_1_VLD & (`SII_L2_1_TT==`SII_L2_RDD) & (`SII_L2_1_S==`DMU)) |
| 743 | -module cpu |
| 744 | -clock l2clk |
| 745 | -name sii_l2_1_RDD_O_chk |
| 746 | */ |
| 747 | /* 0in value -var `SII_L2_2_O |
| 748 | -val 1'b1 |
| 749 | -active (`SII_L2_2_VLD & (`SII_L2_2_TT==`SII_L2_RDD) & (`SII_L2_2_S==`DMU)) |
| 750 | -module cpu |
| 751 | -clock l2clk |
| 752 | -name sii_l2_2_RDD_O_chk |
| 753 | */ |
| 754 | /* 0in value -var `SII_L2_3_O |
| 755 | -val 1'b1 |
| 756 | -active (`SII_L2_3_VLD & (`SII_L2_3_TT==`SII_L2_RDD) & (`SII_L2_3_S==`DMU)) |
| 757 | -module cpu |
| 758 | -clock l2clk |
| 759 | -name sii_l2_3_RDD_O_chk |
| 760 | */ |
| 761 | /* 0in value -var `SII_L2_4_O |
| 762 | -val 1'b1 |
| 763 | -active (`SII_L2_4_VLD & (`SII_L2_4_TT==`SII_L2_RDD) & (`SII_L2_4_S==`DMU)) |
| 764 | -module cpu |
| 765 | -clock l2clk |
| 766 | -name sii_l2_4_RDD_O_chk |
| 767 | */ |
| 768 | /* 0in value -var `SII_L2_5_O |
| 769 | -val 1'b1 |
| 770 | -active (`SII_L2_5_VLD & (`SII_L2_5_TT==`SII_L2_RDD) & (`SII_L2_5_S==`DMU)) |
| 771 | -module cpu |
| 772 | -clock l2clk |
| 773 | -name sii_l2_5_RDD_O_chk |
| 774 | */ |
| 775 | /* 0in value -var `SII_L2_6_O |
| 776 | -val 1'b1 |
| 777 | -active (`SII_L2_6_VLD & (`SII_L2_6_TT==`SII_L2_RDD) & (`SII_L2_6_S==`DMU)) |
| 778 | -module cpu |
| 779 | -clock l2clk |
| 780 | -name sii_l2_6_RDD_O_chk |
| 781 | */ |
| 782 | /* 0in value -var `SII_L2_7_O |
| 783 | -val 1'b1 |
| 784 | -active (`SII_L2_7_VLD & (`SII_L2_7_TT==`SII_L2_RDD) & (`SII_L2_7_S==`DMU)) |
| 785 | -module cpu |
| 786 | -clock l2clk |
| 787 | -name sii_l2_7_RDD_O_chk |
| 788 | */ |
| 789 | |
| 790 | |
| 791 | // 3. |
| 792 | /* 0in value -var `PA_LOW6_0 |
| 793 | -val 6'b000000 |
| 794 | -active $0in_delay((`SII_L2_0_VLD & (`SII_L2_0_CMD==`SII_L2_RDD)), 1) |
| 795 | -module cpu |
| 796 | -clock l2clk |
| 797 | -name sii_l2_0_RDD_PA_align_chk |
| 798 | */ |
| 799 | /* 0in value -var `PA_LOW6_1 |
| 800 | -val 6'b000000 |
| 801 | -active $0in_delay((`SII_L2_1_VLD & (`SII_L2_1_CMD==`SII_L2_RDD)), 1) |
| 802 | -module cpu |
| 803 | -clock l2clk |
| 804 | -name sii_l2_1_RDD_PA_align_chk |
| 805 | */ |
| 806 | /* 0in value -var `PA_LOW6_2 |
| 807 | -val 6'b000000 |
| 808 | -active $0in_delay((`SII_L2_2_VLD & (`SII_L2_2_CMD==`SII_L2_RDD)), 1) |
| 809 | -module cpu |
| 810 | -clock l2clk |
| 811 | -name sii_l2_2_RDD_PA_align_chk |
| 812 | */ |
| 813 | /* 0in value -var `PA_LOW6_3 |
| 814 | -val 6'b000000 |
| 815 | -active $0in_delay((`SII_L2_3_VLD & (`SII_L2_3_CMD==`SII_L2_RDD)), 1) |
| 816 | -module cpu |
| 817 | -clock l2clk |
| 818 | -name sii_l2_3_RDD_PA_align_chk |
| 819 | */ |
| 820 | /* 0in value -var `PA_LOW6_4 |
| 821 | -val 6'b000000 |
| 822 | -active $0in_delay((`SII_L2_4_VLD & (`SII_L2_4_CMD==`SII_L2_RDD)), 1) |
| 823 | -module cpu |
| 824 | -clock l2clk |
| 825 | -name sii_l2_4_RDD_PA_align_chk |
| 826 | */ |
| 827 | /* 0in value -var `PA_LOW6_5 |
| 828 | -val 6'b000000 |
| 829 | -active $0in_delay((`SII_L2_5_VLD & (`SII_L2_5_CMD==`SII_L2_RDD)), 1) |
| 830 | -module cpu |
| 831 | -clock l2clk |
| 832 | -name sii_l2_5_RDD_PA_align_chk |
| 833 | */ |
| 834 | /* 0in value -var `PA_LOW6_6 |
| 835 | -val 6'b000000 |
| 836 | -active $0in_delay((`SII_L2_6_VLD & (`SII_L2_6_CMD==`SII_L2_RDD)), 1) |
| 837 | -module cpu |
| 838 | -clock l2clk |
| 839 | -name sii_l2_6_RDD_PA_align_chk |
| 840 | */ |
| 841 | /* 0in value -var `PA_LOW6_7 |
| 842 | -val 6'b000000 |
| 843 | -active $0in_delay((`SII_L2_7_VLD & (`SII_L2_7_CMD==`SII_L2_RDD)), 1) |
| 844 | -module cpu |
| 845 | -clock l2clk |
| 846 | -name sii_l2_7_RDD_PA_align_chk |
| 847 | */ |
| 848 | |
| 849 | |
| 850 | |
| 851 | |
| 852 | // Outbound valid Transactions |
| 853 | |
| 854 | /* 0in value -var `L2_0_SIO_CMD -casex |
| 855 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 856 | -active l2b0_sio_ctag_vld |
| 857 | -clock l2clk |
| 858 | -module cpu |
| 859 | -name l2_0_sio_hdr_cmd_vld |
| 860 | -message "Bad value for l2_0_sio header" |
| 861 | */ |
| 862 | /* 0in value -var `L2_1_SIO_CMD -casex |
| 863 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 864 | -active l2b1_sio_ctag_vld |
| 865 | -clock l2clk |
| 866 | -module cpu |
| 867 | -name l2_1_sio_hdr_cmd_vld |
| 868 | -message "Bad value for l2_1_sio header" |
| 869 | */ |
| 870 | /* 0in value -var `L2_2_SIO_CMD -casex |
| 871 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 872 | -active l2b2_sio_ctag_vld |
| 873 | -clock l2clk |
| 874 | -module cpu |
| 875 | -name l2_2_sio_hdr_cmd_vld |
| 876 | -message "Bad value for l2_2_sio header" |
| 877 | */ |
| 878 | /* 0in value -var `L2_3_SIO_CMD -casex |
| 879 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 880 | -active l2b3_sio_ctag_vld |
| 881 | -clock l2clk |
| 882 | -module cpu |
| 883 | -name l2_3_sio_hdr_cmd_vld |
| 884 | -message "Bad value for l2_3_sio header" |
| 885 | */ |
| 886 | /* 0in value -var `L2_4_SIO_CMD -casex |
| 887 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 888 | -active l2b4_sio_ctag_vld |
| 889 | -clock l2clk |
| 890 | -module cpu |
| 891 | -name l2_4_sio_hdr_cmd_vld |
| 892 | -message "Bad value for l2_4_sio header" |
| 893 | */ |
| 894 | /* 0in value -var `L2_5_SIO_CMD -casex |
| 895 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 896 | -active l2b5_sio_ctag_vld |
| 897 | -clock l2clk |
| 898 | -module cpu |
| 899 | -name l2_5_sio_hdr_cmd_vld |
| 900 | -message "Bad value for l2_5_sio header" |
| 901 | */ |
| 902 | /* 0in value -var `L2_6_SIO_CMD -casex |
| 903 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 904 | -active l2b6_sio_ctag_vld |
| 905 | -clock l2clk |
| 906 | -module cpu |
| 907 | -name l2_6_sio_hdr_cmd_vld |
| 908 | -message "Bad value for l2_6_sio header" |
| 909 | */ |
| 910 | /* 0in value -var `L2_7_SIO_CMD -casex |
| 911 | -val `L2_DMU_RDD_ord_npt `L2_DMU_WR8_ord_pst `L2_DMU_WRI_pst_ord `L2_NIU_RDD_ord_npt `L2_NIU_RDD_byp_npt `L2_NIU_WRI_ord_npt `L2_NIU_WRI_byp_npt `L2_NIU_WRI_ord_pst `L2_NIU_WRI_byp_pst |
| 912 | -active l2b7_sio_ctag_vld |
| 913 | -clock l2clk |
| 914 | -module cpu |
| 915 | -name l2_7_sio_hdr_cmd_vld |
| 916 | -message "Bad value for l2_7_sio header" |
| 917 | */ |
| 918 | |
| 919 | |
| 920 | /*************************** |
| 921 | Outbound RDD |
| 922 | 1. P always 0 |
| 923 | 2. If from DMU O=1 |
| 924 | 3. CBA[2:0] are zeros |
| 925 | 4. |
| 926 | ***************************/ |
| 927 | |
| 928 | // 1. |
| 929 | /* 0in value -var `L2_0_SIO_P |
| 930 | -val 1'b0 |
| 931 | -active (`L2_0_SIO_VLD & (`L2_0_SIO_TT==`L2_SIO_RDD)) |
| 932 | -module cpu |
| 933 | -clock l2clk |
| 934 | -name l2_0_sii_RDD_P_chk |
| 935 | */ |
| 936 | /* 0in value -var `L2_1_SIO_P |
| 937 | -val 1'b0 |
| 938 | -active (`L2_1_SIO_VLD & (`L2_1_SIO_TT==`L2_SIO_RDD)) |
| 939 | -module cpu |
| 940 | -clock l2clk |
| 941 | -name l2_1_sii_RDD_P_chk |
| 942 | */ |
| 943 | /* 0in value -var `L2_2_SIO_P |
| 944 | -val 1'b0 |
| 945 | -active (`L2_2_SIO_VLD & (`L2_2_SIO_TT==`L2_SIO_RDD)) |
| 946 | -module cpu |
| 947 | -clock l2clk |
| 948 | -name l2_2_sii_RDD_P_chk |
| 949 | */ |
| 950 | /* 0in value -var `L2_3_SIO_P |
| 951 | -val 1'b0 |
| 952 | -active (`L2_3_SIO_VLD & (`L2_3_SIO_TT==`L2_SIO_RDD)) |
| 953 | -module cpu |
| 954 | -clock l2clk |
| 955 | -name l2_3_sii_RDD_P_chk |
| 956 | */ |
| 957 | /* 0in value -var `L2_4_SIO_P |
| 958 | -val 1'b0 |
| 959 | -active (`L2_4_SIO_VLD & (`L2_4_SIO_TT==`L2_SIO_RDD)) |
| 960 | -module cpu |
| 961 | -clock l2clk |
| 962 | -name l2_4_sii_RDD_P_chk |
| 963 | */ |
| 964 | /* 0in value -var `L2_5_SIO_P |
| 965 | -val 1'b0 |
| 966 | -active (`L2_5_SIO_VLD & (`L2_5_SIO_TT==`L2_SIO_RDD)) |
| 967 | -module cpu |
| 968 | -clock l2clk |
| 969 | -name l2_5_sii_RDD_P_chk |
| 970 | */ |
| 971 | /* 0in value -var `L2_6_SIO_P |
| 972 | -val 1'b0 |
| 973 | -active (`L2_6_SIO_VLD & (`L2_6_SIO_TT==`L2_SIO_RDD)) |
| 974 | -module cpu |
| 975 | -clock l2clk |
| 976 | -name l2_6_sii_RDD_P_chk |
| 977 | */ |
| 978 | /* 0in value -var `L2_7_SIO_P |
| 979 | -val 1'b0 |
| 980 | -active (`L2_7_SIO_VLD & (`L2_7_SIO_TT==`L2_SIO_RDD)) |
| 981 | -module cpu |
| 982 | -clock l2clk |
| 983 | -name l2_7_sii_RDD_P_chk |
| 984 | */ |
| 985 | |
| 986 | |
| 987 | // 2. |
| 988 | /* 0in value -var `L2_0_SIO_O |
| 989 | -val 1'b1 |
| 990 | -active (`L2_0_SIO_VLD & (`L2_0_SIO_TT==`L2_SIO_RDD) & (`L2_0_SIO_S==`DMU)) |
| 991 | -module cpu |
| 992 | -clock l2clk |
| 993 | -name l2_0_sii_RDD_O_chk |
| 994 | */ |
| 995 | /* 0in value -var `L2_1_SIO_O |
| 996 | -val 1'b1 |
| 997 | -active (`L2_1_SIO_VLD & (`L2_1_SIO_TT==`L2_SIO_RDD) & (`L2_1_SIO_S==`DMU)) |
| 998 | -module cpu |
| 999 | -clock l2clk |
| 1000 | -name l2_1_sii_RDD_O_chk |
| 1001 | */ |
| 1002 | /* 0in value -var `L2_2_SIO_O |
| 1003 | -val 1'b1 |
| 1004 | -active (`L2_2_SIO_VLD & (`L2_2_SIO_TT==`L2_SIO_RDD) & (`L2_2_SIO_S==`DMU)) |
| 1005 | -module cpu |
| 1006 | -clock l2clk |
| 1007 | -name l2_2_sii_RDD_O_chk |
| 1008 | */ |
| 1009 | /* 0in value -var `L2_3_SIO_O |
| 1010 | -val 1'b1 |
| 1011 | -active (`L2_3_SIO_VLD & (`L2_3_SIO_TT==`L2_SIO_RDD) & (`L2_3_SIO_S==`DMU)) |
| 1012 | -module cpu |
| 1013 | -clock l2clk |
| 1014 | -name l2_3_sii_RDD_O_chk |
| 1015 | */ |
| 1016 | /* 0in value -var `L2_4_SIO_O |
| 1017 | -val 1'b1 |
| 1018 | -active (`L2_4_SIO_VLD & (`L2_4_SIO_TT==`L2_SIO_RDD) & (`L2_4_SIO_S==`DMU)) |
| 1019 | -module cpu |
| 1020 | -clock l2clk |
| 1021 | -name l2_4_sii_RDD_O_chk |
| 1022 | */ |
| 1023 | /* 0in value -var `L2_5_SIO_O |
| 1024 | -val 1'b1 |
| 1025 | -active (`L2_5_SIO_VLD & (`L2_5_SIO_TT==`L2_SIO_RDD) & (`L2_5_SIO_S==`DMU)) |
| 1026 | -module cpu |
| 1027 | -clock l2clk |
| 1028 | -name l2_5_sii_RDD_O_chk |
| 1029 | */ |
| 1030 | /* 0in value -var `L2_6_SIO_O |
| 1031 | -val 1'b1 |
| 1032 | -active (`L2_6_SIO_VLD & (`L2_6_SIO_TT==`L2_SIO_RDD) & (`L2_6_SIO_S==`DMU)) |
| 1033 | -module cpu |
| 1034 | -clock l2clk |
| 1035 | -name l2_6_sii_RDD_O_chk |
| 1036 | */ |
| 1037 | /* 0in value -var `L2_7_SIO_O |
| 1038 | -val 1'b1 |
| 1039 | -active (`L2_7_SIO_VLD & (`L2_7_SIO_TT==`L2_SIO_RDD) & (`L2_7_SIO_S==`DMU)) |
| 1040 | -module cpu |
| 1041 | -clock l2clk |
| 1042 | -name l2_7_sii_RDD_O_chk |
| 1043 | */ |
| 1044 | |
| 1045 | |
| 1046 | // 3. |
| 1047 | /* 0in value -var `CBA_0 |
| 1048 | -val 3'b000 |
| 1049 | -active (`L2_0_SIO_VLD & (`L2_0_SIO_CMD==`L2_SIO_RDD)) |
| 1050 | -module cpu |
| 1051 | -clock l2clk |
| 1052 | -name sii_l2_0_RDD_CBA_chk |
| 1053 | */ |
| 1054 | /* 0in value -var `CBA_1 |
| 1055 | -val 3'b000 |
| 1056 | -active (`L2_1_SIO_VLD & (`L2_1_SIO_CMD==`L2_SIO_RDD)) |
| 1057 | -module cpu |
| 1058 | -clock l2clk |
| 1059 | -name sii_l2_1_RDD_CBA_chk |
| 1060 | */ |
| 1061 | /* 0in value -var `CBA_2 |
| 1062 | -val 3'b000 |
| 1063 | -active (`L2_2_SIO_VLD & (`L2_2_SIO_CMD==`L2_SIO_RDD)) |
| 1064 | -module cpu |
| 1065 | -clock l2clk |
| 1066 | -name sii_l2_2_RDD_CBA_chk |
| 1067 | */ |
| 1068 | /* 0in value -var `CBA_3 |
| 1069 | -val 3'b000 |
| 1070 | -active (`L2_3_SIO_VLD & (`L2_3_SIO_CMD==`L2_SIO_RDD)) |
| 1071 | -module cpu |
| 1072 | -clock l2clk |
| 1073 | -name sii_l2_3_RDD_CBA_chk |
| 1074 | */ |
| 1075 | /* 0in value -var `CBA_4 |
| 1076 | -val 3'b000 |
| 1077 | -active (`L2_4_SIO_VLD & (`L2_4_SIO_CMD==`L2_SIO_RDD)) |
| 1078 | -module cpu |
| 1079 | -clock l2clk |
| 1080 | -name sii_l2_4_RDD_CBA_chk |
| 1081 | */ |
| 1082 | /* 0in value -var `CBA_5 |
| 1083 | -val 3'b000 |
| 1084 | -active (`L2_5_SIO_VLD & (`L2_5_SIO_CMD==`L2_SIO_RDD)) |
| 1085 | -module cpu |
| 1086 | -clock l2clk |
| 1087 | -name sii_l2_5_RDD_CBA_chk |
| 1088 | */ |
| 1089 | /* 0in value -var `CBA_6 |
| 1090 | -val 3'b000 |
| 1091 | -active (`L2_6_SIO_VLD & (`L2_6_SIO_CMD==`L2_SIO_RDD)) |
| 1092 | -module cpu |
| 1093 | -clock l2clk |
| 1094 | -name sii_l2_6_RDD_CBA_chk |
| 1095 | */ |
| 1096 | /* 0in value -var `CBA_7 |
| 1097 | -val 3'b000 |
| 1098 | -active (`L2_7_SIO_VLD & (`L2_7_SIO_CMD==`L2_SIO_RDD)) |
| 1099 | -module cpu |
| 1100 | -clock l2clk |
| 1101 | -name sii_l2_7_RDD_CBA_chk |
| 1102 | */ |
| 1103 | |
| 1104 | |
| 1105 | /*************************** |
| 1106 | Outbound WRI |
| 1107 | 1. P is 1 if from DMU |
| 1108 | 2. If from DMU O=1 |
| 1109 | 3. CBA[2:0] are zeros |
| 1110 | 4. |
| 1111 | ***************************/ |
| 1112 | |
| 1113 | // 1. |
| 1114 | /* 0in value -var `L2_0_SIO_P |
| 1115 | -val 1'b1 |
| 1116 | -active (`L2_0_SIO_VLD & (`L2_0_SIO_TT==`L2_SIO_WRI) & (`L2_0_SIO_S==`DMU)) |
| 1117 | -module cpu |
| 1118 | -clock l2clk |
| 1119 | -name l2_0_sii_WRI_P_chk |
| 1120 | */ |
| 1121 | /* 0in value -var `L2_1_SIO_P |
| 1122 | -val 1'b1 |
| 1123 | -active (`L2_1_SIO_VLD & (`L2_1_SIO_TT==`L2_SIO_WRI) & (`L2_1_SIO_S==`DMU)) |
| 1124 | -module cpu |
| 1125 | -clock l2clk |
| 1126 | -name l2_1_sii_WRI_P_chk |
| 1127 | */ |
| 1128 | /* 0in value -var `L2_2_SIO_P |
| 1129 | -val 1'b1 |
| 1130 | -active (`L2_2_SIO_VLD & (`L2_2_SIO_TT==`L2_SIO_WRI) & (`L2_2_SIO_S==`DMU)) |
| 1131 | -module cpu |
| 1132 | -clock l2clk |
| 1133 | -name l2_2_sii_WRI_P_chk |
| 1134 | */ |
| 1135 | /* 0in value -var `L2_3_SIO_P |
| 1136 | -val 1'b1 |
| 1137 | -active (`L2_3_SIO_VLD & (`L2_3_SIO_TT==`L2_SIO_WRI) & (`L2_3_SIO_S==`DMU)) |
| 1138 | -module cpu |
| 1139 | -clock l2clk |
| 1140 | -name l2_3_sii_WRI_P_chk |
| 1141 | */ |
| 1142 | /* 0in value -var `L2_4_SIO_P |
| 1143 | -val 1'b1 |
| 1144 | -active (`L2_4_SIO_VLD & (`L2_4_SIO_TT==`L2_SIO_WRI) & (`L2_4_SIO_S==`DMU)) |
| 1145 | -module cpu |
| 1146 | -clock l2clk |
| 1147 | -name l2_4_sii_WRI_P_chk |
| 1148 | */ |
| 1149 | /* 0in value -var `L2_5_SIO_P |
| 1150 | -val 1'b1 |
| 1151 | -active (`L2_5_SIO_VLD & (`L2_5_SIO_TT==`L2_SIO_WRI) & (`L2_5_SIO_S==`DMU)) |
| 1152 | -module cpu |
| 1153 | -clock l2clk |
| 1154 | -name l2_5_sii_WRI_P_chk |
| 1155 | */ |
| 1156 | /* 0in value -var `L2_6_SIO_P |
| 1157 | -val 1'b1 |
| 1158 | -active (`L2_6_SIO_VLD & (`L2_6_SIO_TT==`L2_SIO_WRI) & (`L2_6_SIO_S==`DMU)) |
| 1159 | -module cpu |
| 1160 | -clock l2clk |
| 1161 | -name l2_6_sii_WRI_P_chk |
| 1162 | */ |
| 1163 | /* 0in value -var `L2_7_SIO_P |
| 1164 | -val 1'b1 |
| 1165 | -active (`L2_7_SIO_VLD & (`L2_7_SIO_TT==`L2_SIO_WRI) & (`L2_7_SIO_S==`DMU)) |
| 1166 | -module cpu |
| 1167 | -clock l2clk |
| 1168 | -name l2_7_sii_WRI_P_chk |
| 1169 | */ |
| 1170 | |
| 1171 | |
| 1172 | // 2. |
| 1173 | /* 0in value -var `L2_0_SIO_O |
| 1174 | -val 1'b1 |
| 1175 | -active (`L2_0_SIO_VLD & (`L2_0_SIO_TT==`L2_SIO_WRI) & (`L2_0_SIO_S==`DMU)) |
| 1176 | -module cpu |
| 1177 | -clock l2clk |
| 1178 | -name l2_0_sii_WRI_O_chk |
| 1179 | */ |
| 1180 | /* 0in value -var `L2_1_SIO_O |
| 1181 | -val 1'b1 |
| 1182 | -active (`L2_1_SIO_VLD & (`L2_1_SIO_TT==`L2_SIO_WRI) & (`L2_1_SIO_S==`DMU)) |
| 1183 | -module cpu |
| 1184 | -clock l2clk |
| 1185 | -name l2_1_sii_WRI_O_chk |
| 1186 | */ |
| 1187 | /* 0in value -var `L2_2_SIO_O |
| 1188 | -val 1'b1 |
| 1189 | -active (`L2_2_SIO_VLD & (`L2_2_SIO_TT==`L2_SIO_WRI) & (`L2_2_SIO_S==`DMU)) |
| 1190 | -module cpu |
| 1191 | -clock l2clk |
| 1192 | -name l2_2_sii_WRI_O_chk |
| 1193 | */ |
| 1194 | /* 0in value -var `L2_3_SIO_O |
| 1195 | -val 1'b1 |
| 1196 | -active (`L2_3_SIO_VLD & (`L2_3_SIO_TT==`L2_SIO_WRI) & (`L2_3_SIO_S==`DMU)) |
| 1197 | -module cpu |
| 1198 | -clock l2clk |
| 1199 | -name l2_3_sii_WRI_O_chk |
| 1200 | */ |
| 1201 | /* 0in value -var `L2_4_SIO_O |
| 1202 | -val 1'b1 |
| 1203 | -active (`L2_4_SIO_VLD & (`L2_4_SIO_TT==`L2_SIO_WRI) & (`L2_4_SIO_S==`DMU)) |
| 1204 | -module cpu |
| 1205 | -clock l2clk |
| 1206 | -name l2_4_sii_WRI_O_chk |
| 1207 | */ |
| 1208 | /* 0in value -var `L2_5_SIO_O |
| 1209 | -val 1'b1 |
| 1210 | -active (`L2_5_SIO_VLD & (`L2_5_SIO_TT==`L2_SIO_WRI) & (`L2_5_SIO_S==`DMU)) |
| 1211 | -module cpu |
| 1212 | -clock l2clk |
| 1213 | -name l2_5_sii_WRI_O_chk |
| 1214 | */ |
| 1215 | /* 0in value -var `L2_6_SIO_O |
| 1216 | -val 1'b1 |
| 1217 | -active (`L2_6_SIO_VLD & (`L2_6_SIO_TT==`L2_SIO_WRI) & (`L2_6_SIO_S==`DMU)) |
| 1218 | -module cpu |
| 1219 | -clock l2clk |
| 1220 | -name l2_6_sii_WRI_O_chk |
| 1221 | */ |
| 1222 | /* 0in value -var `L2_7_SIO_O |
| 1223 | -val 1'b1 |
| 1224 | -active (`L2_7_SIO_VLD & (`L2_7_SIO_TT==`L2_SIO_WRI) & (`L2_7_SIO_S==`DMU)) |
| 1225 | -module cpu |
| 1226 | -clock l2clk |
| 1227 | -name l2_7_sii_WRI_O_chk |
| 1228 | */ |
| 1229 | |
| 1230 | |
| 1231 | // 3. |
| 1232 | /* 0in value -var `CBA_0 |
| 1233 | -val 3'b000 |
| 1234 | -active (`L2_0_SIO_VLD & (`L2_0_SIO_CMD==`L2_SIO_WRI)) |
| 1235 | -module cpu |
| 1236 | -clock l2clk |
| 1237 | -name sii_l2_0_WRI_CBA_chk |
| 1238 | */ |
| 1239 | /* 0in value -var `CBA_1 |
| 1240 | -val 3'b000 |
| 1241 | -active (`L2_1_SIO_VLD & (`L2_1_SIO_CMD==`L2_SIO_WRI)) |
| 1242 | -module cpu |
| 1243 | -clock l2clk |
| 1244 | -name sii_l2_1_WRI_CBA_chk |
| 1245 | */ |
| 1246 | /* 0in value -var `CBA_2 |
| 1247 | -val 3'b000 |
| 1248 | -active (`L2_2_SIO_VLD & (`L2_2_SIO_CMD==`L2_SIO_WRI)) |
| 1249 | -module cpu |
| 1250 | -clock l2clk |
| 1251 | -name sii_l2_2_WRI_CBA_chk |
| 1252 | */ |
| 1253 | /* 0in value -var `CBA_3 |
| 1254 | -val 3'b000 |
| 1255 | -active (`L2_3_SIO_VLD & (`L2_3_SIO_CMD==`L2_SIO_WRI)) |
| 1256 | -module cpu |
| 1257 | -clock l2clk |
| 1258 | -name sii_l2_3_WRI_CBA_chk |
| 1259 | */ |
| 1260 | /* 0in value -var `CBA_4 |
| 1261 | -val 3'b000 |
| 1262 | -active (`L2_4_SIO_VLD & (`L2_4_SIO_CMD==`L2_SIO_WRI)) |
| 1263 | -module cpu |
| 1264 | -clock l2clk |
| 1265 | -name sii_l2_4_WRI_CBA_chk |
| 1266 | */ |
| 1267 | /* 0in value -var `CBA_5 |
| 1268 | -val 3'b000 |
| 1269 | -active (`L2_5_SIO_VLD & (`L2_5_SIO_CMD==`L2_SIO_WRI)) |
| 1270 | -module cpu |
| 1271 | -clock l2clk |
| 1272 | -name sii_l2_5_WRI_CBA_chk |
| 1273 | */ |
| 1274 | /* 0in value -var `CBA_6 |
| 1275 | -val 3'b000 |
| 1276 | -active (`L2_6_SIO_VLD & (`L2_6_SIO_CMD==`L2_SIO_WRI)) |
| 1277 | -module cpu |
| 1278 | -clock l2clk |
| 1279 | -name sii_l2_6_WRI_CBA_chk |
| 1280 | */ |
| 1281 | /* 0in value -var `CBA_7 |
| 1282 | -val 3'b000 |
| 1283 | -active (`L2_7_SIO_VLD & (`L2_7_SIO_CMD==`L2_SIO_WRI)) |
| 1284 | -module cpu |
| 1285 | -clock l2clk |
| 1286 | -name sii_l2_7_WRI_CBA_chk |
| 1287 | */ |
| 1288 | |
| 1289 | |
| 1290 | /******************************************** |
| 1291 | 16 cycle gap between 2 l2t_sii_iq_dequeue |
| 1292 | ********************************************/ |
| 1293 | |
| 1294 | |
| 1295 | /********************************************************************** |
| 1296 | Minumum 4 (2nd hdr, 2 data/dummy, 1 turn-around) cycles |
| 1297 | gap after an RDD or WR8 |
| 1298 | **********************************************************************/ |
| 1299 | /* 0in assert_window |
| 1300 | -start (`SII_L2_0_VLD & ((`SII_L2_0_TT==`SII_L2_RDD) | (`SII_L2_0_TT==`SII_L2_WR8))) |
| 1301 | -start_count 0 -stop_count 4 |
| 1302 | -not_in `SII_L2_0_VLD |
| 1303 | -clock l2clk |
| 1304 | -module cpu |
| 1305 | -name sii_l2_0_min_gap_WR8_RDD |
| 1306 | */ |
| 1307 | /* 0in assert_window |
| 1308 | -start (`SII_L2_1_VLD & ((`SII_L2_1_TT==`SII_L2_RDD) | (`SII_L2_1_TT==`SII_L2_WR8))) |
| 1309 | -start_count 0 -stop_count 4 |
| 1310 | -not_in `SII_L2_1_VLD |
| 1311 | -clock l2clk |
| 1312 | -module cpu |
| 1313 | -name sii_l2_1_min_gap_WR8_RDD |
| 1314 | */ |
| 1315 | /* 0in assert_window |
| 1316 | -start (`SII_L2_2_VLD & ((`SII_L2_2_TT==`SII_L2_RDD) | (`SII_L2_2_TT==`SII_L2_WR8))) |
| 1317 | -start_count 0 -stop_count 4 |
| 1318 | -not_in `SII_L2_2_VLD |
| 1319 | -clock l2clk |
| 1320 | -module cpu |
| 1321 | -name sii_l2_2_min_gap_WR8_RDD |
| 1322 | */ |
| 1323 | /* 0in assert_window |
| 1324 | -start (`SII_L2_3_VLD & ((`SII_L2_3_TT==`SII_L2_RDD) | (`SII_L2_3_TT==`SII_L2_WR8))) |
| 1325 | -start_count 0 -stop_count 4 |
| 1326 | -not_in `SII_L2_3_VLD |
| 1327 | -clock l2clk |
| 1328 | -module cpu |
| 1329 | -name sii_l2_3_min_gap_WR8_RDD |
| 1330 | */ |
| 1331 | /* 0in assert_window |
| 1332 | -start (`SII_L2_4_VLD & ((`SII_L2_4_TT==`SII_L2_RDD) | (`SII_L2_4_TT==`SII_L2_WR8))) |
| 1333 | -start_count 0 -stop_count 4 |
| 1334 | -not_in `SII_L2_4_VLD |
| 1335 | -clock l2clk |
| 1336 | -module cpu |
| 1337 | -name sii_l2_4_min_gap_WR8_RDD |
| 1338 | */ |
| 1339 | /* 0in assert_window |
| 1340 | -start (`SII_L2_5_VLD & ((`SII_L2_5_TT==`SII_L2_RDD) | (`SII_L2_5_TT==`SII_L2_WR8))) |
| 1341 | -start_count 0 -stop_count 4 |
| 1342 | -not_in `SII_L2_5_VLD |
| 1343 | -clock l2clk |
| 1344 | -module cpu |
| 1345 | -name sii_l2_5_min_gap_WR8_RDD |
| 1346 | */ |
| 1347 | /* 0in assert_window |
| 1348 | -start (`SII_L2_6_VLD & ((`SII_L2_6_TT==`SII_L2_RDD) | (`SII_L2_6_TT==`SII_L2_WR8))) |
| 1349 | -start_count 0 -stop_count 4 |
| 1350 | -not_in `SII_L2_6_VLD |
| 1351 | -clock l2clk |
| 1352 | -module cpu |
| 1353 | -name sii_l2_6_min_gap_WR8_RDD |
| 1354 | */ |
| 1355 | /* 0in assert_window |
| 1356 | -start (`SII_L2_7_VLD & ((`SII_L2_7_TT==`SII_L2_RDD) | (`SII_L2_7_TT==`SII_L2_WR8))) |
| 1357 | -start_count 0 -stop_count 4 |
| 1358 | -not_in `SII_L2_7_VLD |
| 1359 | -clock l2clk |
| 1360 | -module cpu |
| 1361 | -name sii_l2_7_min_gap_WR8_RDD |
| 1362 | */ |
| 1363 | |
| 1364 | /********************************************************************* |
| 1365 | Minumum 18 (2nd hdr, 16 data, 1 turn-around) cycles |
| 1366 | gap after a WRI |
| 1367 | **********************************************************************/ |
| 1368 | /* 0in assert_window |
| 1369 | -start (`SII_L2_0_VLD & (`SII_L2_0_TT==`SII_L2_WRI)) |
| 1370 | -start_count 0 -stop_count 18 |
| 1371 | -not_in `SII_L2_0_VLD |
| 1372 | -clock l2clk |
| 1373 | -module cpu |
| 1374 | -name sii_l2_0_min_gap_WRI |
| 1375 | */ |
| 1376 | /* 0in assert_window |
| 1377 | -start (`SII_L2_1_VLD & (`SII_L2_1_TT==`SII_L2_WRI)) |
| 1378 | -start_count 0 -stop_count 18 |
| 1379 | -not_in `SII_L2_1_VLD |
| 1380 | -clock l2clk |
| 1381 | -module cpu |
| 1382 | -name sii_l2_1_min_gap_WRI |
| 1383 | */ |
| 1384 | /* 0in assert_window |
| 1385 | -start (`SII_L2_2_VLD & (`SII_L2_2_TT==`SII_L2_WRI)) |
| 1386 | -start_count 0 -stop_count 18 |
| 1387 | -not_in `SII_L2_2_VLD |
| 1388 | -clock l2clk |
| 1389 | -module cpu |
| 1390 | -name sii_l2_2_min_gap_WRI |
| 1391 | */ |
| 1392 | /* 0in assert_window |
| 1393 | -start (`SII_L2_3_VLD & (`SII_L2_3_TT==`SII_L2_WRI)) |
| 1394 | -start_count 0 -stop_count 18 |
| 1395 | -not_in `SII_L2_3_VLD |
| 1396 | -clock l2clk |
| 1397 | -module cpu |
| 1398 | -name sii_l2_3_min_gap_WRI |
| 1399 | */ |
| 1400 | /* 0in assert_window |
| 1401 | -start (`SII_L2_4_VLD & (`SII_L2_4_TT==`SII_L2_WRI)) |
| 1402 | -start_count 0 -stop_count 18 |
| 1403 | -not_in `SII_L2_4_VLD |
| 1404 | -clock l2clk |
| 1405 | -module cpu |
| 1406 | -name sii_l2_4_min_gap_WRI |
| 1407 | */ |
| 1408 | /* 0in assert_window |
| 1409 | -start (`SII_L2_5_VLD & (`SII_L2_5_TT==`SII_L2_WRI)) |
| 1410 | -start_count 0 -stop_count 18 |
| 1411 | -not_in `SII_L2_5_VLD |
| 1412 | -clock l2clk |
| 1413 | -module cpu |
| 1414 | -name sii_l2_5_min_gap_WRI |
| 1415 | */ |
| 1416 | /* 0in assert_window |
| 1417 | -start (`SII_L2_6_VLD & (`SII_L2_6_TT==`SII_L2_WRI)) |
| 1418 | -start_count 0 -stop_count 18 |
| 1419 | -not_in `SII_L2_6_VLD |
| 1420 | -clock l2clk |
| 1421 | -module cpu |
| 1422 | -name sii_l2_6_min_gap_WRI |
| 1423 | */ |
| 1424 | /* 0in assert_window |
| 1425 | -start (`SII_L2_7_VLD & (`SII_L2_7_TT==`SII_L2_WRI)) |
| 1426 | -start_count 0 -stop_count 18 |
| 1427 | -not_in `SII_L2_7_VLD |
| 1428 | -clock l2clk |
| 1429 | -module cpu |
| 1430 | -name sii_l2_7_min_gap_WRI |
| 1431 | */ |
| 1432 | |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | /* req and ack */ |
| 1437 | |
| 1438 | /* 0in assert_follower |
| 1439 | -leader `SII_L2_0_VLD |
| 1440 | -follower l2t0_sii_iq_dequeue |
| 1441 | -min 5 |
| 1442 | -max 8000 |
| 1443 | -max_leader 2 |
| 1444 | -module cpu |
| 1445 | -clock l2clk |
| 1446 | -name sii_l2_0_req_assert_follower |
| 1447 | */ |
| 1448 | |
| 1449 | /* 0in assert_leader |
| 1450 | -leader `SII_L2_0_VLD |
| 1451 | -follower l2t0_sii_iq_dequeue |
| 1452 | -min 5 |
| 1453 | -max 8000 |
| 1454 | -max_leader 2 |
| 1455 | -clock l2clk |
| 1456 | -module cpu |
| 1457 | -name sii_l2_0_req_assert_leader |
| 1458 | */ |
| 1459 | /* 0in assert_follower |
| 1460 | -leader `SII_L2_1_VLD |
| 1461 | -follower l2t1_sii_iq_dequeue |
| 1462 | -min 5 |
| 1463 | -max 8000 |
| 1464 | -max_leader 2 |
| 1465 | -module cpu |
| 1466 | -clock l2clk |
| 1467 | -name sii_l2_1_req_assert_follower |
| 1468 | */ |
| 1469 | |
| 1470 | /* 0in assert_leader |
| 1471 | -leader `SII_L2_1_VLD |
| 1472 | -follower l2t1_sii_iq_dequeue |
| 1473 | -min 5 |
| 1474 | -max 8000 |
| 1475 | -max_leader 2 |
| 1476 | -clock l2clk |
| 1477 | -module cpu |
| 1478 | -name sii_l2_1_req_assert_leader |
| 1479 | */ |
| 1480 | /* 0in assert_follower |
| 1481 | -leader `SII_L2_2_VLD |
| 1482 | -follower l2t2_sii_iq_dequeue |
| 1483 | -min 5 |
| 1484 | -max 8000 |
| 1485 | -max_leader 2 |
| 1486 | -module cpu |
| 1487 | -clock l2clk |
| 1488 | -name sii_l2_2_req_assert_follower |
| 1489 | */ |
| 1490 | |
| 1491 | /* 0in assert_leader |
| 1492 | -leader `SII_L2_2_VLD |
| 1493 | -follower l2t2_sii_iq_dequeue |
| 1494 | -min 5 |
| 1495 | -max 8000 |
| 1496 | -max_leader 2 |
| 1497 | -clock l2clk |
| 1498 | -module cpu |
| 1499 | -name sii_l2_2_req_assert_leader |
| 1500 | */ |
| 1501 | /* 0in assert_follower |
| 1502 | -leader `SII_L2_3_VLD |
| 1503 | -follower l2t3_sii_iq_dequeue |
| 1504 | -min 5 |
| 1505 | -max 8000 |
| 1506 | -max_leader 2 |
| 1507 | -module cpu |
| 1508 | -clock l2clk |
| 1509 | -name sii_l2_3_req_assert_follower |
| 1510 | */ |
| 1511 | |
| 1512 | /* 0in assert_leader |
| 1513 | -leader `SII_L2_3_VLD |
| 1514 | -follower l2t3_sii_iq_dequeue |
| 1515 | -min 5 |
| 1516 | -max 8000 |
| 1517 | -max_leader 2 |
| 1518 | -clock l2clk |
| 1519 | -module cpu |
| 1520 | -name sii_l2_3_req_assert_leader |
| 1521 | */ |
| 1522 | /* 0in assert_follower |
| 1523 | -leader `SII_L2_4_VLD |
| 1524 | -follower l2t4_sii_iq_dequeue |
| 1525 | -min 5 |
| 1526 | -max 8000 |
| 1527 | -max_leader 2 |
| 1528 | -module cpu |
| 1529 | -clock l2clk |
| 1530 | -name sii_l2_4_req_assert_follower |
| 1531 | */ |
| 1532 | |
| 1533 | /* 0in assert_leader |
| 1534 | -leader `SII_L2_4_VLD |
| 1535 | -follower l2t4_sii_iq_dequeue |
| 1536 | -min 5 |
| 1537 | -max 8000 |
| 1538 | -max_leader 2 |
| 1539 | -clock l2clk |
| 1540 | -module cpu |
| 1541 | -name sii_l2_4_req_assert_leader |
| 1542 | */ |
| 1543 | /* 0in assert_follower |
| 1544 | -leader `SII_L2_5_VLD |
| 1545 | -follower l2t5_sii_iq_dequeue |
| 1546 | -min 5 |
| 1547 | -max 8000 |
| 1548 | -max_leader 2 |
| 1549 | -module cpu |
| 1550 | -clock l2clk |
| 1551 | -name sii_l2_5_req_assert_follower |
| 1552 | */ |
| 1553 | |
| 1554 | /* 0in assert_leader |
| 1555 | -leader `SII_L2_5_VLD |
| 1556 | -follower l2t5_sii_iq_dequeue |
| 1557 | -min 5 |
| 1558 | -max 8000 |
| 1559 | -max_leader 2 |
| 1560 | -clock l2clk |
| 1561 | -module cpu |
| 1562 | -name sii_l2_5_req_assert_leader |
| 1563 | */ |
| 1564 | /* 0in assert_follower |
| 1565 | -leader `SII_L2_6_VLD |
| 1566 | -follower l2t6_sii_iq_dequeue |
| 1567 | -min 5 |
| 1568 | -max 8000 |
| 1569 | -max_leader 2 |
| 1570 | -module cpu |
| 1571 | -clock l2clk |
| 1572 | -name sii_l2_6_req_assert_follower |
| 1573 | */ |
| 1574 | |
| 1575 | /* 0in assert_leader |
| 1576 | -leader `SII_L2_6_VLD |
| 1577 | -follower l2t6_sii_iq_dequeue |
| 1578 | -min 5 |
| 1579 | -max 8000 |
| 1580 | -max_leader 2 |
| 1581 | -clock l2clk |
| 1582 | -module cpu |
| 1583 | -name sii_l2_6_req_assert_leader |
| 1584 | */ |
| 1585 | /* 0in assert_follower |
| 1586 | -leader `SII_L2_7_VLD |
| 1587 | -follower l2t7_sii_iq_dequeue |
| 1588 | -min 5 |
| 1589 | -max 8000 |
| 1590 | -max_leader 2 |
| 1591 | -module cpu |
| 1592 | -clock l2clk |
| 1593 | -name sii_l2_7_req_assert_follower |
| 1594 | */ |
| 1595 | |
| 1596 | /* 0in assert_leader |
| 1597 | -leader `SII_L2_7_VLD |
| 1598 | -follower l2t7_sii_iq_dequeue |
| 1599 | -min 5 |
| 1600 | -max 8000 |
| 1601 | -max_leader 2 |
| 1602 | -clock l2clk |
| 1603 | -module cpu |
| 1604 | -name sii_l2_7_req_assert_leader |
| 1605 | */ |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | |
| 1610 | // Put some bus_id |
| 1611 | |
| 1612 | // Transactions from the same bank should be in-order; |
| 1613 | // so use fifo chkr |
| 1614 | |
| 1615 | endmodule // sii_l2_chkr |