| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcul2_intf_chkr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcul2_intf_chkr; |
| 36 | |
| 37 | `ifndef NO_MCU_L2_CHECKERS |
| 38 | |
| 39 | /* C1: 31 bits of DIMM address, issued by L2. |
| 40 | SIGNALS : |
| 41 | input [39:7] l2t0_mcu_addr_39to7; |
| 42 | input [39:7] l2t1_mcu_addr_39to7; |
| 43 | |
| 44 | CONSTRAINTS : |
| 45 | 1. Needs to be driven during Read/Write req. |
| 46 | */ |
| 47 | |
| 48 | /*******Constraint C1*********************/ |
| 49 | |
| 50 | |
| 51 | |
| 52 | |
| 53 | |
| 54 | /* C2: Data ordering. Its the 5th bit in the PA. Represents the order |
| 55 | in which the data has to be returned. |
| 56 | SIGNALS : |
| 57 | input l2t0_mcu_addr_5; |
| 58 | input l2t1_mcu_addr_5; |
| 59 | |
| 60 | CONSTRAINTS : |
| 61 | 1. Valid only during Read/Write req. |
| 62 | |
| 63 | Notes: |
| 64 | 1. Active Low - Sequential - 0, 1, 2, 3 [BL = 4] |
| 65 | 2. Active High - Interleaved - 2, 3, 0, 1 [BL = 4] |
| 66 | */ |
| 67 | |
| 68 | /***********Constraint C2***************/ |
| 69 | |
| 70 | |
| 71 | |
| 72 | |
| 73 | |
| 74 | /* C3: READ REQUEST FROM L2. |
| 75 | |
| 76 | SIGNALS : |
| 77 | input l2t0_mcu_rd_req; |
| 78 | input l2t1_mcu_rd_req; |
| 79 | output mcu_l2t0_rd_ack; |
| 80 | output mcu_l2t1_rd_ack; |
| 81 | input [2:0] l2t0_mcu_rd_req_id; |
| 82 | input [2:0] l2t1_mcu_rd_req_id; |
| 83 | input l2t0_mcu_rd_dummy_req; |
| 84 | input l2t1_mcu_rd_dummy_req; |
| 85 | output [2:0] mcu_l2t0_rd_req_id_r0; |
| 86 | output [2:0] mcu_l2t1_rd_req_id_r0; |
| 87 | output [127:0] mcu_l2b_data_r3; |
| 88 | |
| 89 | CONSTRAINTS : |
| 90 | 1. Each read req is acknowledged by the MCU with mcu_l2t0/1_rd_ack. |
| 91 | 2. Max of 8 reqs per bank could be outstanding. |
| 92 | 3. Back to back reads could be issued only after 3 (1 clks is |
| 93 | also fine) clocks after rd_ack. |
| 94 | 4. Each read req is uniquely identified by 3bit mcu_rd_req_id. |
| 95 | 5. No simultaneous rd and wr req from the same bank. |
| 96 | 6. Do we have to ensure that memory reads only initialized locations? |
| 97 | |
| 98 | SIGNALS : |
| 99 | input l2t0_mcu_rd_dummy_req; |
| 100 | input l2t1_mcu_rd_dummy_req; |
| 101 | |
| 102 | C4: Dummy Read Requset. Asserted along with rd req. Data returned |
| 103 | is all zero's. |
| 104 | |
| 105 | CONSTRAINTS : |
| 106 | 1. Asserted along with l2t0/1_mcu_rd_req. |
| 107 | |
| 108 | Notes: |
| 109 | We can have simultaneous rd reqs from both the banks. |
| 110 | The dummy read req is not issued to the DRAM but the MCU |
| 111 | responds with 0's as data. Max of 8 rd reqs can be outstanding, |
| 112 | this includes dummy reqs too. |
| 113 | */ |
| 114 | |
| 115 | /************Constraint C3.1*********/ |
| 116 | |
| 117 | |
| 118 | |
| 119 | /************Constraint C3.3************/ |
| 120 | |
| 121 | reg mcu0_l2t0_rd_ack_d1; |
| 122 | reg mcu0_l2t1_rd_ack_d1; |
| 123 | reg mcu1_l2t0_rd_ack_d1; |
| 124 | reg mcu1_l2t1_rd_ack_d1; |
| 125 | reg mcu2_l2t0_rd_ack_d1; |
| 126 | reg mcu2_l2t1_rd_ack_d1; |
| 127 | reg mcu3_l2t0_rd_ack_d1; |
| 128 | reg mcu3_l2t1_rd_ack_d1; |
| 129 | |
| 130 | always @ (posedge `prefix_0in.l2clk) |
| 131 | begin |
| 132 | mcu0_l2t0_rd_ack_d1 <= `prefix_0in.mcu0.mcu_l2t0_rd_ack; |
| 133 | mcu0_l2t1_rd_ack_d1 <= `prefix_0in.mcu0.mcu_l2t1_rd_ack; |
| 134 | mcu1_l2t0_rd_ack_d1 <= `prefix_0in.mcu1.mcu_l2t0_rd_ack; |
| 135 | mcu1_l2t1_rd_ack_d1 <= `prefix_0in.mcu1.mcu_l2t1_rd_ack; |
| 136 | mcu2_l2t0_rd_ack_d1 <= `prefix_0in.mcu2.mcu_l2t0_rd_ack; |
| 137 | mcu2_l2t1_rd_ack_d1 <= `prefix_0in.mcu2.mcu_l2t1_rd_ack; |
| 138 | mcu3_l2t0_rd_ack_d1 <= `prefix_0in.mcu3.mcu_l2t0_rd_ack; |
| 139 | mcu3_l2t1_rd_ack_d1 <= `prefix_0in.mcu3.mcu_l2t1_rd_ack; |
| 140 | end |
| 141 | |
| 142 | |
| 143 | |
| 144 | |
| 145 | |
| 146 | |
| 147 | |
| 148 | |
| 149 | |
| 150 | |
| 151 | |
| 152 | |
| 153 | |
| 154 | /************Constraint C3.5**********/ |
| 155 | |
| 156 | |
| 157 | |
| 158 | /********The code below is for the constraints C3.2 and C3.4**********/ |
| 159 | reg[1:0] mcu0_l2t0_data_vld_count; |
| 160 | reg[1:0] mcu0_l2t1_data_vld_count; |
| 161 | reg[1:0] mcu1_l2t0_data_vld_count; |
| 162 | reg[1:0] mcu1_l2t1_data_vld_count; |
| 163 | reg[1:0] mcu2_l2t0_data_vld_count; |
| 164 | reg[1:0] mcu2_l2t1_data_vld_count; |
| 165 | reg[1:0] mcu3_l2t0_data_vld_count; |
| 166 | reg[1:0] mcu3_l2t1_data_vld_count; |
| 167 | |
| 168 | initial |
| 169 | begin |
| 170 | mcu0_l2t0_data_vld_count = 2'b0; |
| 171 | mcu0_l2t1_data_vld_count = 2'b0; |
| 172 | mcu1_l2t0_data_vld_count = 2'b0; |
| 173 | mcu1_l2t1_data_vld_count = 2'b0; |
| 174 | mcu2_l2t0_data_vld_count = 2'b0; |
| 175 | mcu2_l2t1_data_vld_count = 2'b0; |
| 176 | mcu3_l2t0_data_vld_count = 2'b0; |
| 177 | mcu3_l2t1_data_vld_count = 2'b0; |
| 178 | end |
| 179 | |
| 180 | always @(posedge `prefix_0in.l2clk) |
| 181 | begin |
| 182 | if(`prefix_0in.mcu0.mcu_l2t0_data_vld_r0) |
| 183 | mcu0_l2t0_data_vld_count = (mcu0_l2t0_data_vld_count + 1)%4; |
| 184 | if(`prefix_0in.mcu0.mcu_l2t1_data_vld_r0) |
| 185 | mcu0_l2t1_data_vld_count = (mcu0_l2t1_data_vld_count + 1)%4; |
| 186 | if(`prefix_0in.mcu1.mcu_l2t0_data_vld_r0) |
| 187 | mcu1_l2t0_data_vld_count = (mcu1_l2t0_data_vld_count + 1)%4; |
| 188 | if(`prefix_0in.mcu1.mcu_l2t1_data_vld_r0) |
| 189 | mcu1_l2t1_data_vld_count = (mcu1_l2t1_data_vld_count + 1)%4; |
| 190 | if(`prefix_0in.mcu2.mcu_l2t0_data_vld_r0) |
| 191 | mcu2_l2t0_data_vld_count = (mcu2_l2t0_data_vld_count + 1)%4; |
| 192 | if(`prefix_0in.mcu2.mcu_l2t1_data_vld_r0) |
| 193 | mcu2_l2t1_data_vld_count = (mcu2_l2t1_data_vld_count + 1)%4; |
| 194 | if(`prefix_0in.mcu3.mcu_l2t0_data_vld_r0) |
| 195 | mcu3_l2t0_data_vld_count = (mcu3_l2t0_data_vld_count + 1)%4; |
| 196 | if(`prefix_0in.mcu3.mcu_l2t1_data_vld_r0) |
| 197 | mcu3_l2t1_data_vld_count = (mcu3_l2t1_data_vld_count + 1)%4; |
| 198 | end |
| 199 | |
| 200 | /* 0in scoreboard -rx `prefix_0in.mcu0.l2t0_mcu_rd_req |
| 201 | -rx_id `prefix_0in.mcu0.l2t0_mcu_rd_req_id |
| 202 | -tx (`prefix_0in.mcu0.mcu_l2t0_data_vld_r0 & (mcu0_l2t0_data_vld_count == 3)) |
| 203 | -tx_id `prefix_0in.mcu0.mcu_l2t0_rd_req_id_r0 |
| 204 | -max_ids 8 |
| 205 | -clock `prefix_0in.l2clk |
| 206 | -constraint rx |
| 207 | */ |
| 208 | |
| 209 | /* 0in scoreboard -rx `prefix_0in.mcu0.l2t1_mcu_rd_req |
| 210 | -rx_id `prefix_0in.mcu0.l2t1_mcu_rd_req_id |
| 211 | -tx (`prefix_0in.mcu0.mcu_l2t1_data_vld_r0 & (mcu0_l2t1_data_vld_count == 3)) |
| 212 | -tx_id `prefix_0in.mcu0.mcu_l2t1_rd_req_id_r0 |
| 213 | -max_ids 8 |
| 214 | -clock `prefix_0in.l2clk |
| 215 | -constraint rx |
| 216 | */ |
| 217 | |
| 218 | /* 0in scoreboard -rx `prefix_0in.mcu1.l2t0_mcu_rd_req |
| 219 | -rx_id `prefix_0in.mcu1.l2t0_mcu_rd_req_id |
| 220 | -tx (`prefix_0in.mcu1.mcu_l2t0_data_vld_r0 & (mcu1_l2t0_data_vld_count == 3)) |
| 221 | -tx_id `prefix_0in.mcu1.mcu_l2t0_rd_req_id_r0 |
| 222 | -max_ids 8 |
| 223 | -clock `prefix_0in.l2clk |
| 224 | -constraint rx |
| 225 | */ |
| 226 | |
| 227 | /* 0in scoreboard -rx `prefix_0in.mcu1.l2t1_mcu_rd_req |
| 228 | -rx_id `prefix_0in.mcu1.l2t1_mcu_rd_req_id |
| 229 | -tx (`prefix_0in.mcu1.mcu_l2t1_data_vld_r0 & (mcu1_l2t1_data_vld_count == 3)) |
| 230 | -tx_id `prefix_0in.mcu1.mcu_l2t1_rd_req_id_r0 |
| 231 | -max_ids 8 |
| 232 | -clock `prefix_0in.l2clk |
| 233 | -constraint rx |
| 234 | */ |
| 235 | |
| 236 | /* 0in scoreboard -rx `prefix_0in.mcu2.l2t0_mcu_rd_req |
| 237 | -rx_id `prefix_0in.mcu2.l2t0_mcu_rd_req_id |
| 238 | -tx (`prefix_0in.mcu2.mcu_l2t0_data_vld_r0 & (mcu2_l2t0_data_vld_count == 3)) |
| 239 | -tx_id `prefix_0in.mcu2.mcu_l2t0_rd_req_id_r0 |
| 240 | -max_ids 8 |
| 241 | -clock `prefix_0in.l2clk |
| 242 | -constraint rx |
| 243 | */ |
| 244 | |
| 245 | /* 0in scoreboard -rx `prefix_0in.mcu2.l2t1_mcu_rd_req |
| 246 | -rx_id `prefix_0in.mcu2.l2t1_mcu_rd_req_id |
| 247 | -tx (`prefix_0in.mcu2.mcu_l2t1_data_vld_r0 & (mcu2_l2t1_data_vld_count == 3)) |
| 248 | -tx_id `prefix_0in.mcu2.mcu_l2t1_rd_req_id_r0 |
| 249 | -max_ids 8 |
| 250 | -clock `prefix_0in.l2clk |
| 251 | -constraint rx |
| 252 | */ |
| 253 | /* 0in scoreboard -rx `prefix_0in.mcu3.l2t0_mcu_rd_req |
| 254 | -rx_id `prefix_0in.mcu3.l2t0_mcu_rd_req_id |
| 255 | -tx (`prefix_0in.mcu3.mcu_l2t0_data_vld_r0 & (mcu3_l2t0_data_vld_count == 3)) |
| 256 | -tx_id `prefix_0in.mcu3.mcu_l2t0_rd_req_id_r0 |
| 257 | -max_ids 8 |
| 258 | -clock `prefix_0in.l2clk |
| 259 | -constraint rx |
| 260 | */ |
| 261 | |
| 262 | /* 0in scoreboard -rx `prefix_0in.mcu3.l2t1_mcu_rd_req |
| 263 | -rx_id `prefix_0in.mcu3.l2t1_mcu_rd_req_id |
| 264 | -tx (`prefix_0in.mcu3.mcu_l2t1_data_vld_r0 & (mcu3_l2t1_data_vld_count == 3)) |
| 265 | -tx_id `prefix_0in.mcu3.mcu_l2t1_rd_req_id_r0 |
| 266 | -max_ids 8 |
| 267 | -clock `prefix_0in.l2clk |
| 268 | -constraint rx |
| 269 | */ |
| 270 | |
| 271 | /************Constraint C4*************/ |
| 272 | |
| 273 | |
| 274 | |
| 275 | |
| 276 | |
| 277 | /* C5: WRITE REQUEST FROM L2. |
| 278 | |
| 279 | SIGNALS : |
| 280 | input l2t0_mcu_wr_req; |
| 281 | input l2t1_mcu_wr_req; |
| 282 | output mcu_l2t0_wr_ack; |
| 283 | output mcu_l2t1_wr_ack; |
| 284 | input [63:0] l2b0_mcu_wr_data_r5; |
| 285 | input [63:0] l2b1_mcu_wr_data_r5; |
| 286 | input l2b0_mcu_data_vld_r5; |
| 287 | input l2b1_mcu_data_vld_r5; |
| 288 | |
| 289 | CONSTRAINTS : |
| 290 | 1. Each write req is acknowledged by the MCU with mcu_l2t0/1_wr_ack. |
| 291 | 2. l2b0/1_mcu_data_vld_r5 is asserted after 5 clock cycles after |
| 292 | the wr_ack. |
| 293 | 3. l2b0/1_mcu_data_vld_r5 is active high for 8 clock cycles. |
| 294 | 4. l2b0/1_mcu_wr_data_r5 should be driven when data_vld_r5 is high. |
| 295 | 5. Back to back writes could be issued only after 3 clocks after |
| 296 | the last data word for write. |
| 297 | 6. (same as C3.5) No simultaneous rd and wr req from the same bank. |
| 298 | |
| 299 | Notes: |
| 300 | We can have simultaneous wr reqs from both the banks. |
| 301 | */ |
| 302 | |
| 303 | /************Constraint C5.1******************/ |
| 304 | /* 0in req_ack -req l2t0_mcu_wr_req |
| 305 | -ack mcu_l2t0_wr_ack |
| 306 | -no_simultaneous_req_ack |
| 307 | -constraint req |
| 308 | -module mcu -clock `prefix_0in.l2clk |
| 309 | */ |
| 310 | |
| 311 | /* 0in req_ack -req l2t1_mcu_wr_req |
| 312 | -ack mcu_l2t1_wr_ack |
| 313 | -no_simultaneous_req_ack |
| 314 | -constraint req |
| 315 | -module mcu -clock `prefix_0in.l2clk |
| 316 | */ |
| 317 | /***********Constraints C5.2 and C5.3**************/ |
| 318 | /* 0in assert_follower -leader mcu_l2t0_wr_ack -follower l2b0_mcu_data_vld_r5 |
| 319 | -max_leader 1 |
| 320 | -min 6 |
| 321 | -max 6 |
| 322 | -constraint |
| 323 | -module mcu -clock `prefix_0in.l2clk |
| 324 | */ |
| 325 | |
| 326 | /* 0in assert_follower -leader mcu_l2t1_wr_ack -follower l2b1_mcu_data_vld_r5 |
| 327 | -max_leader 1 |
| 328 | -min 6 |
| 329 | -max 6 |
| 330 | -constraint |
| 331 | -module mcu -clock `prefix_0in.l2clk |
| 332 | */ |
| 333 | |
| 334 | /* 0in assert_window -start mcu_l2t0_wr_ack |
| 335 | -in l2b0_mcu_data_vld_r5 |
| 336 | -stop_count 14 |
| 337 | -max 8 -min 8 |
| 338 | -constraint in |
| 339 | -module mcu -clock `prefix_0in.l2clk |
| 340 | */ |
| 341 | |
| 342 | /* 0in assert_window -start mcu_l2t1_wr_ack |
| 343 | -in l2b1_mcu_data_vld_r5 |
| 344 | -stop_count 14 |
| 345 | -max 8 -min 8 |
| 346 | -constraint in |
| 347 | -module mcu -clock `prefix_0in.l2clk |
| 348 | */ |
| 349 | |
| 350 | /***********Constraint C5.4**************/ |
| 351 | |
| 352 | |
| 353 | |
| 354 | /***********Constraint C5.5**************/ |
| 355 | /* 0in assert_window -start mcu_l2t0_wr_ack |
| 356 | -stop_count 13 |
| 357 | -not_in l2t0_mcu_wr_req |
| 358 | -constraint not_in |
| 359 | -module mcu -clock `prefix_0in.l2clk |
| 360 | */ |
| 361 | |
| 362 | /* 0in assert_window -start mcu_l2t1_wr_ack |
| 363 | -stop_count 13 |
| 364 | -not_in l2t1_mcu_wr_req |
| 365 | -constraint not_in |
| 366 | -module mcu -clock `prefix_0in.l2clk |
| 367 | */ |
| 368 | |
| 369 | |
| 370 | |
| 371 | /* C6: Inject ECC errors in write data. |
| 372 | |
| 373 | SIGNALS : |
| 374 | input l2b0_mcu_data_mecc_r5; |
| 375 | input l2b1_mcu_data_mecc_r5; |
| 376 | |
| 377 | CONSTRAINTS : |
| 378 | 1. Asserted along with l2b0/1_mcu_data_vld_r5. |
| 379 | |
| 380 | Notes: |
| 381 | Asserted along with l2b0_mcu_data_vld_r5. Only the |
| 382 | corresponding data words get errors injected on them. |
| 383 | */ |
| 384 | |
| 385 | |
| 386 | |
| 387 | |
| 388 | |
| 389 | |
| 390 | /* C7: Power throttling counter synchronizing signals |
| 391 | Whats the use ? Should these be constant ? |
| 392 | |
| 393 | Notes: |
| 394 | The mcu_pt_sync_in ports are tied to the mcu_pt_sync_out |
| 395 | ports of the other 3 MCUs. They are asserted whenever the |
| 396 | power throttling max time or max banks open registers are |
| 397 | written. This is so the power throttling counters in all |
| 398 | MCUs will be reset at the same time. |
| 399 | |
| 400 | // input mcu_pt_sync_in0; |
| 401 | // input mcu_pt_sync_in1; |
| 402 | // input mcu_pt_sync_in2; |
| 403 | */ |
| 404 | |
| 405 | |
| 406 | |
| 407 | /* C8: MCU id for error reporting. |
| 408 | Report what ? Report when ? |
| 409 | |
| 410 | Notes: |
| 411 | It is unique to each MCU. It goes into the dram error address |
| 412 | register so software can identify in which MCU an error |
| 413 | occurred. |
| 414 | |
| 415 | // input [1:0] mcu_id; |
| 416 | */ |
| 417 | |
| 418 | |
| 419 | /* C9.1: Debug Logic |
| 420 | |
| 421 | Signals: |
| 422 | mcu_dbg1_rd_req_in_0[3:0] Read request received from L2 bank 0 |
| 423 | mcu_dbg1_rd_req_in_1[3:0] Read request received from L2 bank 1 |
| 424 | |
| 425 | Property: |
| 426 | 1. Bit 3 is the rd_req signal. Bits 2:0 are the read request id |
| 427 | */ |
| 428 | /********** Property C9.1 **********/ |
| 429 | /* |
| 430 | 0in multi_clock_fifo |
| 431 | -enq (l2t0_mcu_rd_req && ~ucb.ucb_serdes_dtm) |
| 432 | -enq_data l2t0_mcu_rd_req_id |
| 433 | -enq_clock l2clk |
| 434 | -deq (mcu_dbg1_rd_req_in_0[3] && ~ucb.ucb_serdes_dtm) |
| 435 | -deq_data mcu_dbg1_rd_req_in_0[2:0] |
| 436 | -deq_clock iol2clk |
| 437 | -depth 8 |
| 438 | -module mcu |
| 439 | */ |
| 440 | |
| 441 | /* |
| 442 | 0in multi_clock_fifo |
| 443 | -enq (l2t1_mcu_rd_req && ~ucb.ucb_serdes_dtm) |
| 444 | -enq_data l2t1_mcu_rd_req_id |
| 445 | -enq_clock l2clk |
| 446 | -deq (mcu_dbg1_rd_req_in_1[3] && ~ucb.ucb_serdes_dtm) |
| 447 | -deq_data mcu_dbg1_rd_req_in_1[2:0] |
| 448 | -deq_clock iol2clk |
| 449 | -depth 8 |
| 450 | -module mcu |
| 451 | */ |
| 452 | |
| 453 | |
| 454 | /* C9.2: Debug Logic |
| 455 | |
| 456 | Signals: |
| 457 | mcu_dbg1_rd_req_out[4:0] Read data returned to L2 bank |
| 458 | |
| 459 | Property: |
| 460 | 2. Bit 4 is valid. Bit 3 indicates which l2 bank. Bits 2:0 are the |
| 461 | read request id |
| 462 | */ |
| 463 | /********** Property C9.2 **********/ |
| 464 | wire [2:0] mcu0_l2_rd_req_id; |
| 465 | wire [2:0] mcu1_l2_rd_req_id; |
| 466 | wire [2:0] mcu2_l2_rd_req_id; |
| 467 | wire [2:0] mcu3_l2_rd_req_id; |
| 468 | |
| 469 | assign mcu0_l2_rd_req_id = (`prefix_0in.mcu0.mcu_l2t1_data_vld_r0) ? `prefix_0in.mcu0.mcu_l2t1_rd_req_id_r0 : `prefix_0in.mcu0.mcu_l2t0_rd_req_id_r0; |
| 470 | assign mcu1_l2_rd_req_id = (`prefix_0in.mcu1.mcu_l2t1_data_vld_r0) ? `prefix_0in.mcu1.mcu_l2t1_rd_req_id_r0 : `prefix_0in.mcu1.mcu_l2t0_rd_req_id_r0; |
| 471 | assign mcu2_l2_rd_req_id = (`prefix_0in.mcu2.mcu_l2t1_data_vld_r0) ? `prefix_0in.mcu2.mcu_l2t1_rd_req_id_r0 : `prefix_0in.mcu2.mcu_l2t0_rd_req_id_r0; |
| 472 | assign mcu3_l2_rd_req_id = (`prefix_0in.mcu3.mcu_l2t1_data_vld_r0) ? `prefix_0in.mcu3.mcu_l2t1_rd_req_id_r0 : `prefix_0in.mcu3.mcu_l2t0_rd_req_id_r0; |
| 473 | |
| 474 | /* |
| 475 | 0in multi_clock_fifo |
| 476 | -enq (((`prefix_0in.mcu0.mcu_l2t0_data_vld_r0 && (`prefix_0in.mcu0.mcu_l2t0_qword_id_r0[1:0] == 2'b0)) || (`prefix_0in.mcu0.mcu_l2t1_data_vld_r0 && (`prefix_0in.mcu0.mcu_l2t1_qword_id_r0[1:0] == 2'b0))) && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) |
| 477 | -enq_data ({`prefix_0in.mcu0.mcu_l2t1_data_vld_r0, mcu0_l2_rd_req_id}) |
| 478 | -enq_clock `prefix_0in.mcu0.l2clk |
| 479 | -deq (`prefix_0in.mcu0.mcu_dbg1_rd_req_out[4] && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) |
| 480 | -deq_data `prefix_0in.mcu0.mcu_dbg1_rd_req_out[3:0] |
| 481 | -deq_clock `prefix_0in.mcu0.iol2clk |
| 482 | -depth 16 |
| 483 | -module mcu |
| 484 | */ |
| 485 | |
| 486 | /* |
| 487 | 0in multi_clock_fifo |
| 488 | -enq (((`prefix_0in.mcu1.mcu_l2t0_data_vld_r0 && (`prefix_0in.mcu1.mcu_l2t0_qword_id_r0[1:0] == 2'b0)) || (`prefix_0in.mcu1.mcu_l2t1_data_vld_r0 && (`prefix_0in.mcu1.mcu_l2t1_qword_id_r0[1:0] == 2'b0))) && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) |
| 489 | -enq_data ({`prefix_0in.mcu1.mcu_l2t1_data_vld_r0, mcu1_l2_rd_req_id}) |
| 490 | -enq_clock `prefix_0in.mcu1.l2clk |
| 491 | -deq (`prefix_0in.mcu1.mcu_dbg1_rd_req_out[4] && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) |
| 492 | -deq_data `prefix_0in.mcu1.mcu_dbg1_rd_req_out[3:0] |
| 493 | -deq_clock `prefix_0in.mcu1.iol2clk |
| 494 | -depth 16 |
| 495 | -module mcu |
| 496 | */ |
| 497 | |
| 498 | |
| 499 | /* |
| 500 | 0in multi_clock_fifo |
| 501 | -enq (((`prefix_0in.mcu2.mcu_l2t0_data_vld_r0 && (`prefix_0in.mcu2.mcu_l2t0_qword_id_r0[1:0] == 2'b0)) || (`prefix_0in.mcu2.mcu_l2t1_data_vld_r0 && (`prefix_0in.mcu2.mcu_l2t1_qword_id_r0[1:0] == 2'b0))) && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) |
| 502 | -enq_data ({`prefix_0in.mcu2.mcu_l2t1_data_vld_r0, mcu2_l2_rd_req_id}) |
| 503 | -enq_clock `prefix_0in.mcu2.l2clk |
| 504 | -deq (`prefix_0in.mcu2.mcu_dbg1_rd_req_out[4] && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) |
| 505 | -deq_data `prefix_0in.mcu2.mcu_dbg1_rd_req_out[3:0] |
| 506 | -deq_clock `prefix_0in.mcu2.iol2clk |
| 507 | -depth 16 |
| 508 | -module mcu |
| 509 | */ |
| 510 | |
| 511 | |
| 512 | /* |
| 513 | 0in multi_clock_fifo |
| 514 | -enq (((`prefix_0in.mcu3.mcu_l2t0_data_vld_r0 && (`prefix_0in.mcu3.mcu_l2t0_qword_id_r0[1:0] == 2'b0)) || (`prefix_0in.mcu3.mcu_l2t1_data_vld_r0 && (`prefix_0in.mcu3.mcu_l2t1_qword_id_r0[1:0] == 2'b0))) && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) |
| 515 | -enq_data ({`prefix_0in.mcu3.mcu_l2t1_data_vld_r0, mcu3_l2_rd_req_id}) |
| 516 | -enq_clock `prefix_0in.mcu3.l2clk |
| 517 | -deq (`prefix_0in.mcu3.mcu_dbg1_rd_req_out[4] && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) |
| 518 | -deq_data `prefix_0in.mcu3.mcu_dbg1_rd_req_out[3:0] |
| 519 | -deq_clock `prefix_0in.mcu3.iol2clk |
| 520 | -depth 16 |
| 521 | -module mcu |
| 522 | */ |
| 523 | |
| 524 | |
| 525 | |
| 526 | /* C9.3: Debug Logic |
| 527 | |
| 528 | Signals: |
| 529 | mcu_dbg1_wr_req_in_0 Write request received from L2 bank 0 |
| 530 | mcu_dbg1_wr_req_in_1 Write request received from L2 bank 1 |
| 531 | |
| 532 | Property: |
| 533 | 3. wr_req signal |
| 534 | */ |
| 535 | /********** Property C9.3 **********/ |
| 536 | /* |
| 537 | 0in multi_clock_fifo |
| 538 | -enq (l2t0_mcu_wr_req && ~ucb.ucb_serdes_dtm) |
| 539 | -enq_clock l2clk |
| 540 | -deq (mcu_dbg1_wr_req_in_0 && ~ucb.ucb_serdes_dtm) |
| 541 | -deq_clock iol2clk |
| 542 | -depth 8 |
| 543 | -module mcu |
| 544 | */ |
| 545 | |
| 546 | /* |
| 547 | 0in multi_clock_fifo |
| 548 | -enq (l2t1_mcu_wr_req && ~ucb.ucb_serdes_dtm) |
| 549 | -enq_clock l2clk |
| 550 | -deq (mcu_dbg1_wr_req_in_1 && ~ucb.ucb_serdes_dtm) |
| 551 | -deq_clock iol2clk |
| 552 | -depth 8 |
| 553 | -module mcu |
| 554 | */ |
| 555 | |
| 556 | |
| 557 | |
| 558 | /* C9.4: Debug Logic |
| 559 | |
| 560 | Signals: |
| 561 | mcu_dbg1_wr_req_out[1:0] Number of writes retired |
| 562 | |
| 563 | Property: |
| 564 | 4. Number of writes retired from outstanding write queue in woq |
| 565 | */ |
| 566 | /********** Property C9.4 **********/ |
| 567 | /* |
| 568 | 0in multi_clock_multi_enq_deq_fifo |
| 569 | -enq (drif.drif_woq_free[1] && ~ucb.ucb_serdes_dtm) (drif.drif_woq_free[0] && ~ucb.ucb_serdes_dtm) |
| 570 | -enq_clock drl2clk |
| 571 | -deq (mcu_dbg1_wr_req_out[1] && ~ucb.ucb_serdes_dtm) (mcu_dbg1_wr_req_out[0] && ~ucb.ucb_serdes_dtm) |
| 572 | -deq_clock iol2clk |
| 573 | -depth 16 |
| 574 | -module mcu |
| 575 | */ |
| 576 | |
| 577 | |
| 578 | /* C9.5: Debug Logic |
| 579 | |
| 580 | Signals: |
| 581 | mcu_dbg1_mecc_err Multiple nibble ECC error |
| 582 | |
| 583 | Property: |
| 584 | 5. OR of mecc_err and scb_mecc_err for both l2 banks |
| 585 | */ |
| 586 | /********** Property C9.5 **********/ |
| 587 | reg mcu0_mecc_err_enq; |
| 588 | wire mcu0_mecc_err = (`prefix_0in.mcu0.mcu_l2t0_mecc_err_r3 || `prefix_0in.mcu0.mcu_l2t1_mecc_err_r3 || `prefix_0in.mcu0.mcu_l2t0_scb_mecc_err || `prefix_0in.mcu0.mcu_l2t1_scb_mecc_err); |
| 589 | reg mcu1_mecc_err_enq; |
| 590 | wire mcu1_mecc_err = (`prefix_0in.mcu1.mcu_l2t0_mecc_err_r3 || `prefix_0in.mcu1.mcu_l2t1_mecc_err_r3 || `prefix_0in.mcu1.mcu_l2t0_scb_mecc_err || `prefix_0in.mcu1.mcu_l2t1_scb_mecc_err); |
| 591 | reg mcu2_mecc_err_enq; |
| 592 | wire mcu2_mecc_err = (`prefix_0in.mcu2.mcu_l2t0_mecc_err_r3 || `prefix_0in.mcu2.mcu_l2t1_mecc_err_r3 || `prefix_0in.mcu2.mcu_l2t0_scb_mecc_err || `prefix_0in.mcu2.mcu_l2t1_scb_mecc_err); |
| 593 | reg mcu3_mecc_err_enq; |
| 594 | wire mcu3_mecc_err = (`prefix_0in.mcu3.mcu_l2t0_mecc_err_r3 || `prefix_0in.mcu3.mcu_l2t1_mecc_err_r3 || `prefix_0in.mcu3.mcu_l2t0_scb_mecc_err || `prefix_0in.mcu3.mcu_l2t1_scb_mecc_err); |
| 595 | |
| 596 | reg mcu0_dummy_dbg_mecc_err; |
| 597 | reg mcu1_dummy_dbg_mecc_err; |
| 598 | reg mcu2_dummy_dbg_mecc_err; |
| 599 | reg mcu3_dummy_dbg_mecc_err; |
| 600 | |
| 601 | initial |
| 602 | begin |
| 603 | mcu0_mecc_err_enq = 1'b0; |
| 604 | mcu1_mecc_err_enq = 1'b0; |
| 605 | mcu2_mecc_err_enq = 1'b0; |
| 606 | mcu3_mecc_err_enq = 1'b0; |
| 607 | mcu0_dummy_dbg_mecc_err = 1'b0; |
| 608 | mcu1_dummy_dbg_mecc_err = 1'b0; |
| 609 | mcu2_dummy_dbg_mecc_err = 1'b0; |
| 610 | mcu3_dummy_dbg_mecc_err = 1'b0; |
| 611 | end |
| 612 | |
| 613 | always @(posedge mcu0_mecc_err) |
| 614 | begin |
| 615 | mcu0_mecc_err_enq = 1'b1; |
| 616 | @(posedge `prefix_0in.mcu0.l2clk); |
| 617 | mcu0_mecc_err_enq = 1'b0; |
| 618 | end |
| 619 | |
| 620 | always @(posedge mcu1_mecc_err) |
| 621 | begin |
| 622 | mcu1_mecc_err_enq = 1'b1; |
| 623 | @(posedge `prefix_0in.mcu1.l2clk); |
| 624 | mcu1_mecc_err_enq = 1'b0; |
| 625 | end |
| 626 | |
| 627 | always @(posedge mcu2_mecc_err) |
| 628 | begin |
| 629 | mcu2_mecc_err_enq = 1'b1; |
| 630 | @(posedge `prefix_0in.mcu2.l2clk); |
| 631 | mcu2_mecc_err_enq = 1'b0; |
| 632 | end |
| 633 | |
| 634 | always @(posedge mcu3_mecc_err) |
| 635 | begin |
| 636 | mcu3_mecc_err_enq = 1'b1; |
| 637 | @(posedge `prefix_0in.mcu3.l2clk); |
| 638 | mcu3_mecc_err_enq = 1'b0; |
| 639 | end |
| 640 | |
| 641 | always @(posedge `prefix_0in.mcu0.rdata.rdata_cmp_io_sync_en) |
| 642 | begin |
| 643 | if(mcu0_mecc_err) begin |
| 644 | mcu0_dummy_dbg_mecc_err = 1'b1; |
| 645 | @(posedge `prefix_0in.mcu0.l2clk); |
| 646 | mcu0_dummy_dbg_mecc_err = 1'b0; |
| 647 | end |
| 648 | end |
| 649 | |
| 650 | always @(posedge `prefix_0in.mcu1.rdata.rdata_cmp_io_sync_en) |
| 651 | begin |
| 652 | if(mcu1_mecc_err) begin |
| 653 | mcu1_dummy_dbg_mecc_err = 1'b1; |
| 654 | @(posedge `prefix_0in.mcu1.l2clk); |
| 655 | mcu1_dummy_dbg_mecc_err = 1'b0; |
| 656 | end |
| 657 | end |
| 658 | |
| 659 | always @(posedge `prefix_0in.mcu2.rdata.rdata_cmp_io_sync_en) |
| 660 | begin |
| 661 | if(mcu2_mecc_err) begin |
| 662 | mcu2_dummy_dbg_mecc_err = 1'b1; |
| 663 | @(posedge `prefix_0in.mcu2.l2clk); |
| 664 | mcu2_dummy_dbg_mecc_err = 1'b0; |
| 665 | end |
| 666 | end |
| 667 | |
| 668 | always @(posedge `prefix_0in.mcu3.rdata.rdata_cmp_io_sync_en) |
| 669 | begin |
| 670 | if(mcu3_mecc_err) begin |
| 671 | mcu3_dummy_dbg_mecc_err = 1'b1; |
| 672 | @(posedge `prefix_0in.mcu3.l2clk); |
| 673 | mcu3_dummy_dbg_mecc_err = 1'b0; |
| 674 | end |
| 675 | end |
| 676 | |
| 677 | |
| 678 | /* |
| 679 | 0in multi_clock_multi_enq_deq_fifo |
| 680 | -enq (mcu0_mecc_err_enq && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) (mcu0_dummy_dbg_mecc_err && ~mcu0_mecc_err_enq && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) |
| 681 | -enq_clock `prefix_0in.mcu0.l2clk |
| 682 | -deq (`prefix_0in.mcu0.mcu_dbg1_mecc_err && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) |
| 683 | -deq_clock `prefix_0in.mcu0.iol2clk |
| 684 | -depth 200 |
| 685 | -module mcu |
| 686 | */ |
| 687 | |
| 688 | /* |
| 689 | 0in multi_clock_multi_enq_deq_fifo |
| 690 | -enq (mcu1_mecc_err_enq && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) (mcu1_dummy_dbg_mecc_err && ~mcu1_mecc_err_enq && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) |
| 691 | -enq_clock `prefix_0in.mcu1.l2clk |
| 692 | -deq (`prefix_0in.mcu1.mcu_dbg1_mecc_err && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) |
| 693 | -deq_clock `prefix_0in.mcu1.iol2clk |
| 694 | -depth 200 |
| 695 | -module mcu |
| 696 | */ |
| 697 | |
| 698 | /* |
| 699 | 0in multi_clock_multi_enq_deq_fifo |
| 700 | -enq (mcu2_mecc_err_enq && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) (mcu2_dummy_dbg_mecc_err && ~mcu2_mecc_err_enq && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) |
| 701 | -enq_clock `prefix_0in.mcu2.l2clk |
| 702 | -deq (`prefix_0in.mcu2.mcu_dbg1_mecc_err && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) |
| 703 | -deq_clock `prefix_0in.mcu2.iol2clk |
| 704 | -depth 200 |
| 705 | -module mcu |
| 706 | */ |
| 707 | |
| 708 | /* |
| 709 | 0in multi_clock_multi_enq_deq_fifo |
| 710 | -enq (mcu3_mecc_err_enq && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) (mcu3_dummy_dbg_mecc_err && ~mcu3_mecc_err_enq && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) |
| 711 | -enq_clock `prefix_0in.mcu3.l2clk |
| 712 | -deq (`prefix_0in.mcu3.mcu_dbg1_mecc_err && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) |
| 713 | -deq_clock `prefix_0in.mcu3.iol2clk |
| 714 | -depth 200 |
| 715 | -module mcu |
| 716 | */ |
| 717 | |
| 718 | |
| 719 | /* C9.6: Debug Logic |
| 720 | |
| 721 | Signals: |
| 722 | mcu_dbg1_secc_err Single nibble ECC error |
| 723 | |
| 724 | Property: |
| 725 | 6. OR of secc_err and scb_secc_err for both l2 banks |
| 726 | */ |
| 727 | /********** Property C9.6 **********/ |
| 728 | reg mcu0_secc_err_enq; |
| 729 | wire mcu0_secc_err = (`prefix_0in.mcu0.mcu_l2t0_secc_err_r3 || `prefix_0in.mcu0.mcu_l2t1_secc_err_r3 || `prefix_0in.mcu0.mcu_l2t0_scb_secc_err || `prefix_0in.mcu0.mcu_l2t1_scb_secc_err); |
| 730 | reg mcu1_secc_err_enq; |
| 731 | wire mcu1_secc_err = (`prefix_0in.mcu1.mcu_l2t0_secc_err_r3 || `prefix_0in.mcu1.mcu_l2t1_secc_err_r3 || `prefix_0in.mcu1.mcu_l2t0_scb_secc_err || `prefix_0in.mcu1.mcu_l2t1_scb_secc_err); |
| 732 | reg mcu2_secc_err_enq; |
| 733 | wire mcu2_secc_err = (`prefix_0in.mcu2.mcu_l2t0_secc_err_r3 || `prefix_0in.mcu2.mcu_l2t1_secc_err_r3 || `prefix_0in.mcu2.mcu_l2t0_scb_secc_err || `prefix_0in.mcu2.mcu_l2t1_scb_secc_err); |
| 734 | reg mcu3_secc_err_enq; |
| 735 | wire mcu3_secc_err = (`prefix_0in.mcu3.mcu_l2t0_secc_err_r3 || `prefix_0in.mcu3.mcu_l2t1_secc_err_r3 || `prefix_0in.mcu3.mcu_l2t0_scb_secc_err || `prefix_0in.mcu3.mcu_l2t1_scb_secc_err); |
| 736 | |
| 737 | reg mcu0_dummy_secc_err; |
| 738 | reg mcu1_dummy_secc_err; |
| 739 | reg mcu2_dummy_secc_err; |
| 740 | reg mcu3_dummy_secc_err; |
| 741 | |
| 742 | initial |
| 743 | begin |
| 744 | mcu0_secc_err_enq = 1'b0; |
| 745 | mcu1_secc_err_enq = 1'b0; |
| 746 | mcu2_secc_err_enq = 1'b0; |
| 747 | mcu3_secc_err_enq = 1'b0; |
| 748 | mcu0_dummy_secc_err = 1'b0; |
| 749 | mcu1_dummy_secc_err = 1'b0; |
| 750 | mcu2_dummy_secc_err = 1'b0; |
| 751 | mcu3_dummy_secc_err = 1'b0; |
| 752 | end |
| 753 | |
| 754 | always @(posedge mcu0_secc_err) |
| 755 | begin |
| 756 | mcu0_secc_err_enq = 1'b1; |
| 757 | @(posedge `prefix_0in.mcu0.l2clk); |
| 758 | mcu0_secc_err_enq = 1'b0; |
| 759 | end |
| 760 | |
| 761 | always @(posedge mcu1_secc_err) |
| 762 | begin |
| 763 | mcu1_secc_err_enq = 1'b1; |
| 764 | @(posedge `prefix_0in.mcu1.l2clk); |
| 765 | mcu1_secc_err_enq = 1'b0; |
| 766 | end |
| 767 | |
| 768 | always @(posedge mcu2_secc_err) |
| 769 | begin |
| 770 | mcu2_secc_err_enq = 1'b1; |
| 771 | @(posedge `prefix_0in.mcu2.l2clk); |
| 772 | mcu2_secc_err_enq = 1'b0; |
| 773 | end |
| 774 | |
| 775 | always @(posedge mcu3_secc_err) |
| 776 | begin |
| 777 | mcu3_secc_err_enq = 1'b1; |
| 778 | @(posedge `prefix_0in.mcu3.l2clk); |
| 779 | mcu3_secc_err_enq = 1'b0; |
| 780 | end |
| 781 | |
| 782 | always @(posedge `prefix_0in.mcu0.rdata.rdata_cmp_io_sync_en) |
| 783 | begin |
| 784 | if(mcu0_secc_err) begin |
| 785 | mcu0_dummy_secc_err = 1'b1; |
| 786 | @(posedge `prefix_0in.mcu0.l2clk); |
| 787 | mcu0_dummy_secc_err = 1'b0; |
| 788 | end |
| 789 | end |
| 790 | |
| 791 | always @(posedge `prefix_0in.mcu1.rdata.rdata_cmp_io_sync_en) |
| 792 | begin |
| 793 | if(mcu1_secc_err) begin |
| 794 | mcu1_dummy_secc_err = 1'b1; |
| 795 | @(posedge `prefix_0in.mcu1.l2clk); |
| 796 | mcu1_dummy_secc_err = 1'b0; |
| 797 | end |
| 798 | end |
| 799 | |
| 800 | always @(posedge `prefix_0in.mcu2.rdata.rdata_cmp_io_sync_en) |
| 801 | begin |
| 802 | if(mcu2_secc_err) begin |
| 803 | mcu2_dummy_secc_err = 1'b1; |
| 804 | @(posedge `prefix_0in.mcu2.l2clk); |
| 805 | mcu2_dummy_secc_err = 1'b0; |
| 806 | end |
| 807 | end |
| 808 | |
| 809 | always @(posedge `prefix_0in.mcu3.rdata.rdata_cmp_io_sync_en) |
| 810 | begin |
| 811 | if(mcu3_secc_err) begin |
| 812 | mcu3_dummy_secc_err = 1'b1; |
| 813 | @(posedge `prefix_0in.mcu3.l2clk); |
| 814 | mcu3_dummy_secc_err = 1'b0; |
| 815 | end |
| 816 | end |
| 817 | |
| 818 | |
| 819 | /* |
| 820 | 0in multi_clock_multi_enq_deq_fifo |
| 821 | -enq (mcu0_secc_err_enq && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) (mcu0_dummy_secc_err && ~mcu0_secc_err_enq && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) |
| 822 | -enq_clock `prefix_0in.mcu0.l2clk |
| 823 | -deq (`prefix_0in.mcu0.mcu_dbg1_secc_err && ~`prefix_0in.mcu0.ucb.ucb_serdes_dtm) |
| 824 | -deq_clock `prefix_0in.mcu0.iol2clk |
| 825 | -depth 200 |
| 826 | -module mcu |
| 827 | */ |
| 828 | |
| 829 | /* |
| 830 | 0in multi_clock_multi_enq_deq_fifo |
| 831 | -enq (mcu1_secc_err_enq && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) (mcu1_dummy_secc_err && ~mcu1_secc_err_enq && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) |
| 832 | -enq_clock `prefix_0in.mcu1.l2clk |
| 833 | -deq (`prefix_0in.mcu1.mcu_dbg1_secc_err && ~`prefix_0in.mcu1.ucb.ucb_serdes_dtm) |
| 834 | -deq_clock `prefix_0in.mcu1.iol2clk |
| 835 | -depth 200 |
| 836 | -module mcu |
| 837 | */ |
| 838 | |
| 839 | /* |
| 840 | 0in multi_clock_multi_enq_deq_fifo |
| 841 | -enq (mcu2_secc_err_enq && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) (mcu2_dummy_secc_err && ~mcu2_secc_err_enq && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) |
| 842 | -enq_clock `prefix_0in.mcu2.l2clk |
| 843 | -deq (`prefix_0in.mcu2.mcu_dbg1_secc_err && ~`prefix_0in.mcu2.ucb.ucb_serdes_dtm) |
| 844 | -deq_clock `prefix_0in.mcu2.iol2clk |
| 845 | -depth 200 |
| 846 | -module mcu |
| 847 | */ |
| 848 | |
| 849 | /* |
| 850 | 0in multi_clock_multi_enq_deq_fifo |
| 851 | -enq (mcu3_secc_err_enq && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) (mcu3_dummy_secc_err && ~mcu3_secc_err_enq && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) |
| 852 | -enq_clock `prefix_0in.mcu3.l2clk |
| 853 | -deq (`prefix_0in.mcu3.mcu_dbg1_secc_err && ~`prefix_0in.mcu3.ucb.ucb_serdes_dtm) |
| 854 | -deq_clock `prefix_0in.mcu3.iol2clk |
| 855 | -depth 200 |
| 856 | -module mcu |
| 857 | */ |
| 858 | |
| 859 | |
| 860 | /* C9.7: Debug Logic |
| 861 | |
| 862 | Signals: |
| 863 | mcu_dbg1_fbd_err FBD channel error |
| 864 | |
| 865 | Property: |
| 866 | 7. Any FBU or FBR error |
| 867 | */ |
| 868 | /********** Property C9.7 **********/ |
| 869 | /* |
| 870 | 0in multi_clock_fifo |
| 871 | -enq (fbdic.fbdic_fbd_error_in && ~ucb.ucb_serdes_dtm) |
| 872 | -enq_clock drl2clk |
| 873 | -deq (mcu_dbg1_fbd_err && ~ucb.ucb_serdes_dtm) |
| 874 | -deq_clock iol2clk |
| 875 | -depth 200 |
| 876 | -enqueue off |
| 877 | -module mcu |
| 878 | */ |
| 879 | |
| 880 | /* C9.8: Debug Logic |
| 881 | |
| 882 | Signals: |
| 883 | mcu_dbg1_err_mode MCU in error processing mode |
| 884 | |
| 885 | Property: |
| 886 | 8. Asserted when MCU is processing an error, i.e. error state machines are not in |
| 887 | idle state. |
| 888 | */ |
| 889 | /********** Property C9.8 **********/ |
| 890 | /* XXX |
| 891 | 0in multi_clock_fifo |
| 892 | -enq (($0in_rising_edge(drif.drif_mcu_error_mode) || $0in_falling_edge(drif.drif_mcu_error_mode)) && ~ucb.ucb_serdes_dtm) |
| 893 | -enq_clock drl2clk |
| 894 | -deq (($0in_rising_edge(mcu_dbg1_err_mode) || $0in_falling_edge(mcu_dbg1_err_mode)) && ~ucb.ucb_serdes_dtm) |
| 895 | -deq_clock iol2clk |
| 896 | -depth 50 |
| 897 | -module mcu |
| 898 | */ |
| 899 | |
| 900 | |
| 901 | /* C9.9: Debug Logic |
| 902 | |
| 903 | Signals: |
| 904 | mcu_dbg1_err_event Debug error event when debug trigger is enabled |
| 905 | |
| 906 | Property: |
| 907 | 9. Enabled by debug trigger enable register. Asserted for and mecc, secc or fbd error. |
| 908 | */ |
| 909 | /********** Property C9.9 **********/ |
| 910 | /* |
| 911 | 0in multi_clock_fifo |
| 912 | -enq ((rdpctl.rdpctl_dbg_trig_enable && (mcu_l2t0_mecc_err_r3 || mcu_l2t1_mecc_err_r3 || mcu_l2t0_scb_mecc_err || mcu_l2t1_scb_mecc_err || mcu_l2t0_secc_err_r3 || mcu_l2t1_secc_err_r3 || mcu_l2t0_scb_secc_err || mcu_l2t1_scb_secc_err)) && ~ucb.ucb_serdes_dtm) |
| 913 | -enq_clock l2clk |
| 914 | -deq ((rdpctl.rdpctl_dbg_trig_enable && mcu_dbg1_err_event) && ~ucb.ucb_serdes_dtm) |
| 915 | -deq_clock iol2clk |
| 916 | -depth 32 |
| 917 | -module mcu |
| 918 | */ |
| 919 | |
| 920 | /* C9.10: Debug Logic |
| 921 | |
| 922 | Signals: |
| 923 | {mcu_dbg1_crc21,mcu_dbg1_rd_req_in_0[3:0],mcu_dbg1_rd_req_in_1[3:0],mcu_dbg1_rd_req_out[4:0],mcu_dbg1_wr_req_in_0,mcu_dbg1_wr_req_in_1,mcu_dbg1_wr_req_out[1:0],mcu_dbg1_mecc_err,mcu_dbg1_secc_err,mcu_dbg1_fbd_err,mcu_dbg1_err_mode} == crc in dtm mode |
| 924 | |
| 925 | Property: |
| 926 | 10. In DTM mode, crc is transmitted on dbg signals |
| 927 | |
| 928 | */ |
| 929 | /********** Property C9.10 **********/ |
| 930 | |
| 931 | wire [21:0] mcu0_dbg1_crc = {`prefix_0in.mcu0.mcu_dbg1_crc21,`prefix_0in.mcu0.mcu_dbg1_rd_req_in_0[3:0],`prefix_0in.mcu0.mcu_dbg1_rd_req_in_1[3:0],`prefix_0in.mcu0.mcu_dbg1_rd_req_out[4:0],`prefix_0in.mcu0.mcu_dbg1_wr_req_in_0,`prefix_0in.mcu0.mcu_dbg1_wr_req_in_1,`prefix_0in.mcu0.mcu_dbg1_wr_req_out[1:0],`prefix_0in.mcu0.mcu_dbg1_mecc_err,`prefix_0in.mcu0.mcu_dbg1_secc_err,`prefix_0in.mcu0.mcu_dbg1_fbd_err,`prefix_0in.mcu0.mcu_dbg1_err_mode}; |
| 932 | |
| 933 | wire [21:0] mcu1_dbg1_crc = {`prefix_0in.mcu1.mcu_dbg1_crc21,`prefix_0in.mcu1.mcu_dbg1_rd_req_in_0[3:0],`prefix_0in.mcu1.mcu_dbg1_rd_req_in_1[3:0],`prefix_0in.mcu1.mcu_dbg1_rd_req_out[4:0],`prefix_0in.mcu1.mcu_dbg1_wr_req_in_0,`prefix_0in.mcu1.mcu_dbg1_wr_req_in_1,`prefix_0in.mcu1.mcu_dbg1_wr_req_out[1:0],`prefix_0in.mcu1.mcu_dbg1_mecc_err,`prefix_0in.mcu1.mcu_dbg1_secc_err,`prefix_0in.mcu1.mcu_dbg1_fbd_err,`prefix_0in.mcu1.mcu_dbg1_err_mode}; |
| 934 | |
| 935 | wire [21:0] mcu2_dbg1_crc = {`prefix_0in.mcu2.mcu_dbg1_crc21,`prefix_0in.mcu2.mcu_dbg1_rd_req_in_0[3:0],`prefix_0in.mcu2.mcu_dbg1_rd_req_in_1[3:0],`prefix_0in.mcu2.mcu_dbg1_rd_req_out[4:0],`prefix_0in.mcu2.mcu_dbg1_wr_req_in_0,`prefix_0in.mcu2.mcu_dbg1_wr_req_in_1,`prefix_0in.mcu2.mcu_dbg1_wr_req_out[1:0],`prefix_0in.mcu2.mcu_dbg1_mecc_err,`prefix_0in.mcu2.mcu_dbg1_secc_err,`prefix_0in.mcu2.mcu_dbg1_fbd_err,`prefix_0in.mcu2.mcu_dbg1_err_mode}; |
| 936 | |
| 937 | wire [21:0] mcu3_dbg1_crc = {`prefix_0in.mcu3.mcu_dbg1_crc21,`prefix_0in.mcu3.mcu_dbg1_rd_req_in_0[3:0],`prefix_0in.mcu3.mcu_dbg1_rd_req_in_1[3:0],`prefix_0in.mcu3.mcu_dbg1_rd_req_out[4:0],`prefix_0in.mcu3.mcu_dbg1_wr_req_in_0,`prefix_0in.mcu3.mcu_dbg1_wr_req_in_1,`prefix_0in.mcu3.mcu_dbg1_wr_req_out[1:0],`prefix_0in.mcu3.mcu_dbg1_mecc_err,`prefix_0in.mcu3.mcu_dbg1_secc_err,`prefix_0in.mcu3.mcu_dbg1_fbd_err,`prefix_0in.mcu3.mcu_dbg1_err_mode}; |
| 938 | |
| 939 | /* |
| 940 | 0in multi_clock_fifo |
| 941 | -enq (`prefix_0in.mcu0.ucb.ucb_serdes_dtm && (|(`prefix_0in.mcu0.fbdiwr.ch0_crc ^ `prefix_0in.mcu0.fbdiwr.ch1_crc))) |
| 942 | -enq_data ((`prefix_0in.mcu0.fbdiwr.ch0_crc ^ `prefix_0in.mcu0.fbdiwr.ch1_crc)) |
| 943 | -enq_clock `prefix_0in.mcu0.drl2clk |
| 944 | -deq (`prefix_0in.mcu0.ucb.ucb_serdes_dtm && (|mcu0_dbg1_crc)) |
| 945 | -deq_data mcu0_dbg1_crc |
| 946 | -deq_clock `prefix_0in.mcu0.iol2clk |
| 947 | -depth 8 |
| 948 | -module mcu |
| 949 | */ |
| 950 | |
| 951 | /* |
| 952 | 0in multi_clock_fifo |
| 953 | -enq (`prefix_0in.mcu1.ucb.ucb_serdes_dtm && (|(`prefix_0in.mcu1.fbdiwr.ch0_crc ^ `prefix_0in.mcu1.fbdiwr.ch1_crc))) |
| 954 | -enq_data ((`prefix_0in.mcu1.fbdiwr.ch0_crc ^ `prefix_0in.mcu1.fbdiwr.ch1_crc)) |
| 955 | -enq_clock `prefix_0in.mcu1.drl2clk |
| 956 | -deq (`prefix_0in.mcu1.ucb.ucb_serdes_dtm && (|mcu1_dbg1_crc)) |
| 957 | -deq_data mcu1_dbg1_crc |
| 958 | -deq_clock `prefix_0in.mcu1.iol2clk |
| 959 | -depth 8 |
| 960 | -module mcu |
| 961 | */ |
| 962 | |
| 963 | /* |
| 964 | 0in multi_clock_fifo |
| 965 | -enq (`prefix_0in.mcu2.ucb.ucb_serdes_dtm && (|(`prefix_0in.mcu2.fbdiwr.ch0_crc ^ `prefix_0in.mcu2.fbdiwr.ch1_crc))) |
| 966 | -enq_data ((`prefix_0in.mcu2.fbdiwr.ch0_crc ^ `prefix_0in.mcu2.fbdiwr.ch1_crc)) |
| 967 | -enq_clock `prefix_0in.mcu2.drl2clk |
| 968 | -deq (`prefix_0in.mcu2.ucb.ucb_serdes_dtm && (|mcu2_dbg1_crc)) |
| 969 | -deq_data mcu2_dbg1_crc |
| 970 | -deq_clock `prefix_0in.mcu2.iol2clk |
| 971 | -depth 8 |
| 972 | -module mcu |
| 973 | */ |
| 974 | |
| 975 | /* |
| 976 | 0in multi_clock_fifo |
| 977 | -enq (`prefix_0in.mcu3.ucb.ucb_serdes_dtm && (|(`prefix_0in.mcu3.fbdiwr.ch0_crc ^ `prefix_0in.mcu3.fbdiwr.ch1_crc))) |
| 978 | -enq_data ((`prefix_0in.mcu3.fbdiwr.ch0_crc ^ `prefix_0in.mcu3.fbdiwr.ch1_crc)) |
| 979 | -enq_clock `prefix_0in.mcu3.drl2clk |
| 980 | -deq (`prefix_0in.mcu3.ucb.ucb_serdes_dtm && (|mcu3_dbg1_crc)) |
| 981 | -deq_data mcu3_dbg1_crc |
| 982 | -deq_clock `prefix_0in.mcu3.iol2clk |
| 983 | -depth 8 |
| 984 | -module mcu |
| 985 | */ |
| 986 | |
| 987 | |
| 988 | |
| 989 | |
| 990 | `endif |
| 991 | |
| 992 | initial |
| 993 | begin |
| 994 | if($test$plusargs("dump_checkers")) |
| 995 | $fsdbDumpvars(0,mcul2_intf_chkr); |
| 996 | end |
| 997 | |
| 998 | endmodule |