| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: core_sync.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifdef CORE_0 |
| 36 | |
| 37 | module core_sync_c0(); |
| 38 | `ifndef GATESIM |
| 39 | |
| 40 | // common defines |
| 41 | `include "defines.vh" |
| 42 | |
| 43 | wire [64:0] tlu_rng; |
| 44 | wire [63:0] rng_value; |
| 45 | wire [2:0] rng_tid; |
| 46 | reg [2:0] rng_tid_1; |
| 47 | wire tick_rd; |
| 48 | reg tick_rd_1; |
| 49 | wire stick_rd; |
| 50 | reg stick_rd_1; |
| 51 | |
| 52 | wire hwtwPending_rd; |
| 53 | reg hwtwPending_rd_1; |
| 54 | |
| 55 | //--------------------- |
| 56 | // PMU |
| 57 | |
| 58 | wire [64:0] pmu_rng; |
| 59 | wire [63:0] pmu_rng_value; |
| 60 | wire [2:0] pmu_rng_tid; |
| 61 | reg [2:0] pmu_rng_tid_1; |
| 62 | |
| 63 | wire [64:0] pmu_rng_in; |
| 64 | |
| 65 | wire pcr_rd; |
| 66 | reg pcr_rd_1; |
| 67 | wire pic_rd; |
| 68 | reg pic_rd_1; |
| 69 | |
| 70 | reg pcr_rd_2; |
| 71 | reg pic_rd_2; |
| 72 | reg [2:0] pmu_rng_tid_2; |
| 73 | |
| 74 | reg pcr_rd_3; |
| 75 | reg pic_rd_3; |
| 76 | reg [2:0] pmu_rng_tid_3; |
| 77 | |
| 78 | reg [5:0] pmu_tnum; |
| 79 | |
| 80 | //--------------------- |
| 81 | // Misc |
| 82 | reg [2:0] mycid; |
| 83 | reg [2:0] mytid; |
| 84 | reg [5:0] mytnum; |
| 85 | reg [7:0] myasi; |
| 86 | reg [(`TS_WIDTH-1):0] tstamp; |
| 87 | integer junk; |
| 88 | integer i; |
| 89 | |
| 90 | |
| 91 | initial begin // { |
| 92 | mycid = 0; |
| 93 | end //} |
| 94 | |
| 95 | //---------------------------------------------------------- |
| 96 | // DUT probes |
| 97 | |
| 98 | //-------------------- |
| 99 | // TICK & STICK ASR READ |
| 100 | |
| 101 | // 65 bit control/data ring bus |
| 102 | // 64 - ctl/data |
| 103 | // 63 - valid/hole |
| 104 | // 62 - ack |
| 105 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 106 | // 59 - rd/wrx |
| 107 | // 58:56 - Thread ID |
| 108 | // 55:48 - ASI field |
| 109 | // 47:0 - Virtual Address |
| 110 | |
| 111 | assign tlu_rng = `SPC0.tlu.tlu_rngf_cdbus; |
| 112 | |
| 113 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 114 | assign rng_tid = tlu_rng[58:56]; |
| 115 | |
| 116 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 117 | (tlu_rng[63]==1'h1) & // Valid |
| 118 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 119 | (tlu_rng[59]==1'h1) & // Read |
| 120 | (tlu_rng[55:48]==8'h04) // ASR# |
| 121 | ); |
| 122 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 123 | (tlu_rng[63]==1'h1) & // Valid |
| 124 | (tlu_rng[61:60]==2'h1) & // ASR |
| 125 | (tlu_rng[59]==1'h1) & // Read |
| 126 | (tlu_rng[55:48]==8'h18) // ASR# |
| 127 | ); |
| 128 | |
| 129 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 130 | (tlu_rng[63]==1'h1) & // Valid |
| 131 | (tlu_rng[62:60]==3'h0) & // ASR |
| 132 | (tlu_rng[59]==1'h1) & // Read |
| 133 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 134 | (tlu_rng[47:0] == 48'h98) // VA# |
| 135 | ); |
| 136 | //---------------------------------------------------------- |
| 137 | //---------------------------------------------------------- |
| 138 | |
| 139 | always @ (posedge `SPC0.l2clk) begin // { |
| 140 | |
| 141 | tstamp = `TOP.core_cycle_cnt - 1; |
| 142 | |
| 143 | // Delay by 1 cycle so it aligns with rng_value |
| 144 | tick_rd_1 <= tick_rd; |
| 145 | rng_tid_1 <= rng_tid; |
| 146 | stick_rd_1 <= stick_rd; |
| 147 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 148 | |
| 149 | // TICK register followme |
| 150 | if (tick_rd_1) begin // { |
| 151 | |
| 152 | myasi = 8'h04; |
| 153 | mytid = rng_tid_1; |
| 154 | mytnum = (mycid * 8) + mytid; |
| 155 | |
| 156 | `PR_INFO ("pli_int", `INFO, |
| 157 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 158 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 159 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 160 | junk = $sim_send(`PLI_ASR_READ, |
| 161 | mytnum, myasi, rng_value); |
| 162 | end // } |
| 163 | |
| 164 | end // } |
| 165 | |
| 166 | // STICK register followme |
| 167 | if (stick_rd_1) begin // { |
| 168 | |
| 169 | myasi = 8'h18; |
| 170 | mytid = rng_tid_1; |
| 171 | mytnum = (mycid * 8) + mytid; |
| 172 | |
| 173 | `PR_INFO ("pli_int", `INFO, |
| 174 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 175 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 176 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 177 | junk = $sim_send(`PLI_ASR_READ, |
| 178 | mytnum, myasi, rng_value); |
| 179 | end // } |
| 180 | |
| 181 | end // } |
| 182 | |
| 183 | // HWTW Pending register followme |
| 184 | if (hwtwPending_rd_1) begin // { |
| 185 | |
| 186 | myasi = 8'h54; |
| 187 | mytid = rng_tid_1; |
| 188 | mytnum = (mycid * 8) + mytid; |
| 189 | |
| 190 | // followme |
| 191 | `PR_INFO ("pli_int", `INFO, |
| 192 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 193 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 194 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 195 | junk = $sim_send(`PLI_ASI_READ, |
| 196 | mytnum, myasi, 64'h98, rng_value); |
| 197 | end // } |
| 198 | |
| 199 | end // } |
| 200 | |
| 201 | end // always } |
| 202 | |
| 203 | |
| 204 | //------------------------------------------ |
| 205 | // PMU PCR |
| 206 | |
| 207 | // 65 bit control/data ring bus |
| 208 | // 64 - ctl/data |
| 209 | // 63 - valid/hole |
| 210 | // 62 - ack |
| 211 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 212 | // 59 - rd/wrx |
| 213 | // 58:56 - Thread ID |
| 214 | // 55:48 - ASI field |
| 215 | // 47:0 - Virtual Address |
| 216 | |
| 217 | assign pmu_rng = `SPC0.pmu.in_rngl_cdbus; |
| 218 | |
| 219 | assign pmu_rng_in = `SPC0.pmu.pmu_rngl_cdbus; |
| 220 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 221 | |
| 222 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 223 | |
| 224 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 225 | (pmu_rng[63]==1'h1) & // Valid |
| 226 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 227 | (pmu_rng[59]==1'h1) & // Read |
| 228 | (pmu_rng[55:48]==8'h10) // ASR# |
| 229 | ); |
| 230 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 231 | (pmu_rng[63]==1'h1) & // Valid |
| 232 | (pmu_rng[61:60]==2'h1) & // ASR |
| 233 | (pmu_rng[59]==1'h1) & // Read |
| 234 | (pmu_rng[55:48]==8'h11) // ASR# |
| 235 | ); |
| 236 | |
| 237 | always @ (posedge `SPC0.l2clk) begin // { |
| 238 | |
| 239 | tstamp = `TOP.core_cycle_cnt - 1; |
| 240 | |
| 241 | // Delay by 1 cycle so it aligns with rng_value |
| 242 | |
| 243 | pcr_rd_1 <= pcr_rd; |
| 244 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 245 | pic_rd_1 <= pic_rd; |
| 246 | |
| 247 | pcr_rd_2 <= pcr_rd_1; |
| 248 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 249 | pic_rd_2 <= pic_rd_1; |
| 250 | |
| 251 | pcr_rd_3 <= pcr_rd_2; |
| 252 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 253 | pic_rd_3 <= pic_rd_2; |
| 254 | |
| 255 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 256 | |
| 257 | // PCR register followme |
| 258 | if (pcr_rd_3) begin // { |
| 259 | |
| 260 | |
| 261 | |
| 262 | `PR_INFO ("pli_int", `INFO, |
| 263 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 264 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 265 | |
| 266 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 267 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 268 | end // } |
| 269 | |
| 270 | end // } |
| 271 | |
| 272 | // PIC register followme |
| 273 | if (pic_rd_3) begin // { |
| 274 | |
| 275 | `PR_INFO ("pli_int", `INFO, |
| 276 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 277 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 278 | |
| 279 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 280 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 281 | end // } |
| 282 | |
| 283 | end // } |
| 284 | end // always } |
| 285 | |
| 286 | |
| 287 | |
| 288 | //---------------------------------------------------------- |
| 289 | `endif |
| 290 | endmodule |
| 291 | |
| 292 | `endif |
| 293 | |
| 294 | `ifdef CORE_1 |
| 295 | |
| 296 | module core_sync_c1(); |
| 297 | `ifndef GATESIM |
| 298 | |
| 299 | // common defines |
| 300 | `include "defines.vh" |
| 301 | |
| 302 | wire [64:0] tlu_rng; |
| 303 | wire [63:0] rng_value; |
| 304 | wire [2:0] rng_tid; |
| 305 | reg [2:0] rng_tid_1; |
| 306 | wire tick_rd; |
| 307 | reg tick_rd_1; |
| 308 | wire stick_rd; |
| 309 | reg stick_rd_1; |
| 310 | |
| 311 | wire hwtwPending_rd; |
| 312 | reg hwtwPending_rd_1; |
| 313 | |
| 314 | //--------------------- |
| 315 | // PMU |
| 316 | |
| 317 | wire [64:0] pmu_rng; |
| 318 | wire [63:0] pmu_rng_value; |
| 319 | wire [2:0] pmu_rng_tid; |
| 320 | reg [2:0] pmu_rng_tid_1; |
| 321 | |
| 322 | wire [64:0] pmu_rng_in; |
| 323 | |
| 324 | wire pcr_rd; |
| 325 | reg pcr_rd_1; |
| 326 | wire pic_rd; |
| 327 | reg pic_rd_1; |
| 328 | |
| 329 | reg pcr_rd_2; |
| 330 | reg pic_rd_2; |
| 331 | reg [2:0] pmu_rng_tid_2; |
| 332 | |
| 333 | reg pcr_rd_3; |
| 334 | reg pic_rd_3; |
| 335 | reg [2:0] pmu_rng_tid_3; |
| 336 | |
| 337 | reg [5:0] pmu_tnum; |
| 338 | |
| 339 | //--------------------- |
| 340 | // Misc |
| 341 | reg [2:0] mycid; |
| 342 | reg [2:0] mytid; |
| 343 | reg [5:0] mytnum; |
| 344 | reg [7:0] myasi; |
| 345 | reg [(`TS_WIDTH-1):0] tstamp; |
| 346 | integer junk; |
| 347 | integer i; |
| 348 | |
| 349 | |
| 350 | initial begin // { |
| 351 | mycid = 1; |
| 352 | end //} |
| 353 | |
| 354 | //---------------------------------------------------------- |
| 355 | // DUT probes |
| 356 | |
| 357 | //-------------------- |
| 358 | // TICK & STICK ASR READ |
| 359 | |
| 360 | // 65 bit control/data ring bus |
| 361 | // 64 - ctl/data |
| 362 | // 63 - valid/hole |
| 363 | // 62 - ack |
| 364 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 365 | // 59 - rd/wrx |
| 366 | // 58:56 - Thread ID |
| 367 | // 55:48 - ASI field |
| 368 | // 47:0 - Virtual Address |
| 369 | |
| 370 | assign tlu_rng = `SPC1.tlu.tlu_rngf_cdbus; |
| 371 | |
| 372 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 373 | assign rng_tid = tlu_rng[58:56]; |
| 374 | |
| 375 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 376 | (tlu_rng[63]==1'h1) & // Valid |
| 377 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 378 | (tlu_rng[59]==1'h1) & // Read |
| 379 | (tlu_rng[55:48]==8'h04) // ASR# |
| 380 | ); |
| 381 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 382 | (tlu_rng[63]==1'h1) & // Valid |
| 383 | (tlu_rng[61:60]==2'h1) & // ASR |
| 384 | (tlu_rng[59]==1'h1) & // Read |
| 385 | (tlu_rng[55:48]==8'h18) // ASR# |
| 386 | ); |
| 387 | |
| 388 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 389 | (tlu_rng[63]==1'h1) & // Valid |
| 390 | (tlu_rng[62:60]==3'h0) & // ASR |
| 391 | (tlu_rng[59]==1'h1) & // Read |
| 392 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 393 | (tlu_rng[47:0] == 48'h98) // VA# |
| 394 | ); |
| 395 | //---------------------------------------------------------- |
| 396 | //---------------------------------------------------------- |
| 397 | |
| 398 | always @ (posedge `SPC1.l2clk) begin // { |
| 399 | |
| 400 | tstamp = `TOP.core_cycle_cnt - 1; |
| 401 | |
| 402 | // Delay by 1 cycle so it aligns with rng_value |
| 403 | tick_rd_1 <= tick_rd; |
| 404 | rng_tid_1 <= rng_tid; |
| 405 | stick_rd_1 <= stick_rd; |
| 406 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 407 | |
| 408 | // TICK register followme |
| 409 | if (tick_rd_1) begin // { |
| 410 | |
| 411 | myasi = 8'h04; |
| 412 | mytid = rng_tid_1; |
| 413 | mytnum = (mycid * 8) + mytid; |
| 414 | |
| 415 | `PR_INFO ("pli_int", `INFO, |
| 416 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 417 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 418 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 419 | junk = $sim_send(`PLI_ASR_READ, |
| 420 | mytnum, myasi, rng_value); |
| 421 | end // } |
| 422 | |
| 423 | end // } |
| 424 | |
| 425 | // STICK register followme |
| 426 | if (stick_rd_1) begin // { |
| 427 | |
| 428 | myasi = 8'h18; |
| 429 | mytid = rng_tid_1; |
| 430 | mytnum = (mycid * 8) + mytid; |
| 431 | |
| 432 | `PR_INFO ("pli_int", `INFO, |
| 433 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 434 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 435 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 436 | junk = $sim_send(`PLI_ASR_READ, |
| 437 | mytnum, myasi, rng_value); |
| 438 | end // } |
| 439 | |
| 440 | end // } |
| 441 | |
| 442 | // HWTW Pending register followme |
| 443 | if (hwtwPending_rd_1) begin // { |
| 444 | |
| 445 | myasi = 8'h54; |
| 446 | mytid = rng_tid_1; |
| 447 | mytnum = (mycid * 8) + mytid; |
| 448 | |
| 449 | // followme |
| 450 | `PR_INFO ("pli_int", `INFO, |
| 451 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 452 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 453 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 454 | junk = $sim_send(`PLI_ASI_READ, |
| 455 | mytnum, myasi, 64'h98, rng_value); |
| 456 | end // } |
| 457 | |
| 458 | end // } |
| 459 | |
| 460 | end // always } |
| 461 | |
| 462 | |
| 463 | //------------------------------------------ |
| 464 | // PMU PCR |
| 465 | |
| 466 | // 65 bit control/data ring bus |
| 467 | // 64 - ctl/data |
| 468 | // 63 - valid/hole |
| 469 | // 62 - ack |
| 470 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 471 | // 59 - rd/wrx |
| 472 | // 58:56 - Thread ID |
| 473 | // 55:48 - ASI field |
| 474 | // 47:0 - Virtual Address |
| 475 | |
| 476 | assign pmu_rng = `SPC1.pmu.in_rngl_cdbus; |
| 477 | |
| 478 | assign pmu_rng_in = `SPC1.pmu.pmu_rngl_cdbus; |
| 479 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 480 | |
| 481 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 482 | |
| 483 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 484 | (pmu_rng[63]==1'h1) & // Valid |
| 485 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 486 | (pmu_rng[59]==1'h1) & // Read |
| 487 | (pmu_rng[55:48]==8'h10) // ASR# |
| 488 | ); |
| 489 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 490 | (pmu_rng[63]==1'h1) & // Valid |
| 491 | (pmu_rng[61:60]==2'h1) & // ASR |
| 492 | (pmu_rng[59]==1'h1) & // Read |
| 493 | (pmu_rng[55:48]==8'h11) // ASR# |
| 494 | ); |
| 495 | |
| 496 | always @ (posedge `SPC1.l2clk) begin // { |
| 497 | |
| 498 | tstamp = `TOP.core_cycle_cnt - 1; |
| 499 | |
| 500 | // Delay by 1 cycle so it aligns with rng_value |
| 501 | |
| 502 | pcr_rd_1 <= pcr_rd; |
| 503 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 504 | pic_rd_1 <= pic_rd; |
| 505 | |
| 506 | pcr_rd_2 <= pcr_rd_1; |
| 507 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 508 | pic_rd_2 <= pic_rd_1; |
| 509 | |
| 510 | pcr_rd_3 <= pcr_rd_2; |
| 511 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 512 | pic_rd_3 <= pic_rd_2; |
| 513 | |
| 514 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 515 | |
| 516 | // PCR register followme |
| 517 | if (pcr_rd_3) begin // { |
| 518 | |
| 519 | |
| 520 | |
| 521 | `PR_INFO ("pli_int", `INFO, |
| 522 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 523 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 524 | |
| 525 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 526 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 527 | end // } |
| 528 | |
| 529 | end // } |
| 530 | |
| 531 | // PIC register followme |
| 532 | if (pic_rd_3) begin // { |
| 533 | |
| 534 | `PR_INFO ("pli_int", `INFO, |
| 535 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 536 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 537 | |
| 538 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 539 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 540 | end // } |
| 541 | |
| 542 | end // } |
| 543 | end // always } |
| 544 | |
| 545 | |
| 546 | |
| 547 | //---------------------------------------------------------- |
| 548 | `endif |
| 549 | endmodule |
| 550 | |
| 551 | `endif |
| 552 | |
| 553 | `ifdef CORE_2 |
| 554 | |
| 555 | module core_sync_c2(); |
| 556 | `ifndef GATESIM |
| 557 | |
| 558 | // common defines |
| 559 | `include "defines.vh" |
| 560 | |
| 561 | wire [64:0] tlu_rng; |
| 562 | wire [63:0] rng_value; |
| 563 | wire [2:0] rng_tid; |
| 564 | reg [2:0] rng_tid_1; |
| 565 | wire tick_rd; |
| 566 | reg tick_rd_1; |
| 567 | wire stick_rd; |
| 568 | reg stick_rd_1; |
| 569 | |
| 570 | wire hwtwPending_rd; |
| 571 | reg hwtwPending_rd_1; |
| 572 | |
| 573 | //--------------------- |
| 574 | // PMU |
| 575 | |
| 576 | wire [64:0] pmu_rng; |
| 577 | wire [63:0] pmu_rng_value; |
| 578 | wire [2:0] pmu_rng_tid; |
| 579 | reg [2:0] pmu_rng_tid_1; |
| 580 | |
| 581 | wire [64:0] pmu_rng_in; |
| 582 | |
| 583 | wire pcr_rd; |
| 584 | reg pcr_rd_1; |
| 585 | wire pic_rd; |
| 586 | reg pic_rd_1; |
| 587 | |
| 588 | reg pcr_rd_2; |
| 589 | reg pic_rd_2; |
| 590 | reg [2:0] pmu_rng_tid_2; |
| 591 | |
| 592 | reg pcr_rd_3; |
| 593 | reg pic_rd_3; |
| 594 | reg [2:0] pmu_rng_tid_3; |
| 595 | |
| 596 | reg [5:0] pmu_tnum; |
| 597 | |
| 598 | //--------------------- |
| 599 | // Misc |
| 600 | reg [2:0] mycid; |
| 601 | reg [2:0] mytid; |
| 602 | reg [5:0] mytnum; |
| 603 | reg [7:0] myasi; |
| 604 | reg [(`TS_WIDTH-1):0] tstamp; |
| 605 | integer junk; |
| 606 | integer i; |
| 607 | |
| 608 | |
| 609 | initial begin // { |
| 610 | mycid = 2; |
| 611 | end //} |
| 612 | |
| 613 | //---------------------------------------------------------- |
| 614 | // DUT probes |
| 615 | |
| 616 | //-------------------- |
| 617 | // TICK & STICK ASR READ |
| 618 | |
| 619 | // 65 bit control/data ring bus |
| 620 | // 64 - ctl/data |
| 621 | // 63 - valid/hole |
| 622 | // 62 - ack |
| 623 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 624 | // 59 - rd/wrx |
| 625 | // 58:56 - Thread ID |
| 626 | // 55:48 - ASI field |
| 627 | // 47:0 - Virtual Address |
| 628 | |
| 629 | assign tlu_rng = `SPC2.tlu.tlu_rngf_cdbus; |
| 630 | |
| 631 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 632 | assign rng_tid = tlu_rng[58:56]; |
| 633 | |
| 634 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 635 | (tlu_rng[63]==1'h1) & // Valid |
| 636 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 637 | (tlu_rng[59]==1'h1) & // Read |
| 638 | (tlu_rng[55:48]==8'h04) // ASR# |
| 639 | ); |
| 640 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 641 | (tlu_rng[63]==1'h1) & // Valid |
| 642 | (tlu_rng[61:60]==2'h1) & // ASR |
| 643 | (tlu_rng[59]==1'h1) & // Read |
| 644 | (tlu_rng[55:48]==8'h18) // ASR# |
| 645 | ); |
| 646 | |
| 647 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 648 | (tlu_rng[63]==1'h1) & // Valid |
| 649 | (tlu_rng[62:60]==3'h0) & // ASR |
| 650 | (tlu_rng[59]==1'h1) & // Read |
| 651 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 652 | (tlu_rng[47:0] == 48'h98) // VA# |
| 653 | ); |
| 654 | //---------------------------------------------------------- |
| 655 | //---------------------------------------------------------- |
| 656 | |
| 657 | always @ (posedge `SPC2.l2clk) begin // { |
| 658 | |
| 659 | tstamp = `TOP.core_cycle_cnt - 1; |
| 660 | |
| 661 | // Delay by 1 cycle so it aligns with rng_value |
| 662 | tick_rd_1 <= tick_rd; |
| 663 | rng_tid_1 <= rng_tid; |
| 664 | stick_rd_1 <= stick_rd; |
| 665 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 666 | |
| 667 | // TICK register followme |
| 668 | if (tick_rd_1) begin // { |
| 669 | |
| 670 | myasi = 8'h04; |
| 671 | mytid = rng_tid_1; |
| 672 | mytnum = (mycid * 8) + mytid; |
| 673 | |
| 674 | `PR_INFO ("pli_int", `INFO, |
| 675 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 676 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 677 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 678 | junk = $sim_send(`PLI_ASR_READ, |
| 679 | mytnum, myasi, rng_value); |
| 680 | end // } |
| 681 | |
| 682 | end // } |
| 683 | |
| 684 | // STICK register followme |
| 685 | if (stick_rd_1) begin // { |
| 686 | |
| 687 | myasi = 8'h18; |
| 688 | mytid = rng_tid_1; |
| 689 | mytnum = (mycid * 8) + mytid; |
| 690 | |
| 691 | `PR_INFO ("pli_int", `INFO, |
| 692 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 693 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 694 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 695 | junk = $sim_send(`PLI_ASR_READ, |
| 696 | mytnum, myasi, rng_value); |
| 697 | end // } |
| 698 | |
| 699 | end // } |
| 700 | |
| 701 | // HWTW Pending register followme |
| 702 | if (hwtwPending_rd_1) begin // { |
| 703 | |
| 704 | myasi = 8'h54; |
| 705 | mytid = rng_tid_1; |
| 706 | mytnum = (mycid * 8) + mytid; |
| 707 | |
| 708 | // followme |
| 709 | `PR_INFO ("pli_int", `INFO, |
| 710 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 711 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 712 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 713 | junk = $sim_send(`PLI_ASI_READ, |
| 714 | mytnum, myasi, 64'h98, rng_value); |
| 715 | end // } |
| 716 | |
| 717 | end // } |
| 718 | |
| 719 | end // always } |
| 720 | |
| 721 | |
| 722 | //------------------------------------------ |
| 723 | // PMU PCR |
| 724 | |
| 725 | // 65 bit control/data ring bus |
| 726 | // 64 - ctl/data |
| 727 | // 63 - valid/hole |
| 728 | // 62 - ack |
| 729 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 730 | // 59 - rd/wrx |
| 731 | // 58:56 - Thread ID |
| 732 | // 55:48 - ASI field |
| 733 | // 47:0 - Virtual Address |
| 734 | |
| 735 | assign pmu_rng = `SPC2.pmu.in_rngl_cdbus; |
| 736 | |
| 737 | assign pmu_rng_in = `SPC2.pmu.pmu_rngl_cdbus; |
| 738 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 739 | |
| 740 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 741 | |
| 742 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 743 | (pmu_rng[63]==1'h1) & // Valid |
| 744 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 745 | (pmu_rng[59]==1'h1) & // Read |
| 746 | (pmu_rng[55:48]==8'h10) // ASR# |
| 747 | ); |
| 748 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 749 | (pmu_rng[63]==1'h1) & // Valid |
| 750 | (pmu_rng[61:60]==2'h1) & // ASR |
| 751 | (pmu_rng[59]==1'h1) & // Read |
| 752 | (pmu_rng[55:48]==8'h11) // ASR# |
| 753 | ); |
| 754 | |
| 755 | always @ (posedge `SPC2.l2clk) begin // { |
| 756 | |
| 757 | tstamp = `TOP.core_cycle_cnt - 1; |
| 758 | |
| 759 | // Delay by 1 cycle so it aligns with rng_value |
| 760 | |
| 761 | pcr_rd_1 <= pcr_rd; |
| 762 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 763 | pic_rd_1 <= pic_rd; |
| 764 | |
| 765 | pcr_rd_2 <= pcr_rd_1; |
| 766 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 767 | pic_rd_2 <= pic_rd_1; |
| 768 | |
| 769 | pcr_rd_3 <= pcr_rd_2; |
| 770 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 771 | pic_rd_3 <= pic_rd_2; |
| 772 | |
| 773 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 774 | |
| 775 | // PCR register followme |
| 776 | if (pcr_rd_3) begin // { |
| 777 | |
| 778 | |
| 779 | |
| 780 | `PR_INFO ("pli_int", `INFO, |
| 781 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 782 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 783 | |
| 784 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 785 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 786 | end // } |
| 787 | |
| 788 | end // } |
| 789 | |
| 790 | // PIC register followme |
| 791 | if (pic_rd_3) begin // { |
| 792 | |
| 793 | `PR_INFO ("pli_int", `INFO, |
| 794 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 795 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 796 | |
| 797 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 798 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 799 | end // } |
| 800 | |
| 801 | end // } |
| 802 | end // always } |
| 803 | |
| 804 | |
| 805 | |
| 806 | //---------------------------------------------------------- |
| 807 | `endif |
| 808 | endmodule |
| 809 | |
| 810 | `endif |
| 811 | |
| 812 | `ifdef CORE_3 |
| 813 | |
| 814 | module core_sync_c3(); |
| 815 | `ifndef GATESIM |
| 816 | |
| 817 | // common defines |
| 818 | `include "defines.vh" |
| 819 | |
| 820 | wire [64:0] tlu_rng; |
| 821 | wire [63:0] rng_value; |
| 822 | wire [2:0] rng_tid; |
| 823 | reg [2:0] rng_tid_1; |
| 824 | wire tick_rd; |
| 825 | reg tick_rd_1; |
| 826 | wire stick_rd; |
| 827 | reg stick_rd_1; |
| 828 | |
| 829 | wire hwtwPending_rd; |
| 830 | reg hwtwPending_rd_1; |
| 831 | |
| 832 | //--------------------- |
| 833 | // PMU |
| 834 | |
| 835 | wire [64:0] pmu_rng; |
| 836 | wire [63:0] pmu_rng_value; |
| 837 | wire [2:0] pmu_rng_tid; |
| 838 | reg [2:0] pmu_rng_tid_1; |
| 839 | |
| 840 | wire [64:0] pmu_rng_in; |
| 841 | |
| 842 | wire pcr_rd; |
| 843 | reg pcr_rd_1; |
| 844 | wire pic_rd; |
| 845 | reg pic_rd_1; |
| 846 | |
| 847 | reg pcr_rd_2; |
| 848 | reg pic_rd_2; |
| 849 | reg [2:0] pmu_rng_tid_2; |
| 850 | |
| 851 | reg pcr_rd_3; |
| 852 | reg pic_rd_3; |
| 853 | reg [2:0] pmu_rng_tid_3; |
| 854 | |
| 855 | reg [5:0] pmu_tnum; |
| 856 | |
| 857 | //--------------------- |
| 858 | // Misc |
| 859 | reg [2:0] mycid; |
| 860 | reg [2:0] mytid; |
| 861 | reg [5:0] mytnum; |
| 862 | reg [7:0] myasi; |
| 863 | reg [(`TS_WIDTH-1):0] tstamp; |
| 864 | integer junk; |
| 865 | integer i; |
| 866 | |
| 867 | |
| 868 | initial begin // { |
| 869 | mycid = 3; |
| 870 | end //} |
| 871 | |
| 872 | //---------------------------------------------------------- |
| 873 | // DUT probes |
| 874 | |
| 875 | //-------------------- |
| 876 | // TICK & STICK ASR READ |
| 877 | |
| 878 | // 65 bit control/data ring bus |
| 879 | // 64 - ctl/data |
| 880 | // 63 - valid/hole |
| 881 | // 62 - ack |
| 882 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 883 | // 59 - rd/wrx |
| 884 | // 58:56 - Thread ID |
| 885 | // 55:48 - ASI field |
| 886 | // 47:0 - Virtual Address |
| 887 | |
| 888 | assign tlu_rng = `SPC3.tlu.tlu_rngf_cdbus; |
| 889 | |
| 890 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 891 | assign rng_tid = tlu_rng[58:56]; |
| 892 | |
| 893 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 894 | (tlu_rng[63]==1'h1) & // Valid |
| 895 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 896 | (tlu_rng[59]==1'h1) & // Read |
| 897 | (tlu_rng[55:48]==8'h04) // ASR# |
| 898 | ); |
| 899 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 900 | (tlu_rng[63]==1'h1) & // Valid |
| 901 | (tlu_rng[61:60]==2'h1) & // ASR |
| 902 | (tlu_rng[59]==1'h1) & // Read |
| 903 | (tlu_rng[55:48]==8'h18) // ASR# |
| 904 | ); |
| 905 | |
| 906 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 907 | (tlu_rng[63]==1'h1) & // Valid |
| 908 | (tlu_rng[62:60]==3'h0) & // ASR |
| 909 | (tlu_rng[59]==1'h1) & // Read |
| 910 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 911 | (tlu_rng[47:0] == 48'h98) // VA# |
| 912 | ); |
| 913 | //---------------------------------------------------------- |
| 914 | //---------------------------------------------------------- |
| 915 | |
| 916 | always @ (posedge `SPC3.l2clk) begin // { |
| 917 | |
| 918 | tstamp = `TOP.core_cycle_cnt - 1; |
| 919 | |
| 920 | // Delay by 1 cycle so it aligns with rng_value |
| 921 | tick_rd_1 <= tick_rd; |
| 922 | rng_tid_1 <= rng_tid; |
| 923 | stick_rd_1 <= stick_rd; |
| 924 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 925 | |
| 926 | // TICK register followme |
| 927 | if (tick_rd_1) begin // { |
| 928 | |
| 929 | myasi = 8'h04; |
| 930 | mytid = rng_tid_1; |
| 931 | mytnum = (mycid * 8) + mytid; |
| 932 | |
| 933 | `PR_INFO ("pli_int", `INFO, |
| 934 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 935 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 936 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 937 | junk = $sim_send(`PLI_ASR_READ, |
| 938 | mytnum, myasi, rng_value); |
| 939 | end // } |
| 940 | |
| 941 | end // } |
| 942 | |
| 943 | // STICK register followme |
| 944 | if (stick_rd_1) begin // { |
| 945 | |
| 946 | myasi = 8'h18; |
| 947 | mytid = rng_tid_1; |
| 948 | mytnum = (mycid * 8) + mytid; |
| 949 | |
| 950 | `PR_INFO ("pli_int", `INFO, |
| 951 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 952 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 953 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 954 | junk = $sim_send(`PLI_ASR_READ, |
| 955 | mytnum, myasi, rng_value); |
| 956 | end // } |
| 957 | |
| 958 | end // } |
| 959 | |
| 960 | // HWTW Pending register followme |
| 961 | if (hwtwPending_rd_1) begin // { |
| 962 | |
| 963 | myasi = 8'h54; |
| 964 | mytid = rng_tid_1; |
| 965 | mytnum = (mycid * 8) + mytid; |
| 966 | |
| 967 | // followme |
| 968 | `PR_INFO ("pli_int", `INFO, |
| 969 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 970 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 971 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 972 | junk = $sim_send(`PLI_ASI_READ, |
| 973 | mytnum, myasi, 64'h98, rng_value); |
| 974 | end // } |
| 975 | |
| 976 | end // } |
| 977 | |
| 978 | end // always } |
| 979 | |
| 980 | |
| 981 | //------------------------------------------ |
| 982 | // PMU PCR |
| 983 | |
| 984 | // 65 bit control/data ring bus |
| 985 | // 64 - ctl/data |
| 986 | // 63 - valid/hole |
| 987 | // 62 - ack |
| 988 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 989 | // 59 - rd/wrx |
| 990 | // 58:56 - Thread ID |
| 991 | // 55:48 - ASI field |
| 992 | // 47:0 - Virtual Address |
| 993 | |
| 994 | assign pmu_rng = `SPC3.pmu.in_rngl_cdbus; |
| 995 | |
| 996 | assign pmu_rng_in = `SPC3.pmu.pmu_rngl_cdbus; |
| 997 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 998 | |
| 999 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 1000 | |
| 1001 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1002 | (pmu_rng[63]==1'h1) & // Valid |
| 1003 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 1004 | (pmu_rng[59]==1'h1) & // Read |
| 1005 | (pmu_rng[55:48]==8'h10) // ASR# |
| 1006 | ); |
| 1007 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1008 | (pmu_rng[63]==1'h1) & // Valid |
| 1009 | (pmu_rng[61:60]==2'h1) & // ASR |
| 1010 | (pmu_rng[59]==1'h1) & // Read |
| 1011 | (pmu_rng[55:48]==8'h11) // ASR# |
| 1012 | ); |
| 1013 | |
| 1014 | always @ (posedge `SPC3.l2clk) begin // { |
| 1015 | |
| 1016 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1017 | |
| 1018 | // Delay by 1 cycle so it aligns with rng_value |
| 1019 | |
| 1020 | pcr_rd_1 <= pcr_rd; |
| 1021 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 1022 | pic_rd_1 <= pic_rd; |
| 1023 | |
| 1024 | pcr_rd_2 <= pcr_rd_1; |
| 1025 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 1026 | pic_rd_2 <= pic_rd_1; |
| 1027 | |
| 1028 | pcr_rd_3 <= pcr_rd_2; |
| 1029 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 1030 | pic_rd_3 <= pic_rd_2; |
| 1031 | |
| 1032 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 1033 | |
| 1034 | // PCR register followme |
| 1035 | if (pcr_rd_3) begin // { |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | `PR_INFO ("pli_int", `INFO, |
| 1040 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1041 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 1042 | |
| 1043 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1044 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 1045 | end // } |
| 1046 | |
| 1047 | end // } |
| 1048 | |
| 1049 | // PIC register followme |
| 1050 | if (pic_rd_3) begin // { |
| 1051 | |
| 1052 | `PR_INFO ("pli_int", `INFO, |
| 1053 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1054 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 1055 | |
| 1056 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1057 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 1058 | end // } |
| 1059 | |
| 1060 | end // } |
| 1061 | end // always } |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | //---------------------------------------------------------- |
| 1066 | `endif |
| 1067 | endmodule |
| 1068 | |
| 1069 | `endif |
| 1070 | |
| 1071 | `ifdef CORE_4 |
| 1072 | |
| 1073 | module core_sync_c4(); |
| 1074 | `ifndef GATESIM |
| 1075 | |
| 1076 | // common defines |
| 1077 | `include "defines.vh" |
| 1078 | |
| 1079 | wire [64:0] tlu_rng; |
| 1080 | wire [63:0] rng_value; |
| 1081 | wire [2:0] rng_tid; |
| 1082 | reg [2:0] rng_tid_1; |
| 1083 | wire tick_rd; |
| 1084 | reg tick_rd_1; |
| 1085 | wire stick_rd; |
| 1086 | reg stick_rd_1; |
| 1087 | |
| 1088 | wire hwtwPending_rd; |
| 1089 | reg hwtwPending_rd_1; |
| 1090 | |
| 1091 | //--------------------- |
| 1092 | // PMU |
| 1093 | |
| 1094 | wire [64:0] pmu_rng; |
| 1095 | wire [63:0] pmu_rng_value; |
| 1096 | wire [2:0] pmu_rng_tid; |
| 1097 | reg [2:0] pmu_rng_tid_1; |
| 1098 | |
| 1099 | wire [64:0] pmu_rng_in; |
| 1100 | |
| 1101 | wire pcr_rd; |
| 1102 | reg pcr_rd_1; |
| 1103 | wire pic_rd; |
| 1104 | reg pic_rd_1; |
| 1105 | |
| 1106 | reg pcr_rd_2; |
| 1107 | reg pic_rd_2; |
| 1108 | reg [2:0] pmu_rng_tid_2; |
| 1109 | |
| 1110 | reg pcr_rd_3; |
| 1111 | reg pic_rd_3; |
| 1112 | reg [2:0] pmu_rng_tid_3; |
| 1113 | |
| 1114 | reg [5:0] pmu_tnum; |
| 1115 | |
| 1116 | //--------------------- |
| 1117 | // Misc |
| 1118 | reg [2:0] mycid; |
| 1119 | reg [2:0] mytid; |
| 1120 | reg [5:0] mytnum; |
| 1121 | reg [7:0] myasi; |
| 1122 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1123 | integer junk; |
| 1124 | integer i; |
| 1125 | |
| 1126 | |
| 1127 | initial begin // { |
| 1128 | mycid = 4; |
| 1129 | end //} |
| 1130 | |
| 1131 | //---------------------------------------------------------- |
| 1132 | // DUT probes |
| 1133 | |
| 1134 | //-------------------- |
| 1135 | // TICK & STICK ASR READ |
| 1136 | |
| 1137 | // 65 bit control/data ring bus |
| 1138 | // 64 - ctl/data |
| 1139 | // 63 - valid/hole |
| 1140 | // 62 - ack |
| 1141 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1142 | // 59 - rd/wrx |
| 1143 | // 58:56 - Thread ID |
| 1144 | // 55:48 - ASI field |
| 1145 | // 47:0 - Virtual Address |
| 1146 | |
| 1147 | assign tlu_rng = `SPC4.tlu.tlu_rngf_cdbus; |
| 1148 | |
| 1149 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 1150 | assign rng_tid = tlu_rng[58:56]; |
| 1151 | |
| 1152 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1153 | (tlu_rng[63]==1'h1) & // Valid |
| 1154 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 1155 | (tlu_rng[59]==1'h1) & // Read |
| 1156 | (tlu_rng[55:48]==8'h04) // ASR# |
| 1157 | ); |
| 1158 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1159 | (tlu_rng[63]==1'h1) & // Valid |
| 1160 | (tlu_rng[61:60]==2'h1) & // ASR |
| 1161 | (tlu_rng[59]==1'h1) & // Read |
| 1162 | (tlu_rng[55:48]==8'h18) // ASR# |
| 1163 | ); |
| 1164 | |
| 1165 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1166 | (tlu_rng[63]==1'h1) & // Valid |
| 1167 | (tlu_rng[62:60]==3'h0) & // ASR |
| 1168 | (tlu_rng[59]==1'h1) & // Read |
| 1169 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 1170 | (tlu_rng[47:0] == 48'h98) // VA# |
| 1171 | ); |
| 1172 | //---------------------------------------------------------- |
| 1173 | //---------------------------------------------------------- |
| 1174 | |
| 1175 | always @ (posedge `SPC4.l2clk) begin // { |
| 1176 | |
| 1177 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1178 | |
| 1179 | // Delay by 1 cycle so it aligns with rng_value |
| 1180 | tick_rd_1 <= tick_rd; |
| 1181 | rng_tid_1 <= rng_tid; |
| 1182 | stick_rd_1 <= stick_rd; |
| 1183 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 1184 | |
| 1185 | // TICK register followme |
| 1186 | if (tick_rd_1) begin // { |
| 1187 | |
| 1188 | myasi = 8'h04; |
| 1189 | mytid = rng_tid_1; |
| 1190 | mytnum = (mycid * 8) + mytid; |
| 1191 | |
| 1192 | `PR_INFO ("pli_int", `INFO, |
| 1193 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1194 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1195 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1196 | junk = $sim_send(`PLI_ASR_READ, |
| 1197 | mytnum, myasi, rng_value); |
| 1198 | end // } |
| 1199 | |
| 1200 | end // } |
| 1201 | |
| 1202 | // STICK register followme |
| 1203 | if (stick_rd_1) begin // { |
| 1204 | |
| 1205 | myasi = 8'h18; |
| 1206 | mytid = rng_tid_1; |
| 1207 | mytnum = (mycid * 8) + mytid; |
| 1208 | |
| 1209 | `PR_INFO ("pli_int", `INFO, |
| 1210 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1211 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1212 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1213 | junk = $sim_send(`PLI_ASR_READ, |
| 1214 | mytnum, myasi, rng_value); |
| 1215 | end // } |
| 1216 | |
| 1217 | end // } |
| 1218 | |
| 1219 | // HWTW Pending register followme |
| 1220 | if (hwtwPending_rd_1) begin // { |
| 1221 | |
| 1222 | myasi = 8'h54; |
| 1223 | mytid = rng_tid_1; |
| 1224 | mytnum = (mycid * 8) + mytid; |
| 1225 | |
| 1226 | // followme |
| 1227 | `PR_INFO ("pli_int", `INFO, |
| 1228 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 1229 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 1230 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1231 | junk = $sim_send(`PLI_ASI_READ, |
| 1232 | mytnum, myasi, 64'h98, rng_value); |
| 1233 | end // } |
| 1234 | |
| 1235 | end // } |
| 1236 | |
| 1237 | end // always } |
| 1238 | |
| 1239 | |
| 1240 | //------------------------------------------ |
| 1241 | // PMU PCR |
| 1242 | |
| 1243 | // 65 bit control/data ring bus |
| 1244 | // 64 - ctl/data |
| 1245 | // 63 - valid/hole |
| 1246 | // 62 - ack |
| 1247 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1248 | // 59 - rd/wrx |
| 1249 | // 58:56 - Thread ID |
| 1250 | // 55:48 - ASI field |
| 1251 | // 47:0 - Virtual Address |
| 1252 | |
| 1253 | assign pmu_rng = `SPC4.pmu.in_rngl_cdbus; |
| 1254 | |
| 1255 | assign pmu_rng_in = `SPC4.pmu.pmu_rngl_cdbus; |
| 1256 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 1257 | |
| 1258 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 1259 | |
| 1260 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1261 | (pmu_rng[63]==1'h1) & // Valid |
| 1262 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 1263 | (pmu_rng[59]==1'h1) & // Read |
| 1264 | (pmu_rng[55:48]==8'h10) // ASR# |
| 1265 | ); |
| 1266 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1267 | (pmu_rng[63]==1'h1) & // Valid |
| 1268 | (pmu_rng[61:60]==2'h1) & // ASR |
| 1269 | (pmu_rng[59]==1'h1) & // Read |
| 1270 | (pmu_rng[55:48]==8'h11) // ASR# |
| 1271 | ); |
| 1272 | |
| 1273 | always @ (posedge `SPC4.l2clk) begin // { |
| 1274 | |
| 1275 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1276 | |
| 1277 | // Delay by 1 cycle so it aligns with rng_value |
| 1278 | |
| 1279 | pcr_rd_1 <= pcr_rd; |
| 1280 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 1281 | pic_rd_1 <= pic_rd; |
| 1282 | |
| 1283 | pcr_rd_2 <= pcr_rd_1; |
| 1284 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 1285 | pic_rd_2 <= pic_rd_1; |
| 1286 | |
| 1287 | pcr_rd_3 <= pcr_rd_2; |
| 1288 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 1289 | pic_rd_3 <= pic_rd_2; |
| 1290 | |
| 1291 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 1292 | |
| 1293 | // PCR register followme |
| 1294 | if (pcr_rd_3) begin // { |
| 1295 | |
| 1296 | |
| 1297 | |
| 1298 | `PR_INFO ("pli_int", `INFO, |
| 1299 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1300 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 1301 | |
| 1302 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1303 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 1304 | end // } |
| 1305 | |
| 1306 | end // } |
| 1307 | |
| 1308 | // PIC register followme |
| 1309 | if (pic_rd_3) begin // { |
| 1310 | |
| 1311 | `PR_INFO ("pli_int", `INFO, |
| 1312 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1313 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 1314 | |
| 1315 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1316 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 1317 | end // } |
| 1318 | |
| 1319 | end // } |
| 1320 | end // always } |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | //---------------------------------------------------------- |
| 1325 | `endif |
| 1326 | endmodule |
| 1327 | |
| 1328 | `endif |
| 1329 | |
| 1330 | `ifdef CORE_5 |
| 1331 | |
| 1332 | module core_sync_c5(); |
| 1333 | `ifndef GATESIM |
| 1334 | |
| 1335 | // common defines |
| 1336 | `include "defines.vh" |
| 1337 | |
| 1338 | wire [64:0] tlu_rng; |
| 1339 | wire [63:0] rng_value; |
| 1340 | wire [2:0] rng_tid; |
| 1341 | reg [2:0] rng_tid_1; |
| 1342 | wire tick_rd; |
| 1343 | reg tick_rd_1; |
| 1344 | wire stick_rd; |
| 1345 | reg stick_rd_1; |
| 1346 | |
| 1347 | wire hwtwPending_rd; |
| 1348 | reg hwtwPending_rd_1; |
| 1349 | |
| 1350 | //--------------------- |
| 1351 | // PMU |
| 1352 | |
| 1353 | wire [64:0] pmu_rng; |
| 1354 | wire [63:0] pmu_rng_value; |
| 1355 | wire [2:0] pmu_rng_tid; |
| 1356 | reg [2:0] pmu_rng_tid_1; |
| 1357 | |
| 1358 | wire [64:0] pmu_rng_in; |
| 1359 | |
| 1360 | wire pcr_rd; |
| 1361 | reg pcr_rd_1; |
| 1362 | wire pic_rd; |
| 1363 | reg pic_rd_1; |
| 1364 | |
| 1365 | reg pcr_rd_2; |
| 1366 | reg pic_rd_2; |
| 1367 | reg [2:0] pmu_rng_tid_2; |
| 1368 | |
| 1369 | reg pcr_rd_3; |
| 1370 | reg pic_rd_3; |
| 1371 | reg [2:0] pmu_rng_tid_3; |
| 1372 | |
| 1373 | reg [5:0] pmu_tnum; |
| 1374 | |
| 1375 | //--------------------- |
| 1376 | // Misc |
| 1377 | reg [2:0] mycid; |
| 1378 | reg [2:0] mytid; |
| 1379 | reg [5:0] mytnum; |
| 1380 | reg [7:0] myasi; |
| 1381 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1382 | integer junk; |
| 1383 | integer i; |
| 1384 | |
| 1385 | |
| 1386 | initial begin // { |
| 1387 | mycid = 5; |
| 1388 | end //} |
| 1389 | |
| 1390 | //---------------------------------------------------------- |
| 1391 | // DUT probes |
| 1392 | |
| 1393 | //-------------------- |
| 1394 | // TICK & STICK ASR READ |
| 1395 | |
| 1396 | // 65 bit control/data ring bus |
| 1397 | // 64 - ctl/data |
| 1398 | // 63 - valid/hole |
| 1399 | // 62 - ack |
| 1400 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1401 | // 59 - rd/wrx |
| 1402 | // 58:56 - Thread ID |
| 1403 | // 55:48 - ASI field |
| 1404 | // 47:0 - Virtual Address |
| 1405 | |
| 1406 | assign tlu_rng = `SPC5.tlu.tlu_rngf_cdbus; |
| 1407 | |
| 1408 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 1409 | assign rng_tid = tlu_rng[58:56]; |
| 1410 | |
| 1411 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1412 | (tlu_rng[63]==1'h1) & // Valid |
| 1413 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 1414 | (tlu_rng[59]==1'h1) & // Read |
| 1415 | (tlu_rng[55:48]==8'h04) // ASR# |
| 1416 | ); |
| 1417 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1418 | (tlu_rng[63]==1'h1) & // Valid |
| 1419 | (tlu_rng[61:60]==2'h1) & // ASR |
| 1420 | (tlu_rng[59]==1'h1) & // Read |
| 1421 | (tlu_rng[55:48]==8'h18) // ASR# |
| 1422 | ); |
| 1423 | |
| 1424 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1425 | (tlu_rng[63]==1'h1) & // Valid |
| 1426 | (tlu_rng[62:60]==3'h0) & // ASR |
| 1427 | (tlu_rng[59]==1'h1) & // Read |
| 1428 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 1429 | (tlu_rng[47:0] == 48'h98) // VA# |
| 1430 | ); |
| 1431 | //---------------------------------------------------------- |
| 1432 | //---------------------------------------------------------- |
| 1433 | |
| 1434 | always @ (posedge `SPC5.l2clk) begin // { |
| 1435 | |
| 1436 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1437 | |
| 1438 | // Delay by 1 cycle so it aligns with rng_value |
| 1439 | tick_rd_1 <= tick_rd; |
| 1440 | rng_tid_1 <= rng_tid; |
| 1441 | stick_rd_1 <= stick_rd; |
| 1442 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 1443 | |
| 1444 | // TICK register followme |
| 1445 | if (tick_rd_1) begin // { |
| 1446 | |
| 1447 | myasi = 8'h04; |
| 1448 | mytid = rng_tid_1; |
| 1449 | mytnum = (mycid * 8) + mytid; |
| 1450 | |
| 1451 | `PR_INFO ("pli_int", `INFO, |
| 1452 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1453 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1454 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1455 | junk = $sim_send(`PLI_ASR_READ, |
| 1456 | mytnum, myasi, rng_value); |
| 1457 | end // } |
| 1458 | |
| 1459 | end // } |
| 1460 | |
| 1461 | // STICK register followme |
| 1462 | if (stick_rd_1) begin // { |
| 1463 | |
| 1464 | myasi = 8'h18; |
| 1465 | mytid = rng_tid_1; |
| 1466 | mytnum = (mycid * 8) + mytid; |
| 1467 | |
| 1468 | `PR_INFO ("pli_int", `INFO, |
| 1469 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1470 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1471 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1472 | junk = $sim_send(`PLI_ASR_READ, |
| 1473 | mytnum, myasi, rng_value); |
| 1474 | end // } |
| 1475 | |
| 1476 | end // } |
| 1477 | |
| 1478 | // HWTW Pending register followme |
| 1479 | if (hwtwPending_rd_1) begin // { |
| 1480 | |
| 1481 | myasi = 8'h54; |
| 1482 | mytid = rng_tid_1; |
| 1483 | mytnum = (mycid * 8) + mytid; |
| 1484 | |
| 1485 | // followme |
| 1486 | `PR_INFO ("pli_int", `INFO, |
| 1487 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 1488 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 1489 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1490 | junk = $sim_send(`PLI_ASI_READ, |
| 1491 | mytnum, myasi, 64'h98, rng_value); |
| 1492 | end // } |
| 1493 | |
| 1494 | end // } |
| 1495 | |
| 1496 | end // always } |
| 1497 | |
| 1498 | |
| 1499 | //------------------------------------------ |
| 1500 | // PMU PCR |
| 1501 | |
| 1502 | // 65 bit control/data ring bus |
| 1503 | // 64 - ctl/data |
| 1504 | // 63 - valid/hole |
| 1505 | // 62 - ack |
| 1506 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1507 | // 59 - rd/wrx |
| 1508 | // 58:56 - Thread ID |
| 1509 | // 55:48 - ASI field |
| 1510 | // 47:0 - Virtual Address |
| 1511 | |
| 1512 | assign pmu_rng = `SPC5.pmu.in_rngl_cdbus; |
| 1513 | |
| 1514 | assign pmu_rng_in = `SPC5.pmu.pmu_rngl_cdbus; |
| 1515 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 1516 | |
| 1517 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 1518 | |
| 1519 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1520 | (pmu_rng[63]==1'h1) & // Valid |
| 1521 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 1522 | (pmu_rng[59]==1'h1) & // Read |
| 1523 | (pmu_rng[55:48]==8'h10) // ASR# |
| 1524 | ); |
| 1525 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1526 | (pmu_rng[63]==1'h1) & // Valid |
| 1527 | (pmu_rng[61:60]==2'h1) & // ASR |
| 1528 | (pmu_rng[59]==1'h1) & // Read |
| 1529 | (pmu_rng[55:48]==8'h11) // ASR# |
| 1530 | ); |
| 1531 | |
| 1532 | always @ (posedge `SPC5.l2clk) begin // { |
| 1533 | |
| 1534 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1535 | |
| 1536 | // Delay by 1 cycle so it aligns with rng_value |
| 1537 | |
| 1538 | pcr_rd_1 <= pcr_rd; |
| 1539 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 1540 | pic_rd_1 <= pic_rd; |
| 1541 | |
| 1542 | pcr_rd_2 <= pcr_rd_1; |
| 1543 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 1544 | pic_rd_2 <= pic_rd_1; |
| 1545 | |
| 1546 | pcr_rd_3 <= pcr_rd_2; |
| 1547 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 1548 | pic_rd_3 <= pic_rd_2; |
| 1549 | |
| 1550 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 1551 | |
| 1552 | // PCR register followme |
| 1553 | if (pcr_rd_3) begin // { |
| 1554 | |
| 1555 | |
| 1556 | |
| 1557 | `PR_INFO ("pli_int", `INFO, |
| 1558 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1559 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 1560 | |
| 1561 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1562 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 1563 | end // } |
| 1564 | |
| 1565 | end // } |
| 1566 | |
| 1567 | // PIC register followme |
| 1568 | if (pic_rd_3) begin // { |
| 1569 | |
| 1570 | `PR_INFO ("pli_int", `INFO, |
| 1571 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1572 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 1573 | |
| 1574 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1575 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 1576 | end // } |
| 1577 | |
| 1578 | end // } |
| 1579 | end // always } |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | //---------------------------------------------------------- |
| 1584 | `endif |
| 1585 | endmodule |
| 1586 | |
| 1587 | `endif |
| 1588 | |
| 1589 | `ifdef CORE_6 |
| 1590 | |
| 1591 | module core_sync_c6(); |
| 1592 | `ifndef GATESIM |
| 1593 | |
| 1594 | // common defines |
| 1595 | `include "defines.vh" |
| 1596 | |
| 1597 | wire [64:0] tlu_rng; |
| 1598 | wire [63:0] rng_value; |
| 1599 | wire [2:0] rng_tid; |
| 1600 | reg [2:0] rng_tid_1; |
| 1601 | wire tick_rd; |
| 1602 | reg tick_rd_1; |
| 1603 | wire stick_rd; |
| 1604 | reg stick_rd_1; |
| 1605 | |
| 1606 | wire hwtwPending_rd; |
| 1607 | reg hwtwPending_rd_1; |
| 1608 | |
| 1609 | //--------------------- |
| 1610 | // PMU |
| 1611 | |
| 1612 | wire [64:0] pmu_rng; |
| 1613 | wire [63:0] pmu_rng_value; |
| 1614 | wire [2:0] pmu_rng_tid; |
| 1615 | reg [2:0] pmu_rng_tid_1; |
| 1616 | |
| 1617 | wire [64:0] pmu_rng_in; |
| 1618 | |
| 1619 | wire pcr_rd; |
| 1620 | reg pcr_rd_1; |
| 1621 | wire pic_rd; |
| 1622 | reg pic_rd_1; |
| 1623 | |
| 1624 | reg pcr_rd_2; |
| 1625 | reg pic_rd_2; |
| 1626 | reg [2:0] pmu_rng_tid_2; |
| 1627 | |
| 1628 | reg pcr_rd_3; |
| 1629 | reg pic_rd_3; |
| 1630 | reg [2:0] pmu_rng_tid_3; |
| 1631 | |
| 1632 | reg [5:0] pmu_tnum; |
| 1633 | |
| 1634 | //--------------------- |
| 1635 | // Misc |
| 1636 | reg [2:0] mycid; |
| 1637 | reg [2:0] mytid; |
| 1638 | reg [5:0] mytnum; |
| 1639 | reg [7:0] myasi; |
| 1640 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1641 | integer junk; |
| 1642 | integer i; |
| 1643 | |
| 1644 | |
| 1645 | initial begin // { |
| 1646 | mycid = 6; |
| 1647 | end //} |
| 1648 | |
| 1649 | //---------------------------------------------------------- |
| 1650 | // DUT probes |
| 1651 | |
| 1652 | //-------------------- |
| 1653 | // TICK & STICK ASR READ |
| 1654 | |
| 1655 | // 65 bit control/data ring bus |
| 1656 | // 64 - ctl/data |
| 1657 | // 63 - valid/hole |
| 1658 | // 62 - ack |
| 1659 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1660 | // 59 - rd/wrx |
| 1661 | // 58:56 - Thread ID |
| 1662 | // 55:48 - ASI field |
| 1663 | // 47:0 - Virtual Address |
| 1664 | |
| 1665 | assign tlu_rng = `SPC6.tlu.tlu_rngf_cdbus; |
| 1666 | |
| 1667 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 1668 | assign rng_tid = tlu_rng[58:56]; |
| 1669 | |
| 1670 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1671 | (tlu_rng[63]==1'h1) & // Valid |
| 1672 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 1673 | (tlu_rng[59]==1'h1) & // Read |
| 1674 | (tlu_rng[55:48]==8'h04) // ASR# |
| 1675 | ); |
| 1676 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1677 | (tlu_rng[63]==1'h1) & // Valid |
| 1678 | (tlu_rng[61:60]==2'h1) & // ASR |
| 1679 | (tlu_rng[59]==1'h1) & // Read |
| 1680 | (tlu_rng[55:48]==8'h18) // ASR# |
| 1681 | ); |
| 1682 | |
| 1683 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1684 | (tlu_rng[63]==1'h1) & // Valid |
| 1685 | (tlu_rng[62:60]==3'h0) & // ASR |
| 1686 | (tlu_rng[59]==1'h1) & // Read |
| 1687 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 1688 | (tlu_rng[47:0] == 48'h98) // VA# |
| 1689 | ); |
| 1690 | //---------------------------------------------------------- |
| 1691 | //---------------------------------------------------------- |
| 1692 | |
| 1693 | always @ (posedge `SPC6.l2clk) begin // { |
| 1694 | |
| 1695 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1696 | |
| 1697 | // Delay by 1 cycle so it aligns with rng_value |
| 1698 | tick_rd_1 <= tick_rd; |
| 1699 | rng_tid_1 <= rng_tid; |
| 1700 | stick_rd_1 <= stick_rd; |
| 1701 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 1702 | |
| 1703 | // TICK register followme |
| 1704 | if (tick_rd_1) begin // { |
| 1705 | |
| 1706 | myasi = 8'h04; |
| 1707 | mytid = rng_tid_1; |
| 1708 | mytnum = (mycid * 8) + mytid; |
| 1709 | |
| 1710 | `PR_INFO ("pli_int", `INFO, |
| 1711 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1712 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1713 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1714 | junk = $sim_send(`PLI_ASR_READ, |
| 1715 | mytnum, myasi, rng_value); |
| 1716 | end // } |
| 1717 | |
| 1718 | end // } |
| 1719 | |
| 1720 | // STICK register followme |
| 1721 | if (stick_rd_1) begin // { |
| 1722 | |
| 1723 | myasi = 8'h18; |
| 1724 | mytid = rng_tid_1; |
| 1725 | mytnum = (mycid * 8) + mytid; |
| 1726 | |
| 1727 | `PR_INFO ("pli_int", `INFO, |
| 1728 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1729 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1730 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1731 | junk = $sim_send(`PLI_ASR_READ, |
| 1732 | mytnum, myasi, rng_value); |
| 1733 | end // } |
| 1734 | |
| 1735 | end // } |
| 1736 | |
| 1737 | // HWTW Pending register followme |
| 1738 | if (hwtwPending_rd_1) begin // { |
| 1739 | |
| 1740 | myasi = 8'h54; |
| 1741 | mytid = rng_tid_1; |
| 1742 | mytnum = (mycid * 8) + mytid; |
| 1743 | |
| 1744 | // followme |
| 1745 | `PR_INFO ("pli_int", `INFO, |
| 1746 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 1747 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 1748 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1749 | junk = $sim_send(`PLI_ASI_READ, |
| 1750 | mytnum, myasi, 64'h98, rng_value); |
| 1751 | end // } |
| 1752 | |
| 1753 | end // } |
| 1754 | |
| 1755 | end // always } |
| 1756 | |
| 1757 | |
| 1758 | //------------------------------------------ |
| 1759 | // PMU PCR |
| 1760 | |
| 1761 | // 65 bit control/data ring bus |
| 1762 | // 64 - ctl/data |
| 1763 | // 63 - valid/hole |
| 1764 | // 62 - ack |
| 1765 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1766 | // 59 - rd/wrx |
| 1767 | // 58:56 - Thread ID |
| 1768 | // 55:48 - ASI field |
| 1769 | // 47:0 - Virtual Address |
| 1770 | |
| 1771 | assign pmu_rng = `SPC6.pmu.in_rngl_cdbus; |
| 1772 | |
| 1773 | assign pmu_rng_in = `SPC6.pmu.pmu_rngl_cdbus; |
| 1774 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 1775 | |
| 1776 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 1777 | |
| 1778 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1779 | (pmu_rng[63]==1'h1) & // Valid |
| 1780 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 1781 | (pmu_rng[59]==1'h1) & // Read |
| 1782 | (pmu_rng[55:48]==8'h10) // ASR# |
| 1783 | ); |
| 1784 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 1785 | (pmu_rng[63]==1'h1) & // Valid |
| 1786 | (pmu_rng[61:60]==2'h1) & // ASR |
| 1787 | (pmu_rng[59]==1'h1) & // Read |
| 1788 | (pmu_rng[55:48]==8'h11) // ASR# |
| 1789 | ); |
| 1790 | |
| 1791 | always @ (posedge `SPC6.l2clk) begin // { |
| 1792 | |
| 1793 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1794 | |
| 1795 | // Delay by 1 cycle so it aligns with rng_value |
| 1796 | |
| 1797 | pcr_rd_1 <= pcr_rd; |
| 1798 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 1799 | pic_rd_1 <= pic_rd; |
| 1800 | |
| 1801 | pcr_rd_2 <= pcr_rd_1; |
| 1802 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 1803 | pic_rd_2 <= pic_rd_1; |
| 1804 | |
| 1805 | pcr_rd_3 <= pcr_rd_2; |
| 1806 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 1807 | pic_rd_3 <= pic_rd_2; |
| 1808 | |
| 1809 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 1810 | |
| 1811 | // PCR register followme |
| 1812 | if (pcr_rd_3) begin // { |
| 1813 | |
| 1814 | |
| 1815 | |
| 1816 | `PR_INFO ("pli_int", `INFO, |
| 1817 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1818 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 1819 | |
| 1820 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1821 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 1822 | end // } |
| 1823 | |
| 1824 | end // } |
| 1825 | |
| 1826 | // PIC register followme |
| 1827 | if (pic_rd_3) begin // { |
| 1828 | |
| 1829 | `PR_INFO ("pli_int", `INFO, |
| 1830 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1831 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 1832 | |
| 1833 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1834 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 1835 | end // } |
| 1836 | |
| 1837 | end // } |
| 1838 | end // always } |
| 1839 | |
| 1840 | |
| 1841 | |
| 1842 | //---------------------------------------------------------- |
| 1843 | `endif |
| 1844 | endmodule |
| 1845 | |
| 1846 | `endif |
| 1847 | |
| 1848 | `ifdef CORE_7 |
| 1849 | |
| 1850 | module core_sync_c7(); |
| 1851 | `ifndef GATESIM |
| 1852 | |
| 1853 | // common defines |
| 1854 | `include "defines.vh" |
| 1855 | |
| 1856 | wire [64:0] tlu_rng; |
| 1857 | wire [63:0] rng_value; |
| 1858 | wire [2:0] rng_tid; |
| 1859 | reg [2:0] rng_tid_1; |
| 1860 | wire tick_rd; |
| 1861 | reg tick_rd_1; |
| 1862 | wire stick_rd; |
| 1863 | reg stick_rd_1; |
| 1864 | |
| 1865 | wire hwtwPending_rd; |
| 1866 | reg hwtwPending_rd_1; |
| 1867 | |
| 1868 | //--------------------- |
| 1869 | // PMU |
| 1870 | |
| 1871 | wire [64:0] pmu_rng; |
| 1872 | wire [63:0] pmu_rng_value; |
| 1873 | wire [2:0] pmu_rng_tid; |
| 1874 | reg [2:0] pmu_rng_tid_1; |
| 1875 | |
| 1876 | wire [64:0] pmu_rng_in; |
| 1877 | |
| 1878 | wire pcr_rd; |
| 1879 | reg pcr_rd_1; |
| 1880 | wire pic_rd; |
| 1881 | reg pic_rd_1; |
| 1882 | |
| 1883 | reg pcr_rd_2; |
| 1884 | reg pic_rd_2; |
| 1885 | reg [2:0] pmu_rng_tid_2; |
| 1886 | |
| 1887 | reg pcr_rd_3; |
| 1888 | reg pic_rd_3; |
| 1889 | reg [2:0] pmu_rng_tid_3; |
| 1890 | |
| 1891 | reg [5:0] pmu_tnum; |
| 1892 | |
| 1893 | //--------------------- |
| 1894 | // Misc |
| 1895 | reg [2:0] mycid; |
| 1896 | reg [2:0] mytid; |
| 1897 | reg [5:0] mytnum; |
| 1898 | reg [7:0] myasi; |
| 1899 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1900 | integer junk; |
| 1901 | integer i; |
| 1902 | |
| 1903 | |
| 1904 | initial begin // { |
| 1905 | mycid = 7; |
| 1906 | end //} |
| 1907 | |
| 1908 | //---------------------------------------------------------- |
| 1909 | // DUT probes |
| 1910 | |
| 1911 | //-------------------- |
| 1912 | // TICK & STICK ASR READ |
| 1913 | |
| 1914 | // 65 bit control/data ring bus |
| 1915 | // 64 - ctl/data |
| 1916 | // 63 - valid/hole |
| 1917 | // 62 - ack |
| 1918 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 1919 | // 59 - rd/wrx |
| 1920 | // 58:56 - Thread ID |
| 1921 | // 55:48 - ASI field |
| 1922 | // 47:0 - Virtual Address |
| 1923 | |
| 1924 | assign tlu_rng = `SPC7.tlu.tlu_rngf_cdbus; |
| 1925 | |
| 1926 | assign rng_value = {1'b0,tlu_rng[62:0]}; |
| 1927 | assign rng_tid = tlu_rng[58:56]; |
| 1928 | |
| 1929 | assign tick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1930 | (tlu_rng[63]==1'h1) & // Valid |
| 1931 | ((tlu_rng[61:60]==2'h1) | (tlu_rng[61:60]==2'h2)) & // ASR or PR |
| 1932 | (tlu_rng[59]==1'h1) & // Read |
| 1933 | (tlu_rng[55:48]==8'h04) // ASR# |
| 1934 | ); |
| 1935 | assign stick_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1936 | (tlu_rng[63]==1'h1) & // Valid |
| 1937 | (tlu_rng[61:60]==2'h1) & // ASR |
| 1938 | (tlu_rng[59]==1'h1) & // Read |
| 1939 | (tlu_rng[55:48]==8'h18) // ASR# |
| 1940 | ); |
| 1941 | |
| 1942 | assign hwtwPending_rd = ((tlu_rng[64]==1'h1) & // Ctl pkt |
| 1943 | (tlu_rng[63]==1'h1) & // Valid |
| 1944 | (tlu_rng[62:60]==3'h0) & // ASR |
| 1945 | (tlu_rng[59]==1'h1) & // Read |
| 1946 | (tlu_rng[55:48]==8'h54) & // ASI# |
| 1947 | (tlu_rng[47:0] == 48'h98) // VA# |
| 1948 | ); |
| 1949 | //---------------------------------------------------------- |
| 1950 | //---------------------------------------------------------- |
| 1951 | |
| 1952 | always @ (posedge `SPC7.l2clk) begin // { |
| 1953 | |
| 1954 | tstamp = `TOP.core_cycle_cnt - 1; |
| 1955 | |
| 1956 | // Delay by 1 cycle so it aligns with rng_value |
| 1957 | tick_rd_1 <= tick_rd; |
| 1958 | rng_tid_1 <= rng_tid; |
| 1959 | stick_rd_1 <= stick_rd; |
| 1960 | hwtwPending_rd_1 <= hwtwPending_rd; |
| 1961 | |
| 1962 | // TICK register followme |
| 1963 | if (tick_rd_1) begin // { |
| 1964 | |
| 1965 | myasi = 8'h04; |
| 1966 | mytid = rng_tid_1; |
| 1967 | mytnum = (mycid * 8) + mytid; |
| 1968 | |
| 1969 | `PR_INFO ("pli_int", `INFO, |
| 1970 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1971 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1972 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1973 | junk = $sim_send(`PLI_ASR_READ, |
| 1974 | mytnum, myasi, rng_value); |
| 1975 | end // } |
| 1976 | |
| 1977 | end // } |
| 1978 | |
| 1979 | // STICK register followme |
| 1980 | if (stick_rd_1) begin // { |
| 1981 | |
| 1982 | myasi = 8'h18; |
| 1983 | mytid = rng_tid_1; |
| 1984 | mytnum = (mycid * 8) + mytid; |
| 1985 | |
| 1986 | `PR_INFO ("pli_int", `INFO, |
| 1987 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 1988 | mycid,mytid,mytnum, myasi, rng_value, tstamp); |
| 1989 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 1990 | junk = $sim_send(`PLI_ASR_READ, |
| 1991 | mytnum, myasi, rng_value); |
| 1992 | end // } |
| 1993 | |
| 1994 | end // } |
| 1995 | |
| 1996 | // HWTW Pending register followme |
| 1997 | if (hwtwPending_rd_1) begin // { |
| 1998 | |
| 1999 | myasi = 8'h54; |
| 2000 | mytid = rng_tid_1; |
| 2001 | mytnum = (mycid * 8) + mytid; |
| 2002 | |
| 2003 | // followme |
| 2004 | `PR_INFO ("pli_int", `INFO, |
| 2005 | "C%0d T%0d PLI_ASI_READ tid=%d asi=%0h va=%h val=0x%h ts=%0d", |
| 2006 | mycid,mytid,mytnum,myasi, 64'h98, rng_value, tstamp); |
| 2007 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 2008 | junk = $sim_send(`PLI_ASI_READ, |
| 2009 | mytnum, myasi, 64'h98, rng_value); |
| 2010 | end // } |
| 2011 | |
| 2012 | end // } |
| 2013 | |
| 2014 | end // always } |
| 2015 | |
| 2016 | |
| 2017 | //------------------------------------------ |
| 2018 | // PMU PCR |
| 2019 | |
| 2020 | // 65 bit control/data ring bus |
| 2021 | // 64 - ctl/data |
| 2022 | // 63 - valid/hole |
| 2023 | // 62 - ack |
| 2024 | // 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR |
| 2025 | // 59 - rd/wrx |
| 2026 | // 58:56 - Thread ID |
| 2027 | // 55:48 - ASI field |
| 2028 | // 47:0 - Virtual Address |
| 2029 | |
| 2030 | assign pmu_rng = `SPC7.pmu.in_rngl_cdbus; |
| 2031 | |
| 2032 | assign pmu_rng_in = `SPC7.pmu.pmu_rngl_cdbus; |
| 2033 | assign pmu_rng_value[63:0] = {pmu_rng_in[63:0]}; |
| 2034 | |
| 2035 | assign pmu_rng_tid[2:0] = pmu_rng[58:56]; |
| 2036 | |
| 2037 | assign pcr_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 2038 | (pmu_rng[63]==1'h1) & // Valid |
| 2039 | (pmu_rng[61:60]==2'h1) & // ASR or PR |
| 2040 | (pmu_rng[59]==1'h1) & // Read |
| 2041 | (pmu_rng[55:48]==8'h10) // ASR# |
| 2042 | ); |
| 2043 | assign pic_rd = ((pmu_rng[64]==1'h1) & // Ctl pkt |
| 2044 | (pmu_rng[63]==1'h1) & // Valid |
| 2045 | (pmu_rng[61:60]==2'h1) & // ASR |
| 2046 | (pmu_rng[59]==1'h1) & // Read |
| 2047 | (pmu_rng[55:48]==8'h11) // ASR# |
| 2048 | ); |
| 2049 | |
| 2050 | always @ (posedge `SPC7.l2clk) begin // { |
| 2051 | |
| 2052 | tstamp = `TOP.core_cycle_cnt - 1; |
| 2053 | |
| 2054 | // Delay by 1 cycle so it aligns with rng_value |
| 2055 | |
| 2056 | pcr_rd_1 <= pcr_rd; |
| 2057 | pmu_rng_tid_1 <= pmu_rng_tid[2:0]; |
| 2058 | pic_rd_1 <= pic_rd; |
| 2059 | |
| 2060 | pcr_rd_2 <= pcr_rd_1; |
| 2061 | pmu_rng_tid_2 <= pmu_rng_tid_1[2:0]; |
| 2062 | pic_rd_2 <= pic_rd_1; |
| 2063 | |
| 2064 | pcr_rd_3 <= pcr_rd_2; |
| 2065 | pmu_rng_tid_3 <= pmu_rng_tid_2[2:0]; |
| 2066 | pic_rd_3 <= pic_rd_2; |
| 2067 | |
| 2068 | pmu_tnum = (mycid * 8) + pmu_rng_tid_3; |
| 2069 | |
| 2070 | // PCR register followme |
| 2071 | if (pcr_rd_3) begin // { |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | `PR_INFO ("pli_int", `INFO, |
| 2076 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 2077 | mycid, pmu_rng_tid_1, pmu_tnum,8'h10 , pmu_rng_value, tstamp); |
| 2078 | |
| 2079 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 2080 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h10, pmu_rng_value); |
| 2081 | end // } |
| 2082 | |
| 2083 | end // } |
| 2084 | |
| 2085 | // PIC register followme |
| 2086 | if (pic_rd_3) begin // { |
| 2087 | |
| 2088 | `PR_INFO ("pli_int", `INFO, |
| 2089 | "C%0d T%0d PLI_ASR_READ tid=%h asi=%0h val=0x%h ts=%0d", |
| 2090 | mycid, pmu_rng_tid_1, pmu_tnum, 8'h11, pmu_rng_value, tstamp); |
| 2091 | |
| 2092 | if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // { |
| 2093 | junk = $sim_send(`PLI_ASR_READ, pmu_tnum, 8'h11, pmu_rng_value); |
| 2094 | end // } |
| 2095 | |
| 2096 | end // } |
| 2097 | end // always } |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | //---------------------------------------------------------- |
| 2102 | `endif |
| 2103 | endmodule |
| 2104 | |
| 2105 | `endif |
| 2106 | |
| 2107 | //---------------------------------------------------------- |
| 2108 | //---------------------------------------------------------- |