| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ldst_l2.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `timescale 1 ps / 1 ps |
| 36 | |
| 37 | module ldst_l2 (); |
| 38 | `ifndef GATESIM |
| 39 | |
| 40 | // common defines |
| 41 | `include "defines.vh" |
| 42 | // PCX/CPX packet defines (see :/verif/env/common/vera/include) |
| 43 | `include "ccx.vri" |
| 44 | |
| 45 | // Partial Bank Support |
| 46 | `ifdef RTL_NO_BNK01 |
| 47 | `define NO_L2_BNK0 |
| 48 | `define NO_L2_BNK1 |
| 49 | `endif |
| 50 | `ifdef RTL_NO_BNK23 |
| 51 | `define NO_L2_BNK2 |
| 52 | `define NO_L2_BNK3 |
| 53 | `endif |
| 54 | `ifdef RTL_NO_BNK45 |
| 55 | `define NO_L2_BNK4 |
| 56 | `define NO_L2_BNK5 |
| 57 | `endif |
| 58 | `ifdef RTL_NO_BNK67 |
| 59 | `define NO_L2_BNK6 |
| 60 | `define NO_L2_BNK7 |
| 61 | `endif |
| 62 | |
| 63 | // SPC Bench only has Bank0 |
| 64 | `ifdef SPC |
| 65 | `define NO_L2_BNK1 |
| 66 | `define NO_L2_BNK2 |
| 67 | `define NO_L2_BNK3 |
| 68 | `define NO_L2_BNK4 |
| 69 | `define NO_L2_BNK5 |
| 70 | `define NO_L2_BNK6 |
| 71 | `define NO_L2_BNK7 |
| 72 | `define NO_L2_BNK8 |
| 73 | `endif |
| 74 | |
| 75 | //--------------------- |
| 76 | // Misc Signals |
| 77 | wire [7:0] dsrc; |
| 78 | integer tstamp; |
| 79 | integer junk; |
| 80 | integer i; |
| 81 | |
| 82 | //---------------------------------------------------------- |
| 83 | //---------------------------------------------------------- |
| 84 | // DUT probes |
| 85 | |
| 86 | assign dsrc = `DSRC_L2_MEMORY; |
| 87 | |
| 88 | //========================================================== |
| 89 | //========================================================== |
| 90 | // L2 Stub Probes |
| 91 | |
| 92 | `ifdef NO_L2_BNK0 |
| 93 | `else |
| 94 | `ifdef NOL2RTL |
| 95 | |
| 96 | //---------------------------------------------------------- |
| 97 | // Signals for L2 Stub Bank0 |
| 98 | |
| 99 | wire [145:0] b0_cpx_pkt; |
| 100 | wire [39:0] b0_cpx_pa; |
| 101 | wire [2:0] b0_cpx_cid; |
| 102 | wire [2:0] b0_cpx_tid; |
| 103 | wire [5:0] b0_cpx_tnum; |
| 104 | wire b0_cpx_ctrue; |
| 105 | wire b0_cpx_swap; |
| 106 | wire b0_cpx_valid; |
| 107 | |
| 108 | // b0_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 109 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 110 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 111 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 112 | // for the StAck of a Swap/Ldstub. |
| 113 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 114 | |
| 115 | assign b0_cpx_pkt = `TOP.b0_cpx_pkt; |
| 116 | assign b0_cpx_pa = `TOP.b0_cpx_pa; |
| 117 | assign b0_cpx_cid = `TOP.b0_cpx_cid; |
| 118 | assign b0_cpx_tid = b0_cpx_pkt[`CPX_TID]; |
| 119 | assign b0_cpx_tnum = {b0_cpx_cid,b0_cpx_tid}; |
| 120 | assign b0_cpx_ctrue = `TOP.b0_cpx_ctrue; // ctrue = compare true for CAS |
| 121 | assign b0_cpx_swap = `TOP.b0_cpx_swap; // swap = St Ack is from a Swap |
| 122 | assign b0_cpx_valid = b0_cpx_pkt[`CPX_VALID]; |
| 123 | |
| 124 | //--------------------- |
| 125 | // Evict |
| 126 | |
| 127 | reg [31:0] b0_ev_vect0; |
| 128 | reg [23:0] b0_ev_vect1; |
| 129 | reg [31:0] b0_ev_vect2; |
| 130 | reg [23:0] b0_ev_vect3; |
| 131 | reg [1:0] b0_pa54; |
| 132 | reg [31:0] b0_inv_vect [0:3]; |
| 133 | reg [39:0] b0_evict_pa; |
| 134 | wire [39:0] b0_ev_pa; |
| 135 | reg [31:0] b0_evict_inv_vect; |
| 136 | |
| 137 | wire b0_evict; |
| 138 | wire [111:0] b0_ev_invvect; |
| 139 | |
| 140 | assign b0_evict = b0_cpx_valid & |
| 141 | (b0_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 142 | assign b0_ev_invvect = b0_cpx_pkt[`CPX_VINV_VECT]; |
| 143 | assign b0_ev_pa = b0_cpx_pa; |
| 144 | |
| 145 | //--------------------- |
| 146 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 147 | |
| 148 | wire b0_load_data_miss; |
| 149 | wire b0_ldd_suppress; |
| 150 | |
| 151 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 152 | |
| 153 | assign b0_load_data_miss = b0_cpx_valid & |
| 154 | ((((b0_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 155 | (b0_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 156 | (b0_cpx_pkt[`CPX_PF]==1'b0)) || |
| 157 | ((b0_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 158 | (b0_cpx_swap==1'b1))); |
| 159 | |
| 160 | assign b0_ldd_suppress = (b0_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 161 | |
| 162 | //--------------------- |
| 163 | // Store L2 Commit |
| 164 | |
| 165 | wire b0_store_commit; |
| 166 | wire [7:0] b0_stc_size; |
| 167 | wire [31:0] b0_stc_inv_vect; |
| 168 | reg [31:0] b0_stc_vect; |
| 169 | wire b0_stc_l2hit; |
| 170 | wire b0_stc_suppress; |
| 171 | |
| 172 | // rtntyp covers ST, CAS, SWAP since same decode |
| 173 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 174 | assign b0_store_commit = b0_cpx_valid & |
| 175 | (b0_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 176 | (b0_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 177 | // Set size=0 if CAS store didn't happen |
| 178 | assign b0_stc_size = (b0_cpx_pkt[`CPX_ATOMIC] & !b0_cpx_ctrue) ? |
| 179 | 8'b0 : b0_cpx_pkt[`CPX_VACK_BMASK]; |
| 180 | |
| 181 | assign b0_stc_inv_vect = b0_cpx_pkt[`CPX_VACK_VECT]; |
| 182 | assign b0_stc_suppress = (b0_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 183 | |
| 184 | // SPC bench - all L2 accesses are hits because this is used to |
| 185 | // determine whether Block Init St will initialize cache line or not |
| 186 | // if l2hit, then memory model doesn't initialize cache line |
| 187 | // in SPC bench, cache line is never initialized by CCX stub. |
| 188 | assign b0_stc_l2hit = 1'b1; |
| 189 | |
| 190 | `endif |
| 191 | `endif |
| 192 | |
| 193 | `ifdef NO_L2_BNK1 |
| 194 | `else |
| 195 | `ifdef NOL2RTL |
| 196 | |
| 197 | //---------------------------------------------------------- |
| 198 | // Signals for L2 Stub Bank1 |
| 199 | |
| 200 | wire [145:0] b1_cpx_pkt; |
| 201 | wire [39:0] b1_cpx_pa; |
| 202 | wire [2:0] b1_cpx_cid; |
| 203 | wire [2:0] b1_cpx_tid; |
| 204 | wire [5:0] b1_cpx_tnum; |
| 205 | wire b1_cpx_ctrue; |
| 206 | wire b1_cpx_swap; |
| 207 | wire b1_cpx_valid; |
| 208 | |
| 209 | // b1_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 210 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 211 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 212 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 213 | // for the StAck of a Swap/Ldstub. |
| 214 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 215 | |
| 216 | assign b1_cpx_pkt = `TOP.b1_cpx_pkt; |
| 217 | assign b1_cpx_pa = `TOP.b1_cpx_pa; |
| 218 | assign b1_cpx_cid = `TOP.b1_cpx_cid; |
| 219 | assign b1_cpx_tid = b1_cpx_pkt[`CPX_TID]; |
| 220 | assign b1_cpx_tnum = {b1_cpx_cid,b1_cpx_tid}; |
| 221 | assign b1_cpx_ctrue = `TOP.b1_cpx_ctrue; // ctrue = compare true for CAS |
| 222 | assign b1_cpx_swap = `TOP.b1_cpx_swap; // swap = St Ack is from a Swap |
| 223 | assign b1_cpx_valid = b1_cpx_pkt[`CPX_VALID]; |
| 224 | |
| 225 | //--------------------- |
| 226 | // Evict |
| 227 | |
| 228 | reg [31:0] b1_ev_vect0; |
| 229 | reg [23:0] b1_ev_vect1; |
| 230 | reg [31:0] b1_ev_vect2; |
| 231 | reg [23:0] b1_ev_vect3; |
| 232 | reg [1:0] b1_pa54; |
| 233 | reg [31:0] b1_inv_vect [0:3]; |
| 234 | reg [39:0] b1_evict_pa; |
| 235 | wire [39:0] b1_ev_pa; |
| 236 | reg [31:0] b1_evict_inv_vect; |
| 237 | |
| 238 | wire b1_evict; |
| 239 | wire [111:0] b1_ev_invvect; |
| 240 | |
| 241 | assign b1_evict = b1_cpx_valid & |
| 242 | (b1_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 243 | assign b1_ev_invvect = b1_cpx_pkt[`CPX_VINV_VECT]; |
| 244 | assign b1_ev_pa = b1_cpx_pa; |
| 245 | |
| 246 | //--------------------- |
| 247 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 248 | |
| 249 | wire b1_load_data_miss; |
| 250 | wire b1_ldd_suppress; |
| 251 | |
| 252 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 253 | |
| 254 | assign b1_load_data_miss = b1_cpx_valid & |
| 255 | ((((b1_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 256 | (b1_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 257 | (b1_cpx_pkt[`CPX_PF]==1'b0)) || |
| 258 | ((b1_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 259 | (b1_cpx_swap==1'b1))); |
| 260 | |
| 261 | assign b1_ldd_suppress = (b1_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 262 | |
| 263 | //--------------------- |
| 264 | // Store L2 Commit |
| 265 | |
| 266 | wire b1_store_commit; |
| 267 | wire [7:0] b1_stc_size; |
| 268 | wire [31:0] b1_stc_inv_vect; |
| 269 | reg [31:0] b1_stc_vect; |
| 270 | wire b1_stc_l2hit; |
| 271 | wire b1_stc_suppress; |
| 272 | |
| 273 | // rtntyp covers ST, CAS, SWAP since same decode |
| 274 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 275 | assign b1_store_commit = b1_cpx_valid & |
| 276 | (b1_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 277 | (b1_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 278 | // Set size=0 if CAS store didn't happen |
| 279 | assign b1_stc_size = (b1_cpx_pkt[`CPX_ATOMIC] & !b1_cpx_ctrue) ? |
| 280 | 8'b0 : b1_cpx_pkt[`CPX_VACK_BMASK]; |
| 281 | |
| 282 | assign b1_stc_inv_vect = b1_cpx_pkt[`CPX_VACK_VECT]; |
| 283 | assign b1_stc_suppress = (b1_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 284 | |
| 285 | // SPC bench - all L2 accesses are hits because this is used to |
| 286 | // determine whether Block Init St will initialize cache line or not |
| 287 | // if l2hit, then memory model doesn't initialize cache line |
| 288 | // in SPC bench, cache line is never initialized by CCX stub. |
| 289 | assign b1_stc_l2hit = 1'b1; |
| 290 | |
| 291 | `endif |
| 292 | `endif |
| 293 | |
| 294 | `ifdef NO_L2_BNK2 |
| 295 | `else |
| 296 | `ifdef NOL2RTL |
| 297 | |
| 298 | //---------------------------------------------------------- |
| 299 | // Signals for L2 Stub Bank2 |
| 300 | |
| 301 | wire [145:0] b2_cpx_pkt; |
| 302 | wire [39:0] b2_cpx_pa; |
| 303 | wire [2:0] b2_cpx_cid; |
| 304 | wire [2:0] b2_cpx_tid; |
| 305 | wire [5:0] b2_cpx_tnum; |
| 306 | wire b2_cpx_ctrue; |
| 307 | wire b2_cpx_swap; |
| 308 | wire b2_cpx_valid; |
| 309 | |
| 310 | // b2_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 311 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 312 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 313 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 314 | // for the StAck of a Swap/Ldstub. |
| 315 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 316 | |
| 317 | assign b2_cpx_pkt = `TOP.b2_cpx_pkt; |
| 318 | assign b2_cpx_pa = `TOP.b2_cpx_pa; |
| 319 | assign b2_cpx_cid = `TOP.b2_cpx_cid; |
| 320 | assign b2_cpx_tid = b2_cpx_pkt[`CPX_TID]; |
| 321 | assign b2_cpx_tnum = {b2_cpx_cid,b2_cpx_tid}; |
| 322 | assign b2_cpx_ctrue = `TOP.b2_cpx_ctrue; // ctrue = compare true for CAS |
| 323 | assign b2_cpx_swap = `TOP.b2_cpx_swap; // swap = St Ack is from a Swap |
| 324 | assign b2_cpx_valid = b2_cpx_pkt[`CPX_VALID]; |
| 325 | |
| 326 | //--------------------- |
| 327 | // Evict |
| 328 | |
| 329 | reg [31:0] b2_ev_vect0; |
| 330 | reg [23:0] b2_ev_vect1; |
| 331 | reg [31:0] b2_ev_vect2; |
| 332 | reg [23:0] b2_ev_vect3; |
| 333 | reg [1:0] b2_pa54; |
| 334 | reg [31:0] b2_inv_vect [0:3]; |
| 335 | reg [39:0] b2_evict_pa; |
| 336 | wire [39:0] b2_ev_pa; |
| 337 | reg [31:0] b2_evict_inv_vect; |
| 338 | |
| 339 | wire b2_evict; |
| 340 | wire [111:0] b2_ev_invvect; |
| 341 | |
| 342 | assign b2_evict = b2_cpx_valid & |
| 343 | (b2_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 344 | assign b2_ev_invvect = b2_cpx_pkt[`CPX_VINV_VECT]; |
| 345 | assign b2_ev_pa = b2_cpx_pa; |
| 346 | |
| 347 | //--------------------- |
| 348 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 349 | |
| 350 | wire b2_load_data_miss; |
| 351 | wire b2_ldd_suppress; |
| 352 | |
| 353 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 354 | |
| 355 | assign b2_load_data_miss = b2_cpx_valid & |
| 356 | ((((b2_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 357 | (b2_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 358 | (b2_cpx_pkt[`CPX_PF]==1'b0)) || |
| 359 | ((b2_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 360 | (b2_cpx_swap==1'b1))); |
| 361 | |
| 362 | assign b2_ldd_suppress = (b2_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 363 | |
| 364 | //--------------------- |
| 365 | // Store L2 Commit |
| 366 | |
| 367 | wire b2_store_commit; |
| 368 | wire [7:0] b2_stc_size; |
| 369 | wire [31:0] b2_stc_inv_vect; |
| 370 | reg [31:0] b2_stc_vect; |
| 371 | wire b2_stc_l2hit; |
| 372 | wire b2_stc_suppress; |
| 373 | |
| 374 | // rtntyp covers ST, CAS, SWAP since same decode |
| 375 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 376 | assign b2_store_commit = b2_cpx_valid & |
| 377 | (b2_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 378 | (b2_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 379 | // Set size=0 if CAS store didn't happen |
| 380 | assign b2_stc_size = (b2_cpx_pkt[`CPX_ATOMIC] & !b2_cpx_ctrue) ? |
| 381 | 8'b0 : b2_cpx_pkt[`CPX_VACK_BMASK]; |
| 382 | |
| 383 | assign b2_stc_inv_vect = b2_cpx_pkt[`CPX_VACK_VECT]; |
| 384 | assign b2_stc_suppress = (b2_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 385 | |
| 386 | // SPC bench - all L2 accesses are hits because this is used to |
| 387 | // determine whether Block Init St will initialize cache line or not |
| 388 | // if l2hit, then memory model doesn't initialize cache line |
| 389 | // in SPC bench, cache line is never initialized by CCX stub. |
| 390 | assign b2_stc_l2hit = 1'b1; |
| 391 | |
| 392 | `endif |
| 393 | `endif |
| 394 | |
| 395 | `ifdef NO_L2_BNK3 |
| 396 | `else |
| 397 | `ifdef NOL2RTL |
| 398 | |
| 399 | //---------------------------------------------------------- |
| 400 | // Signals for L2 Stub Bank3 |
| 401 | |
| 402 | wire [145:0] b3_cpx_pkt; |
| 403 | wire [39:0] b3_cpx_pa; |
| 404 | wire [2:0] b3_cpx_cid; |
| 405 | wire [2:0] b3_cpx_tid; |
| 406 | wire [5:0] b3_cpx_tnum; |
| 407 | wire b3_cpx_ctrue; |
| 408 | wire b3_cpx_swap; |
| 409 | wire b3_cpx_valid; |
| 410 | |
| 411 | // b3_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 412 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 413 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 414 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 415 | // for the StAck of a Swap/Ldstub. |
| 416 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 417 | |
| 418 | assign b3_cpx_pkt = `TOP.b3_cpx_pkt; |
| 419 | assign b3_cpx_pa = `TOP.b3_cpx_pa; |
| 420 | assign b3_cpx_cid = `TOP.b3_cpx_cid; |
| 421 | assign b3_cpx_tid = b3_cpx_pkt[`CPX_TID]; |
| 422 | assign b3_cpx_tnum = {b3_cpx_cid,b3_cpx_tid}; |
| 423 | assign b3_cpx_ctrue = `TOP.b3_cpx_ctrue; // ctrue = compare true for CAS |
| 424 | assign b3_cpx_swap = `TOP.b3_cpx_swap; // swap = St Ack is from a Swap |
| 425 | assign b3_cpx_valid = b3_cpx_pkt[`CPX_VALID]; |
| 426 | |
| 427 | //--------------------- |
| 428 | // Evict |
| 429 | |
| 430 | reg [31:0] b3_ev_vect0; |
| 431 | reg [23:0] b3_ev_vect1; |
| 432 | reg [31:0] b3_ev_vect2; |
| 433 | reg [23:0] b3_ev_vect3; |
| 434 | reg [1:0] b3_pa54; |
| 435 | reg [31:0] b3_inv_vect [0:3]; |
| 436 | reg [39:0] b3_evict_pa; |
| 437 | wire [39:0] b3_ev_pa; |
| 438 | reg [31:0] b3_evict_inv_vect; |
| 439 | |
| 440 | wire b3_evict; |
| 441 | wire [111:0] b3_ev_invvect; |
| 442 | |
| 443 | assign b3_evict = b3_cpx_valid & |
| 444 | (b3_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 445 | assign b3_ev_invvect = b3_cpx_pkt[`CPX_VINV_VECT]; |
| 446 | assign b3_ev_pa = b3_cpx_pa; |
| 447 | |
| 448 | //--------------------- |
| 449 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 450 | |
| 451 | wire b3_load_data_miss; |
| 452 | wire b3_ldd_suppress; |
| 453 | |
| 454 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 455 | |
| 456 | assign b3_load_data_miss = b3_cpx_valid & |
| 457 | ((((b3_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 458 | (b3_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 459 | (b3_cpx_pkt[`CPX_PF]==1'b0)) || |
| 460 | ((b3_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 461 | (b3_cpx_swap==1'b1))); |
| 462 | |
| 463 | assign b3_ldd_suppress = (b3_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 464 | |
| 465 | //--------------------- |
| 466 | // Store L2 Commit |
| 467 | |
| 468 | wire b3_store_commit; |
| 469 | wire [7:0] b3_stc_size; |
| 470 | wire [31:0] b3_stc_inv_vect; |
| 471 | reg [31:0] b3_stc_vect; |
| 472 | wire b3_stc_l2hit; |
| 473 | wire b3_stc_suppress; |
| 474 | |
| 475 | // rtntyp covers ST, CAS, SWAP since same decode |
| 476 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 477 | assign b3_store_commit = b3_cpx_valid & |
| 478 | (b3_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 479 | (b3_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 480 | // Set size=0 if CAS store didn't happen |
| 481 | assign b3_stc_size = (b3_cpx_pkt[`CPX_ATOMIC] & !b3_cpx_ctrue) ? |
| 482 | 8'b0 : b3_cpx_pkt[`CPX_VACK_BMASK]; |
| 483 | |
| 484 | assign b3_stc_inv_vect = b3_cpx_pkt[`CPX_VACK_VECT]; |
| 485 | assign b3_stc_suppress = (b3_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 486 | |
| 487 | // SPC bench - all L2 accesses are hits because this is used to |
| 488 | // determine whether Block Init St will initialize cache line or not |
| 489 | // if l2hit, then memory model doesn't initialize cache line |
| 490 | // in SPC bench, cache line is never initialized by CCX stub. |
| 491 | assign b3_stc_l2hit = 1'b1; |
| 492 | |
| 493 | `endif |
| 494 | `endif |
| 495 | |
| 496 | `ifdef NO_L2_BNK4 |
| 497 | `else |
| 498 | `ifdef NOL2RTL |
| 499 | |
| 500 | //---------------------------------------------------------- |
| 501 | // Signals for L2 Stub Bank4 |
| 502 | |
| 503 | wire [145:0] b4_cpx_pkt; |
| 504 | wire [39:0] b4_cpx_pa; |
| 505 | wire [2:0] b4_cpx_cid; |
| 506 | wire [2:0] b4_cpx_tid; |
| 507 | wire [5:0] b4_cpx_tnum; |
| 508 | wire b4_cpx_ctrue; |
| 509 | wire b4_cpx_swap; |
| 510 | wire b4_cpx_valid; |
| 511 | |
| 512 | // b4_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 513 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 514 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 515 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 516 | // for the StAck of a Swap/Ldstub. |
| 517 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 518 | |
| 519 | assign b4_cpx_pkt = `TOP.b4_cpx_pkt; |
| 520 | assign b4_cpx_pa = `TOP.b4_cpx_pa; |
| 521 | assign b4_cpx_cid = `TOP.b4_cpx_cid; |
| 522 | assign b4_cpx_tid = b4_cpx_pkt[`CPX_TID]; |
| 523 | assign b4_cpx_tnum = {b4_cpx_cid,b4_cpx_tid}; |
| 524 | assign b4_cpx_ctrue = `TOP.b4_cpx_ctrue; // ctrue = compare true for CAS |
| 525 | assign b4_cpx_swap = `TOP.b4_cpx_swap; // swap = St Ack is from a Swap |
| 526 | assign b4_cpx_valid = b4_cpx_pkt[`CPX_VALID]; |
| 527 | |
| 528 | //--------------------- |
| 529 | // Evict |
| 530 | |
| 531 | reg [31:0] b4_ev_vect0; |
| 532 | reg [23:0] b4_ev_vect1; |
| 533 | reg [31:0] b4_ev_vect2; |
| 534 | reg [23:0] b4_ev_vect3; |
| 535 | reg [1:0] b4_pa54; |
| 536 | reg [31:0] b4_inv_vect [0:3]; |
| 537 | reg [39:0] b4_evict_pa; |
| 538 | wire [39:0] b4_ev_pa; |
| 539 | reg [31:0] b4_evict_inv_vect; |
| 540 | |
| 541 | wire b4_evict; |
| 542 | wire [111:0] b4_ev_invvect; |
| 543 | |
| 544 | assign b4_evict = b4_cpx_valid & |
| 545 | (b4_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 546 | assign b4_ev_invvect = b4_cpx_pkt[`CPX_VINV_VECT]; |
| 547 | assign b4_ev_pa = b4_cpx_pa; |
| 548 | |
| 549 | //--------------------- |
| 550 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 551 | |
| 552 | wire b4_load_data_miss; |
| 553 | wire b4_ldd_suppress; |
| 554 | |
| 555 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 556 | |
| 557 | assign b4_load_data_miss = b4_cpx_valid & |
| 558 | ((((b4_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 559 | (b4_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 560 | (b4_cpx_pkt[`CPX_PF]==1'b0)) || |
| 561 | ((b4_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 562 | (b4_cpx_swap==1'b1))); |
| 563 | |
| 564 | assign b4_ldd_suppress = (b4_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 565 | |
| 566 | //--------------------- |
| 567 | // Store L2 Commit |
| 568 | |
| 569 | wire b4_store_commit; |
| 570 | wire [7:0] b4_stc_size; |
| 571 | wire [31:0] b4_stc_inv_vect; |
| 572 | reg [31:0] b4_stc_vect; |
| 573 | wire b4_stc_l2hit; |
| 574 | wire b4_stc_suppress; |
| 575 | |
| 576 | // rtntyp covers ST, CAS, SWAP since same decode |
| 577 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 578 | assign b4_store_commit = b4_cpx_valid & |
| 579 | (b4_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 580 | (b4_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 581 | // Set size=0 if CAS store didn't happen |
| 582 | assign b4_stc_size = (b4_cpx_pkt[`CPX_ATOMIC] & !b4_cpx_ctrue) ? |
| 583 | 8'b0 : b4_cpx_pkt[`CPX_VACK_BMASK]; |
| 584 | |
| 585 | assign b4_stc_inv_vect = b4_cpx_pkt[`CPX_VACK_VECT]; |
| 586 | assign b4_stc_suppress = (b4_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 587 | |
| 588 | // SPC bench - all L2 accesses are hits because this is used to |
| 589 | // determine whether Block Init St will initialize cache line or not |
| 590 | // if l2hit, then memory model doesn't initialize cache line |
| 591 | // in SPC bench, cache line is never initialized by CCX stub. |
| 592 | assign b4_stc_l2hit = 1'b1; |
| 593 | |
| 594 | `endif |
| 595 | `endif |
| 596 | |
| 597 | `ifdef NO_L2_BNK5 |
| 598 | `else |
| 599 | `ifdef NOL2RTL |
| 600 | |
| 601 | //---------------------------------------------------------- |
| 602 | // Signals for L2 Stub Bank5 |
| 603 | |
| 604 | wire [145:0] b5_cpx_pkt; |
| 605 | wire [39:0] b5_cpx_pa; |
| 606 | wire [2:0] b5_cpx_cid; |
| 607 | wire [2:0] b5_cpx_tid; |
| 608 | wire [5:0] b5_cpx_tnum; |
| 609 | wire b5_cpx_ctrue; |
| 610 | wire b5_cpx_swap; |
| 611 | wire b5_cpx_valid; |
| 612 | |
| 613 | // b5_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 614 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 615 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 616 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 617 | // for the StAck of a Swap/Ldstub. |
| 618 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 619 | |
| 620 | assign b5_cpx_pkt = `TOP.b5_cpx_pkt; |
| 621 | assign b5_cpx_pa = `TOP.b5_cpx_pa; |
| 622 | assign b5_cpx_cid = `TOP.b5_cpx_cid; |
| 623 | assign b5_cpx_tid = b5_cpx_pkt[`CPX_TID]; |
| 624 | assign b5_cpx_tnum = {b5_cpx_cid,b5_cpx_tid}; |
| 625 | assign b5_cpx_ctrue = `TOP.b5_cpx_ctrue; // ctrue = compare true for CAS |
| 626 | assign b5_cpx_swap = `TOP.b5_cpx_swap; // swap = St Ack is from a Swap |
| 627 | assign b5_cpx_valid = b5_cpx_pkt[`CPX_VALID]; |
| 628 | |
| 629 | //--------------------- |
| 630 | // Evict |
| 631 | |
| 632 | reg [31:0] b5_ev_vect0; |
| 633 | reg [23:0] b5_ev_vect1; |
| 634 | reg [31:0] b5_ev_vect2; |
| 635 | reg [23:0] b5_ev_vect3; |
| 636 | reg [1:0] b5_pa54; |
| 637 | reg [31:0] b5_inv_vect [0:3]; |
| 638 | reg [39:0] b5_evict_pa; |
| 639 | wire [39:0] b5_ev_pa; |
| 640 | reg [31:0] b5_evict_inv_vect; |
| 641 | |
| 642 | wire b5_evict; |
| 643 | wire [111:0] b5_ev_invvect; |
| 644 | |
| 645 | assign b5_evict = b5_cpx_valid & |
| 646 | (b5_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 647 | assign b5_ev_invvect = b5_cpx_pkt[`CPX_VINV_VECT]; |
| 648 | assign b5_ev_pa = b5_cpx_pa; |
| 649 | |
| 650 | //--------------------- |
| 651 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 652 | |
| 653 | wire b5_load_data_miss; |
| 654 | wire b5_ldd_suppress; |
| 655 | |
| 656 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 657 | |
| 658 | assign b5_load_data_miss = b5_cpx_valid & |
| 659 | ((((b5_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 660 | (b5_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 661 | (b5_cpx_pkt[`CPX_PF]==1'b0)) || |
| 662 | ((b5_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 663 | (b5_cpx_swap==1'b1))); |
| 664 | |
| 665 | assign b5_ldd_suppress = (b5_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 666 | |
| 667 | //--------------------- |
| 668 | // Store L2 Commit |
| 669 | |
| 670 | wire b5_store_commit; |
| 671 | wire [7:0] b5_stc_size; |
| 672 | wire [31:0] b5_stc_inv_vect; |
| 673 | reg [31:0] b5_stc_vect; |
| 674 | wire b5_stc_l2hit; |
| 675 | wire b5_stc_suppress; |
| 676 | |
| 677 | // rtntyp covers ST, CAS, SWAP since same decode |
| 678 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 679 | assign b5_store_commit = b5_cpx_valid & |
| 680 | (b5_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 681 | (b5_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 682 | // Set size=0 if CAS store didn't happen |
| 683 | assign b5_stc_size = (b5_cpx_pkt[`CPX_ATOMIC] & !b5_cpx_ctrue) ? |
| 684 | 8'b0 : b5_cpx_pkt[`CPX_VACK_BMASK]; |
| 685 | |
| 686 | assign b5_stc_inv_vect = b5_cpx_pkt[`CPX_VACK_VECT]; |
| 687 | assign b5_stc_suppress = (b5_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 688 | |
| 689 | // SPC bench - all L2 accesses are hits because this is used to |
| 690 | // determine whether Block Init St will initialize cache line or not |
| 691 | // if l2hit, then memory model doesn't initialize cache line |
| 692 | // in SPC bench, cache line is never initialized by CCX stub. |
| 693 | assign b5_stc_l2hit = 1'b1; |
| 694 | |
| 695 | `endif |
| 696 | `endif |
| 697 | |
| 698 | `ifdef NO_L2_BNK6 |
| 699 | `else |
| 700 | `ifdef NOL2RTL |
| 701 | |
| 702 | //---------------------------------------------------------- |
| 703 | // Signals for L2 Stub Bank6 |
| 704 | |
| 705 | wire [145:0] b6_cpx_pkt; |
| 706 | wire [39:0] b6_cpx_pa; |
| 707 | wire [2:0] b6_cpx_cid; |
| 708 | wire [2:0] b6_cpx_tid; |
| 709 | wire [5:0] b6_cpx_tnum; |
| 710 | wire b6_cpx_ctrue; |
| 711 | wire b6_cpx_swap; |
| 712 | wire b6_cpx_valid; |
| 713 | |
| 714 | // b6_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 715 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 716 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 717 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 718 | // for the StAck of a Swap/Ldstub. |
| 719 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 720 | |
| 721 | assign b6_cpx_pkt = `TOP.b6_cpx_pkt; |
| 722 | assign b6_cpx_pa = `TOP.b6_cpx_pa; |
| 723 | assign b6_cpx_cid = `TOP.b6_cpx_cid; |
| 724 | assign b6_cpx_tid = b6_cpx_pkt[`CPX_TID]; |
| 725 | assign b6_cpx_tnum = {b6_cpx_cid,b6_cpx_tid}; |
| 726 | assign b6_cpx_ctrue = `TOP.b6_cpx_ctrue; // ctrue = compare true for CAS |
| 727 | assign b6_cpx_swap = `TOP.b6_cpx_swap; // swap = St Ack is from a Swap |
| 728 | assign b6_cpx_valid = b6_cpx_pkt[`CPX_VALID]; |
| 729 | |
| 730 | //--------------------- |
| 731 | // Evict |
| 732 | |
| 733 | reg [31:0] b6_ev_vect0; |
| 734 | reg [23:0] b6_ev_vect1; |
| 735 | reg [31:0] b6_ev_vect2; |
| 736 | reg [23:0] b6_ev_vect3; |
| 737 | reg [1:0] b6_pa54; |
| 738 | reg [31:0] b6_inv_vect [0:3]; |
| 739 | reg [39:0] b6_evict_pa; |
| 740 | wire [39:0] b6_ev_pa; |
| 741 | reg [31:0] b6_evict_inv_vect; |
| 742 | |
| 743 | wire b6_evict; |
| 744 | wire [111:0] b6_ev_invvect; |
| 745 | |
| 746 | assign b6_evict = b6_cpx_valid & |
| 747 | (b6_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 748 | assign b6_ev_invvect = b6_cpx_pkt[`CPX_VINV_VECT]; |
| 749 | assign b6_ev_pa = b6_cpx_pa; |
| 750 | |
| 751 | //--------------------- |
| 752 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 753 | |
| 754 | wire b6_load_data_miss; |
| 755 | wire b6_ldd_suppress; |
| 756 | |
| 757 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 758 | |
| 759 | assign b6_load_data_miss = b6_cpx_valid & |
| 760 | ((((b6_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 761 | (b6_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 762 | (b6_cpx_pkt[`CPX_PF]==1'b0)) || |
| 763 | ((b6_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 764 | (b6_cpx_swap==1'b1))); |
| 765 | |
| 766 | assign b6_ldd_suppress = (b6_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 767 | |
| 768 | //--------------------- |
| 769 | // Store L2 Commit |
| 770 | |
| 771 | wire b6_store_commit; |
| 772 | wire [7:0] b6_stc_size; |
| 773 | wire [31:0] b6_stc_inv_vect; |
| 774 | reg [31:0] b6_stc_vect; |
| 775 | wire b6_stc_l2hit; |
| 776 | wire b6_stc_suppress; |
| 777 | |
| 778 | // rtntyp covers ST, CAS, SWAP since same decode |
| 779 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 780 | assign b6_store_commit = b6_cpx_valid & |
| 781 | (b6_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 782 | (b6_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 783 | // Set size=0 if CAS store didn't happen |
| 784 | assign b6_stc_size = (b6_cpx_pkt[`CPX_ATOMIC] & !b6_cpx_ctrue) ? |
| 785 | 8'b0 : b6_cpx_pkt[`CPX_VACK_BMASK]; |
| 786 | |
| 787 | assign b6_stc_inv_vect = b6_cpx_pkt[`CPX_VACK_VECT]; |
| 788 | assign b6_stc_suppress = (b6_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 789 | |
| 790 | // SPC bench - all L2 accesses are hits because this is used to |
| 791 | // determine whether Block Init St will initialize cache line or not |
| 792 | // if l2hit, then memory model doesn't initialize cache line |
| 793 | // in SPC bench, cache line is never initialized by CCX stub. |
| 794 | assign b6_stc_l2hit = 1'b1; |
| 795 | |
| 796 | `endif |
| 797 | `endif |
| 798 | |
| 799 | `ifdef NO_L2_BNK7 |
| 800 | `else |
| 801 | `ifdef NOL2RTL |
| 802 | |
| 803 | //---------------------------------------------------------- |
| 804 | // Signals for L2 Stub Bank7 |
| 805 | |
| 806 | wire [145:0] b7_cpx_pkt; |
| 807 | wire [39:0] b7_cpx_pa; |
| 808 | wire [2:0] b7_cpx_cid; |
| 809 | wire [2:0] b7_cpx_tid; |
| 810 | wire [5:0] b7_cpx_tnum; |
| 811 | wire b7_cpx_ctrue; |
| 812 | wire b7_cpx_swap; |
| 813 | wire b7_cpx_valid; |
| 814 | |
| 815 | // b7_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 816 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 817 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 818 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 819 | // for the StAck of a Swap/Ldstub. |
| 820 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 821 | |
| 822 | assign b7_cpx_pkt = `TOP.b7_cpx_pkt; |
| 823 | assign b7_cpx_pa = `TOP.b7_cpx_pa; |
| 824 | assign b7_cpx_cid = `TOP.b7_cpx_cid; |
| 825 | assign b7_cpx_tid = b7_cpx_pkt[`CPX_TID]; |
| 826 | assign b7_cpx_tnum = {b7_cpx_cid,b7_cpx_tid}; |
| 827 | assign b7_cpx_ctrue = `TOP.b7_cpx_ctrue; // ctrue = compare true for CAS |
| 828 | assign b7_cpx_swap = `TOP.b7_cpx_swap; // swap = St Ack is from a Swap |
| 829 | assign b7_cpx_valid = b7_cpx_pkt[`CPX_VALID]; |
| 830 | |
| 831 | //--------------------- |
| 832 | // Evict |
| 833 | |
| 834 | reg [31:0] b7_ev_vect0; |
| 835 | reg [23:0] b7_ev_vect1; |
| 836 | reg [31:0] b7_ev_vect2; |
| 837 | reg [23:0] b7_ev_vect3; |
| 838 | reg [1:0] b7_pa54; |
| 839 | reg [31:0] b7_inv_vect [0:3]; |
| 840 | reg [39:0] b7_evict_pa; |
| 841 | wire [39:0] b7_ev_pa; |
| 842 | reg [31:0] b7_evict_inv_vect; |
| 843 | |
| 844 | wire b7_evict; |
| 845 | wire [111:0] b7_ev_invvect; |
| 846 | |
| 847 | assign b7_evict = b7_cpx_valid & |
| 848 | (b7_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 849 | assign b7_ev_invvect = b7_cpx_pkt[`CPX_VINV_VECT]; |
| 850 | assign b7_ev_pa = b7_cpx_pa; |
| 851 | |
| 852 | //--------------------- |
| 853 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 854 | |
| 855 | wire b7_load_data_miss; |
| 856 | wire b7_ldd_suppress; |
| 857 | |
| 858 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 859 | |
| 860 | assign b7_load_data_miss = b7_cpx_valid & |
| 861 | ((((b7_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 862 | (b7_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 863 | (b7_cpx_pkt[`CPX_PF]==1'b0)) || |
| 864 | ((b7_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 865 | (b7_cpx_swap==1'b1))); |
| 866 | |
| 867 | assign b7_ldd_suppress = (b7_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 868 | |
| 869 | //--------------------- |
| 870 | // Store L2 Commit |
| 871 | |
| 872 | wire b7_store_commit; |
| 873 | wire [7:0] b7_stc_size; |
| 874 | wire [31:0] b7_stc_inv_vect; |
| 875 | reg [31:0] b7_stc_vect; |
| 876 | wire b7_stc_l2hit; |
| 877 | wire b7_stc_suppress; |
| 878 | |
| 879 | // rtntyp covers ST, CAS, SWAP since same decode |
| 880 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 881 | assign b7_store_commit = b7_cpx_valid & |
| 882 | (b7_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 883 | (b7_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 884 | // Set size=0 if CAS store didn't happen |
| 885 | assign b7_stc_size = (b7_cpx_pkt[`CPX_ATOMIC] & !b7_cpx_ctrue) ? |
| 886 | 8'b0 : b7_cpx_pkt[`CPX_VACK_BMASK]; |
| 887 | |
| 888 | assign b7_stc_inv_vect = b7_cpx_pkt[`CPX_VACK_VECT]; |
| 889 | assign b7_stc_suppress = (b7_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 890 | |
| 891 | // SPC bench - all L2 accesses are hits because this is used to |
| 892 | // determine whether Block Init St will initialize cache line or not |
| 893 | // if l2hit, then memory model doesn't initialize cache line |
| 894 | // in SPC bench, cache line is never initialized by CCX stub. |
| 895 | assign b7_stc_l2hit = 1'b1; |
| 896 | |
| 897 | `endif |
| 898 | `endif |
| 899 | |
| 900 | `ifdef NO_L2_BNK8 |
| 901 | `else |
| 902 | `ifdef NCURTL |
| 903 | //---------------------------------------------------------- |
| 904 | // Signals for NCU RTL Bank8 |
| 905 | |
| 906 | //wire [145:0] b8_cpx_pkt; // Unused for NCU since ldst_ncu probes the packets |
| 907 | wire [39:0] b8_cpx_pa; |
| 908 | wire [2:0] b8_cpx_cid; |
| 909 | wire [2:0] b8_cpx_tid; |
| 910 | wire [5:0] b8_cpx_tnum; |
| 911 | wire b8_cpx_ctrue; |
| 912 | wire b8_cpx_swap; |
| 913 | wire b8_cpx_valid; |
| 914 | |
| 915 | assign b8_cpx_pa = `LDST_NCU.ncu_cpx_pa; |
| 916 | assign b8_cpx_cid = `LDST_NCU.ncu_cpx_cid; |
| 917 | assign b8_cpx_tid = `LDST_NCU.ncu_cpx_tid; |
| 918 | assign b8_cpx_tnum = {b8_cpx_cid,b8_cpx_tid}; |
| 919 | assign b8_cpx_ctrue = 1'b0; // CAS,SWAP never sent to NCU |
| 920 | assign b8_cpx_swap = 1'b0; // CAS,SWAP never sent to NCU |
| 921 | assign b8_cpx_valid = `LDST_NCU.ncu_cpx_valid; |
| 922 | |
| 923 | //--------------------- |
| 924 | // Evict |
| 925 | |
| 926 | reg [31:0] b8_ev_vect0; |
| 927 | reg [23:0] b8_ev_vect1; |
| 928 | reg [31:0] b8_ev_vect2; |
| 929 | reg [23:0] b8_ev_vect3; |
| 930 | reg [1:0] b8_pa54; |
| 931 | reg [31:0] b8_inv_vect [0:3]; |
| 932 | reg [39:0] b8_evict_pa; |
| 933 | wire [39:0] b8_ev_pa; |
| 934 | reg [31:0] b8_evict_inv_vect; |
| 935 | |
| 936 | wire b8_evict; |
| 937 | wire [111:0] b8_ev_invvect; |
| 938 | |
| 939 | // Note: NCU cannot send evictions |
| 940 | |
| 941 | assign b8_evict = 0; |
| 942 | assign b8_ev_invvect = 0; |
| 943 | assign b8_ev_pa = 0; |
| 944 | |
| 945 | //--------------------- |
| 946 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 947 | |
| 948 | wire b8_load_data_miss; |
| 949 | wire b8_ldd_suppress; |
| 950 | |
| 951 | // Note: CAS,SWAP never sent to NCU |
| 952 | // Note: all LD/ST have nc=1 |
| 953 | |
| 954 | assign b8_load_data_miss = `LDST_NCU.ncu_cpx_valid & |
| 955 | (`LDST_NCU.ncu_cpx_typ==`CCX_REQ_LD); // Warning - must use PCX/REQ define! |
| 956 | |
| 957 | assign b8_ldd_suppress = (`LDST_NCU.ncu_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 958 | |
| 959 | //--------------------- |
| 960 | // Store L2 Commit |
| 961 | |
| 962 | wire b8_store_commit; |
| 963 | wire [7:0] b8_stc_size; |
| 964 | wire [31:0] b8_stc_inv_vect; |
| 965 | reg [31:0] b8_stc_vect; // 32 bits to support 32 cores (for future chips) |
| 966 | wire b8_stc_l2hit; |
| 967 | wire b8_stc_suppress; |
| 968 | |
| 969 | // Note: CAS,SWAP never sent to NCU |
| 970 | // Note: all LD/ST have nc=1 |
| 971 | |
| 972 | assign b8_store_commit = `LDST_NCU.ncu_cpx_valid & |
| 973 | (`LDST_NCU.ncu_cpx_typ==`CCX_REQ_ST); // Warning - must use PCX/REQ define! |
| 974 | |
| 975 | assign b8_stc_size = `LDST_NCU.ncu_cpx_bmask; |
| 976 | |
| 977 | assign b8_stc_inv_vect = 0; |
| 978 | assign b8_stc_suppress = (`LDST_NCU.ncu_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 979 | |
| 980 | // SPC bench - all L2 accesses are hits because this is used to |
| 981 | // determine whether Block Init St will initialize cache line or not |
| 982 | // if l2hit, then memory model doesn't initialize cache line |
| 983 | // in SPC bench, cache line is never initialized by CCX stub. |
| 984 | assign b8_stc_l2hit = 1'b1; |
| 985 | |
| 986 | `else |
| 987 | |
| 988 | //---------------------------------------------------------- |
| 989 | // Signals for NCU Stub Bank8 |
| 990 | |
| 991 | //---------------------------------------------------------- |
| 992 | // Signals for L2 Stub Bank8 |
| 993 | |
| 994 | wire [145:0] b8_cpx_pkt; |
| 995 | wire [39:0] b8_cpx_pa; |
| 996 | wire [2:0] b8_cpx_cid; |
| 997 | wire [2:0] b8_cpx_tid; |
| 998 | wire [5:0] b8_cpx_tnum; |
| 999 | wire b8_cpx_ctrue; |
| 1000 | wire b8_cpx_swap; |
| 1001 | wire b8_cpx_valid; |
| 1002 | |
| 1003 | // b8_cpx_swap is required for the L2 Stub to work properly on Swap/Ldstub. |
| 1004 | // Swap/Ldstub have 1 PCX but 2 CPX packets. |
| 1005 | // The L2 Stub processes the 2 CPX packets in 0 time when it accesses memory. |
| 1006 | // When probing L2 stub, ldst_sync must know to send out a LDDATA and STCOMMIT message |
| 1007 | // for the StAck of a Swap/Ldstub. |
| 1008 | // If StAck & cpx_swap==1, then send LDDATA & STCOMMIT. |
| 1009 | |
| 1010 | assign b8_cpx_pkt = `TOP.b8_cpx_pkt; |
| 1011 | assign b8_cpx_pa = `TOP.b8_cpx_pa; |
| 1012 | assign b8_cpx_cid = `TOP.b8_cpx_cid; |
| 1013 | assign b8_cpx_tid = b8_cpx_pkt[`CPX_TID]; |
| 1014 | assign b8_cpx_tnum = {b8_cpx_cid,b8_cpx_tid}; |
| 1015 | assign b8_cpx_ctrue = `TOP.b8_cpx_ctrue; // ctrue = compare true for CAS |
| 1016 | assign b8_cpx_swap = `TOP.b8_cpx_swap; // swap = St Ack is from a Swap |
| 1017 | assign b8_cpx_valid = b8_cpx_pkt[`CPX_VALID]; |
| 1018 | |
| 1019 | //--------------------- |
| 1020 | // Evict |
| 1021 | |
| 1022 | reg [31:0] b8_ev_vect0; |
| 1023 | reg [23:0] b8_ev_vect1; |
| 1024 | reg [31:0] b8_ev_vect2; |
| 1025 | reg [23:0] b8_ev_vect3; |
| 1026 | reg [1:0] b8_pa54; |
| 1027 | reg [31:0] b8_inv_vect [0:3]; |
| 1028 | reg [39:0] b8_evict_pa; |
| 1029 | wire [39:0] b8_ev_pa; |
| 1030 | reg [31:0] b8_evict_inv_vect; |
| 1031 | |
| 1032 | wire b8_evict; |
| 1033 | wire [111:0] b8_ev_invvect; |
| 1034 | |
| 1035 | assign b8_evict = b8_cpx_valid & |
| 1036 | (b8_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_EVICT); |
| 1037 | assign b8_ev_invvect = b8_cpx_pkt[`CPX_VINV_VECT]; |
| 1038 | assign b8_ev_pa = b8_cpx_pa; |
| 1039 | |
| 1040 | //--------------------- |
| 1041 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 1042 | |
| 1043 | wire b8_load_data_miss; |
| 1044 | wire b8_ldd_suppress; |
| 1045 | |
| 1046 | // Special case for L2 Stub - if StAck & swap, then send LDDATA |
| 1047 | |
| 1048 | assign b8_load_data_miss = b8_cpx_valid & |
| 1049 | ((((b8_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_LD)|| |
| 1050 | (b8_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_NCU_LD)) & |
| 1051 | (b8_cpx_pkt[`CPX_PF]==1'b0)) || |
| 1052 | ((b8_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 1053 | (b8_cpx_swap==1'b1))); |
| 1054 | |
| 1055 | assign b8_ldd_suppress = (b8_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1056 | |
| 1057 | //--------------------- |
| 1058 | // Store L2 Commit |
| 1059 | |
| 1060 | wire b8_store_commit; |
| 1061 | wire [7:0] b8_stc_size; |
| 1062 | wire [31:0] b8_stc_inv_vect; |
| 1063 | reg [31:0] b8_stc_vect; |
| 1064 | wire b8_stc_l2hit; |
| 1065 | wire b8_stc_suppress; |
| 1066 | |
| 1067 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1068 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1069 | assign b8_store_commit = b8_cpx_valid & |
| 1070 | (b8_cpx_pkt[`CPX_RTNTYP]== `CCX_RESP_ST) & |
| 1071 | (b8_cpx_pkt[`CPX_VACK_INVAL]==2'b0); |
| 1072 | // Set size=0 if CAS store didn't happen |
| 1073 | assign b8_stc_size = (b8_cpx_pkt[`CPX_ATOMIC] & !b8_cpx_ctrue) ? |
| 1074 | 8'b0 : b8_cpx_pkt[`CPX_VACK_BMASK]; |
| 1075 | |
| 1076 | assign b8_stc_inv_vect = b8_cpx_pkt[`CPX_VACK_VECT]; |
| 1077 | assign b8_stc_suppress = (b8_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1078 | |
| 1079 | // SPC bench - all L2 accesses are hits because this is used to |
| 1080 | // determine whether Block Init St will initialize cache line or not |
| 1081 | // if l2hit, then memory model doesn't initialize cache line |
| 1082 | // in SPC bench, cache line is never initialized by CCX stub. |
| 1083 | assign b8_stc_l2hit = 1'b1; |
| 1084 | |
| 1085 | `endif |
| 1086 | `endif |
| 1087 | |
| 1088 | //========================================================== |
| 1089 | //========================================================== |
| 1090 | // L2 RTL Probes |
| 1091 | |
| 1092 | `ifdef NO_L2_BNK0 |
| 1093 | `else |
| 1094 | `ifdef NOL2RTL |
| 1095 | `else |
| 1096 | |
| 1097 | //---------------------------------------------------------- |
| 1098 | // Signals for L2 RTL Bank0 |
| 1099 | |
| 1100 | wire [2:0] b0_cpx_cid_c8; |
| 1101 | reg [2:0] b0_cpx_cid_c9; |
| 1102 | wire [2:0] b0_cpx_cid; |
| 1103 | wire [145:0] b0_cpx_pkt_c8; |
| 1104 | wire [39:0] b0_pa_c8; |
| 1105 | reg [39:0] b0_pa_c9; |
| 1106 | wire [39:0] b0_cpx_pa; |
| 1107 | wire [39:0] b0_ev_pa_c4; |
| 1108 | reg [39:0] b0_ev_pa_c5; |
| 1109 | reg [39:0] b0_ev_pa_c52; |
| 1110 | reg [39:0] b0_ev_pa_c6; |
| 1111 | reg [39:0] b0_ev_pa_c7; |
| 1112 | reg [39:0] b0_ev_pa_c8; |
| 1113 | wire [39:0] b0_ev_pa; |
| 1114 | wire b0_req_c6; |
| 1115 | reg b0_req_c7; |
| 1116 | reg b0_req_c8; |
| 1117 | wire b0_cpx_valid; |
| 1118 | wire b0_cpx_pf; |
| 1119 | wire [3:0] b0_cpx_rtntyp; |
| 1120 | wire [2:0] b0_cpx_tid; |
| 1121 | wire [5:0] b0_cpx_tnum; |
| 1122 | wire [39:0] b0_stall_c1; |
| 1123 | reg [39:0] b0_stall_c2; |
| 1124 | reg [39:0] b0_stall_c3; |
| 1125 | reg [39:0] b0_stall_c4; |
| 1126 | reg [39:0] b0_stall_c5; |
| 1127 | reg [39:0] b0_stall_c52; |
| 1128 | reg [39:0] b0_stall_c6; |
| 1129 | reg [39:0] b0_stall_c7; |
| 1130 | reg [39:0] b0_stall_c8; |
| 1131 | reg [39:0] b0_stall_c9; |
| 1132 | |
| 1133 | assign b0_cpx_cid_c8 = `CPU.l2t0.oque.inst_cpuid_c8; |
| 1134 | // When pipeline stalls, pa must be stalled, too. |
| 1135 | assign b0_cpx_cid = (b0_stall_c9) ? b0_cpx_cid_c9 : b0_cpx_cid_c8; |
| 1136 | assign b0_cpx_pkt_c8 = `CPU.l2t0.oque.oque_oq_array_data_in; |
| 1137 | assign b0_pa_c8 = `CPU.l2t0.arbadr.arbdp_addr_c8; |
| 1138 | // When pipeline stalls, pa must be stalled, too. |
| 1139 | assign b0_cpx_pa = (b0_stall_c9) ? b0_pa_c9 : b0_pa_c8; |
| 1140 | assign b0_ev_pa_c4 = `CPU.l2t0.evctag.evctag_wb_write_addr; |
| 1141 | assign b0_ev_pa = b0_ev_pa_c8; |
| 1142 | assign b0_req_c6 = |(`CPU.l2t0.oqu.req_out_c6); |
| 1143 | assign b0_cpx_tnum = {b0_cpx_cid,b0_cpx_tid}; |
| 1144 | assign b0_cpx_tid = b0_cpx_pkt_c8[`CPX_TID]; |
| 1145 | assign b0_cpx_valid = b0_cpx_pkt_c8[`CPX_VALID]; |
| 1146 | assign b0_cpx_pf = b0_cpx_pkt_c8[`CPX_PF]; |
| 1147 | assign b0_cpx_rtntyp = b0_cpx_pkt_c8[`CPX_RTNTYP]; |
| 1148 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 1149 | assign b0_stall_c1 = `CPU.l2t0.arb.arb_inst_diag_c1; |
| 1150 | |
| 1151 | //--------------------- |
| 1152 | // Load Data |
| 1153 | |
| 1154 | wire b0_load_data_miss; |
| 1155 | wire b0_ldd_suppress; |
| 1156 | |
| 1157 | assign b0_load_data_miss = b0_req_c8 && |
| 1158 | (b0_cpx_valid==1'b1) && |
| 1159 | ((b0_cpx_rtntyp==`CCX_RESP_LD)|| |
| 1160 | (b0_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 1161 | (b0_cpx_pf==1'b0); |
| 1162 | assign b0_ldd_suppress = (b0_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1163 | |
| 1164 | //--------------------- |
| 1165 | // Store L2 Commit |
| 1166 | |
| 1167 | wire b0_store_commit; |
| 1168 | wire b0_stc_suppress; |
| 1169 | wire [7:0] b0_stc_size; |
| 1170 | wire [31:0] b0_stc_inv_vect; |
| 1171 | reg [31:0] b0_stc_vect; |
| 1172 | wire b0_stc_atomic; |
| 1173 | wire b0_l2_ctrue_c3; |
| 1174 | reg b0_l2_ctrue_c4; |
| 1175 | reg b0_l2_ctrue_c5; |
| 1176 | reg b0_l2_ctrue_c52; |
| 1177 | reg b0_l2_ctrue_c6; |
| 1178 | reg b0_l2_ctrue_c7; |
| 1179 | reg b0_l2_ctrue_c8; |
| 1180 | wire b0_stc_l2hit; |
| 1181 | wire b0_stc_l2hit_c3; |
| 1182 | reg b0_stc_l2hit_c4; |
| 1183 | reg b0_stc_l2hit_c5; |
| 1184 | reg b0_stc_l2hit_c52; |
| 1185 | reg b0_stc_l2hit_c6; |
| 1186 | reg b0_stc_l2hit_c7; |
| 1187 | reg b0_stc_l2hit_c8; |
| 1188 | wire b0_cam_pa_match_c1; |
| 1189 | wire b0_csr_l2_bypass_mode_on; |
| 1190 | reg b0_cam_pa_match_c2; |
| 1191 | reg b0_cam_pa_match_c3; |
| 1192 | |
| 1193 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1194 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1195 | assign b0_store_commit = b0_req_c8 && |
| 1196 | (b0_cpx_valid==1'b1) && |
| 1197 | (b0_cpx_rtntyp==`CCX_RESP_ST) & |
| 1198 | (b0_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 1199 | assign b0_stc_suppress = (b0_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1200 | assign b0_stc_inv_vect = b0_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 1201 | assign b0_stc_atomic = b0_cpx_pkt_c8[`CPX_ATOMIC]; |
| 1202 | |
| 1203 | assign b0_stc_size = (b0_stc_atomic & !b0_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 1204 | 8'b0 : b0_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 1205 | assign b0_l2_ctrue_c3 = `CPU.l2t0.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 1206 | assign b0_csr_l2_bypass_mode_on = `CPU.l2t0.csr_l2_bypass_mode_on; // l2 off mode |
| 1207 | assign b0_cam_pa_match_c1 = (|(`CPU.l2t0.misbuf.mb_cam_match | {32{`CPU.l2t0.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 1208 | | {32{`CPU.l2t0.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 1209 | assign b0_stc_l2hit_c3 = {32{`CPU.l2t0.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 1210 | ((`CPU.l2t0.tagctl.tag_hit_l2orfb_c3 & !(b0_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 1211 | (`CPU.l2t0.misbuf.misbuf_hit_c3 & b0_cam_pa_match_c3 & !(b0_csr_l2_bypass_mode_on))) |
| 1212 | : |
| 1213 | ((`CPU.l2t0.tagctl.tag_hit_l2orfb_c3 & !(b0_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 1214 | (`CPU.l2t0.misbuf.misbuf_hit_c3 & !(b0_csr_l2_bypass_mode_on))) |
| 1215 | ; |
| 1216 | assign b0_stc_l2hit = b0_stc_l2hit_c8; |
| 1217 | |
| 1218 | //--------------------- |
| 1219 | // Evict |
| 1220 | |
| 1221 | reg [31:0] b0_ev_vect0; |
| 1222 | reg [23:0] b0_ev_vect1; |
| 1223 | reg [31:0] b0_ev_vect2; |
| 1224 | reg [23:0] b0_ev_vect3; |
| 1225 | reg [1:0] b0_pa54; |
| 1226 | reg [31:0] b0_inv_vect [0:3]; |
| 1227 | reg [39:0] b0_evict_pa; |
| 1228 | reg [31:0] b0_evict_inv_vect; |
| 1229 | |
| 1230 | wire b0_evict; |
| 1231 | wire [111:0] b0_ev_invvect; |
| 1232 | |
| 1233 | assign b0_evict = b0_req_c8 && |
| 1234 | (b0_cpx_valid==1'b1) && |
| 1235 | (b0_cpx_rtntyp==`CCX_RESP_EVICT); |
| 1236 | assign b0_ev_invvect = b0_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 1237 | |
| 1238 | `endif |
| 1239 | `endif |
| 1240 | |
| 1241 | `ifdef NO_L2_BNK1 |
| 1242 | `else |
| 1243 | `ifdef NOL2RTL |
| 1244 | `else |
| 1245 | |
| 1246 | //---------------------------------------------------------- |
| 1247 | // Signals for L2 RTL Bank1 |
| 1248 | |
| 1249 | wire [2:0] b1_cpx_cid_c8; |
| 1250 | reg [2:0] b1_cpx_cid_c9; |
| 1251 | wire [2:0] b1_cpx_cid; |
| 1252 | wire [145:0] b1_cpx_pkt_c8; |
| 1253 | wire [39:0] b1_pa_c8; |
| 1254 | reg [39:0] b1_pa_c9; |
| 1255 | wire [39:0] b1_cpx_pa; |
| 1256 | wire [39:0] b1_ev_pa_c4; |
| 1257 | reg [39:0] b1_ev_pa_c5; |
| 1258 | reg [39:0] b1_ev_pa_c52; |
| 1259 | reg [39:0] b1_ev_pa_c6; |
| 1260 | reg [39:0] b1_ev_pa_c7; |
| 1261 | reg [39:0] b1_ev_pa_c8; |
| 1262 | wire [39:0] b1_ev_pa; |
| 1263 | wire b1_req_c6; |
| 1264 | reg b1_req_c7; |
| 1265 | reg b1_req_c8; |
| 1266 | wire b1_cpx_valid; |
| 1267 | wire b1_cpx_pf; |
| 1268 | wire [3:0] b1_cpx_rtntyp; |
| 1269 | wire [2:0] b1_cpx_tid; |
| 1270 | wire [5:0] b1_cpx_tnum; |
| 1271 | wire [39:0] b1_stall_c1; |
| 1272 | reg [39:0] b1_stall_c2; |
| 1273 | reg [39:0] b1_stall_c3; |
| 1274 | reg [39:0] b1_stall_c4; |
| 1275 | reg [39:0] b1_stall_c5; |
| 1276 | reg [39:0] b1_stall_c52; |
| 1277 | reg [39:0] b1_stall_c6; |
| 1278 | reg [39:0] b1_stall_c7; |
| 1279 | reg [39:0] b1_stall_c8; |
| 1280 | reg [39:0] b1_stall_c9; |
| 1281 | |
| 1282 | assign b1_cpx_cid_c8 = `CPU.l2t1.oque.inst_cpuid_c8; |
| 1283 | // When pipeline stalls, pa must be stalled, too. |
| 1284 | assign b1_cpx_cid = (b1_stall_c9) ? b1_cpx_cid_c9 : b1_cpx_cid_c8; |
| 1285 | assign b1_cpx_pkt_c8 = `CPU.l2t1.oque.oque_oq_array_data_in; |
| 1286 | assign b1_pa_c8 = `CPU.l2t1.arbadr.arbdp_addr_c8; |
| 1287 | // When pipeline stalls, pa must be stalled, too. |
| 1288 | assign b1_cpx_pa = (b1_stall_c9) ? b1_pa_c9 : b1_pa_c8; |
| 1289 | assign b1_ev_pa_c4 = `CPU.l2t1.evctag.evctag_wb_write_addr; |
| 1290 | assign b1_ev_pa = b1_ev_pa_c8; |
| 1291 | assign b1_req_c6 = |(`CPU.l2t1.oqu.req_out_c6); |
| 1292 | assign b1_cpx_tnum = {b1_cpx_cid,b1_cpx_tid}; |
| 1293 | assign b1_cpx_tid = b1_cpx_pkt_c8[`CPX_TID]; |
| 1294 | assign b1_cpx_valid = b1_cpx_pkt_c8[`CPX_VALID]; |
| 1295 | assign b1_cpx_pf = b1_cpx_pkt_c8[`CPX_PF]; |
| 1296 | assign b1_cpx_rtntyp = b1_cpx_pkt_c8[`CPX_RTNTYP]; |
| 1297 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 1298 | assign b1_stall_c1 = `CPU.l2t1.arb.arb_inst_diag_c1; |
| 1299 | |
| 1300 | //--------------------- |
| 1301 | // Load Data |
| 1302 | |
| 1303 | wire b1_load_data_miss; |
| 1304 | wire b1_ldd_suppress; |
| 1305 | |
| 1306 | assign b1_load_data_miss = b1_req_c8 && |
| 1307 | (b1_cpx_valid==1'b1) && |
| 1308 | ((b1_cpx_rtntyp==`CCX_RESP_LD)|| |
| 1309 | (b1_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 1310 | (b1_cpx_pf==1'b0); |
| 1311 | assign b1_ldd_suppress = (b1_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1312 | |
| 1313 | //--------------------- |
| 1314 | // Store L2 Commit |
| 1315 | |
| 1316 | wire b1_store_commit; |
| 1317 | wire b1_stc_suppress; |
| 1318 | wire [7:0] b1_stc_size; |
| 1319 | wire [31:0] b1_stc_inv_vect; |
| 1320 | reg [31:0] b1_stc_vect; |
| 1321 | wire b1_stc_atomic; |
| 1322 | wire b1_l2_ctrue_c3; |
| 1323 | reg b1_l2_ctrue_c4; |
| 1324 | reg b1_l2_ctrue_c5; |
| 1325 | reg b1_l2_ctrue_c52; |
| 1326 | reg b1_l2_ctrue_c6; |
| 1327 | reg b1_l2_ctrue_c7; |
| 1328 | reg b1_l2_ctrue_c8; |
| 1329 | wire b1_stc_l2hit; |
| 1330 | wire b1_stc_l2hit_c3; |
| 1331 | reg b1_stc_l2hit_c4; |
| 1332 | reg b1_stc_l2hit_c5; |
| 1333 | reg b1_stc_l2hit_c52; |
| 1334 | reg b1_stc_l2hit_c6; |
| 1335 | reg b1_stc_l2hit_c7; |
| 1336 | reg b1_stc_l2hit_c8; |
| 1337 | wire b1_cam_pa_match_c1; |
| 1338 | wire b1_csr_l2_bypass_mode_on; |
| 1339 | reg b1_cam_pa_match_c2; |
| 1340 | reg b1_cam_pa_match_c3; |
| 1341 | |
| 1342 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1343 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1344 | assign b1_store_commit = b1_req_c8 && |
| 1345 | (b1_cpx_valid==1'b1) && |
| 1346 | (b1_cpx_rtntyp==`CCX_RESP_ST) & |
| 1347 | (b1_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 1348 | assign b1_stc_suppress = (b1_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1349 | assign b1_stc_inv_vect = b1_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 1350 | assign b1_stc_atomic = b1_cpx_pkt_c8[`CPX_ATOMIC]; |
| 1351 | |
| 1352 | assign b1_stc_size = (b1_stc_atomic & !b1_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 1353 | 8'b0 : b1_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 1354 | assign b1_l2_ctrue_c3 = `CPU.l2t1.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 1355 | assign b1_csr_l2_bypass_mode_on = `CPU.l2t1.csr_l2_bypass_mode_on; // l2 off mode |
| 1356 | assign b1_cam_pa_match_c1 = (|(`CPU.l2t1.misbuf.mb_cam_match | {32{`CPU.l2t1.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 1357 | | {32{`CPU.l2t1.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 1358 | assign b1_stc_l2hit_c3 = {32{`CPU.l2t1.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 1359 | ((`CPU.l2t1.tagctl.tag_hit_l2orfb_c3 & !(b1_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 1360 | (`CPU.l2t1.misbuf.misbuf_hit_c3 & b1_cam_pa_match_c3 & !(b1_csr_l2_bypass_mode_on))) |
| 1361 | : |
| 1362 | ((`CPU.l2t1.tagctl.tag_hit_l2orfb_c3 & !(b1_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 1363 | (`CPU.l2t1.misbuf.misbuf_hit_c3 & !(b1_csr_l2_bypass_mode_on))) |
| 1364 | ; |
| 1365 | assign b1_stc_l2hit = b1_stc_l2hit_c8; |
| 1366 | |
| 1367 | //--------------------- |
| 1368 | // Evict |
| 1369 | |
| 1370 | reg [31:0] b1_ev_vect0; |
| 1371 | reg [23:0] b1_ev_vect1; |
| 1372 | reg [31:0] b1_ev_vect2; |
| 1373 | reg [23:0] b1_ev_vect3; |
| 1374 | reg [1:0] b1_pa54; |
| 1375 | reg [31:0] b1_inv_vect [0:3]; |
| 1376 | reg [39:0] b1_evict_pa; |
| 1377 | reg [31:0] b1_evict_inv_vect; |
| 1378 | |
| 1379 | wire b1_evict; |
| 1380 | wire [111:0] b1_ev_invvect; |
| 1381 | |
| 1382 | assign b1_evict = b1_req_c8 && |
| 1383 | (b1_cpx_valid==1'b1) && |
| 1384 | (b1_cpx_rtntyp==`CCX_RESP_EVICT); |
| 1385 | assign b1_ev_invvect = b1_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 1386 | |
| 1387 | `endif |
| 1388 | `endif |
| 1389 | |
| 1390 | `ifdef NO_L2_BNK2 |
| 1391 | `else |
| 1392 | `ifdef NOL2RTL |
| 1393 | `else |
| 1394 | |
| 1395 | //---------------------------------------------------------- |
| 1396 | // Signals for L2 RTL Bank2 |
| 1397 | |
| 1398 | wire [2:0] b2_cpx_cid_c8; |
| 1399 | reg [2:0] b2_cpx_cid_c9; |
| 1400 | wire [2:0] b2_cpx_cid; |
| 1401 | wire [145:0] b2_cpx_pkt_c8; |
| 1402 | wire [39:0] b2_pa_c8; |
| 1403 | reg [39:0] b2_pa_c9; |
| 1404 | wire [39:0] b2_cpx_pa; |
| 1405 | wire [39:0] b2_ev_pa_c4; |
| 1406 | reg [39:0] b2_ev_pa_c5; |
| 1407 | reg [39:0] b2_ev_pa_c52; |
| 1408 | reg [39:0] b2_ev_pa_c6; |
| 1409 | reg [39:0] b2_ev_pa_c7; |
| 1410 | reg [39:0] b2_ev_pa_c8; |
| 1411 | wire [39:0] b2_ev_pa; |
| 1412 | wire b2_req_c6; |
| 1413 | reg b2_req_c7; |
| 1414 | reg b2_req_c8; |
| 1415 | wire b2_cpx_valid; |
| 1416 | wire b2_cpx_pf; |
| 1417 | wire [3:0] b2_cpx_rtntyp; |
| 1418 | wire [2:0] b2_cpx_tid; |
| 1419 | wire [5:0] b2_cpx_tnum; |
| 1420 | wire [39:0] b2_stall_c1; |
| 1421 | reg [39:0] b2_stall_c2; |
| 1422 | reg [39:0] b2_stall_c3; |
| 1423 | reg [39:0] b2_stall_c4; |
| 1424 | reg [39:0] b2_stall_c5; |
| 1425 | reg [39:0] b2_stall_c52; |
| 1426 | reg [39:0] b2_stall_c6; |
| 1427 | reg [39:0] b2_stall_c7; |
| 1428 | reg [39:0] b2_stall_c8; |
| 1429 | reg [39:0] b2_stall_c9; |
| 1430 | |
| 1431 | assign b2_cpx_cid_c8 = `CPU.l2t2.oque.inst_cpuid_c8; |
| 1432 | // When pipeline stalls, pa must be stalled, too. |
| 1433 | assign b2_cpx_cid = (b2_stall_c9) ? b2_cpx_cid_c9 : b2_cpx_cid_c8; |
| 1434 | assign b2_cpx_pkt_c8 = `CPU.l2t2.oque.oque_oq_array_data_in; |
| 1435 | assign b2_pa_c8 = `CPU.l2t2.arbadr.arbdp_addr_c8; |
| 1436 | // When pipeline stalls, pa must be stalled, too. |
| 1437 | assign b2_cpx_pa = (b2_stall_c9) ? b2_pa_c9 : b2_pa_c8; |
| 1438 | assign b2_ev_pa_c4 = `CPU.l2t2.evctag.evctag_wb_write_addr; |
| 1439 | assign b2_ev_pa = b2_ev_pa_c8; |
| 1440 | assign b2_req_c6 = |(`CPU.l2t2.oqu.req_out_c6); |
| 1441 | assign b2_cpx_tnum = {b2_cpx_cid,b2_cpx_tid}; |
| 1442 | assign b2_cpx_tid = b2_cpx_pkt_c8[`CPX_TID]; |
| 1443 | assign b2_cpx_valid = b2_cpx_pkt_c8[`CPX_VALID]; |
| 1444 | assign b2_cpx_pf = b2_cpx_pkt_c8[`CPX_PF]; |
| 1445 | assign b2_cpx_rtntyp = b2_cpx_pkt_c8[`CPX_RTNTYP]; |
| 1446 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 1447 | assign b2_stall_c1 = `CPU.l2t2.arb.arb_inst_diag_c1; |
| 1448 | |
| 1449 | //--------------------- |
| 1450 | // Load Data |
| 1451 | |
| 1452 | wire b2_load_data_miss; |
| 1453 | wire b2_ldd_suppress; |
| 1454 | |
| 1455 | assign b2_load_data_miss = b2_req_c8 && |
| 1456 | (b2_cpx_valid==1'b1) && |
| 1457 | ((b2_cpx_rtntyp==`CCX_RESP_LD)|| |
| 1458 | (b2_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 1459 | (b2_cpx_pf==1'b0); |
| 1460 | assign b2_ldd_suppress = (b2_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1461 | |
| 1462 | //--------------------- |
| 1463 | // Store L2 Commit |
| 1464 | |
| 1465 | wire b2_store_commit; |
| 1466 | wire b2_stc_suppress; |
| 1467 | wire [7:0] b2_stc_size; |
| 1468 | wire [31:0] b2_stc_inv_vect; |
| 1469 | reg [31:0] b2_stc_vect; |
| 1470 | wire b2_stc_atomic; |
| 1471 | wire b2_l2_ctrue_c3; |
| 1472 | reg b2_l2_ctrue_c4; |
| 1473 | reg b2_l2_ctrue_c5; |
| 1474 | reg b2_l2_ctrue_c52; |
| 1475 | reg b2_l2_ctrue_c6; |
| 1476 | reg b2_l2_ctrue_c7; |
| 1477 | reg b2_l2_ctrue_c8; |
| 1478 | wire b2_stc_l2hit; |
| 1479 | wire b2_stc_l2hit_c3; |
| 1480 | reg b2_stc_l2hit_c4; |
| 1481 | reg b2_stc_l2hit_c5; |
| 1482 | reg b2_stc_l2hit_c52; |
| 1483 | reg b2_stc_l2hit_c6; |
| 1484 | reg b2_stc_l2hit_c7; |
| 1485 | reg b2_stc_l2hit_c8; |
| 1486 | wire b2_cam_pa_match_c1; |
| 1487 | wire b2_csr_l2_bypass_mode_on; |
| 1488 | reg b2_cam_pa_match_c2; |
| 1489 | reg b2_cam_pa_match_c3; |
| 1490 | |
| 1491 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1492 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1493 | assign b2_store_commit = b2_req_c8 && |
| 1494 | (b2_cpx_valid==1'b1) && |
| 1495 | (b2_cpx_rtntyp==`CCX_RESP_ST) & |
| 1496 | (b2_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 1497 | assign b2_stc_suppress = (b2_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1498 | assign b2_stc_inv_vect = b2_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 1499 | assign b2_stc_atomic = b2_cpx_pkt_c8[`CPX_ATOMIC]; |
| 1500 | |
| 1501 | assign b2_stc_size = (b2_stc_atomic & !b2_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 1502 | 8'b0 : b2_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 1503 | assign b2_l2_ctrue_c3 = `CPU.l2t2.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 1504 | assign b2_csr_l2_bypass_mode_on = `CPU.l2t2.csr_l2_bypass_mode_on; // l2 off mode |
| 1505 | assign b2_cam_pa_match_c1 = (|(`CPU.l2t2.misbuf.mb_cam_match | {32{`CPU.l2t2.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 1506 | | {32{`CPU.l2t2.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 1507 | assign b2_stc_l2hit_c3 = {32{`CPU.l2t2.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 1508 | ((`CPU.l2t2.tagctl.tag_hit_l2orfb_c3 & !(b2_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 1509 | (`CPU.l2t2.misbuf.misbuf_hit_c3 & b2_cam_pa_match_c3 & !(b2_csr_l2_bypass_mode_on))) |
| 1510 | : |
| 1511 | ((`CPU.l2t2.tagctl.tag_hit_l2orfb_c3 & !(b2_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 1512 | (`CPU.l2t2.misbuf.misbuf_hit_c3 & !(b2_csr_l2_bypass_mode_on))) |
| 1513 | ; |
| 1514 | assign b2_stc_l2hit = b2_stc_l2hit_c8; |
| 1515 | |
| 1516 | //--------------------- |
| 1517 | // Evict |
| 1518 | |
| 1519 | reg [31:0] b2_ev_vect0; |
| 1520 | reg [23:0] b2_ev_vect1; |
| 1521 | reg [31:0] b2_ev_vect2; |
| 1522 | reg [23:0] b2_ev_vect3; |
| 1523 | reg [1:0] b2_pa54; |
| 1524 | reg [31:0] b2_inv_vect [0:3]; |
| 1525 | reg [39:0] b2_evict_pa; |
| 1526 | reg [31:0] b2_evict_inv_vect; |
| 1527 | |
| 1528 | wire b2_evict; |
| 1529 | wire [111:0] b2_ev_invvect; |
| 1530 | |
| 1531 | assign b2_evict = b2_req_c8 && |
| 1532 | (b2_cpx_valid==1'b1) && |
| 1533 | (b2_cpx_rtntyp==`CCX_RESP_EVICT); |
| 1534 | assign b2_ev_invvect = b2_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 1535 | |
| 1536 | `endif |
| 1537 | `endif |
| 1538 | |
| 1539 | `ifdef NO_L2_BNK3 |
| 1540 | `else |
| 1541 | `ifdef NOL2RTL |
| 1542 | `else |
| 1543 | |
| 1544 | //---------------------------------------------------------- |
| 1545 | // Signals for L2 RTL Bank3 |
| 1546 | |
| 1547 | wire [2:0] b3_cpx_cid_c8; |
| 1548 | reg [2:0] b3_cpx_cid_c9; |
| 1549 | wire [2:0] b3_cpx_cid; |
| 1550 | wire [145:0] b3_cpx_pkt_c8; |
| 1551 | wire [39:0] b3_pa_c8; |
| 1552 | reg [39:0] b3_pa_c9; |
| 1553 | wire [39:0] b3_cpx_pa; |
| 1554 | wire [39:0] b3_ev_pa_c4; |
| 1555 | reg [39:0] b3_ev_pa_c5; |
| 1556 | reg [39:0] b3_ev_pa_c52; |
| 1557 | reg [39:0] b3_ev_pa_c6; |
| 1558 | reg [39:0] b3_ev_pa_c7; |
| 1559 | reg [39:0] b3_ev_pa_c8; |
| 1560 | wire [39:0] b3_ev_pa; |
| 1561 | wire b3_req_c6; |
| 1562 | reg b3_req_c7; |
| 1563 | reg b3_req_c8; |
| 1564 | wire b3_cpx_valid; |
| 1565 | wire b3_cpx_pf; |
| 1566 | wire [3:0] b3_cpx_rtntyp; |
| 1567 | wire [2:0] b3_cpx_tid; |
| 1568 | wire [5:0] b3_cpx_tnum; |
| 1569 | wire [39:0] b3_stall_c1; |
| 1570 | reg [39:0] b3_stall_c2; |
| 1571 | reg [39:0] b3_stall_c3; |
| 1572 | reg [39:0] b3_stall_c4; |
| 1573 | reg [39:0] b3_stall_c5; |
| 1574 | reg [39:0] b3_stall_c52; |
| 1575 | reg [39:0] b3_stall_c6; |
| 1576 | reg [39:0] b3_stall_c7; |
| 1577 | reg [39:0] b3_stall_c8; |
| 1578 | reg [39:0] b3_stall_c9; |
| 1579 | |
| 1580 | assign b3_cpx_cid_c8 = `CPU.l2t3.oque.inst_cpuid_c8; |
| 1581 | // When pipeline stalls, pa must be stalled, too. |
| 1582 | assign b3_cpx_cid = (b3_stall_c9) ? b3_cpx_cid_c9 : b3_cpx_cid_c8; |
| 1583 | assign b3_cpx_pkt_c8 = `CPU.l2t3.oque.oque_oq_array_data_in; |
| 1584 | assign b3_pa_c8 = `CPU.l2t3.arbadr.arbdp_addr_c8; |
| 1585 | // When pipeline stalls, pa must be stalled, too. |
| 1586 | assign b3_cpx_pa = (b3_stall_c9) ? b3_pa_c9 : b3_pa_c8; |
| 1587 | assign b3_ev_pa_c4 = `CPU.l2t3.evctag.evctag_wb_write_addr; |
| 1588 | assign b3_ev_pa = b3_ev_pa_c8; |
| 1589 | assign b3_req_c6 = |(`CPU.l2t3.oqu.req_out_c6); |
| 1590 | assign b3_cpx_tnum = {b3_cpx_cid,b3_cpx_tid}; |
| 1591 | assign b3_cpx_tid = b3_cpx_pkt_c8[`CPX_TID]; |
| 1592 | assign b3_cpx_valid = b3_cpx_pkt_c8[`CPX_VALID]; |
| 1593 | assign b3_cpx_pf = b3_cpx_pkt_c8[`CPX_PF]; |
| 1594 | assign b3_cpx_rtntyp = b3_cpx_pkt_c8[`CPX_RTNTYP]; |
| 1595 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 1596 | assign b3_stall_c1 = `CPU.l2t3.arb.arb_inst_diag_c1; |
| 1597 | |
| 1598 | //--------------------- |
| 1599 | // Load Data |
| 1600 | |
| 1601 | wire b3_load_data_miss; |
| 1602 | wire b3_ldd_suppress; |
| 1603 | |
| 1604 | assign b3_load_data_miss = b3_req_c8 && |
| 1605 | (b3_cpx_valid==1'b1) && |
| 1606 | ((b3_cpx_rtntyp==`CCX_RESP_LD)|| |
| 1607 | (b3_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 1608 | (b3_cpx_pf==1'b0); |
| 1609 | assign b3_ldd_suppress = (b3_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1610 | |
| 1611 | //--------------------- |
| 1612 | // Store L2 Commit |
| 1613 | |
| 1614 | wire b3_store_commit; |
| 1615 | wire b3_stc_suppress; |
| 1616 | wire [7:0] b3_stc_size; |
| 1617 | wire [31:0] b3_stc_inv_vect; |
| 1618 | reg [31:0] b3_stc_vect; |
| 1619 | wire b3_stc_atomic; |
| 1620 | wire b3_l2_ctrue_c3; |
| 1621 | reg b3_l2_ctrue_c4; |
| 1622 | reg b3_l2_ctrue_c5; |
| 1623 | reg b3_l2_ctrue_c52; |
| 1624 | reg b3_l2_ctrue_c6; |
| 1625 | reg b3_l2_ctrue_c7; |
| 1626 | reg b3_l2_ctrue_c8; |
| 1627 | wire b3_stc_l2hit; |
| 1628 | wire b3_stc_l2hit_c3; |
| 1629 | reg b3_stc_l2hit_c4; |
| 1630 | reg b3_stc_l2hit_c5; |
| 1631 | reg b3_stc_l2hit_c52; |
| 1632 | reg b3_stc_l2hit_c6; |
| 1633 | reg b3_stc_l2hit_c7; |
| 1634 | reg b3_stc_l2hit_c8; |
| 1635 | wire b3_cam_pa_match_c1; |
| 1636 | wire b3_csr_l2_bypass_mode_on; |
| 1637 | reg b3_cam_pa_match_c2; |
| 1638 | reg b3_cam_pa_match_c3; |
| 1639 | |
| 1640 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1641 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1642 | assign b3_store_commit = b3_req_c8 && |
| 1643 | (b3_cpx_valid==1'b1) && |
| 1644 | (b3_cpx_rtntyp==`CCX_RESP_ST) & |
| 1645 | (b3_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 1646 | assign b3_stc_suppress = (b3_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1647 | assign b3_stc_inv_vect = b3_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 1648 | assign b3_stc_atomic = b3_cpx_pkt_c8[`CPX_ATOMIC]; |
| 1649 | |
| 1650 | assign b3_stc_size = (b3_stc_atomic & !b3_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 1651 | 8'b0 : b3_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 1652 | assign b3_l2_ctrue_c3 = `CPU.l2t3.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 1653 | assign b3_csr_l2_bypass_mode_on = `CPU.l2t3.csr_l2_bypass_mode_on; // l2 off mode |
| 1654 | assign b3_cam_pa_match_c1 = (|(`CPU.l2t3.misbuf.mb_cam_match | {32{`CPU.l2t3.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 1655 | | {32{`CPU.l2t3.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 1656 | assign b3_stc_l2hit_c3 = {32{`CPU.l2t3.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 1657 | ((`CPU.l2t3.tagctl.tag_hit_l2orfb_c3 & !(b3_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 1658 | (`CPU.l2t3.misbuf.misbuf_hit_c3 & b3_cam_pa_match_c3 & !(b3_csr_l2_bypass_mode_on))) |
| 1659 | : |
| 1660 | ((`CPU.l2t3.tagctl.tag_hit_l2orfb_c3 & !(b3_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 1661 | (`CPU.l2t3.misbuf.misbuf_hit_c3 & !(b3_csr_l2_bypass_mode_on))) |
| 1662 | ; |
| 1663 | assign b3_stc_l2hit = b3_stc_l2hit_c8; |
| 1664 | |
| 1665 | //--------------------- |
| 1666 | // Evict |
| 1667 | |
| 1668 | reg [31:0] b3_ev_vect0; |
| 1669 | reg [23:0] b3_ev_vect1; |
| 1670 | reg [31:0] b3_ev_vect2; |
| 1671 | reg [23:0] b3_ev_vect3; |
| 1672 | reg [1:0] b3_pa54; |
| 1673 | reg [31:0] b3_inv_vect [0:3]; |
| 1674 | reg [39:0] b3_evict_pa; |
| 1675 | reg [31:0] b3_evict_inv_vect; |
| 1676 | |
| 1677 | wire b3_evict; |
| 1678 | wire [111:0] b3_ev_invvect; |
| 1679 | |
| 1680 | assign b3_evict = b3_req_c8 && |
| 1681 | (b3_cpx_valid==1'b1) && |
| 1682 | (b3_cpx_rtntyp==`CCX_RESP_EVICT); |
| 1683 | assign b3_ev_invvect = b3_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 1684 | |
| 1685 | `endif |
| 1686 | `endif |
| 1687 | |
| 1688 | `ifdef NO_L2_BNK4 |
| 1689 | `else |
| 1690 | `ifdef NOL2RTL |
| 1691 | `else |
| 1692 | |
| 1693 | //---------------------------------------------------------- |
| 1694 | // Signals for L2 RTL Bank4 |
| 1695 | |
| 1696 | wire [2:0] b4_cpx_cid_c8; |
| 1697 | reg [2:0] b4_cpx_cid_c9; |
| 1698 | wire [2:0] b4_cpx_cid; |
| 1699 | wire [145:0] b4_cpx_pkt_c8; |
| 1700 | wire [39:0] b4_pa_c8; |
| 1701 | reg [39:0] b4_pa_c9; |
| 1702 | wire [39:0] b4_cpx_pa; |
| 1703 | wire [39:0] b4_ev_pa_c4; |
| 1704 | reg [39:0] b4_ev_pa_c5; |
| 1705 | reg [39:0] b4_ev_pa_c52; |
| 1706 | reg [39:0] b4_ev_pa_c6; |
| 1707 | reg [39:0] b4_ev_pa_c7; |
| 1708 | reg [39:0] b4_ev_pa_c8; |
| 1709 | wire [39:0] b4_ev_pa; |
| 1710 | wire b4_req_c6; |
| 1711 | reg b4_req_c7; |
| 1712 | reg b4_req_c8; |
| 1713 | wire b4_cpx_valid; |
| 1714 | wire b4_cpx_pf; |
| 1715 | wire [3:0] b4_cpx_rtntyp; |
| 1716 | wire [2:0] b4_cpx_tid; |
| 1717 | wire [5:0] b4_cpx_tnum; |
| 1718 | wire [39:0] b4_stall_c1; |
| 1719 | reg [39:0] b4_stall_c2; |
| 1720 | reg [39:0] b4_stall_c3; |
| 1721 | reg [39:0] b4_stall_c4; |
| 1722 | reg [39:0] b4_stall_c5; |
| 1723 | reg [39:0] b4_stall_c52; |
| 1724 | reg [39:0] b4_stall_c6; |
| 1725 | reg [39:0] b4_stall_c7; |
| 1726 | reg [39:0] b4_stall_c8; |
| 1727 | reg [39:0] b4_stall_c9; |
| 1728 | |
| 1729 | assign b4_cpx_cid_c8 = `CPU.l2t4.oque.inst_cpuid_c8; |
| 1730 | // When pipeline stalls, pa must be stalled, too. |
| 1731 | assign b4_cpx_cid = (b4_stall_c9) ? b4_cpx_cid_c9 : b4_cpx_cid_c8; |
| 1732 | assign b4_cpx_pkt_c8 = `CPU.l2t4.oque.oque_oq_array_data_in; |
| 1733 | assign b4_pa_c8 = `CPU.l2t4.arbadr.arbdp_addr_c8; |
| 1734 | // When pipeline stalls, pa must be stalled, too. |
| 1735 | assign b4_cpx_pa = (b4_stall_c9) ? b4_pa_c9 : b4_pa_c8; |
| 1736 | assign b4_ev_pa_c4 = `CPU.l2t4.evctag.evctag_wb_write_addr; |
| 1737 | assign b4_ev_pa = b4_ev_pa_c8; |
| 1738 | assign b4_req_c6 = |(`CPU.l2t4.oqu.req_out_c6); |
| 1739 | assign b4_cpx_tnum = {b4_cpx_cid,b4_cpx_tid}; |
| 1740 | assign b4_cpx_tid = b4_cpx_pkt_c8[`CPX_TID]; |
| 1741 | assign b4_cpx_valid = b4_cpx_pkt_c8[`CPX_VALID]; |
| 1742 | assign b4_cpx_pf = b4_cpx_pkt_c8[`CPX_PF]; |
| 1743 | assign b4_cpx_rtntyp = b4_cpx_pkt_c8[`CPX_RTNTYP]; |
| 1744 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 1745 | assign b4_stall_c1 = `CPU.l2t4.arb.arb_inst_diag_c1; |
| 1746 | |
| 1747 | //--------------------- |
| 1748 | // Load Data |
| 1749 | |
| 1750 | wire b4_load_data_miss; |
| 1751 | wire b4_ldd_suppress; |
| 1752 | |
| 1753 | assign b4_load_data_miss = b4_req_c8 && |
| 1754 | (b4_cpx_valid==1'b1) && |
| 1755 | ((b4_cpx_rtntyp==`CCX_RESP_LD)|| |
| 1756 | (b4_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 1757 | (b4_cpx_pf==1'b0); |
| 1758 | assign b4_ldd_suppress = (b4_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1759 | |
| 1760 | //--------------------- |
| 1761 | // Store L2 Commit |
| 1762 | |
| 1763 | wire b4_store_commit; |
| 1764 | wire b4_stc_suppress; |
| 1765 | wire [7:0] b4_stc_size; |
| 1766 | wire [31:0] b4_stc_inv_vect; |
| 1767 | reg [31:0] b4_stc_vect; |
| 1768 | wire b4_stc_atomic; |
| 1769 | wire b4_l2_ctrue_c3; |
| 1770 | reg b4_l2_ctrue_c4; |
| 1771 | reg b4_l2_ctrue_c5; |
| 1772 | reg b4_l2_ctrue_c52; |
| 1773 | reg b4_l2_ctrue_c6; |
| 1774 | reg b4_l2_ctrue_c7; |
| 1775 | reg b4_l2_ctrue_c8; |
| 1776 | wire b4_stc_l2hit; |
| 1777 | wire b4_stc_l2hit_c3; |
| 1778 | reg b4_stc_l2hit_c4; |
| 1779 | reg b4_stc_l2hit_c5; |
| 1780 | reg b4_stc_l2hit_c52; |
| 1781 | reg b4_stc_l2hit_c6; |
| 1782 | reg b4_stc_l2hit_c7; |
| 1783 | reg b4_stc_l2hit_c8; |
| 1784 | wire b4_cam_pa_match_c1; |
| 1785 | wire b4_csr_l2_bypass_mode_on; |
| 1786 | reg b4_cam_pa_match_c2; |
| 1787 | reg b4_cam_pa_match_c3; |
| 1788 | |
| 1789 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1790 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1791 | assign b4_store_commit = b4_req_c8 && |
| 1792 | (b4_cpx_valid==1'b1) && |
| 1793 | (b4_cpx_rtntyp==`CCX_RESP_ST) & |
| 1794 | (b4_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 1795 | assign b4_stc_suppress = (b4_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1796 | assign b4_stc_inv_vect = b4_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 1797 | assign b4_stc_atomic = b4_cpx_pkt_c8[`CPX_ATOMIC]; |
| 1798 | |
| 1799 | assign b4_stc_size = (b4_stc_atomic & !b4_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 1800 | 8'b0 : b4_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 1801 | assign b4_l2_ctrue_c3 = `CPU.l2t4.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 1802 | assign b4_csr_l2_bypass_mode_on = `CPU.l2t4.csr_l2_bypass_mode_on; // l2 off mode |
| 1803 | assign b4_cam_pa_match_c1 = (|(`CPU.l2t4.misbuf.mb_cam_match | {32{`CPU.l2t4.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 1804 | | {32{`CPU.l2t4.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 1805 | assign b4_stc_l2hit_c3 = {32{`CPU.l2t4.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 1806 | ((`CPU.l2t4.tagctl.tag_hit_l2orfb_c3 & !(b4_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 1807 | (`CPU.l2t4.misbuf.misbuf_hit_c3 & b4_cam_pa_match_c3 & !(b4_csr_l2_bypass_mode_on))) |
| 1808 | : |
| 1809 | ((`CPU.l2t4.tagctl.tag_hit_l2orfb_c3 & !(b4_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 1810 | (`CPU.l2t4.misbuf.misbuf_hit_c3 & !(b4_csr_l2_bypass_mode_on))) |
| 1811 | ; |
| 1812 | assign b4_stc_l2hit = b4_stc_l2hit_c8; |
| 1813 | |
| 1814 | //--------------------- |
| 1815 | // Evict |
| 1816 | |
| 1817 | reg [31:0] b4_ev_vect0; |
| 1818 | reg [23:0] b4_ev_vect1; |
| 1819 | reg [31:0] b4_ev_vect2; |
| 1820 | reg [23:0] b4_ev_vect3; |
| 1821 | reg [1:0] b4_pa54; |
| 1822 | reg [31:0] b4_inv_vect [0:3]; |
| 1823 | reg [39:0] b4_evict_pa; |
| 1824 | reg [31:0] b4_evict_inv_vect; |
| 1825 | |
| 1826 | wire b4_evict; |
| 1827 | wire [111:0] b4_ev_invvect; |
| 1828 | |
| 1829 | assign b4_evict = b4_req_c8 && |
| 1830 | (b4_cpx_valid==1'b1) && |
| 1831 | (b4_cpx_rtntyp==`CCX_RESP_EVICT); |
| 1832 | assign b4_ev_invvect = b4_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 1833 | |
| 1834 | `endif |
| 1835 | `endif |
| 1836 | |
| 1837 | `ifdef NO_L2_BNK5 |
| 1838 | `else |
| 1839 | `ifdef NOL2RTL |
| 1840 | `else |
| 1841 | |
| 1842 | //---------------------------------------------------------- |
| 1843 | // Signals for L2 RTL Bank5 |
| 1844 | |
| 1845 | wire [2:0] b5_cpx_cid_c8; |
| 1846 | reg [2:0] b5_cpx_cid_c9; |
| 1847 | wire [2:0] b5_cpx_cid; |
| 1848 | wire [145:0] b5_cpx_pkt_c8; |
| 1849 | wire [39:0] b5_pa_c8; |
| 1850 | reg [39:0] b5_pa_c9; |
| 1851 | wire [39:0] b5_cpx_pa; |
| 1852 | wire [39:0] b5_ev_pa_c4; |
| 1853 | reg [39:0] b5_ev_pa_c5; |
| 1854 | reg [39:0] b5_ev_pa_c52; |
| 1855 | reg [39:0] b5_ev_pa_c6; |
| 1856 | reg [39:0] b5_ev_pa_c7; |
| 1857 | reg [39:0] b5_ev_pa_c8; |
| 1858 | wire [39:0] b5_ev_pa; |
| 1859 | wire b5_req_c6; |
| 1860 | reg b5_req_c7; |
| 1861 | reg b5_req_c8; |
| 1862 | wire b5_cpx_valid; |
| 1863 | wire b5_cpx_pf; |
| 1864 | wire [3:0] b5_cpx_rtntyp; |
| 1865 | wire [2:0] b5_cpx_tid; |
| 1866 | wire [5:0] b5_cpx_tnum; |
| 1867 | wire [39:0] b5_stall_c1; |
| 1868 | reg [39:0] b5_stall_c2; |
| 1869 | reg [39:0] b5_stall_c3; |
| 1870 | reg [39:0] b5_stall_c4; |
| 1871 | reg [39:0] b5_stall_c5; |
| 1872 | reg [39:0] b5_stall_c52; |
| 1873 | reg [39:0] b5_stall_c6; |
| 1874 | reg [39:0] b5_stall_c7; |
| 1875 | reg [39:0] b5_stall_c8; |
| 1876 | reg [39:0] b5_stall_c9; |
| 1877 | |
| 1878 | assign b5_cpx_cid_c8 = `CPU.l2t5.oque.inst_cpuid_c8; |
| 1879 | // When pipeline stalls, pa must be stalled, too. |
| 1880 | assign b5_cpx_cid = (b5_stall_c9) ? b5_cpx_cid_c9 : b5_cpx_cid_c8; |
| 1881 | assign b5_cpx_pkt_c8 = `CPU.l2t5.oque.oque_oq_array_data_in; |
| 1882 | assign b5_pa_c8 = `CPU.l2t5.arbadr.arbdp_addr_c8; |
| 1883 | // When pipeline stalls, pa must be stalled, too. |
| 1884 | assign b5_cpx_pa = (b5_stall_c9) ? b5_pa_c9 : b5_pa_c8; |
| 1885 | assign b5_ev_pa_c4 = `CPU.l2t5.evctag.evctag_wb_write_addr; |
| 1886 | assign b5_ev_pa = b5_ev_pa_c8; |
| 1887 | assign b5_req_c6 = |(`CPU.l2t5.oqu.req_out_c6); |
| 1888 | assign b5_cpx_tnum = {b5_cpx_cid,b5_cpx_tid}; |
| 1889 | assign b5_cpx_tid = b5_cpx_pkt_c8[`CPX_TID]; |
| 1890 | assign b5_cpx_valid = b5_cpx_pkt_c8[`CPX_VALID]; |
| 1891 | assign b5_cpx_pf = b5_cpx_pkt_c8[`CPX_PF]; |
| 1892 | assign b5_cpx_rtntyp = b5_cpx_pkt_c8[`CPX_RTNTYP]; |
| 1893 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 1894 | assign b5_stall_c1 = `CPU.l2t5.arb.arb_inst_diag_c1; |
| 1895 | |
| 1896 | //--------------------- |
| 1897 | // Load Data |
| 1898 | |
| 1899 | wire b5_load_data_miss; |
| 1900 | wire b5_ldd_suppress; |
| 1901 | |
| 1902 | assign b5_load_data_miss = b5_req_c8 && |
| 1903 | (b5_cpx_valid==1'b1) && |
| 1904 | ((b5_cpx_rtntyp==`CCX_RESP_LD)|| |
| 1905 | (b5_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 1906 | (b5_cpx_pf==1'b0); |
| 1907 | assign b5_ldd_suppress = (b5_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1908 | |
| 1909 | //--------------------- |
| 1910 | // Store L2 Commit |
| 1911 | |
| 1912 | wire b5_store_commit; |
| 1913 | wire b5_stc_suppress; |
| 1914 | wire [7:0] b5_stc_size; |
| 1915 | wire [31:0] b5_stc_inv_vect; |
| 1916 | reg [31:0] b5_stc_vect; |
| 1917 | wire b5_stc_atomic; |
| 1918 | wire b5_l2_ctrue_c3; |
| 1919 | reg b5_l2_ctrue_c4; |
| 1920 | reg b5_l2_ctrue_c5; |
| 1921 | reg b5_l2_ctrue_c52; |
| 1922 | reg b5_l2_ctrue_c6; |
| 1923 | reg b5_l2_ctrue_c7; |
| 1924 | reg b5_l2_ctrue_c8; |
| 1925 | wire b5_stc_l2hit; |
| 1926 | wire b5_stc_l2hit_c3; |
| 1927 | reg b5_stc_l2hit_c4; |
| 1928 | reg b5_stc_l2hit_c5; |
| 1929 | reg b5_stc_l2hit_c52; |
| 1930 | reg b5_stc_l2hit_c6; |
| 1931 | reg b5_stc_l2hit_c7; |
| 1932 | reg b5_stc_l2hit_c8; |
| 1933 | wire b5_cam_pa_match_c1; |
| 1934 | wire b5_csr_l2_bypass_mode_on; |
| 1935 | reg b5_cam_pa_match_c2; |
| 1936 | reg b5_cam_pa_match_c3; |
| 1937 | |
| 1938 | // rtntyp covers ST, CAS, SWAP since same decode |
| 1939 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 1940 | assign b5_store_commit = b5_req_c8 && |
| 1941 | (b5_cpx_valid==1'b1) && |
| 1942 | (b5_cpx_rtntyp==`CCX_RESP_ST) & |
| 1943 | (b5_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 1944 | assign b5_stc_suppress = (b5_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 1945 | assign b5_stc_inv_vect = b5_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 1946 | assign b5_stc_atomic = b5_cpx_pkt_c8[`CPX_ATOMIC]; |
| 1947 | |
| 1948 | assign b5_stc_size = (b5_stc_atomic & !b5_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 1949 | 8'b0 : b5_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 1950 | assign b5_l2_ctrue_c3 = `CPU.l2t5.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 1951 | assign b5_csr_l2_bypass_mode_on = `CPU.l2t5.csr_l2_bypass_mode_on; // l2 off mode |
| 1952 | assign b5_cam_pa_match_c1 = (|(`CPU.l2t5.misbuf.mb_cam_match | {32{`CPU.l2t5.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 1953 | | {32{`CPU.l2t5.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 1954 | assign b5_stc_l2hit_c3 = {32{`CPU.l2t5.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 1955 | ((`CPU.l2t5.tagctl.tag_hit_l2orfb_c3 & !(b5_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 1956 | (`CPU.l2t5.misbuf.misbuf_hit_c3 & b5_cam_pa_match_c3 & !(b5_csr_l2_bypass_mode_on))) |
| 1957 | : |
| 1958 | ((`CPU.l2t5.tagctl.tag_hit_l2orfb_c3 & !(b5_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 1959 | (`CPU.l2t5.misbuf.misbuf_hit_c3 & !(b5_csr_l2_bypass_mode_on))) |
| 1960 | ; |
| 1961 | assign b5_stc_l2hit = b5_stc_l2hit_c8; |
| 1962 | |
| 1963 | //--------------------- |
| 1964 | // Evict |
| 1965 | |
| 1966 | reg [31:0] b5_ev_vect0; |
| 1967 | reg [23:0] b5_ev_vect1; |
| 1968 | reg [31:0] b5_ev_vect2; |
| 1969 | reg [23:0] b5_ev_vect3; |
| 1970 | reg [1:0] b5_pa54; |
| 1971 | reg [31:0] b5_inv_vect [0:3]; |
| 1972 | reg [39:0] b5_evict_pa; |
| 1973 | reg [31:0] b5_evict_inv_vect; |
| 1974 | |
| 1975 | wire b5_evict; |
| 1976 | wire [111:0] b5_ev_invvect; |
| 1977 | |
| 1978 | assign b5_evict = b5_req_c8 && |
| 1979 | (b5_cpx_valid==1'b1) && |
| 1980 | (b5_cpx_rtntyp==`CCX_RESP_EVICT); |
| 1981 | assign b5_ev_invvect = b5_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 1982 | |
| 1983 | `endif |
| 1984 | `endif |
| 1985 | |
| 1986 | `ifdef NO_L2_BNK6 |
| 1987 | `else |
| 1988 | `ifdef NOL2RTL |
| 1989 | `else |
| 1990 | |
| 1991 | //---------------------------------------------------------- |
| 1992 | // Signals for L2 RTL Bank6 |
| 1993 | |
| 1994 | wire [2:0] b6_cpx_cid_c8; |
| 1995 | reg [2:0] b6_cpx_cid_c9; |
| 1996 | wire [2:0] b6_cpx_cid; |
| 1997 | wire [145:0] b6_cpx_pkt_c8; |
| 1998 | wire [39:0] b6_pa_c8; |
| 1999 | reg [39:0] b6_pa_c9; |
| 2000 | wire [39:0] b6_cpx_pa; |
| 2001 | wire [39:0] b6_ev_pa_c4; |
| 2002 | reg [39:0] b6_ev_pa_c5; |
| 2003 | reg [39:0] b6_ev_pa_c52; |
| 2004 | reg [39:0] b6_ev_pa_c6; |
| 2005 | reg [39:0] b6_ev_pa_c7; |
| 2006 | reg [39:0] b6_ev_pa_c8; |
| 2007 | wire [39:0] b6_ev_pa; |
| 2008 | wire b6_req_c6; |
| 2009 | reg b6_req_c7; |
| 2010 | reg b6_req_c8; |
| 2011 | wire b6_cpx_valid; |
| 2012 | wire b6_cpx_pf; |
| 2013 | wire [3:0] b6_cpx_rtntyp; |
| 2014 | wire [2:0] b6_cpx_tid; |
| 2015 | wire [5:0] b6_cpx_tnum; |
| 2016 | wire [39:0] b6_stall_c1; |
| 2017 | reg [39:0] b6_stall_c2; |
| 2018 | reg [39:0] b6_stall_c3; |
| 2019 | reg [39:0] b6_stall_c4; |
| 2020 | reg [39:0] b6_stall_c5; |
| 2021 | reg [39:0] b6_stall_c52; |
| 2022 | reg [39:0] b6_stall_c6; |
| 2023 | reg [39:0] b6_stall_c7; |
| 2024 | reg [39:0] b6_stall_c8; |
| 2025 | reg [39:0] b6_stall_c9; |
| 2026 | |
| 2027 | assign b6_cpx_cid_c8 = `CPU.l2t6.oque.inst_cpuid_c8; |
| 2028 | // When pipeline stalls, pa must be stalled, too. |
| 2029 | assign b6_cpx_cid = (b6_stall_c9) ? b6_cpx_cid_c9 : b6_cpx_cid_c8; |
| 2030 | assign b6_cpx_pkt_c8 = `CPU.l2t6.oque.oque_oq_array_data_in; |
| 2031 | assign b6_pa_c8 = `CPU.l2t6.arbadr.arbdp_addr_c8; |
| 2032 | // When pipeline stalls, pa must be stalled, too. |
| 2033 | assign b6_cpx_pa = (b6_stall_c9) ? b6_pa_c9 : b6_pa_c8; |
| 2034 | assign b6_ev_pa_c4 = `CPU.l2t6.evctag.evctag_wb_write_addr; |
| 2035 | assign b6_ev_pa = b6_ev_pa_c8; |
| 2036 | assign b6_req_c6 = |(`CPU.l2t6.oqu.req_out_c6); |
| 2037 | assign b6_cpx_tnum = {b6_cpx_cid,b6_cpx_tid}; |
| 2038 | assign b6_cpx_tid = b6_cpx_pkt_c8[`CPX_TID]; |
| 2039 | assign b6_cpx_valid = b6_cpx_pkt_c8[`CPX_VALID]; |
| 2040 | assign b6_cpx_pf = b6_cpx_pkt_c8[`CPX_PF]; |
| 2041 | assign b6_cpx_rtntyp = b6_cpx_pkt_c8[`CPX_RTNTYP]; |
| 2042 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 2043 | assign b6_stall_c1 = `CPU.l2t6.arb.arb_inst_diag_c1; |
| 2044 | |
| 2045 | //--------------------- |
| 2046 | // Load Data |
| 2047 | |
| 2048 | wire b6_load_data_miss; |
| 2049 | wire b6_ldd_suppress; |
| 2050 | |
| 2051 | assign b6_load_data_miss = b6_req_c8 && |
| 2052 | (b6_cpx_valid==1'b1) && |
| 2053 | ((b6_cpx_rtntyp==`CCX_RESP_LD)|| |
| 2054 | (b6_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 2055 | (b6_cpx_pf==1'b0); |
| 2056 | assign b6_ldd_suppress = (b6_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 2057 | |
| 2058 | //--------------------- |
| 2059 | // Store L2 Commit |
| 2060 | |
| 2061 | wire b6_store_commit; |
| 2062 | wire b6_stc_suppress; |
| 2063 | wire [7:0] b6_stc_size; |
| 2064 | wire [31:0] b6_stc_inv_vect; |
| 2065 | reg [31:0] b6_stc_vect; |
| 2066 | wire b6_stc_atomic; |
| 2067 | wire b6_l2_ctrue_c3; |
| 2068 | reg b6_l2_ctrue_c4; |
| 2069 | reg b6_l2_ctrue_c5; |
| 2070 | reg b6_l2_ctrue_c52; |
| 2071 | reg b6_l2_ctrue_c6; |
| 2072 | reg b6_l2_ctrue_c7; |
| 2073 | reg b6_l2_ctrue_c8; |
| 2074 | wire b6_stc_l2hit; |
| 2075 | wire b6_stc_l2hit_c3; |
| 2076 | reg b6_stc_l2hit_c4; |
| 2077 | reg b6_stc_l2hit_c5; |
| 2078 | reg b6_stc_l2hit_c52; |
| 2079 | reg b6_stc_l2hit_c6; |
| 2080 | reg b6_stc_l2hit_c7; |
| 2081 | reg b6_stc_l2hit_c8; |
| 2082 | wire b6_cam_pa_match_c1; |
| 2083 | wire b6_csr_l2_bypass_mode_on; |
| 2084 | reg b6_cam_pa_match_c2; |
| 2085 | reg b6_cam_pa_match_c3; |
| 2086 | |
| 2087 | // rtntyp covers ST, CAS, SWAP since same decode |
| 2088 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 2089 | assign b6_store_commit = b6_req_c8 && |
| 2090 | (b6_cpx_valid==1'b1) && |
| 2091 | (b6_cpx_rtntyp==`CCX_RESP_ST) & |
| 2092 | (b6_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 2093 | assign b6_stc_suppress = (b6_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 2094 | assign b6_stc_inv_vect = b6_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 2095 | assign b6_stc_atomic = b6_cpx_pkt_c8[`CPX_ATOMIC]; |
| 2096 | |
| 2097 | assign b6_stc_size = (b6_stc_atomic & !b6_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 2098 | 8'b0 : b6_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 2099 | assign b6_l2_ctrue_c3 = `CPU.l2t6.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 2100 | assign b6_csr_l2_bypass_mode_on = `CPU.l2t6.csr_l2_bypass_mode_on; // l2 off mode |
| 2101 | assign b6_cam_pa_match_c1 = (|(`CPU.l2t6.misbuf.mb_cam_match | {32{`CPU.l2t6.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 2102 | | {32{`CPU.l2t6.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 2103 | assign b6_stc_l2hit_c3 = {32{`CPU.l2t6.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 2104 | ((`CPU.l2t6.tagctl.tag_hit_l2orfb_c3 & !(b6_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 2105 | (`CPU.l2t6.misbuf.misbuf_hit_c3 & b6_cam_pa_match_c3 & !(b6_csr_l2_bypass_mode_on))) |
| 2106 | : |
| 2107 | ((`CPU.l2t6.tagctl.tag_hit_l2orfb_c3 & !(b6_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 2108 | (`CPU.l2t6.misbuf.misbuf_hit_c3 & !(b6_csr_l2_bypass_mode_on))) |
| 2109 | ; |
| 2110 | assign b6_stc_l2hit = b6_stc_l2hit_c8; |
| 2111 | |
| 2112 | //--------------------- |
| 2113 | // Evict |
| 2114 | |
| 2115 | reg [31:0] b6_ev_vect0; |
| 2116 | reg [23:0] b6_ev_vect1; |
| 2117 | reg [31:0] b6_ev_vect2; |
| 2118 | reg [23:0] b6_ev_vect3; |
| 2119 | reg [1:0] b6_pa54; |
| 2120 | reg [31:0] b6_inv_vect [0:3]; |
| 2121 | reg [39:0] b6_evict_pa; |
| 2122 | reg [31:0] b6_evict_inv_vect; |
| 2123 | |
| 2124 | wire b6_evict; |
| 2125 | wire [111:0] b6_ev_invvect; |
| 2126 | |
| 2127 | assign b6_evict = b6_req_c8 && |
| 2128 | (b6_cpx_valid==1'b1) && |
| 2129 | (b6_cpx_rtntyp==`CCX_RESP_EVICT); |
| 2130 | assign b6_ev_invvect = b6_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 2131 | |
| 2132 | `endif |
| 2133 | `endif |
| 2134 | |
| 2135 | `ifdef NO_L2_BNK7 |
| 2136 | `else |
| 2137 | `ifdef NOL2RTL |
| 2138 | `else |
| 2139 | |
| 2140 | //---------------------------------------------------------- |
| 2141 | // Signals for L2 RTL Bank7 |
| 2142 | |
| 2143 | wire [2:0] b7_cpx_cid_c8; |
| 2144 | reg [2:0] b7_cpx_cid_c9; |
| 2145 | wire [2:0] b7_cpx_cid; |
| 2146 | wire [145:0] b7_cpx_pkt_c8; |
| 2147 | wire [39:0] b7_pa_c8; |
| 2148 | reg [39:0] b7_pa_c9; |
| 2149 | wire [39:0] b7_cpx_pa; |
| 2150 | wire [39:0] b7_ev_pa_c4; |
| 2151 | reg [39:0] b7_ev_pa_c5; |
| 2152 | reg [39:0] b7_ev_pa_c52; |
| 2153 | reg [39:0] b7_ev_pa_c6; |
| 2154 | reg [39:0] b7_ev_pa_c7; |
| 2155 | reg [39:0] b7_ev_pa_c8; |
| 2156 | wire [39:0] b7_ev_pa; |
| 2157 | wire b7_req_c6; |
| 2158 | reg b7_req_c7; |
| 2159 | reg b7_req_c8; |
| 2160 | wire b7_cpx_valid; |
| 2161 | wire b7_cpx_pf; |
| 2162 | wire [3:0] b7_cpx_rtntyp; |
| 2163 | wire [2:0] b7_cpx_tid; |
| 2164 | wire [5:0] b7_cpx_tnum; |
| 2165 | wire [39:0] b7_stall_c1; |
| 2166 | reg [39:0] b7_stall_c2; |
| 2167 | reg [39:0] b7_stall_c3; |
| 2168 | reg [39:0] b7_stall_c4; |
| 2169 | reg [39:0] b7_stall_c5; |
| 2170 | reg [39:0] b7_stall_c52; |
| 2171 | reg [39:0] b7_stall_c6; |
| 2172 | reg [39:0] b7_stall_c7; |
| 2173 | reg [39:0] b7_stall_c8; |
| 2174 | reg [39:0] b7_stall_c9; |
| 2175 | |
| 2176 | assign b7_cpx_cid_c8 = `CPU.l2t7.oque.inst_cpuid_c8; |
| 2177 | // When pipeline stalls, pa must be stalled, too. |
| 2178 | assign b7_cpx_cid = (b7_stall_c9) ? b7_cpx_cid_c9 : b7_cpx_cid_c8; |
| 2179 | assign b7_cpx_pkt_c8 = `CPU.l2t7.oque.oque_oq_array_data_in; |
| 2180 | assign b7_pa_c8 = `CPU.l2t7.arbadr.arbdp_addr_c8; |
| 2181 | // When pipeline stalls, pa must be stalled, too. |
| 2182 | assign b7_cpx_pa = (b7_stall_c9) ? b7_pa_c9 : b7_pa_c8; |
| 2183 | assign b7_ev_pa_c4 = `CPU.l2t7.evctag.evctag_wb_write_addr; |
| 2184 | assign b7_ev_pa = b7_ev_pa_c8; |
| 2185 | assign b7_req_c6 = |(`CPU.l2t7.oqu.req_out_c6); |
| 2186 | assign b7_cpx_tnum = {b7_cpx_cid,b7_cpx_tid}; |
| 2187 | assign b7_cpx_tid = b7_cpx_pkt_c8[`CPX_TID]; |
| 2188 | assign b7_cpx_valid = b7_cpx_pkt_c8[`CPX_VALID]; |
| 2189 | assign b7_cpx_pf = b7_cpx_pkt_c8[`CPX_PF]; |
| 2190 | assign b7_cpx_rtntyp = b7_cpx_pkt_c8[`CPX_RTNTYP]; |
| 2191 | // arb_inst_diag_c1 is asserted for LD/ST to L2 CSR registers which causes pipeline stall |
| 2192 | assign b7_stall_c1 = `CPU.l2t7.arb.arb_inst_diag_c1; |
| 2193 | |
| 2194 | //--------------------- |
| 2195 | // Load Data |
| 2196 | |
| 2197 | wire b7_load_data_miss; |
| 2198 | wire b7_ldd_suppress; |
| 2199 | |
| 2200 | assign b7_load_data_miss = b7_req_c8 && |
| 2201 | (b7_cpx_valid==1'b1) && |
| 2202 | ((b7_cpx_rtntyp==`CCX_RESP_LD)|| |
| 2203 | (b7_cpx_rtntyp==`CCX_RESP_NCU_LD)) && |
| 2204 | (b7_cpx_pf==1'b0); |
| 2205 | assign b7_ldd_suppress = (b7_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 2206 | |
| 2207 | //--------------------- |
| 2208 | // Store L2 Commit |
| 2209 | |
| 2210 | wire b7_store_commit; |
| 2211 | wire b7_stc_suppress; |
| 2212 | wire [7:0] b7_stc_size; |
| 2213 | wire [31:0] b7_stc_inv_vect; |
| 2214 | reg [31:0] b7_stc_vect; |
| 2215 | wire b7_stc_atomic; |
| 2216 | wire b7_l2_ctrue_c3; |
| 2217 | reg b7_l2_ctrue_c4; |
| 2218 | reg b7_l2_ctrue_c5; |
| 2219 | reg b7_l2_ctrue_c52; |
| 2220 | reg b7_l2_ctrue_c6; |
| 2221 | reg b7_l2_ctrue_c7; |
| 2222 | reg b7_l2_ctrue_c8; |
| 2223 | wire b7_stc_l2hit; |
| 2224 | wire b7_stc_l2hit_c3; |
| 2225 | reg b7_stc_l2hit_c4; |
| 2226 | reg b7_stc_l2hit_c5; |
| 2227 | reg b7_stc_l2hit_c52; |
| 2228 | reg b7_stc_l2hit_c6; |
| 2229 | reg b7_stc_l2hit_c7; |
| 2230 | reg b7_stc_l2hit_c8; |
| 2231 | wire b7_cam_pa_match_c1; |
| 2232 | wire b7_csr_l2_bypass_mode_on; |
| 2233 | reg b7_cam_pa_match_c2; |
| 2234 | reg b7_cam_pa_match_c3; |
| 2235 | |
| 2236 | // rtntyp covers ST, CAS, SWAP since same decode |
| 2237 | // but not Dcache Inval Ack (same rtntyp as ST Ack) |
| 2238 | assign b7_store_commit = b7_req_c8 && |
| 2239 | (b7_cpx_valid==1'b1) && |
| 2240 | (b7_cpx_rtntyp==`CCX_RESP_ST) & |
| 2241 | (b7_cpx_pkt_c8[`CPX_VACK_INVAL]==2'b0); |
| 2242 | assign b7_stc_suppress = (b7_cpx_pa[39:32]==`IO_ASI_ADDR); |
| 2243 | assign b7_stc_inv_vect = b7_cpx_pkt_c8[`CPX_VACK_VECT]; |
| 2244 | assign b7_stc_atomic = b7_cpx_pkt_c8[`CPX_ATOMIC]; |
| 2245 | |
| 2246 | assign b7_stc_size = (b7_stc_atomic & !b7_l2_ctrue_c8) ? // ctrue = compare true for CAS |
| 2247 | 8'b0 : b7_cpx_pkt_c8[`CPX_VACK_BMASK]; |
| 2248 | assign b7_l2_ctrue_c3 = `CPU.l2t7.arbdec.arbdp_inst_c3[37]; // `L2_CTRUE = 37 |
| 2249 | assign b7_csr_l2_bypass_mode_on = `CPU.l2t7.csr_l2_bypass_mode_on; // l2 off mode |
| 2250 | assign b7_cam_pa_match_c1 = (|(`CPU.l2t7.misbuf.mb_cam_match | {32{`CPU.l2t7.misbuf.arbadr_arbdp_addr_c1c3comp_c1}} |
| 2251 | | {32{`CPU.l2t7.misbuf.arbadr_arbdp_addr_c1c2comp_c1}})); |
| 2252 | assign b7_stc_l2hit_c3 = {32{`CPU.l2t7.misbuf.l2_dir_map_on_d1}} ? // if l2 directmap on |
| 2253 | ((`CPU.l2t7.tagctl.tag_hit_l2orfb_c3 & !(b7_csr_l2_bypass_mode_on)) || // select the equaltion with cam_pa_match_c3 |
| 2254 | (`CPU.l2t7.misbuf.misbuf_hit_c3 & b7_cam_pa_match_c3 & !(b7_csr_l2_bypass_mode_on))) |
| 2255 | : |
| 2256 | ((`CPU.l2t7.tagctl.tag_hit_l2orfb_c3 & !(b7_csr_l2_bypass_mode_on))|| // else select the equaltion witout cam_pa_match_c3 |
| 2257 | (`CPU.l2t7.misbuf.misbuf_hit_c3 & !(b7_csr_l2_bypass_mode_on))) |
| 2258 | ; |
| 2259 | assign b7_stc_l2hit = b7_stc_l2hit_c8; |
| 2260 | |
| 2261 | //--------------------- |
| 2262 | // Evict |
| 2263 | |
| 2264 | reg [31:0] b7_ev_vect0; |
| 2265 | reg [23:0] b7_ev_vect1; |
| 2266 | reg [31:0] b7_ev_vect2; |
| 2267 | reg [23:0] b7_ev_vect3; |
| 2268 | reg [1:0] b7_pa54; |
| 2269 | reg [31:0] b7_inv_vect [0:3]; |
| 2270 | reg [39:0] b7_evict_pa; |
| 2271 | reg [31:0] b7_evict_inv_vect; |
| 2272 | |
| 2273 | wire b7_evict; |
| 2274 | wire [111:0] b7_ev_invvect; |
| 2275 | |
| 2276 | assign b7_evict = b7_req_c8 && |
| 2277 | (b7_cpx_valid==1'b1) && |
| 2278 | (b7_cpx_rtntyp==`CCX_RESP_EVICT); |
| 2279 | assign b7_ev_invvect = b7_cpx_pkt_c8[`CPX_VINV_VECT]; |
| 2280 | |
| 2281 | `endif |
| 2282 | `endif |
| 2283 | |
| 2284 | |
| 2285 | // Must include ldst_dma.v before send of socket messages |
| 2286 | // but after wire declarations |
| 2287 | // because ldst_dma reuses some wires declared above and |
| 2288 | // because DMA_STORE socket msg must come before related EVICT |
| 2289 | `include "ldst_dma.v" |
| 2290 | |
| 2291 | //========================================================== |
| 2292 | //========================================================== |
| 2293 | |
| 2294 | |
| 2295 | //========================================================== |
| 2296 | // Bank0 |
| 2297 | |
| 2298 | always @ (posedge `BENCH_L2T0_GCLK) begin // { |
| 2299 | |
| 2300 | tstamp = `TOP.core_cycle_cnt - 1; |
| 2301 | |
| 2302 | //------------------------------ |
| 2303 | // Pipeline signals |
| 2304 | |
| 2305 | `ifdef NO_L2_BNK0 |
| 2306 | `else |
| 2307 | `ifdef NOL2RTL |
| 2308 | `else |
| 2309 | |
| 2310 | //------------------------------ |
| 2311 | // L2 RTL Bank0 |
| 2312 | |
| 2313 | b0_pa_c9 <= b0_pa_c8; |
| 2314 | b0_cpx_cid_c9 <= b0_cpx_cid_c8; |
| 2315 | b0_req_c7 <= b0_req_c6; |
| 2316 | b0_req_c8 <= b0_req_c7; |
| 2317 | |
| 2318 | b0_cam_pa_match_c2 <= b0_cam_pa_match_c1; |
| 2319 | b0_cam_pa_match_c3 <= b0_cam_pa_match_c2; |
| 2320 | |
| 2321 | b0_stall_c2 <= b0_stall_c1; |
| 2322 | b0_stall_c3 <= b0_stall_c2; |
| 2323 | b0_stall_c4 <= b0_stall_c3; |
| 2324 | b0_stall_c5 <= b0_stall_c4; |
| 2325 | b0_stall_c52 <= b0_stall_c5; |
| 2326 | b0_stall_c6 <= b0_stall_c52; |
| 2327 | b0_stall_c7 <= b0_stall_c6; |
| 2328 | b0_stall_c8 <= b0_stall_c7; |
| 2329 | b0_stall_c9 <= b0_stall_c8; |
| 2330 | |
| 2331 | b0_ev_pa_c5 <= b0_ev_pa_c4; |
| 2332 | b0_ev_pa_c52 <= b0_ev_pa_c5; |
| 2333 | b0_ev_pa_c6 <= b0_ev_pa_c52; |
| 2334 | b0_ev_pa_c7 <= b0_ev_pa_c6; |
| 2335 | b0_ev_pa_c8 <= b0_ev_pa_c7; |
| 2336 | |
| 2337 | b0_stc_l2hit_c4 <= b0_stc_l2hit_c3; |
| 2338 | b0_stc_l2hit_c5 <= b0_stc_l2hit_c4; |
| 2339 | b0_stc_l2hit_c52 <= b0_stc_l2hit_c5; |
| 2340 | b0_stc_l2hit_c6 <= b0_stc_l2hit_c52; |
| 2341 | b0_stc_l2hit_c7 <= b0_stc_l2hit_c6; |
| 2342 | b0_stc_l2hit_c8 <= b0_stc_l2hit_c7; |
| 2343 | |
| 2344 | b0_l2_ctrue_c4 <= b0_l2_ctrue_c3; |
| 2345 | b0_l2_ctrue_c5 <= b0_l2_ctrue_c4; |
| 2346 | b0_l2_ctrue_c52 <= b0_l2_ctrue_c5; |
| 2347 | b0_l2_ctrue_c6 <= b0_l2_ctrue_c52; |
| 2348 | b0_l2_ctrue_c7 <= b0_l2_ctrue_c6; |
| 2349 | b0_l2_ctrue_c8 <= b0_l2_ctrue_c7; |
| 2350 | |
| 2351 | `endif |
| 2352 | `endif |
| 2353 | |
| 2354 | //---------------------------------------------------------- |
| 2355 | //---------------------------------------------------------- |
| 2356 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 2357 | |
| 2358 | `ifdef NO_L2_BNK0 |
| 2359 | `else |
| 2360 | |
| 2361 | //------------------------------ |
| 2362 | // L2 Stub or L2 RTL Bank0 |
| 2363 | |
| 2364 | if (b0_load_data_miss && !b0_ldd_suppress) begin // { |
| 2365 | |
| 2366 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b0_cpx_tnum]) begin // { |
| 2367 | if (`PARGS.hash_on && (b0_cpx_pa[39]==1'b0)) begin // { |
| 2368 | `PR_INFO ("pli_ldst", `INFO, |
| 2369 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2370 | b0_cpx_cid,b0_cpx_tid,b0_cpx_tnum,`TOP.hashpa(b0_cpx_pa),dsrc,tstamp); |
| 2371 | junk = $sim_send(`PLI_MEM_LD_DATA,b0_cpx_tnum,`TOP.hashpa(b0_cpx_pa),dsrc,tstamp); |
| 2372 | end // } |
| 2373 | else begin //{ |
| 2374 | `PR_INFO ("pli_ldst", `INFO, |
| 2375 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2376 | b0_cpx_cid,b0_cpx_tid,b0_cpx_tnum,b0_cpx_pa,dsrc,tstamp); |
| 2377 | junk = $sim_send(`PLI_MEM_LD_DATA,b0_cpx_tnum,b0_cpx_pa,dsrc,tstamp); |
| 2378 | end // } |
| 2379 | end // } |
| 2380 | end // } |
| 2381 | else if (b0_load_data_miss && b0_ldd_suppress) begin // { |
| 2382 | `PR_INFO ("pli_ldst", `INFO, |
| 2383 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b0_cpx_cid,b0_cpx_tid,b0_cpx_tnum,b0_cpx_pa); |
| 2384 | |
| 2385 | end // } |
| 2386 | |
| 2387 | //---------------------------------------------------------- |
| 2388 | //---------------------------------------------------------- |
| 2389 | // Store L2 Commit |
| 2390 | |
| 2391 | //------------------------------ |
| 2392 | // L2 Stub or L2 RTL Bank0 |
| 2393 | |
| 2394 | if (b0_store_commit && !b0_stc_suppress) begin // { |
| 2395 | |
| 2396 | b0_stc_vect = get_vect (b0_stc_inv_vect); |
| 2397 | |
| 2398 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b0_cpx_tnum]) begin // { |
| 2399 | if (`PARGS.hash_on && (b0_cpx_pa[39]==1'b0)) begin // { |
| 2400 | `PR_INFO ("pli_ldst", `INFO, |
| 2401 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2402 | b0_cpx_cid,b0_cpx_tid,b0_cpx_tnum,`TOP.hashpa(b0_cpx_pa), |
| 2403 | b0_stc_size,b0_stc_vect,b0_stc_l2hit,tstamp); |
| 2404 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b0_cpx_tnum,`TOP.hashpa(b0_cpx_pa), |
| 2405 | b0_stc_size,b0_stc_vect,b0_stc_l2hit,tstamp); |
| 2406 | end // } |
| 2407 | else begin //{ |
| 2408 | `PR_INFO ("pli_ldst", `INFO, |
| 2409 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2410 | b0_cpx_cid,b0_cpx_tid,b0_cpx_tnum,b0_cpx_pa, |
| 2411 | b0_stc_size,b0_stc_vect,b0_stc_l2hit,tstamp); |
| 2412 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b0_cpx_tnum,b0_cpx_pa, |
| 2413 | b0_stc_size,b0_stc_vect,b0_stc_l2hit,tstamp); |
| 2414 | end // } |
| 2415 | end // } |
| 2416 | |
| 2417 | end // } |
| 2418 | else if (b0_store_commit && b0_stc_suppress) begin // { |
| 2419 | `PR_INFO ("pli_ldst", `INFO, |
| 2420 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b0_cpx_cid,b0_cpx_tid,b0_cpx_tnum,b0_cpx_pa); |
| 2421 | |
| 2422 | end // } |
| 2423 | |
| 2424 | //---------------------------------------------------------- |
| 2425 | //---------------------------------------------------------- |
| 2426 | // Evict |
| 2427 | // Note - NCU (bnk8 cannot send evictions) |
| 2428 | |
| 2429 | //------------------------------ |
| 2430 | // L2 Stub or L2 RTL Bank0 |
| 2431 | |
| 2432 | if (b0_evict) begin // { |
| 2433 | |
| 2434 | b0_ev_vect0 = b0_ev_invvect[31:0]; |
| 2435 | b0_ev_vect1 = b0_ev_invvect[55:32]; |
| 2436 | b0_ev_vect2 = b0_ev_invvect[87:56]; |
| 2437 | b0_ev_vect3 = b0_ev_invvect[111:88]; |
| 2438 | |
| 2439 | b0_inv_vect[0] = get_vect(b0_ev_vect0); |
| 2440 | b0_inv_vect[1] = get_vect31(b0_ev_vect1); // different function for odd inval vector |
| 2441 | b0_inv_vect[2] = get_vect(b0_ev_vect2); |
| 2442 | b0_inv_vect[3] = get_vect31(b0_ev_vect3); // different function for odd inval vector |
| 2443 | |
| 2444 | for (i=0; i<=3; i=i+1) begin // { |
| 2445 | |
| 2446 | b0_pa54 = i; |
| 2447 | b0_evict_pa = {b0_ev_pa[39:6],b0_pa54,4'b0}; |
| 2448 | b0_evict_inv_vect = b0_inv_vect[i]; |
| 2449 | |
| 2450 | if (b0_inv_vect[i]!=0) begin // { |
| 2451 | |
| 2452 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 2453 | if (`PARGS.hash_on && (b0_evict_pa[39]==1'b0)) begin // { |
| 2454 | `PR_INFO ("pli_ldst", `INFO, |
| 2455 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 2456 | `TOP.hashpa(b0_evict_pa),b0_evict_inv_vect,tstamp); |
| 2457 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b0_evict_pa),b0_evict_inv_vect,tstamp); |
| 2458 | end // } |
| 2459 | else begin //{ |
| 2460 | `PR_INFO ("pli_ldst", `INFO, |
| 2461 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 2462 | b0_evict_pa,b0_evict_inv_vect,tstamp); |
| 2463 | junk = $sim_send(`PLI_MEM_EVICT,b0_evict_pa,b0_evict_inv_vect,tstamp); |
| 2464 | end // if} |
| 2465 | end // if} |
| 2466 | |
| 2467 | if (`PARGS.show_memop_on) begin // { |
| 2468 | if (`PARGS.hash_on && (b0_evict_pa[39]==1'b0)) begin // { |
| 2469 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 2470 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 2471 | `TOP.hashpa(b0_evict_pa),tstamp); |
| 2472 | end // } |
| 2473 | else begin //{ |
| 2474 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 2475 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 2476 | b0_evict_pa,tstamp); |
| 2477 | end // } |
| 2478 | end // } |
| 2479 | |
| 2480 | end // if} |
| 2481 | end // for} |
| 2482 | |
| 2483 | end // } |
| 2484 | |
| 2485 | |
| 2486 | `endif |
| 2487 | |
| 2488 | end // always} |
| 2489 | |
| 2490 | //========================================================== |
| 2491 | // Bank1 |
| 2492 | |
| 2493 | always @ (posedge `BENCH_L2T1_GCLK) begin // { |
| 2494 | |
| 2495 | tstamp = `TOP.core_cycle_cnt - 1; |
| 2496 | |
| 2497 | //------------------------------ |
| 2498 | // Pipeline signals |
| 2499 | |
| 2500 | `ifdef NO_L2_BNK1 |
| 2501 | `else |
| 2502 | `ifdef NOL2RTL |
| 2503 | `else |
| 2504 | |
| 2505 | //------------------------------ |
| 2506 | // L2 RTL Bank1 |
| 2507 | |
| 2508 | b1_pa_c9 <= b1_pa_c8; |
| 2509 | b1_cpx_cid_c9 <= b1_cpx_cid_c8; |
| 2510 | b1_req_c7 <= b1_req_c6; |
| 2511 | b1_req_c8 <= b1_req_c7; |
| 2512 | |
| 2513 | b1_cam_pa_match_c2 <= b1_cam_pa_match_c1; |
| 2514 | b1_cam_pa_match_c3 <= b1_cam_pa_match_c2; |
| 2515 | |
| 2516 | b1_stall_c2 <= b1_stall_c1; |
| 2517 | b1_stall_c3 <= b1_stall_c2; |
| 2518 | b1_stall_c4 <= b1_stall_c3; |
| 2519 | b1_stall_c5 <= b1_stall_c4; |
| 2520 | b1_stall_c52 <= b1_stall_c5; |
| 2521 | b1_stall_c6 <= b1_stall_c52; |
| 2522 | b1_stall_c7 <= b1_stall_c6; |
| 2523 | b1_stall_c8 <= b1_stall_c7; |
| 2524 | b1_stall_c9 <= b1_stall_c8; |
| 2525 | |
| 2526 | b1_ev_pa_c5 <= b1_ev_pa_c4; |
| 2527 | b1_ev_pa_c52 <= b1_ev_pa_c5; |
| 2528 | b1_ev_pa_c6 <= b1_ev_pa_c52; |
| 2529 | b1_ev_pa_c7 <= b1_ev_pa_c6; |
| 2530 | b1_ev_pa_c8 <= b1_ev_pa_c7; |
| 2531 | |
| 2532 | b1_stc_l2hit_c4 <= b1_stc_l2hit_c3; |
| 2533 | b1_stc_l2hit_c5 <= b1_stc_l2hit_c4; |
| 2534 | b1_stc_l2hit_c52 <= b1_stc_l2hit_c5; |
| 2535 | b1_stc_l2hit_c6 <= b1_stc_l2hit_c52; |
| 2536 | b1_stc_l2hit_c7 <= b1_stc_l2hit_c6; |
| 2537 | b1_stc_l2hit_c8 <= b1_stc_l2hit_c7; |
| 2538 | |
| 2539 | b1_l2_ctrue_c4 <= b1_l2_ctrue_c3; |
| 2540 | b1_l2_ctrue_c5 <= b1_l2_ctrue_c4; |
| 2541 | b1_l2_ctrue_c52 <= b1_l2_ctrue_c5; |
| 2542 | b1_l2_ctrue_c6 <= b1_l2_ctrue_c52; |
| 2543 | b1_l2_ctrue_c7 <= b1_l2_ctrue_c6; |
| 2544 | b1_l2_ctrue_c8 <= b1_l2_ctrue_c7; |
| 2545 | |
| 2546 | `endif |
| 2547 | `endif |
| 2548 | |
| 2549 | //---------------------------------------------------------- |
| 2550 | //---------------------------------------------------------- |
| 2551 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 2552 | |
| 2553 | `ifdef NO_L2_BNK1 |
| 2554 | `else |
| 2555 | |
| 2556 | //------------------------------ |
| 2557 | // L2 Stub or L2 RTL Bank1 |
| 2558 | |
| 2559 | if (b1_load_data_miss && !b1_ldd_suppress) begin // { |
| 2560 | |
| 2561 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b1_cpx_tnum]) begin // { |
| 2562 | if (`PARGS.hash_on && (b1_cpx_pa[39]==1'b0)) begin // { |
| 2563 | `PR_INFO ("pli_ldst", `INFO, |
| 2564 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2565 | b1_cpx_cid,b1_cpx_tid,b1_cpx_tnum,`TOP.hashpa(b1_cpx_pa),dsrc,tstamp); |
| 2566 | junk = $sim_send(`PLI_MEM_LD_DATA,b1_cpx_tnum,`TOP.hashpa(b1_cpx_pa),dsrc,tstamp); |
| 2567 | end // } |
| 2568 | else begin //{ |
| 2569 | `PR_INFO ("pli_ldst", `INFO, |
| 2570 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2571 | b1_cpx_cid,b1_cpx_tid,b1_cpx_tnum,b1_cpx_pa,dsrc,tstamp); |
| 2572 | junk = $sim_send(`PLI_MEM_LD_DATA,b1_cpx_tnum,b1_cpx_pa,dsrc,tstamp); |
| 2573 | end // } |
| 2574 | end // } |
| 2575 | end // } |
| 2576 | else if (b1_load_data_miss && b1_ldd_suppress) begin // { |
| 2577 | `PR_INFO ("pli_ldst", `INFO, |
| 2578 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b1_cpx_cid,b1_cpx_tid,b1_cpx_tnum,b1_cpx_pa); |
| 2579 | |
| 2580 | end // } |
| 2581 | |
| 2582 | //---------------------------------------------------------- |
| 2583 | //---------------------------------------------------------- |
| 2584 | // Store L2 Commit |
| 2585 | |
| 2586 | //------------------------------ |
| 2587 | // L2 Stub or L2 RTL Bank1 |
| 2588 | |
| 2589 | if (b1_store_commit && !b1_stc_suppress) begin // { |
| 2590 | |
| 2591 | b1_stc_vect = get_vect (b1_stc_inv_vect); |
| 2592 | |
| 2593 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b1_cpx_tnum]) begin // { |
| 2594 | if (`PARGS.hash_on && (b1_cpx_pa[39]==1'b0)) begin // { |
| 2595 | `PR_INFO ("pli_ldst", `INFO, |
| 2596 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2597 | b1_cpx_cid,b1_cpx_tid,b1_cpx_tnum,`TOP.hashpa(b1_cpx_pa), |
| 2598 | b1_stc_size,b1_stc_vect,b1_stc_l2hit,tstamp); |
| 2599 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b1_cpx_tnum,`TOP.hashpa(b1_cpx_pa), |
| 2600 | b1_stc_size,b1_stc_vect,b1_stc_l2hit,tstamp); |
| 2601 | end // } |
| 2602 | else begin //{ |
| 2603 | `PR_INFO ("pli_ldst", `INFO, |
| 2604 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2605 | b1_cpx_cid,b1_cpx_tid,b1_cpx_tnum,b1_cpx_pa, |
| 2606 | b1_stc_size,b1_stc_vect,b1_stc_l2hit,tstamp); |
| 2607 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b1_cpx_tnum,b1_cpx_pa, |
| 2608 | b1_stc_size,b1_stc_vect,b1_stc_l2hit,tstamp); |
| 2609 | end // } |
| 2610 | end // } |
| 2611 | |
| 2612 | end // } |
| 2613 | else if (b1_store_commit && b1_stc_suppress) begin // { |
| 2614 | `PR_INFO ("pli_ldst", `INFO, |
| 2615 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b1_cpx_cid,b1_cpx_tid,b1_cpx_tnum,b1_cpx_pa); |
| 2616 | |
| 2617 | end // } |
| 2618 | |
| 2619 | //---------------------------------------------------------- |
| 2620 | //---------------------------------------------------------- |
| 2621 | // Evict |
| 2622 | // Note - NCU (bnk8 cannot send evictions) |
| 2623 | |
| 2624 | //------------------------------ |
| 2625 | // L2 Stub or L2 RTL Bank1 |
| 2626 | |
| 2627 | if (b1_evict) begin // { |
| 2628 | |
| 2629 | b1_ev_vect0 = b1_ev_invvect[31:0]; |
| 2630 | b1_ev_vect1 = b1_ev_invvect[55:32]; |
| 2631 | b1_ev_vect2 = b1_ev_invvect[87:56]; |
| 2632 | b1_ev_vect3 = b1_ev_invvect[111:88]; |
| 2633 | |
| 2634 | b1_inv_vect[0] = get_vect(b1_ev_vect0); |
| 2635 | b1_inv_vect[1] = get_vect31(b1_ev_vect1); // different function for odd inval vector |
| 2636 | b1_inv_vect[2] = get_vect(b1_ev_vect2); |
| 2637 | b1_inv_vect[3] = get_vect31(b1_ev_vect3); // different function for odd inval vector |
| 2638 | |
| 2639 | for (i=0; i<=3; i=i+1) begin // { |
| 2640 | |
| 2641 | b1_pa54 = i; |
| 2642 | b1_evict_pa = {b1_ev_pa[39:6],b1_pa54,4'b0}; |
| 2643 | b1_evict_inv_vect = b1_inv_vect[i]; |
| 2644 | |
| 2645 | if (b1_inv_vect[i]!=0) begin // { |
| 2646 | |
| 2647 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 2648 | if (`PARGS.hash_on && (b1_evict_pa[39]==1'b0)) begin // { |
| 2649 | `PR_INFO ("pli_ldst", `INFO, |
| 2650 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 2651 | `TOP.hashpa(b1_evict_pa),b1_evict_inv_vect,tstamp); |
| 2652 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b1_evict_pa),b1_evict_inv_vect,tstamp); |
| 2653 | end // } |
| 2654 | else begin //{ |
| 2655 | `PR_INFO ("pli_ldst", `INFO, |
| 2656 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 2657 | b1_evict_pa,b1_evict_inv_vect,tstamp); |
| 2658 | junk = $sim_send(`PLI_MEM_EVICT,b1_evict_pa,b1_evict_inv_vect,tstamp); |
| 2659 | end // if} |
| 2660 | end // if} |
| 2661 | |
| 2662 | if (`PARGS.show_memop_on) begin // { |
| 2663 | if (`PARGS.hash_on && (b1_evict_pa[39]==1'b0)) begin // { |
| 2664 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 2665 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 2666 | `TOP.hashpa(b1_evict_pa),tstamp); |
| 2667 | end // } |
| 2668 | else begin //{ |
| 2669 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 2670 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 2671 | b1_evict_pa,tstamp); |
| 2672 | end // } |
| 2673 | end // } |
| 2674 | |
| 2675 | end // if} |
| 2676 | end // for} |
| 2677 | |
| 2678 | end // } |
| 2679 | |
| 2680 | |
| 2681 | `endif |
| 2682 | |
| 2683 | end // always} |
| 2684 | |
| 2685 | //========================================================== |
| 2686 | // Bank2 |
| 2687 | |
| 2688 | always @ (posedge `BENCH_L2T2_GCLK) begin // { |
| 2689 | |
| 2690 | tstamp = `TOP.core_cycle_cnt - 1; |
| 2691 | |
| 2692 | //------------------------------ |
| 2693 | // Pipeline signals |
| 2694 | |
| 2695 | `ifdef NO_L2_BNK2 |
| 2696 | `else |
| 2697 | `ifdef NOL2RTL |
| 2698 | `else |
| 2699 | |
| 2700 | //------------------------------ |
| 2701 | // L2 RTL Bank2 |
| 2702 | |
| 2703 | b2_pa_c9 <= b2_pa_c8; |
| 2704 | b2_cpx_cid_c9 <= b2_cpx_cid_c8; |
| 2705 | b2_req_c7 <= b2_req_c6; |
| 2706 | b2_req_c8 <= b2_req_c7; |
| 2707 | |
| 2708 | b2_cam_pa_match_c2 <= b2_cam_pa_match_c1; |
| 2709 | b2_cam_pa_match_c3 <= b2_cam_pa_match_c2; |
| 2710 | |
| 2711 | b2_stall_c2 <= b2_stall_c1; |
| 2712 | b2_stall_c3 <= b2_stall_c2; |
| 2713 | b2_stall_c4 <= b2_stall_c3; |
| 2714 | b2_stall_c5 <= b2_stall_c4; |
| 2715 | b2_stall_c52 <= b2_stall_c5; |
| 2716 | b2_stall_c6 <= b2_stall_c52; |
| 2717 | b2_stall_c7 <= b2_stall_c6; |
| 2718 | b2_stall_c8 <= b2_stall_c7; |
| 2719 | b2_stall_c9 <= b2_stall_c8; |
| 2720 | |
| 2721 | b2_ev_pa_c5 <= b2_ev_pa_c4; |
| 2722 | b2_ev_pa_c52 <= b2_ev_pa_c5; |
| 2723 | b2_ev_pa_c6 <= b2_ev_pa_c52; |
| 2724 | b2_ev_pa_c7 <= b2_ev_pa_c6; |
| 2725 | b2_ev_pa_c8 <= b2_ev_pa_c7; |
| 2726 | |
| 2727 | b2_stc_l2hit_c4 <= b2_stc_l2hit_c3; |
| 2728 | b2_stc_l2hit_c5 <= b2_stc_l2hit_c4; |
| 2729 | b2_stc_l2hit_c52 <= b2_stc_l2hit_c5; |
| 2730 | b2_stc_l2hit_c6 <= b2_stc_l2hit_c52; |
| 2731 | b2_stc_l2hit_c7 <= b2_stc_l2hit_c6; |
| 2732 | b2_stc_l2hit_c8 <= b2_stc_l2hit_c7; |
| 2733 | |
| 2734 | b2_l2_ctrue_c4 <= b2_l2_ctrue_c3; |
| 2735 | b2_l2_ctrue_c5 <= b2_l2_ctrue_c4; |
| 2736 | b2_l2_ctrue_c52 <= b2_l2_ctrue_c5; |
| 2737 | b2_l2_ctrue_c6 <= b2_l2_ctrue_c52; |
| 2738 | b2_l2_ctrue_c7 <= b2_l2_ctrue_c6; |
| 2739 | b2_l2_ctrue_c8 <= b2_l2_ctrue_c7; |
| 2740 | |
| 2741 | `endif |
| 2742 | `endif |
| 2743 | |
| 2744 | //---------------------------------------------------------- |
| 2745 | //---------------------------------------------------------- |
| 2746 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 2747 | |
| 2748 | `ifdef NO_L2_BNK2 |
| 2749 | `else |
| 2750 | |
| 2751 | //------------------------------ |
| 2752 | // L2 Stub or L2 RTL Bank2 |
| 2753 | |
| 2754 | if (b2_load_data_miss && !b2_ldd_suppress) begin // { |
| 2755 | |
| 2756 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b2_cpx_tnum]) begin // { |
| 2757 | if (`PARGS.hash_on && (b2_cpx_pa[39]==1'b0)) begin // { |
| 2758 | `PR_INFO ("pli_ldst", `INFO, |
| 2759 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2760 | b2_cpx_cid,b2_cpx_tid,b2_cpx_tnum,`TOP.hashpa(b2_cpx_pa),dsrc,tstamp); |
| 2761 | junk = $sim_send(`PLI_MEM_LD_DATA,b2_cpx_tnum,`TOP.hashpa(b2_cpx_pa),dsrc,tstamp); |
| 2762 | end // } |
| 2763 | else begin //{ |
| 2764 | `PR_INFO ("pli_ldst", `INFO, |
| 2765 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2766 | b2_cpx_cid,b2_cpx_tid,b2_cpx_tnum,b2_cpx_pa,dsrc,tstamp); |
| 2767 | junk = $sim_send(`PLI_MEM_LD_DATA,b2_cpx_tnum,b2_cpx_pa,dsrc,tstamp); |
| 2768 | end // } |
| 2769 | end // } |
| 2770 | end // } |
| 2771 | else if (b2_load_data_miss && b2_ldd_suppress) begin // { |
| 2772 | `PR_INFO ("pli_ldst", `INFO, |
| 2773 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b2_cpx_cid,b2_cpx_tid,b2_cpx_tnum,b2_cpx_pa); |
| 2774 | |
| 2775 | end // } |
| 2776 | |
| 2777 | //---------------------------------------------------------- |
| 2778 | //---------------------------------------------------------- |
| 2779 | // Store L2 Commit |
| 2780 | |
| 2781 | //------------------------------ |
| 2782 | // L2 Stub or L2 RTL Bank2 |
| 2783 | |
| 2784 | if (b2_store_commit && !b2_stc_suppress) begin // { |
| 2785 | |
| 2786 | b2_stc_vect = get_vect (b2_stc_inv_vect); |
| 2787 | |
| 2788 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b2_cpx_tnum]) begin // { |
| 2789 | if (`PARGS.hash_on && (b2_cpx_pa[39]==1'b0)) begin // { |
| 2790 | `PR_INFO ("pli_ldst", `INFO, |
| 2791 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2792 | b2_cpx_cid,b2_cpx_tid,b2_cpx_tnum,`TOP.hashpa(b2_cpx_pa), |
| 2793 | b2_stc_size,b2_stc_vect,b2_stc_l2hit,tstamp); |
| 2794 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b2_cpx_tnum,`TOP.hashpa(b2_cpx_pa), |
| 2795 | b2_stc_size,b2_stc_vect,b2_stc_l2hit,tstamp); |
| 2796 | end // } |
| 2797 | else begin //{ |
| 2798 | `PR_INFO ("pli_ldst", `INFO, |
| 2799 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2800 | b2_cpx_cid,b2_cpx_tid,b2_cpx_tnum,b2_cpx_pa, |
| 2801 | b2_stc_size,b2_stc_vect,b2_stc_l2hit,tstamp); |
| 2802 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b2_cpx_tnum,b2_cpx_pa, |
| 2803 | b2_stc_size,b2_stc_vect,b2_stc_l2hit,tstamp); |
| 2804 | end // } |
| 2805 | end // } |
| 2806 | |
| 2807 | end // } |
| 2808 | else if (b2_store_commit && b2_stc_suppress) begin // { |
| 2809 | `PR_INFO ("pli_ldst", `INFO, |
| 2810 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b2_cpx_cid,b2_cpx_tid,b2_cpx_tnum,b2_cpx_pa); |
| 2811 | |
| 2812 | end // } |
| 2813 | |
| 2814 | //---------------------------------------------------------- |
| 2815 | //---------------------------------------------------------- |
| 2816 | // Evict |
| 2817 | // Note - NCU (bnk8 cannot send evictions) |
| 2818 | |
| 2819 | //------------------------------ |
| 2820 | // L2 Stub or L2 RTL Bank2 |
| 2821 | |
| 2822 | if (b2_evict) begin // { |
| 2823 | |
| 2824 | b2_ev_vect0 = b2_ev_invvect[31:0]; |
| 2825 | b2_ev_vect1 = b2_ev_invvect[55:32]; |
| 2826 | b2_ev_vect2 = b2_ev_invvect[87:56]; |
| 2827 | b2_ev_vect3 = b2_ev_invvect[111:88]; |
| 2828 | |
| 2829 | b2_inv_vect[0] = get_vect(b2_ev_vect0); |
| 2830 | b2_inv_vect[1] = get_vect31(b2_ev_vect1); // different function for odd inval vector |
| 2831 | b2_inv_vect[2] = get_vect(b2_ev_vect2); |
| 2832 | b2_inv_vect[3] = get_vect31(b2_ev_vect3); // different function for odd inval vector |
| 2833 | |
| 2834 | for (i=0; i<=3; i=i+1) begin // { |
| 2835 | |
| 2836 | b2_pa54 = i; |
| 2837 | b2_evict_pa = {b2_ev_pa[39:6],b2_pa54,4'b0}; |
| 2838 | b2_evict_inv_vect = b2_inv_vect[i]; |
| 2839 | |
| 2840 | if (b2_inv_vect[i]!=0) begin // { |
| 2841 | |
| 2842 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 2843 | if (`PARGS.hash_on && (b2_evict_pa[39]==1'b0)) begin // { |
| 2844 | `PR_INFO ("pli_ldst", `INFO, |
| 2845 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 2846 | `TOP.hashpa(b2_evict_pa),b2_evict_inv_vect,tstamp); |
| 2847 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b2_evict_pa),b2_evict_inv_vect,tstamp); |
| 2848 | end // } |
| 2849 | else begin //{ |
| 2850 | `PR_INFO ("pli_ldst", `INFO, |
| 2851 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 2852 | b2_evict_pa,b2_evict_inv_vect,tstamp); |
| 2853 | junk = $sim_send(`PLI_MEM_EVICT,b2_evict_pa,b2_evict_inv_vect,tstamp); |
| 2854 | end // if} |
| 2855 | end // if} |
| 2856 | |
| 2857 | if (`PARGS.show_memop_on) begin // { |
| 2858 | if (`PARGS.hash_on && (b2_evict_pa[39]==1'b0)) begin // { |
| 2859 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 2860 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 2861 | `TOP.hashpa(b2_evict_pa),tstamp); |
| 2862 | end // } |
| 2863 | else begin //{ |
| 2864 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 2865 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 2866 | b2_evict_pa,tstamp); |
| 2867 | end // } |
| 2868 | end // } |
| 2869 | |
| 2870 | end // if} |
| 2871 | end // for} |
| 2872 | |
| 2873 | end // } |
| 2874 | |
| 2875 | |
| 2876 | `endif |
| 2877 | |
| 2878 | end // always} |
| 2879 | |
| 2880 | //========================================================== |
| 2881 | // Bank3 |
| 2882 | |
| 2883 | always @ (posedge `BENCH_L2T3_GCLK) begin // { |
| 2884 | |
| 2885 | tstamp = `TOP.core_cycle_cnt - 1; |
| 2886 | |
| 2887 | //------------------------------ |
| 2888 | // Pipeline signals |
| 2889 | |
| 2890 | `ifdef NO_L2_BNK3 |
| 2891 | `else |
| 2892 | `ifdef NOL2RTL |
| 2893 | `else |
| 2894 | |
| 2895 | //------------------------------ |
| 2896 | // L2 RTL Bank3 |
| 2897 | |
| 2898 | b3_pa_c9 <= b3_pa_c8; |
| 2899 | b3_cpx_cid_c9 <= b3_cpx_cid_c8; |
| 2900 | b3_req_c7 <= b3_req_c6; |
| 2901 | b3_req_c8 <= b3_req_c7; |
| 2902 | |
| 2903 | b3_cam_pa_match_c2 <= b3_cam_pa_match_c1; |
| 2904 | b3_cam_pa_match_c3 <= b3_cam_pa_match_c2; |
| 2905 | |
| 2906 | b3_stall_c2 <= b3_stall_c1; |
| 2907 | b3_stall_c3 <= b3_stall_c2; |
| 2908 | b3_stall_c4 <= b3_stall_c3; |
| 2909 | b3_stall_c5 <= b3_stall_c4; |
| 2910 | b3_stall_c52 <= b3_stall_c5; |
| 2911 | b3_stall_c6 <= b3_stall_c52; |
| 2912 | b3_stall_c7 <= b3_stall_c6; |
| 2913 | b3_stall_c8 <= b3_stall_c7; |
| 2914 | b3_stall_c9 <= b3_stall_c8; |
| 2915 | |
| 2916 | b3_ev_pa_c5 <= b3_ev_pa_c4; |
| 2917 | b3_ev_pa_c52 <= b3_ev_pa_c5; |
| 2918 | b3_ev_pa_c6 <= b3_ev_pa_c52; |
| 2919 | b3_ev_pa_c7 <= b3_ev_pa_c6; |
| 2920 | b3_ev_pa_c8 <= b3_ev_pa_c7; |
| 2921 | |
| 2922 | b3_stc_l2hit_c4 <= b3_stc_l2hit_c3; |
| 2923 | b3_stc_l2hit_c5 <= b3_stc_l2hit_c4; |
| 2924 | b3_stc_l2hit_c52 <= b3_stc_l2hit_c5; |
| 2925 | b3_stc_l2hit_c6 <= b3_stc_l2hit_c52; |
| 2926 | b3_stc_l2hit_c7 <= b3_stc_l2hit_c6; |
| 2927 | b3_stc_l2hit_c8 <= b3_stc_l2hit_c7; |
| 2928 | |
| 2929 | b3_l2_ctrue_c4 <= b3_l2_ctrue_c3; |
| 2930 | b3_l2_ctrue_c5 <= b3_l2_ctrue_c4; |
| 2931 | b3_l2_ctrue_c52 <= b3_l2_ctrue_c5; |
| 2932 | b3_l2_ctrue_c6 <= b3_l2_ctrue_c52; |
| 2933 | b3_l2_ctrue_c7 <= b3_l2_ctrue_c6; |
| 2934 | b3_l2_ctrue_c8 <= b3_l2_ctrue_c7; |
| 2935 | |
| 2936 | `endif |
| 2937 | `endif |
| 2938 | |
| 2939 | //---------------------------------------------------------- |
| 2940 | //---------------------------------------------------------- |
| 2941 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 2942 | |
| 2943 | `ifdef NO_L2_BNK3 |
| 2944 | `else |
| 2945 | |
| 2946 | //------------------------------ |
| 2947 | // L2 Stub or L2 RTL Bank3 |
| 2948 | |
| 2949 | if (b3_load_data_miss && !b3_ldd_suppress) begin // { |
| 2950 | |
| 2951 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b3_cpx_tnum]) begin // { |
| 2952 | if (`PARGS.hash_on && (b3_cpx_pa[39]==1'b0)) begin // { |
| 2953 | `PR_INFO ("pli_ldst", `INFO, |
| 2954 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2955 | b3_cpx_cid,b3_cpx_tid,b3_cpx_tnum,`TOP.hashpa(b3_cpx_pa),dsrc,tstamp); |
| 2956 | junk = $sim_send(`PLI_MEM_LD_DATA,b3_cpx_tnum,`TOP.hashpa(b3_cpx_pa),dsrc,tstamp); |
| 2957 | end // } |
| 2958 | else begin //{ |
| 2959 | `PR_INFO ("pli_ldst", `INFO, |
| 2960 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 2961 | b3_cpx_cid,b3_cpx_tid,b3_cpx_tnum,b3_cpx_pa,dsrc,tstamp); |
| 2962 | junk = $sim_send(`PLI_MEM_LD_DATA,b3_cpx_tnum,b3_cpx_pa,dsrc,tstamp); |
| 2963 | end // } |
| 2964 | end // } |
| 2965 | end // } |
| 2966 | else if (b3_load_data_miss && b3_ldd_suppress) begin // { |
| 2967 | `PR_INFO ("pli_ldst", `INFO, |
| 2968 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b3_cpx_cid,b3_cpx_tid,b3_cpx_tnum,b3_cpx_pa); |
| 2969 | |
| 2970 | end // } |
| 2971 | |
| 2972 | //---------------------------------------------------------- |
| 2973 | //---------------------------------------------------------- |
| 2974 | // Store L2 Commit |
| 2975 | |
| 2976 | //------------------------------ |
| 2977 | // L2 Stub or L2 RTL Bank3 |
| 2978 | |
| 2979 | if (b3_store_commit && !b3_stc_suppress) begin // { |
| 2980 | |
| 2981 | b3_stc_vect = get_vect (b3_stc_inv_vect); |
| 2982 | |
| 2983 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b3_cpx_tnum]) begin // { |
| 2984 | if (`PARGS.hash_on && (b3_cpx_pa[39]==1'b0)) begin // { |
| 2985 | `PR_INFO ("pli_ldst", `INFO, |
| 2986 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2987 | b3_cpx_cid,b3_cpx_tid,b3_cpx_tnum,`TOP.hashpa(b3_cpx_pa), |
| 2988 | b3_stc_size,b3_stc_vect,b3_stc_l2hit,tstamp); |
| 2989 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b3_cpx_tnum,`TOP.hashpa(b3_cpx_pa), |
| 2990 | b3_stc_size,b3_stc_vect,b3_stc_l2hit,tstamp); |
| 2991 | end // } |
| 2992 | else begin //{ |
| 2993 | `PR_INFO ("pli_ldst", `INFO, |
| 2994 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 2995 | b3_cpx_cid,b3_cpx_tid,b3_cpx_tnum,b3_cpx_pa, |
| 2996 | b3_stc_size,b3_stc_vect,b3_stc_l2hit,tstamp); |
| 2997 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b3_cpx_tnum,b3_cpx_pa, |
| 2998 | b3_stc_size,b3_stc_vect,b3_stc_l2hit,tstamp); |
| 2999 | end // } |
| 3000 | end // } |
| 3001 | |
| 3002 | end // } |
| 3003 | else if (b3_store_commit && b3_stc_suppress) begin // { |
| 3004 | `PR_INFO ("pli_ldst", `INFO, |
| 3005 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b3_cpx_cid,b3_cpx_tid,b3_cpx_tnum,b3_cpx_pa); |
| 3006 | |
| 3007 | end // } |
| 3008 | |
| 3009 | //---------------------------------------------------------- |
| 3010 | //---------------------------------------------------------- |
| 3011 | // Evict |
| 3012 | // Note - NCU (bnk8 cannot send evictions) |
| 3013 | |
| 3014 | //------------------------------ |
| 3015 | // L2 Stub or L2 RTL Bank3 |
| 3016 | |
| 3017 | if (b3_evict) begin // { |
| 3018 | |
| 3019 | b3_ev_vect0 = b3_ev_invvect[31:0]; |
| 3020 | b3_ev_vect1 = b3_ev_invvect[55:32]; |
| 3021 | b3_ev_vect2 = b3_ev_invvect[87:56]; |
| 3022 | b3_ev_vect3 = b3_ev_invvect[111:88]; |
| 3023 | |
| 3024 | b3_inv_vect[0] = get_vect(b3_ev_vect0); |
| 3025 | b3_inv_vect[1] = get_vect31(b3_ev_vect1); // different function for odd inval vector |
| 3026 | b3_inv_vect[2] = get_vect(b3_ev_vect2); |
| 3027 | b3_inv_vect[3] = get_vect31(b3_ev_vect3); // different function for odd inval vector |
| 3028 | |
| 3029 | for (i=0; i<=3; i=i+1) begin // { |
| 3030 | |
| 3031 | b3_pa54 = i; |
| 3032 | b3_evict_pa = {b3_ev_pa[39:6],b3_pa54,4'b0}; |
| 3033 | b3_evict_inv_vect = b3_inv_vect[i]; |
| 3034 | |
| 3035 | if (b3_inv_vect[i]!=0) begin // { |
| 3036 | |
| 3037 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 3038 | if (`PARGS.hash_on && (b3_evict_pa[39]==1'b0)) begin // { |
| 3039 | `PR_INFO ("pli_ldst", `INFO, |
| 3040 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3041 | `TOP.hashpa(b3_evict_pa),b3_evict_inv_vect,tstamp); |
| 3042 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b3_evict_pa),b3_evict_inv_vect,tstamp); |
| 3043 | end // } |
| 3044 | else begin //{ |
| 3045 | `PR_INFO ("pli_ldst", `INFO, |
| 3046 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3047 | b3_evict_pa,b3_evict_inv_vect,tstamp); |
| 3048 | junk = $sim_send(`PLI_MEM_EVICT,b3_evict_pa,b3_evict_inv_vect,tstamp); |
| 3049 | end // if} |
| 3050 | end // if} |
| 3051 | |
| 3052 | if (`PARGS.show_memop_on) begin // { |
| 3053 | if (`PARGS.hash_on && (b3_evict_pa[39]==1'b0)) begin // { |
| 3054 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3055 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3056 | `TOP.hashpa(b3_evict_pa),tstamp); |
| 3057 | end // } |
| 3058 | else begin //{ |
| 3059 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3060 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3061 | b3_evict_pa,tstamp); |
| 3062 | end // } |
| 3063 | end // } |
| 3064 | |
| 3065 | end // if} |
| 3066 | end // for} |
| 3067 | |
| 3068 | end // } |
| 3069 | |
| 3070 | |
| 3071 | `endif |
| 3072 | |
| 3073 | end // always} |
| 3074 | |
| 3075 | //========================================================== |
| 3076 | // Bank4 |
| 3077 | |
| 3078 | always @ (posedge `BENCH_L2T4_GCLK) begin // { |
| 3079 | |
| 3080 | tstamp = `TOP.core_cycle_cnt - 1; |
| 3081 | |
| 3082 | //------------------------------ |
| 3083 | // Pipeline signals |
| 3084 | |
| 3085 | `ifdef NO_L2_BNK4 |
| 3086 | `else |
| 3087 | `ifdef NOL2RTL |
| 3088 | `else |
| 3089 | |
| 3090 | //------------------------------ |
| 3091 | // L2 RTL Bank4 |
| 3092 | |
| 3093 | b4_pa_c9 <= b4_pa_c8; |
| 3094 | b4_cpx_cid_c9 <= b4_cpx_cid_c8; |
| 3095 | b4_req_c7 <= b4_req_c6; |
| 3096 | b4_req_c8 <= b4_req_c7; |
| 3097 | |
| 3098 | b4_cam_pa_match_c2 <= b4_cam_pa_match_c1; |
| 3099 | b4_cam_pa_match_c3 <= b4_cam_pa_match_c2; |
| 3100 | |
| 3101 | b4_stall_c2 <= b4_stall_c1; |
| 3102 | b4_stall_c3 <= b4_stall_c2; |
| 3103 | b4_stall_c4 <= b4_stall_c3; |
| 3104 | b4_stall_c5 <= b4_stall_c4; |
| 3105 | b4_stall_c52 <= b4_stall_c5; |
| 3106 | b4_stall_c6 <= b4_stall_c52; |
| 3107 | b4_stall_c7 <= b4_stall_c6; |
| 3108 | b4_stall_c8 <= b4_stall_c7; |
| 3109 | b4_stall_c9 <= b4_stall_c8; |
| 3110 | |
| 3111 | b4_ev_pa_c5 <= b4_ev_pa_c4; |
| 3112 | b4_ev_pa_c52 <= b4_ev_pa_c5; |
| 3113 | b4_ev_pa_c6 <= b4_ev_pa_c52; |
| 3114 | b4_ev_pa_c7 <= b4_ev_pa_c6; |
| 3115 | b4_ev_pa_c8 <= b4_ev_pa_c7; |
| 3116 | |
| 3117 | b4_stc_l2hit_c4 <= b4_stc_l2hit_c3; |
| 3118 | b4_stc_l2hit_c5 <= b4_stc_l2hit_c4; |
| 3119 | b4_stc_l2hit_c52 <= b4_stc_l2hit_c5; |
| 3120 | b4_stc_l2hit_c6 <= b4_stc_l2hit_c52; |
| 3121 | b4_stc_l2hit_c7 <= b4_stc_l2hit_c6; |
| 3122 | b4_stc_l2hit_c8 <= b4_stc_l2hit_c7; |
| 3123 | |
| 3124 | b4_l2_ctrue_c4 <= b4_l2_ctrue_c3; |
| 3125 | b4_l2_ctrue_c5 <= b4_l2_ctrue_c4; |
| 3126 | b4_l2_ctrue_c52 <= b4_l2_ctrue_c5; |
| 3127 | b4_l2_ctrue_c6 <= b4_l2_ctrue_c52; |
| 3128 | b4_l2_ctrue_c7 <= b4_l2_ctrue_c6; |
| 3129 | b4_l2_ctrue_c8 <= b4_l2_ctrue_c7; |
| 3130 | |
| 3131 | `endif |
| 3132 | `endif |
| 3133 | |
| 3134 | //---------------------------------------------------------- |
| 3135 | //---------------------------------------------------------- |
| 3136 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 3137 | |
| 3138 | `ifdef NO_L2_BNK4 |
| 3139 | `else |
| 3140 | |
| 3141 | //------------------------------ |
| 3142 | // L2 Stub or L2 RTL Bank4 |
| 3143 | |
| 3144 | if (b4_load_data_miss && !b4_ldd_suppress) begin // { |
| 3145 | |
| 3146 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b4_cpx_tnum]) begin // { |
| 3147 | if (`PARGS.hash_on && (b4_cpx_pa[39]==1'b0)) begin // { |
| 3148 | `PR_INFO ("pli_ldst", `INFO, |
| 3149 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3150 | b4_cpx_cid,b4_cpx_tid,b4_cpx_tnum,`TOP.hashpa(b4_cpx_pa),dsrc,tstamp); |
| 3151 | junk = $sim_send(`PLI_MEM_LD_DATA,b4_cpx_tnum,`TOP.hashpa(b4_cpx_pa),dsrc,tstamp); |
| 3152 | end // } |
| 3153 | else begin //{ |
| 3154 | `PR_INFO ("pli_ldst", `INFO, |
| 3155 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3156 | b4_cpx_cid,b4_cpx_tid,b4_cpx_tnum,b4_cpx_pa,dsrc,tstamp); |
| 3157 | junk = $sim_send(`PLI_MEM_LD_DATA,b4_cpx_tnum,b4_cpx_pa,dsrc,tstamp); |
| 3158 | end // } |
| 3159 | end // } |
| 3160 | end // } |
| 3161 | else if (b4_load_data_miss && b4_ldd_suppress) begin // { |
| 3162 | `PR_INFO ("pli_ldst", `INFO, |
| 3163 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b4_cpx_cid,b4_cpx_tid,b4_cpx_tnum,b4_cpx_pa); |
| 3164 | |
| 3165 | end // } |
| 3166 | |
| 3167 | //---------------------------------------------------------- |
| 3168 | //---------------------------------------------------------- |
| 3169 | // Store L2 Commit |
| 3170 | |
| 3171 | //------------------------------ |
| 3172 | // L2 Stub or L2 RTL Bank4 |
| 3173 | |
| 3174 | if (b4_store_commit && !b4_stc_suppress) begin // { |
| 3175 | |
| 3176 | b4_stc_vect = get_vect (b4_stc_inv_vect); |
| 3177 | |
| 3178 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b4_cpx_tnum]) begin // { |
| 3179 | if (`PARGS.hash_on && (b4_cpx_pa[39]==1'b0)) begin // { |
| 3180 | `PR_INFO ("pli_ldst", `INFO, |
| 3181 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3182 | b4_cpx_cid,b4_cpx_tid,b4_cpx_tnum,`TOP.hashpa(b4_cpx_pa), |
| 3183 | b4_stc_size,b4_stc_vect,b4_stc_l2hit,tstamp); |
| 3184 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b4_cpx_tnum,`TOP.hashpa(b4_cpx_pa), |
| 3185 | b4_stc_size,b4_stc_vect,b4_stc_l2hit,tstamp); |
| 3186 | end // } |
| 3187 | else begin //{ |
| 3188 | `PR_INFO ("pli_ldst", `INFO, |
| 3189 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3190 | b4_cpx_cid,b4_cpx_tid,b4_cpx_tnum,b4_cpx_pa, |
| 3191 | b4_stc_size,b4_stc_vect,b4_stc_l2hit,tstamp); |
| 3192 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b4_cpx_tnum,b4_cpx_pa, |
| 3193 | b4_stc_size,b4_stc_vect,b4_stc_l2hit,tstamp); |
| 3194 | end // } |
| 3195 | end // } |
| 3196 | |
| 3197 | end // } |
| 3198 | else if (b4_store_commit && b4_stc_suppress) begin // { |
| 3199 | `PR_INFO ("pli_ldst", `INFO, |
| 3200 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b4_cpx_cid,b4_cpx_tid,b4_cpx_tnum,b4_cpx_pa); |
| 3201 | |
| 3202 | end // } |
| 3203 | |
| 3204 | //---------------------------------------------------------- |
| 3205 | //---------------------------------------------------------- |
| 3206 | // Evict |
| 3207 | // Note - NCU (bnk8 cannot send evictions) |
| 3208 | |
| 3209 | //------------------------------ |
| 3210 | // L2 Stub or L2 RTL Bank4 |
| 3211 | |
| 3212 | if (b4_evict) begin // { |
| 3213 | |
| 3214 | b4_ev_vect0 = b4_ev_invvect[31:0]; |
| 3215 | b4_ev_vect1 = b4_ev_invvect[55:32]; |
| 3216 | b4_ev_vect2 = b4_ev_invvect[87:56]; |
| 3217 | b4_ev_vect3 = b4_ev_invvect[111:88]; |
| 3218 | |
| 3219 | b4_inv_vect[0] = get_vect(b4_ev_vect0); |
| 3220 | b4_inv_vect[1] = get_vect31(b4_ev_vect1); // different function for odd inval vector |
| 3221 | b4_inv_vect[2] = get_vect(b4_ev_vect2); |
| 3222 | b4_inv_vect[3] = get_vect31(b4_ev_vect3); // different function for odd inval vector |
| 3223 | |
| 3224 | for (i=0; i<=3; i=i+1) begin // { |
| 3225 | |
| 3226 | b4_pa54 = i; |
| 3227 | b4_evict_pa = {b4_ev_pa[39:6],b4_pa54,4'b0}; |
| 3228 | b4_evict_inv_vect = b4_inv_vect[i]; |
| 3229 | |
| 3230 | if (b4_inv_vect[i]!=0) begin // { |
| 3231 | |
| 3232 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 3233 | if (`PARGS.hash_on && (b4_evict_pa[39]==1'b0)) begin // { |
| 3234 | `PR_INFO ("pli_ldst", `INFO, |
| 3235 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3236 | `TOP.hashpa(b4_evict_pa),b4_evict_inv_vect,tstamp); |
| 3237 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b4_evict_pa),b4_evict_inv_vect,tstamp); |
| 3238 | end // } |
| 3239 | else begin //{ |
| 3240 | `PR_INFO ("pli_ldst", `INFO, |
| 3241 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3242 | b4_evict_pa,b4_evict_inv_vect,tstamp); |
| 3243 | junk = $sim_send(`PLI_MEM_EVICT,b4_evict_pa,b4_evict_inv_vect,tstamp); |
| 3244 | end // if} |
| 3245 | end // if} |
| 3246 | |
| 3247 | if (`PARGS.show_memop_on) begin // { |
| 3248 | if (`PARGS.hash_on && (b4_evict_pa[39]==1'b0)) begin // { |
| 3249 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3250 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3251 | `TOP.hashpa(b4_evict_pa),tstamp); |
| 3252 | end // } |
| 3253 | else begin //{ |
| 3254 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3255 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3256 | b4_evict_pa,tstamp); |
| 3257 | end // } |
| 3258 | end // } |
| 3259 | |
| 3260 | end // if} |
| 3261 | end // for} |
| 3262 | |
| 3263 | end // } |
| 3264 | |
| 3265 | |
| 3266 | `endif |
| 3267 | |
| 3268 | end // always} |
| 3269 | |
| 3270 | //========================================================== |
| 3271 | // Bank5 |
| 3272 | |
| 3273 | always @ (posedge `BENCH_L2T5_GCLK) begin // { |
| 3274 | |
| 3275 | tstamp = `TOP.core_cycle_cnt - 1; |
| 3276 | |
| 3277 | //------------------------------ |
| 3278 | // Pipeline signals |
| 3279 | |
| 3280 | `ifdef NO_L2_BNK5 |
| 3281 | `else |
| 3282 | `ifdef NOL2RTL |
| 3283 | `else |
| 3284 | |
| 3285 | //------------------------------ |
| 3286 | // L2 RTL Bank5 |
| 3287 | |
| 3288 | b5_pa_c9 <= b5_pa_c8; |
| 3289 | b5_cpx_cid_c9 <= b5_cpx_cid_c8; |
| 3290 | b5_req_c7 <= b5_req_c6; |
| 3291 | b5_req_c8 <= b5_req_c7; |
| 3292 | |
| 3293 | b5_cam_pa_match_c2 <= b5_cam_pa_match_c1; |
| 3294 | b5_cam_pa_match_c3 <= b5_cam_pa_match_c2; |
| 3295 | |
| 3296 | b5_stall_c2 <= b5_stall_c1; |
| 3297 | b5_stall_c3 <= b5_stall_c2; |
| 3298 | b5_stall_c4 <= b5_stall_c3; |
| 3299 | b5_stall_c5 <= b5_stall_c4; |
| 3300 | b5_stall_c52 <= b5_stall_c5; |
| 3301 | b5_stall_c6 <= b5_stall_c52; |
| 3302 | b5_stall_c7 <= b5_stall_c6; |
| 3303 | b5_stall_c8 <= b5_stall_c7; |
| 3304 | b5_stall_c9 <= b5_stall_c8; |
| 3305 | |
| 3306 | b5_ev_pa_c5 <= b5_ev_pa_c4; |
| 3307 | b5_ev_pa_c52 <= b5_ev_pa_c5; |
| 3308 | b5_ev_pa_c6 <= b5_ev_pa_c52; |
| 3309 | b5_ev_pa_c7 <= b5_ev_pa_c6; |
| 3310 | b5_ev_pa_c8 <= b5_ev_pa_c7; |
| 3311 | |
| 3312 | b5_stc_l2hit_c4 <= b5_stc_l2hit_c3; |
| 3313 | b5_stc_l2hit_c5 <= b5_stc_l2hit_c4; |
| 3314 | b5_stc_l2hit_c52 <= b5_stc_l2hit_c5; |
| 3315 | b5_stc_l2hit_c6 <= b5_stc_l2hit_c52; |
| 3316 | b5_stc_l2hit_c7 <= b5_stc_l2hit_c6; |
| 3317 | b5_stc_l2hit_c8 <= b5_stc_l2hit_c7; |
| 3318 | |
| 3319 | b5_l2_ctrue_c4 <= b5_l2_ctrue_c3; |
| 3320 | b5_l2_ctrue_c5 <= b5_l2_ctrue_c4; |
| 3321 | b5_l2_ctrue_c52 <= b5_l2_ctrue_c5; |
| 3322 | b5_l2_ctrue_c6 <= b5_l2_ctrue_c52; |
| 3323 | b5_l2_ctrue_c7 <= b5_l2_ctrue_c6; |
| 3324 | b5_l2_ctrue_c8 <= b5_l2_ctrue_c7; |
| 3325 | |
| 3326 | `endif |
| 3327 | `endif |
| 3328 | |
| 3329 | //---------------------------------------------------------- |
| 3330 | //---------------------------------------------------------- |
| 3331 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 3332 | |
| 3333 | `ifdef NO_L2_BNK5 |
| 3334 | `else |
| 3335 | |
| 3336 | //------------------------------ |
| 3337 | // L2 Stub or L2 RTL Bank5 |
| 3338 | |
| 3339 | if (b5_load_data_miss && !b5_ldd_suppress) begin // { |
| 3340 | |
| 3341 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b5_cpx_tnum]) begin // { |
| 3342 | if (`PARGS.hash_on && (b5_cpx_pa[39]==1'b0)) begin // { |
| 3343 | `PR_INFO ("pli_ldst", `INFO, |
| 3344 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3345 | b5_cpx_cid,b5_cpx_tid,b5_cpx_tnum,`TOP.hashpa(b5_cpx_pa),dsrc,tstamp); |
| 3346 | junk = $sim_send(`PLI_MEM_LD_DATA,b5_cpx_tnum,`TOP.hashpa(b5_cpx_pa),dsrc,tstamp); |
| 3347 | end // } |
| 3348 | else begin //{ |
| 3349 | `PR_INFO ("pli_ldst", `INFO, |
| 3350 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3351 | b5_cpx_cid,b5_cpx_tid,b5_cpx_tnum,b5_cpx_pa,dsrc,tstamp); |
| 3352 | junk = $sim_send(`PLI_MEM_LD_DATA,b5_cpx_tnum,b5_cpx_pa,dsrc,tstamp); |
| 3353 | end // } |
| 3354 | end // } |
| 3355 | end // } |
| 3356 | else if (b5_load_data_miss && b5_ldd_suppress) begin // { |
| 3357 | `PR_INFO ("pli_ldst", `INFO, |
| 3358 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b5_cpx_cid,b5_cpx_tid,b5_cpx_tnum,b5_cpx_pa); |
| 3359 | |
| 3360 | end // } |
| 3361 | |
| 3362 | //---------------------------------------------------------- |
| 3363 | //---------------------------------------------------------- |
| 3364 | // Store L2 Commit |
| 3365 | |
| 3366 | //------------------------------ |
| 3367 | // L2 Stub or L2 RTL Bank5 |
| 3368 | |
| 3369 | if (b5_store_commit && !b5_stc_suppress) begin // { |
| 3370 | |
| 3371 | b5_stc_vect = get_vect (b5_stc_inv_vect); |
| 3372 | |
| 3373 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b5_cpx_tnum]) begin // { |
| 3374 | if (`PARGS.hash_on && (b5_cpx_pa[39]==1'b0)) begin // { |
| 3375 | `PR_INFO ("pli_ldst", `INFO, |
| 3376 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3377 | b5_cpx_cid,b5_cpx_tid,b5_cpx_tnum,`TOP.hashpa(b5_cpx_pa), |
| 3378 | b5_stc_size,b5_stc_vect,b5_stc_l2hit,tstamp); |
| 3379 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b5_cpx_tnum,`TOP.hashpa(b5_cpx_pa), |
| 3380 | b5_stc_size,b5_stc_vect,b5_stc_l2hit,tstamp); |
| 3381 | end // } |
| 3382 | else begin //{ |
| 3383 | `PR_INFO ("pli_ldst", `INFO, |
| 3384 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3385 | b5_cpx_cid,b5_cpx_tid,b5_cpx_tnum,b5_cpx_pa, |
| 3386 | b5_stc_size,b5_stc_vect,b5_stc_l2hit,tstamp); |
| 3387 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b5_cpx_tnum,b5_cpx_pa, |
| 3388 | b5_stc_size,b5_stc_vect,b5_stc_l2hit,tstamp); |
| 3389 | end // } |
| 3390 | end // } |
| 3391 | |
| 3392 | end // } |
| 3393 | else if (b5_store_commit && b5_stc_suppress) begin // { |
| 3394 | `PR_INFO ("pli_ldst", `INFO, |
| 3395 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b5_cpx_cid,b5_cpx_tid,b5_cpx_tnum,b5_cpx_pa); |
| 3396 | |
| 3397 | end // } |
| 3398 | |
| 3399 | //---------------------------------------------------------- |
| 3400 | //---------------------------------------------------------- |
| 3401 | // Evict |
| 3402 | // Note - NCU (bnk8 cannot send evictions) |
| 3403 | |
| 3404 | //------------------------------ |
| 3405 | // L2 Stub or L2 RTL Bank5 |
| 3406 | |
| 3407 | if (b5_evict) begin // { |
| 3408 | |
| 3409 | b5_ev_vect0 = b5_ev_invvect[31:0]; |
| 3410 | b5_ev_vect1 = b5_ev_invvect[55:32]; |
| 3411 | b5_ev_vect2 = b5_ev_invvect[87:56]; |
| 3412 | b5_ev_vect3 = b5_ev_invvect[111:88]; |
| 3413 | |
| 3414 | b5_inv_vect[0] = get_vect(b5_ev_vect0); |
| 3415 | b5_inv_vect[1] = get_vect31(b5_ev_vect1); // different function for odd inval vector |
| 3416 | b5_inv_vect[2] = get_vect(b5_ev_vect2); |
| 3417 | b5_inv_vect[3] = get_vect31(b5_ev_vect3); // different function for odd inval vector |
| 3418 | |
| 3419 | for (i=0; i<=3; i=i+1) begin // { |
| 3420 | |
| 3421 | b5_pa54 = i; |
| 3422 | b5_evict_pa = {b5_ev_pa[39:6],b5_pa54,4'b0}; |
| 3423 | b5_evict_inv_vect = b5_inv_vect[i]; |
| 3424 | |
| 3425 | if (b5_inv_vect[i]!=0) begin // { |
| 3426 | |
| 3427 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 3428 | if (`PARGS.hash_on && (b5_evict_pa[39]==1'b0)) begin // { |
| 3429 | `PR_INFO ("pli_ldst", `INFO, |
| 3430 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3431 | `TOP.hashpa(b5_evict_pa),b5_evict_inv_vect,tstamp); |
| 3432 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b5_evict_pa),b5_evict_inv_vect,tstamp); |
| 3433 | end // } |
| 3434 | else begin //{ |
| 3435 | `PR_INFO ("pli_ldst", `INFO, |
| 3436 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3437 | b5_evict_pa,b5_evict_inv_vect,tstamp); |
| 3438 | junk = $sim_send(`PLI_MEM_EVICT,b5_evict_pa,b5_evict_inv_vect,tstamp); |
| 3439 | end // if} |
| 3440 | end // if} |
| 3441 | |
| 3442 | if (`PARGS.show_memop_on) begin // { |
| 3443 | if (`PARGS.hash_on && (b5_evict_pa[39]==1'b0)) begin // { |
| 3444 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3445 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3446 | `TOP.hashpa(b5_evict_pa),tstamp); |
| 3447 | end // } |
| 3448 | else begin //{ |
| 3449 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3450 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3451 | b5_evict_pa,tstamp); |
| 3452 | end // } |
| 3453 | end // } |
| 3454 | |
| 3455 | end // if} |
| 3456 | end // for} |
| 3457 | |
| 3458 | end // } |
| 3459 | |
| 3460 | |
| 3461 | `endif |
| 3462 | |
| 3463 | end // always} |
| 3464 | |
| 3465 | //========================================================== |
| 3466 | // Bank6 |
| 3467 | |
| 3468 | always @ (posedge `BENCH_L2T6_GCLK) begin // { |
| 3469 | |
| 3470 | tstamp = `TOP.core_cycle_cnt - 1; |
| 3471 | |
| 3472 | //------------------------------ |
| 3473 | // Pipeline signals |
| 3474 | |
| 3475 | `ifdef NO_L2_BNK6 |
| 3476 | `else |
| 3477 | `ifdef NOL2RTL |
| 3478 | `else |
| 3479 | |
| 3480 | //------------------------------ |
| 3481 | // L2 RTL Bank6 |
| 3482 | |
| 3483 | b6_pa_c9 <= b6_pa_c8; |
| 3484 | b6_cpx_cid_c9 <= b6_cpx_cid_c8; |
| 3485 | b6_req_c7 <= b6_req_c6; |
| 3486 | b6_req_c8 <= b6_req_c7; |
| 3487 | |
| 3488 | b6_cam_pa_match_c2 <= b6_cam_pa_match_c1; |
| 3489 | b6_cam_pa_match_c3 <= b6_cam_pa_match_c2; |
| 3490 | |
| 3491 | b6_stall_c2 <= b6_stall_c1; |
| 3492 | b6_stall_c3 <= b6_stall_c2; |
| 3493 | b6_stall_c4 <= b6_stall_c3; |
| 3494 | b6_stall_c5 <= b6_stall_c4; |
| 3495 | b6_stall_c52 <= b6_stall_c5; |
| 3496 | b6_stall_c6 <= b6_stall_c52; |
| 3497 | b6_stall_c7 <= b6_stall_c6; |
| 3498 | b6_stall_c8 <= b6_stall_c7; |
| 3499 | b6_stall_c9 <= b6_stall_c8; |
| 3500 | |
| 3501 | b6_ev_pa_c5 <= b6_ev_pa_c4; |
| 3502 | b6_ev_pa_c52 <= b6_ev_pa_c5; |
| 3503 | b6_ev_pa_c6 <= b6_ev_pa_c52; |
| 3504 | b6_ev_pa_c7 <= b6_ev_pa_c6; |
| 3505 | b6_ev_pa_c8 <= b6_ev_pa_c7; |
| 3506 | |
| 3507 | b6_stc_l2hit_c4 <= b6_stc_l2hit_c3; |
| 3508 | b6_stc_l2hit_c5 <= b6_stc_l2hit_c4; |
| 3509 | b6_stc_l2hit_c52 <= b6_stc_l2hit_c5; |
| 3510 | b6_stc_l2hit_c6 <= b6_stc_l2hit_c52; |
| 3511 | b6_stc_l2hit_c7 <= b6_stc_l2hit_c6; |
| 3512 | b6_stc_l2hit_c8 <= b6_stc_l2hit_c7; |
| 3513 | |
| 3514 | b6_l2_ctrue_c4 <= b6_l2_ctrue_c3; |
| 3515 | b6_l2_ctrue_c5 <= b6_l2_ctrue_c4; |
| 3516 | b6_l2_ctrue_c52 <= b6_l2_ctrue_c5; |
| 3517 | b6_l2_ctrue_c6 <= b6_l2_ctrue_c52; |
| 3518 | b6_l2_ctrue_c7 <= b6_l2_ctrue_c6; |
| 3519 | b6_l2_ctrue_c8 <= b6_l2_ctrue_c7; |
| 3520 | |
| 3521 | `endif |
| 3522 | `endif |
| 3523 | |
| 3524 | //---------------------------------------------------------- |
| 3525 | //---------------------------------------------------------- |
| 3526 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 3527 | |
| 3528 | `ifdef NO_L2_BNK6 |
| 3529 | `else |
| 3530 | |
| 3531 | //------------------------------ |
| 3532 | // L2 Stub or L2 RTL Bank6 |
| 3533 | |
| 3534 | if (b6_load_data_miss && !b6_ldd_suppress) begin // { |
| 3535 | |
| 3536 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b6_cpx_tnum]) begin // { |
| 3537 | if (`PARGS.hash_on && (b6_cpx_pa[39]==1'b0)) begin // { |
| 3538 | `PR_INFO ("pli_ldst", `INFO, |
| 3539 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3540 | b6_cpx_cid,b6_cpx_tid,b6_cpx_tnum,`TOP.hashpa(b6_cpx_pa),dsrc,tstamp); |
| 3541 | junk = $sim_send(`PLI_MEM_LD_DATA,b6_cpx_tnum,`TOP.hashpa(b6_cpx_pa),dsrc,tstamp); |
| 3542 | end // } |
| 3543 | else begin //{ |
| 3544 | `PR_INFO ("pli_ldst", `INFO, |
| 3545 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3546 | b6_cpx_cid,b6_cpx_tid,b6_cpx_tnum,b6_cpx_pa,dsrc,tstamp); |
| 3547 | junk = $sim_send(`PLI_MEM_LD_DATA,b6_cpx_tnum,b6_cpx_pa,dsrc,tstamp); |
| 3548 | end // } |
| 3549 | end // } |
| 3550 | end // } |
| 3551 | else if (b6_load_data_miss && b6_ldd_suppress) begin // { |
| 3552 | `PR_INFO ("pli_ldst", `INFO, |
| 3553 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b6_cpx_cid,b6_cpx_tid,b6_cpx_tnum,b6_cpx_pa); |
| 3554 | |
| 3555 | end // } |
| 3556 | |
| 3557 | //---------------------------------------------------------- |
| 3558 | //---------------------------------------------------------- |
| 3559 | // Store L2 Commit |
| 3560 | |
| 3561 | //------------------------------ |
| 3562 | // L2 Stub or L2 RTL Bank6 |
| 3563 | |
| 3564 | if (b6_store_commit && !b6_stc_suppress) begin // { |
| 3565 | |
| 3566 | b6_stc_vect = get_vect (b6_stc_inv_vect); |
| 3567 | |
| 3568 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b6_cpx_tnum]) begin // { |
| 3569 | if (`PARGS.hash_on && (b6_cpx_pa[39]==1'b0)) begin // { |
| 3570 | `PR_INFO ("pli_ldst", `INFO, |
| 3571 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3572 | b6_cpx_cid,b6_cpx_tid,b6_cpx_tnum,`TOP.hashpa(b6_cpx_pa), |
| 3573 | b6_stc_size,b6_stc_vect,b6_stc_l2hit,tstamp); |
| 3574 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b6_cpx_tnum,`TOP.hashpa(b6_cpx_pa), |
| 3575 | b6_stc_size,b6_stc_vect,b6_stc_l2hit,tstamp); |
| 3576 | end // } |
| 3577 | else begin //{ |
| 3578 | `PR_INFO ("pli_ldst", `INFO, |
| 3579 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3580 | b6_cpx_cid,b6_cpx_tid,b6_cpx_tnum,b6_cpx_pa, |
| 3581 | b6_stc_size,b6_stc_vect,b6_stc_l2hit,tstamp); |
| 3582 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b6_cpx_tnum,b6_cpx_pa, |
| 3583 | b6_stc_size,b6_stc_vect,b6_stc_l2hit,tstamp); |
| 3584 | end // } |
| 3585 | end // } |
| 3586 | |
| 3587 | end // } |
| 3588 | else if (b6_store_commit && b6_stc_suppress) begin // { |
| 3589 | `PR_INFO ("pli_ldst", `INFO, |
| 3590 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b6_cpx_cid,b6_cpx_tid,b6_cpx_tnum,b6_cpx_pa); |
| 3591 | |
| 3592 | end // } |
| 3593 | |
| 3594 | //---------------------------------------------------------- |
| 3595 | //---------------------------------------------------------- |
| 3596 | // Evict |
| 3597 | // Note - NCU (bnk8 cannot send evictions) |
| 3598 | |
| 3599 | //------------------------------ |
| 3600 | // L2 Stub or L2 RTL Bank6 |
| 3601 | |
| 3602 | if (b6_evict) begin // { |
| 3603 | |
| 3604 | b6_ev_vect0 = b6_ev_invvect[31:0]; |
| 3605 | b6_ev_vect1 = b6_ev_invvect[55:32]; |
| 3606 | b6_ev_vect2 = b6_ev_invvect[87:56]; |
| 3607 | b6_ev_vect3 = b6_ev_invvect[111:88]; |
| 3608 | |
| 3609 | b6_inv_vect[0] = get_vect(b6_ev_vect0); |
| 3610 | b6_inv_vect[1] = get_vect31(b6_ev_vect1); // different function for odd inval vector |
| 3611 | b6_inv_vect[2] = get_vect(b6_ev_vect2); |
| 3612 | b6_inv_vect[3] = get_vect31(b6_ev_vect3); // different function for odd inval vector |
| 3613 | |
| 3614 | for (i=0; i<=3; i=i+1) begin // { |
| 3615 | |
| 3616 | b6_pa54 = i; |
| 3617 | b6_evict_pa = {b6_ev_pa[39:6],b6_pa54,4'b0}; |
| 3618 | b6_evict_inv_vect = b6_inv_vect[i]; |
| 3619 | |
| 3620 | if (b6_inv_vect[i]!=0) begin // { |
| 3621 | |
| 3622 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 3623 | if (`PARGS.hash_on && (b6_evict_pa[39]==1'b0)) begin // { |
| 3624 | `PR_INFO ("pli_ldst", `INFO, |
| 3625 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3626 | `TOP.hashpa(b6_evict_pa),b6_evict_inv_vect,tstamp); |
| 3627 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b6_evict_pa),b6_evict_inv_vect,tstamp); |
| 3628 | end // } |
| 3629 | else begin //{ |
| 3630 | `PR_INFO ("pli_ldst", `INFO, |
| 3631 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3632 | b6_evict_pa,b6_evict_inv_vect,tstamp); |
| 3633 | junk = $sim_send(`PLI_MEM_EVICT,b6_evict_pa,b6_evict_inv_vect,tstamp); |
| 3634 | end // if} |
| 3635 | end // if} |
| 3636 | |
| 3637 | if (`PARGS.show_memop_on) begin // { |
| 3638 | if (`PARGS.hash_on && (b6_evict_pa[39]==1'b0)) begin // { |
| 3639 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3640 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3641 | `TOP.hashpa(b6_evict_pa),tstamp); |
| 3642 | end // } |
| 3643 | else begin //{ |
| 3644 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3645 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3646 | b6_evict_pa,tstamp); |
| 3647 | end // } |
| 3648 | end // } |
| 3649 | |
| 3650 | end // if} |
| 3651 | end // for} |
| 3652 | |
| 3653 | end // } |
| 3654 | |
| 3655 | |
| 3656 | `endif |
| 3657 | |
| 3658 | end // always} |
| 3659 | |
| 3660 | //========================================================== |
| 3661 | // Bank7 |
| 3662 | |
| 3663 | always @ (posedge `BENCH_L2T7_GCLK) begin // { |
| 3664 | |
| 3665 | tstamp = `TOP.core_cycle_cnt - 1; |
| 3666 | |
| 3667 | //------------------------------ |
| 3668 | // Pipeline signals |
| 3669 | |
| 3670 | `ifdef NO_L2_BNK7 |
| 3671 | `else |
| 3672 | `ifdef NOL2RTL |
| 3673 | `else |
| 3674 | |
| 3675 | //------------------------------ |
| 3676 | // L2 RTL Bank7 |
| 3677 | |
| 3678 | b7_pa_c9 <= b7_pa_c8; |
| 3679 | b7_cpx_cid_c9 <= b7_cpx_cid_c8; |
| 3680 | b7_req_c7 <= b7_req_c6; |
| 3681 | b7_req_c8 <= b7_req_c7; |
| 3682 | |
| 3683 | b7_cam_pa_match_c2 <= b7_cam_pa_match_c1; |
| 3684 | b7_cam_pa_match_c3 <= b7_cam_pa_match_c2; |
| 3685 | |
| 3686 | b7_stall_c2 <= b7_stall_c1; |
| 3687 | b7_stall_c3 <= b7_stall_c2; |
| 3688 | b7_stall_c4 <= b7_stall_c3; |
| 3689 | b7_stall_c5 <= b7_stall_c4; |
| 3690 | b7_stall_c52 <= b7_stall_c5; |
| 3691 | b7_stall_c6 <= b7_stall_c52; |
| 3692 | b7_stall_c7 <= b7_stall_c6; |
| 3693 | b7_stall_c8 <= b7_stall_c7; |
| 3694 | b7_stall_c9 <= b7_stall_c8; |
| 3695 | |
| 3696 | b7_ev_pa_c5 <= b7_ev_pa_c4; |
| 3697 | b7_ev_pa_c52 <= b7_ev_pa_c5; |
| 3698 | b7_ev_pa_c6 <= b7_ev_pa_c52; |
| 3699 | b7_ev_pa_c7 <= b7_ev_pa_c6; |
| 3700 | b7_ev_pa_c8 <= b7_ev_pa_c7; |
| 3701 | |
| 3702 | b7_stc_l2hit_c4 <= b7_stc_l2hit_c3; |
| 3703 | b7_stc_l2hit_c5 <= b7_stc_l2hit_c4; |
| 3704 | b7_stc_l2hit_c52 <= b7_stc_l2hit_c5; |
| 3705 | b7_stc_l2hit_c6 <= b7_stc_l2hit_c52; |
| 3706 | b7_stc_l2hit_c7 <= b7_stc_l2hit_c6; |
| 3707 | b7_stc_l2hit_c8 <= b7_stc_l2hit_c7; |
| 3708 | |
| 3709 | b7_l2_ctrue_c4 <= b7_l2_ctrue_c3; |
| 3710 | b7_l2_ctrue_c5 <= b7_l2_ctrue_c4; |
| 3711 | b7_l2_ctrue_c52 <= b7_l2_ctrue_c5; |
| 3712 | b7_l2_ctrue_c6 <= b7_l2_ctrue_c52; |
| 3713 | b7_l2_ctrue_c7 <= b7_l2_ctrue_c6; |
| 3714 | b7_l2_ctrue_c8 <= b7_l2_ctrue_c7; |
| 3715 | |
| 3716 | `endif |
| 3717 | `endif |
| 3718 | |
| 3719 | //---------------------------------------------------------- |
| 3720 | //---------------------------------------------------------- |
| 3721 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 3722 | |
| 3723 | `ifdef NO_L2_BNK7 |
| 3724 | `else |
| 3725 | |
| 3726 | //------------------------------ |
| 3727 | // L2 Stub or L2 RTL Bank7 |
| 3728 | |
| 3729 | if (b7_load_data_miss && !b7_ldd_suppress) begin // { |
| 3730 | |
| 3731 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b7_cpx_tnum]) begin // { |
| 3732 | if (`PARGS.hash_on && (b7_cpx_pa[39]==1'b0)) begin // { |
| 3733 | `PR_INFO ("pli_ldst", `INFO, |
| 3734 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3735 | b7_cpx_cid,b7_cpx_tid,b7_cpx_tnum,`TOP.hashpa(b7_cpx_pa),dsrc,tstamp); |
| 3736 | junk = $sim_send(`PLI_MEM_LD_DATA,b7_cpx_tnum,`TOP.hashpa(b7_cpx_pa),dsrc,tstamp); |
| 3737 | end // } |
| 3738 | else begin //{ |
| 3739 | `PR_INFO ("pli_ldst", `INFO, |
| 3740 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3741 | b7_cpx_cid,b7_cpx_tid,b7_cpx_tnum,b7_cpx_pa,dsrc,tstamp); |
| 3742 | junk = $sim_send(`PLI_MEM_LD_DATA,b7_cpx_tnum,b7_cpx_pa,dsrc,tstamp); |
| 3743 | end // } |
| 3744 | end // } |
| 3745 | end // } |
| 3746 | else if (b7_load_data_miss && b7_ldd_suppress) begin // { |
| 3747 | `PR_INFO ("pli_ldst", `INFO, |
| 3748 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b7_cpx_cid,b7_cpx_tid,b7_cpx_tnum,b7_cpx_pa); |
| 3749 | |
| 3750 | end // } |
| 3751 | |
| 3752 | //---------------------------------------------------------- |
| 3753 | //---------------------------------------------------------- |
| 3754 | // Store L2 Commit |
| 3755 | |
| 3756 | //------------------------------ |
| 3757 | // L2 Stub or L2 RTL Bank7 |
| 3758 | |
| 3759 | if (b7_store_commit && !b7_stc_suppress) begin // { |
| 3760 | |
| 3761 | b7_stc_vect = get_vect (b7_stc_inv_vect); |
| 3762 | |
| 3763 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b7_cpx_tnum]) begin // { |
| 3764 | if (`PARGS.hash_on && (b7_cpx_pa[39]==1'b0)) begin // { |
| 3765 | `PR_INFO ("pli_ldst", `INFO, |
| 3766 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3767 | b7_cpx_cid,b7_cpx_tid,b7_cpx_tnum,`TOP.hashpa(b7_cpx_pa), |
| 3768 | b7_stc_size,b7_stc_vect,b7_stc_l2hit,tstamp); |
| 3769 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b7_cpx_tnum,`TOP.hashpa(b7_cpx_pa), |
| 3770 | b7_stc_size,b7_stc_vect,b7_stc_l2hit,tstamp); |
| 3771 | end // } |
| 3772 | else begin //{ |
| 3773 | `PR_INFO ("pli_ldst", `INFO, |
| 3774 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3775 | b7_cpx_cid,b7_cpx_tid,b7_cpx_tnum,b7_cpx_pa, |
| 3776 | b7_stc_size,b7_stc_vect,b7_stc_l2hit,tstamp); |
| 3777 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b7_cpx_tnum,b7_cpx_pa, |
| 3778 | b7_stc_size,b7_stc_vect,b7_stc_l2hit,tstamp); |
| 3779 | end // } |
| 3780 | end // } |
| 3781 | |
| 3782 | end // } |
| 3783 | else if (b7_store_commit && b7_stc_suppress) begin // { |
| 3784 | `PR_INFO ("pli_ldst", `INFO, |
| 3785 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b7_cpx_cid,b7_cpx_tid,b7_cpx_tnum,b7_cpx_pa); |
| 3786 | |
| 3787 | end // } |
| 3788 | |
| 3789 | //---------------------------------------------------------- |
| 3790 | //---------------------------------------------------------- |
| 3791 | // Evict |
| 3792 | // Note - NCU (bnk8 cannot send evictions) |
| 3793 | |
| 3794 | //------------------------------ |
| 3795 | // L2 Stub or L2 RTL Bank7 |
| 3796 | |
| 3797 | if (b7_evict) begin // { |
| 3798 | |
| 3799 | b7_ev_vect0 = b7_ev_invvect[31:0]; |
| 3800 | b7_ev_vect1 = b7_ev_invvect[55:32]; |
| 3801 | b7_ev_vect2 = b7_ev_invvect[87:56]; |
| 3802 | b7_ev_vect3 = b7_ev_invvect[111:88]; |
| 3803 | |
| 3804 | b7_inv_vect[0] = get_vect(b7_ev_vect0); |
| 3805 | b7_inv_vect[1] = get_vect31(b7_ev_vect1); // different function for odd inval vector |
| 3806 | b7_inv_vect[2] = get_vect(b7_ev_vect2); |
| 3807 | b7_inv_vect[3] = get_vect31(b7_ev_vect3); // different function for odd inval vector |
| 3808 | |
| 3809 | for (i=0; i<=3; i=i+1) begin // { |
| 3810 | |
| 3811 | b7_pa54 = i; |
| 3812 | b7_evict_pa = {b7_ev_pa[39:6],b7_pa54,4'b0}; |
| 3813 | b7_evict_inv_vect = b7_inv_vect[i]; |
| 3814 | |
| 3815 | if (b7_inv_vect[i]!=0) begin // { |
| 3816 | |
| 3817 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 3818 | if (`PARGS.hash_on && (b7_evict_pa[39]==1'b0)) begin // { |
| 3819 | `PR_INFO ("pli_ldst", `INFO, |
| 3820 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3821 | `TOP.hashpa(b7_evict_pa),b7_evict_inv_vect,tstamp); |
| 3822 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b7_evict_pa),b7_evict_inv_vect,tstamp); |
| 3823 | end // } |
| 3824 | else begin //{ |
| 3825 | `PR_INFO ("pli_ldst", `INFO, |
| 3826 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3827 | b7_evict_pa,b7_evict_inv_vect,tstamp); |
| 3828 | junk = $sim_send(`PLI_MEM_EVICT,b7_evict_pa,b7_evict_inv_vect,tstamp); |
| 3829 | end // if} |
| 3830 | end // if} |
| 3831 | |
| 3832 | if (`PARGS.show_memop_on) begin // { |
| 3833 | if (`PARGS.hash_on && (b7_evict_pa[39]==1'b0)) begin // { |
| 3834 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3835 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3836 | `TOP.hashpa(b7_evict_pa),tstamp); |
| 3837 | end // } |
| 3838 | else begin //{ |
| 3839 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3840 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3841 | b7_evict_pa,tstamp); |
| 3842 | end // } |
| 3843 | end // } |
| 3844 | |
| 3845 | end // if} |
| 3846 | end // for} |
| 3847 | |
| 3848 | end // } |
| 3849 | |
| 3850 | |
| 3851 | `endif |
| 3852 | |
| 3853 | end // always} |
| 3854 | |
| 3855 | //========================================================== |
| 3856 | // Bank8 |
| 3857 | |
| 3858 | always @ (posedge `BENCH_NCU_GCLK) begin // { |
| 3859 | |
| 3860 | tstamp = `TOP.core_cycle_cnt - 1; |
| 3861 | |
| 3862 | //---------------------------------------------------------- |
| 3863 | //---------------------------------------------------------- |
| 3864 | // Load Data (miss only) (See ldst_lsu.v for Load Data - hit) |
| 3865 | |
| 3866 | `ifdef NO_L2_BNK8 |
| 3867 | `else |
| 3868 | |
| 3869 | //------------------------------ |
| 3870 | // L2 Stub or L2 RTL Bank8 |
| 3871 | |
| 3872 | if (b8_load_data_miss && !b8_ldd_suppress) begin // { |
| 3873 | |
| 3874 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b8_cpx_tnum]) begin // { |
| 3875 | if (`PARGS.hash_on && (b8_cpx_pa[39]==1'b0)) begin // { |
| 3876 | `PR_INFO ("pli_ldst", `INFO, |
| 3877 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3878 | b8_cpx_cid,b8_cpx_tid,b8_cpx_tnum,`TOP.hashpa(b8_cpx_pa),dsrc,tstamp); |
| 3879 | junk = $sim_send(`PLI_MEM_LD_DATA,b8_cpx_tnum,`TOP.hashpa(b8_cpx_pa),dsrc,tstamp); |
| 3880 | end // } |
| 3881 | else begin //{ |
| 3882 | `PR_INFO ("pli_ldst", `INFO, |
| 3883 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h dsrc=%0h ts=%0d", |
| 3884 | b8_cpx_cid,b8_cpx_tid,b8_cpx_tnum,b8_cpx_pa,dsrc,tstamp); |
| 3885 | junk = $sim_send(`PLI_MEM_LD_DATA,b8_cpx_tnum,b8_cpx_pa,dsrc,tstamp); |
| 3886 | end // } |
| 3887 | end // } |
| 3888 | end // } |
| 3889 | else if (b8_load_data_miss && b8_ldd_suppress) begin // { |
| 3890 | `PR_INFO ("pli_ldst", `INFO, |
| 3891 | "C%0d T%0d PLI_MEM_LDDATA tid=%d pa=%h Suppress for IO ASI",b8_cpx_cid,b8_cpx_tid,b8_cpx_tnum,b8_cpx_pa); |
| 3892 | |
| 3893 | end // } |
| 3894 | |
| 3895 | //---------------------------------------------------------- |
| 3896 | //---------------------------------------------------------- |
| 3897 | // Store L2 Commit |
| 3898 | |
| 3899 | //------------------------------ |
| 3900 | // L2 Stub or L2 RTL Bank8 |
| 3901 | |
| 3902 | if (b8_store_commit && !b8_stc_suppress) begin // { |
| 3903 | |
| 3904 | b8_stc_vect = get_vect (b8_stc_inv_vect); |
| 3905 | |
| 3906 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on && `PARGS.th_check_enable[b8_cpx_tnum]) begin // { |
| 3907 | if (`PARGS.hash_on && (b8_cpx_pa[39]==1'b0)) begin // { |
| 3908 | `PR_INFO ("pli_ldst", `INFO, |
| 3909 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3910 | b8_cpx_cid,b8_cpx_tid,b8_cpx_tnum,`TOP.hashpa(b8_cpx_pa), |
| 3911 | b8_stc_size,b8_stc_vect,b8_stc_l2hit,tstamp); |
| 3912 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b8_cpx_tnum,`TOP.hashpa(b8_cpx_pa), |
| 3913 | b8_stc_size,b8_stc_vect,b8_stc_l2hit,tstamp); |
| 3914 | end // } |
| 3915 | else begin //{ |
| 3916 | `PR_INFO ("pli_ldst", `INFO, |
| 3917 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h sz=%h ivect=%h l2hit=%0d ts=%0d", |
| 3918 | b8_cpx_cid,b8_cpx_tid,b8_cpx_tnum,b8_cpx_pa, |
| 3919 | b8_stc_size,b8_stc_vect,b8_stc_l2hit,tstamp); |
| 3920 | junk = $sim_send(`PLI_MEM_ST_L2_COMMIT,b8_cpx_tnum,b8_cpx_pa, |
| 3921 | b8_stc_size,b8_stc_vect,b8_stc_l2hit,tstamp); |
| 3922 | end // } |
| 3923 | end // } |
| 3924 | |
| 3925 | end // } |
| 3926 | else if (b8_store_commit && b8_stc_suppress) begin // { |
| 3927 | `PR_INFO ("pli_ldst", `INFO, |
| 3928 | "C%0d T%0d PLI_MEM_STCOM tid=%d pa=%h Suppress for IO ASI",b8_cpx_cid,b8_cpx_tid,b8_cpx_tnum,b8_cpx_pa); |
| 3929 | |
| 3930 | end // } |
| 3931 | |
| 3932 | //---------------------------------------------------------- |
| 3933 | //---------------------------------------------------------- |
| 3934 | // Evict |
| 3935 | // Note - NCU (bnk8 cannot send evictions) |
| 3936 | |
| 3937 | //------------------------------ |
| 3938 | // L2 Stub or L2 RTL Bank8 |
| 3939 | |
| 3940 | if (b8_evict) begin // { |
| 3941 | |
| 3942 | b8_ev_vect0 = b8_ev_invvect[31:0]; |
| 3943 | b8_ev_vect1 = b8_ev_invvect[55:32]; |
| 3944 | b8_ev_vect2 = b8_ev_invvect[87:56]; |
| 3945 | b8_ev_vect3 = b8_ev_invvect[111:88]; |
| 3946 | |
| 3947 | b8_inv_vect[0] = get_vect(b8_ev_vect0); |
| 3948 | b8_inv_vect[1] = get_vect31(b8_ev_vect1); // different function for odd inval vector |
| 3949 | b8_inv_vect[2] = get_vect(b8_ev_vect2); |
| 3950 | b8_inv_vect[3] = get_vect31(b8_ev_vect3); // different function for odd inval vector |
| 3951 | |
| 3952 | for (i=0; i<=3; i=i+1) begin // { |
| 3953 | |
| 3954 | b8_pa54 = i; |
| 3955 | b8_evict_pa = {b8_ev_pa[39:6],b8_pa54,4'b0}; |
| 3956 | b8_evict_inv_vect = b8_inv_vect[i]; |
| 3957 | |
| 3958 | if (b8_inv_vect[i]!=0) begin // { |
| 3959 | |
| 3960 | if (`PARGS.nas_check_on && `PARGS.ldst_sync_on) begin // { |
| 3961 | if (`PARGS.hash_on && (b8_evict_pa[39]==1'b0)) begin // { |
| 3962 | `PR_INFO ("pli_ldst", `INFO, |
| 3963 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3964 | `TOP.hashpa(b8_evict_pa),b8_evict_inv_vect,tstamp); |
| 3965 | junk = $sim_send(`PLI_MEM_EVICT,`TOP.hashpa(b8_evict_pa),b8_evict_inv_vect,tstamp); |
| 3966 | end // } |
| 3967 | else begin //{ |
| 3968 | `PR_INFO ("pli_ldst", `INFO, |
| 3969 | " PLI_MEM_EVICT pa=%h ivect=%h ts=%0d", |
| 3970 | b8_evict_pa,b8_evict_inv_vect,tstamp); |
| 3971 | junk = $sim_send(`PLI_MEM_EVICT,b8_evict_pa,b8_evict_inv_vect,tstamp); |
| 3972 | end // if} |
| 3973 | end // if} |
| 3974 | |
| 3975 | if (`PARGS.show_memop_on) begin // { |
| 3976 | if (`PARGS.hash_on && (b8_evict_pa[39]==1'b0)) begin // { |
| 3977 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3978 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3979 | `TOP.hashpa(b8_evict_pa),tstamp); |
| 3980 | end // } |
| 3981 | else begin //{ |
| 3982 | `PR_NORMAL ("pli_ldst", `NORMAL, |
| 3983 | " MEMOP_EVICT pa=%h ts=%0d (L2 - c8 stage)", |
| 3984 | b8_evict_pa,tstamp); |
| 3985 | end // } |
| 3986 | end // } |
| 3987 | |
| 3988 | end // if} |
| 3989 | end // for} |
| 3990 | |
| 3991 | end // } |
| 3992 | |
| 3993 | |
| 3994 | `endif |
| 3995 | |
| 3996 | end // always} |
| 3997 | |
| 3998 | //---------------------------------------------------------- |
| 3999 | // Return inv_vector (argument for PLI msg) from inval.vector in CPX response pkt |
| 4000 | function [31:0] get_vect; |
| 4001 | input [31:0] inv_vect; |
| 4002 | begin |
| 4003 | // Vector is 32 bits to support 32 cores (for future chips). N2 only has 8 cores. |
| 4004 | get_vect = {24'b0, |
| 4005 | (inv_vect[`CPX_D_INV7]==2'b10), |
| 4006 | (inv_vect[`CPX_D_INV6]==2'b10), |
| 4007 | (inv_vect[`CPX_D_INV5]==2'b10), |
| 4008 | (inv_vect[`CPX_D_INV4]==2'b10), |
| 4009 | (inv_vect[`CPX_D_INV3]==2'b10), |
| 4010 | (inv_vect[`CPX_D_INV2]==2'b10), |
| 4011 | (inv_vect[`CPX_D_INV1]==2'b10), |
| 4012 | (inv_vect[`CPX_D_INV0]==2'b10) |
| 4013 | }; |
| 4014 | end |
| 4015 | endfunction |
| 4016 | |
| 4017 | //---------------------------------------------------------- |
| 4018 | // Return inv_vector (argument for PLI msg) from inval.vector in CPX response pkt |
| 4019 | // Note: inval.vector addr[5:4]=3|1 from eviction invalidation pkt has different |
| 4020 | // format than addr[5:4]=2|0. |
| 4021 | function [31:0] get_vect31; |
| 4022 | input [23:0] inv_vect; |
| 4023 | begin |
| 4024 | // Vector is 32 bits to support 32 cores (for future chips). N2 only has 8 cores. |
| 4025 | get_vect31 = {24'b0, |
| 4026 | (inv_vect[`CPX_D_INV7_ALT]==1'b1), |
| 4027 | (inv_vect[`CPX_D_INV6_ALT]==1'b1), |
| 4028 | (inv_vect[`CPX_D_INV5_ALT]==1'b1), |
| 4029 | (inv_vect[`CPX_D_INV4_ALT]==1'b1), |
| 4030 | (inv_vect[`CPX_D_INV3_ALT]==1'b1), |
| 4031 | (inv_vect[`CPX_D_INV2_ALT]==1'b1), |
| 4032 | (inv_vect[`CPX_D_INV1_ALT]==1'b1), |
| 4033 | (inv_vect[`CPX_D_INV0_ALT]==1'b1) |
| 4034 | }; |
| 4035 | end |
| 4036 | endfunction |
| 4037 | |
| 4038 | |
| 4039 | //---------------------------------------------------------- |
| 4040 | `endif |
| 4041 | endmodule |
| 4042 | |
| 4043 | //---------------------------------------------------------- |
| 4044 | //---------------------------------------------------------- |