| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cmp_tasks.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `include "cmp.vri" |
| 36 | |
| 37 | // CMP registers // |
| 38 | |
| 39 | // RO. fuses in sets of 8, based on cores built into model. |
| 40 | reg [63:0] cmp_core_avail; |
| 41 | |
| 42 | // RO. done is sets of 8. always has 0's where cores are not avail. |
| 43 | // Takes value of cmp_core_enable at deassertion of warm reset (after POR). |
| 44 | reg [63:0] cmp_core_enable_status; |
| 45 | |
| 46 | // R/W. must be done in sets of 8. only effective after warm reset/POR. |
| 47 | // disable a core (make invisible). NOT PARKING. |
| 48 | // Logic must not allow all threads to be disabled. No self disable. |
| 49 | reg [63:0] cmp_core_enable; |
| 50 | |
| 51 | // R/W. will initially take the value of th_check_enable plusarg. |
| 52 | // After that, th_check_enable will follow the value of this reg *after* thread parks. |
| 53 | // Parks threads. Can not park self. No self parking. Any thread |
| 54 | // that is either not avail or is disabled, will also be forced parked. |
| 55 | // After sys reset, lowest enabled thread will always be unparked, others parked. |
| 56 | // This is done in Vera code. |
| 57 | reg [63:0] cmp_core_running_rw; |
| 58 | reg diag_change_core_running; |
| 59 | // Note: th_check_enable and cmp_core_running_rw are essentially the same. |
| 60 | |
| 61 | // RW. which threads get XIR. Any thread |
| 62 | // that is either not avail or is disabled, will also be forced off. |
| 63 | // Takes value of cmp_core_enable at deassertion of warm reset (after POR). |
| 64 | // Writes are to be 'anded' with cmp_cone_enable .. |
| 65 | reg [63:0] cmp_xir_steering; |
| 66 | |
| 67 | // RW. |
| 68 | reg ncu_cmp_tick_enable; |
| 69 | |
| 70 | // misc NCU registers imlemented in HW so they can drive the core |
| 71 | reg [63:0] asi_power_throttle; |
| 72 | reg asi_wmr_vec_mask; // preserve accross warm reset |
| 73 | reg asi_l2_idx_hash_en; |
| 74 | reg [63:0] asi_reset_stat; |
| 75 | |
| 76 | // DUT will drive high as needed. We read this wire as a register. |
| 77 | wire [63:0] cmp_core_running_status; |
| 78 | |
| 79 | // signal that an ASI was read (for Riesling) |
| 80 | reg asi_read_edge; |
| 81 | reg [25:0] asi_read_addr; |
| 82 | reg [63:0] asi_read_data; |
| 83 | reg [5:0] asi_read_tid; |
| 84 | |
| 85 | wire cmp_gclk_c3_spc0; |
| 86 | wire cmp_gclk_c3_spc1; |
| 87 | wire cmp_gclk_c3_spc2; |
| 88 | wire cmp_gclk_c3_spc3; |
| 89 | wire cmp_gclk_c3_spc4; |
| 90 | wire cmp_gclk_c3_spc5; |
| 91 | wire cmp_gclk_c3_spc6; |
| 92 | wire cmp_gclk_c3_spc7; |
| 93 | wire gl_spc0_clk_stop; |
| 94 | wire gl_spc1_clk_stop; |
| 95 | wire gl_spc2_clk_stop; |
| 96 | wire gl_spc3_clk_stop; |
| 97 | wire gl_spc4_clk_stop; |
| 98 | wire gl_spc5_clk_stop; |
| 99 | wire gl_spc6_clk_stop; |
| 100 | wire gl_spc7_clk_stop; |
| 101 | wire cmp_gclk_c2_ccx_left; |
| 102 | wire cmp_gclk_c2_ccx_right; |
| 103 | wire gl_ccx_clk_stop_left; |
| 104 | wire gl_ccx_clk_stop_right; |
| 105 | wire cmp_gclk_c3_l2d0; |
| 106 | wire cmp_gclk_c3_l2d1; |
| 107 | wire cmp_gclk_c3_l2d2; |
| 108 | wire cmp_gclk_c3_l2d3; |
| 109 | wire cmp_gclk_c3_l2d4; |
| 110 | wire cmp_gclk_c3_l2d5; |
| 111 | wire cmp_gclk_c3_l2d6; |
| 112 | wire cmp_gclk_c3_l2d7; |
| 113 | wire gl_l2d0_clk_stop; |
| 114 | wire gl_l2d1_clk_stop; |
| 115 | wire gl_l2d2_clk_stop; |
| 116 | wire gl_l2d3_clk_stop; |
| 117 | wire gl_l2d4_clk_stop; |
| 118 | wire gl_l2d5_clk_stop; |
| 119 | wire gl_l2d6_clk_stop; |
| 120 | wire gl_l2d7_clk_stop; |
| 121 | wire cmp_gclk_c3_l2t0; |
| 122 | wire cmp_gclk_c3_l2t1; |
| 123 | wire cmp_gclk_c3_l2t2; |
| 124 | wire cmp_gclk_c3_l2t3; |
| 125 | wire cmp_gclk_c3_l2t4; |
| 126 | wire cmp_gclk_c3_l2t5; |
| 127 | wire cmp_gclk_c3_l2t6; |
| 128 | wire cmp_gclk_c3_l2t7; |
| 129 | wire gl_l2t0_clk_stop; |
| 130 | wire gl_l2t1_clk_stop; |
| 131 | wire gl_l2t2_clk_stop; |
| 132 | wire gl_l2t3_clk_stop; |
| 133 | wire gl_l2t4_clk_stop; |
| 134 | wire gl_l2t5_clk_stop; |
| 135 | wire gl_l2t6_clk_stop; |
| 136 | wire gl_l2t7_clk_stop; |
| 137 | |
| 138 | |
| 139 | //---------------------------------------------------------- |
| 140 | // Initialize registers |
| 141 | initial |
| 142 | begin |
| 143 | |
| 144 | // do not init anything here that gets set by a +arg, do it in verif_args.v |
| 145 | asi_wmr_vec_mask = 0; // preserve accross warm reset |
| 146 | asi_l2_idx_hash_en = 0; |
| 147 | ncu_cmp_tick_enable = 1; |
| 148 | cmp_core_running_rw = 64'h0; |
| 149 | diag_change_core_running = 0; |
| 150 | cmp_core_avail = 64'h0; |
| 151 | cmp_core_enable = 64'h0; |
| 152 | asi_reset_stat = 4; |
| 153 | |
| 154 | `ifdef CORE_0 |
| 155 | cmp_core_avail = cmp_core_avail | 64'h00000000_000000ff; |
| 156 | cmp_core_enable = cmp_core_enable | 64'h00000000_000000ff; |
| 157 | `endif |
| 158 | |
| 159 | `ifdef CORE_1 |
| 160 | cmp_core_avail = cmp_core_avail | 64'h00000000_0000ff00; |
| 161 | cmp_core_enable = cmp_core_enable | 64'h00000000_0000ff00; |
| 162 | `endif |
| 163 | |
| 164 | `ifdef CORE_2 |
| 165 | cmp_core_avail = cmp_core_avail | 64'h00000000_00ff0000; |
| 166 | cmp_core_enable = cmp_core_enable | 64'h00000000_00ff0000; |
| 167 | `endif |
| 168 | |
| 169 | `ifdef CORE_3 |
| 170 | cmp_core_avail = cmp_core_avail | 64'h00000000_ff000000; |
| 171 | cmp_core_enable = cmp_core_enable | 64'h00000000_ff000000; |
| 172 | `endif |
| 173 | |
| 174 | `ifdef CORE_4 |
| 175 | cmp_core_avail = cmp_core_avail | 64'h000000ff_00000000; |
| 176 | cmp_core_enable = cmp_core_enable | 64'h000000ff_00000000; |
| 177 | `endif |
| 178 | |
| 179 | `ifdef CORE_5 |
| 180 | cmp_core_avail = cmp_core_avail | 64'h0000ff00_00000000; |
| 181 | cmp_core_enable = cmp_core_enable | 64'h0000ff00_00000000; |
| 182 | `endif |
| 183 | |
| 184 | `ifdef CORE_6 |
| 185 | cmp_core_avail = cmp_core_avail | 64'h00ff0000_00000000; |
| 186 | cmp_core_enable = cmp_core_enable | 64'h00ff0000_00000000; |
| 187 | `endif |
| 188 | |
| 189 | `ifdef CORE_7 |
| 190 | cmp_core_avail = cmp_core_avail | 64'hff000000_00000000; |
| 191 | cmp_core_enable = cmp_core_enable | 64'hff000000_00000000; |
| 192 | `endif |
| 193 | |
| 194 | // Takes value of cmp_core_enable at deassertion of warm reset (after POR). |
| 195 | cmp_xir_steering = cmp_core_enable; |
| 196 | cmp_core_enable_status = cmp_core_enable; |
| 197 | |
| 198 | asi_read_edge = 1'b0; |
| 199 | asi_read_addr = 26'b0; |
| 200 | asi_read_data = 64'b0; |
| 201 | asi_read_tid = 6'b0; |
| 202 | |
| 203 | //-------------------- |
| 204 | // Time must pass so that there is not a race condition with +args |
| 205 | @ (posedge `SYSTEMCLOCK); |
| 206 | asi_l2_idx_hash_en = `PARGS.hash_on; |
| 207 | |
| 208 | end // initial |
| 209 | |
| 210 | |
| 211 | //---------------------------------------------------------- |
| 212 | // cmp_core_enable_status takes value of cmp_core_enable at |
| 213 | // deassertion of warm reset (after POR). just do this for now. |
| 214 | always @(cmp_core_enable[63:0]) |
| 215 | begin |
| 216 | cmp_core_enable_status[63:0] = cmp_core_enable[63:0]; |
| 217 | end |
| 218 | |
| 219 | |
| 220 | assign (weak0, weak1) `CPU.tcu_do_mode = 0; |
| 221 | assign (weak0, weak1) `CPU.tcu_ss_mode = 0; |
| 222 | |
| 223 | |
| 224 | // The reset source bits in this register are writable to allow software to |
| 225 | // clear them after the chip reset sequence is complete, in order for virtual |
| 226 | // core warm resets to be distinguished from chip resets. HW will copy the |
| 227 | // current reset status into a shadow status whenever a warm reset occurs. |
| 228 | // |
| 229 | // Field Bit Initial Value R/W Description |
| 230 | // RSVD0 63:12 0 RO Reserved |
| 231 | // FREQ_S 11 0 RO Shadow status of FREQ |
| 232 | // POR_S 10 0 RO Shadow status of POR |
| 233 | // WMR_S 9 0 RO Shadow status of WMR |
| 234 | // RSVD1 8:5 0 RO Reserved |
| 235 | // RSVD2 4 0 R/W Reserved |
| 236 | // FREQ 3 0 R/W Set to one if the reset is a warm reset that changed frequency. |
| 237 | // POR 2 1 R/W Set to one if the reset is from PWRON_RST_L pin. |
| 238 | // WMR 1 0 R/W Set to one if the reset is from the WRM_RST pin. |
| 239 | always @(posedge `TOP.cpu.rst_wmr_protect) begin |
| 240 | asi_reset_stat[11:9] = asi_reset_stat[3:1]; |
| 241 | asi_reset_stat[1] = 1; |
| 242 | end |
| 243 | |
| 244 | |
| 245 | ///////////////////////////////////////////////////////////////// |
| 246 | // Make assigns weak so that other assigns (Vera) can over-ride |
| 247 | ///////////////////////////////////////////////////////////////// |
| 248 | |
| 249 | |
| 250 | // not core specific |
| 251 | `ifdef EMUL_COSIM |
| 252 | initial force `CPU.ncu_cmp_tick_enable = 1; |
| 253 | initial force `CPU.ncu_spc0_core_enable_status = &cmp_core_enable_status[7:0]; |
| 254 | initial force `CPU.ncu_spc1_core_enable_status = &cmp_core_enable_status[15:8]; |
| 255 | initial force `CPU.ncu_spc2_core_enable_status = &cmp_core_enable_status[23:16]; |
| 256 | initial force `CPU.ncu_spc3_core_enable_status = &cmp_core_enable_status[31:24]; |
| 257 | initial force `CPU.ncu_spc4_core_enable_status = &cmp_core_enable_status[39:32]; |
| 258 | initial force `CPU.ncu_spc5_core_enable_status = &cmp_core_enable_status[47:40]; |
| 259 | initial force `CPU.ncu_spc6_core_enable_status = &cmp_core_enable_status[55:48]; |
| 260 | initial force `CPU.ncu_spc7_core_enable_status = &cmp_core_enable_status[63:56]; |
| 261 | initial force `CPU.mio_spc_pwr_throttle_0[2:0] = 0; |
| 262 | initial force `CPU.mio_spc_pwr_throttle_1[2:0] = 0; |
| 263 | initial force `CPU.ncu_spc_l2_idx_hash_en = 0; |
| 264 | initial force `CPU.ncu_wmr_vec_mask = 0; |
| 265 | initial force `CPU.tcu_do_mode[7:0] = 0; |
| 266 | initial force `CPU.tcu_ss_mode[7:0] = 0; |
| 267 | `else |
| 268 | // from ncu_cmp_tick_enable register |
| 269 | assign (weak0, weak1) `CPU.ncu_cmp_tick_enable = ncu_cmp_tick_enable; |
| 270 | assign (weak0, weak1) `CPU.ncu_spc0_core_enable_status = &cmp_core_enable_status[7:0]; |
| 271 | assign (weak0, weak1) `CPU.ncu_spc1_core_enable_status = &cmp_core_enable_status[15:8]; |
| 272 | assign (weak0, weak1) `CPU.ncu_spc2_core_enable_status = &cmp_core_enable_status[23:16]; |
| 273 | assign (weak0, weak1) `CPU.ncu_spc3_core_enable_status = &cmp_core_enable_status[31:24]; |
| 274 | assign (weak0, weak1) `CPU.ncu_spc4_core_enable_status = &cmp_core_enable_status[39:32]; |
| 275 | assign (weak0, weak1) `CPU.ncu_spc5_core_enable_status = &cmp_core_enable_status[47:40]; |
| 276 | assign (weak0, weak1) `CPU.ncu_spc6_core_enable_status = &cmp_core_enable_status[55:48]; |
| 277 | assign (weak0, weak1) `CPU.ncu_spc7_core_enable_status = &cmp_core_enable_status[63:56]; |
| 278 | assign (weak0, weak1) `CPU.mio_spc_pwr_throttle_0[2:0] = asi_power_throttle[2:0]; |
| 279 | assign (weak0, weak1) `CPU.mio_spc_pwr_throttle_1[2:0] = asi_power_throttle[5:3]; |
| 280 | assign (weak0, weak1) `CPU.ncu_spc_l2_idx_hash_en = asi_l2_idx_hash_en; |
| 281 | |
| 282 | // `ifdef CMP |
| 283 | // `ifdef NOL2RTL |
| 284 | // assign (weak0, weak1) `CPU.ncu_spc_l2_idx_hash_en_t7lff = asi_l2_idx_hash_en; |
| 285 | // `endif |
| 286 | // `endif |
| 287 | |
| 288 | assign (weak0, weak1) `CPU.ncu_wmr_vec_mask = asi_wmr_vec_mask; |
| 289 | assign (weak0, weak1) cmp_core_running_status = 0; |
| 290 | `endif |
| 291 | |
| 292 | |
| 293 | `ifdef CORE_0 |
| 294 | `ifdef EMUL_COSIM |
| 295 | initial force `CPU.ncu_spc0_core_running[7:0] = cmp_core_running_rw[7:0]; |
| 296 | `else |
| 297 | assign `CPU.ncu_spc0_core_running[7:0] = cmp_core_running_rw[7:0]; |
| 298 | `endif |
| 299 | assign cmp_core_running_status[7:0] = `CPU.spc0_ncu_core_running_status[7:0]; |
| 300 | `else |
| 301 | assign cmp_core_running_status[7:0] = 8'h0; |
| 302 | `endif |
| 303 | |
| 304 | |
| 305 | `ifdef CORE_1 |
| 306 | `ifdef EMUL_COSIM |
| 307 | initial force `CPU.ncu_spc1_core_running[7:0] = cmp_core_running_rw[15:8]; |
| 308 | `else |
| 309 | assign `CPU.ncu_spc1_core_running[7:0] = cmp_core_running_rw[15:8]; |
| 310 | `endif |
| 311 | assign cmp_core_running_status[15:8] = `CPU.spc1_ncu_core_running_status[7:0]; |
| 312 | `else |
| 313 | assign cmp_core_running_status[15:8] = 8'h0; |
| 314 | `endif |
| 315 | |
| 316 | |
| 317 | `ifdef CORE_2 |
| 318 | `ifdef EMUL_COSIM |
| 319 | initial force `CPU.ncu_spc2_core_running[7:0] = cmp_core_running_rw[23:16]; |
| 320 | `else |
| 321 | assign `CPU.ncu_spc2_core_running[7:0] = cmp_core_running_rw[23:16]; |
| 322 | `endif |
| 323 | assign cmp_core_running_status[23:16] = `CPU.spc2_ncu_core_running_status[7:0]; |
| 324 | `else |
| 325 | assign cmp_core_running_status[23:16] = 8'h0; |
| 326 | `endif |
| 327 | |
| 328 | |
| 329 | `ifdef CORE_3 |
| 330 | `ifdef EMUL_COSIM |
| 331 | initial force `CPU.ncu_spc3_core_running[7:0] = cmp_core_running_rw[31:24]; |
| 332 | `else |
| 333 | assign `CPU.ncu_spc3_core_running[7:0] = cmp_core_running_rw[31:24]; |
| 334 | `endif |
| 335 | assign cmp_core_running_status[31:24] = `CPU.spc3_ncu_core_running_status[7:0]; |
| 336 | `else |
| 337 | assign cmp_core_running_status[31:24] = 8'h0; |
| 338 | `endif |
| 339 | |
| 340 | |
| 341 | `ifdef CORE_4 |
| 342 | `ifdef EMUL_COSIM |
| 343 | initial force `CPU.ncu_spc4_core_running[7:0] = cmp_core_running_rw[39:32]; |
| 344 | `else |
| 345 | assign `CPU.ncu_spc4_core_running[7:0] = cmp_core_running_rw[39:32]; |
| 346 | `endif |
| 347 | assign cmp_core_running_status[39:32] = `CPU.spc4_ncu_core_running_status[7:0]; |
| 348 | `else |
| 349 | assign cmp_core_running_status[39:32] = 8'h0; |
| 350 | `endif |
| 351 | |
| 352 | |
| 353 | `ifdef CORE_5 |
| 354 | `ifdef EMUL_COSIM |
| 355 | initial force `CPU.ncu_spc5_core_running[7:0] = cmp_core_running_rw[47:40]; |
| 356 | `else |
| 357 | assign `CPU.ncu_spc5_core_running[7:0] = cmp_core_running_rw[47:40]; |
| 358 | `endif |
| 359 | assign cmp_core_running_status[47:40] = `CPU.spc5_ncu_core_running_status[7:0]; |
| 360 | `else |
| 361 | assign cmp_core_running_status[47:40] = 8'h0; |
| 362 | `endif |
| 363 | |
| 364 | |
| 365 | `ifdef CORE_6 |
| 366 | `ifdef EMUL_COSIM |
| 367 | initial force `CPU.ncu_spc6_core_running[7:0] = cmp_core_running_rw[55:48]; |
| 368 | `else |
| 369 | assign `CPU.ncu_spc6_core_running[7:0] = cmp_core_running_rw[55:48]; |
| 370 | `endif |
| 371 | assign cmp_core_running_status[55:48] = `CPU.spc6_ncu_core_running_status[7:0]; |
| 372 | `else |
| 373 | assign cmp_core_running_status[55:48] = 8'h0; |
| 374 | `endif |
| 375 | |
| 376 | |
| 377 | `ifdef CORE_7 |
| 378 | `ifdef EMUL_COSIM |
| 379 | initial force `CPU.ncu_spc7_core_running[7:0] = cmp_core_running_rw[63:56]; |
| 380 | `else |
| 381 | assign `CPU.ncu_spc7_core_running[7:0] = cmp_core_running_rw[63:56]; |
| 382 | `endif |
| 383 | assign cmp_core_running_status[63:56] = `CPU.spc7_ncu_core_running_status[7:0]; |
| 384 | `else |
| 385 | assign cmp_core_running_status[63:56] = 8'h0; |
| 386 | `endif |
| 387 | |
| 388 | `ifdef CMP_BENCH |
| 389 | `ifndef CORE_0 initial force `CPU.ncu_spc0_core_running[7:0] = 0; `endif |
| 390 | `ifndef CORE_1 initial force `CPU.ncu_spc1_core_running[7:0] = 0; `endif |
| 391 | `ifndef CORE_2 initial force `CPU.ncu_spc2_core_running[7:0] = 0; `endif |
| 392 | `ifndef CORE_3 initial force `CPU.ncu_spc3_core_running[7:0] = 0; `endif |
| 393 | `ifndef CORE_4 initial force `CPU.ncu_spc4_core_running[7:0] = 0; `endif |
| 394 | `ifndef CORE_5 initial force `CPU.ncu_spc5_core_running[7:0] = 0; `endif |
| 395 | `ifndef CORE_6 initial force `CPU.ncu_spc6_core_running[7:0] = 0; `endif |
| 396 | `ifndef CORE_7 initial force `CPU.ncu_spc7_core_running[7:0] = 0; `endif |
| 397 | `endif |
| 398 | |
| 399 | //---------------------------------------------------------- |
| 400 | // Read CMP (or any NCU) registers (task called by Vera) |
| 401 | task read_cmp_reg; |
| 402 | input [31:0] addr; |
| 403 | inout [63:0] data; |
| 404 | input [5:0] tid; |
| 405 | |
| 406 | reg read_error; |
| 407 | |
| 408 | begin // { |
| 409 | |
| 410 | read_error = 0; |
| 411 | data = 0; |
| 412 | |
| 413 | if (addr[`IO_ASI_ADDR_REG] == `ASI_CMP_CORE) begin // { |
| 414 | case (addr[`IO_ASI_ADDR_VA]) // { |
| 415 | `ASI_CMP_CORE_AVAIL: |
| 416 | begin // { |
| 417 | // RO. fuses in sets of 8, based on cores built into model. |
| 418 | data = cmp_core_avail; |
| 419 | end // } |
| 420 | `ASI_CMP_CORE_ENABLE_STATUS: |
| 421 | begin // { |
| 422 | // RO. done is sets of 8. always has 0's where cores are not avail. |
| 423 | // Takes value of cmp_core_enable at deassertion of warm reset (after POR). |
| 424 | data = cmp_core_enable_status; |
| 425 | end // } |
| 426 | `ASI_CMP_CORE_ENABLE: |
| 427 | begin // { |
| 428 | // R/W. must be done in sets of 8. only effective after warm reset/POR. |
| 429 | // disable a core (make invisible). NOT PARKING. |
| 430 | // Logic must not allow all threads to be disabled. No self disable. |
| 431 | data = cmp_core_enable; |
| 432 | end // } |
| 433 | `ASI_CMP_XIR_STEERING: |
| 434 | begin // { |
| 435 | data = cmp_xir_steering; |
| 436 | end // } |
| 437 | `ASI_CMP_CORE_RUNNING_RW: |
| 438 | begin // { |
| 439 | // R/W. will initially take the value of th_check_enable plusarg. |
| 440 | // After that, th_check_enable will follow the value of this reg *after* thread parks. |
| 441 | // Parks threads. Can not park self. No self parking. Any thread |
| 442 | // that is either not avail or is disabled, will also be forced parked on RD. |
| 443 | // After sys reset, lowest enabled thread will always be unparked, others parked. |
| 444 | data = cmp_core_running_rw; |
| 445 | end // } |
| 446 | `ASI_CMP_CORE_RUNNING_STATUS: |
| 447 | begin // { |
| 448 | // DUT will drive high as needed. We read this wire as a register. |
| 449 | data = cmp_core_running_status; |
| 450 | end // } |
| 451 | `ASI_CMP_CORE_RUNNING_W1C: |
| 452 | begin // { |
| 453 | data = 64'h0; |
| 454 | `PR_NORMAL ("top", `NORMAL, "LD to WRITE-only register. Returning 0's"); |
| 455 | end // } |
| 456 | `ASI_CMP_CORE_RUNNING_W1S: |
| 457 | begin // { |
| 458 | data = 64'h0; |
| 459 | `PR_NORMAL ("top", `NORMAL, "LD to WRITE-only register. Returning 0's"); |
| 460 | end // } |
| 461 | `ASI_CMP_TICK_ENABLE: |
| 462 | begin // { |
| 463 | data = `CPU.ncu_cmp_tick_enable; |
| 464 | end // } |
| 465 | default: |
| 466 | begin // { |
| 467 | `PR_ERROR ("top", `ERROR, "Attempt to LD to invalid VA (%h) for CMP register",addr[`IO_ASI_ADDR_VA]); |
| 468 | read_error = 1; |
| 469 | end // } |
| 470 | endcase // } |
| 471 | end // } |
| 472 | |
| 473 | // not a cmp reg |
| 474 | else begin |
| 475 | case (addr[`IO_ASI_ADDR_ADR]) // { |
| 476 | `ASI_POWER_THROTTLE_ADR: |
| 477 | begin |
| 478 | data = asi_power_throttle; |
| 479 | end |
| 480 | |
| 481 | `ASI_WMR_VEC_MASK_ADR: |
| 482 | begin |
| 483 | data = asi_wmr_vec_mask; |
| 484 | end |
| 485 | |
| 486 | `ASI_L2_IDX_HASH_EN_ADR: |
| 487 | begin |
| 488 | data[0] = asi_l2_idx_hash_en; |
| 489 | end |
| 490 | |
| 491 | (`ASI_RESET_STAT & 32'hffffffff): |
| 492 | begin |
| 493 | data = asi_reset_stat; |
| 494 | end |
| 495 | |
| 496 | default: |
| 497 | begin // { |
| 498 | `PR_ERROR ("top", `ERROR, "Attempt to LD to invalid tb_top I/O register (%h)",addr); |
| 499 | read_error = 1; |
| 500 | end // } |
| 501 | |
| 502 | endcase |
| 503 | end |
| 504 | |
| 505 | |
| 506 | |
| 507 | `PR_INFO ("top", `INFO, "LD CMP Reg. asi=%h VA=%h reg_value=%h", |
| 508 | addr[`IO_ASI_ADDR_REG],addr[`IO_ASI_ADDR_VA],data); |
| 509 | |
| 510 | if (!read_error) begin |
| 511 | // signal that the reg was read |
| 512 | asi_read_edge = ~asi_read_edge; // for @(asi_read_edge) |
| 513 | asi_read_addr = addr[`IO_ASI_ADDR_ADR]; // addr[25:0] (addr[39:32] will always be 8'h90) |
| 514 | asi_read_data = data; // data[63:0] |
| 515 | asi_read_tid = tid; |
| 516 | end |
| 517 | end // } |
| 518 | endtask |
| 519 | |
| 520 | //---------------------------------------------------------- |
| 521 | // Write CMP (or any NCU) registers (task called by Vera) |
| 522 | task write_cmp_reg; |
| 523 | input [31:0] addr; |
| 524 | input [63:0] data; |
| 525 | input [6:0] tid; |
| 526 | |
| 527 | reg [63:0] reg_data; |
| 528 | integer i; |
| 529 | reg debugMode; // use to force a thread to park self |
| 530 | |
| 531 | begin // { |
| 532 | |
| 533 | // if requesting thread is 1ff then set debugMode. this |
| 534 | // is a special 'back door' case to allow the SPC bench to park |
| 535 | // all threads for debug logic testing. |
| 536 | if (tid == 7'h7f) debugMode = 1; |
| 537 | else debugMode = 0; |
| 538 | |
| 539 | if (addr[`IO_ASI_ADDR_REG] == `ASI_CMP_CORE) begin // { |
| 540 | case (addr[`IO_ASI_ADDR_VA]) // { |
| 541 | `ASI_CMP_CORE_AVAIL: |
| 542 | begin // { |
| 543 | // RO. fuses in sets of 8, based on cores built into model. |
| 544 | reg_data = cmp_core_avail; |
| 545 | `PR_NORMAL ("top", `NORMAL, "ST to READ-only register. Value will not change"); |
| 546 | end // } |
| 547 | `ASI_CMP_CORE_ENABLE_STATUS: |
| 548 | begin // { |
| 549 | // RO. done is sets of 8. always has 0's where cores are not avail. |
| 550 | // Takes value of cmp_core_enable at deassertion of warm reset (after POR). |
| 551 | reg_data = cmp_core_enable_status; |
| 552 | `PR_NORMAL ("top", `NORMAL, "ST to READ-only register. Value will not change"); |
| 553 | end // } |
| 554 | `ASI_CMP_CORE_ENABLE: |
| 555 | begin // { |
| 556 | reg_data[63:0] = 0; |
| 557 | |
| 558 | // R/W. must be done in sets of 8. only effective after warm reset/POR. |
| 559 | // disable a core (make invisible). NOT PARKING. |
| 560 | // Logic must not allow all threads to be disabled. No self disable. |
| 561 | |
| 562 | // make into sets of 8 and only if core exists |
| 563 | if (cmp_core_avail[63:54] & data[63:54]) reg_data[63:54] = 8'hff; |
| 564 | if (cmp_core_avail[53:48] & data[53:48]) reg_data[53:48] = 8'hff; |
| 565 | if (cmp_core_avail[47:40] & data[47:40]) reg_data[47:40] = 8'hff; |
| 566 | if (cmp_core_avail[39:32] & data[39:32]) reg_data[39:32] = 8'hff; |
| 567 | if (cmp_core_avail[31:24] & data[31:24]) reg_data[31:24] = 8'hff; |
| 568 | if (cmp_core_avail[23:16] & data[23:16]) reg_data[23:16] = 8'hff; |
| 569 | if (cmp_core_avail[15:8] & data[15:8]) reg_data[15:8] = 8'hff; |
| 570 | if (cmp_core_avail[7:0] & data[7:0]) reg_data[7:0] = 8'hff; |
| 571 | |
| 572 | // the core that called this stays on unless core 0 is on? |
| 573 | //if (!cmp_core_enable[7:0]) reg_data[63:0] = reg_data[63:0] | (64'hff << tid[5:3]); |
| 574 | // the core that called this always stays on if data=0. |
| 575 | if (reg_data[63:0] == 64'h0) reg_data[63:0] = reg_data[63:0] | (64'hff << tid[5:3]); |
| 576 | cmp_core_enable[63:0] = reg_data[63:0]; |
| 577 | if (!debugMode) diag_change_core_running = ~diag_change_core_running; |
| 578 | end // } |
| 579 | `ASI_CMP_XIR_STEERING: |
| 580 | begin // { |
| 581 | cmp_xir_steering = data & cmp_core_enable; |
| 582 | //reg_data = data; |
| 583 | end // } |
| 584 | `ASI_CMP_CORE_RUNNING_RW: |
| 585 | begin // { |
| 586 | |
| 587 | // R/W. will initially take the value of th_check_enable plusarg. |
| 588 | // After that, th_check_enable will follow the value of reg *after* thread parks. |
| 589 | // Parks threads. Can not park self if that is only thread running. Any thread |
| 590 | // that is either not avail or is disabled, will also appear parked on RD/WR. |
| 591 | // After sys reset, lowest enabled thread will normaly be unparked. |
| 592 | reg_data = data; |
| 593 | |
| 594 | // the thread that called this ALWAYS stays on if no others would be left on. |
| 595 | // Can not have all threads parked via software. |
| 596 | if ((reg_data & cmp_core_enable & cmp_core_avail) == 0 && debugMode !== 1'b1) |
| 597 | reg_data[tid] = 1; |
| 598 | |
| 599 | // Any thread that is either not avail or is disabled, will also be forced parked. |
| 600 | reg_data = reg_data & cmp_core_enable & cmp_core_avail; |
| 601 | |
| 602 | cmp_core_running_rw = reg_data; |
| 603 | if (!debugMode) diag_change_core_running = ~diag_change_core_running; |
| 604 | end // } |
| 605 | `ASI_CMP_CORE_RUNNING_STATUS: |
| 606 | begin // { |
| 607 | //reg_data = cmp_core_running_status; |
| 608 | `PR_NORMAL ("top", `NORMAL, "ST to READ-only register. Value will not change"); |
| 609 | end // } |
| 610 | `ASI_CMP_CORE_RUNNING_W1S: |
| 611 | begin // { |
| 612 | // Any thread that is either not avail or is disabled, will also be forced parked. |
| 613 | reg_data = data & cmp_core_enable & cmp_core_avail; |
| 614 | reg_data = cmp_core_running_rw | reg_data; |
| 615 | cmp_core_running_rw = reg_data; |
| 616 | if (!debugMode) diag_change_core_running = ~diag_change_core_running; |
| 617 | end // } |
| 618 | `ASI_CMP_CORE_RUNNING_W1C: |
| 619 | begin // { |
| 620 | reg_data = cmp_core_running_rw & ~data; |
| 621 | // the thread that called this ALWAYS stays on if all threads would be parked. |
| 622 | // Can not park self if parking all. |
| 623 | if (reg_data[63:0] == 64'h0 && debugMode !== 1'b1) reg_data[tid] = 1; |
| 624 | cmp_core_running_rw = reg_data; |
| 625 | if (!debugMode) diag_change_core_running = ~diag_change_core_running; |
| 626 | end // } |
| 627 | `ASI_CMP_TICK_ENABLE: |
| 628 | begin // { |
| 629 | ncu_cmp_tick_enable = data[0]; |
| 630 | end // } |
| 631 | default: |
| 632 | begin // { |
| 633 | `PR_ERROR ("top", `ERROR, "Attempt to ST to invalid VA (%h) for CMP register",addr[`IO_ASI_ADDR_VA]); |
| 634 | end // } |
| 635 | endcase // } |
| 636 | end // } |
| 637 | |
| 638 | // not a cmp reg |
| 639 | else begin |
| 640 | case (addr[`IO_ASI_ADDR_ADR]) // { |
| 641 | `ASI_POWER_THROTTLE_ADR: |
| 642 | begin |
| 643 | asi_power_throttle = data; |
| 644 | end |
| 645 | |
| 646 | `ASI_WMR_VEC_MASK_ADR: |
| 647 | begin |
| 648 | asi_wmr_vec_mask = data[0]; |
| 649 | end |
| 650 | |
| 651 | `ASI_L2_IDX_HASH_EN_ADR: |
| 652 | begin |
| 653 | asi_l2_idx_hash_en = data[0]; |
| 654 | end |
| 655 | |
| 656 | (`ASI_RESET_STAT & 32'hffffffff): |
| 657 | begin |
| 658 | asi_reset_stat = data & 64'he; |
| 659 | end |
| 660 | |
| 661 | default: |
| 662 | begin // { |
| 663 | `PR_ERROR ("top", `ERROR, "Attempt to ST to invalid tb_top I/O register (%h)",addr); |
| 664 | end // } |
| 665 | |
| 666 | endcase |
| 667 | end |
| 668 | |
| 669 | |
| 670 | `PR_INFO ("top", `INFO, "ST CMP Reg. asi=%h VA=%h reg_value=%h",addr[`IO_ASI_ADDR_REG],addr[`IO_ASI_ADDR_VA],reg_data); |
| 671 | end // } |
| 672 | endtask |
| 673 | |