| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ddr2_monitor.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifdef MCUSAT |
| 36 | `include "mcu_dispmonDefines.vh" |
| 37 | `else |
| 38 | `include "defines.vh" |
| 39 | `include "dispmonDefines.vh" |
| 40 | `endif |
| 41 | |
| 42 | // Some general `defines used for OVA checker readability. |
| 43 | `ifdef DDR2_OVA_SIM_MON // {{{ |
| 44 | |
| 45 | `define DELAY 0 |
| 46 | `define EDGE_EXPR 0 // 0 -> posedge, 1 -> negedge, 2 -> edge |
| 47 | `define SEVERITY 0 |
| 48 | `define CATEGORY 0 |
| 49 | `define START 1'b0 |
| 50 | `define STOP 1'b0 |
| 51 | |
| 52 | `endif |
| 53 | // }}} |
| 54 | |
| 55 | // DDR-II Commands // {{{ |
| 56 | `define DESELECT 4'b1000 // cs_bar |
| 57 | `define NOP 4'b0111 // ~cs_bar,ras_bar,cas_bar,we_bar |
| 58 | `define ACTIVE 4'b0011 // ~cs_bar,~ras_bar,cas_bar,we_bar |
| 59 | `define READ 4'b0101 // ~cs_bar,ras_bar,~cas_bar,we_bar |
| 60 | `define WRITE 4'b0100 // ~cs_bar,ras_bar,~cas_bar,~we_bar |
| 61 | `define BURST_STOP 4'b0110 // ~cs_bar,ras_bar,cas_bar,~we_bar |
| 62 | // NOTE: DDR-II does not have such command |
| 63 | |
| 64 | `define PRECHARGE 4'b0010 // ~cs_bar,~ras_bar,cas_bar,~we_bar, |
| 65 | // addr[10]: for precharging all banks, |
| 66 | // ~addr[10], ba[1:0]: for precharging a specific bank. |
| 67 | `define REF_SREF 4'b0001 // ~cs_bar,~ras_bar,~cas_bar,we_bar ~cke: SREF, cke: REF |
| 68 | `define MRS 4'b0000 // ~cs_bar,~ras_bar,~cas_bar,~we_bar |
| 69 | // NOTE: ba[1:0]=2'b00 for MRS, 2'b01 for EMRS |
| 70 | // }}} |
| 71 | |
| 72 | // Controler States // {{{ |
| 73 | `define CS_MODE_REG_SET 3'b000 |
| 74 | `define CS_IDLE 3'b001 // All banks are idle |
| 75 | `define CS_BANKS_ACTIVE_OR_IDLE 3'b010 // Some banks are active of R/W |
| 76 | `define CS_SELF_REFRESH 3'b011 |
| 77 | `define CS_REFRESH 3'b100 |
| 78 | `define CS_POWER_DOWN 3'b101 // When (~CKE @ t-1) and ~CKE @ t |
| 79 | `define CS_POWER_DOWN_EXIT 3'b110 |
| 80 | `define CS_ILLEGAL 3'b111 |
| 81 | |
| 82 | // }}} |
| 83 | |
| 84 | // Bank States // {{{ |
| 85 | `define BS_IDLE 3'b000 |
| 86 | `define BS_ROW_ACT 3'b001 |
| 87 | `define BS_READING 3'b010 |
| 88 | `define BS_READING_AUTOPRE 3'b011 |
| 89 | `define BS_WRITING 3'b100 |
| 90 | `define BS_WRITING_AUTOPRE 3'b101 |
| 91 | `define BS_PRECHARGE 3'b110 |
| 92 | `define BS_ILLEGAL 3'b111 |
| 93 | |
| 94 | // }}} |
| 95 | |
| 96 | module ddr2_monitor(/*{{{*/ |
| 97 | ck, |
| 98 | ck_bar, |
| 99 | cke, |
| 100 | areset, |
| 101 | cs_bar, |
| 102 | ras_bar, |
| 103 | cas_bar, |
| 104 | ba, |
| 105 | we_bar, |
| 106 | addr, |
| 107 | dm, |
| 108 | dq, |
| 109 | dqs, |
| 110 | dqs_bar, |
| 111 | init_done, |
| 112 | odt |
| 113 | ); |
| 114 | |
| 115 | parameter tMRD = 2; // Mode reg set command cycle time -- |
| 116 | // any new command needs to wait tMRD cycles after MRD |
| 117 | parameter tRFC = 15; // Min delay between SHELF REFRESH to ACT/SHELF REFRESH |
| 118 | parameter tXSRD = 200; // Min delay between exit SHELF REFRESH and a READ |
| 119 | parameter tXSNR = 10; // Min delay between exit SHELF REFRESH and a non-READ |
| 120 | parameter tRAS = 9; // Min delay between ACT and a PRECHARGE -- Rank Active Time |
| 121 | parameter tCAS = 3; // Min CAS latency |
| 122 | parameter tRCD = 3; // Min delay between ACT and a READ/WRITE to the same row (RAS -> CAS) |
| 123 | parameter tCCD = 2; // Min delay between READ/WRITE -- CAS to CAS delay time |
| 124 | parameter tRC = 12; // Min delay between successive ACTIVE to the same banks -- RAS Cycle time |
| 125 | parameter tRRD = 2; // Min delay between successive ACTIVE to diff banks |
| 126 | parameter tWTR = 2; // Min delay between a WRITE and a READ (WRITE -> READ) |
| 127 | parameter tRTW = 4; // Min delay between a READ and a WRITE to the same bank (READ -> WRITE) |
| 128 | parameter tWR = 3; // Write recovery time -- |
| 129 | // Min delay between completion of WRITE burst and precharge |
| 130 | parameter tXP = 2; // Min delay from PRECHARGE Power-down Exit to non-read command |
| 131 | parameter tXARD = 2; // Min delay from Active Power-down Exit to READ command |
| 132 | parameter tRP = 3; // Row precharge period |
| 133 | parameter tFAW = 9; // Four Activate Window. |
| 134 | |
| 135 | parameter ROW_WIDTH = 15; // A0-A12, while if A13 is used for 1G densities the width should be 14 |
| 136 | parameter DATA_WIDTH = 8; // Min data bus width |
| 137 | parameter DATA_MASK_WIDTH = 1; |
| 138 | parameter DDL_TRACK_EN = 1; // DDL tracking enable |
| 139 | parameter BURST_TYPE_SEQ = 1; // Default Burst Sequentially |
| 140 | parameter BURST_LENGTH = 4; // Default Burst length |
| 141 | parameter ADDITIVE_LATENCY = 0; // Default additive latency |
| 142 | // Actually DDR-II does require you to program AL in |
| 143 | // EMRS. |
| 144 | parameter DATA_STROBE_NUM = 4; // numbers of data strobe signals (dqs, ldqs, udqs, rdqs) |
| 145 | |
| 146 | |
| 147 | input ck; // ck and ck_bar are differential clock inputs |
| 148 | input ck_bar; // |
| 149 | input cke; // Clock enalbe |
| 150 | input areset; // Asyn Reset |
| 151 | input cs_bar; // Chip select |
| 152 | input ras_bar; // Row addr strobe |
| 153 | input cas_bar; // Column addr strob |
| 154 | input [2:0] ba; // Bank addr b[1:0] for 256Mb/512Mb with 4 banks, |
| 155 | // b[2:0] for 1/2/4Gb with 8 banks |
| 156 | input we_bar; // Write enable |
| 157 | input [ROW_WIDTH - 1 : 0] addr; // Addr bus |
| 158 | input [DATA_MASK_WIDTH - 1 : 0] dm; // Data mask |
| 159 | input [DATA_WIDTH - 1 : 0] dq; // Data |
| 160 | input [DATA_STROBE_NUM - 1 : 0] dqs; // Data strobe |
| 161 | input [DATA_STROBE_NUM - 1 : 0] dqs_bar; // Data strobe |
| 162 | input init_done; // dram_init_done |
| 163 | input odt; // On Die Termination |
| 164 | |
| 165 | |
| 166 | |
| 167 | wire [3:0] command = ((cs_bar !== 1'bz) && (ras_bar !== 1'bz) && (cas_bar !== 1'bz) && (we_bar !== 1'bz)) ? {cs_bar,ras_bar,cas_bar,we_bar} : 4'h7; |
| 168 | // wire [3:0] command = {cs_bar,ras_bar,cas_bar,we_bar}; |
| 169 | wire command_DESELECT = cs_bar; |
| 170 | |
| 171 | reg [4:0] tMRD_reg = tMRD; |
| 172 | reg [4:0] tRFC_reg = tRFC; |
| 173 | reg [8:0] tXSRD_reg = tXSRD; |
| 174 | reg [4:0] tXSNR_reg = tXSNR; |
| 175 | reg [4:0] tRAS_reg = tRAS; |
| 176 | reg [4:0] tCAS_reg = tCAS; |
| 177 | reg [4:0] tRCD_reg = tRCD; |
| 178 | reg [4:0] tCCD_reg = tCCD; |
| 179 | reg [4:0] tRC_reg = tRC; |
| 180 | reg [4:0] tRRD_reg = tRRD; |
| 181 | reg [4:0] tWTR_reg = tWTR; |
| 182 | reg [4:0] tRTW_reg = tRTW; |
| 183 | reg [4:0] tWR_reg = tWR; |
| 184 | reg [4:0] tXP_reg = tXP; |
| 185 | reg [4:0] tXARD_reg = tXARD; |
| 186 | reg [4:0] tRP_reg = tRP; |
| 187 | reg [4:0] tFAW_reg = tFAW; |
| 188 | |
| 189 | reg [4:0] BURST_LENGTH_reg = BURST_LENGTH; |
| 190 | reg [4:0] ADDITIVE_LATENCY_reg = ADDITIVE_LATENCY; |
| 191 | reg [4:0] BURST_TYPE_SEQ_reg = BURST_TYPE_SEQ; |
| 192 | // reg ROW_WIDTH_reg = ROW_WIDTH; |
| 193 | // reg DATA_WIDTH_reg = DATA_WIDTH; |
| 194 | // reg DATA_MASK_WIDTH_reg = DATA_MASK_WIDTH; |
| 195 | // reg DDL_TRACK_EN_reg = DDL_TRACK_EN; |
| 196 | // reg DATA_STROBE_NUM_reg = DATA_STROBE_NUM; |
| 197 | |
| 198 | |
| 199 | |
| 200 | |
| 201 | // Rule6: RAS Cycle Time |
| 202 | // Time( Act(Bank x) -> Precharge (Bank x) -> Act(Bank x) ) >= tRC_reg |
| 203 | // |
| 204 | |
| 205 | // Rule7: Bank Active Time |
| 206 | // Time( Act(Bank x) -> Precharge (Bank x) ) >= tRAS_reg |
| 207 | // |
| 208 | |
| 209 | // Rule8: |
| 210 | // if Time((Act(Bank x) -> Read(Bank x)) < tRCD_reg then |
| 211 | // Time((Act(Bank x) -> Read(Bank x)) + Additive >= tRCD_reg |
| 212 | |
| 213 | // MRS fields |
| 214 | reg [3:0] MRS_BL; // Addr [2:0], Burst Len |
| 215 | reg MRS_BT; // Addr [3], Burst Type; ~Addr[3] for Sequential, Addr[3] for Interleave. |
| 216 | reg [2:0] MRS_CAS; // Addr [6:4], Cas latency |
| 217 | reg [2:0] MRS_WR; // Addr [11:9], Write Recovery |
| 218 | reg MRS_TM; |
| 219 | reg MRS_DLL_RESET; |
| 220 | |
| 221 | // EMRS files |
| 222 | reg [2:0] EMRS_AL; // Addr [5:3], Additive Latency |
| 223 | reg EMRS_DLL_ENABLE; |
| 224 | reg [1:0] EMRS_RTT; |
| 225 | reg [2:0] EMRS_OCD; |
| 226 | reg EMRS_DQS_BAR_DISABLE; |
| 227 | |
| 228 | |
| 229 | // Global Timers |
| 230 | reg [5:0] time_after_ACT; |
| 231 | reg is_there_ACT; |
| 232 | reg [5:0] time_after_READ; |
| 233 | reg is_there_READ; |
| 234 | reg [5:0] time_after_WRITE; |
| 235 | reg is_there_WRITE; |
| 236 | reg [5:0] time_after_MRS; |
| 237 | reg is_there_MRS; |
| 238 | reg [5:0] time_after_REF; |
| 239 | reg is_there_REF; |
| 240 | reg [7:0] time_after_SREF; |
| 241 | reg is_there_SREF; |
| 242 | reg [10:0] time_after_DLL_reset; |
| 243 | reg start_time_after_DLL_reset; |
| 244 | reg [5:0] time_after_PWD_EXIT; |
| 245 | reg is_there_PWD_EXIT; |
| 246 | reg precharge_pwdn; // power down types: precharge/active power down |
| 247 | |
| 248 | reg [5:0] time_after_PREALL; |
| 249 | |
| 250 | reg [15:0] ddr2_err; |
| 251 | reg [21:0] init_err; |
| 252 | reg seq_act_violation; |
| 253 | reg is_init_done; |
| 254 | reg is_DLL_reset; |
| 255 | |
| 256 | |
| 257 | initial |
| 258 | `PR_DEBUG("ddr2_monitor", `DEBUG, "INFO: DDR2_mon initiated at %m"); |
| 259 | |
| 260 | |
| 261 | // Global Timing constraint flags (applicable to all banks) |
| 262 | wire tREAD_TO_WRITE_met = (time_after_READ >= tRTW_reg); |
| 263 | |
| 264 | wire tREAD_TO_READ_met = |
| 265 | (time_after_READ >= ( (MRS_BL > tCCD_reg) ? MRS_BL : tCCD_reg) ); |
| 266 | |
| 267 | wire stop_time_after_READ = (time_after_READ == 6'b111111) || |
| 268 | (tREAD_TO_WRITE_met && tREAD_TO_READ_met); |
| 269 | |
| 270 | // min time (WRITE -> READ) : WL + 1/2 * BL + tWTR_reg |
| 271 | wire tWRITE_TO_READ_met = |
| 272 | (time_after_WRITE >= ( (EMRS_AL + MRS_CAS - 1) + (MRS_BL >> 1) + tWTR_reg ) ); |
| 273 | // min time (WRITE -> WRITE): |
| 274 | wire tWRITE_TO_WRITE_met = |
| 275 | (time_after_WRITE >= ( (MRS_BL > tCCD_reg) ? MRS_BL : tCCD_reg) ); |
| 276 | |
| 277 | wire stop_time_after_WRITE = (time_after_WRITE == 6'b111111) || |
| 278 | ( tWRITE_TO_READ_met && tWRITE_TO_WRITE_met ); |
| 279 | // min time (ACT -> ACT) : See JC 42.3 page 24 |
| 280 | wire tACT_TO_ACT_met = ( time_after_ACT >= tRRD_reg); |
| 281 | wire stop_time_after_ACT = (time_after_ACT == 6'b111111) || tACT_TO_ACT_met; |
| 282 | |
| 283 | // min time (MRS -> Any) : |
| 284 | wire tMRS_TO_ANY_met = (time_after_MRS >= tMRD_reg) && is_there_MRS; |
| 285 | wire stop_time_after_MRS = ( time_after_MRS == 6'b111111) || tMRS_TO_ANY_met ; |
| 286 | |
| 287 | // min time (REF -> any command) See JC42.3 page 46 |
| 288 | wire tREF_TO_ANY_met = (time_after_REF >= tRFC_reg); |
| 289 | wire stop_time_after_REF = (time_after_REF == 6'b111111) || tREF_TO_ANY_met; |
| 290 | |
| 291 | // min time (SREF -> any_non_read) : `tXSNR_reg |
| 292 | // min time (SREF -> read) : `tXSRD_reg |
| 293 | wire tSREF_TO_ANY_NON_RD_met = (time_after_SREF >= tXSNR_reg); |
| 294 | |
| 295 | wire tSREF_TO_RD_met = (time_after_SREF >= tXSRD_reg); |
| 296 | |
| 297 | wire stop_time_after_SREF = (time_after_REF == 8'b11111111) || |
| 298 | ( tSREF_TO_ANY_NON_RD_met && tSREF_TO_RD_met); |
| 299 | |
| 300 | // min time (ACT_PWDN_EXIT -> RD): |
| 301 | // min time (PRECHARGE_PWDN_EXIT -> ANY_NON_RD) |
| 302 | wire tACTIVE_POWERDOWN_EXIT_TO_RD_met = (time_after_PWD_EXIT >= tXARD_reg); |
| 303 | wire tPRECHARGE_POWERDOWN_EXIT_TO_NON_RD_met = (time_after_PWD_EXIT >= tXP_reg); |
| 304 | |
| 305 | wire stop_time_after_PWD_EXIT = ( time_after_PWD_EXIT == 6'b111111) || |
| 306 | ( tACTIVE_POWERDOWN_EXIT_TO_RD_met && tPRECHARGE_POWERDOWN_EXIT_TO_NON_RD_met); |
| 307 | |
| 308 | |
| 309 | // min time (PRECHARGE_ALL -> REFRESHING) : tRP_reg see JC42.3 page 46 on the Refresh command |
| 310 | wire tPREALL_TO_REF_met = ( time_after_PREALL >= tRP_reg); |
| 311 | wire stop_time_after_PREALL = (time_after_PREALL == 6'b111111) || tPREALL_TO_REF_met; |
| 312 | |
| 313 | |
| 314 | // PreCharge Indiation: One bank or All banks |
| 315 | |
| 316 | wire ref = ( command == `REF_SREF) && cke; |
| 317 | wire sref = ( command == `REF_SREF) && ~cke; |
| 318 | |
| 319 | // Controller State |
| 320 | reg [2:0] controller_state; |
| 321 | |
| 322 | wire [2:0] bank1_status; |
| 323 | wire [2:0] bank2_status; |
| 324 | wire [2:0] bank3_status; |
| 325 | wire [2:0] bank4_status; |
| 326 | wire [2:0] bank5_status; |
| 327 | wire [2:0] bank6_status; |
| 328 | wire [2:0] bank7_status; |
| 329 | wire [2:0] bank8_status; |
| 330 | |
| 331 | wire all_bank_idle = |
| 332 | (bank1_status == `BS_IDLE) && |
| 333 | (bank2_status == `BS_IDLE) && |
| 334 | (bank3_status == `BS_IDLE) && |
| 335 | (bank4_status == `BS_IDLE) && |
| 336 | (bank5_status == `BS_IDLE) && |
| 337 | (bank6_status == `BS_IDLE) && |
| 338 | (bank7_status == `BS_IDLE) && |
| 339 | (bank8_status == `BS_IDLE); |
| 340 | |
| 341 | /* Monitors for DDR-II */ |
| 342 | |
| 343 | reg err_cmd_BURST_STOP; |
| 344 | reg err_bad_ba_for_mrs; |
| 345 | reg err_bad_burst_len; |
| 346 | reg err_bad_addr_for_mrs; |
| 347 | reg err_bad_write_recover; |
| 348 | reg err_bad_cas_latency; |
| 349 | reg err_bad_additive_latency; |
| 350 | reg err_rd_dqs_not_asserted_when_rd_data_ready; |
| 351 | reg err_wr_dqs_not_asserted_when_wr_data_ready; |
| 352 | reg err_normal_operation_started_with_DLL_reset_in_MRS; |
| 353 | reg err_normal_operation_started_with_TM_set_in_MRS; |
| 354 | reg err_normal_operation_started_without_DLL_enable; |
| 355 | reg err_normal_operation_started_without_initialization; |
| 356 | reg err_invalid_ODT_value_RTT_in_EMRS; |
| 357 | reg err_unknown_value_in_MRS_or_EMRS; |
| 358 | reg err_invalid_cmd; |
| 359 | reg err_clk_and_clkbar_not_in_sync; |
| 360 | reg err_dqs_bar_disabled_but_not_tied_low; |
| 361 | reg err_unknown_clk_or_clkbar_or_cke; |
| 362 | reg err_unknown_value_on_precharge_pin_during_read_or_write; |
| 363 | reg err_unknown_col_or_bank_addr_during_read; |
| 364 | reg err_unknown_col_or_bank_addr_during_write; |
| 365 | reg err_unknown_row_or_bank_addr_during_active_cmd; |
| 366 | reg err_unknown_bank_or_precharge_pin_during_precharge; |
| 367 | reg err_sref_issued_when_bank_not_idle; |
| 368 | reg err_dqs_and_dqsbar_not_in_sync; |
| 369 | reg err_unknown_value_on_odt_pin; |
| 370 | reg err_ref_issued_when_bank_not_idle; |
| 371 | reg Ill_OCD_activity; |
| 372 | |
| 373 | // Rule: data strobe is not asserted when write data is enabled |
| 374 | `ifdef REGISTERED_DIMMS |
| 375 | wire [3:0] RL = MRS_CAS + EMRS_AL + 1'b1; // RL = CL + AL |
| 376 | `else |
| 377 | wire [3:0] RL = MRS_CAS + EMRS_AL; // RL = CL + AL |
| 378 | `endif |
| 379 | // I only assert rd_data_ready when 1st cycle of the read data is ready (I need to check the rest latter) |
| 380 | wire rd_data_ready = (time_after_READ == RL) ; |
| 381 | wire [2:0] burst_len_addr2_0 = addr[2:0]; |
| 382 | // rd_data_ready ==> (&dqs) |
| 383 | |
| 384 | // Rule: data strobe is not asserted when read data is ready |
| 385 | // WL = RL - 1 == AL + CL - 1 |
| 386 | wire [3:0] WL = RL - 1; |
| 387 | |
| 388 | // I only assert wr_data_ready when 1st cycle of the write data is ready (I need to check the rest latter) |
| 389 | wire wr_data_ready = time_after_WRITE == WL; |
| 390 | |
| 391 | |
| 392 | integer j; |
| 393 | |
| 394 | |
| 395 | always @(posedge ck) |
| 396 | begin |
| 397 | if(init_done) |
| 398 | begin |
| 399 | // Rule: DDR-2 does not support burst_stop |
| 400 | err_cmd_BURST_STOP = ( command == `BURST_STOP) ? 1'b1 : 1'b0; |
| 401 | // Rule: Ill bank address |
| 402 | // See JC42.3 Page 14 on the Bank Address Table |
| 403 | |
| 404 | err_bad_ba_for_mrs = (command == `MRS) && (ba[2] == 1'b1); |
| 405 | |
| 406 | //err_bad_ba_for_mrs = (command == `MRS) && (ba[1:0] == 2'b10 || ba[1:0] == 2'b11 || ba[2] == 1'b1 ); |
| 407 | |
| 408 | |
| 409 | // Rule: Burst length can be either 4 or 8 in MRS (A[2:0]) |
| 410 | err_bad_burst_len = (areset != 1'b1) && (command == `MRS) && (ba[1:0] == 2'b00) && |
| 411 | ~(addr[2:0] == 3'b010 || addr[2:0] == 3'b011); |
| 412 | |
| 413 | // Rule: See JC42.3 Page 14 A13 - A15 shoud be set to 0 when MRS/EMRS |
| 414 | // err_bad_addr_for_mrs = (command == `MRS) && (addr[14:13] != 2'b00); |
| 415 | if(command == `MRS) |
| 416 | begin |
| 417 | for(j = ROW_WIDTH - 1; j > 12; j = j - 1) |
| 418 | begin |
| 419 | if(addr[j]) |
| 420 | err_bad_addr_for_mrs = 1'b1; |
| 421 | end |
| 422 | end |
| 423 | |
| 424 | // Rule: Write recovery for autoprecharge in MRS (A[11:9]) |
| 425 | // The possilbe vaules are 2, 3, 4, 5 or 6 |
| 426 | err_bad_write_recover = (areset != 1'b1) && (command == `MRS) && (ba[1:0] == 2'b00) && |
| 427 | ~(addr[11:9] == 3'b001 || addr[11:9] == 3'b010 || addr[11:9] == 3'b011 || addr[11:9] == 3'b100 || addr[11:9] == 3'b101); |
| 428 | |
| 429 | // Rule: Cas latency can be 3, 4 or 5 in MRS (A[6:4]) |
| 430 | err_bad_cas_latency = (areset != 1'b1) && (command == `MRS) && (ba[1:0] == 2'b00) && |
| 431 | ~(addr[6:4] == 3'b010 || addr[6:4] == 3'b011 || addr[6:4] == 3'b100 || addr[6:4] == 3'b101 ); |
| 432 | |
| 433 | // Rule: Additive latency can be 0, 1, 2, 3 or 4, in EMRS (A[5:3]) |
| 434 | err_bad_additive_latency = (areset != 1'b1) && (command == `MRS) && (ba[1:0] == 2'b01) && |
| 435 | ~(addr[5:3] == 3'b000 || addr[5:3] == 3'b001 || addr[5:3] == 3'b010 || addr[5:3] == 3'b011 || addr[5:3] == 3'b100 ); |
| 436 | |
| 437 | // rd_data_ready ==> (&dqs) |
| 438 | err_rd_dqs_not_asserted_when_rd_data_ready = rd_data_ready && (^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b1 && ^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b0 ); |
| 439 | //err_rd_dqs_not_asserted_when_rd_data_ready = ddr2_err[10]; |
| 440 | |
| 441 | // wr_data_ready ==> active (dqs) |
| 442 | err_wr_dqs_not_asserted_when_wr_data_ready = wr_data_ready && (^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b1 && ^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b0 ); |
| 443 | |
| 444 | err_normal_operation_started_with_DLL_reset_in_MRS = (command == `ACTIVE) && MRS_DLL_RESET; |
| 445 | |
| 446 | err_normal_operation_started_with_TM_set_in_MRS = is_init_done && (command == `ACTIVE) && MRS_TM; |
| 447 | |
| 448 | err_normal_operation_started_without_DLL_enable = is_init_done && (command == `ACTIVE) && ~EMRS_DLL_ENABLE; |
| 449 | |
| 450 | err_normal_operation_started_without_initialization = !is_init_done && (command == `ACTIVE); |
| 451 | |
| 452 | err_invalid_ODT_value_RTT_in_EMRS = (EMRS_RTT == 2'b11); |
| 453 | |
| 454 | err_unknown_value_in_MRS_or_EMRS = (command == `MRS) && ((^addr[ROW_WIDTH - 1:0]) === 1'bx); |
| 455 | |
| 456 | err_invalid_cmd = (!areset) && (command_DESELECT !== 1'b1) && ((command !== `DESELECT) && (command !== `NOP) && (command !== `ACTIVE) && (command !== `READ) && (command !== `WRITE) && (command !== `BURST_STOP) && (command !== `PRECHARGE) && (command !== `REF_SREF) && (command !== `MRS)); |
| 457 | |
| 458 | err_clk_and_clkbar_not_in_sync = ((!areset) && (cke) && (ck !== ~ck_bar)); |
| 459 | |
| 460 | err_dqs_bar_disabled_but_not_tied_low = (EMRS_DQS_BAR_DISABLE) && (dqs_bar[DATA_STROBE_NUM - 1 : 0] !== {DATA_STROBE_NUM{1'b0}}); |
| 461 | |
| 462 | err_unknown_clk_or_clkbar_or_cke = (!areset) && ((ck === 1'bx) || (ck_bar === 1'bx) || (cke === 1'bx)); |
| 463 | |
| 464 | err_unknown_value_on_precharge_pin_during_read_or_write = ((command == `READ) || (command == `WRITE)) && ((addr[10] !== 1'b1) && (addr[10] !== 1'b0)); |
| 465 | |
| 466 | err_unknown_col_or_bank_addr_during_read = ((command == `READ) && (((^addr[ROW_WIDTH - 1:0]) === 1'bx) || (^ba[2:0] === 1'bx))); |
| 467 | |
| 468 | err_unknown_col_or_bank_addr_during_write = ((command == `WRITE) && (((^addr[ROW_WIDTH - 1:0]) === 1'bx) || (^ba[2:0] === 1'bx))); |
| 469 | |
| 470 | err_unknown_row_or_bank_addr_during_active_cmd = ((command == `ACTIVE) && (((^addr[ROW_WIDTH - 1:0]) === 1'bx) || (^ba[2:0] === 1'bx))); |
| 471 | |
| 472 | err_unknown_bank_or_precharge_pin_during_precharge = ((command == `PRECHARGE) && ((addr[10] === 1'bx) || (^ba[2:0] === 1'bx))); |
| 473 | |
| 474 | err_sref_issued_when_bank_not_idle = (sref && !all_bank_idle); |
| 475 | |
| 476 | err_dqs_and_dqsbar_not_in_sync = ((!EMRS_DQS_BAR_DISABLE) ? (((dqs[DATA_STROBE_NUM - 1 : 0] !== {DATA_STROBE_NUM{1'bz}}) || (dqs_bar[DATA_STROBE_NUM - 1 : 0] !== {DATA_STROBE_NUM{1'bz}})) ? (dqs !== ~dqs_bar) : 1'b0 ) : 1'b0); |
| 477 | |
| 478 | err_unknown_value_on_odt_pin = (odt != 1'b1 && odt != 1'b0); |
| 479 | |
| 480 | err_ref_issued_when_bank_not_idle = (ref && !all_bank_idle); |
| 481 | |
| 482 | Ill_OCD_activity = ((command == `MRS) && (ba[0] == 1'b1 && ba[1] == 1'b0 && ba[2] == 1'b0) && ({addr[9],addr[8],addr[7]} != 3'b000) && is_init_done); |
| 483 | |
| 484 | end // init_done |
| 485 | end |
| 486 | |
| 487 | |
| 488 | // Rules: Sequential errors |
| 489 | |
| 490 | // err[1] |
| 491 | wire err_mrs_when_not_bank_idle = ddr2_err[1]; |
| 492 | // err[2] |
| 493 | wire err_mrs_to_any = ddr2_err[2]; |
| 494 | // err[3] |
| 495 | wire err_ref_to_any = ddr2_err[3]; |
| 496 | // err[4] |
| 497 | wire err_sref_to_rd = ddr2_err[4]; |
| 498 | // err[5] |
| 499 | wire err_sref_to_any_non_rd = ddr2_err[5]; |
| 500 | // err[6] |
| 501 | wire err_pwr_down = ddr2_err[6]; |
| 502 | // err[7] |
| 503 | wire err_active_pwr_down_exit_to_rd = ddr2_err[7]; |
| 504 | // err[8] |
| 505 | wire err_precharge_pwr_down_exit_to_non_rd = ddr2_err[8]; |
| 506 | // err[9] |
| 507 | wire err_cke_diasserted_when_not_pwr_down = ddr2_err[9]; |
| 508 | |
| 509 | wire err_sequential_activation_violation = seq_act_violation; |
| 510 | |
| 511 | // Initialization Errors (init_err) |
| 512 | wire Ill_cmd_before_init = init_err[0]; |
| 513 | wire Ill_cmd_during_init_pre_all_expected = init_err[1]; |
| 514 | wire Ill_cmd_during_init_EMRS2_expected = init_err[2]; |
| 515 | wire Ill_cmd_during_init_EMRS3_expected = init_err[3]; |
| 516 | wire Ill_cmd_during_init_EMRS_with_DLL_enable_expected = init_err[4]; |
| 517 | wire Ill_cmd_during_init_MRS_with_DLL_reset_expected = init_err[5]; |
| 518 | wire Ill_cmd_during_init_pre_all_after_MRS_expected = init_err[6]; |
| 519 | wire Ill_cmd_during_init_ref_expected = init_err[7]; |
| 520 | wire Ill_cmd_during_init_2_ref_expected = init_err[8]; |
| 521 | wire Ill_cmd_during_init_MRS_with_DLL_disable_expected = init_err[9]; |
| 522 | wire Ill_cmd_during_init_cke_not_low_for_200ns = init_err[10]; |
| 523 | wire Ill_cmd_during_init_pre_all_issued_early = init_err[11]; |
| 524 | wire Ill_cmd_during_init_odt_not_low = init_err[12]; |
| 525 | wire Ill_cmd_during_init_DLL_lock_time_violation = init_err[13]; |
| 526 | wire Ill_cmd_during_init_missing_OCD_calibration = init_err[14]; |
| 527 | wire err_No_EMRS_to_turn_OCD_mode_off = init_err[15]; |
| 528 | wire Ill_cmd_during_OCD_calibration = init_err[16]; |
| 529 | wire Ill_cmd_or_data_during_OCD_calibration = init_err[17]; |
| 530 | wire err_BL_not_4_during_OCD_calibration = init_err[18]; |
| 531 | wire err_exceeded_max_attempts_during_OCD_adjust = init_err[19]; |
| 532 | wire err_dq_or_dqs_not_driven_during_OCD_adjust = init_err[20]; |
| 533 | wire err_extra_dqs_during_OCD_adjust = init_err[21]; |
| 534 | |
| 535 | task finish_test; |
| 536 | input [512:0] message; |
| 537 | integer Failure_time; |
| 538 | |
| 539 | begin |
| 540 | Failure_time =$time; |
| 541 | `PR_ERROR("ddr2_monitor", `ERROR, " %s", message); |
| 542 | @(posedge ck); |
| 543 | @(posedge ck); |
| 544 | @(posedge ck); |
| 545 | `PR_ERROR("ddr2_monitor", `ERROR, "DDR2 monitor exiting because of ERROR at %d", Failure_time) ; |
| 546 | $finish; |
| 547 | end |
| 548 | endtask |
| 549 | |
| 550 | `ifdef DDR2_0IN_SIM_MON /*{{{*/ |
| 551 | |
| 552 | always @(posedge ck_bar) begin |
| 553 | `ifdef NO_err_cmd_BURST_STOP_CHECK |
| 554 | `else |
| 555 | if (err_cmd_BURST_STOP) |
| 556 | `PR_ERROR("ddr2_monitor", `ERROR, "err_cmd_BURST_STOP\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_cmd_BURST_STOP\n" ) -constraint |
| 557 | `endif |
| 558 | |
| 559 | `ifdef NO_err_bad_ba_for_mrs_CHECK |
| 560 | `else |
| 561 | if (err_bad_ba_for_mrs ) |
| 562 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_ba_for_mrs\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_bad_ba_for_mrs\n" ) -constraint |
| 563 | `endif |
| 564 | |
| 565 | `ifdef NO_err_bad_burst_len_CHECK |
| 566 | `else |
| 567 | if (err_bad_burst_len) |
| 568 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_burst_len\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_bad_burst_len\n" ) -constraint |
| 569 | `endif |
| 570 | |
| 571 | `ifdef NO_err_bad_addr_for_mrs_CHECK |
| 572 | `else |
| 573 | if(err_bad_addr_for_mrs) |
| 574 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_addr_for_mrs\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_bad_addr_for_mrs\n") -constraint |
| 575 | `endif |
| 576 | |
| 577 | `ifdef NO_err_bad_write_recover_CHECK |
| 578 | `else |
| 579 | if (err_bad_write_recover) |
| 580 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_write_recover\n "); // 0in < fire -message ("ERROR: DDR2_mon: err_bad_write_recover\n ") -constraint |
| 581 | `endif |
| 582 | |
| 583 | `ifdef NO_err_bad_cas_latency_CHECK |
| 584 | `else |
| 585 | if (err_bad_cas_latency ) |
| 586 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_cas_latency\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_bad_cas_latency \n") |
| 587 | |
| 588 | `endif |
| 589 | |
| 590 | `ifdef NO_err_bad_additive_latency_CHECK |
| 591 | `else |
| 592 | if (err_bad_additive_latency ) |
| 593 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_additive_latency \n"); // 0in < fire -message ("ERROR: DDR2_mon: err_bad_additive_latency \n") -constraint |
| 594 | `endif |
| 595 | |
| 596 | `ifdef NO_err_wr_dqs_not_asserted_when_wr_data_ready_CHECK |
| 597 | `else |
| 598 | if(err_wr_dqs_not_asserted_when_wr_data_ready) |
| 599 | `PR_ERROR("ddr2_monitor", `ERROR, " err_wr_dqs_not_asserted_when_wr_data_ready \n"); // 0in < fire -message ("ERROR: DDR2_mon: err_wr_dqs_not_asserted_when_wr_data_ready \n") -constraint |
| 600 | `endif |
| 601 | |
| 602 | `ifdef NO_err_rd_dqs_not_asserted_when_rd_data_ready_CHECK |
| 603 | `else |
| 604 | if(err_rd_dqs_not_asserted_when_rd_data_ready) |
| 605 | `PR_ERROR("ddr2_monitor", `ERROR, " err_rd_dqs_not_asserted_when_rd_data_ready \n"); // 0in < fire -message ("ERROR: DDR2_mon: err_rd_dqs_not_asserted_when_rd_data_ready \n") -constraint |
| 606 | `endif |
| 607 | |
| 608 | `ifdef NO_err_mrs_when_not_bank_idle_CHECK |
| 609 | `else |
| 610 | if (err_mrs_when_not_bank_idle ) |
| 611 | `PR_ERROR("ddr2_monitor", `ERROR, "err_mrs_when_not_bank_idle\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_mrs_when_not_bank_idle\n" ) |
| 612 | `endif |
| 613 | |
| 614 | `ifdef NO_err_mrs_to_any_CHECK |
| 615 | `else |
| 616 | if (err_mrs_to_any) |
| 617 | `PR_ERROR("ddr2_monitor", `ERROR, "err_mrs_to_any\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_mrs_to_any\n") |
| 618 | `endif |
| 619 | |
| 620 | `ifdef NO_err_ref_to_any_CHECK |
| 621 | `else |
| 622 | if (err_ref_to_any) |
| 623 | `PR_ERROR("ddr2_monitor", `ERROR, "err_ref_to_any\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_ref_to_any\n") |
| 624 | `endif |
| 625 | |
| 626 | `ifdef NO_err_sref_to_rd_CHECK |
| 627 | `else |
| 628 | if (err_sref_to_rd) |
| 629 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sref_to_rd\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_sref_to_rd\n" ) |
| 630 | `endif |
| 631 | |
| 632 | `ifdef NO_err_sref_to_any_non_rd_CHECK |
| 633 | `else |
| 634 | if (err_sref_to_any_non_rd) |
| 635 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sref_to_any_non_rd\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_sref_to_any_non_rd\n" ) |
| 636 | `endif |
| 637 | |
| 638 | `ifdef NO_err_pwr_down_CHECK |
| 639 | `else |
| 640 | if (err_pwr_down) |
| 641 | `PR_ERROR("ddr2_monitor", `ERROR, "err_pwr_down\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_pwr_down\n" ) |
| 642 | `endif |
| 643 | |
| 644 | `ifdef NO_err_active_pwr_down_exit_to_rd_CHECK |
| 645 | `else |
| 646 | if (err_active_pwr_down_exit_to_rd) |
| 647 | `PR_ERROR("ddr2_monitor", `ERROR, "err_active_pwr_down_exit_to_rd\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_active_pwr_down_exit_to_rd\n" ) |
| 648 | `endif |
| 649 | |
| 650 | `ifdef NO_err_precharge_pwr_down_exit_to_non_rd_CHECK |
| 651 | `else |
| 652 | if (err_precharge_pwr_down_exit_to_non_rd) |
| 653 | `PR_ERROR("ddr2_monitor", `ERROR, "err_precharge_pwr_down_exit_to_non_rd\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_precharge_pwr_down_exit_to_non_rd\n" ) |
| 654 | `endif |
| 655 | |
| 656 | `ifdef NO_err_cke_diasserted_when_not_pwr_down_CHECK |
| 657 | `else |
| 658 | if (err_cke_diasserted_when_not_pwr_down) |
| 659 | `PR_ERROR("ddr2_monitor", `ERROR, "err_cke_diasserted_when_not_pwr_down\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_cke_diasserted_when_not_pwr_down\n" ) |
| 660 | `endif |
| 661 | |
| 662 | `ifdef NO_err_sequential_activation_violation_CHECK |
| 663 | `else |
| 664 | if(err_sequential_activation_violation) |
| 665 | begin |
| 666 | // `PR_ERROR("ddr2_monitor", `ERROR, "err_sequential_activation_violation : More than 4 ACTIVE commands in a window of (tFAW_reg)."); // 0in < fire -message ("ERROR: DDR2_mon: err_sequential_activation_violation : More than 4 ACTIVE commands in a window of (tFAW_reg).") |
| 667 | $display ("ERROR: err_sequential_activation_violation\n"); |
| 668 | finish_test("err_sequential_activation_violation : More than 4 ACTIVE commands in a window of tFAW_reg."); |
| 669 | end |
| 670 | `endif |
| 671 | |
| 672 | `ifdef NO_Ill_cmd_before_init_CHECK |
| 673 | `else |
| 674 | if(Ill_cmd_before_init) |
| 675 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_before_init\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_before_init\n") |
| 676 | `endif |
| 677 | |
| 678 | `ifdef NO_Ill_cmd_during_init_pre_all_expected_CHECK |
| 679 | `else |
| 680 | if(Ill_cmd_during_init_pre_all_expected) |
| 681 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_pre_all_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_pre_all_expected\n") |
| 682 | `endif |
| 683 | |
| 684 | `ifdef NO_Ill_cmd_during_init_EMRS2_expected_CHECK |
| 685 | `else |
| 686 | if(Ill_cmd_during_init_EMRS2_expected) |
| 687 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_EMRS2_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_EMRS2_expected\n") |
| 688 | `endif |
| 689 | |
| 690 | `ifdef NO_Ill_cmd_during_init_EMRS3_expected_CHECK |
| 691 | `else |
| 692 | if(Ill_cmd_during_init_EMRS3_expected) |
| 693 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_EMRS3_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_EMRS3_expected\n") |
| 694 | `endif |
| 695 | |
| 696 | `ifdef NO_Ill_cmd_during_init_EMRS_with_DLL_enable_expected_CHECK |
| 697 | `else |
| 698 | if(Ill_cmd_during_init_EMRS_with_DLL_enable_expected) |
| 699 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_EMRS_with_DLL_enable_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_EMRS_with_DLL_enable_expected\n") |
| 700 | `endif |
| 701 | |
| 702 | `ifdef NO_Ill_cmd_during_init_MRS_with_DLL_reset_expected_CHECK |
| 703 | `else |
| 704 | if(Ill_cmd_during_init_MRS_with_DLL_reset_expected) |
| 705 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_MRS_with_DLL_reset_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_MRS_with_DLL_reset_expected\n") |
| 706 | `endif |
| 707 | |
| 708 | `ifdef NO_Ill_cmd_during_init_pre_all_after_MRS_expected_CHECK |
| 709 | `else |
| 710 | if(Ill_cmd_during_init_pre_all_after_MRS_expected) |
| 711 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_pre_all_after_MRS_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_pre_all_after_MRS_expected\n") |
| 712 | `endif |
| 713 | |
| 714 | `ifdef NO_Ill_cmd_during_init_ref_expected_CHECK |
| 715 | `else |
| 716 | if(Ill_cmd_during_init_ref_expected) |
| 717 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_ref_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_ref_expected\n") |
| 718 | `endif |
| 719 | |
| 720 | `ifdef NO_Ill_cmd_during_init_2_ref_expected_CHECK |
| 721 | `else |
| 722 | if(Ill_cmd_during_init_2_ref_expected) |
| 723 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_2_ref_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_2_ref_expected\n") |
| 724 | `endif |
| 725 | |
| 726 | `ifdef NO_Ill_cmd_during_init_MRS_with_DLL_disable_expected_CHECK |
| 727 | `else |
| 728 | if(Ill_cmd_during_init_MRS_with_DLL_disable_expected) |
| 729 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_MRS_with_DLL_disable_expected\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_MRS_with_DLL_disable_expected\n") |
| 730 | `endif |
| 731 | |
| 732 | `ifdef NO_Ill_cmd_during_init_cke_not_low_for_200ns_CHECK |
| 733 | `else |
| 734 | if(Ill_cmd_during_init_cke_not_low_for_200ns) |
| 735 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_cke_not_low_for_200ns\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_cke_not_low_for_200ns\n") |
| 736 | `endif |
| 737 | |
| 738 | `ifdef NO_Ill_cmd_during_init_pre_all_issued_early_CHECK |
| 739 | `else |
| 740 | if(Ill_cmd_during_init_pre_all_issued_early) |
| 741 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_pre_all_issued_early\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_pre_all_issued_early\n") |
| 742 | `endif |
| 743 | |
| 744 | `ifdef NO_Ill_cmd_during_init_odt_not_low_CHECK |
| 745 | `else |
| 746 | if(Ill_cmd_during_init_odt_not_low) |
| 747 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_odt_not_low\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_odt_not_low\n") |
| 748 | `endif |
| 749 | |
| 750 | `ifdef NO_Ill_cmd_during_init_DLL_lock_time_violation_CHECK |
| 751 | `else |
| 752 | if(Ill_cmd_during_init_DLL_lock_time_violation) |
| 753 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_DLL_lock_time_violation\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_DLL_lock_time_violation\n") |
| 754 | `endif |
| 755 | |
| 756 | `ifdef NO_Ill_cmd_during_init_missing_OCD_calibration_CHECK |
| 757 | `else |
| 758 | if(Ill_cmd_during_init_missing_OCD_calibration) |
| 759 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_missing_OCD_calibration\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_init_missing_OCD_calibration\n") |
| 760 | `endif |
| 761 | |
| 762 | `ifdef NO_No_EMRS_to_turn_OCD_mode_off_CHECK |
| 763 | `else |
| 764 | if(err_No_EMRS_to_turn_OCD_mode_off) |
| 765 | `PR_ERROR("ddr2_monitor", `ERROR, "err_No_EMRS_to_turn_OCD_mode_off\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_No_EMRS_to_turn_OCD_mode_off\n") |
| 766 | `endif |
| 767 | |
| 768 | `ifdef NO_Ill_cmd_during_OCD_calibration_CHECK |
| 769 | `else |
| 770 | if(Ill_cmd_during_OCD_calibration) |
| 771 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_OCD_calibration\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_during_OCD_calibration\n") |
| 772 | `endif |
| 773 | |
| 774 | `ifdef NO_err_normal_operation_started_with_DLL_reset_in_MRS_CHECK |
| 775 | `else |
| 776 | if( err_normal_operation_started_with_DLL_reset_in_MRS) |
| 777 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_with_DLL_reset_in_MRS\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_normal_operation_started_with_DLL_reset_in_MRS\n") |
| 778 | `endif |
| 779 | |
| 780 | `ifdef NO_err_normal_operation_started_with_TM_set_in_MRS_CHECK |
| 781 | `else |
| 782 | if( err_normal_operation_started_with_TM_set_in_MRS) |
| 783 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_with_TM_set_in_MRS\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_normal_operation_started_with_TM_set_in_MRS\n") |
| 784 | `endif |
| 785 | |
| 786 | `ifdef NO_err_normal_operation_started_without_DLL_enable_CHECK |
| 787 | `else |
| 788 | if( err_normal_operation_started_without_DLL_enable) |
| 789 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_without_DLL_enable\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_normal_operation_started_without_DLL_enable\n") |
| 790 | `endif |
| 791 | |
| 792 | `ifdef NO_err_normal_operation_started_without_initialization_CHECK |
| 793 | `else |
| 794 | if( err_normal_operation_started_without_initialization) |
| 795 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_without_initialization\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_normal_operation_started_without_initialization\n") |
| 796 | `endif |
| 797 | |
| 798 | `ifdef NO_err_invalid_ODT_value_RTT_in_EMRS_CHECK |
| 799 | `else |
| 800 | if( err_invalid_ODT_value_RTT_in_EMRS) |
| 801 | `PR_ERROR("ddr2_monitor", `ERROR, "err_invalid_ODT_value_RTT_in_EMRS\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_invalid_ODT_value_RTT_in_EMRS\n") |
| 802 | `endif |
| 803 | |
| 804 | `ifdef NO_err_unknown_value_in_MRS_or_EMRS_CHECK |
| 805 | `else |
| 806 | if(err_unknown_value_in_MRS_or_EMRS) |
| 807 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_value_in_MRS_or_EMRS\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_value_in_MRS_or_EMRS\n") |
| 808 | `endif |
| 809 | |
| 810 | `ifdef NO_err_invalid_cmd_CHECK |
| 811 | `else |
| 812 | if(err_invalid_cmd) |
| 813 | `PR_ERROR("ddr2_monitor", `ERROR, "err_invalid_cmd\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_invalid_cmd\n") |
| 814 | `endif |
| 815 | |
| 816 | `ifdef NO_err_clk_and_clkbar_not_in_sync_CHECK |
| 817 | `else |
| 818 | if(err_clk_and_clkbar_not_in_sync) |
| 819 | `PR_ERROR("ddr2_monitor", `ERROR, "err_clk_and_clkbar_not_in_sync\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_clk_and_clkbar_not_in_sync\n") |
| 820 | `endif |
| 821 | |
| 822 | `ifdef NO_err_dqs_bar_disabled_but_not_tied_low_CHECK |
| 823 | `else |
| 824 | if(err_dqs_bar_disabled_but_not_tied_low) |
| 825 | `PR_ERROR("ddr2_monitor", `ERROR, "err_dqs_bar_disabled_but_not_tied_low\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_dqs_bar_disabled_but_not_tied_low\n") |
| 826 | `endif |
| 827 | |
| 828 | `ifdef NO_err_unknown_clk_or_clkbar_CHECK |
| 829 | `else |
| 830 | if(err_unknown_clk_or_clkbar_or_cke) |
| 831 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_clk_or_clkbar_or_cke\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_clk_or_clkbar_or_cke\n") |
| 832 | `endif |
| 833 | |
| 834 | `ifdef NO_err_unknown_value_on_precharge_pin_during_read_or_write_CHECK |
| 835 | `else |
| 836 | if(err_unknown_value_on_precharge_pin_during_read_or_write) |
| 837 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_value_on_precharge_pin_during_read_or_write\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_value_on_precharge_pin_during_read_or_write\n") |
| 838 | `endif |
| 839 | |
| 840 | `ifdef NO_err_unknown_col_or_bank_addr_during_read_CHECK |
| 841 | `else |
| 842 | if(err_unknown_col_or_bank_addr_during_read) |
| 843 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_col_or_bank_addr_during_read\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_col_or_bank_addr_during_read\n") |
| 844 | `endif |
| 845 | |
| 846 | `ifdef NO_err_unknown_col_or_bank_addr_during_write_CHECK |
| 847 | `else |
| 848 | if(err_unknown_col_or_bank_addr_during_write) |
| 849 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_col_or_bank_addr_during_write\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_col_or_bank_addr_during_write\n") |
| 850 | `endif |
| 851 | |
| 852 | `ifdef NO_err_unknown_row_or_bank_addr_during_active_cmd_CHECK |
| 853 | `else |
| 854 | if(err_unknown_row_or_bank_addr_during_active_cmd) |
| 855 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_row_or_bank_addr_during_active_cmd\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_row_or_bank_addr_during_active_cmd\n") |
| 856 | `endif |
| 857 | |
| 858 | `ifdef NO_err_unknown_bank_or_precharge_pin_during_precharge_CHECK |
| 859 | `else |
| 860 | if(err_unknown_bank_or_precharge_pin_during_precharge) |
| 861 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_bank_or_precharge_pin_during_precharge\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_bank_or_precharge_pin_during_precharge\n") |
| 862 | `endif |
| 863 | |
| 864 | `ifdef NO_Ill_cmd_or_data_during_OCD_calibration_CHECK |
| 865 | `else |
| 866 | if(Ill_cmd_or_data_during_OCD_calibration) |
| 867 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_or_data_during_OCD_calibration\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_cmd_or_data_during_OCD_calibration\n") |
| 868 | `endif |
| 869 | |
| 870 | `ifdef NO_err_BL_not_4_during_OCD_calibration_CHECK |
| 871 | `else |
| 872 | if(err_BL_not_4_during_OCD_calibration) |
| 873 | `PR_ERROR("ddr2_monitor", `ERROR, "err_BL_not_4_during_OCD_calibration\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_BL_not_4_during_OCD_calibration\n") |
| 874 | `endif |
| 875 | |
| 876 | `ifdef NO_err_exceeded_max_attempts_during_OCD_adjust_CHECK |
| 877 | `else |
| 878 | if(err_exceeded_max_attempts_during_OCD_adjust) |
| 879 | `PR_ERROR("ddr2_monitor", `ERROR, "err_exceeded_max_attempts_during_OCD_adjust\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_exceeded_max_attempts_during_OCD_adjust\n") |
| 880 | `endif |
| 881 | |
| 882 | `ifdef NO_err_dq_or_dqs_not_driven_during_OCD_adjust_CHECK |
| 883 | `else |
| 884 | if(err_dq_or_dqs_not_driven_during_OCD_adjust) |
| 885 | `PR_ERROR("ddr2_monitor", `ERROR, "err_dq_or_dqs_not_driven_during_OCD_adjust\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_dq_or_dqs_not_driven_during_OCD_adjust\n") |
| 886 | `endif |
| 887 | |
| 888 | `ifdef NO_err_extra_dqs_during_OCD_adjust_CHECK |
| 889 | `else |
| 890 | if(err_extra_dqs_during_OCD_adjust) |
| 891 | `PR_ERROR("ddr2_monitor", `ERROR, "err_extra_dqs_during_OCD_adjust\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_extra_dqs_during_OCD_adjust\n") |
| 892 | `endif |
| 893 | |
| 894 | `ifdef NO_err_sref_issued_when_bank_not_idle_CHECK |
| 895 | `else |
| 896 | if(err_sref_issued_when_bank_not_idle) |
| 897 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sref_issued_when_bank_not_idle\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_sref_issued_when_bank_not_idle\n") |
| 898 | `endif |
| 899 | |
| 900 | `ifdef NO_err_dqs_and_dqsbar_not_in_sync_CHECK |
| 901 | `else |
| 902 | if(err_dqs_and_dqsbar_not_in_sync) |
| 903 | `PR_ERROR("ddr2_monitor", `ERROR, "err_dqs_and_dqsbar_not_in_sync\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_dqs_and_dqsbar_not_in_sync\n") |
| 904 | `endif |
| 905 | |
| 906 | `ifdef NO_err_unknown_value_on_odt_pin_CHECK |
| 907 | `else |
| 908 | if(err_unknown_value_on_odt_pin) |
| 909 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_value_on_odt_pin\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_unknown_value_on_odt_pin\n") |
| 910 | `endif |
| 911 | |
| 912 | `ifdef NO_err_ref_issued_when_bank_not_idle_CHECK |
| 913 | `else |
| 914 | if(err_ref_issued_when_bank_not_idle) |
| 915 | `PR_ERROR("ddr2_monitor", `ERROR, "err_ref_issued_when_bank_not_idle\n"); // 0in < fire -message ("ERROR: DDR2_mon: err_ref_issued_when_bank_not_idle\n") |
| 916 | `endif |
| 917 | |
| 918 | `ifdef NO_Ill_OCD_activity_CHECK |
| 919 | `else |
| 920 | if(Ill_OCD_activity) |
| 921 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_OCD_activity\n"); // 0in < fire -message ("ERROR: DDR2_mon: Ill_OCD_activity\n") |
| 922 | `endif |
| 923 | |
| 924 | end // always |
| 925 | |
| 926 | `else /*}}}*/ |
| 927 | `ifdef DDR2_OVA_SIM_MON /*{{{*/ |
| 928 | |
| 929 | always @(posedge ck_bar) begin |
| 930 | `ifdef NO_err_cmd_BURST_STOP_CHECK |
| 931 | `else |
| 932 | if (err_cmd_BURST_STOP) |
| 933 | `PR_ERROR("ddr2_monitor", `ERROR, "err_cmd_BURST_STOP\n"); |
| 934 | /* ova ova_asserted ddr2_ova1 |
| 935 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_cmd_BURST_STOP\n", `SEVERITY, `CATEGORY) |
| 936 | (!(areset), ck, !(err_cmd_BURST_STOP), `START, `STOP ); */ |
| 937 | `endif |
| 938 | |
| 939 | `ifdef NO_err_bad_ba_for_mrs_CHECK |
| 940 | `else |
| 941 | if (err_bad_ba_for_mrs) |
| 942 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_ba_for_mrs\n"); |
| 943 | /* ova ova_asserted ddr2_ova2 |
| 944 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_bad_ba_for_mrs\n", `SEVERITY, `CATEGORY) |
| 945 | (!(areset), ck, !(err_bad_ba_for_mrs), `START, `STOP ); */ |
| 946 | `endif |
| 947 | |
| 948 | `ifdef NO_err_bad_burst_len_CHECK |
| 949 | `else |
| 950 | if (err_bad_burst_len) |
| 951 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_burst_len\n"); |
| 952 | /* ova ova_asserted ddr2_ova3 |
| 953 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_bad_burst_len\n", `SEVERITY, `CATEGORY) |
| 954 | (!(areset), ck, !(err_bad_burst_len), `START, `STOP ); */ |
| 955 | `endif |
| 956 | |
| 957 | `ifdef NO_err_bad_addr_for_mrs_CHECK |
| 958 | `else |
| 959 | if(err_bad_addr_for_mrs) |
| 960 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_addr_for_mrs\n"); |
| 961 | /* ova ova_asserted ddr2_ova4 |
| 962 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_bad_addr_for_mrs\n", `SEVERITY, `CATEGORY) |
| 963 | (!(areset), ck, !(err_bad_addr_for_mrs), `START, `STOP ); */ |
| 964 | `endif |
| 965 | |
| 966 | `ifdef NO_err_bad_write_recover_CHECK |
| 967 | `else |
| 968 | if (err_bad_write_recover) |
| 969 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_write_recover\n "); |
| 970 | /* ova ova_asserted ddr2_ova5 |
| 971 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_bad_write_recover\n", `SEVERITY, `CATEGORY) |
| 972 | (!(areset), ck, !(err_bad_write_recover), `START, `STOP ); */ |
| 973 | `endif |
| 974 | |
| 975 | `ifdef NO_err_bad_cas_latency_CHECK |
| 976 | `else |
| 977 | if (err_bad_cas_latency) |
| 978 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_cas_latency\n"); |
| 979 | /* ova ova_asserted ddr2_ova6 |
| 980 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_bad_cas_latency\n", `SEVERITY, `CATEGORY) |
| 981 | (!(areset), ck, !(err_bad_cas_latency), `START, `STOP ); */ |
| 982 | `endif |
| 983 | |
| 984 | `ifdef NO_err_bad_additive_latency_CHECK |
| 985 | `else |
| 986 | if (err_bad_additive_latency) |
| 987 | `PR_ERROR("ddr2_monitor", `ERROR, "err_bad_additive_latency \n"); |
| 988 | /* ova ova_asserted ddr2_ova7 |
| 989 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_bad_additive_latency\n", `SEVERITY, `CATEGORY) |
| 990 | (!(areset), ck, !(err_bad_additive_latency), `START, `STOP ); */ |
| 991 | `endif |
| 992 | |
| 993 | `ifdef NO_err_wr_dqs_not_asserted_when_wr_data_ready_CHECK |
| 994 | `else |
| 995 | if(err_wr_dqs_not_asserted_when_wr_data_ready) |
| 996 | `PR_ERROR("ddr2_monitor", `ERROR, " err_wr_dqs_not_asserted_when_wr_data_ready \n"); |
| 997 | /* ova ova_asserted ddr2_ova8 |
| 998 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_wr_dqs_not_asserted_when_wr_data_ready\n", `SEVERITY, `CATEGORY) |
| 999 | (!(areset), ck, !(err_wr_dqs_not_asserted_when_wr_data_ready), `START, `STOP ); */ |
| 1000 | `endif |
| 1001 | |
| 1002 | `ifdef NO_err_rd_dqs_not_asserted_when_rd_data_ready_CHECK |
| 1003 | `else |
| 1004 | if(err_rd_dqs_not_asserted_when_rd_data_ready) |
| 1005 | `PR_ERROR("ddr2_monitor", `ERROR, " err_rd_dqs_not_asserted_when_rd_data_ready \n"); |
| 1006 | /* ova ova_asserted ddr2_ova9 |
| 1007 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_rd_dqs_not_asserted_when_rd_data_ready\n", `SEVERITY, `CATEGORY) |
| 1008 | (!(areset), ck, !(err_rd_dqs_not_asserted_when_rd_data_ready), `START, `STOP ); */ |
| 1009 | `endif |
| 1010 | |
| 1011 | `ifdef NO_err_mrs_when_not_bank_idle_CHECK |
| 1012 | `else |
| 1013 | if (err_mrs_when_not_bank_idle) |
| 1014 | `PR_ERROR("ddr2_monitor", `ERROR, "err_mrs_when_not_bank_idle\n"); |
| 1015 | /* ova ova_asserted ddr2_ova10 |
| 1016 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_mrs_when_not_bank_idle\n", `SEVERITY, `CATEGORY) |
| 1017 | (!(areset), ck, !(err_mrs_when_not_bank_idle), `START, `STOP ); */ |
| 1018 | `endif |
| 1019 | |
| 1020 | `ifdef NO_err_mrs_to_any_CHECK |
| 1021 | `else |
| 1022 | if (err_mrs_to_any) |
| 1023 | `PR_ERROR("ddr2_monitor", `ERROR, "err_mrs_to_any\n"); |
| 1024 | /* ova ova_asserted ddr2_ova11 |
| 1025 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_mrs_to_any\n", `SEVERITY, `CATEGORY) |
| 1026 | (!(areset), ck, !(err_mrs_to_any), `START, `STOP ); */ |
| 1027 | `endif |
| 1028 | |
| 1029 | `ifdef NO_err_ref_to_any_CHECK |
| 1030 | `else |
| 1031 | if (err_ref_to_any) |
| 1032 | `PR_ERROR("ddr2_monitor", `ERROR, "err_ref_to_any\n"); |
| 1033 | /* ova ova_asserted ddr2_ova12 |
| 1034 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_ref_to_any\n", `SEVERITY, `CATEGORY) |
| 1035 | (!(areset), ck, !(err_ref_to_any), `START, `STOP ); */ |
| 1036 | `endif |
| 1037 | |
| 1038 | `ifdef NO_err_sref_to_rd_CHECK |
| 1039 | `else |
| 1040 | if (err_sref_to_rd) |
| 1041 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sref_to_rd\n"); |
| 1042 | /* ova ova_asserted ddr2_ova13 |
| 1043 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_sref_to_rd\n", `SEVERITY, `CATEGORY) |
| 1044 | (!(areset), ck, !(err_sref_to_rd), `START, `STOP ); */ |
| 1045 | `endif |
| 1046 | |
| 1047 | `ifdef NO_err_sref_to_any_non_rd_CHECK |
| 1048 | `else |
| 1049 | if (err_sref_to_any_non_rd) |
| 1050 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sref_to_any_non_rd\n"); |
| 1051 | /* ova ova_asserted ddr2_ova14 |
| 1052 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_sref_to_any_non_rd\n", `SEVERITY, `CATEGORY) |
| 1053 | (!(areset), ck, !(err_sref_to_any_non_rd), `START, `STOP ); */ |
| 1054 | `endif |
| 1055 | |
| 1056 | `ifdef NO_err_pwr_down_CHECK |
| 1057 | `else |
| 1058 | if (err_pwr_down) |
| 1059 | `PR_ERROR("ddr2_monitor", `ERROR, "err_pwr_down\n"); |
| 1060 | /* ova ova_asserted ddr2_ova15 |
| 1061 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_pwr_down\n", `SEVERITY, `CATEGORY) |
| 1062 | (!(areset), ck, !(err_pwr_down), `START, `STOP ); */ |
| 1063 | `endif |
| 1064 | |
| 1065 | `ifdef NO_err_active_pwr_down_exit_to_rd_CHECK |
| 1066 | `else |
| 1067 | if (err_active_pwr_down_exit_to_rd) |
| 1068 | `PR_ERROR("ddr2_monitor", `ERROR, "err_active_pwr_down_exit_to_rd\n"); |
| 1069 | /* ova ova_asserted ddr2_ova16 |
| 1070 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_active_pwr_down_exit_to_rd\n", `SEVERITY, `CATEGORY) |
| 1071 | (!(areset), ck, !(err_active_pwr_down_exit_to_rd), `START, `STOP ); */ |
| 1072 | `endif |
| 1073 | |
| 1074 | `ifdef NO_err_precharge_pwr_down_exit_to_non_rd_CHECK |
| 1075 | `else |
| 1076 | if (err_precharge_pwr_down_exit_to_non_rd) |
| 1077 | `PR_ERROR("ddr2_monitor", `ERROR, "err_precharge_pwr_down_exit_to_non_rd\n"); |
| 1078 | /* ova ova_asserted ddr2_ova17 |
| 1079 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_precharge_pwr_down_exit_to_non_rd\n", `SEVERITY, `CATEGORY) |
| 1080 | (!(areset), ck, !(err_precharge_pwr_down_exit_to_non_rd), `START, `STOP ); */ |
| 1081 | `endif |
| 1082 | |
| 1083 | `ifdef NO_err_cke_diasserted_when_not_pwr_down_CHECK |
| 1084 | `else |
| 1085 | if (err_cke_diasserted_when_not_pwr_down) |
| 1086 | `PR_ERROR("ddr2_monitor", `ERROR, "err_cke_diasserted_when_not_pwr_down\n"); |
| 1087 | /* ova ova_asserted ddr2_ova18 |
| 1088 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_cke_diasserted_when_not_pwr_down\n", `SEVERITY, `CATEGORY) |
| 1089 | (!(areset), ck, !(err_cke_diasserted_when_not_pwr_down), `START, `STOP ); */ |
| 1090 | `endif |
| 1091 | |
| 1092 | `ifdef NO_err_sequential_activation_violation_CHECK |
| 1093 | `else |
| 1094 | if(err_sequential_activation_violation) |
| 1095 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sequential_activation_violation : More than 4 ACTIVE commands in a window of (tFAW_reg)."); |
| 1096 | /* ova ova_asserted ddr2_ova19 |
| 1097 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_sequential_activation_violation\n", `SEVERITY, `CATEGORY) |
| 1098 | (!(areset), ck, !(err_sequential_activation_violation), `START, `STOP ); */ |
| 1099 | `endif |
| 1100 | |
| 1101 | `ifdef NO_Ill_cmd_before_init_CHECK |
| 1102 | `else |
| 1103 | if(Ill_cmd_before_init) |
| 1104 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_before_init\n"); |
| 1105 | /* ova ova_asserted ddr2_ova20 |
| 1106 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_before_init\n", `SEVERITY, `CATEGORY) |
| 1107 | (!(areset), ck, !(Ill_cmd_before_init), `START, `STOP); */ |
| 1108 | `endif |
| 1109 | |
| 1110 | `ifdef NO_Ill_cmd_during_init_pre_all_expected_CHECK |
| 1111 | `else |
| 1112 | if(Ill_cmd_during_init_pre_all_expected) |
| 1113 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_pre_all_expected\n"); |
| 1114 | /* ova ova_asserted ddr2_ova21 |
| 1115 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_pre_all_expected\n", `SEVERITY, `CATEGORY) |
| 1116 | (!(areset), ck, !(Ill_cmd_during_init_pre_all_expected), `START, `STOP); */ |
| 1117 | `endif |
| 1118 | |
| 1119 | `ifdef NO_Ill_cmd_during_init_EMRS2_expected_CHECK |
| 1120 | `else |
| 1121 | if(Ill_cmd_during_init_EMRS2_expected) |
| 1122 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_EMRS2_expected\n"); |
| 1123 | /* ova ova_asserted ddr2_ova22 |
| 1124 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_EMRS2_expected\n", `SEVERITY, `CATEGORY) |
| 1125 | (!(areset), ck, !(Ill_cmd_during_init_EMRS2_expected), `START, `STOP); */ |
| 1126 | `endif |
| 1127 | |
| 1128 | `ifdef NO_Ill_cmd_during_init_EMRS3_expected_CHECK |
| 1129 | `else |
| 1130 | if(Ill_cmd_during_init_EMRS3_expected) |
| 1131 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_EMRS3_expected\n"); |
| 1132 | /* ova ova_asserted ddr2_ova23 |
| 1133 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_EMRS3_expected\n", `SEVERITY, `CATEGORY) |
| 1134 | (!(areset), ck, !(Ill_cmd_during_init_EMRS3_expected), `START, `STOP); */ |
| 1135 | `endif |
| 1136 | |
| 1137 | `ifdef NO_Ill_cmd_during_init_EMRS_with_DLL_enable_expected_CHECK |
| 1138 | `else |
| 1139 | if(Ill_cmd_during_init_EMRS_with_DLL_enable_expected) |
| 1140 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_EMRS_with_DLL_enable_expected\n"); |
| 1141 | /* ova ova_asserted ddr2_ova24 |
| 1142 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_EMRS_with_DLL_enable_expected\n", `SEVERITY, `CATEGORY) |
| 1143 | (!(areset), ck, !(Ill_cmd_during_init_EMRS_with_DLL_enable_expected), `START, `STOP); */ |
| 1144 | `endif |
| 1145 | |
| 1146 | `ifdef NO_Ill_cmd_during_init_MRS_with_DLL_reset_expected_CHECK |
| 1147 | `else |
| 1148 | if(Ill_cmd_during_init_MRS_with_DLL_reset_expected) |
| 1149 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_MRS_with_DLL_reset_expected\n"); |
| 1150 | /* ova ova_asserted ddr2_ova25 |
| 1151 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_MRS_with_DLL_reset_expected\n", `SEVERITY, `CATEGORY) |
| 1152 | (!(areset), ck, !(Ill_cmd_during_init_MRS_with_DLL_reset_expected), `START, `STOP); */ |
| 1153 | `endif |
| 1154 | |
| 1155 | `ifdef NO_Ill_cmd_during_init_pre_all_after_MRS_expected_CHECK |
| 1156 | `else |
| 1157 | if(Ill_cmd_during_init_pre_all_after_MRS_expected) |
| 1158 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_pre_all_after_MRS_expected\n"); |
| 1159 | /* ova ova_asserted ddr2_ova26 |
| 1160 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_pre_all_after_MRS_expected\n", `SEVERITY, `CATEGORY) |
| 1161 | (!(areset), ck, !(Ill_cmd_during_init_pre_all_after_MRS_expected), `START, `STOP); */ |
| 1162 | `endif |
| 1163 | |
| 1164 | `ifdef NO_Ill_cmd_during_init_ref_expected_CHECK |
| 1165 | `else |
| 1166 | if(Ill_cmd_during_init_ref_expected) |
| 1167 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_ref_expected\n"); |
| 1168 | /* ova ova_asserted ddr2_ova27 |
| 1169 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_ref_expected\n", `SEVERITY, `CATEGORY) |
| 1170 | (!(areset), ck, !(Ill_cmd_during_init_ref_expected), `START, `STOP); */ |
| 1171 | `endif |
| 1172 | |
| 1173 | `ifdef NO_Ill_cmd_during_init_2_ref_expected_CHECK |
| 1174 | `else |
| 1175 | if(Ill_cmd_during_init_2_ref_expected) |
| 1176 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_2_ref_expected\n"); |
| 1177 | /* ova ova_asserted ddr2_ova28 |
| 1178 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_2_ref_expected\n", `SEVERITY, `CATEGORY) |
| 1179 | (!(areset), ck, !(Ill_cmd_during_init_2_ref_expected), `START, `STOP); */ |
| 1180 | `endif |
| 1181 | |
| 1182 | `ifdef NO_Ill_cmd_during_init_MRS_with_DLL_disable_expected_CHECK |
| 1183 | `else |
| 1184 | if(Ill_cmd_during_init_MRS_with_DLL_disable_expected) |
| 1185 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_MRS_with_DLL_disable_expected\n"); |
| 1186 | /* ova ova_asserted ddr2_ova29 |
| 1187 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_MRS_with_DLL_disable_expected\n", `SEVERITY, `CATEGORY) |
| 1188 | (!(areset), ck, !(Ill_cmd_during_init_MRS_with_DLL_disable_expected), `START, `STOP); */ |
| 1189 | `endif |
| 1190 | |
| 1191 | `ifdef NO_Ill_cmd_during_init_cke_not_low_for_200ns_CHECK |
| 1192 | `else |
| 1193 | if(Ill_cmd_during_init_cke_not_low_for_200ns) |
| 1194 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_cke_not_low_for_200ns\n"); |
| 1195 | /* ova ova_asserted ddr2_ova30 |
| 1196 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_cke_not_low_for_200ns\n", `SEVERITY, `CATEGORY) |
| 1197 | (!(areset), ck, !(Ill_cmd_during_init_cke_not_low_for_200ns), `START, `STOP); */ |
| 1198 | `endif |
| 1199 | |
| 1200 | `ifdef NO_Ill_cmd_during_init_pre_all_issued_early_CHECK |
| 1201 | `else |
| 1202 | if(Ill_cmd_during_init_pre_all_issued_early) |
| 1203 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_pre_all_issued_early\n"); |
| 1204 | /* ova ova_asserted ddr2_ova31 |
| 1205 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_pre_all_issued_early\n", `SEVERITY, `CATEGORY) |
| 1206 | (!(areset), ck, !(Ill_cmd_during_init_pre_all_issued_early), `START, `STOP); */ |
| 1207 | `endif |
| 1208 | |
| 1209 | `ifdef NO_Ill_cmd_during_init_odt_not_low_CHECK |
| 1210 | `else |
| 1211 | if(Ill_cmd_during_init_odt_not_low) |
| 1212 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_odt_not_low\n"); |
| 1213 | /* ova ova_asserted ddr2_ova32 |
| 1214 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_odt_not_low\n", `SEVERITY, `CATEGORY) |
| 1215 | (!(areset), ck, !(Ill_cmd_during_init_odt_not_low), `START, `STOP); */ |
| 1216 | `endif |
| 1217 | |
| 1218 | `ifdef NO_Ill_cmd_during_init_DLL_lock_time_violation_CHECK |
| 1219 | `else |
| 1220 | if(Ill_cmd_during_init_DLL_lock_time_violation) |
| 1221 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_DLL_lock_time_violation\n"); |
| 1222 | /* ova ova_asserted ddr2_ova33 |
| 1223 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_DLL_lock_time_violation\n", `SEVERITY, `CATEGORY) |
| 1224 | (!(areset), ck, !(Ill_cmd_during_init_DLL_lock_time_violation), `START, `STOP); */ |
| 1225 | `endif |
| 1226 | |
| 1227 | `ifdef NO_Ill_cmd_during_init_missing_OCD_calibration_CHECK |
| 1228 | `else |
| 1229 | if(Ill_cmd_during_init_missing_OCD_calibration) |
| 1230 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_init_missing_OCD_calibration\n"); |
| 1231 | /* ova ova_asserted ddr2_ova34 |
| 1232 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_init_missing_OCD_calibration\n", `SEVERITY, `CATEGORY) |
| 1233 | (!(areset), ck, !(Ill_cmd_during_init_missing_OCD_calibration), `START, `STOP); */ |
| 1234 | `endif |
| 1235 | |
| 1236 | `ifdef NO_err_No_EMRS_to_turn_OCD_mode_off_CHECK |
| 1237 | `else |
| 1238 | if(err_No_EMRS_to_turn_OCD_mode_off) |
| 1239 | `PR_ERROR("ddr2_monitor", `ERROR, "err_No_EMRS_to_turn_OCD_mode_off\n"); |
| 1240 | /* ova ova_asserted ddr2_ova35 |
| 1241 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_No_EMRS_to_turn_OCD_mode_off\n", `SEVERITY, `CATEGORY) |
| 1242 | (!(areset), ck, !(err_No_EMRS_to_turn_OCD_mode_off), `START, `STOP); */ |
| 1243 | `endif |
| 1244 | |
| 1245 | `ifdef NO_Ill_cmd_during_OCD_calibration_CHECK |
| 1246 | `else |
| 1247 | if(Ill_cmd_during_OCD_calibration) |
| 1248 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_during_OCD_calibration\n"); |
| 1249 | /* ova ova_asserted ddr2_ova36 |
| 1250 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_during_OCD_calibration\n", `SEVERITY, `CATEGORY) |
| 1251 | (!(areset), ck, !(Ill_cmd_during_OCD_calibration), `START, `STOP); */ |
| 1252 | `endif |
| 1253 | |
| 1254 | `ifdef NO_err_normal_operation_started_with_DLL_reset_in_MRS_CHECK |
| 1255 | `else |
| 1256 | if( err_normal_operation_started_with_DLL_reset_in_MRS) |
| 1257 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_with_DLL_reset_in_MRS\n"); |
| 1258 | /* ova ova_asserted ddr2_ova37 |
| 1259 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_normal_operation_started_with_DLL_reset_in_MRS\n", `SEVERITY, `CATEGORY) |
| 1260 | (!(areset), ck, !(err_normal_operation_started_with_DLL_reset_in_MRS), `START, `STOP); */ |
| 1261 | `endif |
| 1262 | |
| 1263 | `ifdef NO_err_normal_operation_started_with_TM_set_in_MRS_CHECK |
| 1264 | `else |
| 1265 | if( err_normal_operation_started_with_TM_set_in_MRS) |
| 1266 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_with_TM_set_in_MRS\n"); |
| 1267 | /* ova ova_asserted ddr2_ova38 |
| 1268 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_normal_operation_started_with_TM_set_in_MRS\n", `SEVERITY, `CATEGORY) |
| 1269 | (!(areset), ck, !(err_normal_operation_started_with_TM_set_in_MRS), `START, `STOP); */ |
| 1270 | `endif |
| 1271 | |
| 1272 | `ifdef NO_err_normal_operation_started_without_DLL_enable_CHECK |
| 1273 | `else |
| 1274 | if( err_normal_operation_started_without_DLL_enable) |
| 1275 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_without_DLL_enable\n"); |
| 1276 | /* ova ova_asserted ddr2_ova39 |
| 1277 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_normal_operation_started_without_DLL_enable\n", `SEVERITY, `CATEGORY) |
| 1278 | (!(areset), ck, !(err_normal_operation_started_without_DLL_enable), `START, `STOP); */ |
| 1279 | `endif |
| 1280 | |
| 1281 | `ifdef NO_err_normal_operation_started_without_initialization_CHECK |
| 1282 | `else |
| 1283 | if( err_normal_operation_started_without_initialization) |
| 1284 | `PR_ERROR("ddr2_monitor", `ERROR, "err_normal_operation_started_without_initialization\n"); |
| 1285 | /* ova ova_asserted ddr2_ova40 |
| 1286 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_normal_operation_started_without_initialization\n", `SEVERITY, `CATEGORY) |
| 1287 | (!(areset), ck, !(err_normal_operation_started_without_initialization), `START, `STOP); */ |
| 1288 | |
| 1289 | `endif |
| 1290 | |
| 1291 | `ifdef NO_err_invalid_ODT_value_RTT_in_EMRS_CHECK |
| 1292 | `else |
| 1293 | if( err_invalid_ODT_value_RTT_in_EMRS) |
| 1294 | `PR_ERROR("ddr2_monitor", `ERROR, "err_invalid_ODT_value_RTT_in_EMRS\n"); |
| 1295 | /* ova ova_asserted ddr2_ova41 |
| 1296 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_invalid_ODT_value_RTT_in_EMRS\n", `SEVERITY, `CATEGORY) |
| 1297 | (!(areset), ck, !(err_invalid_ODT_value_RTT_in_EMRS), `START, `STOP); */ |
| 1298 | `endif |
| 1299 | |
| 1300 | `ifdef NO_err_unknown_value_in_MRS_or_EMRS_CHECK |
| 1301 | `else |
| 1302 | if(err_unknown_value_in_MRS_or_EMRS) |
| 1303 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_value_in_MRS_or_EMRS\n"); |
| 1304 | /* ova ova_asserted ddr2_ova42 |
| 1305 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_value_in_MRS_or_EMRS\n", `SEVERITY, `CATEGORY) |
| 1306 | (!(areset), ck, !(err_unknown_value_in_MRS_or_EMRS), `START, `STOP); */ |
| 1307 | `endif |
| 1308 | |
| 1309 | `ifdef NO_err_invalid_cmd_CHECK |
| 1310 | `else |
| 1311 | if(err_invalid_cmd) |
| 1312 | `PR_ERROR("ddr2_monitor", `ERROR, "err_invalid_cmd\n"); |
| 1313 | /* ova ova_asserted ddr2_ova43 |
| 1314 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_invalid_cmd\n", `SEVERITY, `CATEGORY) |
| 1315 | (!(areset), ck, !(err_invalid_cmd), `START, `STOP); */ |
| 1316 | `endif |
| 1317 | |
| 1318 | `ifdef NO_err_clk_and_clkbar_not_in_sync_CHECK |
| 1319 | `else |
| 1320 | if(err_clk_and_clkbar_not_in_sync) |
| 1321 | `PR_ERROR("ddr2_monitor", `ERROR, "err_clk_and_clkbar_not_in_sync\n"); |
| 1322 | /* ova ova_asserted ddr2_ova44 |
| 1323 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_clk_and_clkbar_not_in_sync\n", `SEVERITY, `CATEGORY) |
| 1324 | (!(areset), ck, !(err_clk_and_clkbar_not_in_sync), `START, `STOP); */ |
| 1325 | `endif |
| 1326 | |
| 1327 | `ifdef NO_err_dqs_bar_disabled_but_not_tied_low_CHECK |
| 1328 | `else |
| 1329 | if(err_dqs_bar_disabled_but_not_tied_low) |
| 1330 | `PR_ERROR("ddr2_monitor", `ERROR, "err_dqs_bar_disabled_but_not_tied_low\n"); |
| 1331 | /* ova ova_asserted ddr2_ova45 |
| 1332 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_dqs_bar_disabled_but_not_tied_low\n", `SEVERITY, `CATEGORY) |
| 1333 | (!(areset), ck, !(err_dqs_bar_disabled_but_not_tied_low), `START, `STOP); */ |
| 1334 | `endif |
| 1335 | |
| 1336 | `ifdef NO_err_unknown_clk_or_clkbar_CHECK |
| 1337 | `else |
| 1338 | if(err_unknown_clk_or_clkbar_or_cke) |
| 1339 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_clk_or_clkbar_or_cke\n"); |
| 1340 | /* ova ova_asserted ddr2_ova46 |
| 1341 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_clk_or_clkbar_or_cke\n", `SEVERITY, `CATEGORY) |
| 1342 | (!(areset), ck, !(err_unknown_clk_or_clkbar_or_cke), `START, `STOP); */ |
| 1343 | `endif |
| 1344 | |
| 1345 | `ifdef NO_err_unknown_value_on_precharge_pin_during_read_or_write_CHECK |
| 1346 | `else |
| 1347 | if(err_unknown_value_on_precharge_pin_during_read_or_write) |
| 1348 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_value_on_precharge_pin_during_read_or_write\n"); |
| 1349 | /* ova ova_asserted ddr2_ova47 |
| 1350 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_value_on_precharge_pin_during_read_or_write\n", `SEVERITY, `CATEGORY) |
| 1351 | (!(areset), ck, !(err_unknown_value_on_precharge_pin_during_read_or_write), `START, `STOP); */ |
| 1352 | `endif |
| 1353 | |
| 1354 | `ifdef NO_err_unknown_col_or_bank_addr_during_read_CHECK |
| 1355 | `else |
| 1356 | if(err_unknown_col_or_bank_addr_during_read) |
| 1357 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_col_or_bank_addr_during_read\n"); |
| 1358 | /* ova ova_asserted ddr2_ova48 |
| 1359 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_col_or_bank_addr_during_read\n", `SEVERITY, `CATEGORY) |
| 1360 | (!(areset), ck, !(err_unknown_col_or_bank_addr_during_read), `START, `STOP); */ |
| 1361 | `endif |
| 1362 | |
| 1363 | `ifdef NO_err_unknown_col_or_bank_addr_during_write_CHECK |
| 1364 | `else |
| 1365 | if(err_unknown_col_or_bank_addr_during_write) |
| 1366 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_col_or_bank_addr_during_write\n"); |
| 1367 | /* ova ova_asserted ddr2_ova49 |
| 1368 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_col_or_bank_addr_during_write\n", `SEVERITY, `CATEGORY) |
| 1369 | (!(areset), ck, !(err_unknown_col_or_bank_addr_during_write), `START, `STOP); */ |
| 1370 | `endif |
| 1371 | |
| 1372 | `ifdef NO_err_unknown_row_or_bank_addr_during_active_cmd_CHECK |
| 1373 | `else |
| 1374 | if(err_unknown_row_or_bank_addr_during_active_cmd) |
| 1375 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_row_or_bank_addr_during_active_cmd\n"); |
| 1376 | /* ova ova_asserted ddr2_ova50 |
| 1377 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_row_or_bank_addr_during_active_cmd\n", `SEVERITY, `CATEGORY) |
| 1378 | (!(areset), ck, !(err_unknown_row_or_bank_addr_during_active_cmd), `START, `STOP); */ |
| 1379 | `endif |
| 1380 | |
| 1381 | `ifdef NO_err_unknown_bank_or_precharge_pin_during_precharge_CHECK |
| 1382 | `else |
| 1383 | if(err_unknown_bank_or_precharge_pin_during_precharge) |
| 1384 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_bank_or_precharge_pin_during_precharge\n"); |
| 1385 | /* ova ova_asserted ddr2_ova51 |
| 1386 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_bank_or_precharge_pin_during_precharge\n", `SEVERITY, `CATEGORY) |
| 1387 | (!(areset), ck, !(err_unknown_bank_or_precharge_pin_during_precharge), `START, `STOP); */ |
| 1388 | `endif |
| 1389 | |
| 1390 | `ifdef NO_Ill_cmd_or_data_during_OCD_calibration_CHECK |
| 1391 | `else |
| 1392 | if(Ill_cmd_or_data_during_OCD_calibration) |
| 1393 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_or_data_during_OCD_calibration\n"); |
| 1394 | /* ova ova_asserted ddr2_ova52 |
| 1395 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_cmd_or_data_during_OCD_calibration\n", `SEVERITY, `CATEGORY) |
| 1396 | (!(areset), ck, !(Ill_cmd_or_data_during_OCD_calibration), `START, `STOP); */ |
| 1397 | `endif |
| 1398 | |
| 1399 | `ifdef NO_err_BL_not_4_during_OCD_calibration_CHECK |
| 1400 | `else |
| 1401 | if(err_BL_not_4_during_OCD_calibration) |
| 1402 | `PR_ERROR("ddr2_monitor", `ERROR, "err_BL_not_4_during_OCD_calibration\n"); |
| 1403 | /* ova ova_asserted ddr2_ova53 |
| 1404 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_BL_not_4_during_OCD_calibration\n", `SEVERITY, `CATEGORY) |
| 1405 | (!(areset), ck, !(err_BL_not_4_during_OCD_calibration), `START, `STOP); */ |
| 1406 | `endif |
| 1407 | |
| 1408 | `ifdef NO_err_exceeded_max_attempts_during_OCD_adjust_CHECK |
| 1409 | `else |
| 1410 | if(err_exceeded_max_attempts_during_OCD_adjust) |
| 1411 | `PR_ERROR("ddr2_monitor", `ERROR, "err_exceeded_max_attempts_during_OCD_adjust\n"); |
| 1412 | /* ova ova_asserted ddr2_ova54 |
| 1413 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_exceeded_max_attempts_during_OCD_adjust\n", `SEVERITY, `CATEGORY) |
| 1414 | (!(areset), ck, !(err_exceeded_max_attempts_during_OCD_adjust), `START, `STOP); */ |
| 1415 | `endif |
| 1416 | |
| 1417 | `ifdef NO_err_dq_or_dqs_not_driven_during_OCD_adjust_CHECK |
| 1418 | `else |
| 1419 | if(err_dq_or_dqs_not_driven_during_OCD_adjust) |
| 1420 | `PR_ERROR("ddr2_monitor", `ERROR, "err_dq_or_dqs_not_driven_during_OCD_adjust\n"); |
| 1421 | /* ova ova_asserted ddr2_ova55 |
| 1422 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_dq_or_dqs_not_driven_during_OCD_adjust\n", `SEVERITY, `CATEGORY) |
| 1423 | (!(areset), ck, !(err_dq_or_dqs_not_driven_during_OCD_adjust), `START, `STOP); */ |
| 1424 | `endif |
| 1425 | |
| 1426 | `ifdef NO_err_extra_dqs_during_OCD_adjust_CHECK |
| 1427 | `else |
| 1428 | if(err_extra_dqs_during_OCD_adjust) |
| 1429 | `PR_ERROR("ddr2_monitor", `ERROR, "err_extra_dqs_during_OCD_adjust\n"); |
| 1430 | /* ova ova_asserted ddr2_ova56 |
| 1431 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_extra_dqs_during_OCD_adjust\n", `SEVERITY, `CATEGORY) |
| 1432 | (!(areset), ck, !(err_extra_dqs_during_OCD_adjust), `START, `STOP); */ |
| 1433 | `endif |
| 1434 | |
| 1435 | `ifdef NO_err_sref_issued_when_bank_not_idle_CHECK |
| 1436 | `else |
| 1437 | if(err_sref_issued_when_bank_not_idle) |
| 1438 | `PR_ERROR("ddr2_monitor", `ERROR, "err_sref_issued_when_bank_not_idle\n"); |
| 1439 | /* ova ova_asserted ddr2_ova57 |
| 1440 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_sref_issued_when_bank_not_idle\n", `SEVERITY, `CATEGORY) |
| 1441 | (!(areset), ck, !(err_sref_issued_when_bank_not_idle), `START, `STOP); */ |
| 1442 | `endif |
| 1443 | |
| 1444 | `ifdef NO_err_dqs_and_dqsbar_not_in_sync_CHECK |
| 1445 | `else |
| 1446 | if(err_dqs_and_dqsbar_not_in_sync) |
| 1447 | `PR_ERROR("ddr2_monitor", `ERROR, "err_dqs_and_dqsbar_not_in_sync\n"); |
| 1448 | /* ova ova_asserted ddr2_ova58 |
| 1449 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_dqs_and_dqsbar_not_in_sync\n", `SEVERITY, `CATEGORY) |
| 1450 | (!(areset), ck, !(err_dqs_and_dqsbar_not_in_sync), `START, `STOP); */ |
| 1451 | `endif |
| 1452 | |
| 1453 | `ifdef NO_err_unknown_value_on_odt_pin_CHECK |
| 1454 | `else |
| 1455 | if(err_unknown_value_on_odt_pin) |
| 1456 | `PR_ERROR("ddr2_monitor", `ERROR, "err_unknown_value_on_odt_pin\n"); |
| 1457 | /* ova ova_asserted ddr2_ova59 |
| 1458 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_unknown_value_on_odt_pin\n", `SEVERITY, `CATEGORY) |
| 1459 | (!(areset), ck, !(err_unknown_value_on_odt_pin), `START, `STOP); */ |
| 1460 | `endif |
| 1461 | |
| 1462 | `ifdef NO_err_ref_issued_when_bank_not_idle_CHECK |
| 1463 | `else |
| 1464 | if(err_ref_issued_when_bank_not_idle) |
| 1465 | `PR_ERROR("ddr2_monitor", `ERROR, "err_ref_issued_when_bank_not_idle\n"); |
| 1466 | /* ova ova_asserted ddr2_ova60 |
| 1467 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: err_ref_issued_when_bank_not_idle\n", `SEVERITY, `CATEGORY) |
| 1468 | (!(areset), ck, !(err_ref_issued_when_bank_not_idle), `START, `STOP); */ |
| 1469 | `endif |
| 1470 | |
| 1471 | `ifdef NO_Ill_OCD_activity_CHECK |
| 1472 | `else |
| 1473 | if(Ill_OCD_activity) |
| 1474 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_OCD_activity\n"); |
| 1475 | /* ova ova_asserted ddr2_ova61 |
| 1476 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_mon: Ill_OCD_activity\n", `SEVERITY, `CATEGORY) |
| 1477 | (!(areset), ck, !(Ill_OCD_activity), `START, `STOP); */ |
| 1478 | `endif |
| 1479 | |
| 1480 | end // always |
| 1481 | `else |
| 1482 | initial |
| 1483 | `PR_DEBUG("ddr2_monitor", `DEBUG, "WARNING: NONE of the monitors enabled. Enable OVA/ZIN monitor\n"); |
| 1484 | `endif // ifdef DDR2_OVA_SIM_MON |
| 1485 | `endif // ifdef DDR2_0IN_SIM_MON/*}}}*/ |
| 1486 | |
| 1487 | |
| 1488 | // Need to add ECC checks for Niagara project. Note that such checks |
| 1489 | // are NOT specified in the JDEC specifiction. |
| 1490 | |
| 1491 | always @( posedge areset or posedge ck) begin |
| 1492 | if (areset) |
| 1493 | ddr2_err[15:10] <= 7'b0; |
| 1494 | else |
| 1495 | ; |
| 1496 | end |
| 1497 | |
| 1498 | // Initialization Checks /*{{{*/ |
| 1499 | reg [14:0] cs; |
| 1500 | reg starttimecheck; |
| 1501 | time startrealtime, midrealtime, endrealtime; |
| 1502 | real duration; |
| 1503 | reg is_odt_low; |
| 1504 | reg OCD_calibration_default; |
| 1505 | reg OCD_drive_1, OCD_drive_0, OCD_adjust ; |
| 1506 | reg [9:0] dqs_adjust_queue; |
| 1507 | reg [4:0] dqs_adjust_window; |
| 1508 | reg [4:0] time_ellapsed_in_adjust; |
| 1509 | |
| 1510 | parameter |
| 1511 | PRE_INIT = 15'b000_0000_0000_0001, |
| 1512 | INIT = 15'b000_0000_0000_0010, |
| 1513 | ST_1 = 15'b000_0000_0000_0100, |
| 1514 | ST_2 = 15'b000_0000_0000_1000, |
| 1515 | ST_3 = 15'b000_0000_0001_0000, |
| 1516 | ST_4 = 15'b000_0000_0010_0000, |
| 1517 | ST_5 = 15'b000_0000_0100_0000, |
| 1518 | ST_6 = 15'b000_0000_1000_0000, |
| 1519 | ST_7 = 15'b000_0001_0000_0000, |
| 1520 | ST_8 = 15'b000_0010_0000_0000, |
| 1521 | ST_9 = 15'b000_0100_0000_0000, |
| 1522 | ST_10 = 15'b000_1000_0000_0000, |
| 1523 | ST_11 = 15'b001_0000_0000_0000, |
| 1524 | ST_12 = 15'b010_0000_0000_0000, |
| 1525 | END = 15'b100_0000_0000_0000; |
| 1526 | |
| 1527 | initial |
| 1528 | begin |
| 1529 | init_err <= 22'b0; |
| 1530 | cs <= PRE_INIT; |
| 1531 | is_init_done <= 1'b0; |
| 1532 | is_DLL_reset <= 0; |
| 1533 | starttimecheck = 1'b0; |
| 1534 | OCD_calibration_default <= 1'b0; |
| 1535 | OCD_drive_0 <= 1'b0; |
| 1536 | OCD_drive_1 <= 1'b0; |
| 1537 | OCD_adjust <= 1'b0; |
| 1538 | dqs_adjust_window <= 5'b0; |
| 1539 | dqs_adjust_queue <= 10'b0; |
| 1540 | time_ellapsed_in_adjust <= 5'b0; |
| 1541 | end |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | task calc_nextstate; |
| 1546 | inout [14:0] cs; |
| 1547 | input [3:0] command; |
| 1548 | input [ROW_WIDTH - 1 : 0] addr; |
| 1549 | input [2:0] ba; |
| 1550 | input cke; |
| 1551 | input command_DESELECT; |
| 1552 | inout [21:0] init_err; |
| 1553 | output is_init_done; |
| 1554 | output is_DLL_reset; |
| 1555 | output is_odt_low; |
| 1556 | output OCD_calibration_default; |
| 1557 | output OCD_drive_0; |
| 1558 | output OCD_drive_1; |
| 1559 | output OCD_adjust; |
| 1560 | output [4:0] dqs_adjust_window; |
| 1561 | output [9:0] dqs_adjust_queue; |
| 1562 | output [4:0] time_ellapsed_in_adjust; |
| 1563 | begin |
| 1564 | if(areset) |
| 1565 | init_err = 22'b0; |
| 1566 | else |
| 1567 | begin |
| 1568 | case (cs) |
| 1569 | PRE_INIT: // check if cke is low b4 ck is stable |
| 1570 | begin |
| 1571 | if(~cke && ~starttimecheck) |
| 1572 | begin |
| 1573 | startrealtime = $time; |
| 1574 | starttimecheck = 1'b1; |
| 1575 | if(odt == 1'b0) |
| 1576 | is_odt_low = 1'b1; |
| 1577 | else |
| 1578 | is_odt_low = 1'b0; |
| 1579 | end |
| 1580 | if(cke && starttimecheck) |
| 1581 | begin |
| 1582 | midrealtime = $time; |
| 1583 | duration = midrealtime - startrealtime; |
| 1584 | if(duration < 200) |
| 1585 | init_err[10] = 1'b1; |
| 1586 | if(~is_odt_low || odt) |
| 1587 | init_err[12] = 1'b1; |
| 1588 | if(command != `NOP) |
| 1589 | init_err[0] = 1'b1; |
| 1590 | cs = INIT; |
| 1591 | end |
| 1592 | else if(cke && ~starttimecheck) |
| 1593 | begin |
| 1594 | init_err[0] = 1'b1; |
| 1595 | cs = INIT; |
| 1596 | end |
| 1597 | end |
| 1598 | |
| 1599 | INIT: // Only NOP's accepted |
| 1600 | begin |
| 1601 | if(command == `NOP && cke) |
| 1602 | cs = ST_1; |
| 1603 | else if(cke) |
| 1604 | begin |
| 1605 | init_err[0] = 1'b1; |
| 1606 | cs = INIT; |
| 1607 | end |
| 1608 | end |
| 1609 | |
| 1610 | ST_1: // wait minimum of 400ns then issue prechargeall |
| 1611 | // cmd. |
| 1612 | begin |
| 1613 | if(command == `PRECHARGE && addr[10]) |
| 1614 | begin |
| 1615 | cs = ST_2; |
| 1616 | if(starttimecheck) |
| 1617 | begin |
| 1618 | endrealtime = $time; |
| 1619 | duration = endrealtime - midrealtime; |
| 1620 | if(duration < 400) |
| 1621 | init_err[11] = 1'b1; |
| 1622 | end |
| 1623 | end |
| 1624 | else if(command == `NOP || command_DESELECT) |
| 1625 | cs = ST_1; |
| 1626 | else |
| 1627 | begin |
| 1628 | init_err[1] = 1'b1; |
| 1629 | cs = ST_1; |
| 1630 | end |
| 1631 | end |
| 1632 | |
| 1633 | ST_2: // expect EMRS(2) |
| 1634 | begin |
| 1635 | if(command == `MRS && ba[0] == 1'b0 && ba[1] == 1'b1 && ba[2] == 1'b0) |
| 1636 | cs = ST_3; |
| 1637 | else if(command == `NOP || command_DESELECT) |
| 1638 | cs = ST_2; |
| 1639 | else |
| 1640 | begin |
| 1641 | init_err[2] = 1'b1; |
| 1642 | cs = ST_2; |
| 1643 | end |
| 1644 | end |
| 1645 | |
| 1646 | ST_3: // expect EMRS(3) |
| 1647 | begin |
| 1648 | if(command == `MRS && ba[0] == 1'b1 && ba[1] == 1'b1 && ba[2] == 1'b0) |
| 1649 | cs = ST_4; |
| 1650 | else if (command == `NOP || command_DESELECT) |
| 1651 | cs = ST_3; |
| 1652 | else |
| 1653 | begin |
| 1654 | init_err[3] = 1'b1; |
| 1655 | cs = ST_3; |
| 1656 | end |
| 1657 | end |
| 1658 | |
| 1659 | ST_4: // expect EMRS to enable DLL |
| 1660 | begin |
| 1661 | if(command == `MRS && addr[0] == 1'b0 && ba[0] == 1'b1 && ba[1] == 1'b0 && ba[2] == 1'b0) // addr[13-15] == 1'b0 |
| 1662 | cs = ST_5; |
| 1663 | else if (command == `NOP || command_DESELECT) |
| 1664 | cs = ST_4; |
| 1665 | else |
| 1666 | begin |
| 1667 | init_err[4] = 1'b1; |
| 1668 | cs = ST_4; |
| 1669 | end |
| 1670 | end |
| 1671 | |
| 1672 | ST_5: // expect MRS for DLL reset |
| 1673 | begin |
| 1674 | if(command == `MRS && addr[8] && ba[0] == 1'b0 && ba[1] == 1'b0 && ba[2] == 1'b0) // addr[13-15] == 1'b0 |
| 1675 | begin |
| 1676 | cs = ST_6; |
| 1677 | is_DLL_reset <= 1; |
| 1678 | end |
| 1679 | else if (command == `NOP || command_DESELECT) |
| 1680 | cs = ST_5; |
| 1681 | else |
| 1682 | begin |
| 1683 | init_err[5] = 1'b1; |
| 1684 | cs = ST_5; |
| 1685 | end |
| 1686 | end |
| 1687 | |
| 1688 | ST_6: // expect precharge all cmd |
| 1689 | begin |
| 1690 | if(command == `PRECHARGE && addr[10]) |
| 1691 | cs = ST_7; |
| 1692 | else if (command == `NOP || command_DESELECT) |
| 1693 | cs = ST_6; |
| 1694 | else |
| 1695 | begin |
| 1696 | init_err[6] = 1'b1; |
| 1697 | cs = ST_6; |
| 1698 | end |
| 1699 | end |
| 1700 | |
| 1701 | ST_7: // 1st auto-refresh cmd |
| 1702 | begin |
| 1703 | if(command == `REF_SREF && cke) |
| 1704 | cs = ST_8; |
| 1705 | else if (command == `NOP || command_DESELECT) |
| 1706 | cs = ST_7; |
| 1707 | else |
| 1708 | begin |
| 1709 | init_err[7] = 1'b1; |
| 1710 | cs = ST_7; |
| 1711 | end |
| 1712 | end |
| 1713 | |
| 1714 | ST_8: // 2nd auto-refresh cmd |
| 1715 | begin |
| 1716 | if(command == `REF_SREF && cke) |
| 1717 | cs = ST_9; |
| 1718 | else if ((command == `NOP) || (command_DESELECT)) |
| 1719 | cs = ST_8; |
| 1720 | else |
| 1721 | begin |
| 1722 | init_err[8] = 1'b1; |
| 1723 | cs = ST_8; |
| 1724 | end |
| 1725 | end |
| 1726 | |
| 1727 | ST_9: // MRS cmd without DLL reset |
| 1728 | begin |
| 1729 | if(command == `MRS && addr[8] == 1'b0) |
| 1730 | begin |
| 1731 | cs = ST_10; |
| 1732 | is_DLL_reset <= 0; |
| 1733 | end |
| 1734 | else if (command == `NOP || command_DESELECT || (command == `REF_SREF && cke)) |
| 1735 | cs = ST_9; |
| 1736 | else |
| 1737 | begin |
| 1738 | init_err[9] = 1'b1; |
| 1739 | cs = ST_9; |
| 1740 | end |
| 1741 | end |
| 1742 | |
| 1743 | // OCD calibration |
| 1744 | ST_10: |
| 1745 | begin |
| 1746 | if(command == `MRS && ba[0] == 1'b1 && ba[1] == 1'b0 && ba[2] == 1'b0) // addr[13-15] == 1'b0 |
| 1747 | begin |
| 1748 | if(time_after_DLL_reset >= 200) |
| 1749 | begin |
| 1750 | cs = ST_11; |
| 1751 | if({addr[9],addr[8],addr[7]} == 3'b111) |
| 1752 | OCD_calibration_default <= 1'b1; |
| 1753 | if(({addr[9],addr[8],addr[7]} == 3'b001) && (&dq[DATA_WIDTH - 1 : 0] == 1'b1) && (&dqs[DATA_STROBE_NUM - 1 : 0] == 1'b1)) |
| 1754 | OCD_drive_1 <= 1; |
| 1755 | end |
| 1756 | else |
| 1757 | init_err[13] <= 1'b1; |
| 1758 | end |
| 1759 | else if (command == `NOP || command_DESELECT) |
| 1760 | cs = ST_10; |
| 1761 | else |
| 1762 | begin |
| 1763 | init_err[14] <= 1'b1; |
| 1764 | cs = ST_10; |
| 1765 | end |
| 1766 | end |
| 1767 | |
| 1768 | ST_11: |
| 1769 | begin |
| 1770 | if(command == `MRS && ba[0] == 1'b1 && ba[1] == 1'b0 && ba[2] == 1'b0) // addr[13-15] == 1'b0 |
| 1771 | begin |
| 1772 | if(OCD_calibration_default && ({addr[9],addr[8],addr[7]} == 3'b0)) |
| 1773 | begin |
| 1774 | OCD_calibration_default <= 1'b0; |
| 1775 | cs = END; |
| 1776 | end |
| 1777 | else if (OCD_calibration_default) |
| 1778 | init_err[15] <= 1'b1; |
| 1779 | |
| 1780 | if(OCD_drive_1) |
| 1781 | begin |
| 1782 | if({addr[9],addr[8],addr[7]} == 3'b0) |
| 1783 | OCD_drive_1 <= 1'b0; |
| 1784 | |
| 1785 | if(({addr[9],addr[8],addr[7]} != 3'b0) || (&dq[DATA_WIDTH - 1 : 0] != 1'b1) || (&dqs[DATA_STROBE_NUM - 1 : 0] != 1'b1) || (&dqs_bar[DATA_STROBE_NUM - 1 : 0] != 1'b0)) |
| 1786 | init_err[17] <= 1'b1; |
| 1787 | end |
| 1788 | |
| 1789 | if(!OCD_drive_1 && ({addr[9],addr[8],addr[7]} == 3'b100)) |
| 1790 | begin |
| 1791 | OCD_adjust = 1'b1; |
| 1792 | dqs_adjust_queue[0] = 1'b1; |
| 1793 | time_ellapsed_in_adjust = 5'b0; |
| 1794 | end |
| 1795 | |
| 1796 | if(OCD_adjust && ({addr[9],addr[8],addr[7]} == 3'b0)) |
| 1797 | begin |
| 1798 | OCD_adjust = 1'b0; |
| 1799 | cs = ST_10; |
| 1800 | end |
| 1801 | |
| 1802 | if(!OCD_drive_1 && !OCD_adjust && ({addr[9],addr[8],addr[7]} == 3'b010)) |
| 1803 | begin |
| 1804 | OCD_drive_0 <= 1'b1; |
| 1805 | cs = ST_12; |
| 1806 | end |
| 1807 | |
| 1808 | if(!OCD_drive_1 && !OCD_adjust && ({addr[9],addr[8],addr[7]} != 3'b010) && ({addr[9],addr[8],addr[7]} != 3'b100) && ({addr[9],addr[8],addr[7]} != 3'b000)) |
| 1809 | init_err[16] <= 1'b1; |
| 1810 | |
| 1811 | end |
| 1812 | else if (command == `NOP || command_DESELECT) |
| 1813 | begin |
| 1814 | if(OCD_adjust) |
| 1815 | begin |
| 1816 | if(MRS_BL != 4'd4) |
| 1817 | init_err[18] <= 1'b1; |
| 1818 | |
| 1819 | time_ellapsed_in_adjust = time_ellapsed_in_adjust + 1'b1; |
| 1820 | if(time_ellapsed_in_adjust > 5'd16) |
| 1821 | init_err[19] <= 1'b1; |
| 1822 | |
| 1823 | dqs_adjust_queue = dqs_adjust_queue << 1; |
| 1824 | if(dqs_adjust_queue[WL]) |
| 1825 | dqs_adjust_window = dqs_adjust_window + (MRS_BL >> 1); |
| 1826 | |
| 1827 | if(dqs_adjust_window > 0) |
| 1828 | begin |
| 1829 | if((^dq[DATA_WIDTH - 1 : 0] == 1'bx) || (^dqs[DATA_STROBE_NUM - 1 : 0] == 1'bx)) |
| 1830 | init_err[20] <= 1'b1; |
| 1831 | dqs_adjust_window = dqs_adjust_window - 1; |
| 1832 | end |
| 1833 | else |
| 1834 | begin |
| 1835 | if((^dqs[DATA_STROBE_NUM - 1 : 0] == 1'b1) || (^dqs[DATA_STROBE_NUM - 1 : 0] == 1'b0)) |
| 1836 | init_err[21] <= 1'b1; |
| 1837 | end |
| 1838 | |
| 1839 | cs = ST_11; |
| 1840 | end |
| 1841 | end |
| 1842 | else |
| 1843 | begin |
| 1844 | init_err[16] <= 1'b1; |
| 1845 | cs = ST_11; |
| 1846 | end |
| 1847 | end |
| 1848 | |
| 1849 | ST_12: |
| 1850 | begin |
| 1851 | if(command == `MRS && ba[0] == 1'b1 && ba[1] == 1'b0 && ba[2] == 1'b0) // addr[13-15] == 1'b0 |
| 1852 | begin |
| 1853 | if(OCD_drive_0) |
| 1854 | begin |
| 1855 | if({addr[9],addr[8],addr[7]} == 3'b0) |
| 1856 | begin |
| 1857 | OCD_drive_0 <= 1'b0; |
| 1858 | cs = END; |
| 1859 | end |
| 1860 | |
| 1861 | if(({addr[9],addr[8],addr[7]} != 3'b0) || (&dq[DATA_WIDTH - 1 : 0] != 1'b0) || (&dqs[DATA_STROBE_NUM - 1 : 0] != 1'b0) || (&dqs_bar[DATA_STROBE_NUM - 1 : 0] != 1'b1)) |
| 1862 | init_err[17] <= 1'b1; |
| 1863 | end |
| 1864 | |
| 1865 | // I'm not checking for drive_0 adjust coz of |
| 1866 | // the ambigious nature of the FSM it is |
| 1867 | // difficult to tell the END of inti_sequence |
| 1868 | /* |
| 1869 | if(!OCD_drive_0 && ({addr[9],addr[8],addr[7]} == 3'b100)) |
| 1870 | OCD_adjust <= 1'b1; |
| 1871 | |
| 1872 | if(OCD_adjust) |
| 1873 | begin |
| 1874 | // adjust check |
| 1875 | end |
| 1876 | */ |
| 1877 | |
| 1878 | end |
| 1879 | else if (command == `NOP || command_DESELECT) |
| 1880 | cs = ST_12; |
| 1881 | else |
| 1882 | begin |
| 1883 | init_err[16] <= 1'b1; |
| 1884 | cs = ST_12; |
| 1885 | end |
| 1886 | end |
| 1887 | |
| 1888 | END: |
| 1889 | begin |
| 1890 | is_init_done <= 1'b1; |
| 1891 | end |
| 1892 | endcase |
| 1893 | end |
| 1894 | end |
| 1895 | endtask |
| 1896 | |
| 1897 | /* |
| 1898 | always @ (areset or posedge ck) |
| 1899 | calc_nextstate(cs, command, addr, ba, cke, command_DESELECT, init_err, is_init_done, is_DLL_reset, is_odt_low, OCD_calibration_default, OCD_drive_0, OCD_drive_1, OCD_adjust, dqs_adjust_window, dqs_adjust_queue, time_ellapsed_in_adjust); |
| 1900 | */ |
| 1901 | |
| 1902 | always @ (posedge ck) |
| 1903 | is_init_done <= init_done; |
| 1904 | |
| 1905 | /*}}}*/ |
| 1906 | |
| 1907 | // Decode MRS /*{{{*/ |
| 1908 | // For DDR-II there is no default value for MRS, the user have to |
| 1909 | // program it before any access is performed. |
| 1910 | always @( posedge areset or posedge ck) |
| 1911 | begin |
| 1912 | if (areset) |
| 1913 | begin |
| 1914 | MRS_BL <= BURST_LENGTH_reg; |
| 1915 | MRS_BT <= BURST_TYPE_SEQ_reg; |
| 1916 | MRS_CAS <= tCAS_reg; |
| 1917 | MRS_TM <= 0; |
| 1918 | MRS_DLL_RESET <= 0; |
| 1919 | MRS_WR <= tWR_reg; |
| 1920 | EMRS_AL <= ADDITIVE_LATENCY_reg; |
| 1921 | end |
| 1922 | else |
| 1923 | begin |
| 1924 | if(command == `MRS) |
| 1925 | begin |
| 1926 | case (ba[1:0]) |
| 1927 | 2'b00 : // MRS |
| 1928 | begin |
| 1929 | MRS_BL <= ((addr [2:0] == 3'd2) ? 4'd4 : (addr [2:0] == 3'd3) ? 4'd8 : BURST_LENGTH_reg); |
| 1930 | MRS_BT <= addr [3]; |
| 1931 | MRS_CAS <= addr [6:4]; |
| 1932 | MRS_TM <= addr [7]; |
| 1933 | MRS_DLL_RESET <= addr [8]; |
| 1934 | MRS_WR <= addr [11:9]; |
| 1935 | end |
| 1936 | 2'b01: // EMRS |
| 1937 | begin |
| 1938 | EMRS_DLL_ENABLE <= ~addr [0]; |
| 1939 | EMRS_AL <= addr [5:3]; |
| 1940 | EMRS_RTT <= {addr[2], addr[6]}; |
| 1941 | EMRS_OCD <= addr[9:7]; |
| 1942 | EMRS_DQS_BAR_DISABLE <= addr[10]; |
| 1943 | end |
| 1944 | |
| 1945 | default: |
| 1946 | ; |
| 1947 | |
| 1948 | endcase // case(ba[1:0]) |
| 1949 | end |
| 1950 | end // else: !if(areset) |
| 1951 | end // always @ ( posedge areset or posedge ck) /*}}}*/ |
| 1952 | |
| 1953 | // Sequential Activation Check /*{{{*/ |
| 1954 | // Check if ACT to multiple banks obey sequential bank activation |
| 1955 | // restriction (4 in tFAW_reg ) |
| 1956 | reg [3:0] act_act_window[3:0]; |
| 1957 | reg vld_windows[3:0]; |
| 1958 | integer i; |
| 1959 | |
| 1960 | initial |
| 1961 | begin |
| 1962 | for(i = 0; i < 4; i = i + 1) |
| 1963 | begin |
| 1964 | vld_windows[i] = 1'b0; |
| 1965 | act_act_window[i] = 4'b0; |
| 1966 | end |
| 1967 | end |
| 1968 | |
| 1969 | always @(posedge ck or posedge areset) |
| 1970 | begin |
| 1971 | if(areset) |
| 1972 | begin |
| 1973 | for(i = 0; i < 4; i = i + 1) |
| 1974 | begin |
| 1975 | vld_windows[i] = 1'b0; |
| 1976 | act_act_window[i] = 4'b0; |
| 1977 | end |
| 1978 | seq_act_violation <= 1'b0; |
| 1979 | end |
| 1980 | else |
| 1981 | begin |
| 1982 | for(i = 0; i < 4; i = i + 1) |
| 1983 | begin |
| 1984 | if(vld_windows[i] == 1'b1) |
| 1985 | begin |
| 1986 | act_act_window[i] = act_act_window[i] + 4'b0001; |
| 1987 | if(act_act_window[i] > (tFAW_reg)) |
| 1988 | begin |
| 1989 | act_act_window[i] = 4'b0; |
| 1990 | vld_windows[i] = 1'b0; |
| 1991 | end |
| 1992 | end |
| 1993 | end |
| 1994 | |
| 1995 | |
| 1996 | if(command == `ACTIVE) |
| 1997 | begin |
| 1998 | if(vld_windows[0] == 1'b1 && vld_windows[1] == 1'b1 && vld_windows[2] == 1'b1 && vld_windows[3] == 1'b1) |
| 1999 | seq_act_violation <= 1'b1; |
| 2000 | |
| 2001 | if(vld_windows[0] == 1'b0) |
| 2002 | begin |
| 2003 | vld_windows[0] = 1'b1; |
| 2004 | act_act_window[0] = 4'b0001; |
| 2005 | end |
| 2006 | else if(vld_windows[1] == 1'b0) |
| 2007 | begin |
| 2008 | vld_windows[1] = 1'b1; |
| 2009 | act_act_window[1] = 4'b0001; |
| 2010 | end |
| 2011 | else if(vld_windows[2] == 1'b0) |
| 2012 | begin |
| 2013 | vld_windows[2] = 1'b1; |
| 2014 | act_act_window[2] = 4'b0001; |
| 2015 | end |
| 2016 | else if(vld_windows[3] == 1'b0) |
| 2017 | begin |
| 2018 | vld_windows[3] = 1'b1; |
| 2019 | act_act_window[3] = 4'b0001; |
| 2020 | end |
| 2021 | end |
| 2022 | end |
| 2023 | end /*}}}*/ |
| 2024 | |
| 2025 | |
| 2026 | always @(posedge ck or posedge areset) begin |
| 2027 | if(areset) |
| 2028 | is_there_ACT <= 1'b0; |
| 2029 | else if (command == `ACTIVE) |
| 2030 | is_there_ACT <= 1'b1; |
| 2031 | end |
| 2032 | |
| 2033 | always @(posedge ck or posedge areset) begin |
| 2034 | if(areset) |
| 2035 | is_there_READ <= 1'b0; |
| 2036 | else if (command == `READ) |
| 2037 | is_there_READ <= 1'b1; |
| 2038 | end |
| 2039 | |
| 2040 | always @(posedge ck or posedge areset) begin |
| 2041 | if(areset) |
| 2042 | is_there_WRITE <= 1'b0; |
| 2043 | else if (command == `WRITE) |
| 2044 | is_there_WRITE <= 1'b1; |
| 2045 | end |
| 2046 | |
| 2047 | |
| 2048 | always @(posedge ck or posedge areset) begin |
| 2049 | if(areset) |
| 2050 | is_there_MRS <= 1'b0; |
| 2051 | else if (command == `MRS) |
| 2052 | is_there_MRS <= 1'b1; |
| 2053 | end |
| 2054 | |
| 2055 | |
| 2056 | always @(posedge ck or posedge areset) begin |
| 2057 | if(areset) |
| 2058 | is_there_REF<= 1'b0; |
| 2059 | else if (ref) |
| 2060 | is_there_REF <= 1'b1; |
| 2061 | end |
| 2062 | |
| 2063 | always @(posedge ck or posedge areset) begin |
| 2064 | if(areset) |
| 2065 | is_there_SREF <= 1'b0; |
| 2066 | else if (sref) |
| 2067 | is_there_SREF <= 1'b1; |
| 2068 | end |
| 2069 | |
| 2070 | always @(posedge ck or posedge areset) begin |
| 2071 | if(areset) |
| 2072 | is_there_PWD_EXIT <= 1'b0; |
| 2073 | else if (controller_state == `CS_POWER_DOWN_EXIT) |
| 2074 | is_there_PWD_EXIT<= 1'b1; |
| 2075 | end |
| 2076 | |
| 2077 | |
| 2078 | // NOTE!!!: |
| 2079 | // After areset, all banks are in idle. |
| 2080 | // 1. All banks should be allowed to accept an which means |
| 2081 | // min_time(ACT -> ACT) is met. (`tRRD_reg) |
| 2082 | // 2. Assume min_time(MRS -> Any) is met (`tMRD_reg) |
| 2083 | // 3. Assume min_time(REF -> Any) is met (`tRFC_reg) |
| 2084 | |
| 2085 | always @(posedge ck or posedge areset) begin |
| 2086 | if (areset) |
| 2087 | time_after_ACT <= tRRD_reg; |
| 2088 | else if ( command == `ACTIVE) |
| 2089 | time_after_ACT <= 6'd0; |
| 2090 | else if(~stop_time_after_ACT && is_there_ACT) |
| 2091 | time_after_ACT <= time_after_ACT + 6'd1; |
| 2092 | end |
| 2093 | |
| 2094 | always @(posedge ck or posedge areset) begin |
| 2095 | if (areset ) |
| 2096 | time_after_READ <= 6'd1; |
| 2097 | else if (command == `READ) |
| 2098 | time_after_READ <= 6'd0; |
| 2099 | else if (~stop_time_after_READ && is_there_READ) |
| 2100 | time_after_READ <= time_after_READ + 6'd1; |
| 2101 | end |
| 2102 | |
| 2103 | always @(posedge ck or posedge areset) begin |
| 2104 | if (areset ) |
| 2105 | time_after_WRITE <= 6'd1; |
| 2106 | else if ( command == `WRITE) |
| 2107 | time_after_WRITE <= 6'd0; |
| 2108 | else if (~stop_time_after_WRITE && is_there_WRITE) |
| 2109 | time_after_WRITE <= time_after_WRITE + 6'd1; |
| 2110 | end |
| 2111 | |
| 2112 | always @(posedge ck or posedge areset) begin |
| 2113 | if (areset) |
| 2114 | time_after_MRS <= tMRD_reg; |
| 2115 | else if (command == `MRS) |
| 2116 | time_after_MRS <= 6'd0; |
| 2117 | else if (~stop_time_after_MRS && is_there_MRS) |
| 2118 | time_after_MRS <= time_after_MRS + 6'd1; |
| 2119 | end |
| 2120 | |
| 2121 | always @(posedge ck or posedge areset) begin |
| 2122 | if (areset) |
| 2123 | time_after_REF <= tRFC_reg; |
| 2124 | else if (ref) |
| 2125 | time_after_REF <= 6'd0; |
| 2126 | else if (~stop_time_after_REF && is_there_REF) |
| 2127 | time_after_REF <= time_after_REF + 6'd1; |
| 2128 | end |
| 2129 | |
| 2130 | //wire [7:0] min_self_ref_cycle_time = ( ( tXSNR_reg >= tXSRD_reg ) ? tXSRD_reg : tXSNR_reg); |
| 2131 | |
| 2132 | always @(posedge ck or posedge areset) |
| 2133 | begin |
| 2134 | if (areset) |
| 2135 | // time_after_SREF <= min_self_ref_cycle_time; |
| 2136 | time_after_SREF <= ( ( tXSNR_reg >= tXSRD_reg ) ? tXSRD_reg : tXSNR_reg); |
| 2137 | else if (sref) |
| 2138 | time_after_SREF <= 8'd0; |
| 2139 | else if (~stop_time_after_SREF && is_there_SREF) |
| 2140 | time_after_SREF <= time_after_SREF + 8'd1; |
| 2141 | end |
| 2142 | |
| 2143 | always @(posedge ck or posedge areset or is_DLL_reset) |
| 2144 | begin |
| 2145 | if(areset) |
| 2146 | begin |
| 2147 | time_after_DLL_reset <= 11'd0; |
| 2148 | start_time_after_DLL_reset <= 1'b0; |
| 2149 | end |
| 2150 | else if (!start_time_after_DLL_reset && is_DLL_reset) |
| 2151 | begin |
| 2152 | start_time_after_DLL_reset <= 1'b1; |
| 2153 | time_after_DLL_reset <= 11'd1; |
| 2154 | end |
| 2155 | else if (start_time_after_DLL_reset) |
| 2156 | time_after_DLL_reset <= time_after_DLL_reset + 11'd1; |
| 2157 | end |
| 2158 | |
| 2159 | //wire [5:0] min_powerdown_exit_cycle_time = ( (tXP_reg >= tXARD_reg) ? tXARD_reg : tXP_reg); |
| 2160 | |
| 2161 | always @(posedge ck or posedge areset) |
| 2162 | begin |
| 2163 | if (areset) |
| 2164 | // time_after_PWD_EXIT <= min_powerdown_exit_cycle_time; |
| 2165 | time_after_PWD_EXIT <= ( (tXP_reg >= tXARD_reg) ? tXARD_reg : tXP_reg); |
| 2166 | else if (controller_state == `CS_POWER_DOWN_EXIT) |
| 2167 | time_after_PWD_EXIT <= 1'd0; |
| 2168 | else if (~stop_time_after_PWD_EXIT && is_there_PWD_EXIT) |
| 2169 | time_after_PWD_EXIT <= time_after_PWD_EXIT + 6'd1; |
| 2170 | end |
| 2171 | |
| 2172 | reg [3:0] bank1_command; |
| 2173 | reg [3:0] bank2_command; |
| 2174 | reg [3:0] bank3_command; |
| 2175 | reg [3:0] bank4_command; |
| 2176 | reg [3:0] bank5_command; |
| 2177 | reg [3:0] bank6_command; |
| 2178 | reg [3:0] bank7_command; |
| 2179 | reg [3:0] bank8_command; |
| 2180 | |
| 2181 | // Issuing commands to banks /*{{{*/ |
| 2182 | always @(command or ba or addr or cke or cs_bar ) |
| 2183 | begin |
| 2184 | if ((command == `NOP) || ( command_DESELECT) || (command == `PRECHARGE && addr[10]) || (command == `MRS)) |
| 2185 | begin |
| 2186 | bank1_command = command; |
| 2187 | bank2_command = command; |
| 2188 | bank3_command = command; |
| 2189 | bank4_command = command; |
| 2190 | bank5_command = command; |
| 2191 | bank6_command = command; |
| 2192 | bank7_command = command; |
| 2193 | bank8_command = command; |
| 2194 | end |
| 2195 | else |
| 2196 | begin |
| 2197 | case (ba) |
| 2198 | 3'b000: |
| 2199 | begin |
| 2200 | bank1_command = command; |
| 2201 | bank2_command = `NOP; |
| 2202 | bank3_command = `NOP; |
| 2203 | bank4_command = `NOP; |
| 2204 | bank5_command = `NOP; |
| 2205 | bank6_command = `NOP; |
| 2206 | bank7_command = `NOP; |
| 2207 | bank8_command = `NOP; |
| 2208 | end |
| 2209 | |
| 2210 | 3'b001: |
| 2211 | begin |
| 2212 | bank1_command = `NOP; |
| 2213 | bank2_command = command; |
| 2214 | bank3_command = `NOP; |
| 2215 | bank4_command = `NOP; |
| 2216 | bank5_command = `NOP; |
| 2217 | bank6_command = `NOP; |
| 2218 | bank7_command = `NOP; |
| 2219 | bank8_command = `NOP; |
| 2220 | end |
| 2221 | |
| 2222 | 3'b010: |
| 2223 | begin |
| 2224 | bank1_command = `NOP; |
| 2225 | bank2_command = `NOP; |
| 2226 | bank3_command = command; |
| 2227 | bank4_command = `NOP; |
| 2228 | bank5_command = `NOP; |
| 2229 | bank6_command = `NOP; |
| 2230 | bank7_command = `NOP; |
| 2231 | bank8_command = `NOP; |
| 2232 | end |
| 2233 | |
| 2234 | 3'b011: |
| 2235 | begin |
| 2236 | bank1_command = `NOP; |
| 2237 | bank2_command = `NOP; |
| 2238 | bank3_command = `NOP; |
| 2239 | bank4_command = command; |
| 2240 | bank5_command = `NOP; |
| 2241 | bank6_command = `NOP; |
| 2242 | bank7_command = `NOP; |
| 2243 | bank8_command = `NOP; |
| 2244 | end |
| 2245 | |
| 2246 | 3'b100: |
| 2247 | begin |
| 2248 | bank1_command = `NOP; |
| 2249 | bank2_command = `NOP; |
| 2250 | bank3_command = `NOP; |
| 2251 | bank4_command = `NOP; |
| 2252 | bank5_command = command; |
| 2253 | bank6_command = `NOP; |
| 2254 | bank7_command = `NOP; |
| 2255 | bank8_command = `NOP; |
| 2256 | end |
| 2257 | |
| 2258 | 3'b101: |
| 2259 | begin |
| 2260 | bank1_command = `NOP; |
| 2261 | bank2_command = `NOP; |
| 2262 | bank3_command = `NOP; |
| 2263 | bank4_command = `NOP; |
| 2264 | bank5_command = `NOP; |
| 2265 | bank6_command = command; |
| 2266 | bank7_command = `NOP; |
| 2267 | bank8_command = `NOP; |
| 2268 | end |
| 2269 | |
| 2270 | 3'b110: |
| 2271 | begin |
| 2272 | bank1_command = `NOP; |
| 2273 | bank2_command = `NOP; |
| 2274 | bank3_command = `NOP; |
| 2275 | bank4_command = `NOP; |
| 2276 | bank5_command = `NOP; |
| 2277 | bank6_command = `NOP; |
| 2278 | bank7_command = command; |
| 2279 | bank8_command = `NOP; |
| 2280 | end |
| 2281 | |
| 2282 | 3'b111: |
| 2283 | begin |
| 2284 | bank1_command = `NOP; |
| 2285 | bank2_command = `NOP; |
| 2286 | bank3_command = `NOP; |
| 2287 | bank4_command = `NOP; |
| 2288 | bank5_command = `NOP; |
| 2289 | bank6_command = `NOP; |
| 2290 | bank7_command = `NOP; |
| 2291 | bank8_command = command; |
| 2292 | end |
| 2293 | |
| 2294 | default: |
| 2295 | begin |
| 2296 | bank1_command = `NOP; |
| 2297 | bank2_command = `NOP; |
| 2298 | bank3_command = `NOP; |
| 2299 | bank4_command = `NOP; |
| 2300 | bank5_command = `NOP; |
| 2301 | bank6_command = `NOP; |
| 2302 | bank7_command = `NOP; |
| 2303 | bank8_command = `NOP; |
| 2304 | end |
| 2305 | endcase // case(ba |
| 2306 | end // else: !if((command == `NOP) || (command == `PRECHARGE && addr[10])) |
| 2307 | end // always (command or ba or addr[10] or cke or cs_bar) /*}}}*/ |
| 2308 | |
| 2309 | // Controller FSM /*{{{*/ |
| 2310 | always @(posedge ck or posedge areset) |
| 2311 | begin |
| 2312 | if (areset && ~init_done) |
| 2313 | begin |
| 2314 | controller_state <= `CS_IDLE; |
| 2315 | ddr2_err[9:0] <= 10'b0; |
| 2316 | end |
| 2317 | else if (all_bank_idle && controller_state != `CS_ILLEGAL) |
| 2318 | begin |
| 2319 | case (command) |
| 2320 | `MRS: |
| 2321 | begin |
| 2322 | if(cke) |
| 2323 | controller_state <= `CS_MODE_REG_SET; |
| 2324 | else |
| 2325 | begin |
| 2326 | controller_state <= `CS_ILLEGAL; // err[1] |
| 2327 | ddr2_err[1] <= 1'b1; |
| 2328 | end |
| 2329 | end |
| 2330 | |
| 2331 | `REF_SREF: |
| 2332 | begin |
| 2333 | if (cke) |
| 2334 | controller_state <= `CS_REFRESH; |
| 2335 | else |
| 2336 | controller_state <= `CS_SELF_REFRESH; |
| 2337 | end |
| 2338 | |
| 2339 | //`DESELECT: begin |
| 2340 | // if(~cke) begin |
| 2341 | // controller_state <= `CS_POWER_DOWN; |
| 2342 | // precharge_pwdn <= 1'b1; |
| 2343 | // end else |
| 2344 | // controller_state <= `CS_IDLE; |
| 2345 | //end |
| 2346 | |
| 2347 | `NOP: |
| 2348 | begin |
| 2349 | if(~cke) |
| 2350 | begin |
| 2351 | controller_state <= `CS_POWER_DOWN; |
| 2352 | precharge_pwdn <= 1'b1; // if all bank idle, it is a precharge pwr_down |
| 2353 | end |
| 2354 | else |
| 2355 | controller_state <= `CS_IDLE; |
| 2356 | end |
| 2357 | |
| 2358 | default: |
| 2359 | begin |
| 2360 | if(command_DESELECT) |
| 2361 | begin |
| 2362 | if(~cke) |
| 2363 | begin |
| 2364 | controller_state <= `CS_POWER_DOWN; |
| 2365 | precharge_pwdn <= 1'b1; |
| 2366 | end |
| 2367 | else |
| 2368 | controller_state <= `CS_IDLE; |
| 2369 | end |
| 2370 | else |
| 2371 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2372 | end |
| 2373 | endcase // end of case (command) |
| 2374 | |
| 2375 | end // if (all_bank_idle) |
| 2376 | else |
| 2377 | begin |
| 2378 | case (controller_state) |
| 2379 | // After MRS, only NOP can be issued before tMRD_reg is met |
| 2380 | `CS_MODE_REG_SET: |
| 2381 | begin |
| 2382 | if((command != `NOP && ~command_DESELECT) && ~tMRS_TO_ANY_met) |
| 2383 | begin |
| 2384 | controller_state <= `CS_ILLEGAL; // err[2] |
| 2385 | ddr2_err[2] <= 1'b1; |
| 2386 | end |
| 2387 | else |
| 2388 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2389 | end |
| 2390 | |
| 2391 | // After REF, only NOP can be issued before tRFC_reg is met |
| 2392 | `CS_REFRESH: |
| 2393 | begin |
| 2394 | if((command != `NOP && ~command_DESELECT) && ~tREF_TO_ANY_met) |
| 2395 | begin |
| 2396 | controller_state <= `CS_ILLEGAL; // err[3] |
| 2397 | ddr2_err[3] <= 1'b1; |
| 2398 | end |
| 2399 | else |
| 2400 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2401 | end |
| 2402 | |
| 2403 | // After SELF_REFRESH, there are 2 possible commands can be issued |
| 2404 | // and the corresponding time to be met; so, after one command is issued |
| 2405 | // and the corresponding time is met, we need to check if the other |
| 2406 | // type of timing requirement is met too to move the Controller State |
| 2407 | // to from CS_SELF_REFRESH to CS_BANKS_ACTIVE_OR_IDLE. |
| 2408 | `CS_SELF_REFRESH: |
| 2409 | begin |
| 2410 | if (command == `READ ) |
| 2411 | begin |
| 2412 | if(~tSREF_TO_RD_met) |
| 2413 | begin |
| 2414 | controller_state <= `CS_ILLEGAL; // err[4] |
| 2415 | ddr2_err[4] <= 1'b1; |
| 2416 | end |
| 2417 | else if (tSREF_TO_ANY_NON_RD_met) |
| 2418 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2419 | else |
| 2420 | controller_state <= `CS_SELF_REFRESH; |
| 2421 | end |
| 2422 | else |
| 2423 | begin |
| 2424 | if (command != `NOP && ~command_DESELECT) |
| 2425 | begin |
| 2426 | if(~tSREF_TO_ANY_NON_RD_met) |
| 2427 | begin |
| 2428 | controller_state <= `CS_ILLEGAL; //err[5] |
| 2429 | ddr2_err[5] <= 1'b1; |
| 2430 | end |
| 2431 | else if(tSREF_TO_RD_met) |
| 2432 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2433 | else |
| 2434 | controller_state <= `CS_SELF_REFRESH; |
| 2435 | end |
| 2436 | if (tSREF_TO_ANY_NON_RD_met && tSREF_TO_RD_met) |
| 2437 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2438 | else |
| 2439 | controller_state <= `CS_SELF_REFRESH; |
| 2440 | end // else: !if(command == `READ ) |
| 2441 | end // case: `CS_SELF_REFRESH |
| 2442 | |
| 2443 | `CS_POWER_DOWN: |
| 2444 | begin |
| 2445 | if(command == `NOP || command_DESELECT) |
| 2446 | begin |
| 2447 | if(cke) |
| 2448 | controller_state <= `CS_POWER_DOWN_EXIT; |
| 2449 | else |
| 2450 | controller_state <= `CS_POWER_DOWN; |
| 2451 | end |
| 2452 | else |
| 2453 | begin |
| 2454 | controller_state <= `CS_ILLEGAL; //err[6] |
| 2455 | ddr2_err[6] <= 1'b1; |
| 2456 | end |
| 2457 | end |
| 2458 | |
| 2459 | `CS_POWER_DOWN_EXIT: |
| 2460 | begin |
| 2461 | if(stop_time_after_PWD_EXIT) |
| 2462 | begin |
| 2463 | controller_state <= `CS_BANKS_ACTIVE_OR_IDLE; |
| 2464 | end |
| 2465 | else |
| 2466 | begin |
| 2467 | if ((command == `READ) && ~precharge_pwdn && ~tACTIVE_POWERDOWN_EXIT_TO_RD_met) |
| 2468 | begin |
| 2469 | controller_state <= `CS_ILLEGAL; // err[7] |
| 2470 | ddr2_err[7] <= 1'b1; |
| 2471 | end |
| 2472 | else if ((command != `READ) && precharge_pwdn && ~tPRECHARGE_POWERDOWN_EXIT_TO_NON_RD_met) |
| 2473 | begin |
| 2474 | controller_state <= `CS_ILLEGAL; // err[8] |
| 2475 | ddr2_err[8] <= 1'b1; |
| 2476 | end |
| 2477 | else |
| 2478 | controller_state <= controller_state; |
| 2479 | end |
| 2480 | end // case: `CS_POWER_DOWN_EXIT |
| 2481 | |
| 2482 | `CS_ILLEGAL: |
| 2483 | begin |
| 2484 | controller_state <= `CS_ILLEGAL; |
| 2485 | end |
| 2486 | |
| 2487 | default: |
| 2488 | begin |
| 2489 | if(command_DESELECT || command == `NOP) |
| 2490 | begin |
| 2491 | if(~cke) |
| 2492 | begin |
| 2493 | controller_state <= `CS_POWER_DOWN; |
| 2494 | precharge_pwdn <= 1'b0; // if not all bank idle, it is an active power-down |
| 2495 | end |
| 2496 | else |
| 2497 | begin |
| 2498 | controller_state <= controller_state; |
| 2499 | end |
| 2500 | end |
| 2501 | else |
| 2502 | begin |
| 2503 | if(~cke) |
| 2504 | begin |
| 2505 | controller_state <= `CS_ILLEGAL; //cke should not go low if not PWDN |
| 2506 | ddr2_err[9] <= 1'b1; |
| 2507 | end |
| 2508 | else |
| 2509 | controller_state <= controller_state; |
| 2510 | end // else: !if(command_DESELECT || command == `NOP) |
| 2511 | end // case: default |
| 2512 | |
| 2513 | endcase // case(controller_state) |
| 2514 | |
| 2515 | end // else: !if(all_bank_idle) |
| 2516 | |
| 2517 | end // end of Contoller FSM /*}}}*/ |
| 2518 | |
| 2519 | // Instantiantion of banks /*{{{*/ |
| 2520 | ddr_bank #(tMRD, |
| 2521 | tRFC, |
| 2522 | tXSRD, |
| 2523 | tXSNR, |
| 2524 | tRAS, |
| 2525 | tCAS, |
| 2526 | tRCD, |
| 2527 | tCCD, |
| 2528 | tRC, |
| 2529 | tRRD, |
| 2530 | tWTR, |
| 2531 | tRTW, |
| 2532 | tWR, |
| 2533 | tXP, |
| 2534 | tXARD, |
| 2535 | tRP, |
| 2536 | DATA_WIDTH, |
| 2537 | DATA_STROBE_NUM |
| 2538 | ) bank1( |
| 2539 | .ck (ck), |
| 2540 | .cke (cke), |
| 2541 | .areset (areset), |
| 2542 | .bank_cmd (bank1_command), |
| 2543 | .addr_10 (addr[10]), |
| 2544 | .mrs_bl (MRS_BL), |
| 2545 | .mrs_bt (MRS_BT), |
| 2546 | .mrs_cas (MRS_CAS), |
| 2547 | .mrs_wr (MRS_WR), |
| 2548 | .emrs_al (EMRS_AL), |
| 2549 | .global_tWRITE_TO (time_after_WRITE), |
| 2550 | .global_tREAD_TO (time_after_READ), |
| 2551 | .bank_status (bank1_status), |
| 2552 | .dq (dq), |
| 2553 | .dqs (dqs) |
| 2554 | ); |
| 2555 | |
| 2556 | |
| 2557 | ddr_bank #(tMRD, |
| 2558 | tRFC, |
| 2559 | tXSRD, |
| 2560 | tXSNR, |
| 2561 | tRAS, |
| 2562 | tCAS, |
| 2563 | tRCD, |
| 2564 | tCCD, |
| 2565 | tRC, |
| 2566 | tRRD, |
| 2567 | tWTR, |
| 2568 | tRTW, |
| 2569 | tWR, |
| 2570 | tXP, |
| 2571 | tXARD, |
| 2572 | tRP, |
| 2573 | DATA_WIDTH, |
| 2574 | DATA_STROBE_NUM |
| 2575 | ) bank2( |
| 2576 | .ck (ck), |
| 2577 | .cke (cke), |
| 2578 | .areset (areset), |
| 2579 | .bank_cmd (bank2_command), |
| 2580 | .addr_10 (addr[10]), |
| 2581 | .mrs_bl (MRS_BL), |
| 2582 | .mrs_bt (MRS_BT), |
| 2583 | .mrs_cas (MRS_CAS), |
| 2584 | .mrs_wr (MRS_WR), |
| 2585 | .emrs_al (EMRS_AL), |
| 2586 | .global_tWRITE_TO (time_after_WRITE), |
| 2587 | .global_tREAD_TO (time_after_READ), |
| 2588 | .bank_status (bank2_status), |
| 2589 | .dq (dq), |
| 2590 | .dqs (dqs) |
| 2591 | ); |
| 2592 | |
| 2593 | ddr_bank #(tMRD, |
| 2594 | tRFC, |
| 2595 | tXSRD, |
| 2596 | tXSNR, |
| 2597 | tRAS, |
| 2598 | tCAS, |
| 2599 | tRCD, |
| 2600 | tCCD, |
| 2601 | tRC, |
| 2602 | tRRD, |
| 2603 | tWTR, |
| 2604 | tRTW, |
| 2605 | tWR, |
| 2606 | tXP, |
| 2607 | tXARD, |
| 2608 | tRP, |
| 2609 | DATA_WIDTH, |
| 2610 | DATA_STROBE_NUM |
| 2611 | ) bank3( |
| 2612 | .ck (ck), |
| 2613 | .cke (cke), |
| 2614 | .areset (areset), |
| 2615 | .bank_cmd (bank3_command), |
| 2616 | .addr_10 (addr[10]), |
| 2617 | .mrs_bl (MRS_BL), |
| 2618 | .mrs_bt (MRS_BT), |
| 2619 | .mrs_cas (MRS_CAS), |
| 2620 | .mrs_wr (MRS_WR), |
| 2621 | .emrs_al (EMRS_AL), |
| 2622 | .global_tWRITE_TO (time_after_WRITE), |
| 2623 | .global_tREAD_TO (time_after_READ), |
| 2624 | .bank_status (bank3_status), |
| 2625 | .dq (dq), |
| 2626 | .dqs (dqs) |
| 2627 | ); |
| 2628 | |
| 2629 | ddr_bank #(tMRD, |
| 2630 | tRFC, |
| 2631 | tXSRD, |
| 2632 | tXSNR, |
| 2633 | tRAS, |
| 2634 | tCAS, |
| 2635 | tRCD, |
| 2636 | tCCD, |
| 2637 | tRC, |
| 2638 | tRRD, |
| 2639 | tWTR, |
| 2640 | tRTW, |
| 2641 | tWR, |
| 2642 | tXP, |
| 2643 | tXARD, |
| 2644 | tRP, |
| 2645 | DATA_WIDTH, |
| 2646 | DATA_STROBE_NUM |
| 2647 | ) bank4( |
| 2648 | .ck (ck), |
| 2649 | .cke (cke), |
| 2650 | .areset (areset), |
| 2651 | .bank_cmd (bank4_command), |
| 2652 | .addr_10 (addr[10]), |
| 2653 | .mrs_bl (MRS_BL), |
| 2654 | .mrs_bt (MRS_BT), |
| 2655 | .mrs_cas (MRS_CAS), |
| 2656 | .mrs_wr (MRS_WR), |
| 2657 | .emrs_al (EMRS_AL), |
| 2658 | .global_tWRITE_TO (time_after_WRITE), |
| 2659 | .global_tREAD_TO (time_after_READ), |
| 2660 | .bank_status (bank4_status), |
| 2661 | .dq (dq), |
| 2662 | .dqs (dqs) |
| 2663 | ); |
| 2664 | |
| 2665 | |
| 2666 | ddr_bank #(tMRD, |
| 2667 | tRFC, |
| 2668 | tXSRD, |
| 2669 | tXSNR, |
| 2670 | tRAS, |
| 2671 | tCAS, |
| 2672 | tRCD, |
| 2673 | tCCD, |
| 2674 | tRC, |
| 2675 | tRRD, |
| 2676 | tWTR, |
| 2677 | tRTW, |
| 2678 | tWR, |
| 2679 | tXP, |
| 2680 | tXARD, |
| 2681 | tRP, |
| 2682 | DATA_WIDTH, |
| 2683 | DATA_STROBE_NUM |
| 2684 | ) bank5( |
| 2685 | .ck (ck), |
| 2686 | .cke (cke), |
| 2687 | .areset (areset), |
| 2688 | .bank_cmd (bank5_command), |
| 2689 | .addr_10 (addr[10]), |
| 2690 | .mrs_bl (MRS_BL), |
| 2691 | .mrs_bt (MRS_BT), |
| 2692 | .mrs_cas (MRS_CAS), |
| 2693 | .mrs_wr (MRS_WR), |
| 2694 | .emrs_al (EMRS_AL), |
| 2695 | .global_tWRITE_TO (time_after_WRITE), |
| 2696 | .global_tREAD_TO (time_after_READ), |
| 2697 | .bank_status (bank5_status), |
| 2698 | .dq (dq), |
| 2699 | .dqs (dqs) |
| 2700 | ); |
| 2701 | |
| 2702 | |
| 2703 | ddr_bank #(tMRD, |
| 2704 | tRFC, |
| 2705 | tXSRD, |
| 2706 | tXSNR, |
| 2707 | tRAS, |
| 2708 | tCAS, |
| 2709 | tRCD, |
| 2710 | tCCD, |
| 2711 | tRC, |
| 2712 | tRRD, |
| 2713 | tWTR, |
| 2714 | tRTW, |
| 2715 | tWR, |
| 2716 | tXP, |
| 2717 | tXARD, |
| 2718 | tRP, |
| 2719 | DATA_WIDTH, |
| 2720 | DATA_STROBE_NUM |
| 2721 | ) bank6( |
| 2722 | .ck (ck), |
| 2723 | .cke (cke), |
| 2724 | .areset (areset), |
| 2725 | .bank_cmd (bank6_command), |
| 2726 | .addr_10 (addr[10]), |
| 2727 | .mrs_bl (MRS_BL), |
| 2728 | .mrs_bt (MRS_BT), |
| 2729 | .mrs_cas (MRS_CAS), |
| 2730 | .mrs_wr (MRS_WR), |
| 2731 | .emrs_al (EMRS_AL), |
| 2732 | .global_tWRITE_TO (time_after_WRITE), |
| 2733 | .global_tREAD_TO (time_after_READ), |
| 2734 | .bank_status (bank6_status), |
| 2735 | .dq (dq), |
| 2736 | .dqs (dqs) |
| 2737 | ); |
| 2738 | |
| 2739 | ddr_bank #(tMRD, |
| 2740 | tRFC, |
| 2741 | tXSRD, |
| 2742 | tXSNR, |
| 2743 | tRAS, |
| 2744 | tCAS, |
| 2745 | tRCD, |
| 2746 | tCCD, |
| 2747 | tRC, |
| 2748 | tRRD, |
| 2749 | tWTR, |
| 2750 | tRTW, |
| 2751 | tWR, |
| 2752 | tXP, |
| 2753 | tXARD, |
| 2754 | tRP, |
| 2755 | DATA_WIDTH, |
| 2756 | DATA_STROBE_NUM |
| 2757 | ) bank7( |
| 2758 | .ck (ck), |
| 2759 | .cke (cke), |
| 2760 | .areset (areset), |
| 2761 | .bank_cmd (bank7_command), |
| 2762 | .addr_10 (addr[10]), |
| 2763 | .mrs_bl (MRS_BL), |
| 2764 | .mrs_bt (MRS_BT), |
| 2765 | .mrs_cas (MRS_CAS), |
| 2766 | .mrs_wr (MRS_WR), |
| 2767 | .emrs_al (EMRS_AL), |
| 2768 | .global_tWRITE_TO (time_after_WRITE), |
| 2769 | .global_tREAD_TO (time_after_READ), |
| 2770 | .bank_status (bank7_status), |
| 2771 | .dq (dq), |
| 2772 | .dqs (dqs) |
| 2773 | ); |
| 2774 | |
| 2775 | ddr_bank #(tMRD, |
| 2776 | tRFC, |
| 2777 | tXSRD, |
| 2778 | tXSNR, |
| 2779 | tRAS, |
| 2780 | tCAS, |
| 2781 | tRCD, |
| 2782 | tCCD, |
| 2783 | tRC, |
| 2784 | tRRD, |
| 2785 | tWTR, |
| 2786 | tRTW, |
| 2787 | tWR, |
| 2788 | tXP, |
| 2789 | tXARD, |
| 2790 | tRP, |
| 2791 | DATA_WIDTH, |
| 2792 | DATA_STROBE_NUM |
| 2793 | ) bank8( |
| 2794 | .ck (ck), |
| 2795 | .cke (cke), |
| 2796 | .areset (areset), |
| 2797 | .bank_cmd (bank8_command), |
| 2798 | .addr_10 (addr[10]), |
| 2799 | .mrs_bl (MRS_BL), |
| 2800 | .mrs_bt (MRS_BT), |
| 2801 | .mrs_cas (MRS_CAS), |
| 2802 | .mrs_wr (MRS_WR), |
| 2803 | .emrs_al (EMRS_AL), |
| 2804 | .global_tWRITE_TO (time_after_WRITE), |
| 2805 | .global_tREAD_TO (time_after_READ), |
| 2806 | .bank_status (bank8_status), |
| 2807 | .dq (dq), |
| 2808 | .dqs (dqs) |
| 2809 | ); |
| 2810 | |
| 2811 | /*}}}*/ |
| 2812 | |
| 2813 | endmodule/*}}}*/ |
| 2814 | |
| 2815 | module ddr_bank (ck,cke,areset, bank_cmd, addr_10, mrs_bl, mrs_bt, mrs_cas, mrs_wr, emrs_al, /*{{{*/ |
| 2816 | global_tWRITE_TO, |
| 2817 | global_tREAD_TO, dqs, dq, |
| 2818 | bank_status); |
| 2819 | |
| 2820 | parameter tMRD = 2; // Mode reg set command cycle time -- |
| 2821 | // any new command needs to wait tMRD cycles after MRD |
| 2822 | parameter tRFC = 15; // Min delay between SHELF REFRESH to ACT/SHELF REFRESH |
| 2823 | parameter tXSRD = 200; // Min delay between exit SHELF REFRESH and a READ |
| 2824 | parameter tXSNR = 10; // Min delay between exit SHELF REFRESH and a non-READ |
| 2825 | parameter tRAS = 9; // Min delay between ACT and a PRECHARGE -- Rank Active Time |
| 2826 | parameter tCAS = 3; // Min CAS latency |
| 2827 | parameter tRCD = 3; // Min delay between ACT and a READ/WRITE to the same row (RAS -> CAS) |
| 2828 | parameter tCCD = 2; // Min delay between READ/WRITE -- CAS to CAS delay time |
| 2829 | parameter tRC = 12; // Min delay between successive ACTIVE to the same banks -- RAS Cycle time |
| 2830 | parameter tRRD = 2; // Min delay between successive ACTIVE to diff banks |
| 2831 | parameter tWTR = 2; // Min delay between a WRITE and a READ (WRITE -> READ) |
| 2832 | parameter tRTW = 4; // Min delay between a READ and a WRITE to the same bank (READ -> WRITE) |
| 2833 | parameter tWR = 3; // Write recovery time -- |
| 2834 | parameter tXP = 2; // Min delay from PRECHARGE Power-down Exit to non-read command |
| 2835 | parameter tXARD = 2; // Min delay from Active Power-down Exit to READ command |
| 2836 | parameter tRP = 3; // Row precharge period |
| 2837 | parameter DATA_WIDTH = 8; // Min data bus width |
| 2838 | parameter DATA_STROBE_NUM = 4; // numbers of data strobe signals (dqs, ldqs, udqs, rdqs) |
| 2839 | |
| 2840 | input ck; |
| 2841 | input cke; |
| 2842 | input areset; |
| 2843 | input [3:0] bank_cmd; |
| 2844 | input addr_10; // indicator for precharge of all banks |
| 2845 | input [3:0] mrs_bl; // burst len |
| 2846 | input mrs_bt; // burst type |
| 2847 | input [2:0] mrs_cas; // cas latency |
| 2848 | input [2:0] mrs_wr; // write recovery |
| 2849 | input [2:0] emrs_al; // additive latency |
| 2850 | input [5:0] global_tWRITE_TO; // time passed since the last WRITE |
| 2851 | input [5:0] global_tREAD_TO; // time passed since the last READ |
| 2852 | input [DATA_WIDTH - 1 : 0] dq; // Data |
| 2853 | input [DATA_STROBE_NUM - 1 : 0] dqs; // Data strobe |
| 2854 | |
| 2855 | output [2:0] bank_status; |
| 2856 | |
| 2857 | // Rule8: |
| 2858 | // if Time((Act(Bank x) -> Read(Bank x))) < tRCD_reg then |
| 2859 | // Time((Act(Bank x) -> Read(Bank x))) + Additive >= tRCD_reg |
| 2860 | |
| 2861 | reg [5:0] tACT_TO; // timer for the time passed by after an ACT |
| 2862 | reg [5:0] tWRITE_TO; // the time passed by after a WRITE |
| 2863 | reg [5:0] tREAD_TO; // the time passed by after a READ |
| 2864 | reg [5:0] tPRE_TO; // the time passed by after a PRECHARGE |
| 2865 | reg [2:0] bank_state; |
| 2866 | reg [18:0] ddr2_bank_err; |
| 2867 | reg begin_auto_pre; |
| 2868 | |
| 2869 | reg [4:0] tMRD_reg = tMRD; |
| 2870 | reg [4:0] tRFC_reg = tRFC; |
| 2871 | reg [8:0] tXSRD_reg = tXSRD; |
| 2872 | reg [4:0] tXSNR_reg = tXSNR; |
| 2873 | reg [4:0] tRAS_reg = tRAS; |
| 2874 | reg [4:0] tCAS_reg = tCAS; |
| 2875 | reg [4:0] tRCD_reg = tRCD; |
| 2876 | reg [4:0] tCCD_reg = tCCD; |
| 2877 | reg [4:0] tRC_reg = tRC; |
| 2878 | reg [4:0] tRRD_reg = tRRD; |
| 2879 | reg [4:0] tWTR_reg = tWTR; |
| 2880 | reg [4:0] tRTW_reg = tRTW; |
| 2881 | reg [4:0] tWR_reg = tWR; |
| 2882 | reg [4:0] tXP_reg = tXP; |
| 2883 | reg [4:0] tXARD_reg = tXARD; |
| 2884 | reg [4:0] tRP_reg = tRP; |
| 2885 | // reg DATA_WIDTH_reg = DATA_WIDTH; |
| 2886 | // reg DATA_STROBE_NUM_reg = DATA_STROBE_NUM; |
| 2887 | |
| 2888 | |
| 2889 | |
| 2890 | |
| 2891 | wire stop_tACT_TO; |
| 2892 | wire stop_tWRITE_TO; |
| 2893 | wire stop_tREAD_TO; |
| 2894 | wire stop_tPRE_TO; |
| 2895 | |
| 2896 | |
| 2897 | wire command_DESELECT = bank_cmd[3]; |
| 2898 | |
| 2899 | // time (ACT -> READ) + AL >= tRCD_reg |
| 2900 | // So, min time (ACT -> READ) >= tRCD_reg - AL |
| 2901 | wire tACT_TO_READ_met = (tACT_TO >= (tRCD_reg - emrs_al) ); |
| 2902 | |
| 2903 | wire tACT_TO_WRITE_met = (tACT_TO >= (tRCD_reg - emrs_al) ); |
| 2904 | wire tACT_TO_PRE_met = (tACT_TO >= tRAS_reg ); |
| 2905 | |
| 2906 | // min time (READ -> PRE ): additive + 1/2 * burst len |
| 2907 | wire tREAD_TO_PRE_met = (tREAD_TO >= (emrs_al + (mrs_bl >> 1)) ); |
| 2908 | // gloabl RD -> RD min delay |
| 2909 | wire tREAD_TO_READ_met = (global_tREAD_TO >= ( (mrs_bl > tCCD_reg) ? mrs_bl : tCCD_reg) ); |
| 2910 | // global READ -> WRITE min trun around time |
| 2911 | wire tREAD_TO_WRITE_met = (global_tREAD_TO >= tRTW_reg); |
| 2912 | |
| 2913 | |
| 2914 | wire tWRITE_TO_PRE_met = (tWRITE_TO >= (emrs_al + (mrs_cas - 1) + (mrs_bl >> 1) + mrs_wr ) ) ; |
| 2915 | // global WRITE -> WRITE min delay |
| 2916 | wire tWRITE_TO_WRITE_met = (global_tWRITE_TO >= ( (mrs_bl > tCCD_reg) ? mrs_bl : tCCD_reg) ); |
| 2917 | // global WRIE -> READ) min delay: WL + 1/2 * burst len + tWTR_reg, where WL (Write Latency) is (additive + CL - 1) |
| 2918 | |
| 2919 | wire tWRITE_TO_READ_met = (global_tWRITE_TO >= (emrs_al + (mrs_cas - 1) + (mrs_bl >> 1) + tWTR_reg) ) ; |
| 2920 | |
| 2921 | // min time (PRE -> Idle State): tRP_reg; See JESD79 Rel 2 Page14 |
| 2922 | wire tPRE_TO_IDLE_met = (tPRE_TO >= tRP_reg); |
| 2923 | |
| 2924 | assign stop_tACT_TO = (tACT_TO == 6'b111111) || |
| 2925 | ( tACT_TO_READ_met && tACT_TO_WRITE_met && tACT_TO_PRE_met); |
| 2926 | |
| 2927 | assign stop_tWRITE_TO = (tWRITE_TO == 6'b111111) || tWRITE_TO_PRE_met; |
| 2928 | |
| 2929 | assign stop_tREAD_TO = (tREAD_TO == 6'b111111) || tREAD_TO_PRE_met; |
| 2930 | |
| 2931 | assign stop_tPRE_TO = (tPRE_TO == 6'b111111 ) || tPRE_TO_IDLE_met; |
| 2932 | |
| 2933 | assign bank_status = bank_state; |
| 2934 | |
| 2935 | |
| 2936 | wire bank_cmd_ACT = (bank_cmd == `ACTIVE); |
| 2937 | |
| 2938 | /* Bank Error Conditions */ |
| 2939 | |
| 2940 | wire Ill_cmd_while_bank_idle = ddr2_bank_err[0]; |
| 2941 | wire Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met = ddr2_bank_err[1]; |
| 2942 | wire act_to_pre_timing_not_met = ddr2_bank_err[2]; |
| 2943 | wire act_to_rd_timing_not_met = ddr2_bank_err[3]; |
| 2944 | wire act_to_wr_timing_not_met = ddr2_bank_err[4]; |
| 2945 | wire Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met = ddr2_bank_err[5]; |
| 2946 | wire wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre = ddr2_bank_err[6]; |
| 2947 | wire wr_to_rd_timing_not_met_when_wr_to_rd = ddr2_bank_err[7]; |
| 2948 | wire wr_to_wr_timing_not_met = ddr2_bank_err[8]; |
| 2949 | wire Ill_cmd_after_wr = ddr2_bank_err[9]; // nor nop, rd, wr |
| 2950 | wire Ill_cmd_after_wra = ddr2_bank_err[10]; |
| 2951 | wire Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met = ddr2_bank_err[11]; |
| 2952 | wire rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre = ddr2_bank_err[12]; |
| 2953 | wire rd_to_rd_timing_not_met = ddr2_bank_err[13]; |
| 2954 | wire rd_to_wr_timing_not_met = ddr2_bank_err[14]; |
| 2955 | wire Ill_cmd_after_rd = ddr2_bank_err[15]; // nor nop, rd, wr |
| 2956 | wire Ill_cmd_after_rda = ddr2_bank_err[16]; |
| 2957 | wire Ill_cmd_after_pre = ddr2_bank_err[17]; |
| 2958 | wire Ill_cmd_while_bank_active = ddr2_bank_err[18]; |
| 2959 | wire Ill_bank_state = (bank_state == `CS_ILLEGAL); |
| 2960 | |
| 2961 | |
| 2962 | // always @( posedge areset or posedge ck) begin |
| 2963 | // if (areset) |
| 2964 | // ddr2_bank_err <= 18'b0; |
| 2965 | // else |
| 2966 | // ; |
| 2967 | // |
| 2968 | //end |
| 2969 | |
| 2970 | always @(posedge ck or posedge areset) begin |
| 2971 | if(areset) // we assume after a reset, Time (ACT -> Pre) is satisfied |
| 2972 | tACT_TO <= tRAS_reg; |
| 2973 | else if (bank_cmd_ACT) |
| 2974 | tACT_TO <= 6'd1; |
| 2975 | else if (~stop_tACT_TO) |
| 2976 | tACT_TO <= tACT_TO + 6'd1; |
| 2977 | end |
| 2978 | |
| 2979 | wire bank_cmd_NOP = (bank_cmd == `NOP) || command_DESELECT; |
| 2980 | wire bank_cmd_WRITE = (bank_cmd == `WRITE); |
| 2981 | always @(posedge ck or posedge areset or begin_auto_pre) begin |
| 2982 | if(areset) |
| 2983 | tWRITE_TO <= 6'd1; |
| 2984 | else if (bank_cmd_WRITE || begin_auto_pre) |
| 2985 | tWRITE_TO <= 6'd1; |
| 2986 | else if (~stop_tWRITE_TO) |
| 2987 | tWRITE_TO <= tWRITE_TO + 6'd1; |
| 2988 | end |
| 2989 | |
| 2990 | wire bank_cmd_READ = ( bank_cmd == `READ ); |
| 2991 | always @(posedge ck or posedge areset or begin_auto_pre) begin |
| 2992 | if(areset) |
| 2993 | tREAD_TO <= 6'd1; |
| 2994 | else if (bank_cmd_READ || begin_auto_pre) |
| 2995 | tREAD_TO <= 6'd1; |
| 2996 | else if (~stop_tREAD_TO) |
| 2997 | tREAD_TO <= tREAD_TO + 6'd1; |
| 2998 | end |
| 2999 | |
| 3000 | wire bank_cmd_PRECHARGE = (bank_cmd == `PRECHARGE ); |
| 3001 | wire bank_cmd_non_REF_MRS_NOP = (!( (bank_cmd == `REF_SREF) || |
| 3002 | (bank_cmd == `MRS) || |
| 3003 | (bank_cmd == `NOP || command_DESELECT ) |
| 3004 | )); |
| 3005 | always @(posedge ck or posedge areset) begin |
| 3006 | if(areset) |
| 3007 | tPRE_TO <= 6'd1; |
| 3008 | else if (bank_cmd_PRECHARGE) |
| 3009 | tPRE_TO <= 6'd1; |
| 3010 | else if (~stop_tPRE_TO) |
| 3011 | tPRE_TO <= tPRE_TO + 6'd1; |
| 3012 | end |
| 3013 | |
| 3014 | |
| 3015 | wire tACT_TO_READ_tACT_TO_WRITE_tACT_TO_PRE_not_met = (~tACT_TO_READ_met && |
| 3016 | ~tACT_TO_WRITE_met && |
| 3017 | ~tACT_TO_PRE_met); |
| 3018 | wire tWRITE_TO_READ_tWRITE_TO_PRE_not_met = ~tWRITE_TO_READ_met && ~tWRITE_TO_PRE_met; |
| 3019 | wire tREAD_TO_READ_tREAD_TO_PRE_not_met= ~tREAD_TO_READ_met && ~tREAD_TO_PRE_met; |
| 3020 | |
| 3021 | `ifdef REGISTERED_DIMMS |
| 3022 | wire [3:0] RL = mrs_cas + emrs_al + 1'b1; // RL = CL + AL |
| 3023 | `else |
| 3024 | wire [3:0] RL = mrs_cas + emrs_al; // RL = CL + AL |
| 3025 | `endif |
| 3026 | reg rd_dqs_not_asserted; |
| 3027 | reg [9:0] read_queue; |
| 3028 | reg [3:0] rd_data_window; |
| 3029 | wire err_rd_dqs_not_asserted_when_rd_data_ready = rd_dqs_not_asserted; |
| 3030 | |
| 3031 | initial |
| 3032 | begin |
| 3033 | rd_data_window <= 4'b0; |
| 3034 | read_queue <= 10'b0; |
| 3035 | rd_dqs_not_asserted <= 1'b0; |
| 3036 | end |
| 3037 | |
| 3038 | always @(posedge ck) |
| 3039 | begin |
| 3040 | read_queue = read_queue << 1; |
| 3041 | if(read_queue[RL]) |
| 3042 | begin |
| 3043 | rd_data_window = rd_data_window + (mrs_bl >> 1 ); |
| 3044 | end |
| 3045 | |
| 3046 | if(rd_data_window > 0) |
| 3047 | begin |
| 3048 | rd_dqs_not_asserted = (^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b1 && ^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b0 ); |
| 3049 | rd_data_window = rd_data_window - 1; |
| 3050 | end |
| 3051 | |
| 3052 | if(bank_cmd_READ) |
| 3053 | read_queue[0] <= 1'b1; |
| 3054 | end |
| 3055 | |
| 3056 | |
| 3057 | // WL = RL - 1 == AL + CL - 1 |
| 3058 | wire [3:0] WL = RL - 1; |
| 3059 | reg wr_dqs_not_asserted; |
| 3060 | wire err_wr_dqs_not_asserted_when_wr_data_ready = wr_dqs_not_asserted; |
| 3061 | reg [9:0] write_queue; |
| 3062 | reg [3:0] wr_data_window; |
| 3063 | |
| 3064 | initial |
| 3065 | begin |
| 3066 | wr_data_window <= 4'b0; |
| 3067 | write_queue <= 10'b0; |
| 3068 | wr_dqs_not_asserted <= 1'b0; |
| 3069 | end |
| 3070 | |
| 3071 | always @(posedge ck) |
| 3072 | begin |
| 3073 | write_queue = write_queue << 1; |
| 3074 | if(write_queue[WL]) |
| 3075 | begin |
| 3076 | wr_data_window = wr_data_window + (mrs_bl >> 1); |
| 3077 | end |
| 3078 | |
| 3079 | if(wr_data_window > 0) |
| 3080 | begin |
| 3081 | wr_dqs_not_asserted = (^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b1 && ^dqs[DATA_STROBE_NUM - 1 : 0] != 1'b0 ); |
| 3082 | wr_data_window = wr_data_window - 1; |
| 3083 | end |
| 3084 | |
| 3085 | if(bank_cmd_WRITE) |
| 3086 | write_queue[0] <= 1'b1; |
| 3087 | end |
| 3088 | |
| 3089 | |
| 3090 | // Bank FSM /*{{{*/ |
| 3091 | always @(posedge ck or posedge areset) |
| 3092 | begin |
| 3093 | if(areset) |
| 3094 | begin |
| 3095 | ddr2_bank_err <= 19'b0; |
| 3096 | bank_state <= `BS_IDLE; |
| 3097 | begin_auto_pre <= 1'b0; |
| 3098 | end |
| 3099 | else |
| 3100 | begin |
| 3101 | case (bank_state) |
| 3102 | `BS_IDLE: |
| 3103 | begin |
| 3104 | if (bank_cmd_PRECHARGE ) |
| 3105 | bank_state <= `BS_PRECHARGE; |
| 3106 | else if (bank_cmd_ACT) |
| 3107 | bank_state <= `BS_ROW_ACT; |
| 3108 | else if ( bank_cmd_non_REF_MRS_NOP ) |
| 3109 | begin |
| 3110 | bank_state <= `BS_ILLEGAL; |
| 3111 | ddr2_bank_err[0] <= 1'b1; |
| 3112 | end |
| 3113 | else |
| 3114 | bank_state <= `BS_IDLE; |
| 3115 | end |
| 3116 | |
| 3117 | // I merge the ROW_ACTIVATING state into the ROW_ACT state, |
| 3118 | // since ROW_ACTIVATING -> ROW_ACT is an auto sequence |
| 3119 | `BS_ROW_ACT: |
| 3120 | begin |
| 3121 | if(tACT_TO_READ_tACT_TO_WRITE_tACT_TO_PRE_not_met) |
| 3122 | begin |
| 3123 | if(bank_cmd_NOP) |
| 3124 | bank_state <= bank_state; |
| 3125 | else |
| 3126 | begin |
| 3127 | bank_state <= `BS_ILLEGAL; |
| 3128 | ddr2_bank_err[1] <= 1'b1; |
| 3129 | end |
| 3130 | end |
| 3131 | else if (bank_cmd_PRECHARGE) |
| 3132 | begin |
| 3133 | if (tACT_TO_PRE_met) |
| 3134 | bank_state <= `BS_PRECHARGE; |
| 3135 | else |
| 3136 | begin |
| 3137 | bank_state <= `BS_ILLEGAL; |
| 3138 | ddr2_bank_err[2] <= 1'b1; |
| 3139 | end |
| 3140 | end |
| 3141 | else if (bank_cmd_READ) |
| 3142 | begin |
| 3143 | if(tACT_TO_READ_met) |
| 3144 | // If a READ is with addr[10] asserted, autopre is performed |
| 3145 | if(addr_10) |
| 3146 | bank_state <= `BS_READING_AUTOPRE; |
| 3147 | else |
| 3148 | bank_state <= `BS_READING; |
| 3149 | else |
| 3150 | begin |
| 3151 | bank_state <= `BS_ILLEGAL; |
| 3152 | ddr2_bank_err[3] <= 1'b1; |
| 3153 | end |
| 3154 | end |
| 3155 | else if (bank_cmd_WRITE) |
| 3156 | begin |
| 3157 | if (tACT_TO_WRITE_met) |
| 3158 | if(addr_10) |
| 3159 | bank_state <= `BS_WRITING_AUTOPRE; |
| 3160 | else |
| 3161 | bank_state <= `BS_WRITING; |
| 3162 | else |
| 3163 | begin |
| 3164 | bank_state <= `BS_ILLEGAL; |
| 3165 | ddr2_bank_err[4] <= 1'b1; |
| 3166 | end |
| 3167 | end |
| 3168 | else if (bank_cmd_NOP) |
| 3169 | bank_state <= bank_state; |
| 3170 | else |
| 3171 | begin |
| 3172 | bank_state <= `BS_ILLEGAL; |
| 3173 | ddr2_bank_err[18] <= 1'b1; |
| 3174 | end |
| 3175 | end // BS_ROW_ACT |
| 3176 | |
| 3177 | |
| 3178 | `BS_WRITING: |
| 3179 | begin |
| 3180 | if(tWRITE_TO_READ_tWRITE_TO_PRE_not_met) |
| 3181 | begin |
| 3182 | if(bank_cmd_NOP) |
| 3183 | bank_state <= bank_state; |
| 3184 | else |
| 3185 | begin |
| 3186 | bank_state <= `BS_ILLEGAL; |
| 3187 | ddr2_bank_err[5] <= 1'b1; |
| 3188 | end |
| 3189 | end |
| 3190 | else if (bank_cmd_PRECHARGE) |
| 3191 | begin |
| 3192 | if (tACT_TO_PRE_met && tWRITE_TO_PRE_met) |
| 3193 | bank_state <= `BS_PRECHARGE; |
| 3194 | else |
| 3195 | begin |
| 3196 | bank_state <= `BS_ILLEGAL; |
| 3197 | ddr2_bank_err[6] <= 1'b1; |
| 3198 | end |
| 3199 | end |
| 3200 | else if (bank_cmd_READ) |
| 3201 | begin |
| 3202 | if(tWRITE_TO_READ_met) |
| 3203 | // If a READ is with addr[10] asserted, autopre is performed |
| 3204 | if(addr_10) |
| 3205 | bank_state <= `BS_READING_AUTOPRE; |
| 3206 | else |
| 3207 | bank_state <= `BS_READING; |
| 3208 | else |
| 3209 | begin |
| 3210 | bank_state <= `BS_ILLEGAL; |
| 3211 | ddr2_bank_err[7] <= 1'b1; |
| 3212 | end |
| 3213 | end |
| 3214 | else if (bank_cmd_WRITE) |
| 3215 | begin |
| 3216 | if (tWRITE_TO_WRITE_met) |
| 3217 | if(addr_10) |
| 3218 | bank_state <= `BS_WRITING_AUTOPRE; |
| 3219 | else |
| 3220 | bank_state <= `BS_WRITING; |
| 3221 | else |
| 3222 | begin |
| 3223 | bank_state <= `BS_ILLEGAL; |
| 3224 | ddr2_bank_err[8] <= 1'b1; |
| 3225 | end |
| 3226 | end |
| 3227 | else if (bank_cmd_NOP) |
| 3228 | begin |
| 3229 | // from WRITE to BS_ROW_ACT is an auto path which |
| 3230 | // means if tWRIE_TO_READ_met && tWRITE_TO_WRITE_met && |
| 3231 | // tWRITE_TO_PRE_met |
| 3232 | |
| 3233 | if(tWRITE_TO_READ_met && tWRITE_TO_WRITE_met && tWRITE_TO_PRE_met) |
| 3234 | bank_state <= `BS_ROW_ACT; |
| 3235 | else |
| 3236 | bank_state <= bank_state; |
| 3237 | end |
| 3238 | else |
| 3239 | begin |
| 3240 | bank_state <= `BS_ILLEGAL; |
| 3241 | ddr2_bank_err[9] <= 1'b1; |
| 3242 | end |
| 3243 | end // case: `BS_WRITING |
| 3244 | |
| 3245 | |
| 3246 | // from WRITE_A to PRE is an auto path when tWRITE_TO_PRE_met |
| 3247 | `BS_WRITING_AUTOPRE: |
| 3248 | begin |
| 3249 | if (bank_cmd_NOP) |
| 3250 | begin |
| 3251 | if(tWRITE_TO_PRE_met) |
| 3252 | begin |
| 3253 | bank_state <= `BS_PRECHARGE; |
| 3254 | begin_auto_pre <= 1'b1; |
| 3255 | end |
| 3256 | else |
| 3257 | bank_state <= bank_state; |
| 3258 | end |
| 3259 | else |
| 3260 | begin |
| 3261 | bank_state <= `BS_ILLEGAL; |
| 3262 | ddr2_bank_err[10] <= 1'b1; |
| 3263 | end |
| 3264 | |
| 3265 | end // case: `BS_WRITING_AUTOPRE |
| 3266 | |
| 3267 | |
| 3268 | `BS_READING: |
| 3269 | begin |
| 3270 | if(tREAD_TO_READ_tREAD_TO_PRE_not_met) |
| 3271 | begin |
| 3272 | if(bank_cmd_NOP) |
| 3273 | bank_state <= bank_state; |
| 3274 | else |
| 3275 | begin |
| 3276 | bank_state <= `BS_ILLEGAL; |
| 3277 | ddr2_bank_err[11] <= 1'b1; |
| 3278 | end |
| 3279 | end |
| 3280 | else if (bank_cmd_PRECHARGE) |
| 3281 | begin |
| 3282 | if (tACT_TO_PRE_met && tREAD_TO_PRE_met) |
| 3283 | bank_state <= `BS_PRECHARGE; |
| 3284 | else |
| 3285 | begin |
| 3286 | bank_state <= `BS_ILLEGAL; |
| 3287 | ddr2_bank_err[12] <= 1'b1; |
| 3288 | end |
| 3289 | end |
| 3290 | else if (bank_cmd_READ) |
| 3291 | begin |
| 3292 | if(tREAD_TO_READ_met) |
| 3293 | // If a READ is with addr[10] asserted, autopre is performed |
| 3294 | if(addr_10) |
| 3295 | bank_state <= `BS_READING_AUTOPRE; |
| 3296 | else |
| 3297 | bank_state <= `BS_READING; |
| 3298 | else |
| 3299 | begin |
| 3300 | bank_state <= `BS_ILLEGAL; |
| 3301 | ddr2_bank_err[13] <= 1'b1; |
| 3302 | end |
| 3303 | end |
| 3304 | else if (bank_cmd_WRITE) |
| 3305 | begin |
| 3306 | if (tREAD_TO_WRITE_met) |
| 3307 | if(addr_10) |
| 3308 | bank_state <= `BS_WRITING_AUTOPRE; |
| 3309 | else |
| 3310 | bank_state <= `BS_WRITING; |
| 3311 | else |
| 3312 | begin |
| 3313 | bank_state <= `BS_ILLEGAL; |
| 3314 | ddr2_bank_err[14] <= 1'b1; |
| 3315 | end |
| 3316 | end |
| 3317 | else if (bank_cmd_NOP) |
| 3318 | begin |
| 3319 | // from READ to BS_ROW_ACT is an auto path which |
| 3320 | // means if tREAD_TO_READ_met && tREAD_TO_WRITE_met && |
| 3321 | // tREAD_TO_PRE_met |
| 3322 | if(tREAD_TO_READ_met && tREAD_TO_WRITE_met && tREAD_TO_PRE_met) |
| 3323 | bank_state <= `BS_ROW_ACT; |
| 3324 | else |
| 3325 | bank_state <= bank_state; |
| 3326 | end |
| 3327 | else |
| 3328 | begin |
| 3329 | bank_state <= `BS_ILLEGAL; |
| 3330 | ddr2_bank_err[15] <= 1'b1; |
| 3331 | end |
| 3332 | end // case: `BS_READING |
| 3333 | |
| 3334 | `BS_READING_AUTOPRE: |
| 3335 | begin |
| 3336 | if (bank_cmd_NOP) |
| 3337 | begin |
| 3338 | if(tREAD_TO_PRE_met) |
| 3339 | begin |
| 3340 | bank_state <= `BS_PRECHARGE; |
| 3341 | begin_auto_pre <= 1'b1; |
| 3342 | end |
| 3343 | else |
| 3344 | bank_state <= bank_state; |
| 3345 | end |
| 3346 | else |
| 3347 | begin |
| 3348 | bank_state <= `BS_ILLEGAL; |
| 3349 | ddr2_bank_err[16] <= 1'b1; |
| 3350 | end |
| 3351 | end |
| 3352 | |
| 3353 | `BS_PRECHARGE: |
| 3354 | begin |
| 3355 | if(bank_cmd_NOP) |
| 3356 | if(~tPRE_TO_IDLE_met) |
| 3357 | bank_state <= bank_state; |
| 3358 | else |
| 3359 | begin |
| 3360 | bank_state <= `BS_IDLE; |
| 3361 | begin_auto_pre <= 1'b0; |
| 3362 | end |
| 3363 | else |
| 3364 | begin |
| 3365 | bank_state <= `BS_ILLEGAL; |
| 3366 | ddr2_bank_err[17] <= 1'b1; |
| 3367 | end |
| 3368 | end |
| 3369 | |
| 3370 | `CS_ILLEGAL: |
| 3371 | begin |
| 3372 | bank_state <= `BS_ILLEGAL; |
| 3373 | end // CS_ILLEGAL |
| 3374 | |
| 3375 | endcase // case(bank_state) |
| 3376 | end // else: !if(arese) |
| 3377 | end // always @(posedge ck or posedge areset) /*}}}*/ |
| 3378 | |
| 3379 | `ifdef DDR2_0IN_SIM_MON /*{{{*/ |
| 3380 | always @(posedge ck) begin |
| 3381 | `ifdef NO_Ill_cmd_while_bank_idle_CHECK |
| 3382 | `else |
| 3383 | if (Ill_cmd_while_bank_idle) |
| 3384 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_while_bank_idle \n"); // 0in < fire -message ("Ill_cmd_while_bank_idle \n") |
| 3385 | `endif |
| 3386 | |
| 3387 | `ifdef NO_Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met_CHECK |
| 3388 | `else |
| 3389 | if (Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met) |
| 3390 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met \n"); //0in < fire -message ("Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met \n") |
| 3391 | `endif |
| 3392 | |
| 3393 | `ifdef NO_act_to_pre_timing_not_met_CHECK |
| 3394 | `else |
| 3395 | if (act_to_pre_timing_not_met ) |
| 3396 | `PR_ERROR("ddr2_monitor", `ERROR, "act_to_pre_timing_not_met\n"); //0in < fire -message ("act_to_pre_timing_not_met \n") |
| 3397 | `endif |
| 3398 | |
| 3399 | `ifdef NO_act_to_rd_timing_not_met_CHECK |
| 3400 | `else |
| 3401 | if (act_to_rd_timing_not_met ) |
| 3402 | `PR_ERROR("ddr2_monitor", `ERROR, "act_to_rd_timing_not_met\n"); //0in < fire -message ("act_to_rd_timing_not_met \n") |
| 3403 | `endif |
| 3404 | |
| 3405 | `ifdef NO_act_to_wr_timing_not_met_CHECK |
| 3406 | `else |
| 3407 | if (act_to_wr_timing_not_met ) |
| 3408 | `PR_ERROR("ddr2_monitor", `ERROR, "act_to_wr_timing_not_met\n"); //0in < fire -message ("act_to_wr_timing_not_met \n") |
| 3409 | `endif |
| 3410 | |
| 3411 | `ifdef NO_Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met_CHECK |
| 3412 | `else |
| 3413 | if (Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met ) |
| 3414 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met\n"); //0in < fire -message ("Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met \n") |
| 3415 | `endif |
| 3416 | |
| 3417 | `ifdef NO_wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre_CHECK |
| 3418 | `else |
| 3419 | if (wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre ) |
| 3420 | `PR_ERROR("ddr2_monitor", `ERROR, "wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre\n"); //0in < fire -message ("wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre \n") |
| 3421 | `endif |
| 3422 | |
| 3423 | `ifdef NO_wr_to_rd_timing_not_met_when_wr_to_rd_CHECK |
| 3424 | `else |
| 3425 | if (wr_to_rd_timing_not_met_when_wr_to_rd ) |
| 3426 | `PR_ERROR("ddr2_monitor", `ERROR, "wr_to_rd_timing_not_met_when_wr_to_rd\n"); //0in < fire -message ("wr_to_rd_timing_not_met_when_wr_to_rd \n") |
| 3427 | `endif |
| 3428 | |
| 3429 | `ifdef NO_wr_to_wr_timing_not_met_CHECK |
| 3430 | `else |
| 3431 | if (wr_to_wr_timing_not_met ) |
| 3432 | `PR_ERROR("ddr2_monitor", `ERROR, "wr_to_wr_timing_not_met\n"); //0in < fire -message ("wr_to_wr_timing_not_met \n") |
| 3433 | `endif |
| 3434 | |
| 3435 | `ifdef NO_Ill_cmd_after_wr_CHECK |
| 3436 | `else |
| 3437 | if (Ill_cmd_after_wr ) |
| 3438 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_wr\n"); //0in < fire -message ("Ill_cmd_after_wr \n") |
| 3439 | `endif |
| 3440 | |
| 3441 | `ifdef NO_Ill_cmd_after_wra_CHECK |
| 3442 | `else |
| 3443 | if (Ill_cmd_after_wra ) |
| 3444 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_wra\n"); //0in < fire -message ("Ill_cmd_after_wra \n") |
| 3445 | `endif |
| 3446 | |
| 3447 | `ifdef NO_Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met_CHECK |
| 3448 | `else |
| 3449 | if (Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met ) |
| 3450 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met\n"); //0in < fire -message ("Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met \n") |
| 3451 | `endif |
| 3452 | |
| 3453 | `ifdef NO_rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre_CHECK |
| 3454 | `else |
| 3455 | if (rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre ) |
| 3456 | `PR_ERROR("ddr2_monitor", `ERROR, "rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre\n"); //0in < fire -message ("rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre \n") |
| 3457 | `endif |
| 3458 | |
| 3459 | `ifdef NO_rd_to_rd_timing_not_met_CHECK |
| 3460 | `else |
| 3461 | if (rd_to_rd_timing_not_met ) |
| 3462 | `PR_ERROR("ddr2_monitor", `ERROR, "rd_to_rd_timing_not_met\n"); //0in < fire -message ("rd_to_rd_timing_not_met \n") |
| 3463 | `endif |
| 3464 | |
| 3465 | `ifdef NO_rd_to_wr_timing_not_met_CHECK |
| 3466 | `else |
| 3467 | if (rd_to_wr_timing_not_met ) |
| 3468 | `PR_ERROR("ddr2_monitor", `ERROR, "rd_to_wr_timing_not_met\n"); //0in < fire -message ("rd_to_wr_timing_not_met \n") |
| 3469 | `endif |
| 3470 | |
| 3471 | `ifdef NO_Ill_cmd_after_rd_CHECK |
| 3472 | `else |
| 3473 | if (Ill_cmd_after_rd ) |
| 3474 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_rd\n"); //0in < fire -message ("Ill_cmd_after_rd \n") |
| 3475 | `endif |
| 3476 | |
| 3477 | `ifdef NO_Ill_cmd_after_rda_CHECK |
| 3478 | `else |
| 3479 | if (Ill_cmd_after_rda ) |
| 3480 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_rda\n"); //0in < fire -message ("Ill_cmd_after_rda \n") |
| 3481 | `endif |
| 3482 | |
| 3483 | `ifdef NO_Ill_cmd_after_pre_CHECK |
| 3484 | `else |
| 3485 | if (Ill_cmd_after_pre ) |
| 3486 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_pre\n"); //0in < fire -message ("Ill_cmd_after_pre \n") |
| 3487 | `endif |
| 3488 | |
| 3489 | `ifdef NO_Ill_cmd_while_bank_active_CHECK |
| 3490 | `else |
| 3491 | if(Ill_cmd_while_bank_active) |
| 3492 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_while_bank_active\n"); // 0in < fire -message ("Ill_cmd_while_bank_active\n") |
| 3493 | `endif |
| 3494 | |
| 3495 | `ifdef NO_Ill_bank_state_CHECK |
| 3496 | `else |
| 3497 | if (Ill_bank_state ) |
| 3498 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_bank_state\n"); //0in < fire -message ("Ill_bank_state \n") |
| 3499 | `endif |
| 3500 | |
| 3501 | `ifdef NO_err_rd_dqs_not_asserted_when_rd_data_ready_CHECK |
| 3502 | `else |
| 3503 | if(err_rd_dqs_not_asserted_when_rd_data_ready) |
| 3504 | `PR_ERROR("ddr2_monitor", `ERROR, "err_rd_dqs_not_asserted_when_rd_data_ready\n"); // 0in < fire -message ("err_rd_dqs_not_asserted_when_rd_data_ready\n") |
| 3505 | `endif |
| 3506 | |
| 3507 | `ifdef NO_err_wr_dqs_not_asserted_when_wr_data_ready_CHECK |
| 3508 | `else |
| 3509 | if(err_wr_dqs_not_asserted_when_wr_data_ready) |
| 3510 | `PR_ERROR("ddr2_monitor", `ERROR, "err_wr_dqs_not_asserted_when_wr_data_ready\n"); // 0in < fire -message ("err_wr_dqs_not_asserted_when_wr_data_ready\n") |
| 3511 | `endif |
| 3512 | |
| 3513 | end |
| 3514 | `else /*}}}*/ |
| 3515 | `ifdef DDR2_OVA_SIM_MON /*{{{*/ |
| 3516 | always @(posedge ck) begin |
| 3517 | `ifdef NO_Ill_cmd_while_bank_idle_CHECK |
| 3518 | `else |
| 3519 | if (Ill_cmd_while_bank_idle) |
| 3520 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_while_bank_idle \n"); |
| 3521 | /* ova ova_asserted ddr2_bank_ova1 |
| 3522 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_while_bank_idle\n", `SEVERITY, `CATEGORY) |
| 3523 | (!(areset), ck, !(Ill_cmd_while_bank_idle), `START, `STOP ); */ |
| 3524 | `endif |
| 3525 | |
| 3526 | `ifdef NO_Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met_CHECK |
| 3527 | `else |
| 3528 | if (Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met) |
| 3529 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met \n"); |
| 3530 | /* ova ova_asserted ddr2_bank_ova2 |
| 3531 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3532 | (!(areset), ck, !(Ill_cmd_after_act_while_act_to_rd_wr_pre_timing_not_met), `START, `STOP ); */ |
| 3533 | `endif |
| 3534 | |
| 3535 | `ifdef NO_act_to_pre_timing_not_met_CHECK |
| 3536 | `else |
| 3537 | if (act_to_pre_timing_not_met ) |
| 3538 | `PR_ERROR("ddr2_monitor", `ERROR, "act_to_pre_timing_not_met\n"); |
| 3539 | /* ova ova_asserted ddr2_bank_ova3 |
| 3540 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: act_to_pre_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3541 | (!(areset), ck, !(act_to_pre_timing_not_met), `START, `STOP ); */ |
| 3542 | `endif |
| 3543 | |
| 3544 | `ifdef NO_act_to_rd_timing_not_met_CHECK |
| 3545 | `else |
| 3546 | if (act_to_rd_timing_not_met ) |
| 3547 | `PR_ERROR("ddr2_monitor", `ERROR, "act_to_rd_timing_not_met\n"); |
| 3548 | /* ova ova_asserted ddr2_bank_ova4 |
| 3549 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: act_to_rd_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3550 | (!(areset), ck, !(act_to_rd_timing_not_met), `START, `STOP ); */ |
| 3551 | `endif |
| 3552 | |
| 3553 | `ifdef NO_act_to_wr_timing_not_met_CHECK |
| 3554 | `else |
| 3555 | if (act_to_wr_timing_not_met ) |
| 3556 | `PR_ERROR("ddr2_monitor", `ERROR, "act_to_wr_timing_not_met\n"); |
| 3557 | /* ova ova_asserted ddr2_bank_ova5 |
| 3558 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: act_to_wr_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3559 | (!(areset), ck, !(act_to_wr_timing_not_met), `START, `STOP ); */ |
| 3560 | `endif |
| 3561 | |
| 3562 | `ifdef NO_Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met_CHECK |
| 3563 | `else |
| 3564 | if (Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met ) |
| 3565 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met\n"); |
| 3566 | /* ova ova_asserted ddr2_bank_ova6 |
| 3567 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3568 | (!(areset), ck, !(Ill_cmd_after_wr_while_wr_to_rd_pre_timing_not_met), `START, `STOP ); */ |
| 3569 | `endif |
| 3570 | |
| 3571 | `ifdef NO_wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre_CHECK |
| 3572 | `else |
| 3573 | if (wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre ) |
| 3574 | `PR_ERROR("ddr2_monitor", `ERROR, "wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre\n"); |
| 3575 | /* ova ova_asserted ddr2_bank_ova7 |
| 3576 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre\n", `SEVERITY, `CATEGORY) |
| 3577 | (!(areset), ck, !(wr_to_pre_or_act_to_pre_timing_not_met_when_wr_to_pre), `START, `STOP ); */ |
| 3578 | `endif |
| 3579 | |
| 3580 | `ifdef NO_wr_to_rd_timing_not_met_when_wr_to_rd_CHECK |
| 3581 | `else |
| 3582 | if (wr_to_rd_timing_not_met_when_wr_to_rd ) |
| 3583 | `PR_ERROR("ddr2_monitor", `ERROR, "wr_to_rd_timing_not_met_when_wr_to_rd\n"); |
| 3584 | /* ova ova_asserted ddr2_bank_ova8 |
| 3585 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: wr_to_rd_timing_not_met_when_wr_to_rd\n", `SEVERITY, `CATEGORY) |
| 3586 | (!(areset), ck, !(wr_to_rd_timing_not_met_when_wr_to_rd), `START, `STOP ); */ |
| 3587 | `endif |
| 3588 | |
| 3589 | `ifdef NO_wr_to_wr_timing_not_met_CHECK |
| 3590 | `else |
| 3591 | if (wr_to_wr_timing_not_met ) |
| 3592 | `PR_ERROR("ddr2_monitor", `ERROR, "wr_to_wr_timing_not_met\n"); |
| 3593 | /* ova ova_asserted ddr2_bank_ova9 |
| 3594 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: wr_to_wr_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3595 | (!(areset), ck, !(wr_to_wr_timing_not_met), `START, `STOP ); */ |
| 3596 | `endif |
| 3597 | |
| 3598 | `ifdef NO_Ill_cmd_after_wr_CHECK |
| 3599 | `else |
| 3600 | if (Ill_cmd_after_wr ) |
| 3601 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_wr\n"); |
| 3602 | /* ova ova_asserted ddr2_bank_ova10 |
| 3603 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_wr\n", `SEVERITY, `CATEGORY) |
| 3604 | (!(areset), ck, !(Ill_cmd_after_wr), `START, `STOP ); */ |
| 3605 | `endif |
| 3606 | |
| 3607 | `ifdef NO_Ill_cmd_after_wra_CHECK |
| 3608 | `else |
| 3609 | if (Ill_cmd_after_wra ) |
| 3610 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_wra\n"); |
| 3611 | /* ova ova_asserted ddr2_bank_ova11 |
| 3612 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_wra\n", `SEVERITY, `CATEGORY) |
| 3613 | (!(areset), ck, !(Ill_cmd_after_wra), `START, `STOP ); */ |
| 3614 | `endif |
| 3615 | |
| 3616 | `ifdef NO_Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met_CHECK |
| 3617 | `else |
| 3618 | if (Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met ) |
| 3619 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met\n"); |
| 3620 | /* ova ova_asserted ddr2_bank_ova12 |
| 3621 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3622 | (!(areset), ck, !(Ill_cmd_after_rd_while_rd_to_rd_and_rd_pre_timing_not_met), `START, `STOP ); */ |
| 3623 | `endif |
| 3624 | |
| 3625 | `ifdef NO_rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre_CHECK |
| 3626 | `else |
| 3627 | if (rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre ) |
| 3628 | `PR_ERROR("ddr2_monitor", `ERROR, "rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre\n"); |
| 3629 | /* ova ova_asserted ddr2_bank_ova13 |
| 3630 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre\n", `SEVERITY, `CATEGORY) |
| 3631 | (!(areset), ck, !(rd_to_pre_or_act_to_pre_timing_not_met_when_rd_pre), `START, `STOP ); */ |
| 3632 | `endif |
| 3633 | |
| 3634 | `ifdef NO_rd_to_rd_timing_not_met_CHECK |
| 3635 | `else |
| 3636 | if (rd_to_rd_timing_not_met ) |
| 3637 | `PR_ERROR("ddr2_monitor", `ERROR, "rd_to_rd_timing_not_met\n"); |
| 3638 | /* ova ova_asserted ddr2_bank_ova14 |
| 3639 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: rd_to_rd_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3640 | (!(areset), ck, !(rd_to_rd_timing_not_met), `START, `STOP ); */ |
| 3641 | `endif |
| 3642 | |
| 3643 | `ifdef NO_rd_to_wr_timing_not_met_CHECK |
| 3644 | `else |
| 3645 | if (rd_to_wr_timing_not_met ) |
| 3646 | `PR_ERROR("ddr2_monitor", `ERROR, "rd_to_wr_timing_not_met\n"); |
| 3647 | /* ova ova_asserted ddr2_bank_ova15 |
| 3648 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: rd_to_wr_timing_not_met\n", `SEVERITY, `CATEGORY) |
| 3649 | (!(areset), ck, !(rd_to_wr_timing_not_met), `START, `STOP ); */ |
| 3650 | `endif |
| 3651 | |
| 3652 | `ifdef NO_Ill_cmd_after_rd_CHECK |
| 3653 | `else |
| 3654 | if (Ill_cmd_after_rd ) |
| 3655 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_rd\n"); |
| 3656 | /* ova ova_asserted ddr2_bank_ova16 |
| 3657 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_rd\n", `SEVERITY, `CATEGORY) |
| 3658 | (!(areset), ck, !(Ill_cmd_after_rd), `START, `STOP ); */ |
| 3659 | `endif |
| 3660 | |
| 3661 | `ifdef NO_Ill_cmd_after_rda_CHECK |
| 3662 | `else |
| 3663 | if (Ill_cmd_after_rda ) |
| 3664 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_rda\n"); |
| 3665 | /* ova ova_asserted ddr2_bank_ova17 |
| 3666 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_rda\n", `SEVERITY, `CATEGORY) |
| 3667 | (!(areset), ck, !(Ill_cmd_after_rda), `START, `STOP ); */ |
| 3668 | `endif |
| 3669 | |
| 3670 | `ifdef NO_Ill_cmd_after_pre_CHECK |
| 3671 | `else |
| 3672 | if (Ill_cmd_after_pre ) |
| 3673 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_after_pre\n"); |
| 3674 | /* ova ova_asserted ddr2_bank_ova18 |
| 3675 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_after_pre\n", `SEVERITY, `CATEGORY) |
| 3676 | (!(areset), ck, !(Ill_cmd_after_pre), `START, `STOP ); */ |
| 3677 | `endif |
| 3678 | |
| 3679 | `ifdef NO_Ill_cmd_while_bank_active_CHECK |
| 3680 | `else |
| 3681 | if(Ill_cmd_while_bank_active) |
| 3682 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_cmd_while_bank_active\n"); |
| 3683 | /* ova ova_asserted ddr2_bank_ova19 |
| 3684 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_cmd_while_bank_active\n", `SEVERITY, `CATEGORY) |
| 3685 | (!(areset), ck, !(Ill_cmd_while_bank_active), `START, `STOP ); */ |
| 3686 | `endif |
| 3687 | |
| 3688 | `ifdef NO_Ill_bank_state_CHECK |
| 3689 | `else |
| 3690 | if (Ill_bank_state ) |
| 3691 | `PR_ERROR("ddr2_monitor", `ERROR, "Ill_bank_state\n"); |
| 3692 | /* ova ova_asserted ddr2_bank_ova20 |
| 3693 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: Ill_bank_state\n", `SEVERITY, `CATEGORY) |
| 3694 | (!(areset), ck, !(Ill_bank_state), `START, `STOP ); */ |
| 3695 | `endif |
| 3696 | |
| 3697 | `ifdef NO_err_rd_dqs_not_asserted_when_rd_data_ready_CHECK |
| 3698 | `else |
| 3699 | if(err_rd_dqs_not_asserted_when_rd_data_ready) |
| 3700 | `PR_ERROR("ddr2_monitor", `ERROR, "err_rd_dqs_not_asserted_when_rd_data_ready\n"); |
| 3701 | /* ova ova_asserted ddr2_bank_ova21 |
| 3702 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: err_rd_dqs_not_asserted_when_rd_data_ready\n", `SEVERITY, `CATEGORY) |
| 3703 | (!(areset), ck, !(err_rd_dqs_not_asserted_when_rd_data_ready), `START, `STOP ); */ |
| 3704 | `endif |
| 3705 | |
| 3706 | `ifdef NO_err_wr_dqs_not_asserted_when_wr_data_ready_CHECK |
| 3707 | `else |
| 3708 | if(err_wr_dqs_not_asserted_when_wr_data_ready) |
| 3709 | `PR_ERROR("ddr2_monitor", `ERROR, "err_wr_dqs_not_asserted_when_wr_data_ready\n"); |
| 3710 | /* ova ova_asserted ddr2_bank_ova22 |
| 3711 | #(`DELAY, `EDGE_EXPR, "ERROR: DDR2_bank_mon: err_wr_dqs_not_asserted_when_wr_data_ready\n", `SEVERITY, `CATEGORY) |
| 3712 | (!(areset), ck, !(err_wr_dqs_not_asserted_when_wr_data_ready), `START, `STOP ); */ |
| 3713 | `endif |
| 3714 | |
| 3715 | end |
| 3716 | `endif |
| 3717 | `endif /*}}}*/ |
| 3718 | |
| 3719 | endmodule // ddr_bank /*}}}*/ |
| 3720 | /*}}}*/ |