| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lsu_mon.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define LD 5'h0 |
| 36 | `define ST 5'h1 |
| 37 | `define FP 5'h2 |
| 38 | `define PREF 5'h3 |
| 39 | `define SWAP 5'h4 |
| 40 | `define CASA 5'h5 |
| 41 | `define LDSTUB 5'h6 |
| 42 | `define FLUSH 5'h7 |
| 43 | `define MEMBAR 5'h8 |
| 44 | `define LDD 5'h9 |
| 45 | `define QLD 5'ha |
| 46 | `define STD 5'hb |
| 47 | `define BLKLD 5'hc |
| 48 | `define BLKST 5'hd |
| 49 | `define ASR_RD_WR 5'he |
| 50 | `define PR_RD_WR 5'hf |
| 51 | `define HPR_RD_WR 5'h10 |
| 52 | `define FSR_RD_WR 5'h11 |
| 53 | |
| 54 | `define USER 2'b00 |
| 55 | `define PRIV 2'b01 |
| 56 | `define HPRIV 2'b10 |
| 57 | |
| 58 | `define LOCAL 1'b0 |
| 59 | `define FAST 1'b1 |
| 60 | |
| 61 | `define ASI_AIU_BIS_QUAD_LDD_P 8'h22 |
| 62 | `define ASI_AIU_BIS_QUAD_LDD_S 8'h23 |
| 63 | `define ASI_NUCLEUS_BIS_QUAD_LDD 8'h27 |
| 64 | `define ASI_AIU_BIS_QUAD_LDD_P_LITTLE 8'h2A |
| 65 | `define ASI_AIU_BIS_QUAD_LDD_S_LITTLE 8'h2B |
| 66 | `define ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE 8'h2F |
| 67 | `define ASI_BIS_QUAD_LDD_P 8'hE2 |
| 68 | `define ASI_BIS_QUAD_LDD_S 8'hE3 |
| 69 | `define ASI_BIS_QUAD_LDD_P_LITTLE 8'hEA |
| 70 | `define ASI_BIS_QUAD_LDD_S_LITTLE 8'hEB |
| 71 | `define ASI_QUAD_LDD 8'h24 |
| 72 | `define ASI_QUAD_LDD_REAL 8'h26 |
| 73 | `define ASI_QUAD_LDD_L 8'h2C |
| 74 | `define ASI_QUAD_LDD_REAL_L 8'h2E |
| 75 | |
| 76 | `define ASI_BLK_AIUP 8'h16 |
| 77 | `define ASI_BLK_AIUS 8'h17 |
| 78 | `define ASI_BLK_AIUPL 8'h1e |
| 79 | `define ASI_BLK_AIUSL 8'h1f |
| 80 | `define ASI_BLK_P 8'hF0 |
| 81 | `define ASI_BLK_S 8'hF1 |
| 82 | `define ASI_BLK_PL 8'hF8 |
| 83 | `define ASI_BLK_SL 8'hF9 |
| 84 | `define ASI_BLK_COMMIT_P 8'hE0 |
| 85 | `define ASI_BLK_COMMIT_S 8'hE1 |
| 86 | |
| 87 | `define PCX_VALID 129 |
| 88 | `define PCX_RQTYP 128:124 |
| 89 | `define PCX_NC 123 |
| 90 | `define PCX_CPU_ID 122:120 |
| 91 | `define PCX_THR_ID 119:117 |
| 92 | `define PCX_INV 116 |
| 93 | `define PCX_PF 115 |
| 94 | `define PCX_BST 115 |
| 95 | `define PCX_BIS 114 |
| 96 | `define PCX_ADDR 103:64 |
| 97 | `define PCX_DATA 63:0 |
| 98 | |
| 99 | `define PCX_LOAD 5'b0 |
| 100 | `define PCX_STORE 5'h1 |
| 101 | `define PCX_CAS1 5'h2 |
| 102 | `define PCX_CAS2 5'h3 |
| 103 | `define PCX_SWAP_LDSTUB 5'h7 |
| 104 | |
| 105 | `define CPX_VALID 145 |
| 106 | `define CPX_RTNTYP 144:141 |
| 107 | `define CPX_ERR 139:138 |
| 108 | `define CPX_NC 137 |
| 109 | `define CPX_THR_ID 136:134 |
| 110 | `define CPX_ATM 129 |
| 111 | `define CPX_PF 128 |
| 112 | `define CPX_LSB_BITS 63:0 |
| 113 | `define CPX_INVAL_VEC 95:64 |
| 114 | `define CPX_BIS 125 |
| 115 | |
| 116 | `define INST_VA 47:0 |
| 117 | `define MEMOP_VA 95:48 |
| 118 | `define INST 127:96 |
| 119 | `define MEMOP_PA 167:128 |
| 120 | `define LSU_MON_INST 188:168 |
| 121 | `define L2_ISS 192:189 |
| 122 | `define L2_RESP 196:193 |
| 123 | `define L2_ST_ISS 189 |
| 124 | `define L2_ACK 190 |
| 125 | `define RMO 191 |
| 126 | `define ST_SQUASH 192 |
| 127 | `define ST_PRIV 194:193 |
| 128 | `define ASI_ST_ISS 195 |
| 129 | `define INST_ASI 204:197 |
| 130 | `define L2_ERR0 206:205 |
| 131 | `define L2_ERR1 208:207 |
| 132 | `define L2_ERR2 210:209 |
| 133 | `define L2_ERR3 212:211 |
| 134 | |
| 135 | `define TLB_MISS_Pend_Width 127:0 |
| 136 | `define LD_Pend_Width 212:0 |
| 137 | `define STB_Pend_Width 204:0 |
| 138 | `define LAST_INST_Pend_Width 135:0 |
| 139 | `define NE 2'b0 |
| 140 | `define CE 2'b01 |
| 141 | `define UE 2'b10 |
| 142 | `define ND 2'b11 |
| 143 | |
| 144 | `ifdef CORE_0 |
| 145 | |
| 146 | module lsu_mon_c0; |
| 147 | `ifndef GATESIM |
| 148 | |
| 149 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 150 | `ifndef NO_MONITORS |
| 151 | |
| 152 | reg imm_asi_vld_e; |
| 153 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 154 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 155 | reg [1:0] exu_ecc_b; |
| 156 | reg [1:0] exu_lsu_va_error_b; |
| 157 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 158 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 159 | reg [31:0] inst_e, inst_m, inst_b; |
| 160 | reg [47:0] vaddr_m, vaddr_b; |
| 161 | reg [63:0] int_st_data_m, int_st_data_b; |
| 162 | reg [63:0] fp_st_sata_fx2; |
| 163 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 164 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 165 | |
| 166 | reg [7:0] ld_valid; |
| 167 | reg [7:0] tlb_valid; |
| 168 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 169 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 170 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 171 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 172 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 173 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 174 | //the L2c. |
| 175 | reg [63:0] stb_valid; |
| 176 | reg [`STB_Pend_Width] stb[63:0]; |
| 177 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 178 | |
| 179 | reg [7:0] pf_cnt[7:0]; |
| 180 | reg [7:0] dcache_inv_cnt[7:0]; |
| 181 | reg [7:0] st_rmo_cnt[7:0]; |
| 182 | |
| 183 | reg [55:0] print_inst; |
| 184 | |
| 185 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 186 | |
| 187 | reg [7:0] lsu_bst_active; |
| 188 | reg store_alloc; |
| 189 | reg [3:0] bst_cnt; |
| 190 | reg [195:0] stb_alloc_data; |
| 191 | reg [195:0] bst_data, bst_inst_data; |
| 192 | reg [2:0] bst_active_thid; |
| 193 | reg bst_fgu_err; |
| 194 | |
| 195 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 196 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 197 | //different types of err occur on blk ld helper returns |
| 198 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 199 | //stored in DFESR |
| 200 | |
| 201 | wire [2:0] core_id = 0; |
| 202 | |
| 203 | integer i; |
| 204 | integer err_cnt; |
| 205 | |
| 206 | reg enabled; |
| 207 | reg reset_in_middle; |
| 208 | reg [7:0] finish_mask; |
| 209 | |
| 210 | initial |
| 211 | begin |
| 212 | enabled = 0; |
| 213 | reset_in_middle = 0; |
| 214 | ld_valid = 8'b0; |
| 215 | lsu_inst_e = 0; |
| 216 | tlb_valid = 8'b0; |
| 217 | for (i = 0; i < 8; i = i+1) |
| 218 | begin |
| 219 | pf_cnt[i] = 0; |
| 220 | dcache_inv_cnt[i] = 0; |
| 221 | wrptr[i] = 0; |
| 222 | rdptr[i] = 0; |
| 223 | iss_ptr[i] = 0; |
| 224 | ret_ptr[i] = 0; |
| 225 | st_rmo_cnt[i] = 0; |
| 226 | is_blkld[i] = 1'b0; |
| 227 | st_priv[i] = 2'b0; |
| 228 | l2_blk_ld_errtype[i] = 2'b0; |
| 229 | end |
| 230 | lsu_bst_active = 8'b0; |
| 231 | store_alloc = 1'b0; |
| 232 | bst_cnt = 4'b0; |
| 233 | stb_valid = 64'b0; |
| 234 | |
| 235 | // avoid time zero ugliness. jp |
| 236 | //@(posedge `SPC0.l2clk); |
| 237 | //@(negedge `SPC0.l2clk); |
| 238 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 239 | |
| 240 | case (core_id) |
| 241 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 242 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 243 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 244 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 245 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 246 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 247 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 248 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 249 | endcase |
| 250 | end |
| 251 | |
| 252 | always @ (`TOP.in_reset) |
| 253 | begin |
| 254 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 255 | begin |
| 256 | enabled = 1'b1; |
| 257 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 258 | end |
| 259 | |
| 260 | |
| 261 | if (`TOP.in_reset & enabled) |
| 262 | begin |
| 263 | reset_in_middle = 1'b1; |
| 264 | enabled = 1'b0; |
| 265 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 266 | end |
| 267 | end |
| 268 | |
| 269 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 270 | begin //{ |
| 271 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 272 | begin //{ |
| 273 | for (i = 0; i < 8; i=i+1) |
| 274 | begin |
| 275 | if (ld_valid[i]) |
| 276 | begin |
| 277 | DispPendReq(i); |
| 278 | end |
| 279 | end |
| 280 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 281 | end //} |
| 282 | if (|stb_valid[63:0]) |
| 283 | begin //{ |
| 284 | err_cnt = 0; |
| 285 | for (i = 0; i < 64; i=i+1) |
| 286 | begin |
| 287 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 288 | begin |
| 289 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 290 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 291 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 292 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 293 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 294 | //of simualation. |
| 295 | if (~is_squash_bit_set(i[5:0])) |
| 296 | begin |
| 297 | err_cnt = err_cnt + 1; |
| 298 | Disp_STB_entry(i[5:3],i[2:0]); |
| 299 | end |
| 300 | end |
| 301 | end |
| 302 | if (err_cnt) |
| 303 | begin |
| 304 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 305 | end |
| 306 | end //} |
| 307 | err_cnt = 0; |
| 308 | for (i = 0; i < 8; i=i+1) |
| 309 | begin //{ |
| 310 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 311 | begin |
| 312 | err_cnt = 1; |
| 313 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 314 | end |
| 315 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 316 | begin |
| 317 | err_cnt = 1; |
| 318 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 319 | end |
| 320 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 321 | begin |
| 322 | err_cnt = 1; |
| 323 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 324 | end |
| 325 | end //} |
| 326 | if (err_cnt) |
| 327 | begin |
| 328 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 329 | end |
| 330 | end //} |
| 331 | |
| 332 | function is_squash_bit_set; |
| 333 | input [5:0] index; |
| 334 | reg [204:0] tmp; |
| 335 | begin |
| 336 | tmp = stb[index]; |
| 337 | if (tmp[`ST_SQUASH]) |
| 338 | is_squash_bit_set = 1'b1; |
| 339 | else |
| 340 | is_squash_bit_set = 1'b0; |
| 341 | end |
| 342 | endfunction |
| 343 | |
| 344 | |
| 345 | always @ (negedge (`SPC0.l2clk & enabled)) |
| 346 | begin //{ |
| 347 | |
| 348 | asi_e = `SPC0.lsu.dcc.dcc_asi_e[7:0]; |
| 349 | |
| 350 | lsu_inst_e[`LD] <= `SPC0.dec_ld_inst_e; |
| 351 | lsu_inst_e[`ST] <= `SPC0.dec_st_inst_e; |
| 352 | lsu_inst_e[`FP] <= `SPC0.dec_fpldst_inst_e; |
| 353 | lsu_inst_e[`PREF] <= `SPC0.dec_pref_inst_e; |
| 354 | lsu_inst_e[`SWAP] <= `SPC0.dec_swap_inst_e; |
| 355 | lsu_inst_e[`CASA] <= `SPC0.dec_casa_inst_e; |
| 356 | lsu_inst_e[`LDSTUB] <= `SPC0.dec_ldstub_inst_e; |
| 357 | lsu_inst_e[`FLUSH] <= `SPC0.dec_flush_inst_e; |
| 358 | lsu_inst_e[`MEMBAR] <= `SPC0.dec_memstbar_inst_e; |
| 359 | lsu_inst_e[`LDD] <= `SPC0.dec_ld_inst_e & `SPC0.dec_ldst_dbl_e & ~`SPC0.dec_fpldst_inst_e; |
| 360 | lsu_inst_e[`STD] <= `SPC0.dec_st_inst_e & `SPC0.dec_ldst_dbl_e & ~`SPC0.lsu.dec_fpldst_inst_e; |
| 361 | |
| 362 | lsu_inst_e[`BLKLD] <= `SPC0.dec_ld_inst_e & `SPC0.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 363 | lsu_inst_e[`BLKST] <= `SPC0.dec_st_inst_e & `SPC0.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 364 | lsu_inst_e[`QLD] <= `SPC0.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 365 | lsu_inst_e[`ASR_RD_WR] <= `SPC0.dec_sr_inst_e & (`SPC0.dec_ld_inst_e | `SPC0.dec_st_inst_e); |
| 366 | lsu_inst_e[`PR_RD_WR] <= `SPC0.dec_pr_inst_e & (`SPC0.dec_ld_inst_e | `SPC0.dec_st_inst_e); |
| 367 | lsu_inst_e[`HPR_RD_WR] <= `SPC0.dec_hpr_inst_e & (`SPC0.dec_ld_inst_e | `SPC0.dec_st_inst_e); |
| 368 | lsu_inst_e[`FSR_RD_WR] <= `SPC0.dec_fsr_ldst_e & (`SPC0.dec_ld_inst_e | `SPC0.dec_st_inst_e); |
| 369 | end //} |
| 370 | |
| 371 | always @ (posedge (`SPC0.l2clk & enabled)) |
| 372 | begin //{ |
| 373 | dec_tg0_inst_d <= `SPC0.dec.ded0.decode_mux[31:0]; |
| 374 | dec_tg1_inst_d <= `SPC0.dec.ded1.decode_mux[31:0]; |
| 375 | imm_asi_vld_e <= `SPC0.lsu.dec_imm_asi_vld_d; |
| 376 | |
| 377 | imm_asi_e <= `SPC0.lsu.dec_imm_asi_d; |
| 378 | dec_altspace_e <= `SPC0.dec_altspace_d; |
| 379 | dec_altspace_m <= dec_altspace_e; |
| 380 | dec_altspace_b <= dec_altspace_m; |
| 381 | |
| 382 | exu_ecc_b <= `SPC0.exu_ecc_m; |
| 383 | exu_lsu_va_error_b <= `SPC0.exu_lsu_va_error_m; |
| 384 | |
| 385 | dec_lsu_tid_e <= `SPC0.dec_lsu_tg_d ? {1'b1, `SPC0.dec_lsu_tid1_d} : {1'b0, `SPC0.dec_lsu_tid0_d}; |
| 386 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 387 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 388 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 389 | |
| 390 | inst_pc_e <= `SPC0.dec_lsu_tg_d ? {`SPC0.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC0.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 391 | inst_pc_m <= inst_pc_e; |
| 392 | inst_pc_b <= inst_pc_m; |
| 393 | inst_pc_w <= inst_pc_b; |
| 394 | |
| 395 | inst_e <= `SPC0.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 396 | inst_m <= inst_e; |
| 397 | inst_b <= inst_m; |
| 398 | |
| 399 | vaddr_m <= `SPC0.exu_lsu_address_e; |
| 400 | vaddr_b <= vaddr_m; |
| 401 | |
| 402 | int_st_data_m <= `SPC0.exu_lsu_store_data_e; |
| 403 | int_st_data_b <= int_st_data_m; |
| 404 | fp_st_sata_fx2 <= `SPC0.fgu_lsu_fst_data_fx1; |
| 405 | |
| 406 | mmu_dtlb_reload_d1 <= `SPC0.mmu_dtlb_reload; |
| 407 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 408 | |
| 409 | //pcx_thid_d1 <= `SPC0.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 410 | lsu_inst_m <= lsu_inst_e; |
| 411 | lsu_inst_b <= lsu_inst_m; |
| 412 | |
| 413 | asi_m <= asi_e; |
| 414 | asi_b <= asi_m; |
| 415 | end //} |
| 416 | |
| 417 | function Is_blk_asi; |
| 418 | input [7:0] asi; |
| 419 | begin |
| 420 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 421 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 422 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 423 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 424 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 425 | end |
| 426 | endfunction |
| 427 | |
| 428 | function Is_qld_asi; |
| 429 | input [7:0] asi; |
| 430 | begin |
| 431 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 432 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 433 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 434 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 435 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 436 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 437 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 438 | end |
| 439 | endfunction |
| 440 | |
| 441 | function Is_bis_asi; |
| 442 | input [7:0] asi; |
| 443 | begin |
| 444 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 445 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 446 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 447 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 448 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 449 | end |
| 450 | endfunction |
| 451 | |
| 452 | always @ (negedge (`SPC0.l2clk & enabled)) |
| 453 | begin //{ |
| 454 | Chk_store; |
| 455 | store_alloc = 1'b0; |
| 456 | if (lsu_inst_m != 0) |
| 457 | begin |
| 458 | if (`SPC0.dec_flush_lm) |
| 459 | begin |
| 460 | lsu_inst_m <= 0; |
| 461 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 462 | end |
| 463 | end |
| 464 | |
| 465 | if (lsu_inst_b != 0) |
| 466 | begin //{ |
| 467 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 468 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 469 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 470 | else print_inst = ""; |
| 471 | |
| 472 | if (`SPC0.dec_flush_lb) |
| 473 | begin |
| 474 | lsu_inst_b <= 0; |
| 475 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 476 | end |
| 477 | else if (`SPC0.tlu_flush_lsu_b) |
| 478 | begin |
| 479 | lsu_inst_b <= 0; |
| 480 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 481 | end |
| 482 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 483 | //casa shd be killed. |
| 484 | //This function will also chk for errors on 2nd cycle. |
| 485 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 486 | begin |
| 487 | lsu_inst_b <= 0; |
| 488 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 489 | end |
| 490 | else if ((`SPC0.fgu_cecc_fx2 || `SPC0.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 491 | begin |
| 492 | lsu_inst_b <= 0; |
| 493 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 494 | end |
| 495 | else if (IsExc(core_id)) |
| 496 | lsu_inst_b <= 0; |
| 497 | else if (!`SPC0.lsu_tlb_miss_b_) |
| 498 | begin |
| 499 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 500 | //Insert_tlb_miss_info; |
| 501 | end |
| 502 | else |
| 503 | begin //{ |
| 504 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 505 | //an exception tlu anyway tells the front end to flush itself there is |
| 506 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 507 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 508 | //handles it when it is reissued by the front end. |
| 509 | |
| 510 | if (`SPC0.lsu_tlb_bypass_b) |
| 511 | begin |
| 512 | if (`SPC0.lsu_sync != 8'b0) |
| 513 | begin |
| 514 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 515 | end |
| 516 | else |
| 517 | begin |
| 518 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 519 | end |
| 520 | end |
| 521 | else |
| 522 | begin |
| 523 | if (`SPC0.lsu_sync != 8'b0) |
| 524 | begin |
| 525 | if (lsu_inst_b[`ST]) |
| 526 | begin |
| 527 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 528 | end |
| 529 | else |
| 530 | begin |
| 531 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 532 | end |
| 533 | end |
| 534 | else |
| 535 | begin |
| 536 | if (lsu_inst_b[`ST]) |
| 537 | begin |
| 538 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 539 | end |
| 540 | else |
| 541 | begin |
| 542 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 543 | end |
| 544 | end |
| 545 | end |
| 546 | |
| 547 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 548 | begin //{ |
| 549 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC0.lsu.stb_cam_hit) |
| 550 | begin |
| 551 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 552 | end |
| 553 | end //} |
| 554 | |
| 555 | if (lsu_inst_b[`LD]) |
| 556 | Insert_ld_miss_info; |
| 557 | |
| 558 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 559 | begin |
| 560 | Make_STB_data; |
| 561 | store_alloc = 1'b1; |
| 562 | end |
| 563 | Insert_in_last_inst_array; |
| 564 | |
| 565 | if (`SPC0.lsu_trap_flush[7:0]) |
| 566 | begin |
| 567 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC0.lsu_trap_flush[7:0])); |
| 568 | end |
| 569 | end //} |
| 570 | end //} |
| 571 | end //} |
| 572 | |
| 573 | //STB ue testing: |
| 574 | //This is how we test squashing of stores by LSU_mon: |
| 575 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 576 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 577 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 578 | //The squashed stores are deallocated when either a block_store_kill is |
| 579 | //asserted or dealloc signals are asserted by the LSU. |
| 580 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 581 | //all the pending stores in the IFU. It means the when block_store_kill |
| 582 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 583 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 584 | //the sbdiou signal to TLU. |
| 585 | |
| 586 | |
| 587 | always @ (negedge (`SPC0.l2clk & enabled)) |
| 588 | begin |
| 589 | if (`SPC0.lsu_l15_valid & `SPC0.lsu.spc_pcx_data_pa[129]) |
| 590 | Chk_pcx_req_pkt(`SPC0.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 591 | if ((`SPC0.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC0.lsu_rngl_cdbus[59]) |
| 592 | Chk_st_on_ASI_ring(`LOCAL); |
| 593 | |
| 594 | if ((`SPC0.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC0.lsu_rngf_cdbus[59]) |
| 595 | Chk_st_on_ASI_ring(`FAST); |
| 596 | |
| 597 | //if (`SPC0.l15_lsu_valid) |
| 598 | //Chk_cpx_response_pkt({`SPC0.l15_lsu_valid, `SPC0.l15_lsu_cpkt[17:13],`SPC0.l15_lsu_cpkt[11:0],`SPC0.l15_spc_data1[127:0]}); |
| 599 | |
| 600 | if (`SPC0.cpx_spc_data_cx[145]) |
| 601 | Chk_cpx_response_pkt(`SPC0.cpx_spc_data_cx); |
| 602 | |
| 603 | if (`SPC0.lsu_complete[7:0] != 8'b0) |
| 604 | begin |
| 605 | if (`SPC0.lsu_complete[0]) Chk_ld_complete(0); |
| 606 | if (`SPC0.lsu_complete[1]) Chk_ld_complete(1); |
| 607 | if (`SPC0.lsu_complete[2]) Chk_ld_complete(2); |
| 608 | if (`SPC0.lsu_complete[3]) Chk_ld_complete(3); |
| 609 | if (`SPC0.lsu_complete[4]) Chk_ld_complete(4); |
| 610 | if (`SPC0.lsu_complete[5]) Chk_ld_complete(5); |
| 611 | if (`SPC0.lsu_complete[6]) Chk_ld_complete(6); |
| 612 | if (`SPC0.lsu_complete[7]) Chk_ld_complete(7); |
| 613 | end |
| 614 | |
| 615 | if (`SPC0.lsu_block_store_kill[7:0] != 8'b0) |
| 616 | begin |
| 617 | if (`SPC0.lsu_block_store_kill[0]) Squash_STB(0); |
| 618 | if (`SPC0.lsu_block_store_kill[1]) Squash_STB(1); |
| 619 | if (`SPC0.lsu_block_store_kill[2]) Squash_STB(2); |
| 620 | if (`SPC0.lsu_block_store_kill[3]) Squash_STB(3); |
| 621 | if (`SPC0.lsu_block_store_kill[4]) Squash_STB(4); |
| 622 | if (`SPC0.lsu_block_store_kill[5]) Squash_STB(5); |
| 623 | if (`SPC0.lsu_block_store_kill[6]) Squash_STB(6); |
| 624 | if (`SPC0.lsu_block_store_kill[7]) Squash_STB(7); |
| 625 | end |
| 626 | |
| 627 | if (`SPC0.lsu_stb_dealloc[7:0] != 8'b0) |
| 628 | begin |
| 629 | if (`SPC0.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 630 | if (`SPC0.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 631 | if (`SPC0.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 632 | if (`SPC0.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 633 | if (`SPC0.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 634 | if (`SPC0.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 635 | if (`SPC0.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 636 | if (`SPC0.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 637 | end |
| 638 | |
| 639 | if (`SPC0.lsu_block_store_stall) |
| 640 | Chk_block_store; |
| 641 | |
| 642 | if (`SPC0.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 643 | Set_block_store_parameters; |
| 644 | |
| 645 | if (`SPC0.lsu_sbdiou_err_g || `SPC0.lsu_sbapp_err_g) |
| 646 | Squash_store; |
| 647 | |
| 648 | if (`SPC0.lsu_stb_flush_g) |
| 649 | st_priv[`SPC0.lsu_stberr_tid_g] = get_priv_on_flush(`SPC0.lsu_stberr_tid_g); |
| 650 | end |
| 651 | |
| 652 | function [1:0] get_priv_on_flush; |
| 653 | input [2:0] tid; |
| 654 | reg [2:0] sq_index; |
| 655 | reg [204:0] tmp; |
| 656 | |
| 657 | begin |
| 658 | sq_index = `SPC0.lsu_stberr_index_g; |
| 659 | tmp = stb[{tid, sq_index}]; |
| 660 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 661 | end |
| 662 | endfunction |
| 663 | |
| 664 | task Chk_block_store; |
| 665 | reg [20:0] inst; |
| 666 | reg [2:0] thid; |
| 667 | begin |
| 668 | thid = `SPC0.lsu_block_store_tid; |
| 669 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 670 | inst = bst_inst_data[`LSU_MON_INST]; |
| 671 | |
| 672 | if (~inst[`BLKST]) |
| 673 | begin |
| 674 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 675 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 676 | end |
| 677 | end |
| 678 | endtask |
| 679 | |
| 680 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 681 | //the 8 stb entries from the previous blk store. |
| 682 | |
| 683 | task Set_block_store_parameters; |
| 684 | reg [2:0] thid; |
| 685 | begin |
| 686 | |
| 687 | thid = decode_tid(`SPC0.lsu.lsu_block_store_alloc[7:0]); |
| 688 | if (lsu_bst_active[thid]) |
| 689 | begin |
| 690 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 691 | end |
| 692 | else |
| 693 | begin |
| 694 | lsu_bst_active[thid] = 1'b1; |
| 695 | bst_active_thid = thid; |
| 696 | if (`SPC0.lsu.fgu_fst_ecc_error_fx2) |
| 697 | bst_fgu_err = 1'b1; |
| 698 | else |
| 699 | bst_fgu_err = 1'b0; |
| 700 | end |
| 701 | end |
| 702 | endtask |
| 703 | |
| 704 | task Squash_store; |
| 705 | reg [2:0] thid; |
| 706 | reg [2:0] sq_index; |
| 707 | reg [2:0] i; |
| 708 | reg [204:0] tmp; |
| 709 | reg [3:0] squash_cnt; |
| 710 | reg [1:0] priv; |
| 711 | |
| 712 | begin |
| 713 | thid = `SPC0.lsu_stberr_tid_g; |
| 714 | sq_index = `SPC0.lsu_stberr_index_g; |
| 715 | priv = `SPC0.lsu_stberr_priv_g; |
| 716 | tmp = stb[{thid, sq_index}]; |
| 717 | squash_cnt = 0; |
| 718 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 719 | |
| 720 | st_priv[thid] = tmp[`ST_PRIV]; |
| 721 | |
| 722 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 723 | //In that case iss_ptr won't be equal to sbdiou index. |
| 724 | //if (sq_index != iss_ptr[thid]) |
| 725 | //begin |
| 726 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 727 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 728 | //end |
| 729 | |
| 730 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 731 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 732 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 733 | //removing this chk. |
| 734 | |
| 735 | //if (tmp[`L2_ST_ISS]) |
| 736 | //begin |
| 737 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 738 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 739 | //end |
| 740 | |
| 741 | if (iss_ptr[thid] == wrptr[thid]) |
| 742 | begin |
| 743 | if (stb_valid[{thid, wrptr[thid]}]) |
| 744 | squash_cnt = 8; |
| 745 | else |
| 746 | begin |
| 747 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 748 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 749 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 750 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 751 | end |
| 752 | end |
| 753 | else |
| 754 | begin |
| 755 | if (iss_ptr[thid] < wrptr[thid]) |
| 756 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 757 | else if (iss_ptr[thid] > wrptr[thid]) |
| 758 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 759 | end |
| 760 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 761 | |
| 762 | i = iss_ptr[thid]; |
| 763 | |
| 764 | while (squash_cnt) |
| 765 | begin |
| 766 | tmp = stb[{thid, i}]; |
| 767 | tmp[`ST_SQUASH] = 1'b1; |
| 768 | if (priv < tmp[`ST_PRIV]) |
| 769 | begin |
| 770 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 771 | priv = tmp[`ST_PRIV]; |
| 772 | end |
| 773 | |
| 774 | stb[{thid, i}] = tmp; |
| 775 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 776 | |
| 777 | i = i + 1; |
| 778 | squash_cnt = squash_cnt - 1'b1; |
| 779 | end |
| 780 | end |
| 781 | endtask |
| 782 | |
| 783 | function [2:0] decode_tid; |
| 784 | input [7:0] thid_encode; |
| 785 | begin |
| 786 | case (thid_encode) |
| 787 | 8'h1: decode_tid = 3'b0; |
| 788 | 8'h2: decode_tid = 3'h1; |
| 789 | 8'h4: decode_tid = 3'h2; |
| 790 | 8'h8: decode_tid = 3'h3; |
| 791 | 8'h10: decode_tid = 3'h4; |
| 792 | 8'h20: decode_tid = 3'h5; |
| 793 | 8'h40: decode_tid = 3'h6; |
| 794 | 8'h80: decode_tid = 3'h7; |
| 795 | default: |
| 796 | begin |
| 797 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 798 | end |
| 799 | endcase |
| 800 | end |
| 801 | endfunction |
| 802 | |
| 803 | task Chk_ld_complete; |
| 804 | input [2:0] thid; |
| 805 | reg [`LD_Pend_Width] tmp; |
| 806 | begin |
| 807 | tmp = ld_pend_array[thid]; |
| 808 | |
| 809 | if (ld_valid[thid]) |
| 810 | begin |
| 811 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 812 | begin |
| 813 | DispPendReq(thid); |
| 814 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 815 | end |
| 816 | ld_valid[thid] = 1'b0; |
| 817 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 818 | end |
| 819 | |
| 820 | tmp = last_inst_array[thid]; |
| 821 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 822 | end |
| 823 | endtask |
| 824 | |
| 825 | task Chk_pcx_req_pkt; |
| 826 | input [129:0] pcx_pkt; |
| 827 | reg [2:0] thid; |
| 828 | reg [`LD_Pend_Width] tmp, tmp1; |
| 829 | reg [15:0] inst; |
| 830 | reg [11*8:0] req; |
| 831 | reg [39:0] addr; |
| 832 | begin |
| 833 | thid = pcx_pkt[`PCX_THR_ID]; |
| 834 | tmp = ld_pend_array[thid]; |
| 835 | inst = tmp[`LSU_MON_INST]; |
| 836 | req = DispPCXReq(pcx_pkt); |
| 837 | addr = pcx_pkt[`PCX_ADDR]; |
| 838 | |
| 839 | |
| 840 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 841 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 842 | |
| 843 | |
| 844 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 845 | begin |
| 846 | if (~ld_valid[thid]) |
| 847 | begin |
| 848 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 849 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 850 | end |
| 851 | if (~inst[`BLKLD]) |
| 852 | begin |
| 853 | if (tmp[`MEMOP_PA] != addr) |
| 854 | begin |
| 855 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 856 | begin |
| 857 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 858 | end |
| 859 | else |
| 860 | begin |
| 861 | DispPendReq(thid); |
| 862 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 863 | end |
| 864 | end |
| 865 | end |
| 866 | end |
| 867 | |
| 868 | case (pcx_pkt[`PCX_RQTYP]) |
| 869 | `PCX_LOAD: |
| 870 | begin |
| 871 | if (pcx_pkt[`PCX_PF]) |
| 872 | begin |
| 873 | if (~inst[`PREF]) |
| 874 | begin |
| 875 | DispPendReq(thid); |
| 876 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 877 | end |
| 878 | if (pcx_pkt[`PCX_INV]) |
| 879 | begin |
| 880 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 881 | end |
| 882 | else |
| 883 | begin |
| 884 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 885 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 886 | end |
| 887 | tmp[`L2_ISS] = 4'hF; |
| 888 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 889 | ld_pend_array[thid] = tmp; |
| 890 | end |
| 891 | else |
| 892 | begin |
| 893 | if (pcx_pkt[`PCX_INV]) |
| 894 | begin |
| 895 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 896 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 897 | end |
| 898 | else |
| 899 | begin |
| 900 | Chk_req_load(pcx_pkt); |
| 901 | end |
| 902 | end |
| 903 | end |
| 904 | `PCX_CAS1, `PCX_CAS2: |
| 905 | begin |
| 906 | if (~inst[`CASA]) |
| 907 | begin |
| 908 | DispPendReq(thid); |
| 909 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 910 | end |
| 911 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 912 | begin |
| 913 | tmp[`L2_ISS] = 4'hE; |
| 914 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 915 | ld_pend_array[thid] = tmp; |
| 916 | end |
| 917 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 918 | begin |
| 919 | tmp[`L2_ISS] = 4'hF; |
| 920 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 921 | ld_pend_array[thid] = tmp; |
| 922 | chk_store_issue_to_pcx(pcx_pkt); |
| 923 | end |
| 924 | |
| 925 | end |
| 926 | `PCX_SWAP_LDSTUB: |
| 927 | begin |
| 928 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 929 | begin |
| 930 | DispPendReq(thid); |
| 931 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 932 | end |
| 933 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 934 | tmp[`L2_ISS] = 4'hF; |
| 935 | ld_pend_array[thid] = tmp; |
| 936 | |
| 937 | chk_store_issue_to_pcx(pcx_pkt); |
| 938 | end |
| 939 | |
| 940 | `PCX_STORE: |
| 941 | begin |
| 942 | chk_store_issue_to_pcx(pcx_pkt); |
| 943 | end |
| 944 | |
| 945 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 946 | endcase |
| 947 | end |
| 948 | endtask |
| 949 | |
| 950 | task Chk_cpx_response_pkt; |
| 951 | input [145:0] cpx_pkt; |
| 952 | reg [2:0] thid; |
| 953 | begin |
| 954 | thid = cpx_pkt[`CPX_THR_ID]; |
| 955 | |
| 956 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 957 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 958 | begin |
| 959 | chk_ccx_ld_response(cpx_pkt); |
| 960 | end |
| 961 | |
| 962 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 963 | begin |
| 964 | if (pf_cnt[thid] == 8'b0) |
| 965 | begin |
| 966 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 967 | end |
| 968 | else |
| 969 | begin |
| 970 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 971 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 972 | end |
| 973 | end |
| 974 | |
| 975 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 976 | chk_ccx_ld_response(cpx_pkt); |
| 977 | |
| 978 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 979 | begin |
| 980 | if (cpx_pkt[123]) //D pkt |
| 981 | begin //{ |
| 982 | if (cpx_pkt[120:118] != core_id) |
| 983 | begin |
| 984 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 985 | end |
| 986 | if (dcache_inv_cnt[thid] == 8'b0) |
| 987 | begin |
| 988 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 989 | end |
| 990 | else |
| 991 | begin |
| 992 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 993 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 994 | end |
| 995 | end //} |
| 996 | else if (cpx_pkt[124]) //I pkt |
| 997 | begin |
| 998 | if (cpx_pkt[120:118] != core_id) |
| 999 | begin |
| 1000 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 1001 | end |
| 1002 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 1003 | end |
| 1004 | else if (cpx_pkt[124:123] == 2'b0) |
| 1005 | begin |
| 1006 | if (cpx_pkt[120:118] == core_id) |
| 1007 | begin |
| 1008 | chk_ccx_st_response(cpx_pkt); |
| 1009 | end |
| 1010 | else |
| 1011 | begin |
| 1012 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 1013 | end |
| 1014 | end |
| 1015 | end |
| 1016 | |
| 1017 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 1018 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 1019 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 1020 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 1021 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 1022 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 1023 | |
| 1024 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 1025 | begin |
| 1026 | chk_ccx_atm_response(cpx_pkt); |
| 1027 | end |
| 1028 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 1029 | begin |
| 1030 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 1031 | begin |
| 1032 | chk_ccx_atm_response(cpx_pkt); |
| 1033 | chk_ccx_st_response(cpx_pkt); |
| 1034 | end |
| 1035 | end |
| 1036 | |
| 1037 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 1038 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 1039 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 1040 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 1041 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 1042 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 1043 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 1044 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 1045 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 1046 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 1047 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 1048 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 1049 | |
| 1050 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 1051 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 1052 | |
| 1053 | default: |
| 1054 | begin |
| 1055 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 1056 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 1057 | |
| 1058 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 1059 | end |
| 1060 | |
| 1061 | endcase |
| 1062 | end |
| 1063 | endtask |
| 1064 | |
| 1065 | task chk_ccx_ld_response; |
| 1066 | input [145:0] cpx_pkt; |
| 1067 | reg [2:0] thid; |
| 1068 | reg [20:0] inst; |
| 1069 | reg [39:0] cpx_pa, inst_pa; |
| 1070 | reg [`LD_Pend_Width] tmp; |
| 1071 | reg [3:0] pkt_type; |
| 1072 | begin |
| 1073 | thid = cpx_pkt[`CPX_THR_ID]; |
| 1074 | tmp = ld_pend_array[thid]; |
| 1075 | inst = tmp[`LSU_MON_INST]; |
| 1076 | inst_pa = tmp[`MEMOP_PA]; |
| 1077 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 1078 | |
| 1079 | if (ld_valid[thid]) |
| 1080 | begin |
| 1081 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 1082 | /* |
| 1083 | if (inst_pa[39] != pkt_type[3]) |
| 1084 | begin |
| 1085 | DispPendReq(thid); |
| 1086 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 1087 | end |
| 1088 | */ |
| 1089 | |
| 1090 | if (inst[`BLKLD]) |
| 1091 | begin |
| 1092 | if (tmp[`L2_RESP] == 4'h0) |
| 1093 | begin |
| 1094 | tmp[`L2_RESP] = 4'h1; |
| 1095 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 1096 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 1097 | begin |
| 1098 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 1099 | end |
| 1100 | |
| 1101 | end |
| 1102 | else if (tmp[`L2_RESP] == 4'h1) |
| 1103 | begin |
| 1104 | tmp[`L2_RESP] = 4'h3; |
| 1105 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 1106 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 1107 | begin |
| 1108 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 1109 | end |
| 1110 | end |
| 1111 | else if (tmp[`L2_RESP] == 4'h3) |
| 1112 | begin |
| 1113 | tmp[`L2_RESP] = 4'h7; |
| 1114 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 1115 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 1116 | begin |
| 1117 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 1118 | end |
| 1119 | end |
| 1120 | else if (tmp[`L2_RESP] == 4'h7) |
| 1121 | begin |
| 1122 | tmp[`L2_RESP] = 4'hF; |
| 1123 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 1124 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 1125 | begin |
| 1126 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 1127 | end |
| 1128 | |
| 1129 | //is_blkld[thid] = 1'b1; |
| 1130 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 1131 | l2_blk_ld_errtype[thid] = `ND; |
| 1132 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 1133 | l2_blk_ld_errtype[thid] = `UE; |
| 1134 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 1135 | l2_blk_ld_errtype[thid] = `CE; |
| 1136 | else |
| 1137 | l2_blk_ld_errtype[thid] = `NE; |
| 1138 | end |
| 1139 | else |
| 1140 | begin |
| 1141 | DispPendReq(thid); |
| 1142 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 1143 | end |
| 1144 | end |
| 1145 | else if (Is_single_pcx_req_ld(inst)) |
| 1146 | begin |
| 1147 | //is_blkld[thid] = 1'b0; |
| 1148 | if (tmp[`L2_RESP] != 4'hE) |
| 1149 | begin |
| 1150 | DispPendReq(thid); |
| 1151 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 1152 | end |
| 1153 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 1154 | tmp[`L2_RESP] = 4'hF; |
| 1155 | end |
| 1156 | else |
| 1157 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 1158 | end |
| 1159 | else |
| 1160 | begin |
| 1161 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 1162 | end |
| 1163 | |
| 1164 | ld_pend_array[thid] = tmp; |
| 1165 | end |
| 1166 | endtask |
| 1167 | |
| 1168 | task chk_ccx_atm_response; |
| 1169 | input [145:0] cpx_pkt; |
| 1170 | reg [2:0] thid; |
| 1171 | reg [20:0] inst; |
| 1172 | reg [39:0] inst_pa; |
| 1173 | reg [`LD_Pend_Width] tmp; |
| 1174 | begin |
| 1175 | thid = cpx_pkt[`CPX_THR_ID]; |
| 1176 | tmp = ld_pend_array[thid]; |
| 1177 | inst = tmp[`LSU_MON_INST]; |
| 1178 | inst_pa = tmp[`MEMOP_PA]; |
| 1179 | |
| 1180 | if (~ld_valid[thid]) |
| 1181 | begin |
| 1182 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 1183 | begin |
| 1184 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 1185 | end |
| 1186 | else |
| 1187 | begin |
| 1188 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 1189 | end |
| 1190 | end |
| 1191 | else |
| 1192 | begin |
| 1193 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 1194 | begin |
| 1195 | DispPendReq(thid); |
| 1196 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 1197 | begin |
| 1198 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 1199 | end |
| 1200 | else |
| 1201 | begin |
| 1202 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 1203 | end |
| 1204 | end |
| 1205 | else |
| 1206 | begin |
| 1207 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 1208 | begin |
| 1209 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 1210 | end |
| 1211 | else |
| 1212 | begin |
| 1213 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 1214 | end |
| 1215 | |
| 1216 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 1217 | begin |
| 1218 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 1219 | else |
| 1220 | begin |
| 1221 | DispPendReq(thid); |
| 1222 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 1223 | end |
| 1224 | end |
| 1225 | else |
| 1226 | begin |
| 1227 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 1228 | else |
| 1229 | begin |
| 1230 | DispPendReq(thid); |
| 1231 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 1232 | end |
| 1233 | end |
| 1234 | end |
| 1235 | end |
| 1236 | ld_pend_array[thid] = tmp; |
| 1237 | end |
| 1238 | endtask |
| 1239 | |
| 1240 | task chk_ccx_st_response; |
| 1241 | input [145:0] cpx_pkt; |
| 1242 | reg [2:0] thid; |
| 1243 | reg [20:0] inst; |
| 1244 | reg [39:0] cpx_pa, inst_pa; |
| 1245 | reg [204:0] tmp; |
| 1246 | reg [3:0] pkt_type; |
| 1247 | begin |
| 1248 | thid = cpx_pkt[`CPX_THR_ID]; |
| 1249 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 1250 | inst = tmp[`LSU_MON_INST]; |
| 1251 | inst_pa = tmp[`MEMOP_PA]; |
| 1252 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 1253 | |
| 1254 | |
| 1255 | //is received. There could be some other store sitting in the STB at that time. |
| 1256 | |
| 1257 | //Chk for squash bit only for non-bis responses. |
| 1258 | |
| 1259 | |
| 1260 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 1261 | begin |
| 1262 | if (st_rmo_cnt[thid] == 0) |
| 1263 | begin |
| 1264 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 1265 | end |
| 1266 | else |
| 1267 | begin |
| 1268 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 1269 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 1270 | end |
| 1271 | end |
| 1272 | else |
| 1273 | begin |
| 1274 | if (tmp[`ST_SQUASH]) |
| 1275 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 1276 | |
| 1277 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 1278 | begin |
| 1279 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 1280 | end |
| 1281 | else |
| 1282 | begin |
| 1283 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 1284 | begin |
| 1285 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 1286 | end |
| 1287 | tmp[`L2_ACK] = 1'b1; |
| 1288 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 1289 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 1290 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 1291 | end |
| 1292 | end |
| 1293 | end |
| 1294 | endtask |
| 1295 | |
| 1296 | task Chk_req_load; |
| 1297 | input [129:0] pcx_pkt; |
| 1298 | reg [2:0] thid; |
| 1299 | reg [`LD_Pend_Width] tmp; |
| 1300 | reg [39:0] pcx_pa, inst_pa; |
| 1301 | reg [20:0] inst; |
| 1302 | reg [11*8:0] req; |
| 1303 | begin |
| 1304 | |
| 1305 | thid = pcx_pkt[`PCX_THR_ID]; |
| 1306 | tmp = ld_pend_array[thid]; |
| 1307 | inst = tmp[`LSU_MON_INST]; |
| 1308 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 1309 | inst_pa = tmp[`MEMOP_PA]; |
| 1310 | req = DispPCXReq(pcx_pkt); |
| 1311 | |
| 1312 | if (inst[`BLKLD]) |
| 1313 | begin |
| 1314 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 1315 | begin |
| 1316 | DispPendReq(thid); |
| 1317 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 1318 | end |
| 1319 | if (pcx_pa[5:0] == 6'b0) |
| 1320 | begin |
| 1321 | if (tmp[`L2_ISS] != 4'h0 ) |
| 1322 | begin |
| 1323 | DispPendReq(thid); |
| 1324 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 1325 | end |
| 1326 | else |
| 1327 | begin |
| 1328 | tmp[`L2_ISS] = 4'h1; |
| 1329 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 1330 | end |
| 1331 | |
| 1332 | end |
| 1333 | if (pcx_pa[5:0] == 6'h10) |
| 1334 | begin |
| 1335 | if (tmp[`L2_ISS] != 4'h1) |
| 1336 | begin |
| 1337 | DispPendReq(thid); |
| 1338 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 1339 | end |
| 1340 | else |
| 1341 | begin |
| 1342 | tmp[`L2_ISS] = 4'h3; |
| 1343 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 1344 | end |
| 1345 | end |
| 1346 | if (pcx_pa[5:0] == 6'h20) |
| 1347 | begin |
| 1348 | if (tmp[`L2_ISS] != 4'h3) |
| 1349 | begin |
| 1350 | DispPendReq(thid); |
| 1351 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 1352 | end |
| 1353 | else |
| 1354 | begin |
| 1355 | tmp[`L2_ISS] = 4'h7; |
| 1356 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 1357 | end |
| 1358 | end |
| 1359 | if (pcx_pa[5:0] == 6'h30) |
| 1360 | begin |
| 1361 | if (tmp[`L2_ISS] != 4'h7) |
| 1362 | begin |
| 1363 | DispPendReq(thid); |
| 1364 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 1365 | end |
| 1366 | else |
| 1367 | begin |
| 1368 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 1369 | tmp[`L2_ISS] = 4'hF; |
| 1370 | end |
| 1371 | end |
| 1372 | ld_pend_array[thid] = tmp; |
| 1373 | end |
| 1374 | else if (Is_single_pcx_req_ld(inst)) |
| 1375 | begin |
| 1376 | if (tmp[`L2_ISS] == 4'hF) |
| 1377 | begin |
| 1378 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 1379 | end |
| 1380 | else |
| 1381 | begin |
| 1382 | tmp[`L2_ISS] = 4'hF; |
| 1383 | ld_pend_array[thid] = tmp; |
| 1384 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 1385 | end |
| 1386 | end |
| 1387 | else |
| 1388 | begin |
| 1389 | DispPendReq(thid); |
| 1390 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 1391 | end |
| 1392 | end |
| 1393 | endtask |
| 1394 | |
| 1395 | |
| 1396 | function Is_single_pcx_req_ld; |
| 1397 | input [20:0] inst; |
| 1398 | begin |
| 1399 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 1400 | Is_single_pcx_req_ld = 1'b1; |
| 1401 | else |
| 1402 | Is_single_pcx_req_ld = 1'b0; |
| 1403 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 1404 | end |
| 1405 | endfunction |
| 1406 | |
| 1407 | |
| 1408 | function Is_trap; |
| 1409 | input [2:0]tid; |
| 1410 | |
| 1411 | begin |
| 1412 | Is_trap = 1'b0; |
| 1413 | case (`SPC0.lsu_trap_flush[7:0]) |
| 1414 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 1415 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 1416 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 1417 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 1418 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 1419 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 1420 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 1421 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 1422 | endcase |
| 1423 | end |
| 1424 | endfunction |
| 1425 | |
| 1426 | function [8*11:0] DispPCXReq; |
| 1427 | input [129:0] pcx_pkt; |
| 1428 | begin |
| 1429 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 1430 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 1431 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 1432 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 1433 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 1434 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 1435 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 1436 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 1437 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 1438 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 1439 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 1440 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 1441 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 1442 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 1443 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 1444 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 1445 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 1446 | default: |
| 1447 | begin |
| 1448 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 1449 | DispPCXReq = " "; |
| 1450 | end |
| 1451 | endcase |
| 1452 | end |
| 1453 | endfunction |
| 1454 | |
| 1455 | function IsExc; |
| 1456 | input [2:0] core_id; |
| 1457 | reg [21*8:0] DispExc; |
| 1458 | |
| 1459 | begin |
| 1460 | DispExc = 170'b0; |
| 1461 | IsExc = 1'b0; |
| 1462 | |
| 1463 | if (`SPC0.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 1464 | if (`SPC0.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 1465 | if (`SPC0.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 1466 | if (`SPC0.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 1467 | if (`SPC0.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 1468 | if (`SPC0.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 1469 | //if (`SPC0.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 1470 | if (`SPC0.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 1471 | if (`SPC0.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 1472 | if (`SPC0.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 1473 | if (`SPC0.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 1474 | if (`SPC0.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 1475 | if (`SPC0.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 1476 | if (`SPC0.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 1477 | //if (`SPC0.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 1478 | if (`SPC0.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 1479 | if (`SPC0.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 1480 | if (`SPC0.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 1481 | |
| 1482 | |
| 1483 | if (DispExc != 0) |
| 1484 | begin |
| 1485 | IsExc = 1'b1; |
| 1486 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 1487 | end |
| 1488 | |
| 1489 | end |
| 1490 | endfunction |
| 1491 | |
| 1492 | function Is_exu_error; |
| 1493 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 1494 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 1495 | reg err_b; |
| 1496 | reg err_m; |
| 1497 | |
| 1498 | begin |
| 1499 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC0.lsu_tlb_bypass_b)): |
| 1500 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC0.lsu_tlb_bypass_b)); |
| 1501 | |
| 1502 | err_m = (dec_lsu_tid_b[2] ? `SPC0.exu_ecc_m[1] : `SPC0.exu_ecc_m[0]) & `SPC0.lsu.dcc.twocycle_b; |
| 1503 | |
| 1504 | Is_exu_error = err_b | err_m; |
| 1505 | end |
| 1506 | endfunction |
| 1507 | |
| 1508 | /* |
| 1509 | task Insert_tlb_miss_info; |
| 1510 | reg [127:0] tmp; |
| 1511 | begin |
| 1512 | tmp = 128'b0; |
| 1513 | if (tlb_valid[dec_lsu_tid_b]) |
| 1514 | begin |
| 1515 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 1516 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 1517 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 1518 | end |
| 1519 | else |
| 1520 | begin |
| 1521 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 1522 | tmp[`INST_VA] = inst_pc_b; |
| 1523 | tmp[`MEMOP_VA] = vaddr_b; |
| 1524 | tmp[`INST] = inst_b; |
| 1525 | end |
| 1526 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 1527 | end |
| 1528 | endtask |
| 1529 | |
| 1530 | */ |
| 1531 | |
| 1532 | //problem with the signal. |
| 1533 | /* |
| 1534 | always @ (negedge `SPC0.l2clk) |
| 1535 | begin |
| 1536 | if (mmu_dtlb_reload_d2) |
| 1537 | Chk_dtlb_reload; |
| 1538 | end |
| 1539 | |
| 1540 | task Chk_dtlb_reload; |
| 1541 | reg [2:0] thid; |
| 1542 | reg [127:0] tmp; |
| 1543 | begin |
| 1544 | if (`SPC0.tlu_trap_pc_0_valid) |
| 1545 | thid = {1'b0, `SPC0.tlu_trap_0_tid}; |
| 1546 | else if (`SPC0.tlu_trap_pc_1_valid) |
| 1547 | thid = {1'b0, `SPC0.tlu_trap_1_tid}; |
| 1548 | else |
| 1549 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 1550 | |
| 1551 | if (~tlb_valid[thid]) |
| 1552 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 1553 | else |
| 1554 | begin |
| 1555 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 1556 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 1557 | tlb_valid[thid] = 1'b0; |
| 1558 | end |
| 1559 | end |
| 1560 | endtask |
| 1561 | */ |
| 1562 | |
| 1563 | task Insert_ld_miss_info; |
| 1564 | reg [`LD_Pend_Width] tmp; |
| 1565 | begin |
| 1566 | tmp = 213'b0; |
| 1567 | if (ld_valid[dec_lsu_tid_b]) |
| 1568 | begin |
| 1569 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 1570 | DispPendReq(dec_lsu_tid_b); |
| 1571 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 1572 | end |
| 1573 | else |
| 1574 | begin |
| 1575 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 1576 | tmp[`INST_VA] = inst_pc_b; |
| 1577 | tmp[`MEMOP_VA] = vaddr_b; |
| 1578 | tmp[`MEMOP_PA] = {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 1579 | tmp[`INST_ASI] = asi_b; |
| 1580 | |
| 1581 | if (lsu_inst_b[`BLKLD]) |
| 1582 | begin |
| 1583 | tmp[`L2_ISS] = 4'h0; |
| 1584 | tmp[`L2_RESP] = 4'h0; |
| 1585 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 1586 | end |
| 1587 | else |
| 1588 | begin |
| 1589 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 1590 | if (lsu_inst_b[`CASA]) |
| 1591 | tmp[`L2_ISS] = 4'hC; |
| 1592 | else |
| 1593 | tmp[`L2_ISS] = 4'hE; |
| 1594 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 1595 | tmp[`L2_RESP] = 4'hC; |
| 1596 | else |
| 1597 | tmp[`L2_RESP] = 4'hE; |
| 1598 | |
| 1599 | end |
| 1600 | |
| 1601 | tmp[`INST] = inst_b; |
| 1602 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 1603 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 1604 | end |
| 1605 | end |
| 1606 | endtask |
| 1607 | |
| 1608 | |
| 1609 | task Insert_in_last_inst_array; |
| 1610 | reg [135:0] tmp; |
| 1611 | begin |
| 1612 | tmp = 128'b0; |
| 1613 | tmp[`INST_VA] = inst_pc_b; |
| 1614 | tmp[`MEMOP_VA] = vaddr_b; |
| 1615 | tmp[`INST] = inst_b; |
| 1616 | tmp[135:128] = asi_b; |
| 1617 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 1618 | end |
| 1619 | endtask |
| 1620 | |
| 1621 | |
| 1622 | task DispPendReq; |
| 1623 | input [2:0] thid; |
| 1624 | reg [`LD_Pend_Width] tmp; |
| 1625 | begin |
| 1626 | |
| 1627 | tmp = ld_pend_array[thid]; |
| 1628 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 1629 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 1630 | end |
| 1631 | endtask |
| 1632 | |
| 1633 | task Disp_STB_entry; |
| 1634 | input [2:0] thid; |
| 1635 | input [2:0] ptr; |
| 1636 | reg [204:0] tmp; |
| 1637 | begin |
| 1638 | |
| 1639 | tmp = stb[{thid, ptr}]; |
| 1640 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 1641 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 1642 | end |
| 1643 | endtask |
| 1644 | |
| 1645 | /* |
| 1646 | |
| 1647 | task Disp_tlbmiss_pend_array_entry; |
| 1648 | input [2:0] thid; |
| 1649 | reg [127:0] tmp; |
| 1650 | begin |
| 1651 | tmp = tlbmiss_pend_array[thid]; |
| 1652 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 1653 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 1654 | |
| 1655 | end |
| 1656 | endtask |
| 1657 | |
| 1658 | */ |
| 1659 | task Disp_CPX_pkt; |
| 1660 | input [145:0] cpx_pkt; |
| 1661 | begin |
| 1662 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 1663 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 1664 | end |
| 1665 | endtask |
| 1666 | |
| 1667 | |
| 1668 | task Make_STB_data; |
| 1669 | reg [204:0] tmp; |
| 1670 | begin |
| 1671 | tmp = 0; |
| 1672 | tmp[`INST_VA] = inst_pc_b; |
| 1673 | tmp[`MEMOP_VA] = vaddr_b; |
| 1674 | tmp[`MEMOP_PA] = {`SPC0.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 1675 | tmp[`L2_ST_ISS] = 1'b0; |
| 1676 | tmp[`ASI_ST_ISS] = 1'b0; |
| 1677 | tmp[`L2_ACK] = 1'b0; |
| 1678 | tmp[`INST] = inst_b; |
| 1679 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 1680 | tmp[`ST_SQUASH] = 1'b0; |
| 1681 | tmp[`INST_ASI] = asi_b; |
| 1682 | if (`SPC0.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 1683 | tmp[`ST_PRIV] = `HPRIV; |
| 1684 | else if (`SPC0.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 1685 | tmp[`ST_PRIV] = `PRIV; |
| 1686 | else |
| 1687 | tmp[`ST_PRIV] = `USER; |
| 1688 | //bis_asi to io space is not rmo |
| 1689 | |
| 1690 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC0.lsu.tlb_pgnum[39]); |
| 1691 | stb_alloc_data <= tmp; |
| 1692 | end |
| 1693 | endtask |
| 1694 | |
| 1695 | task Insert_in_STB; |
| 1696 | input [195:0] store_data; |
| 1697 | input [2:0] thid; |
| 1698 | begin |
| 1699 | if (stb_full(thid)) |
| 1700 | begin |
| 1701 | //DispSTB(thid); |
| 1702 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 1703 | end |
| 1704 | else |
| 1705 | begin |
| 1706 | stb[{thid, wrptr[thid]}] = store_data; |
| 1707 | //Disp_STB_entry(thid, wrptr[thid]); |
| 1708 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 1709 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 1710 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 1711 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 1712 | end |
| 1713 | end |
| 1714 | endtask |
| 1715 | |
| 1716 | function stb_full; |
| 1717 | input [2:0] thid; |
| 1718 | begin |
| 1719 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 1720 | stb_full = 1'b1; |
| 1721 | else |
| 1722 | stb_full = 1'b0; |
| 1723 | end |
| 1724 | endfunction |
| 1725 | |
| 1726 | |
| 1727 | task Dealloc_STB; |
| 1728 | input [2:0] thid; |
| 1729 | reg [204:0] tmp; |
| 1730 | reg [20:0] lsu_inst; |
| 1731 | begin |
| 1732 | //thid = decode_tid(`SPC0.lsu_stb_dealloc); |
| 1733 | tmp = stb[{thid, rdptr[thid]}]; |
| 1734 | lsu_inst = tmp[`LSU_MON_INST]; |
| 1735 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 1736 | begin |
| 1737 | //DispSTB(thid); |
| 1738 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC0.lsu_stb_dealloc); |
| 1739 | end |
| 1740 | if (tmp[`L2_ST_ISS]) |
| 1741 | begin |
| 1742 | if (~tmp[`L2_ACK]) |
| 1743 | begin |
| 1744 | Disp_STB_entry(thid, rdptr[thid]); |
| 1745 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC0.lsu_stb_dealloc); |
| 1746 | end |
| 1747 | end |
| 1748 | else if (tmp[`ASI_ST_ISS]) |
| 1749 | begin |
| 1750 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 1751 | end |
| 1752 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 1753 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 1754 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 1755 | // and deallocated. |
| 1756 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 1757 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 1758 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 1759 | begin |
| 1760 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 1761 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 1762 | end |
| 1763 | else |
| 1764 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC0.lsu_stb_dealloc); |
| 1765 | |
| 1766 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 1767 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 1768 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 1769 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 1770 | /* |
| 1771 | if (tmp[`RMO]) |
| 1772 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 1773 | */ |
| 1774 | end |
| 1775 | endtask |
| 1776 | |
| 1777 | task Squash_STB; |
| 1778 | input [2:0] thid; |
| 1779 | reg [204:0] tmp; |
| 1780 | reg [3:0] squash_cnt; |
| 1781 | reg [2:0] i; |
| 1782 | begin |
| 1783 | squash_cnt = 4'b0; |
| 1784 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 1785 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 1786 | if (rdptr[thid] != iss_ptr[thid]) |
| 1787 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 1788 | |
| 1789 | if (iss_ptr[thid] == wrptr[thid]) |
| 1790 | begin |
| 1791 | if (stb_valid[{thid, wrptr[thid]}]) |
| 1792 | squash_cnt = 8; |
| 1793 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 1794 | * |
| 1795 | else |
| 1796 | begin |
| 1797 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 1798 | end |
| 1799 | */ |
| 1800 | end |
| 1801 | else |
| 1802 | begin |
| 1803 | if (iss_ptr[thid] < wrptr[thid]) |
| 1804 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 1805 | else if (iss_ptr[thid] > wrptr[thid]) |
| 1806 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 1807 | end |
| 1808 | |
| 1809 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 1810 | |
| 1811 | i = iss_ptr[thid]; |
| 1812 | |
| 1813 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 1814 | |
| 1815 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 1816 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 1817 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 1818 | |
| 1819 | while (squash_cnt) |
| 1820 | begin |
| 1821 | tmp = stb[{thid, i}]; |
| 1822 | if (~stb_valid[{thid, i}]) |
| 1823 | begin |
| 1824 | //DispSTB(thid); |
| 1825 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 1826 | end |
| 1827 | if (tmp[`L2_ST_ISS]) |
| 1828 | begin |
| 1829 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 1830 | end |
| 1831 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 1832 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 1833 | //set in the chkr which was causin it to fire. |
| 1834 | //if (~tmp[`ST_SQUASH]) |
| 1835 | //begin |
| 1836 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 1837 | //end |
| 1838 | stb_valid[{thid, i}] = 1'b0; |
| 1839 | |
| 1840 | i = i + 1; |
| 1841 | squash_cnt = squash_cnt - 1'b1; |
| 1842 | end |
| 1843 | |
| 1844 | end |
| 1845 | endtask |
| 1846 | |
| 1847 | task Chk_store; |
| 1848 | reg [2:0] thid; |
| 1849 | reg [47:0] addr; |
| 1850 | reg [3:0] i; |
| 1851 | reg [204:0] tmp; |
| 1852 | begin |
| 1853 | if ((bst_cnt > 0) && (`SPC0.lsu_stb_alloc == 8'b0)) |
| 1854 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 1855 | |
| 1856 | //For bst the stb is still written even though we have errors. |
| 1857 | //Stb is written in W stage. Howvere for first blk store helper |
| 1858 | //the err will be flagged by FGU in b stage. We can miss the |
| 1859 | // err signal if we don't sample in B. |
| 1860 | //for the last helper err will be signalled in B stage of last helper and at |
| 1861 | |
| 1862 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 1863 | bst_fgu_err = 1'b1; |
| 1864 | |
| 1865 | if (`SPC0.lsu_stb_alloc[7:0] != 8'b0) |
| 1866 | begin |
| 1867 | thid = decode_tid(`SPC0.lsu_stb_alloc[7:0]); |
| 1868 | if (store_alloc) |
| 1869 | begin |
| 1870 | if (thid != dec_lsu_tid_w) |
| 1871 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC0.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 1872 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 1873 | end |
| 1874 | else |
| 1875 | begin |
| 1876 | if (lsu_bst_active[thid]) |
| 1877 | begin |
| 1878 | if (bst_cnt == 0) |
| 1879 | begin |
| 1880 | bst_data = bst_inst_data; |
| 1881 | end |
| 1882 | else |
| 1883 | begin |
| 1884 | if (thid != bst_active_thid) |
| 1885 | begin |
| 1886 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC0.lsu_stb_alloc[7:0], bst_active_thid); |
| 1887 | end |
| 1888 | |
| 1889 | addr = bst_data[`MEMOP_VA]; |
| 1890 | |
| 1891 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 1892 | addr = bst_data[`MEMOP_PA]; |
| 1893 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 1894 | end |
| 1895 | bst_cnt = bst_cnt + 1; |
| 1896 | Insert_in_STB(bst_data, bst_active_thid); |
| 1897 | if (bst_cnt == 8) |
| 1898 | begin |
| 1899 | bst_cnt = 0; |
| 1900 | lsu_bst_active[thid] = 1'b0; |
| 1901 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 1902 | begin |
| 1903 | for (i = 0; i < 8; i=i+1) |
| 1904 | begin |
| 1905 | tmp = stb[{thid, i[2:0]}]; |
| 1906 | if (tmp[`ST_SQUASH]) |
| 1907 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 1908 | tmp[`ST_SQUASH] = 1'b1; |
| 1909 | stb[{thid, i[2:0]}] = tmp; |
| 1910 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 1911 | end |
| 1912 | end |
| 1913 | bst_fgu_err = 1'b0; |
| 1914 | end |
| 1915 | end |
| 1916 | else |
| 1917 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC0.lsu_stb_alloc[7:0]); |
| 1918 | |
| 1919 | end |
| 1920 | end |
| 1921 | else |
| 1922 | begin |
| 1923 | if (store_alloc) |
| 1924 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 1925 | end |
| 1926 | end |
| 1927 | endtask |
| 1928 | |
| 1929 | task Chk_st_on_ASI_ring; |
| 1930 | input ring; |
| 1931 | reg [2:0] thid; |
| 1932 | reg [7:0] asi; |
| 1933 | reg [47:0] addr, act_addr; |
| 1934 | reg [1:0] req_type; |
| 1935 | reg [204:0] tmp; |
| 1936 | |
| 1937 | begin |
| 1938 | if (ring == `LOCAL) |
| 1939 | thid =`SPC0.lsu_rngl_cdbus[58:56]; |
| 1940 | else |
| 1941 | thid =`SPC0.lsu_rngf_cdbus[58:56]; |
| 1942 | |
| 1943 | if (ring == `LOCAL) |
| 1944 | asi =`SPC0.lsu_rngl_cdbus[55:48]; |
| 1945 | else |
| 1946 | asi =`SPC0.lsu_rngf_cdbus[55:48]; |
| 1947 | |
| 1948 | if (ring == `LOCAL) |
| 1949 | addr =`SPC0.lsu_rngl_cdbus[47:0]; |
| 1950 | else |
| 1951 | addr =`SPC0.lsu_rngf_cdbus[47:0]; |
| 1952 | |
| 1953 | if (ring == `LOCAL) |
| 1954 | req_type =`SPC0.lsu_rngl_cdbus[61:60]; |
| 1955 | else |
| 1956 | req_type =`SPC0.lsu_rngf_cdbus[61:60]; |
| 1957 | |
| 1958 | |
| 1959 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 1960 | if (tmp[`ASI_ST_ISS]) |
| 1961 | begin |
| 1962 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 1963 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 1964 | end |
| 1965 | |
| 1966 | if (tmp[`ST_SQUASH]) |
| 1967 | begin |
| 1968 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 1969 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 1970 | end |
| 1971 | |
| 1972 | act_addr = tmp[`MEMOP_PA]; |
| 1973 | act_addr = {act_addr[39:3], 3'b0}; |
| 1974 | |
| 1975 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 1976 | //the address. |
| 1977 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 1978 | begin |
| 1979 | tmp[`ASI_ST_ISS] = 1'b1; |
| 1980 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 1981 | if (ring == `LOCAL) |
| 1982 | begin |
| 1983 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 1984 | end |
| 1985 | else |
| 1986 | begin |
| 1987 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 1988 | end |
| 1989 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 1990 | end |
| 1991 | else |
| 1992 | begin |
| 1993 | if (ring == `LOCAL) |
| 1994 | begin |
| 1995 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 1996 | end |
| 1997 | else |
| 1998 | begin |
| 1999 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 2000 | end |
| 2001 | end |
| 2002 | |
| 2003 | end |
| 2004 | endtask |
| 2005 | |
| 2006 | |
| 2007 | task chk_store_issue_to_pcx; |
| 2008 | input [129:0] pcx_pkt; |
| 2009 | reg [2:0] thid; |
| 2010 | reg [204:0] tmp; |
| 2011 | reg [20:0] inst; |
| 2012 | reg [39:0] pcx_pa, inst_pa; |
| 2013 | begin |
| 2014 | thid = pcx_pkt[`PCX_THR_ID]; |
| 2015 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 2016 | inst = tmp[`LSU_MON_INST]; |
| 2017 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 2018 | inst_pa = tmp[`MEMOP_PA]; |
| 2019 | |
| 2020 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 2021 | begin |
| 2022 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 2023 | end |
| 2024 | if (pcx_pkt[`PCX_INV]) |
| 2025 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 2026 | |
| 2027 | |
| 2028 | if (~inst[`ST]) |
| 2029 | begin |
| 2030 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2031 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2032 | end |
| 2033 | |
| 2034 | /* CONFIRM WITH MARK |
| 2035 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 2036 | begin |
| 2037 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2038 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 2039 | end |
| 2040 | */ |
| 2041 | //enhancement req 100146 |
| 2042 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 2043 | begin |
| 2044 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2045 | end |
| 2046 | |
| 2047 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 2048 | begin |
| 2049 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2050 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2051 | end |
| 2052 | |
| 2053 | if (tmp[`L2_ST_ISS]) |
| 2054 | begin |
| 2055 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2056 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2057 | end |
| 2058 | else |
| 2059 | tmp[`L2_ST_ISS] = 1'b1; |
| 2060 | |
| 2061 | if (tmp[`ST_SQUASH]) |
| 2062 | begin |
| 2063 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2064 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2065 | end |
| 2066 | |
| 2067 | if (tmp[`RMO]) |
| 2068 | begin |
| 2069 | if (~pcx_pkt[`PCX_BIS]) |
| 2070 | begin |
| 2071 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2072 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2073 | end |
| 2074 | if (tmp[`L2_ACK]) |
| 2075 | begin |
| 2076 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2077 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 2078 | end |
| 2079 | else |
| 2080 | begin |
| 2081 | tmp[`L2_ACK] = 1'b1; |
| 2082 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 2083 | //response seen from stub |
| 2084 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 2085 | end |
| 2086 | end |
| 2087 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 2088 | |
| 2089 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 2090 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 2091 | end |
| 2092 | endtask |
| 2093 | |
| 2094 | `ifdef INJ_STB_ERR_IN_CMP |
| 2095 | |
| 2096 | |
| 2097 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 2098 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 2099 | reg [204:0] err_tmp ; |
| 2100 | reg [20:0] err_inst; |
| 2101 | reg [44:0] cam_data; |
| 2102 | reg [5:0] err_bit; |
| 2103 | integer err_inj_cnt; |
| 2104 | reg cmp_stb_err_inj; |
| 2105 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 2106 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 2107 | |
| 2108 | initial |
| 2109 | begin |
| 2110 | cmp_stb_err_inj = 1'b0; |
| 2111 | |
| 2112 | cam_data = 45'b0; |
| 2113 | err_bit = 11; |
| 2114 | err_inj_cnt = 0; |
| 2115 | stb_err_inj = 0; |
| 2116 | if (("cmp_stb_err_inj_on")) |
| 2117 | cmp_stb_err_inj = 1'b1; |
| 2118 | else |
| 2119 | cmp_stb_err_inj = 1'b0; |
| 2120 | end |
| 2121 | |
| 2122 | always @ (negedge (`SPC0.l2clk & enabled & cmp_stb_err_inj)) |
| 2123 | begin //{ |
| 2124 | //valid stb ram rd for issue to pcx |
| 2125 | stb_err_inj = 1'b0; |
| 2126 | if (`SPC0.lsu.sbc.ram_rptr_vld_2 & `SPC0.lsu.sbc.st_pcx_rq_p3 & `SPC0.lsu.pic.pic_st_sel_p3) |
| 2127 | begin //{ |
| 2128 | err_tid = decode_tid(`SPC0.lsu.sbc.st_rq_sel_p3[7:0]); |
| 2129 | err_index = `SPC0.lsu.sbc.ram_rptr_d1; |
| 2130 | err_tmp = stb[{err_tid, err_index}]; |
| 2131 | err_inst = err_tmp[`LSU_MON_INST]; |
| 2132 | cam_data = `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 2133 | err_priv = err_tmp[`ST_PRIV]; |
| 2134 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 2135 | if (err_inst[`CASA]) |
| 2136 | begin //{ |
| 2137 | err_inj_cnt = err_inj_cnt + 1; |
| 2138 | if (err_inj_cnt == 10) |
| 2139 | begin //{ |
| 2140 | case (err_bit) |
| 2141 | 11, 12: err_bit = err_bit + 1; |
| 2142 | 13: err_bit = 44; |
| 2143 | 44: err_bit = 11; |
| 2144 | endcase |
| 2145 | err_inj_cnt = 0; |
| 2146 | stb_err_inj = 1'b1; |
| 2147 | |
| 2148 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 2149 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 2150 | #1; |
| 2151 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 2152 | end //} |
| 2153 | end //} |
| 2154 | end //} |
| 2155 | if (stb_err_inj_d2) |
| 2156 | begin |
| 2157 | if (~`SPC0.lsu_sbapp_err_g) |
| 2158 | begin |
| 2159 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 2160 | end |
| 2161 | else |
| 2162 | begin |
| 2163 | if ((`SPC0.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 2164 | (`SPC0.lsu_stberr_index_g != stb_err_index_d2) || |
| 2165 | (`SPC0.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 2166 | begin |
| 2167 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 2168 | end |
| 2169 | end |
| 2170 | end |
| 2171 | else |
| 2172 | begin |
| 2173 | if (`SPC0.lsu_sbapp_err_g) |
| 2174 | begin |
| 2175 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC0.lsu_stberr_tid_g); |
| 2176 | end |
| 2177 | end |
| 2178 | |
| 2179 | end //} |
| 2180 | |
| 2181 | |
| 2182 | always @ (posedge (`SPC0.l2clk & enabled & cmp_stb_err_inj)) |
| 2183 | begin |
| 2184 | stb_err_inj_d1 <= stb_err_inj; |
| 2185 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 2186 | stb_err_tid_d1 <= err_tid; |
| 2187 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 2188 | stb_err_index_d1 <= err_index; |
| 2189 | stb_err_index_d2 <= stb_err_index_d1; |
| 2190 | stb_err_priv_d1 <= err_priv; |
| 2191 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 2192 | end |
| 2193 | |
| 2194 | `endif |
| 2195 | `endif |
| 2196 | `endif |
| 2197 | endmodule |
| 2198 | |
| 2199 | `endif |
| 2200 | `ifdef CORE_1 |
| 2201 | |
| 2202 | module lsu_mon_c1; |
| 2203 | `ifndef GATESIM |
| 2204 | |
| 2205 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 2206 | `ifndef NO_MONITORS |
| 2207 | |
| 2208 | reg imm_asi_vld_e; |
| 2209 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 2210 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 2211 | reg [1:0] exu_ecc_b; |
| 2212 | reg [1:0] exu_lsu_va_error_b; |
| 2213 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 2214 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 2215 | reg [31:0] inst_e, inst_m, inst_b; |
| 2216 | reg [47:0] vaddr_m, vaddr_b; |
| 2217 | reg [63:0] int_st_data_m, int_st_data_b; |
| 2218 | reg [63:0] fp_st_sata_fx2; |
| 2219 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 2220 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 2221 | |
| 2222 | reg [7:0] ld_valid; |
| 2223 | reg [7:0] tlb_valid; |
| 2224 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 2225 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 2226 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 2227 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 2228 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 2229 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 2230 | //the L2c. |
| 2231 | reg [63:0] stb_valid; |
| 2232 | reg [`STB_Pend_Width] stb[63:0]; |
| 2233 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 2234 | |
| 2235 | reg [7:0] pf_cnt[7:0]; |
| 2236 | reg [7:0] dcache_inv_cnt[7:0]; |
| 2237 | reg [7:0] st_rmo_cnt[7:0]; |
| 2238 | |
| 2239 | reg [55:0] print_inst; |
| 2240 | |
| 2241 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 2242 | |
| 2243 | reg [7:0] lsu_bst_active; |
| 2244 | reg store_alloc; |
| 2245 | reg [3:0] bst_cnt; |
| 2246 | reg [195:0] stb_alloc_data; |
| 2247 | reg [195:0] bst_data, bst_inst_data; |
| 2248 | reg [2:0] bst_active_thid; |
| 2249 | reg bst_fgu_err; |
| 2250 | |
| 2251 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 2252 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 2253 | //different types of err occur on blk ld helper returns |
| 2254 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 2255 | //stored in DFESR |
| 2256 | |
| 2257 | wire [2:0] core_id = 1; |
| 2258 | |
| 2259 | integer i; |
| 2260 | integer err_cnt; |
| 2261 | |
| 2262 | reg enabled; |
| 2263 | reg reset_in_middle; |
| 2264 | reg [7:0] finish_mask; |
| 2265 | |
| 2266 | initial |
| 2267 | begin |
| 2268 | enabled = 0; |
| 2269 | reset_in_middle = 0; |
| 2270 | ld_valid = 8'b0; |
| 2271 | lsu_inst_e = 0; |
| 2272 | tlb_valid = 8'b0; |
| 2273 | for (i = 0; i < 8; i = i+1) |
| 2274 | begin |
| 2275 | pf_cnt[i] = 0; |
| 2276 | dcache_inv_cnt[i] = 0; |
| 2277 | wrptr[i] = 0; |
| 2278 | rdptr[i] = 0; |
| 2279 | iss_ptr[i] = 0; |
| 2280 | ret_ptr[i] = 0; |
| 2281 | st_rmo_cnt[i] = 0; |
| 2282 | is_blkld[i] = 1'b0; |
| 2283 | st_priv[i] = 2'b0; |
| 2284 | l2_blk_ld_errtype[i] = 2'b0; |
| 2285 | end |
| 2286 | lsu_bst_active = 8'b0; |
| 2287 | store_alloc = 1'b0; |
| 2288 | bst_cnt = 4'b0; |
| 2289 | stb_valid = 64'b0; |
| 2290 | |
| 2291 | // avoid time zero ugliness. jp |
| 2292 | //@(posedge `SPC0.l2clk); |
| 2293 | //@(negedge `SPC0.l2clk); |
| 2294 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 2295 | |
| 2296 | case (core_id) |
| 2297 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 2298 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 2299 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 2300 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 2301 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 2302 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 2303 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 2304 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 2305 | endcase |
| 2306 | end |
| 2307 | |
| 2308 | always @ (`TOP.in_reset) |
| 2309 | begin |
| 2310 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 2311 | begin |
| 2312 | enabled = 1'b1; |
| 2313 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 2314 | end |
| 2315 | |
| 2316 | |
| 2317 | if (`TOP.in_reset & enabled) |
| 2318 | begin |
| 2319 | reset_in_middle = 1'b1; |
| 2320 | enabled = 1'b0; |
| 2321 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 2322 | end |
| 2323 | end |
| 2324 | |
| 2325 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 2326 | begin //{ |
| 2327 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 2328 | begin //{ |
| 2329 | for (i = 0; i < 8; i=i+1) |
| 2330 | begin |
| 2331 | if (ld_valid[i]) |
| 2332 | begin |
| 2333 | DispPendReq(i); |
| 2334 | end |
| 2335 | end |
| 2336 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 2337 | end //} |
| 2338 | if (|stb_valid[63:0]) |
| 2339 | begin //{ |
| 2340 | err_cnt = 0; |
| 2341 | for (i = 0; i < 64; i=i+1) |
| 2342 | begin |
| 2343 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 2344 | begin |
| 2345 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 2346 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 2347 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 2348 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 2349 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 2350 | //of simualation. |
| 2351 | if (~is_squash_bit_set(i[5:0])) |
| 2352 | begin |
| 2353 | err_cnt = err_cnt + 1; |
| 2354 | Disp_STB_entry(i[5:3],i[2:0]); |
| 2355 | end |
| 2356 | end |
| 2357 | end |
| 2358 | if (err_cnt) |
| 2359 | begin |
| 2360 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 2361 | end |
| 2362 | end //} |
| 2363 | err_cnt = 0; |
| 2364 | for (i = 0; i < 8; i=i+1) |
| 2365 | begin //{ |
| 2366 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 2367 | begin |
| 2368 | err_cnt = 1; |
| 2369 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 2370 | end |
| 2371 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 2372 | begin |
| 2373 | err_cnt = 1; |
| 2374 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 2375 | end |
| 2376 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 2377 | begin |
| 2378 | err_cnt = 1; |
| 2379 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 2380 | end |
| 2381 | end //} |
| 2382 | if (err_cnt) |
| 2383 | begin |
| 2384 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 2385 | end |
| 2386 | end //} |
| 2387 | |
| 2388 | function is_squash_bit_set; |
| 2389 | input [5:0] index; |
| 2390 | reg [204:0] tmp; |
| 2391 | begin |
| 2392 | tmp = stb[index]; |
| 2393 | if (tmp[`ST_SQUASH]) |
| 2394 | is_squash_bit_set = 1'b1; |
| 2395 | else |
| 2396 | is_squash_bit_set = 1'b0; |
| 2397 | end |
| 2398 | endfunction |
| 2399 | |
| 2400 | |
| 2401 | always @ (negedge (`SPC1.l2clk & enabled)) |
| 2402 | begin //{ |
| 2403 | |
| 2404 | asi_e = `SPC1.lsu.dcc.dcc_asi_e[7:0]; |
| 2405 | |
| 2406 | lsu_inst_e[`LD] <= `SPC1.dec_ld_inst_e; |
| 2407 | lsu_inst_e[`ST] <= `SPC1.dec_st_inst_e; |
| 2408 | lsu_inst_e[`FP] <= `SPC1.dec_fpldst_inst_e; |
| 2409 | lsu_inst_e[`PREF] <= `SPC1.dec_pref_inst_e; |
| 2410 | lsu_inst_e[`SWAP] <= `SPC1.dec_swap_inst_e; |
| 2411 | lsu_inst_e[`CASA] <= `SPC1.dec_casa_inst_e; |
| 2412 | lsu_inst_e[`LDSTUB] <= `SPC1.dec_ldstub_inst_e; |
| 2413 | lsu_inst_e[`FLUSH] <= `SPC1.dec_flush_inst_e; |
| 2414 | lsu_inst_e[`MEMBAR] <= `SPC1.dec_memstbar_inst_e; |
| 2415 | lsu_inst_e[`LDD] <= `SPC1.dec_ld_inst_e & `SPC1.dec_ldst_dbl_e & ~`SPC1.dec_fpldst_inst_e; |
| 2416 | lsu_inst_e[`STD] <= `SPC1.dec_st_inst_e & `SPC1.dec_ldst_dbl_e & ~`SPC1.lsu.dec_fpldst_inst_e; |
| 2417 | |
| 2418 | lsu_inst_e[`BLKLD] <= `SPC1.dec_ld_inst_e & `SPC1.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 2419 | lsu_inst_e[`BLKST] <= `SPC1.dec_st_inst_e & `SPC1.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 2420 | lsu_inst_e[`QLD] <= `SPC1.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 2421 | lsu_inst_e[`ASR_RD_WR] <= `SPC1.dec_sr_inst_e & (`SPC1.dec_ld_inst_e | `SPC1.dec_st_inst_e); |
| 2422 | lsu_inst_e[`PR_RD_WR] <= `SPC1.dec_pr_inst_e & (`SPC1.dec_ld_inst_e | `SPC1.dec_st_inst_e); |
| 2423 | lsu_inst_e[`HPR_RD_WR] <= `SPC1.dec_hpr_inst_e & (`SPC1.dec_ld_inst_e | `SPC1.dec_st_inst_e); |
| 2424 | lsu_inst_e[`FSR_RD_WR] <= `SPC1.dec_fsr_ldst_e & (`SPC1.dec_ld_inst_e | `SPC1.dec_st_inst_e); |
| 2425 | end //} |
| 2426 | |
| 2427 | always @ (posedge (`SPC1.l2clk & enabled)) |
| 2428 | begin //{ |
| 2429 | dec_tg0_inst_d <= `SPC1.dec.ded0.decode_mux[31:0]; |
| 2430 | dec_tg1_inst_d <= `SPC1.dec.ded1.decode_mux[31:0]; |
| 2431 | imm_asi_vld_e <= `SPC1.lsu.dec_imm_asi_vld_d; |
| 2432 | |
| 2433 | imm_asi_e <= `SPC1.lsu.dec_imm_asi_d; |
| 2434 | dec_altspace_e <= `SPC1.dec_altspace_d; |
| 2435 | dec_altspace_m <= dec_altspace_e; |
| 2436 | dec_altspace_b <= dec_altspace_m; |
| 2437 | |
| 2438 | exu_ecc_b <= `SPC1.exu_ecc_m; |
| 2439 | exu_lsu_va_error_b <= `SPC1.exu_lsu_va_error_m; |
| 2440 | |
| 2441 | dec_lsu_tid_e <= `SPC1.dec_lsu_tg_d ? {1'b1, `SPC1.dec_lsu_tid1_d} : {1'b0, `SPC1.dec_lsu_tid0_d}; |
| 2442 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 2443 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 2444 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 2445 | |
| 2446 | inst_pc_e <= `SPC1.dec_lsu_tg_d ? {`SPC1.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC1.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 2447 | inst_pc_m <= inst_pc_e; |
| 2448 | inst_pc_b <= inst_pc_m; |
| 2449 | inst_pc_w <= inst_pc_b; |
| 2450 | |
| 2451 | inst_e <= `SPC1.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 2452 | inst_m <= inst_e; |
| 2453 | inst_b <= inst_m; |
| 2454 | |
| 2455 | vaddr_m <= `SPC1.exu_lsu_address_e; |
| 2456 | vaddr_b <= vaddr_m; |
| 2457 | |
| 2458 | int_st_data_m <= `SPC1.exu_lsu_store_data_e; |
| 2459 | int_st_data_b <= int_st_data_m; |
| 2460 | fp_st_sata_fx2 <= `SPC1.fgu_lsu_fst_data_fx1; |
| 2461 | |
| 2462 | mmu_dtlb_reload_d1 <= `SPC1.mmu_dtlb_reload; |
| 2463 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 2464 | |
| 2465 | //pcx_thid_d1 <= `SPC1.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 2466 | lsu_inst_m <= lsu_inst_e; |
| 2467 | lsu_inst_b <= lsu_inst_m; |
| 2468 | |
| 2469 | asi_m <= asi_e; |
| 2470 | asi_b <= asi_m; |
| 2471 | end //} |
| 2472 | |
| 2473 | function Is_blk_asi; |
| 2474 | input [7:0] asi; |
| 2475 | begin |
| 2476 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 2477 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 2478 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 2479 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 2480 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 2481 | end |
| 2482 | endfunction |
| 2483 | |
| 2484 | function Is_qld_asi; |
| 2485 | input [7:0] asi; |
| 2486 | begin |
| 2487 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 2488 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 2489 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 2490 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 2491 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 2492 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 2493 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 2494 | end |
| 2495 | endfunction |
| 2496 | |
| 2497 | function Is_bis_asi; |
| 2498 | input [7:0] asi; |
| 2499 | begin |
| 2500 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 2501 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 2502 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 2503 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 2504 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 2505 | end |
| 2506 | endfunction |
| 2507 | |
| 2508 | always @ (negedge (`SPC1.l2clk & enabled)) |
| 2509 | begin //{ |
| 2510 | Chk_store; |
| 2511 | store_alloc = 1'b0; |
| 2512 | if (lsu_inst_m != 0) |
| 2513 | begin |
| 2514 | if (`SPC1.dec_flush_lm) |
| 2515 | begin |
| 2516 | lsu_inst_m <= 0; |
| 2517 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 2518 | end |
| 2519 | end |
| 2520 | |
| 2521 | if (lsu_inst_b != 0) |
| 2522 | begin //{ |
| 2523 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 2524 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 2525 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 2526 | else print_inst = ""; |
| 2527 | |
| 2528 | if (`SPC1.dec_flush_lb) |
| 2529 | begin |
| 2530 | lsu_inst_b <= 0; |
| 2531 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 2532 | end |
| 2533 | else if (`SPC1.tlu_flush_lsu_b) |
| 2534 | begin |
| 2535 | lsu_inst_b <= 0; |
| 2536 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 2537 | end |
| 2538 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 2539 | //casa shd be killed. |
| 2540 | //This function will also chk for errors on 2nd cycle. |
| 2541 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 2542 | begin |
| 2543 | lsu_inst_b <= 0; |
| 2544 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 2545 | end |
| 2546 | else if ((`SPC1.fgu_cecc_fx2 || `SPC1.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 2547 | begin |
| 2548 | lsu_inst_b <= 0; |
| 2549 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 2550 | end |
| 2551 | else if (IsExc(core_id)) |
| 2552 | lsu_inst_b <= 0; |
| 2553 | else if (!`SPC1.lsu_tlb_miss_b_) |
| 2554 | begin |
| 2555 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 2556 | //Insert_tlb_miss_info; |
| 2557 | end |
| 2558 | else |
| 2559 | begin //{ |
| 2560 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 2561 | //an exception tlu anyway tells the front end to flush itself there is |
| 2562 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 2563 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 2564 | //handles it when it is reissued by the front end. |
| 2565 | |
| 2566 | if (`SPC1.lsu_tlb_bypass_b) |
| 2567 | begin |
| 2568 | if (`SPC1.lsu_sync != 8'b0) |
| 2569 | begin |
| 2570 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 2571 | end |
| 2572 | else |
| 2573 | begin |
| 2574 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 2575 | end |
| 2576 | end |
| 2577 | else |
| 2578 | begin |
| 2579 | if (`SPC1.lsu_sync != 8'b0) |
| 2580 | begin |
| 2581 | if (lsu_inst_b[`ST]) |
| 2582 | begin |
| 2583 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 2584 | end |
| 2585 | else |
| 2586 | begin |
| 2587 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 2588 | end |
| 2589 | end |
| 2590 | else |
| 2591 | begin |
| 2592 | if (lsu_inst_b[`ST]) |
| 2593 | begin |
| 2594 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 2595 | end |
| 2596 | else |
| 2597 | begin |
| 2598 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 2599 | end |
| 2600 | end |
| 2601 | end |
| 2602 | |
| 2603 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 2604 | begin //{ |
| 2605 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC1.lsu.stb_cam_hit) |
| 2606 | begin |
| 2607 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 2608 | end |
| 2609 | end //} |
| 2610 | |
| 2611 | if (lsu_inst_b[`LD]) |
| 2612 | Insert_ld_miss_info; |
| 2613 | |
| 2614 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 2615 | begin |
| 2616 | Make_STB_data; |
| 2617 | store_alloc = 1'b1; |
| 2618 | end |
| 2619 | Insert_in_last_inst_array; |
| 2620 | |
| 2621 | if (`SPC1.lsu_trap_flush[7:0]) |
| 2622 | begin |
| 2623 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC1.lsu_trap_flush[7:0])); |
| 2624 | end |
| 2625 | end //} |
| 2626 | end //} |
| 2627 | end //} |
| 2628 | |
| 2629 | //STB ue testing: |
| 2630 | //This is how we test squashing of stores by LSU_mon: |
| 2631 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 2632 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 2633 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 2634 | //The squashed stores are deallocated when either a block_store_kill is |
| 2635 | //asserted or dealloc signals are asserted by the LSU. |
| 2636 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 2637 | //all the pending stores in the IFU. It means the when block_store_kill |
| 2638 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 2639 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 2640 | //the sbdiou signal to TLU. |
| 2641 | |
| 2642 | |
| 2643 | always @ (negedge (`SPC1.l2clk & enabled)) |
| 2644 | begin |
| 2645 | if (`SPC1.lsu_l15_valid & `SPC1.lsu.spc_pcx_data_pa[129]) |
| 2646 | Chk_pcx_req_pkt(`SPC1.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 2647 | if ((`SPC1.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC1.lsu_rngl_cdbus[59]) |
| 2648 | Chk_st_on_ASI_ring(`LOCAL); |
| 2649 | |
| 2650 | if ((`SPC1.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC1.lsu_rngf_cdbus[59]) |
| 2651 | Chk_st_on_ASI_ring(`FAST); |
| 2652 | |
| 2653 | //if (`SPC1.l15_lsu_valid) |
| 2654 | //Chk_cpx_response_pkt({`SPC1.l15_lsu_valid, `SPC1.l15_lsu_cpkt[17:13],`SPC1.l15_lsu_cpkt[11:0],`SPC1.l15_spc_data1[127:0]}); |
| 2655 | |
| 2656 | if (`SPC1.cpx_spc_data_cx[145]) |
| 2657 | Chk_cpx_response_pkt(`SPC1.cpx_spc_data_cx); |
| 2658 | |
| 2659 | if (`SPC1.lsu_complete[7:0] != 8'b0) |
| 2660 | begin |
| 2661 | if (`SPC1.lsu_complete[0]) Chk_ld_complete(0); |
| 2662 | if (`SPC1.lsu_complete[1]) Chk_ld_complete(1); |
| 2663 | if (`SPC1.lsu_complete[2]) Chk_ld_complete(2); |
| 2664 | if (`SPC1.lsu_complete[3]) Chk_ld_complete(3); |
| 2665 | if (`SPC1.lsu_complete[4]) Chk_ld_complete(4); |
| 2666 | if (`SPC1.lsu_complete[5]) Chk_ld_complete(5); |
| 2667 | if (`SPC1.lsu_complete[6]) Chk_ld_complete(6); |
| 2668 | if (`SPC1.lsu_complete[7]) Chk_ld_complete(7); |
| 2669 | end |
| 2670 | |
| 2671 | if (`SPC1.lsu_block_store_kill[7:0] != 8'b0) |
| 2672 | begin |
| 2673 | if (`SPC1.lsu_block_store_kill[0]) Squash_STB(0); |
| 2674 | if (`SPC1.lsu_block_store_kill[1]) Squash_STB(1); |
| 2675 | if (`SPC1.lsu_block_store_kill[2]) Squash_STB(2); |
| 2676 | if (`SPC1.lsu_block_store_kill[3]) Squash_STB(3); |
| 2677 | if (`SPC1.lsu_block_store_kill[4]) Squash_STB(4); |
| 2678 | if (`SPC1.lsu_block_store_kill[5]) Squash_STB(5); |
| 2679 | if (`SPC1.lsu_block_store_kill[6]) Squash_STB(6); |
| 2680 | if (`SPC1.lsu_block_store_kill[7]) Squash_STB(7); |
| 2681 | end |
| 2682 | |
| 2683 | if (`SPC1.lsu_stb_dealloc[7:0] != 8'b0) |
| 2684 | begin |
| 2685 | if (`SPC1.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 2686 | if (`SPC1.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 2687 | if (`SPC1.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 2688 | if (`SPC1.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 2689 | if (`SPC1.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 2690 | if (`SPC1.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 2691 | if (`SPC1.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 2692 | if (`SPC1.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 2693 | end |
| 2694 | |
| 2695 | if (`SPC1.lsu_block_store_stall) |
| 2696 | Chk_block_store; |
| 2697 | |
| 2698 | if (`SPC1.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 2699 | Set_block_store_parameters; |
| 2700 | |
| 2701 | if (`SPC1.lsu_sbdiou_err_g || `SPC1.lsu_sbapp_err_g) |
| 2702 | Squash_store; |
| 2703 | |
| 2704 | if (`SPC1.lsu_stb_flush_g) |
| 2705 | st_priv[`SPC1.lsu_stberr_tid_g] = get_priv_on_flush(`SPC1.lsu_stberr_tid_g); |
| 2706 | end |
| 2707 | |
| 2708 | function [1:0] get_priv_on_flush; |
| 2709 | input [2:0] tid; |
| 2710 | reg [2:0] sq_index; |
| 2711 | reg [204:0] tmp; |
| 2712 | |
| 2713 | begin |
| 2714 | sq_index = `SPC1.lsu_stberr_index_g; |
| 2715 | tmp = stb[{tid, sq_index}]; |
| 2716 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 2717 | end |
| 2718 | endfunction |
| 2719 | |
| 2720 | task Chk_block_store; |
| 2721 | reg [20:0] inst; |
| 2722 | reg [2:0] thid; |
| 2723 | begin |
| 2724 | thid = `SPC1.lsu_block_store_tid; |
| 2725 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 2726 | inst = bst_inst_data[`LSU_MON_INST]; |
| 2727 | |
| 2728 | if (~inst[`BLKST]) |
| 2729 | begin |
| 2730 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 2731 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 2732 | end |
| 2733 | end |
| 2734 | endtask |
| 2735 | |
| 2736 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 2737 | //the 8 stb entries from the previous blk store. |
| 2738 | |
| 2739 | task Set_block_store_parameters; |
| 2740 | reg [2:0] thid; |
| 2741 | begin |
| 2742 | |
| 2743 | thid = decode_tid(`SPC1.lsu.lsu_block_store_alloc[7:0]); |
| 2744 | if (lsu_bst_active[thid]) |
| 2745 | begin |
| 2746 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 2747 | end |
| 2748 | else |
| 2749 | begin |
| 2750 | lsu_bst_active[thid] = 1'b1; |
| 2751 | bst_active_thid = thid; |
| 2752 | if (`SPC1.lsu.fgu_fst_ecc_error_fx2) |
| 2753 | bst_fgu_err = 1'b1; |
| 2754 | else |
| 2755 | bst_fgu_err = 1'b0; |
| 2756 | end |
| 2757 | end |
| 2758 | endtask |
| 2759 | |
| 2760 | task Squash_store; |
| 2761 | reg [2:0] thid; |
| 2762 | reg [2:0] sq_index; |
| 2763 | reg [2:0] i; |
| 2764 | reg [204:0] tmp; |
| 2765 | reg [3:0] squash_cnt; |
| 2766 | reg [1:0] priv; |
| 2767 | |
| 2768 | begin |
| 2769 | thid = `SPC1.lsu_stberr_tid_g; |
| 2770 | sq_index = `SPC1.lsu_stberr_index_g; |
| 2771 | priv = `SPC1.lsu_stberr_priv_g; |
| 2772 | tmp = stb[{thid, sq_index}]; |
| 2773 | squash_cnt = 0; |
| 2774 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 2775 | |
| 2776 | st_priv[thid] = tmp[`ST_PRIV]; |
| 2777 | |
| 2778 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 2779 | //In that case iss_ptr won't be equal to sbdiou index. |
| 2780 | //if (sq_index != iss_ptr[thid]) |
| 2781 | //begin |
| 2782 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 2783 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 2784 | //end |
| 2785 | |
| 2786 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 2787 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 2788 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 2789 | //removing this chk. |
| 2790 | |
| 2791 | //if (tmp[`L2_ST_ISS]) |
| 2792 | //begin |
| 2793 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 2794 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 2795 | //end |
| 2796 | |
| 2797 | if (iss_ptr[thid] == wrptr[thid]) |
| 2798 | begin |
| 2799 | if (stb_valid[{thid, wrptr[thid]}]) |
| 2800 | squash_cnt = 8; |
| 2801 | else |
| 2802 | begin |
| 2803 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 2804 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 2805 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 2806 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 2807 | end |
| 2808 | end |
| 2809 | else |
| 2810 | begin |
| 2811 | if (iss_ptr[thid] < wrptr[thid]) |
| 2812 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 2813 | else if (iss_ptr[thid] > wrptr[thid]) |
| 2814 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 2815 | end |
| 2816 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 2817 | |
| 2818 | i = iss_ptr[thid]; |
| 2819 | |
| 2820 | while (squash_cnt) |
| 2821 | begin |
| 2822 | tmp = stb[{thid, i}]; |
| 2823 | tmp[`ST_SQUASH] = 1'b1; |
| 2824 | if (priv < tmp[`ST_PRIV]) |
| 2825 | begin |
| 2826 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 2827 | priv = tmp[`ST_PRIV]; |
| 2828 | end |
| 2829 | |
| 2830 | stb[{thid, i}] = tmp; |
| 2831 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 2832 | |
| 2833 | i = i + 1; |
| 2834 | squash_cnt = squash_cnt - 1'b1; |
| 2835 | end |
| 2836 | end |
| 2837 | endtask |
| 2838 | |
| 2839 | function [2:0] decode_tid; |
| 2840 | input [7:0] thid_encode; |
| 2841 | begin |
| 2842 | case (thid_encode) |
| 2843 | 8'h1: decode_tid = 3'b0; |
| 2844 | 8'h2: decode_tid = 3'h1; |
| 2845 | 8'h4: decode_tid = 3'h2; |
| 2846 | 8'h8: decode_tid = 3'h3; |
| 2847 | 8'h10: decode_tid = 3'h4; |
| 2848 | 8'h20: decode_tid = 3'h5; |
| 2849 | 8'h40: decode_tid = 3'h6; |
| 2850 | 8'h80: decode_tid = 3'h7; |
| 2851 | default: |
| 2852 | begin |
| 2853 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 2854 | end |
| 2855 | endcase |
| 2856 | end |
| 2857 | endfunction |
| 2858 | |
| 2859 | task Chk_ld_complete; |
| 2860 | input [2:0] thid; |
| 2861 | reg [`LD_Pend_Width] tmp; |
| 2862 | begin |
| 2863 | tmp = ld_pend_array[thid]; |
| 2864 | |
| 2865 | if (ld_valid[thid]) |
| 2866 | begin |
| 2867 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 2868 | begin |
| 2869 | DispPendReq(thid); |
| 2870 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 2871 | end |
| 2872 | ld_valid[thid] = 1'b0; |
| 2873 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 2874 | end |
| 2875 | |
| 2876 | tmp = last_inst_array[thid]; |
| 2877 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 2878 | end |
| 2879 | endtask |
| 2880 | |
| 2881 | task Chk_pcx_req_pkt; |
| 2882 | input [129:0] pcx_pkt; |
| 2883 | reg [2:0] thid; |
| 2884 | reg [`LD_Pend_Width] tmp, tmp1; |
| 2885 | reg [15:0] inst; |
| 2886 | reg [11*8:0] req; |
| 2887 | reg [39:0] addr; |
| 2888 | begin |
| 2889 | thid = pcx_pkt[`PCX_THR_ID]; |
| 2890 | tmp = ld_pend_array[thid]; |
| 2891 | inst = tmp[`LSU_MON_INST]; |
| 2892 | req = DispPCXReq(pcx_pkt); |
| 2893 | addr = pcx_pkt[`PCX_ADDR]; |
| 2894 | |
| 2895 | |
| 2896 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 2897 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 2898 | |
| 2899 | |
| 2900 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 2901 | begin |
| 2902 | if (~ld_valid[thid]) |
| 2903 | begin |
| 2904 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 2905 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 2906 | end |
| 2907 | if (~inst[`BLKLD]) |
| 2908 | begin |
| 2909 | if (tmp[`MEMOP_PA] != addr) |
| 2910 | begin |
| 2911 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 2912 | begin |
| 2913 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 2914 | end |
| 2915 | else |
| 2916 | begin |
| 2917 | DispPendReq(thid); |
| 2918 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 2919 | end |
| 2920 | end |
| 2921 | end |
| 2922 | end |
| 2923 | |
| 2924 | case (pcx_pkt[`PCX_RQTYP]) |
| 2925 | `PCX_LOAD: |
| 2926 | begin |
| 2927 | if (pcx_pkt[`PCX_PF]) |
| 2928 | begin |
| 2929 | if (~inst[`PREF]) |
| 2930 | begin |
| 2931 | DispPendReq(thid); |
| 2932 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 2933 | end |
| 2934 | if (pcx_pkt[`PCX_INV]) |
| 2935 | begin |
| 2936 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 2937 | end |
| 2938 | else |
| 2939 | begin |
| 2940 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 2941 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 2942 | end |
| 2943 | tmp[`L2_ISS] = 4'hF; |
| 2944 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 2945 | ld_pend_array[thid] = tmp; |
| 2946 | end |
| 2947 | else |
| 2948 | begin |
| 2949 | if (pcx_pkt[`PCX_INV]) |
| 2950 | begin |
| 2951 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 2952 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 2953 | end |
| 2954 | else |
| 2955 | begin |
| 2956 | Chk_req_load(pcx_pkt); |
| 2957 | end |
| 2958 | end |
| 2959 | end |
| 2960 | `PCX_CAS1, `PCX_CAS2: |
| 2961 | begin |
| 2962 | if (~inst[`CASA]) |
| 2963 | begin |
| 2964 | DispPendReq(thid); |
| 2965 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 2966 | end |
| 2967 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 2968 | begin |
| 2969 | tmp[`L2_ISS] = 4'hE; |
| 2970 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 2971 | ld_pend_array[thid] = tmp; |
| 2972 | end |
| 2973 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 2974 | begin |
| 2975 | tmp[`L2_ISS] = 4'hF; |
| 2976 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 2977 | ld_pend_array[thid] = tmp; |
| 2978 | chk_store_issue_to_pcx(pcx_pkt); |
| 2979 | end |
| 2980 | |
| 2981 | end |
| 2982 | `PCX_SWAP_LDSTUB: |
| 2983 | begin |
| 2984 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 2985 | begin |
| 2986 | DispPendReq(thid); |
| 2987 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 2988 | end |
| 2989 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 2990 | tmp[`L2_ISS] = 4'hF; |
| 2991 | ld_pend_array[thid] = tmp; |
| 2992 | |
| 2993 | chk_store_issue_to_pcx(pcx_pkt); |
| 2994 | end |
| 2995 | |
| 2996 | `PCX_STORE: |
| 2997 | begin |
| 2998 | chk_store_issue_to_pcx(pcx_pkt); |
| 2999 | end |
| 3000 | |
| 3001 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 3002 | endcase |
| 3003 | end |
| 3004 | endtask |
| 3005 | |
| 3006 | task Chk_cpx_response_pkt; |
| 3007 | input [145:0] cpx_pkt; |
| 3008 | reg [2:0] thid; |
| 3009 | begin |
| 3010 | thid = cpx_pkt[`CPX_THR_ID]; |
| 3011 | |
| 3012 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 3013 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 3014 | begin |
| 3015 | chk_ccx_ld_response(cpx_pkt); |
| 3016 | end |
| 3017 | |
| 3018 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 3019 | begin |
| 3020 | if (pf_cnt[thid] == 8'b0) |
| 3021 | begin |
| 3022 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 3023 | end |
| 3024 | else |
| 3025 | begin |
| 3026 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 3027 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 3028 | end |
| 3029 | end |
| 3030 | |
| 3031 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 3032 | chk_ccx_ld_response(cpx_pkt); |
| 3033 | |
| 3034 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 3035 | begin |
| 3036 | if (cpx_pkt[123]) //D pkt |
| 3037 | begin //{ |
| 3038 | if (cpx_pkt[120:118] != core_id) |
| 3039 | begin |
| 3040 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 3041 | end |
| 3042 | if (dcache_inv_cnt[thid] == 8'b0) |
| 3043 | begin |
| 3044 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 3045 | end |
| 3046 | else |
| 3047 | begin |
| 3048 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 3049 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 3050 | end |
| 3051 | end //} |
| 3052 | else if (cpx_pkt[124]) //I pkt |
| 3053 | begin |
| 3054 | if (cpx_pkt[120:118] != core_id) |
| 3055 | begin |
| 3056 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 3057 | end |
| 3058 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 3059 | end |
| 3060 | else if (cpx_pkt[124:123] == 2'b0) |
| 3061 | begin |
| 3062 | if (cpx_pkt[120:118] == core_id) |
| 3063 | begin |
| 3064 | chk_ccx_st_response(cpx_pkt); |
| 3065 | end |
| 3066 | else |
| 3067 | begin |
| 3068 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 3069 | end |
| 3070 | end |
| 3071 | end |
| 3072 | |
| 3073 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 3074 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 3075 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 3076 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 3077 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 3078 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 3079 | |
| 3080 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 3081 | begin |
| 3082 | chk_ccx_atm_response(cpx_pkt); |
| 3083 | end |
| 3084 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 3085 | begin |
| 3086 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 3087 | begin |
| 3088 | chk_ccx_atm_response(cpx_pkt); |
| 3089 | chk_ccx_st_response(cpx_pkt); |
| 3090 | end |
| 3091 | end |
| 3092 | |
| 3093 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 3094 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 3095 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 3096 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 3097 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 3098 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 3099 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 3100 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 3101 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 3102 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 3103 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 3104 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 3105 | |
| 3106 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 3107 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 3108 | |
| 3109 | default: |
| 3110 | begin |
| 3111 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 3112 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 3113 | |
| 3114 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 3115 | end |
| 3116 | |
| 3117 | endcase |
| 3118 | end |
| 3119 | endtask |
| 3120 | |
| 3121 | task chk_ccx_ld_response; |
| 3122 | input [145:0] cpx_pkt; |
| 3123 | reg [2:0] thid; |
| 3124 | reg [20:0] inst; |
| 3125 | reg [39:0] cpx_pa, inst_pa; |
| 3126 | reg [`LD_Pend_Width] tmp; |
| 3127 | reg [3:0] pkt_type; |
| 3128 | begin |
| 3129 | thid = cpx_pkt[`CPX_THR_ID]; |
| 3130 | tmp = ld_pend_array[thid]; |
| 3131 | inst = tmp[`LSU_MON_INST]; |
| 3132 | inst_pa = tmp[`MEMOP_PA]; |
| 3133 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 3134 | |
| 3135 | if (ld_valid[thid]) |
| 3136 | begin |
| 3137 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 3138 | /* |
| 3139 | if (inst_pa[39] != pkt_type[3]) |
| 3140 | begin |
| 3141 | DispPendReq(thid); |
| 3142 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 3143 | end |
| 3144 | */ |
| 3145 | |
| 3146 | if (inst[`BLKLD]) |
| 3147 | begin |
| 3148 | if (tmp[`L2_RESP] == 4'h0) |
| 3149 | begin |
| 3150 | tmp[`L2_RESP] = 4'h1; |
| 3151 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 3152 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 3153 | begin |
| 3154 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 3155 | end |
| 3156 | |
| 3157 | end |
| 3158 | else if (tmp[`L2_RESP] == 4'h1) |
| 3159 | begin |
| 3160 | tmp[`L2_RESP] = 4'h3; |
| 3161 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 3162 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 3163 | begin |
| 3164 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 3165 | end |
| 3166 | end |
| 3167 | else if (tmp[`L2_RESP] == 4'h3) |
| 3168 | begin |
| 3169 | tmp[`L2_RESP] = 4'h7; |
| 3170 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 3171 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 3172 | begin |
| 3173 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 3174 | end |
| 3175 | end |
| 3176 | else if (tmp[`L2_RESP] == 4'h7) |
| 3177 | begin |
| 3178 | tmp[`L2_RESP] = 4'hF; |
| 3179 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 3180 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 3181 | begin |
| 3182 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 3183 | end |
| 3184 | |
| 3185 | //is_blkld[thid] = 1'b1; |
| 3186 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 3187 | l2_blk_ld_errtype[thid] = `ND; |
| 3188 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 3189 | l2_blk_ld_errtype[thid] = `UE; |
| 3190 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 3191 | l2_blk_ld_errtype[thid] = `CE; |
| 3192 | else |
| 3193 | l2_blk_ld_errtype[thid] = `NE; |
| 3194 | end |
| 3195 | else |
| 3196 | begin |
| 3197 | DispPendReq(thid); |
| 3198 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 3199 | end |
| 3200 | end |
| 3201 | else if (Is_single_pcx_req_ld(inst)) |
| 3202 | begin |
| 3203 | //is_blkld[thid] = 1'b0; |
| 3204 | if (tmp[`L2_RESP] != 4'hE) |
| 3205 | begin |
| 3206 | DispPendReq(thid); |
| 3207 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 3208 | end |
| 3209 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 3210 | tmp[`L2_RESP] = 4'hF; |
| 3211 | end |
| 3212 | else |
| 3213 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 3214 | end |
| 3215 | else |
| 3216 | begin |
| 3217 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 3218 | end |
| 3219 | |
| 3220 | ld_pend_array[thid] = tmp; |
| 3221 | end |
| 3222 | endtask |
| 3223 | |
| 3224 | task chk_ccx_atm_response; |
| 3225 | input [145:0] cpx_pkt; |
| 3226 | reg [2:0] thid; |
| 3227 | reg [20:0] inst; |
| 3228 | reg [39:0] inst_pa; |
| 3229 | reg [`LD_Pend_Width] tmp; |
| 3230 | begin |
| 3231 | thid = cpx_pkt[`CPX_THR_ID]; |
| 3232 | tmp = ld_pend_array[thid]; |
| 3233 | inst = tmp[`LSU_MON_INST]; |
| 3234 | inst_pa = tmp[`MEMOP_PA]; |
| 3235 | |
| 3236 | if (~ld_valid[thid]) |
| 3237 | begin |
| 3238 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 3239 | begin |
| 3240 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 3241 | end |
| 3242 | else |
| 3243 | begin |
| 3244 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 3245 | end |
| 3246 | end |
| 3247 | else |
| 3248 | begin |
| 3249 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 3250 | begin |
| 3251 | DispPendReq(thid); |
| 3252 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 3253 | begin |
| 3254 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 3255 | end |
| 3256 | else |
| 3257 | begin |
| 3258 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 3259 | end |
| 3260 | end |
| 3261 | else |
| 3262 | begin |
| 3263 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 3264 | begin |
| 3265 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 3266 | end |
| 3267 | else |
| 3268 | begin |
| 3269 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 3270 | end |
| 3271 | |
| 3272 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 3273 | begin |
| 3274 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 3275 | else |
| 3276 | begin |
| 3277 | DispPendReq(thid); |
| 3278 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 3279 | end |
| 3280 | end |
| 3281 | else |
| 3282 | begin |
| 3283 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 3284 | else |
| 3285 | begin |
| 3286 | DispPendReq(thid); |
| 3287 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 3288 | end |
| 3289 | end |
| 3290 | end |
| 3291 | end |
| 3292 | ld_pend_array[thid] = tmp; |
| 3293 | end |
| 3294 | endtask |
| 3295 | |
| 3296 | task chk_ccx_st_response; |
| 3297 | input [145:0] cpx_pkt; |
| 3298 | reg [2:0] thid; |
| 3299 | reg [20:0] inst; |
| 3300 | reg [39:0] cpx_pa, inst_pa; |
| 3301 | reg [204:0] tmp; |
| 3302 | reg [3:0] pkt_type; |
| 3303 | begin |
| 3304 | thid = cpx_pkt[`CPX_THR_ID]; |
| 3305 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 3306 | inst = tmp[`LSU_MON_INST]; |
| 3307 | inst_pa = tmp[`MEMOP_PA]; |
| 3308 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 3309 | |
| 3310 | |
| 3311 | //is received. There could be some other store sitting in the STB at that time. |
| 3312 | |
| 3313 | //Chk for squash bit only for non-bis responses. |
| 3314 | |
| 3315 | |
| 3316 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 3317 | begin |
| 3318 | if (st_rmo_cnt[thid] == 0) |
| 3319 | begin |
| 3320 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 3321 | end |
| 3322 | else |
| 3323 | begin |
| 3324 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 3325 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 3326 | end |
| 3327 | end |
| 3328 | else |
| 3329 | begin |
| 3330 | if (tmp[`ST_SQUASH]) |
| 3331 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 3332 | |
| 3333 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 3334 | begin |
| 3335 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 3336 | end |
| 3337 | else |
| 3338 | begin |
| 3339 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 3340 | begin |
| 3341 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 3342 | end |
| 3343 | tmp[`L2_ACK] = 1'b1; |
| 3344 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 3345 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 3346 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 3347 | end |
| 3348 | end |
| 3349 | end |
| 3350 | endtask |
| 3351 | |
| 3352 | task Chk_req_load; |
| 3353 | input [129:0] pcx_pkt; |
| 3354 | reg [2:0] thid; |
| 3355 | reg [`LD_Pend_Width] tmp; |
| 3356 | reg [39:0] pcx_pa, inst_pa; |
| 3357 | reg [20:0] inst; |
| 3358 | reg [11*8:0] req; |
| 3359 | begin |
| 3360 | |
| 3361 | thid = pcx_pkt[`PCX_THR_ID]; |
| 3362 | tmp = ld_pend_array[thid]; |
| 3363 | inst = tmp[`LSU_MON_INST]; |
| 3364 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 3365 | inst_pa = tmp[`MEMOP_PA]; |
| 3366 | req = DispPCXReq(pcx_pkt); |
| 3367 | |
| 3368 | if (inst[`BLKLD]) |
| 3369 | begin |
| 3370 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 3371 | begin |
| 3372 | DispPendReq(thid); |
| 3373 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 3374 | end |
| 3375 | if (pcx_pa[5:0] == 6'b0) |
| 3376 | begin |
| 3377 | if (tmp[`L2_ISS] != 4'h0 ) |
| 3378 | begin |
| 3379 | DispPendReq(thid); |
| 3380 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 3381 | end |
| 3382 | else |
| 3383 | begin |
| 3384 | tmp[`L2_ISS] = 4'h1; |
| 3385 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 3386 | end |
| 3387 | |
| 3388 | end |
| 3389 | if (pcx_pa[5:0] == 6'h10) |
| 3390 | begin |
| 3391 | if (tmp[`L2_ISS] != 4'h1) |
| 3392 | begin |
| 3393 | DispPendReq(thid); |
| 3394 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 3395 | end |
| 3396 | else |
| 3397 | begin |
| 3398 | tmp[`L2_ISS] = 4'h3; |
| 3399 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 3400 | end |
| 3401 | end |
| 3402 | if (pcx_pa[5:0] == 6'h20) |
| 3403 | begin |
| 3404 | if (tmp[`L2_ISS] != 4'h3) |
| 3405 | begin |
| 3406 | DispPendReq(thid); |
| 3407 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 3408 | end |
| 3409 | else |
| 3410 | begin |
| 3411 | tmp[`L2_ISS] = 4'h7; |
| 3412 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 3413 | end |
| 3414 | end |
| 3415 | if (pcx_pa[5:0] == 6'h30) |
| 3416 | begin |
| 3417 | if (tmp[`L2_ISS] != 4'h7) |
| 3418 | begin |
| 3419 | DispPendReq(thid); |
| 3420 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 3421 | end |
| 3422 | else |
| 3423 | begin |
| 3424 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 3425 | tmp[`L2_ISS] = 4'hF; |
| 3426 | end |
| 3427 | end |
| 3428 | ld_pend_array[thid] = tmp; |
| 3429 | end |
| 3430 | else if (Is_single_pcx_req_ld(inst)) |
| 3431 | begin |
| 3432 | if (tmp[`L2_ISS] == 4'hF) |
| 3433 | begin |
| 3434 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 3435 | end |
| 3436 | else |
| 3437 | begin |
| 3438 | tmp[`L2_ISS] = 4'hF; |
| 3439 | ld_pend_array[thid] = tmp; |
| 3440 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 3441 | end |
| 3442 | end |
| 3443 | else |
| 3444 | begin |
| 3445 | DispPendReq(thid); |
| 3446 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 3447 | end |
| 3448 | end |
| 3449 | endtask |
| 3450 | |
| 3451 | |
| 3452 | function Is_single_pcx_req_ld; |
| 3453 | input [20:0] inst; |
| 3454 | begin |
| 3455 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 3456 | Is_single_pcx_req_ld = 1'b1; |
| 3457 | else |
| 3458 | Is_single_pcx_req_ld = 1'b0; |
| 3459 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 3460 | end |
| 3461 | endfunction |
| 3462 | |
| 3463 | |
| 3464 | function Is_trap; |
| 3465 | input [2:0]tid; |
| 3466 | |
| 3467 | begin |
| 3468 | Is_trap = 1'b0; |
| 3469 | case (`SPC1.lsu_trap_flush[7:0]) |
| 3470 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 3471 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 3472 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 3473 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 3474 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 3475 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 3476 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 3477 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 3478 | endcase |
| 3479 | end |
| 3480 | endfunction |
| 3481 | |
| 3482 | function [8*11:0] DispPCXReq; |
| 3483 | input [129:0] pcx_pkt; |
| 3484 | begin |
| 3485 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 3486 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 3487 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 3488 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 3489 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 3490 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 3491 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 3492 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 3493 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 3494 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 3495 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 3496 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 3497 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 3498 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 3499 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 3500 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 3501 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 3502 | default: |
| 3503 | begin |
| 3504 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 3505 | DispPCXReq = " "; |
| 3506 | end |
| 3507 | endcase |
| 3508 | end |
| 3509 | endfunction |
| 3510 | |
| 3511 | function IsExc; |
| 3512 | input [2:0] core_id; |
| 3513 | reg [21*8:0] DispExc; |
| 3514 | |
| 3515 | begin |
| 3516 | DispExc = 170'b0; |
| 3517 | IsExc = 1'b0; |
| 3518 | |
| 3519 | if (`SPC1.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 3520 | if (`SPC1.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 3521 | if (`SPC1.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 3522 | if (`SPC1.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 3523 | if (`SPC1.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 3524 | if (`SPC1.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 3525 | //if (`SPC1.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 3526 | if (`SPC1.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 3527 | if (`SPC1.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 3528 | if (`SPC1.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 3529 | if (`SPC1.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 3530 | if (`SPC1.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 3531 | if (`SPC1.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 3532 | if (`SPC1.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 3533 | //if (`SPC1.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 3534 | if (`SPC1.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 3535 | if (`SPC1.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 3536 | if (`SPC1.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 3537 | |
| 3538 | |
| 3539 | if (DispExc != 0) |
| 3540 | begin |
| 3541 | IsExc = 1'b1; |
| 3542 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 3543 | end |
| 3544 | |
| 3545 | end |
| 3546 | endfunction |
| 3547 | |
| 3548 | function Is_exu_error; |
| 3549 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 3550 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 3551 | reg err_b; |
| 3552 | reg err_m; |
| 3553 | |
| 3554 | begin |
| 3555 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC1.lsu_tlb_bypass_b)): |
| 3556 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC1.lsu_tlb_bypass_b)); |
| 3557 | |
| 3558 | err_m = (dec_lsu_tid_b[2] ? `SPC1.exu_ecc_m[1] : `SPC1.exu_ecc_m[0]) & `SPC1.lsu.dcc.twocycle_b; |
| 3559 | |
| 3560 | Is_exu_error = err_b | err_m; |
| 3561 | end |
| 3562 | endfunction |
| 3563 | |
| 3564 | /* |
| 3565 | task Insert_tlb_miss_info; |
| 3566 | reg [127:0] tmp; |
| 3567 | begin |
| 3568 | tmp = 128'b0; |
| 3569 | if (tlb_valid[dec_lsu_tid_b]) |
| 3570 | begin |
| 3571 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 3572 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 3573 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 3574 | end |
| 3575 | else |
| 3576 | begin |
| 3577 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 3578 | tmp[`INST_VA] = inst_pc_b; |
| 3579 | tmp[`MEMOP_VA] = vaddr_b; |
| 3580 | tmp[`INST] = inst_b; |
| 3581 | end |
| 3582 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 3583 | end |
| 3584 | endtask |
| 3585 | |
| 3586 | */ |
| 3587 | |
| 3588 | //problem with the signal. |
| 3589 | /* |
| 3590 | always @ (negedge `SPC1.l2clk) |
| 3591 | begin |
| 3592 | if (mmu_dtlb_reload_d2) |
| 3593 | Chk_dtlb_reload; |
| 3594 | end |
| 3595 | |
| 3596 | task Chk_dtlb_reload; |
| 3597 | reg [2:0] thid; |
| 3598 | reg [127:0] tmp; |
| 3599 | begin |
| 3600 | if (`SPC1.tlu_trap_pc_0_valid) |
| 3601 | thid = {1'b0, `SPC1.tlu_trap_0_tid}; |
| 3602 | else if (`SPC1.tlu_trap_pc_1_valid) |
| 3603 | thid = {1'b0, `SPC1.tlu_trap_1_tid}; |
| 3604 | else |
| 3605 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 3606 | |
| 3607 | if (~tlb_valid[thid]) |
| 3608 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 3609 | else |
| 3610 | begin |
| 3611 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 3612 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 3613 | tlb_valid[thid] = 1'b0; |
| 3614 | end |
| 3615 | end |
| 3616 | endtask |
| 3617 | */ |
| 3618 | |
| 3619 | task Insert_ld_miss_info; |
| 3620 | reg [`LD_Pend_Width] tmp; |
| 3621 | begin |
| 3622 | tmp = 213'b0; |
| 3623 | if (ld_valid[dec_lsu_tid_b]) |
| 3624 | begin |
| 3625 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 3626 | DispPendReq(dec_lsu_tid_b); |
| 3627 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 3628 | end |
| 3629 | else |
| 3630 | begin |
| 3631 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 3632 | tmp[`INST_VA] = inst_pc_b; |
| 3633 | tmp[`MEMOP_VA] = vaddr_b; |
| 3634 | tmp[`MEMOP_PA] = {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 3635 | tmp[`INST_ASI] = asi_b; |
| 3636 | |
| 3637 | if (lsu_inst_b[`BLKLD]) |
| 3638 | begin |
| 3639 | tmp[`L2_ISS] = 4'h0; |
| 3640 | tmp[`L2_RESP] = 4'h0; |
| 3641 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 3642 | end |
| 3643 | else |
| 3644 | begin |
| 3645 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 3646 | if (lsu_inst_b[`CASA]) |
| 3647 | tmp[`L2_ISS] = 4'hC; |
| 3648 | else |
| 3649 | tmp[`L2_ISS] = 4'hE; |
| 3650 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 3651 | tmp[`L2_RESP] = 4'hC; |
| 3652 | else |
| 3653 | tmp[`L2_RESP] = 4'hE; |
| 3654 | |
| 3655 | end |
| 3656 | |
| 3657 | tmp[`INST] = inst_b; |
| 3658 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 3659 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 3660 | end |
| 3661 | end |
| 3662 | endtask |
| 3663 | |
| 3664 | |
| 3665 | task Insert_in_last_inst_array; |
| 3666 | reg [135:0] tmp; |
| 3667 | begin |
| 3668 | tmp = 128'b0; |
| 3669 | tmp[`INST_VA] = inst_pc_b; |
| 3670 | tmp[`MEMOP_VA] = vaddr_b; |
| 3671 | tmp[`INST] = inst_b; |
| 3672 | tmp[135:128] = asi_b; |
| 3673 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 3674 | end |
| 3675 | endtask |
| 3676 | |
| 3677 | |
| 3678 | task DispPendReq; |
| 3679 | input [2:0] thid; |
| 3680 | reg [`LD_Pend_Width] tmp; |
| 3681 | begin |
| 3682 | |
| 3683 | tmp = ld_pend_array[thid]; |
| 3684 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 3685 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 3686 | end |
| 3687 | endtask |
| 3688 | |
| 3689 | task Disp_STB_entry; |
| 3690 | input [2:0] thid; |
| 3691 | input [2:0] ptr; |
| 3692 | reg [204:0] tmp; |
| 3693 | begin |
| 3694 | |
| 3695 | tmp = stb[{thid, ptr}]; |
| 3696 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 3697 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 3698 | end |
| 3699 | endtask |
| 3700 | |
| 3701 | /* |
| 3702 | |
| 3703 | task Disp_tlbmiss_pend_array_entry; |
| 3704 | input [2:0] thid; |
| 3705 | reg [127:0] tmp; |
| 3706 | begin |
| 3707 | tmp = tlbmiss_pend_array[thid]; |
| 3708 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 3709 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 3710 | |
| 3711 | end |
| 3712 | endtask |
| 3713 | |
| 3714 | */ |
| 3715 | task Disp_CPX_pkt; |
| 3716 | input [145:0] cpx_pkt; |
| 3717 | begin |
| 3718 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 3719 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 3720 | end |
| 3721 | endtask |
| 3722 | |
| 3723 | |
| 3724 | task Make_STB_data; |
| 3725 | reg [204:0] tmp; |
| 3726 | begin |
| 3727 | tmp = 0; |
| 3728 | tmp[`INST_VA] = inst_pc_b; |
| 3729 | tmp[`MEMOP_VA] = vaddr_b; |
| 3730 | tmp[`MEMOP_PA] = {`SPC1.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 3731 | tmp[`L2_ST_ISS] = 1'b0; |
| 3732 | tmp[`ASI_ST_ISS] = 1'b0; |
| 3733 | tmp[`L2_ACK] = 1'b0; |
| 3734 | tmp[`INST] = inst_b; |
| 3735 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 3736 | tmp[`ST_SQUASH] = 1'b0; |
| 3737 | tmp[`INST_ASI] = asi_b; |
| 3738 | if (`SPC1.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 3739 | tmp[`ST_PRIV] = `HPRIV; |
| 3740 | else if (`SPC1.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 3741 | tmp[`ST_PRIV] = `PRIV; |
| 3742 | else |
| 3743 | tmp[`ST_PRIV] = `USER; |
| 3744 | //bis_asi to io space is not rmo |
| 3745 | |
| 3746 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC1.lsu.tlb_pgnum[39]); |
| 3747 | stb_alloc_data <= tmp; |
| 3748 | end |
| 3749 | endtask |
| 3750 | |
| 3751 | task Insert_in_STB; |
| 3752 | input [195:0] store_data; |
| 3753 | input [2:0] thid; |
| 3754 | begin |
| 3755 | if (stb_full(thid)) |
| 3756 | begin |
| 3757 | //DispSTB(thid); |
| 3758 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 3759 | end |
| 3760 | else |
| 3761 | begin |
| 3762 | stb[{thid, wrptr[thid]}] = store_data; |
| 3763 | //Disp_STB_entry(thid, wrptr[thid]); |
| 3764 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 3765 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 3766 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 3767 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 3768 | end |
| 3769 | end |
| 3770 | endtask |
| 3771 | |
| 3772 | function stb_full; |
| 3773 | input [2:0] thid; |
| 3774 | begin |
| 3775 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 3776 | stb_full = 1'b1; |
| 3777 | else |
| 3778 | stb_full = 1'b0; |
| 3779 | end |
| 3780 | endfunction |
| 3781 | |
| 3782 | |
| 3783 | task Dealloc_STB; |
| 3784 | input [2:0] thid; |
| 3785 | reg [204:0] tmp; |
| 3786 | reg [20:0] lsu_inst; |
| 3787 | begin |
| 3788 | //thid = decode_tid(`SPC1.lsu_stb_dealloc); |
| 3789 | tmp = stb[{thid, rdptr[thid]}]; |
| 3790 | lsu_inst = tmp[`LSU_MON_INST]; |
| 3791 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 3792 | begin |
| 3793 | //DispSTB(thid); |
| 3794 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC1.lsu_stb_dealloc); |
| 3795 | end |
| 3796 | if (tmp[`L2_ST_ISS]) |
| 3797 | begin |
| 3798 | if (~tmp[`L2_ACK]) |
| 3799 | begin |
| 3800 | Disp_STB_entry(thid, rdptr[thid]); |
| 3801 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC1.lsu_stb_dealloc); |
| 3802 | end |
| 3803 | end |
| 3804 | else if (tmp[`ASI_ST_ISS]) |
| 3805 | begin |
| 3806 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 3807 | end |
| 3808 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 3809 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 3810 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 3811 | // and deallocated. |
| 3812 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 3813 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 3814 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 3815 | begin |
| 3816 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 3817 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 3818 | end |
| 3819 | else |
| 3820 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC1.lsu_stb_dealloc); |
| 3821 | |
| 3822 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 3823 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 3824 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 3825 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 3826 | /* |
| 3827 | if (tmp[`RMO]) |
| 3828 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 3829 | */ |
| 3830 | end |
| 3831 | endtask |
| 3832 | |
| 3833 | task Squash_STB; |
| 3834 | input [2:0] thid; |
| 3835 | reg [204:0] tmp; |
| 3836 | reg [3:0] squash_cnt; |
| 3837 | reg [2:0] i; |
| 3838 | begin |
| 3839 | squash_cnt = 4'b0; |
| 3840 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 3841 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 3842 | if (rdptr[thid] != iss_ptr[thid]) |
| 3843 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 3844 | |
| 3845 | if (iss_ptr[thid] == wrptr[thid]) |
| 3846 | begin |
| 3847 | if (stb_valid[{thid, wrptr[thid]}]) |
| 3848 | squash_cnt = 8; |
| 3849 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 3850 | * |
| 3851 | else |
| 3852 | begin |
| 3853 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 3854 | end |
| 3855 | */ |
| 3856 | end |
| 3857 | else |
| 3858 | begin |
| 3859 | if (iss_ptr[thid] < wrptr[thid]) |
| 3860 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 3861 | else if (iss_ptr[thid] > wrptr[thid]) |
| 3862 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 3863 | end |
| 3864 | |
| 3865 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 3866 | |
| 3867 | i = iss_ptr[thid]; |
| 3868 | |
| 3869 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 3870 | |
| 3871 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 3872 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 3873 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 3874 | |
| 3875 | while (squash_cnt) |
| 3876 | begin |
| 3877 | tmp = stb[{thid, i}]; |
| 3878 | if (~stb_valid[{thid, i}]) |
| 3879 | begin |
| 3880 | //DispSTB(thid); |
| 3881 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 3882 | end |
| 3883 | if (tmp[`L2_ST_ISS]) |
| 3884 | begin |
| 3885 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 3886 | end |
| 3887 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 3888 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 3889 | //set in the chkr which was causin it to fire. |
| 3890 | //if (~tmp[`ST_SQUASH]) |
| 3891 | //begin |
| 3892 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 3893 | //end |
| 3894 | stb_valid[{thid, i}] = 1'b0; |
| 3895 | |
| 3896 | i = i + 1; |
| 3897 | squash_cnt = squash_cnt - 1'b1; |
| 3898 | end |
| 3899 | |
| 3900 | end |
| 3901 | endtask |
| 3902 | |
| 3903 | task Chk_store; |
| 3904 | reg [2:0] thid; |
| 3905 | reg [47:0] addr; |
| 3906 | reg [3:0] i; |
| 3907 | reg [204:0] tmp; |
| 3908 | begin |
| 3909 | if ((bst_cnt > 0) && (`SPC1.lsu_stb_alloc == 8'b0)) |
| 3910 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 3911 | |
| 3912 | //For bst the stb is still written even though we have errors. |
| 3913 | //Stb is written in W stage. Howvere for first blk store helper |
| 3914 | //the err will be flagged by FGU in b stage. We can miss the |
| 3915 | // err signal if we don't sample in B. |
| 3916 | //for the last helper err will be signalled in B stage of last helper and at |
| 3917 | |
| 3918 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 3919 | bst_fgu_err = 1'b1; |
| 3920 | |
| 3921 | if (`SPC1.lsu_stb_alloc[7:0] != 8'b0) |
| 3922 | begin |
| 3923 | thid = decode_tid(`SPC1.lsu_stb_alloc[7:0]); |
| 3924 | if (store_alloc) |
| 3925 | begin |
| 3926 | if (thid != dec_lsu_tid_w) |
| 3927 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC1.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 3928 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 3929 | end |
| 3930 | else |
| 3931 | begin |
| 3932 | if (lsu_bst_active[thid]) |
| 3933 | begin |
| 3934 | if (bst_cnt == 0) |
| 3935 | begin |
| 3936 | bst_data = bst_inst_data; |
| 3937 | end |
| 3938 | else |
| 3939 | begin |
| 3940 | if (thid != bst_active_thid) |
| 3941 | begin |
| 3942 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC1.lsu_stb_alloc[7:0], bst_active_thid); |
| 3943 | end |
| 3944 | |
| 3945 | addr = bst_data[`MEMOP_VA]; |
| 3946 | |
| 3947 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 3948 | addr = bst_data[`MEMOP_PA]; |
| 3949 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 3950 | end |
| 3951 | bst_cnt = bst_cnt + 1; |
| 3952 | Insert_in_STB(bst_data, bst_active_thid); |
| 3953 | if (bst_cnt == 8) |
| 3954 | begin |
| 3955 | bst_cnt = 0; |
| 3956 | lsu_bst_active[thid] = 1'b0; |
| 3957 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 3958 | begin |
| 3959 | for (i = 0; i < 8; i=i+1) |
| 3960 | begin |
| 3961 | tmp = stb[{thid, i[2:0]}]; |
| 3962 | if (tmp[`ST_SQUASH]) |
| 3963 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 3964 | tmp[`ST_SQUASH] = 1'b1; |
| 3965 | stb[{thid, i[2:0]}] = tmp; |
| 3966 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 3967 | end |
| 3968 | end |
| 3969 | bst_fgu_err = 1'b0; |
| 3970 | end |
| 3971 | end |
| 3972 | else |
| 3973 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC1.lsu_stb_alloc[7:0]); |
| 3974 | |
| 3975 | end |
| 3976 | end |
| 3977 | else |
| 3978 | begin |
| 3979 | if (store_alloc) |
| 3980 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 3981 | end |
| 3982 | end |
| 3983 | endtask |
| 3984 | |
| 3985 | task Chk_st_on_ASI_ring; |
| 3986 | input ring; |
| 3987 | reg [2:0] thid; |
| 3988 | reg [7:0] asi; |
| 3989 | reg [47:0] addr, act_addr; |
| 3990 | reg [1:0] req_type; |
| 3991 | reg [204:0] tmp; |
| 3992 | |
| 3993 | begin |
| 3994 | if (ring == `LOCAL) |
| 3995 | thid =`SPC1.lsu_rngl_cdbus[58:56]; |
| 3996 | else |
| 3997 | thid =`SPC1.lsu_rngf_cdbus[58:56]; |
| 3998 | |
| 3999 | if (ring == `LOCAL) |
| 4000 | asi =`SPC1.lsu_rngl_cdbus[55:48]; |
| 4001 | else |
| 4002 | asi =`SPC1.lsu_rngf_cdbus[55:48]; |
| 4003 | |
| 4004 | if (ring == `LOCAL) |
| 4005 | addr =`SPC1.lsu_rngl_cdbus[47:0]; |
| 4006 | else |
| 4007 | addr =`SPC1.lsu_rngf_cdbus[47:0]; |
| 4008 | |
| 4009 | if (ring == `LOCAL) |
| 4010 | req_type =`SPC1.lsu_rngl_cdbus[61:60]; |
| 4011 | else |
| 4012 | req_type =`SPC1.lsu_rngf_cdbus[61:60]; |
| 4013 | |
| 4014 | |
| 4015 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 4016 | if (tmp[`ASI_ST_ISS]) |
| 4017 | begin |
| 4018 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4019 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 4020 | end |
| 4021 | |
| 4022 | if (tmp[`ST_SQUASH]) |
| 4023 | begin |
| 4024 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4025 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 4026 | end |
| 4027 | |
| 4028 | act_addr = tmp[`MEMOP_PA]; |
| 4029 | act_addr = {act_addr[39:3], 3'b0}; |
| 4030 | |
| 4031 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 4032 | //the address. |
| 4033 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 4034 | begin |
| 4035 | tmp[`ASI_ST_ISS] = 1'b1; |
| 4036 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 4037 | if (ring == `LOCAL) |
| 4038 | begin |
| 4039 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 4040 | end |
| 4041 | else |
| 4042 | begin |
| 4043 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 4044 | end |
| 4045 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 4046 | end |
| 4047 | else |
| 4048 | begin |
| 4049 | if (ring == `LOCAL) |
| 4050 | begin |
| 4051 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 4052 | end |
| 4053 | else |
| 4054 | begin |
| 4055 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 4056 | end |
| 4057 | end |
| 4058 | |
| 4059 | end |
| 4060 | endtask |
| 4061 | |
| 4062 | |
| 4063 | task chk_store_issue_to_pcx; |
| 4064 | input [129:0] pcx_pkt; |
| 4065 | reg [2:0] thid; |
| 4066 | reg [204:0] tmp; |
| 4067 | reg [20:0] inst; |
| 4068 | reg [39:0] pcx_pa, inst_pa; |
| 4069 | begin |
| 4070 | thid = pcx_pkt[`PCX_THR_ID]; |
| 4071 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 4072 | inst = tmp[`LSU_MON_INST]; |
| 4073 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 4074 | inst_pa = tmp[`MEMOP_PA]; |
| 4075 | |
| 4076 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 4077 | begin |
| 4078 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 4079 | end |
| 4080 | if (pcx_pkt[`PCX_INV]) |
| 4081 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 4082 | |
| 4083 | |
| 4084 | if (~inst[`ST]) |
| 4085 | begin |
| 4086 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4087 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4088 | end |
| 4089 | |
| 4090 | /* CONFIRM WITH MARK |
| 4091 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 4092 | begin |
| 4093 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4094 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 4095 | end |
| 4096 | */ |
| 4097 | //enhancement req 100146 |
| 4098 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 4099 | begin |
| 4100 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4101 | end |
| 4102 | |
| 4103 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 4104 | begin |
| 4105 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4106 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4107 | end |
| 4108 | |
| 4109 | if (tmp[`L2_ST_ISS]) |
| 4110 | begin |
| 4111 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4112 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4113 | end |
| 4114 | else |
| 4115 | tmp[`L2_ST_ISS] = 1'b1; |
| 4116 | |
| 4117 | if (tmp[`ST_SQUASH]) |
| 4118 | begin |
| 4119 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4120 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4121 | end |
| 4122 | |
| 4123 | if (tmp[`RMO]) |
| 4124 | begin |
| 4125 | if (~pcx_pkt[`PCX_BIS]) |
| 4126 | begin |
| 4127 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4128 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4129 | end |
| 4130 | if (tmp[`L2_ACK]) |
| 4131 | begin |
| 4132 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4133 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 4134 | end |
| 4135 | else |
| 4136 | begin |
| 4137 | tmp[`L2_ACK] = 1'b1; |
| 4138 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 4139 | //response seen from stub |
| 4140 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 4141 | end |
| 4142 | end |
| 4143 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 4144 | |
| 4145 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 4146 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 4147 | end |
| 4148 | endtask |
| 4149 | |
| 4150 | `ifdef INJ_STB_ERR_IN_CMP |
| 4151 | |
| 4152 | |
| 4153 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 4154 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 4155 | reg [204:0] err_tmp ; |
| 4156 | reg [20:0] err_inst; |
| 4157 | reg [44:0] cam_data; |
| 4158 | reg [5:0] err_bit; |
| 4159 | integer err_inj_cnt; |
| 4160 | reg cmp_stb_err_inj; |
| 4161 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 4162 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 4163 | |
| 4164 | initial |
| 4165 | begin |
| 4166 | cmp_stb_err_inj = 1'b0; |
| 4167 | |
| 4168 | cam_data = 45'b0; |
| 4169 | err_bit = 11; |
| 4170 | err_inj_cnt = 0; |
| 4171 | stb_err_inj = 0; |
| 4172 | if (("cmp_stb_err_inj_on")) |
| 4173 | cmp_stb_err_inj = 1'b1; |
| 4174 | else |
| 4175 | cmp_stb_err_inj = 1'b0; |
| 4176 | end |
| 4177 | |
| 4178 | always @ (negedge (`SPC1.l2clk & enabled & cmp_stb_err_inj)) |
| 4179 | begin //{ |
| 4180 | //valid stb ram rd for issue to pcx |
| 4181 | stb_err_inj = 1'b0; |
| 4182 | if (`SPC1.lsu.sbc.ram_rptr_vld_2 & `SPC1.lsu.sbc.st_pcx_rq_p3 & `SPC1.lsu.pic.pic_st_sel_p3) |
| 4183 | begin //{ |
| 4184 | err_tid = decode_tid(`SPC1.lsu.sbc.st_rq_sel_p3[7:0]); |
| 4185 | err_index = `SPC1.lsu.sbc.ram_rptr_d1; |
| 4186 | err_tmp = stb[{err_tid, err_index}]; |
| 4187 | err_inst = err_tmp[`LSU_MON_INST]; |
| 4188 | cam_data = `SPC1.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 4189 | err_priv = err_tmp[`ST_PRIV]; |
| 4190 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 4191 | if (err_inst[`CASA]) |
| 4192 | begin //{ |
| 4193 | err_inj_cnt = err_inj_cnt + 1; |
| 4194 | if (err_inj_cnt == 10) |
| 4195 | begin //{ |
| 4196 | case (err_bit) |
| 4197 | 11, 12: err_bit = err_bit + 1; |
| 4198 | 13: err_bit = 44; |
| 4199 | 44: err_bit = 11; |
| 4200 | endcase |
| 4201 | err_inj_cnt = 0; |
| 4202 | stb_err_inj = 1'b1; |
| 4203 | |
| 4204 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 4205 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 4206 | #1; |
| 4207 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 4208 | end //} |
| 4209 | end //} |
| 4210 | end //} |
| 4211 | if (stb_err_inj_d2) |
| 4212 | begin |
| 4213 | if (~`SPC1.lsu_sbapp_err_g) |
| 4214 | begin |
| 4215 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 4216 | end |
| 4217 | else |
| 4218 | begin |
| 4219 | if ((`SPC1.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 4220 | (`SPC1.lsu_stberr_index_g != stb_err_index_d2) || |
| 4221 | (`SPC1.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 4222 | begin |
| 4223 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 4224 | end |
| 4225 | end |
| 4226 | end |
| 4227 | else |
| 4228 | begin |
| 4229 | if (`SPC1.lsu_sbapp_err_g) |
| 4230 | begin |
| 4231 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC1.lsu_stberr_tid_g); |
| 4232 | end |
| 4233 | end |
| 4234 | |
| 4235 | end //} |
| 4236 | |
| 4237 | |
| 4238 | always @ (posedge (`SPC1.l2clk & enabled & cmp_stb_err_inj)) |
| 4239 | begin |
| 4240 | stb_err_inj_d1 <= stb_err_inj; |
| 4241 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 4242 | stb_err_tid_d1 <= err_tid; |
| 4243 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 4244 | stb_err_index_d1 <= err_index; |
| 4245 | stb_err_index_d2 <= stb_err_index_d1; |
| 4246 | stb_err_priv_d1 <= err_priv; |
| 4247 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 4248 | end |
| 4249 | |
| 4250 | `endif |
| 4251 | `endif |
| 4252 | `endif |
| 4253 | endmodule |
| 4254 | |
| 4255 | `endif |
| 4256 | `ifdef CORE_2 |
| 4257 | |
| 4258 | module lsu_mon_c2; |
| 4259 | `ifndef GATESIM |
| 4260 | |
| 4261 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 4262 | `ifndef NO_MONITORS |
| 4263 | |
| 4264 | reg imm_asi_vld_e; |
| 4265 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 4266 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 4267 | reg [1:0] exu_ecc_b; |
| 4268 | reg [1:0] exu_lsu_va_error_b; |
| 4269 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 4270 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 4271 | reg [31:0] inst_e, inst_m, inst_b; |
| 4272 | reg [47:0] vaddr_m, vaddr_b; |
| 4273 | reg [63:0] int_st_data_m, int_st_data_b; |
| 4274 | reg [63:0] fp_st_sata_fx2; |
| 4275 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 4276 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 4277 | |
| 4278 | reg [7:0] ld_valid; |
| 4279 | reg [7:0] tlb_valid; |
| 4280 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 4281 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 4282 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 4283 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 4284 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 4285 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 4286 | //the L2c. |
| 4287 | reg [63:0] stb_valid; |
| 4288 | reg [`STB_Pend_Width] stb[63:0]; |
| 4289 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 4290 | |
| 4291 | reg [7:0] pf_cnt[7:0]; |
| 4292 | reg [7:0] dcache_inv_cnt[7:0]; |
| 4293 | reg [7:0] st_rmo_cnt[7:0]; |
| 4294 | |
| 4295 | reg [55:0] print_inst; |
| 4296 | |
| 4297 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 4298 | |
| 4299 | reg [7:0] lsu_bst_active; |
| 4300 | reg store_alloc; |
| 4301 | reg [3:0] bst_cnt; |
| 4302 | reg [195:0] stb_alloc_data; |
| 4303 | reg [195:0] bst_data, bst_inst_data; |
| 4304 | reg [2:0] bst_active_thid; |
| 4305 | reg bst_fgu_err; |
| 4306 | |
| 4307 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 4308 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 4309 | //different types of err occur on blk ld helper returns |
| 4310 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 4311 | //stored in DFESR |
| 4312 | |
| 4313 | wire [2:0] core_id = 2; |
| 4314 | |
| 4315 | integer i; |
| 4316 | integer err_cnt; |
| 4317 | |
| 4318 | reg enabled; |
| 4319 | reg reset_in_middle; |
| 4320 | reg [7:0] finish_mask; |
| 4321 | |
| 4322 | initial |
| 4323 | begin |
| 4324 | enabled = 0; |
| 4325 | reset_in_middle = 0; |
| 4326 | ld_valid = 8'b0; |
| 4327 | lsu_inst_e = 0; |
| 4328 | tlb_valid = 8'b0; |
| 4329 | for (i = 0; i < 8; i = i+1) |
| 4330 | begin |
| 4331 | pf_cnt[i] = 0; |
| 4332 | dcache_inv_cnt[i] = 0; |
| 4333 | wrptr[i] = 0; |
| 4334 | rdptr[i] = 0; |
| 4335 | iss_ptr[i] = 0; |
| 4336 | ret_ptr[i] = 0; |
| 4337 | st_rmo_cnt[i] = 0; |
| 4338 | is_blkld[i] = 1'b0; |
| 4339 | st_priv[i] = 2'b0; |
| 4340 | l2_blk_ld_errtype[i] = 2'b0; |
| 4341 | end |
| 4342 | lsu_bst_active = 8'b0; |
| 4343 | store_alloc = 1'b0; |
| 4344 | bst_cnt = 4'b0; |
| 4345 | stb_valid = 64'b0; |
| 4346 | |
| 4347 | // avoid time zero ugliness. jp |
| 4348 | //@(posedge `SPC0.l2clk); |
| 4349 | //@(negedge `SPC0.l2clk); |
| 4350 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 4351 | |
| 4352 | case (core_id) |
| 4353 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 4354 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 4355 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 4356 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 4357 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 4358 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 4359 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 4360 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 4361 | endcase |
| 4362 | end |
| 4363 | |
| 4364 | always @ (`TOP.in_reset) |
| 4365 | begin |
| 4366 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 4367 | begin |
| 4368 | enabled = 1'b1; |
| 4369 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 4370 | end |
| 4371 | |
| 4372 | |
| 4373 | if (`TOP.in_reset & enabled) |
| 4374 | begin |
| 4375 | reset_in_middle = 1'b1; |
| 4376 | enabled = 1'b0; |
| 4377 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 4378 | end |
| 4379 | end |
| 4380 | |
| 4381 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 4382 | begin //{ |
| 4383 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 4384 | begin //{ |
| 4385 | for (i = 0; i < 8; i=i+1) |
| 4386 | begin |
| 4387 | if (ld_valid[i]) |
| 4388 | begin |
| 4389 | DispPendReq(i); |
| 4390 | end |
| 4391 | end |
| 4392 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 4393 | end //} |
| 4394 | if (|stb_valid[63:0]) |
| 4395 | begin //{ |
| 4396 | err_cnt = 0; |
| 4397 | for (i = 0; i < 64; i=i+1) |
| 4398 | begin |
| 4399 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 4400 | begin |
| 4401 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 4402 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 4403 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 4404 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 4405 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 4406 | //of simualation. |
| 4407 | if (~is_squash_bit_set(i[5:0])) |
| 4408 | begin |
| 4409 | err_cnt = err_cnt + 1; |
| 4410 | Disp_STB_entry(i[5:3],i[2:0]); |
| 4411 | end |
| 4412 | end |
| 4413 | end |
| 4414 | if (err_cnt) |
| 4415 | begin |
| 4416 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 4417 | end |
| 4418 | end //} |
| 4419 | err_cnt = 0; |
| 4420 | for (i = 0; i < 8; i=i+1) |
| 4421 | begin //{ |
| 4422 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 4423 | begin |
| 4424 | err_cnt = 1; |
| 4425 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 4426 | end |
| 4427 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 4428 | begin |
| 4429 | err_cnt = 1; |
| 4430 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 4431 | end |
| 4432 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 4433 | begin |
| 4434 | err_cnt = 1; |
| 4435 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 4436 | end |
| 4437 | end //} |
| 4438 | if (err_cnt) |
| 4439 | begin |
| 4440 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 4441 | end |
| 4442 | end //} |
| 4443 | |
| 4444 | function is_squash_bit_set; |
| 4445 | input [5:0] index; |
| 4446 | reg [204:0] tmp; |
| 4447 | begin |
| 4448 | tmp = stb[index]; |
| 4449 | if (tmp[`ST_SQUASH]) |
| 4450 | is_squash_bit_set = 1'b1; |
| 4451 | else |
| 4452 | is_squash_bit_set = 1'b0; |
| 4453 | end |
| 4454 | endfunction |
| 4455 | |
| 4456 | |
| 4457 | always @ (negedge (`SPC2.l2clk & enabled)) |
| 4458 | begin //{ |
| 4459 | |
| 4460 | asi_e = `SPC2.lsu.dcc.dcc_asi_e[7:0]; |
| 4461 | |
| 4462 | lsu_inst_e[`LD] <= `SPC2.dec_ld_inst_e; |
| 4463 | lsu_inst_e[`ST] <= `SPC2.dec_st_inst_e; |
| 4464 | lsu_inst_e[`FP] <= `SPC2.dec_fpldst_inst_e; |
| 4465 | lsu_inst_e[`PREF] <= `SPC2.dec_pref_inst_e; |
| 4466 | lsu_inst_e[`SWAP] <= `SPC2.dec_swap_inst_e; |
| 4467 | lsu_inst_e[`CASA] <= `SPC2.dec_casa_inst_e; |
| 4468 | lsu_inst_e[`LDSTUB] <= `SPC2.dec_ldstub_inst_e; |
| 4469 | lsu_inst_e[`FLUSH] <= `SPC2.dec_flush_inst_e; |
| 4470 | lsu_inst_e[`MEMBAR] <= `SPC2.dec_memstbar_inst_e; |
| 4471 | lsu_inst_e[`LDD] <= `SPC2.dec_ld_inst_e & `SPC2.dec_ldst_dbl_e & ~`SPC2.dec_fpldst_inst_e; |
| 4472 | lsu_inst_e[`STD] <= `SPC2.dec_st_inst_e & `SPC2.dec_ldst_dbl_e & ~`SPC2.lsu.dec_fpldst_inst_e; |
| 4473 | |
| 4474 | lsu_inst_e[`BLKLD] <= `SPC2.dec_ld_inst_e & `SPC2.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 4475 | lsu_inst_e[`BLKST] <= `SPC2.dec_st_inst_e & `SPC2.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 4476 | lsu_inst_e[`QLD] <= `SPC2.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 4477 | lsu_inst_e[`ASR_RD_WR] <= `SPC2.dec_sr_inst_e & (`SPC2.dec_ld_inst_e | `SPC2.dec_st_inst_e); |
| 4478 | lsu_inst_e[`PR_RD_WR] <= `SPC2.dec_pr_inst_e & (`SPC2.dec_ld_inst_e | `SPC2.dec_st_inst_e); |
| 4479 | lsu_inst_e[`HPR_RD_WR] <= `SPC2.dec_hpr_inst_e & (`SPC2.dec_ld_inst_e | `SPC2.dec_st_inst_e); |
| 4480 | lsu_inst_e[`FSR_RD_WR] <= `SPC2.dec_fsr_ldst_e & (`SPC2.dec_ld_inst_e | `SPC2.dec_st_inst_e); |
| 4481 | end //} |
| 4482 | |
| 4483 | always @ (posedge (`SPC2.l2clk & enabled)) |
| 4484 | begin //{ |
| 4485 | dec_tg0_inst_d <= `SPC2.dec.ded0.decode_mux[31:0]; |
| 4486 | dec_tg1_inst_d <= `SPC2.dec.ded1.decode_mux[31:0]; |
| 4487 | imm_asi_vld_e <= `SPC2.lsu.dec_imm_asi_vld_d; |
| 4488 | |
| 4489 | imm_asi_e <= `SPC2.lsu.dec_imm_asi_d; |
| 4490 | dec_altspace_e <= `SPC2.dec_altspace_d; |
| 4491 | dec_altspace_m <= dec_altspace_e; |
| 4492 | dec_altspace_b <= dec_altspace_m; |
| 4493 | |
| 4494 | exu_ecc_b <= `SPC2.exu_ecc_m; |
| 4495 | exu_lsu_va_error_b <= `SPC2.exu_lsu_va_error_m; |
| 4496 | |
| 4497 | dec_lsu_tid_e <= `SPC2.dec_lsu_tg_d ? {1'b1, `SPC2.dec_lsu_tid1_d} : {1'b0, `SPC2.dec_lsu_tid0_d}; |
| 4498 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 4499 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 4500 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 4501 | |
| 4502 | inst_pc_e <= `SPC2.dec_lsu_tg_d ? {`SPC2.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC2.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 4503 | inst_pc_m <= inst_pc_e; |
| 4504 | inst_pc_b <= inst_pc_m; |
| 4505 | inst_pc_w <= inst_pc_b; |
| 4506 | |
| 4507 | inst_e <= `SPC2.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 4508 | inst_m <= inst_e; |
| 4509 | inst_b <= inst_m; |
| 4510 | |
| 4511 | vaddr_m <= `SPC2.exu_lsu_address_e; |
| 4512 | vaddr_b <= vaddr_m; |
| 4513 | |
| 4514 | int_st_data_m <= `SPC2.exu_lsu_store_data_e; |
| 4515 | int_st_data_b <= int_st_data_m; |
| 4516 | fp_st_sata_fx2 <= `SPC2.fgu_lsu_fst_data_fx1; |
| 4517 | |
| 4518 | mmu_dtlb_reload_d1 <= `SPC2.mmu_dtlb_reload; |
| 4519 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 4520 | |
| 4521 | //pcx_thid_d1 <= `SPC2.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 4522 | lsu_inst_m <= lsu_inst_e; |
| 4523 | lsu_inst_b <= lsu_inst_m; |
| 4524 | |
| 4525 | asi_m <= asi_e; |
| 4526 | asi_b <= asi_m; |
| 4527 | end //} |
| 4528 | |
| 4529 | function Is_blk_asi; |
| 4530 | input [7:0] asi; |
| 4531 | begin |
| 4532 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 4533 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 4534 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 4535 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 4536 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 4537 | end |
| 4538 | endfunction |
| 4539 | |
| 4540 | function Is_qld_asi; |
| 4541 | input [7:0] asi; |
| 4542 | begin |
| 4543 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 4544 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 4545 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 4546 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 4547 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 4548 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 4549 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 4550 | end |
| 4551 | endfunction |
| 4552 | |
| 4553 | function Is_bis_asi; |
| 4554 | input [7:0] asi; |
| 4555 | begin |
| 4556 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 4557 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 4558 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 4559 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 4560 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 4561 | end |
| 4562 | endfunction |
| 4563 | |
| 4564 | always @ (negedge (`SPC2.l2clk & enabled)) |
| 4565 | begin //{ |
| 4566 | Chk_store; |
| 4567 | store_alloc = 1'b0; |
| 4568 | if (lsu_inst_m != 0) |
| 4569 | begin |
| 4570 | if (`SPC2.dec_flush_lm) |
| 4571 | begin |
| 4572 | lsu_inst_m <= 0; |
| 4573 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 4574 | end |
| 4575 | end |
| 4576 | |
| 4577 | if (lsu_inst_b != 0) |
| 4578 | begin //{ |
| 4579 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 4580 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 4581 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 4582 | else print_inst = ""; |
| 4583 | |
| 4584 | if (`SPC2.dec_flush_lb) |
| 4585 | begin |
| 4586 | lsu_inst_b <= 0; |
| 4587 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 4588 | end |
| 4589 | else if (`SPC2.tlu_flush_lsu_b) |
| 4590 | begin |
| 4591 | lsu_inst_b <= 0; |
| 4592 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 4593 | end |
| 4594 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 4595 | //casa shd be killed. |
| 4596 | //This function will also chk for errors on 2nd cycle. |
| 4597 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 4598 | begin |
| 4599 | lsu_inst_b <= 0; |
| 4600 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 4601 | end |
| 4602 | else if ((`SPC2.fgu_cecc_fx2 || `SPC2.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 4603 | begin |
| 4604 | lsu_inst_b <= 0; |
| 4605 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 4606 | end |
| 4607 | else if (IsExc(core_id)) |
| 4608 | lsu_inst_b <= 0; |
| 4609 | else if (!`SPC2.lsu_tlb_miss_b_) |
| 4610 | begin |
| 4611 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 4612 | //Insert_tlb_miss_info; |
| 4613 | end |
| 4614 | else |
| 4615 | begin //{ |
| 4616 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 4617 | //an exception tlu anyway tells the front end to flush itself there is |
| 4618 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 4619 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 4620 | //handles it when it is reissued by the front end. |
| 4621 | |
| 4622 | if (`SPC2.lsu_tlb_bypass_b) |
| 4623 | begin |
| 4624 | if (`SPC2.lsu_sync != 8'b0) |
| 4625 | begin |
| 4626 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 4627 | end |
| 4628 | else |
| 4629 | begin |
| 4630 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 4631 | end |
| 4632 | end |
| 4633 | else |
| 4634 | begin |
| 4635 | if (`SPC2.lsu_sync != 8'b0) |
| 4636 | begin |
| 4637 | if (lsu_inst_b[`ST]) |
| 4638 | begin |
| 4639 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 4640 | end |
| 4641 | else |
| 4642 | begin |
| 4643 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 4644 | end |
| 4645 | end |
| 4646 | else |
| 4647 | begin |
| 4648 | if (lsu_inst_b[`ST]) |
| 4649 | begin |
| 4650 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 4651 | end |
| 4652 | else |
| 4653 | begin |
| 4654 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 4655 | end |
| 4656 | end |
| 4657 | end |
| 4658 | |
| 4659 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 4660 | begin //{ |
| 4661 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC2.lsu.stb_cam_hit) |
| 4662 | begin |
| 4663 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 4664 | end |
| 4665 | end //} |
| 4666 | |
| 4667 | if (lsu_inst_b[`LD]) |
| 4668 | Insert_ld_miss_info; |
| 4669 | |
| 4670 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 4671 | begin |
| 4672 | Make_STB_data; |
| 4673 | store_alloc = 1'b1; |
| 4674 | end |
| 4675 | Insert_in_last_inst_array; |
| 4676 | |
| 4677 | if (`SPC2.lsu_trap_flush[7:0]) |
| 4678 | begin |
| 4679 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC2.lsu_trap_flush[7:0])); |
| 4680 | end |
| 4681 | end //} |
| 4682 | end //} |
| 4683 | end //} |
| 4684 | |
| 4685 | //STB ue testing: |
| 4686 | //This is how we test squashing of stores by LSU_mon: |
| 4687 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 4688 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 4689 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 4690 | //The squashed stores are deallocated when either a block_store_kill is |
| 4691 | //asserted or dealloc signals are asserted by the LSU. |
| 4692 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 4693 | //all the pending stores in the IFU. It means the when block_store_kill |
| 4694 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 4695 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 4696 | //the sbdiou signal to TLU. |
| 4697 | |
| 4698 | |
| 4699 | always @ (negedge (`SPC2.l2clk & enabled)) |
| 4700 | begin |
| 4701 | if (`SPC2.lsu_l15_valid & `SPC2.lsu.spc_pcx_data_pa[129]) |
| 4702 | Chk_pcx_req_pkt(`SPC2.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 4703 | if ((`SPC2.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC2.lsu_rngl_cdbus[59]) |
| 4704 | Chk_st_on_ASI_ring(`LOCAL); |
| 4705 | |
| 4706 | if ((`SPC2.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC2.lsu_rngf_cdbus[59]) |
| 4707 | Chk_st_on_ASI_ring(`FAST); |
| 4708 | |
| 4709 | //if (`SPC2.l15_lsu_valid) |
| 4710 | //Chk_cpx_response_pkt({`SPC2.l15_lsu_valid, `SPC2.l15_lsu_cpkt[17:13],`SPC2.l15_lsu_cpkt[11:0],`SPC2.l15_spc_data1[127:0]}); |
| 4711 | |
| 4712 | if (`SPC2.cpx_spc_data_cx[145]) |
| 4713 | Chk_cpx_response_pkt(`SPC2.cpx_spc_data_cx); |
| 4714 | |
| 4715 | if (`SPC2.lsu_complete[7:0] != 8'b0) |
| 4716 | begin |
| 4717 | if (`SPC2.lsu_complete[0]) Chk_ld_complete(0); |
| 4718 | if (`SPC2.lsu_complete[1]) Chk_ld_complete(1); |
| 4719 | if (`SPC2.lsu_complete[2]) Chk_ld_complete(2); |
| 4720 | if (`SPC2.lsu_complete[3]) Chk_ld_complete(3); |
| 4721 | if (`SPC2.lsu_complete[4]) Chk_ld_complete(4); |
| 4722 | if (`SPC2.lsu_complete[5]) Chk_ld_complete(5); |
| 4723 | if (`SPC2.lsu_complete[6]) Chk_ld_complete(6); |
| 4724 | if (`SPC2.lsu_complete[7]) Chk_ld_complete(7); |
| 4725 | end |
| 4726 | |
| 4727 | if (`SPC2.lsu_block_store_kill[7:0] != 8'b0) |
| 4728 | begin |
| 4729 | if (`SPC2.lsu_block_store_kill[0]) Squash_STB(0); |
| 4730 | if (`SPC2.lsu_block_store_kill[1]) Squash_STB(1); |
| 4731 | if (`SPC2.lsu_block_store_kill[2]) Squash_STB(2); |
| 4732 | if (`SPC2.lsu_block_store_kill[3]) Squash_STB(3); |
| 4733 | if (`SPC2.lsu_block_store_kill[4]) Squash_STB(4); |
| 4734 | if (`SPC2.lsu_block_store_kill[5]) Squash_STB(5); |
| 4735 | if (`SPC2.lsu_block_store_kill[6]) Squash_STB(6); |
| 4736 | if (`SPC2.lsu_block_store_kill[7]) Squash_STB(7); |
| 4737 | end |
| 4738 | |
| 4739 | if (`SPC2.lsu_stb_dealloc[7:0] != 8'b0) |
| 4740 | begin |
| 4741 | if (`SPC2.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 4742 | if (`SPC2.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 4743 | if (`SPC2.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 4744 | if (`SPC2.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 4745 | if (`SPC2.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 4746 | if (`SPC2.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 4747 | if (`SPC2.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 4748 | if (`SPC2.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 4749 | end |
| 4750 | |
| 4751 | if (`SPC2.lsu_block_store_stall) |
| 4752 | Chk_block_store; |
| 4753 | |
| 4754 | if (`SPC2.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 4755 | Set_block_store_parameters; |
| 4756 | |
| 4757 | if (`SPC2.lsu_sbdiou_err_g || `SPC2.lsu_sbapp_err_g) |
| 4758 | Squash_store; |
| 4759 | |
| 4760 | if (`SPC2.lsu_stb_flush_g) |
| 4761 | st_priv[`SPC2.lsu_stberr_tid_g] = get_priv_on_flush(`SPC2.lsu_stberr_tid_g); |
| 4762 | end |
| 4763 | |
| 4764 | function [1:0] get_priv_on_flush; |
| 4765 | input [2:0] tid; |
| 4766 | reg [2:0] sq_index; |
| 4767 | reg [204:0] tmp; |
| 4768 | |
| 4769 | begin |
| 4770 | sq_index = `SPC2.lsu_stberr_index_g; |
| 4771 | tmp = stb[{tid, sq_index}]; |
| 4772 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 4773 | end |
| 4774 | endfunction |
| 4775 | |
| 4776 | task Chk_block_store; |
| 4777 | reg [20:0] inst; |
| 4778 | reg [2:0] thid; |
| 4779 | begin |
| 4780 | thid = `SPC2.lsu_block_store_tid; |
| 4781 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 4782 | inst = bst_inst_data[`LSU_MON_INST]; |
| 4783 | |
| 4784 | if (~inst[`BLKST]) |
| 4785 | begin |
| 4786 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 4787 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 4788 | end |
| 4789 | end |
| 4790 | endtask |
| 4791 | |
| 4792 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 4793 | //the 8 stb entries from the previous blk store. |
| 4794 | |
| 4795 | task Set_block_store_parameters; |
| 4796 | reg [2:0] thid; |
| 4797 | begin |
| 4798 | |
| 4799 | thid = decode_tid(`SPC2.lsu.lsu_block_store_alloc[7:0]); |
| 4800 | if (lsu_bst_active[thid]) |
| 4801 | begin |
| 4802 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 4803 | end |
| 4804 | else |
| 4805 | begin |
| 4806 | lsu_bst_active[thid] = 1'b1; |
| 4807 | bst_active_thid = thid; |
| 4808 | if (`SPC2.lsu.fgu_fst_ecc_error_fx2) |
| 4809 | bst_fgu_err = 1'b1; |
| 4810 | else |
| 4811 | bst_fgu_err = 1'b0; |
| 4812 | end |
| 4813 | end |
| 4814 | endtask |
| 4815 | |
| 4816 | task Squash_store; |
| 4817 | reg [2:0] thid; |
| 4818 | reg [2:0] sq_index; |
| 4819 | reg [2:0] i; |
| 4820 | reg [204:0] tmp; |
| 4821 | reg [3:0] squash_cnt; |
| 4822 | reg [1:0] priv; |
| 4823 | |
| 4824 | begin |
| 4825 | thid = `SPC2.lsu_stberr_tid_g; |
| 4826 | sq_index = `SPC2.lsu_stberr_index_g; |
| 4827 | priv = `SPC2.lsu_stberr_priv_g; |
| 4828 | tmp = stb[{thid, sq_index}]; |
| 4829 | squash_cnt = 0; |
| 4830 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 4831 | |
| 4832 | st_priv[thid] = tmp[`ST_PRIV]; |
| 4833 | |
| 4834 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 4835 | //In that case iss_ptr won't be equal to sbdiou index. |
| 4836 | //if (sq_index != iss_ptr[thid]) |
| 4837 | //begin |
| 4838 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 4839 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 4840 | //end |
| 4841 | |
| 4842 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 4843 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 4844 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 4845 | //removing this chk. |
| 4846 | |
| 4847 | //if (tmp[`L2_ST_ISS]) |
| 4848 | //begin |
| 4849 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 4850 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 4851 | //end |
| 4852 | |
| 4853 | if (iss_ptr[thid] == wrptr[thid]) |
| 4854 | begin |
| 4855 | if (stb_valid[{thid, wrptr[thid]}]) |
| 4856 | squash_cnt = 8; |
| 4857 | else |
| 4858 | begin |
| 4859 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 4860 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 4861 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 4862 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 4863 | end |
| 4864 | end |
| 4865 | else |
| 4866 | begin |
| 4867 | if (iss_ptr[thid] < wrptr[thid]) |
| 4868 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 4869 | else if (iss_ptr[thid] > wrptr[thid]) |
| 4870 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 4871 | end |
| 4872 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 4873 | |
| 4874 | i = iss_ptr[thid]; |
| 4875 | |
| 4876 | while (squash_cnt) |
| 4877 | begin |
| 4878 | tmp = stb[{thid, i}]; |
| 4879 | tmp[`ST_SQUASH] = 1'b1; |
| 4880 | if (priv < tmp[`ST_PRIV]) |
| 4881 | begin |
| 4882 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 4883 | priv = tmp[`ST_PRIV]; |
| 4884 | end |
| 4885 | |
| 4886 | stb[{thid, i}] = tmp; |
| 4887 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 4888 | |
| 4889 | i = i + 1; |
| 4890 | squash_cnt = squash_cnt - 1'b1; |
| 4891 | end |
| 4892 | end |
| 4893 | endtask |
| 4894 | |
| 4895 | function [2:0] decode_tid; |
| 4896 | input [7:0] thid_encode; |
| 4897 | begin |
| 4898 | case (thid_encode) |
| 4899 | 8'h1: decode_tid = 3'b0; |
| 4900 | 8'h2: decode_tid = 3'h1; |
| 4901 | 8'h4: decode_tid = 3'h2; |
| 4902 | 8'h8: decode_tid = 3'h3; |
| 4903 | 8'h10: decode_tid = 3'h4; |
| 4904 | 8'h20: decode_tid = 3'h5; |
| 4905 | 8'h40: decode_tid = 3'h6; |
| 4906 | 8'h80: decode_tid = 3'h7; |
| 4907 | default: |
| 4908 | begin |
| 4909 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 4910 | end |
| 4911 | endcase |
| 4912 | end |
| 4913 | endfunction |
| 4914 | |
| 4915 | task Chk_ld_complete; |
| 4916 | input [2:0] thid; |
| 4917 | reg [`LD_Pend_Width] tmp; |
| 4918 | begin |
| 4919 | tmp = ld_pend_array[thid]; |
| 4920 | |
| 4921 | if (ld_valid[thid]) |
| 4922 | begin |
| 4923 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 4924 | begin |
| 4925 | DispPendReq(thid); |
| 4926 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 4927 | end |
| 4928 | ld_valid[thid] = 1'b0; |
| 4929 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 4930 | end |
| 4931 | |
| 4932 | tmp = last_inst_array[thid]; |
| 4933 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 4934 | end |
| 4935 | endtask |
| 4936 | |
| 4937 | task Chk_pcx_req_pkt; |
| 4938 | input [129:0] pcx_pkt; |
| 4939 | reg [2:0] thid; |
| 4940 | reg [`LD_Pend_Width] tmp, tmp1; |
| 4941 | reg [15:0] inst; |
| 4942 | reg [11*8:0] req; |
| 4943 | reg [39:0] addr; |
| 4944 | begin |
| 4945 | thid = pcx_pkt[`PCX_THR_ID]; |
| 4946 | tmp = ld_pend_array[thid]; |
| 4947 | inst = tmp[`LSU_MON_INST]; |
| 4948 | req = DispPCXReq(pcx_pkt); |
| 4949 | addr = pcx_pkt[`PCX_ADDR]; |
| 4950 | |
| 4951 | |
| 4952 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 4953 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 4954 | |
| 4955 | |
| 4956 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 4957 | begin |
| 4958 | if (~ld_valid[thid]) |
| 4959 | begin |
| 4960 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 4961 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 4962 | end |
| 4963 | if (~inst[`BLKLD]) |
| 4964 | begin |
| 4965 | if (tmp[`MEMOP_PA] != addr) |
| 4966 | begin |
| 4967 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 4968 | begin |
| 4969 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 4970 | end |
| 4971 | else |
| 4972 | begin |
| 4973 | DispPendReq(thid); |
| 4974 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 4975 | end |
| 4976 | end |
| 4977 | end |
| 4978 | end |
| 4979 | |
| 4980 | case (pcx_pkt[`PCX_RQTYP]) |
| 4981 | `PCX_LOAD: |
| 4982 | begin |
| 4983 | if (pcx_pkt[`PCX_PF]) |
| 4984 | begin |
| 4985 | if (~inst[`PREF]) |
| 4986 | begin |
| 4987 | DispPendReq(thid); |
| 4988 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 4989 | end |
| 4990 | if (pcx_pkt[`PCX_INV]) |
| 4991 | begin |
| 4992 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 4993 | end |
| 4994 | else |
| 4995 | begin |
| 4996 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 4997 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 4998 | end |
| 4999 | tmp[`L2_ISS] = 4'hF; |
| 5000 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 5001 | ld_pend_array[thid] = tmp; |
| 5002 | end |
| 5003 | else |
| 5004 | begin |
| 5005 | if (pcx_pkt[`PCX_INV]) |
| 5006 | begin |
| 5007 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5008 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 5009 | end |
| 5010 | else |
| 5011 | begin |
| 5012 | Chk_req_load(pcx_pkt); |
| 5013 | end |
| 5014 | end |
| 5015 | end |
| 5016 | `PCX_CAS1, `PCX_CAS2: |
| 5017 | begin |
| 5018 | if (~inst[`CASA]) |
| 5019 | begin |
| 5020 | DispPendReq(thid); |
| 5021 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 5022 | end |
| 5023 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 5024 | begin |
| 5025 | tmp[`L2_ISS] = 4'hE; |
| 5026 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5027 | ld_pend_array[thid] = tmp; |
| 5028 | end |
| 5029 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 5030 | begin |
| 5031 | tmp[`L2_ISS] = 4'hF; |
| 5032 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5033 | ld_pend_array[thid] = tmp; |
| 5034 | chk_store_issue_to_pcx(pcx_pkt); |
| 5035 | end |
| 5036 | |
| 5037 | end |
| 5038 | `PCX_SWAP_LDSTUB: |
| 5039 | begin |
| 5040 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 5041 | begin |
| 5042 | DispPendReq(thid); |
| 5043 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 5044 | end |
| 5045 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 5046 | tmp[`L2_ISS] = 4'hF; |
| 5047 | ld_pend_array[thid] = tmp; |
| 5048 | |
| 5049 | chk_store_issue_to_pcx(pcx_pkt); |
| 5050 | end |
| 5051 | |
| 5052 | `PCX_STORE: |
| 5053 | begin |
| 5054 | chk_store_issue_to_pcx(pcx_pkt); |
| 5055 | end |
| 5056 | |
| 5057 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 5058 | endcase |
| 5059 | end |
| 5060 | endtask |
| 5061 | |
| 5062 | task Chk_cpx_response_pkt; |
| 5063 | input [145:0] cpx_pkt; |
| 5064 | reg [2:0] thid; |
| 5065 | begin |
| 5066 | thid = cpx_pkt[`CPX_THR_ID]; |
| 5067 | |
| 5068 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 5069 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 5070 | begin |
| 5071 | chk_ccx_ld_response(cpx_pkt); |
| 5072 | end |
| 5073 | |
| 5074 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 5075 | begin |
| 5076 | if (pf_cnt[thid] == 8'b0) |
| 5077 | begin |
| 5078 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 5079 | end |
| 5080 | else |
| 5081 | begin |
| 5082 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 5083 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 5084 | end |
| 5085 | end |
| 5086 | |
| 5087 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 5088 | chk_ccx_ld_response(cpx_pkt); |
| 5089 | |
| 5090 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 5091 | begin |
| 5092 | if (cpx_pkt[123]) //D pkt |
| 5093 | begin //{ |
| 5094 | if (cpx_pkt[120:118] != core_id) |
| 5095 | begin |
| 5096 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 5097 | end |
| 5098 | if (dcache_inv_cnt[thid] == 8'b0) |
| 5099 | begin |
| 5100 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 5101 | end |
| 5102 | else |
| 5103 | begin |
| 5104 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 5105 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 5106 | end |
| 5107 | end //} |
| 5108 | else if (cpx_pkt[124]) //I pkt |
| 5109 | begin |
| 5110 | if (cpx_pkt[120:118] != core_id) |
| 5111 | begin |
| 5112 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 5113 | end |
| 5114 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 5115 | end |
| 5116 | else if (cpx_pkt[124:123] == 2'b0) |
| 5117 | begin |
| 5118 | if (cpx_pkt[120:118] == core_id) |
| 5119 | begin |
| 5120 | chk_ccx_st_response(cpx_pkt); |
| 5121 | end |
| 5122 | else |
| 5123 | begin |
| 5124 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 5125 | end |
| 5126 | end |
| 5127 | end |
| 5128 | |
| 5129 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 5130 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 5131 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 5132 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 5133 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 5134 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 5135 | |
| 5136 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 5137 | begin |
| 5138 | chk_ccx_atm_response(cpx_pkt); |
| 5139 | end |
| 5140 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 5141 | begin |
| 5142 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 5143 | begin |
| 5144 | chk_ccx_atm_response(cpx_pkt); |
| 5145 | chk_ccx_st_response(cpx_pkt); |
| 5146 | end |
| 5147 | end |
| 5148 | |
| 5149 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 5150 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 5151 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 5152 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 5153 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 5154 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 5155 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 5156 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 5157 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 5158 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 5159 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 5160 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 5161 | |
| 5162 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 5163 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 5164 | |
| 5165 | default: |
| 5166 | begin |
| 5167 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 5168 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 5169 | |
| 5170 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 5171 | end |
| 5172 | |
| 5173 | endcase |
| 5174 | end |
| 5175 | endtask |
| 5176 | |
| 5177 | task chk_ccx_ld_response; |
| 5178 | input [145:0] cpx_pkt; |
| 5179 | reg [2:0] thid; |
| 5180 | reg [20:0] inst; |
| 5181 | reg [39:0] cpx_pa, inst_pa; |
| 5182 | reg [`LD_Pend_Width] tmp; |
| 5183 | reg [3:0] pkt_type; |
| 5184 | begin |
| 5185 | thid = cpx_pkt[`CPX_THR_ID]; |
| 5186 | tmp = ld_pend_array[thid]; |
| 5187 | inst = tmp[`LSU_MON_INST]; |
| 5188 | inst_pa = tmp[`MEMOP_PA]; |
| 5189 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 5190 | |
| 5191 | if (ld_valid[thid]) |
| 5192 | begin |
| 5193 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 5194 | /* |
| 5195 | if (inst_pa[39] != pkt_type[3]) |
| 5196 | begin |
| 5197 | DispPendReq(thid); |
| 5198 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 5199 | end |
| 5200 | */ |
| 5201 | |
| 5202 | if (inst[`BLKLD]) |
| 5203 | begin |
| 5204 | if (tmp[`L2_RESP] == 4'h0) |
| 5205 | begin |
| 5206 | tmp[`L2_RESP] = 4'h1; |
| 5207 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 5208 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 5209 | begin |
| 5210 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 5211 | end |
| 5212 | |
| 5213 | end |
| 5214 | else if (tmp[`L2_RESP] == 4'h1) |
| 5215 | begin |
| 5216 | tmp[`L2_RESP] = 4'h3; |
| 5217 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 5218 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 5219 | begin |
| 5220 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 5221 | end |
| 5222 | end |
| 5223 | else if (tmp[`L2_RESP] == 4'h3) |
| 5224 | begin |
| 5225 | tmp[`L2_RESP] = 4'h7; |
| 5226 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 5227 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 5228 | begin |
| 5229 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 5230 | end |
| 5231 | end |
| 5232 | else if (tmp[`L2_RESP] == 4'h7) |
| 5233 | begin |
| 5234 | tmp[`L2_RESP] = 4'hF; |
| 5235 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 5236 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 5237 | begin |
| 5238 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 5239 | end |
| 5240 | |
| 5241 | //is_blkld[thid] = 1'b1; |
| 5242 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 5243 | l2_blk_ld_errtype[thid] = `ND; |
| 5244 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 5245 | l2_blk_ld_errtype[thid] = `UE; |
| 5246 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 5247 | l2_blk_ld_errtype[thid] = `CE; |
| 5248 | else |
| 5249 | l2_blk_ld_errtype[thid] = `NE; |
| 5250 | end |
| 5251 | else |
| 5252 | begin |
| 5253 | DispPendReq(thid); |
| 5254 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 5255 | end |
| 5256 | end |
| 5257 | else if (Is_single_pcx_req_ld(inst)) |
| 5258 | begin |
| 5259 | //is_blkld[thid] = 1'b0; |
| 5260 | if (tmp[`L2_RESP] != 4'hE) |
| 5261 | begin |
| 5262 | DispPendReq(thid); |
| 5263 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 5264 | end |
| 5265 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 5266 | tmp[`L2_RESP] = 4'hF; |
| 5267 | end |
| 5268 | else |
| 5269 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 5270 | end |
| 5271 | else |
| 5272 | begin |
| 5273 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 5274 | end |
| 5275 | |
| 5276 | ld_pend_array[thid] = tmp; |
| 5277 | end |
| 5278 | endtask |
| 5279 | |
| 5280 | task chk_ccx_atm_response; |
| 5281 | input [145:0] cpx_pkt; |
| 5282 | reg [2:0] thid; |
| 5283 | reg [20:0] inst; |
| 5284 | reg [39:0] inst_pa; |
| 5285 | reg [`LD_Pend_Width] tmp; |
| 5286 | begin |
| 5287 | thid = cpx_pkt[`CPX_THR_ID]; |
| 5288 | tmp = ld_pend_array[thid]; |
| 5289 | inst = tmp[`LSU_MON_INST]; |
| 5290 | inst_pa = tmp[`MEMOP_PA]; |
| 5291 | |
| 5292 | if (~ld_valid[thid]) |
| 5293 | begin |
| 5294 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 5295 | begin |
| 5296 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 5297 | end |
| 5298 | else |
| 5299 | begin |
| 5300 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 5301 | end |
| 5302 | end |
| 5303 | else |
| 5304 | begin |
| 5305 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 5306 | begin |
| 5307 | DispPendReq(thid); |
| 5308 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 5309 | begin |
| 5310 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 5311 | end |
| 5312 | else |
| 5313 | begin |
| 5314 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 5315 | end |
| 5316 | end |
| 5317 | else |
| 5318 | begin |
| 5319 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 5320 | begin |
| 5321 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 5322 | end |
| 5323 | else |
| 5324 | begin |
| 5325 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 5326 | end |
| 5327 | |
| 5328 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 5329 | begin |
| 5330 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 5331 | else |
| 5332 | begin |
| 5333 | DispPendReq(thid); |
| 5334 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 5335 | end |
| 5336 | end |
| 5337 | else |
| 5338 | begin |
| 5339 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 5340 | else |
| 5341 | begin |
| 5342 | DispPendReq(thid); |
| 5343 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 5344 | end |
| 5345 | end |
| 5346 | end |
| 5347 | end |
| 5348 | ld_pend_array[thid] = tmp; |
| 5349 | end |
| 5350 | endtask |
| 5351 | |
| 5352 | task chk_ccx_st_response; |
| 5353 | input [145:0] cpx_pkt; |
| 5354 | reg [2:0] thid; |
| 5355 | reg [20:0] inst; |
| 5356 | reg [39:0] cpx_pa, inst_pa; |
| 5357 | reg [204:0] tmp; |
| 5358 | reg [3:0] pkt_type; |
| 5359 | begin |
| 5360 | thid = cpx_pkt[`CPX_THR_ID]; |
| 5361 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 5362 | inst = tmp[`LSU_MON_INST]; |
| 5363 | inst_pa = tmp[`MEMOP_PA]; |
| 5364 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 5365 | |
| 5366 | |
| 5367 | //is received. There could be some other store sitting in the STB at that time. |
| 5368 | |
| 5369 | //Chk for squash bit only for non-bis responses. |
| 5370 | |
| 5371 | |
| 5372 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 5373 | begin |
| 5374 | if (st_rmo_cnt[thid] == 0) |
| 5375 | begin |
| 5376 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 5377 | end |
| 5378 | else |
| 5379 | begin |
| 5380 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 5381 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 5382 | end |
| 5383 | end |
| 5384 | else |
| 5385 | begin |
| 5386 | if (tmp[`ST_SQUASH]) |
| 5387 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 5388 | |
| 5389 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 5390 | begin |
| 5391 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 5392 | end |
| 5393 | else |
| 5394 | begin |
| 5395 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 5396 | begin |
| 5397 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 5398 | end |
| 5399 | tmp[`L2_ACK] = 1'b1; |
| 5400 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 5401 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 5402 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 5403 | end |
| 5404 | end |
| 5405 | end |
| 5406 | endtask |
| 5407 | |
| 5408 | task Chk_req_load; |
| 5409 | input [129:0] pcx_pkt; |
| 5410 | reg [2:0] thid; |
| 5411 | reg [`LD_Pend_Width] tmp; |
| 5412 | reg [39:0] pcx_pa, inst_pa; |
| 5413 | reg [20:0] inst; |
| 5414 | reg [11*8:0] req; |
| 5415 | begin |
| 5416 | |
| 5417 | thid = pcx_pkt[`PCX_THR_ID]; |
| 5418 | tmp = ld_pend_array[thid]; |
| 5419 | inst = tmp[`LSU_MON_INST]; |
| 5420 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 5421 | inst_pa = tmp[`MEMOP_PA]; |
| 5422 | req = DispPCXReq(pcx_pkt); |
| 5423 | |
| 5424 | if (inst[`BLKLD]) |
| 5425 | begin |
| 5426 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 5427 | begin |
| 5428 | DispPendReq(thid); |
| 5429 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 5430 | end |
| 5431 | if (pcx_pa[5:0] == 6'b0) |
| 5432 | begin |
| 5433 | if (tmp[`L2_ISS] != 4'h0 ) |
| 5434 | begin |
| 5435 | DispPendReq(thid); |
| 5436 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 5437 | end |
| 5438 | else |
| 5439 | begin |
| 5440 | tmp[`L2_ISS] = 4'h1; |
| 5441 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5442 | end |
| 5443 | |
| 5444 | end |
| 5445 | if (pcx_pa[5:0] == 6'h10) |
| 5446 | begin |
| 5447 | if (tmp[`L2_ISS] != 4'h1) |
| 5448 | begin |
| 5449 | DispPendReq(thid); |
| 5450 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 5451 | end |
| 5452 | else |
| 5453 | begin |
| 5454 | tmp[`L2_ISS] = 4'h3; |
| 5455 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5456 | end |
| 5457 | end |
| 5458 | if (pcx_pa[5:0] == 6'h20) |
| 5459 | begin |
| 5460 | if (tmp[`L2_ISS] != 4'h3) |
| 5461 | begin |
| 5462 | DispPendReq(thid); |
| 5463 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 5464 | end |
| 5465 | else |
| 5466 | begin |
| 5467 | tmp[`L2_ISS] = 4'h7; |
| 5468 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5469 | end |
| 5470 | end |
| 5471 | if (pcx_pa[5:0] == 6'h30) |
| 5472 | begin |
| 5473 | if (tmp[`L2_ISS] != 4'h7) |
| 5474 | begin |
| 5475 | DispPendReq(thid); |
| 5476 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 5477 | end |
| 5478 | else |
| 5479 | begin |
| 5480 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5481 | tmp[`L2_ISS] = 4'hF; |
| 5482 | end |
| 5483 | end |
| 5484 | ld_pend_array[thid] = tmp; |
| 5485 | end |
| 5486 | else if (Is_single_pcx_req_ld(inst)) |
| 5487 | begin |
| 5488 | if (tmp[`L2_ISS] == 4'hF) |
| 5489 | begin |
| 5490 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 5491 | end |
| 5492 | else |
| 5493 | begin |
| 5494 | tmp[`L2_ISS] = 4'hF; |
| 5495 | ld_pend_array[thid] = tmp; |
| 5496 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 5497 | end |
| 5498 | end |
| 5499 | else |
| 5500 | begin |
| 5501 | DispPendReq(thid); |
| 5502 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 5503 | end |
| 5504 | end |
| 5505 | endtask |
| 5506 | |
| 5507 | |
| 5508 | function Is_single_pcx_req_ld; |
| 5509 | input [20:0] inst; |
| 5510 | begin |
| 5511 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 5512 | Is_single_pcx_req_ld = 1'b1; |
| 5513 | else |
| 5514 | Is_single_pcx_req_ld = 1'b0; |
| 5515 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 5516 | end |
| 5517 | endfunction |
| 5518 | |
| 5519 | |
| 5520 | function Is_trap; |
| 5521 | input [2:0]tid; |
| 5522 | |
| 5523 | begin |
| 5524 | Is_trap = 1'b0; |
| 5525 | case (`SPC2.lsu_trap_flush[7:0]) |
| 5526 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 5527 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 5528 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 5529 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 5530 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 5531 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 5532 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 5533 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 5534 | endcase |
| 5535 | end |
| 5536 | endfunction |
| 5537 | |
| 5538 | function [8*11:0] DispPCXReq; |
| 5539 | input [129:0] pcx_pkt; |
| 5540 | begin |
| 5541 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 5542 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 5543 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 5544 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 5545 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 5546 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 5547 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 5548 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 5549 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 5550 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 5551 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 5552 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 5553 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 5554 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 5555 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 5556 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 5557 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 5558 | default: |
| 5559 | begin |
| 5560 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 5561 | DispPCXReq = " "; |
| 5562 | end |
| 5563 | endcase |
| 5564 | end |
| 5565 | endfunction |
| 5566 | |
| 5567 | function IsExc; |
| 5568 | input [2:0] core_id; |
| 5569 | reg [21*8:0] DispExc; |
| 5570 | |
| 5571 | begin |
| 5572 | DispExc = 170'b0; |
| 5573 | IsExc = 1'b0; |
| 5574 | |
| 5575 | if (`SPC2.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 5576 | if (`SPC2.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 5577 | if (`SPC2.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 5578 | if (`SPC2.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 5579 | if (`SPC2.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 5580 | if (`SPC2.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 5581 | //if (`SPC2.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 5582 | if (`SPC2.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 5583 | if (`SPC2.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 5584 | if (`SPC2.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 5585 | if (`SPC2.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 5586 | if (`SPC2.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 5587 | if (`SPC2.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 5588 | if (`SPC2.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 5589 | //if (`SPC2.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 5590 | if (`SPC2.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 5591 | if (`SPC2.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 5592 | if (`SPC2.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 5593 | |
| 5594 | |
| 5595 | if (DispExc != 0) |
| 5596 | begin |
| 5597 | IsExc = 1'b1; |
| 5598 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 5599 | end |
| 5600 | |
| 5601 | end |
| 5602 | endfunction |
| 5603 | |
| 5604 | function Is_exu_error; |
| 5605 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 5606 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 5607 | reg err_b; |
| 5608 | reg err_m; |
| 5609 | |
| 5610 | begin |
| 5611 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC2.lsu_tlb_bypass_b)): |
| 5612 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC2.lsu_tlb_bypass_b)); |
| 5613 | |
| 5614 | err_m = (dec_lsu_tid_b[2] ? `SPC2.exu_ecc_m[1] : `SPC2.exu_ecc_m[0]) & `SPC2.lsu.dcc.twocycle_b; |
| 5615 | |
| 5616 | Is_exu_error = err_b | err_m; |
| 5617 | end |
| 5618 | endfunction |
| 5619 | |
| 5620 | /* |
| 5621 | task Insert_tlb_miss_info; |
| 5622 | reg [127:0] tmp; |
| 5623 | begin |
| 5624 | tmp = 128'b0; |
| 5625 | if (tlb_valid[dec_lsu_tid_b]) |
| 5626 | begin |
| 5627 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 5628 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 5629 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 5630 | end |
| 5631 | else |
| 5632 | begin |
| 5633 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 5634 | tmp[`INST_VA] = inst_pc_b; |
| 5635 | tmp[`MEMOP_VA] = vaddr_b; |
| 5636 | tmp[`INST] = inst_b; |
| 5637 | end |
| 5638 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 5639 | end |
| 5640 | endtask |
| 5641 | |
| 5642 | */ |
| 5643 | |
| 5644 | //problem with the signal. |
| 5645 | /* |
| 5646 | always @ (negedge `SPC2.l2clk) |
| 5647 | begin |
| 5648 | if (mmu_dtlb_reload_d2) |
| 5649 | Chk_dtlb_reload; |
| 5650 | end |
| 5651 | |
| 5652 | task Chk_dtlb_reload; |
| 5653 | reg [2:0] thid; |
| 5654 | reg [127:0] tmp; |
| 5655 | begin |
| 5656 | if (`SPC2.tlu_trap_pc_0_valid) |
| 5657 | thid = {1'b0, `SPC2.tlu_trap_0_tid}; |
| 5658 | else if (`SPC2.tlu_trap_pc_1_valid) |
| 5659 | thid = {1'b0, `SPC2.tlu_trap_1_tid}; |
| 5660 | else |
| 5661 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 5662 | |
| 5663 | if (~tlb_valid[thid]) |
| 5664 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 5665 | else |
| 5666 | begin |
| 5667 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 5668 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 5669 | tlb_valid[thid] = 1'b0; |
| 5670 | end |
| 5671 | end |
| 5672 | endtask |
| 5673 | */ |
| 5674 | |
| 5675 | task Insert_ld_miss_info; |
| 5676 | reg [`LD_Pend_Width] tmp; |
| 5677 | begin |
| 5678 | tmp = 213'b0; |
| 5679 | if (ld_valid[dec_lsu_tid_b]) |
| 5680 | begin |
| 5681 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 5682 | DispPendReq(dec_lsu_tid_b); |
| 5683 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 5684 | end |
| 5685 | else |
| 5686 | begin |
| 5687 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 5688 | tmp[`INST_VA] = inst_pc_b; |
| 5689 | tmp[`MEMOP_VA] = vaddr_b; |
| 5690 | tmp[`MEMOP_PA] = {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 5691 | tmp[`INST_ASI] = asi_b; |
| 5692 | |
| 5693 | if (lsu_inst_b[`BLKLD]) |
| 5694 | begin |
| 5695 | tmp[`L2_ISS] = 4'h0; |
| 5696 | tmp[`L2_RESP] = 4'h0; |
| 5697 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 5698 | end |
| 5699 | else |
| 5700 | begin |
| 5701 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 5702 | if (lsu_inst_b[`CASA]) |
| 5703 | tmp[`L2_ISS] = 4'hC; |
| 5704 | else |
| 5705 | tmp[`L2_ISS] = 4'hE; |
| 5706 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 5707 | tmp[`L2_RESP] = 4'hC; |
| 5708 | else |
| 5709 | tmp[`L2_RESP] = 4'hE; |
| 5710 | |
| 5711 | end |
| 5712 | |
| 5713 | tmp[`INST] = inst_b; |
| 5714 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 5715 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 5716 | end |
| 5717 | end |
| 5718 | endtask |
| 5719 | |
| 5720 | |
| 5721 | task Insert_in_last_inst_array; |
| 5722 | reg [135:0] tmp; |
| 5723 | begin |
| 5724 | tmp = 128'b0; |
| 5725 | tmp[`INST_VA] = inst_pc_b; |
| 5726 | tmp[`MEMOP_VA] = vaddr_b; |
| 5727 | tmp[`INST] = inst_b; |
| 5728 | tmp[135:128] = asi_b; |
| 5729 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 5730 | end |
| 5731 | endtask |
| 5732 | |
| 5733 | |
| 5734 | task DispPendReq; |
| 5735 | input [2:0] thid; |
| 5736 | reg [`LD_Pend_Width] tmp; |
| 5737 | begin |
| 5738 | |
| 5739 | tmp = ld_pend_array[thid]; |
| 5740 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 5741 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 5742 | end |
| 5743 | endtask |
| 5744 | |
| 5745 | task Disp_STB_entry; |
| 5746 | input [2:0] thid; |
| 5747 | input [2:0] ptr; |
| 5748 | reg [204:0] tmp; |
| 5749 | begin |
| 5750 | |
| 5751 | tmp = stb[{thid, ptr}]; |
| 5752 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 5753 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 5754 | end |
| 5755 | endtask |
| 5756 | |
| 5757 | /* |
| 5758 | |
| 5759 | task Disp_tlbmiss_pend_array_entry; |
| 5760 | input [2:0] thid; |
| 5761 | reg [127:0] tmp; |
| 5762 | begin |
| 5763 | tmp = tlbmiss_pend_array[thid]; |
| 5764 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 5765 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 5766 | |
| 5767 | end |
| 5768 | endtask |
| 5769 | |
| 5770 | */ |
| 5771 | task Disp_CPX_pkt; |
| 5772 | input [145:0] cpx_pkt; |
| 5773 | begin |
| 5774 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 5775 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 5776 | end |
| 5777 | endtask |
| 5778 | |
| 5779 | |
| 5780 | task Make_STB_data; |
| 5781 | reg [204:0] tmp; |
| 5782 | begin |
| 5783 | tmp = 0; |
| 5784 | tmp[`INST_VA] = inst_pc_b; |
| 5785 | tmp[`MEMOP_VA] = vaddr_b; |
| 5786 | tmp[`MEMOP_PA] = {`SPC2.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 5787 | tmp[`L2_ST_ISS] = 1'b0; |
| 5788 | tmp[`ASI_ST_ISS] = 1'b0; |
| 5789 | tmp[`L2_ACK] = 1'b0; |
| 5790 | tmp[`INST] = inst_b; |
| 5791 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 5792 | tmp[`ST_SQUASH] = 1'b0; |
| 5793 | tmp[`INST_ASI] = asi_b; |
| 5794 | if (`SPC2.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 5795 | tmp[`ST_PRIV] = `HPRIV; |
| 5796 | else if (`SPC2.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 5797 | tmp[`ST_PRIV] = `PRIV; |
| 5798 | else |
| 5799 | tmp[`ST_PRIV] = `USER; |
| 5800 | //bis_asi to io space is not rmo |
| 5801 | |
| 5802 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC2.lsu.tlb_pgnum[39]); |
| 5803 | stb_alloc_data <= tmp; |
| 5804 | end |
| 5805 | endtask |
| 5806 | |
| 5807 | task Insert_in_STB; |
| 5808 | input [195:0] store_data; |
| 5809 | input [2:0] thid; |
| 5810 | begin |
| 5811 | if (stb_full(thid)) |
| 5812 | begin |
| 5813 | //DispSTB(thid); |
| 5814 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 5815 | end |
| 5816 | else |
| 5817 | begin |
| 5818 | stb[{thid, wrptr[thid]}] = store_data; |
| 5819 | //Disp_STB_entry(thid, wrptr[thid]); |
| 5820 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 5821 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 5822 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 5823 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 5824 | end |
| 5825 | end |
| 5826 | endtask |
| 5827 | |
| 5828 | function stb_full; |
| 5829 | input [2:0] thid; |
| 5830 | begin |
| 5831 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 5832 | stb_full = 1'b1; |
| 5833 | else |
| 5834 | stb_full = 1'b0; |
| 5835 | end |
| 5836 | endfunction |
| 5837 | |
| 5838 | |
| 5839 | task Dealloc_STB; |
| 5840 | input [2:0] thid; |
| 5841 | reg [204:0] tmp; |
| 5842 | reg [20:0] lsu_inst; |
| 5843 | begin |
| 5844 | //thid = decode_tid(`SPC2.lsu_stb_dealloc); |
| 5845 | tmp = stb[{thid, rdptr[thid]}]; |
| 5846 | lsu_inst = tmp[`LSU_MON_INST]; |
| 5847 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 5848 | begin |
| 5849 | //DispSTB(thid); |
| 5850 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC2.lsu_stb_dealloc); |
| 5851 | end |
| 5852 | if (tmp[`L2_ST_ISS]) |
| 5853 | begin |
| 5854 | if (~tmp[`L2_ACK]) |
| 5855 | begin |
| 5856 | Disp_STB_entry(thid, rdptr[thid]); |
| 5857 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC2.lsu_stb_dealloc); |
| 5858 | end |
| 5859 | end |
| 5860 | else if (tmp[`ASI_ST_ISS]) |
| 5861 | begin |
| 5862 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 5863 | end |
| 5864 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 5865 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 5866 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 5867 | // and deallocated. |
| 5868 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 5869 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 5870 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 5871 | begin |
| 5872 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 5873 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 5874 | end |
| 5875 | else |
| 5876 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC2.lsu_stb_dealloc); |
| 5877 | |
| 5878 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 5879 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 5880 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 5881 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 5882 | /* |
| 5883 | if (tmp[`RMO]) |
| 5884 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 5885 | */ |
| 5886 | end |
| 5887 | endtask |
| 5888 | |
| 5889 | task Squash_STB; |
| 5890 | input [2:0] thid; |
| 5891 | reg [204:0] tmp; |
| 5892 | reg [3:0] squash_cnt; |
| 5893 | reg [2:0] i; |
| 5894 | begin |
| 5895 | squash_cnt = 4'b0; |
| 5896 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 5897 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 5898 | if (rdptr[thid] != iss_ptr[thid]) |
| 5899 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 5900 | |
| 5901 | if (iss_ptr[thid] == wrptr[thid]) |
| 5902 | begin |
| 5903 | if (stb_valid[{thid, wrptr[thid]}]) |
| 5904 | squash_cnt = 8; |
| 5905 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 5906 | * |
| 5907 | else |
| 5908 | begin |
| 5909 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 5910 | end |
| 5911 | */ |
| 5912 | end |
| 5913 | else |
| 5914 | begin |
| 5915 | if (iss_ptr[thid] < wrptr[thid]) |
| 5916 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 5917 | else if (iss_ptr[thid] > wrptr[thid]) |
| 5918 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 5919 | end |
| 5920 | |
| 5921 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 5922 | |
| 5923 | i = iss_ptr[thid]; |
| 5924 | |
| 5925 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 5926 | |
| 5927 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 5928 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 5929 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 5930 | |
| 5931 | while (squash_cnt) |
| 5932 | begin |
| 5933 | tmp = stb[{thid, i}]; |
| 5934 | if (~stb_valid[{thid, i}]) |
| 5935 | begin |
| 5936 | //DispSTB(thid); |
| 5937 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 5938 | end |
| 5939 | if (tmp[`L2_ST_ISS]) |
| 5940 | begin |
| 5941 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 5942 | end |
| 5943 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 5944 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 5945 | //set in the chkr which was causin it to fire. |
| 5946 | //if (~tmp[`ST_SQUASH]) |
| 5947 | //begin |
| 5948 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 5949 | //end |
| 5950 | stb_valid[{thid, i}] = 1'b0; |
| 5951 | |
| 5952 | i = i + 1; |
| 5953 | squash_cnt = squash_cnt - 1'b1; |
| 5954 | end |
| 5955 | |
| 5956 | end |
| 5957 | endtask |
| 5958 | |
| 5959 | task Chk_store; |
| 5960 | reg [2:0] thid; |
| 5961 | reg [47:0] addr; |
| 5962 | reg [3:0] i; |
| 5963 | reg [204:0] tmp; |
| 5964 | begin |
| 5965 | if ((bst_cnt > 0) && (`SPC2.lsu_stb_alloc == 8'b0)) |
| 5966 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 5967 | |
| 5968 | //For bst the stb is still written even though we have errors. |
| 5969 | //Stb is written in W stage. Howvere for first blk store helper |
| 5970 | //the err will be flagged by FGU in b stage. We can miss the |
| 5971 | // err signal if we don't sample in B. |
| 5972 | //for the last helper err will be signalled in B stage of last helper and at |
| 5973 | |
| 5974 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 5975 | bst_fgu_err = 1'b1; |
| 5976 | |
| 5977 | if (`SPC2.lsu_stb_alloc[7:0] != 8'b0) |
| 5978 | begin |
| 5979 | thid = decode_tid(`SPC2.lsu_stb_alloc[7:0]); |
| 5980 | if (store_alloc) |
| 5981 | begin |
| 5982 | if (thid != dec_lsu_tid_w) |
| 5983 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC2.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 5984 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 5985 | end |
| 5986 | else |
| 5987 | begin |
| 5988 | if (lsu_bst_active[thid]) |
| 5989 | begin |
| 5990 | if (bst_cnt == 0) |
| 5991 | begin |
| 5992 | bst_data = bst_inst_data; |
| 5993 | end |
| 5994 | else |
| 5995 | begin |
| 5996 | if (thid != bst_active_thid) |
| 5997 | begin |
| 5998 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC2.lsu_stb_alloc[7:0], bst_active_thid); |
| 5999 | end |
| 6000 | |
| 6001 | addr = bst_data[`MEMOP_VA]; |
| 6002 | |
| 6003 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 6004 | addr = bst_data[`MEMOP_PA]; |
| 6005 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 6006 | end |
| 6007 | bst_cnt = bst_cnt + 1; |
| 6008 | Insert_in_STB(bst_data, bst_active_thid); |
| 6009 | if (bst_cnt == 8) |
| 6010 | begin |
| 6011 | bst_cnt = 0; |
| 6012 | lsu_bst_active[thid] = 1'b0; |
| 6013 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 6014 | begin |
| 6015 | for (i = 0; i < 8; i=i+1) |
| 6016 | begin |
| 6017 | tmp = stb[{thid, i[2:0]}]; |
| 6018 | if (tmp[`ST_SQUASH]) |
| 6019 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 6020 | tmp[`ST_SQUASH] = 1'b1; |
| 6021 | stb[{thid, i[2:0]}] = tmp; |
| 6022 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 6023 | end |
| 6024 | end |
| 6025 | bst_fgu_err = 1'b0; |
| 6026 | end |
| 6027 | end |
| 6028 | else |
| 6029 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC2.lsu_stb_alloc[7:0]); |
| 6030 | |
| 6031 | end |
| 6032 | end |
| 6033 | else |
| 6034 | begin |
| 6035 | if (store_alloc) |
| 6036 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 6037 | end |
| 6038 | end |
| 6039 | endtask |
| 6040 | |
| 6041 | task Chk_st_on_ASI_ring; |
| 6042 | input ring; |
| 6043 | reg [2:0] thid; |
| 6044 | reg [7:0] asi; |
| 6045 | reg [47:0] addr, act_addr; |
| 6046 | reg [1:0] req_type; |
| 6047 | reg [204:0] tmp; |
| 6048 | |
| 6049 | begin |
| 6050 | if (ring == `LOCAL) |
| 6051 | thid =`SPC2.lsu_rngl_cdbus[58:56]; |
| 6052 | else |
| 6053 | thid =`SPC2.lsu_rngf_cdbus[58:56]; |
| 6054 | |
| 6055 | if (ring == `LOCAL) |
| 6056 | asi =`SPC2.lsu_rngl_cdbus[55:48]; |
| 6057 | else |
| 6058 | asi =`SPC2.lsu_rngf_cdbus[55:48]; |
| 6059 | |
| 6060 | if (ring == `LOCAL) |
| 6061 | addr =`SPC2.lsu_rngl_cdbus[47:0]; |
| 6062 | else |
| 6063 | addr =`SPC2.lsu_rngf_cdbus[47:0]; |
| 6064 | |
| 6065 | if (ring == `LOCAL) |
| 6066 | req_type =`SPC2.lsu_rngl_cdbus[61:60]; |
| 6067 | else |
| 6068 | req_type =`SPC2.lsu_rngf_cdbus[61:60]; |
| 6069 | |
| 6070 | |
| 6071 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 6072 | if (tmp[`ASI_ST_ISS]) |
| 6073 | begin |
| 6074 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6075 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 6076 | end |
| 6077 | |
| 6078 | if (tmp[`ST_SQUASH]) |
| 6079 | begin |
| 6080 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6081 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 6082 | end |
| 6083 | |
| 6084 | act_addr = tmp[`MEMOP_PA]; |
| 6085 | act_addr = {act_addr[39:3], 3'b0}; |
| 6086 | |
| 6087 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 6088 | //the address. |
| 6089 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 6090 | begin |
| 6091 | tmp[`ASI_ST_ISS] = 1'b1; |
| 6092 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 6093 | if (ring == `LOCAL) |
| 6094 | begin |
| 6095 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 6096 | end |
| 6097 | else |
| 6098 | begin |
| 6099 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 6100 | end |
| 6101 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 6102 | end |
| 6103 | else |
| 6104 | begin |
| 6105 | if (ring == `LOCAL) |
| 6106 | begin |
| 6107 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 6108 | end |
| 6109 | else |
| 6110 | begin |
| 6111 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 6112 | end |
| 6113 | end |
| 6114 | |
| 6115 | end |
| 6116 | endtask |
| 6117 | |
| 6118 | |
| 6119 | task chk_store_issue_to_pcx; |
| 6120 | input [129:0] pcx_pkt; |
| 6121 | reg [2:0] thid; |
| 6122 | reg [204:0] tmp; |
| 6123 | reg [20:0] inst; |
| 6124 | reg [39:0] pcx_pa, inst_pa; |
| 6125 | begin |
| 6126 | thid = pcx_pkt[`PCX_THR_ID]; |
| 6127 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 6128 | inst = tmp[`LSU_MON_INST]; |
| 6129 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 6130 | inst_pa = tmp[`MEMOP_PA]; |
| 6131 | |
| 6132 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 6133 | begin |
| 6134 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 6135 | end |
| 6136 | if (pcx_pkt[`PCX_INV]) |
| 6137 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 6138 | |
| 6139 | |
| 6140 | if (~inst[`ST]) |
| 6141 | begin |
| 6142 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6143 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6144 | end |
| 6145 | |
| 6146 | /* CONFIRM WITH MARK |
| 6147 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 6148 | begin |
| 6149 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6150 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 6151 | end |
| 6152 | */ |
| 6153 | //enhancement req 100146 |
| 6154 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 6155 | begin |
| 6156 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6157 | end |
| 6158 | |
| 6159 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 6160 | begin |
| 6161 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6162 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6163 | end |
| 6164 | |
| 6165 | if (tmp[`L2_ST_ISS]) |
| 6166 | begin |
| 6167 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6168 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6169 | end |
| 6170 | else |
| 6171 | tmp[`L2_ST_ISS] = 1'b1; |
| 6172 | |
| 6173 | if (tmp[`ST_SQUASH]) |
| 6174 | begin |
| 6175 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6176 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6177 | end |
| 6178 | |
| 6179 | if (tmp[`RMO]) |
| 6180 | begin |
| 6181 | if (~pcx_pkt[`PCX_BIS]) |
| 6182 | begin |
| 6183 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6184 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6185 | end |
| 6186 | if (tmp[`L2_ACK]) |
| 6187 | begin |
| 6188 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6189 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 6190 | end |
| 6191 | else |
| 6192 | begin |
| 6193 | tmp[`L2_ACK] = 1'b1; |
| 6194 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 6195 | //response seen from stub |
| 6196 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 6197 | end |
| 6198 | end |
| 6199 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 6200 | |
| 6201 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 6202 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 6203 | end |
| 6204 | endtask |
| 6205 | |
| 6206 | `ifdef INJ_STB_ERR_IN_CMP |
| 6207 | |
| 6208 | |
| 6209 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 6210 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 6211 | reg [204:0] err_tmp ; |
| 6212 | reg [20:0] err_inst; |
| 6213 | reg [44:0] cam_data; |
| 6214 | reg [5:0] err_bit; |
| 6215 | integer err_inj_cnt; |
| 6216 | reg cmp_stb_err_inj; |
| 6217 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 6218 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 6219 | |
| 6220 | initial |
| 6221 | begin |
| 6222 | cmp_stb_err_inj = 1'b0; |
| 6223 | |
| 6224 | cam_data = 45'b0; |
| 6225 | err_bit = 11; |
| 6226 | err_inj_cnt = 0; |
| 6227 | stb_err_inj = 0; |
| 6228 | if (("cmp_stb_err_inj_on")) |
| 6229 | cmp_stb_err_inj = 1'b1; |
| 6230 | else |
| 6231 | cmp_stb_err_inj = 1'b0; |
| 6232 | end |
| 6233 | |
| 6234 | always @ (negedge (`SPC2.l2clk & enabled & cmp_stb_err_inj)) |
| 6235 | begin //{ |
| 6236 | //valid stb ram rd for issue to pcx |
| 6237 | stb_err_inj = 1'b0; |
| 6238 | if (`SPC2.lsu.sbc.ram_rptr_vld_2 & `SPC2.lsu.sbc.st_pcx_rq_p3 & `SPC2.lsu.pic.pic_st_sel_p3) |
| 6239 | begin //{ |
| 6240 | err_tid = decode_tid(`SPC2.lsu.sbc.st_rq_sel_p3[7:0]); |
| 6241 | err_index = `SPC2.lsu.sbc.ram_rptr_d1; |
| 6242 | err_tmp = stb[{err_tid, err_index}]; |
| 6243 | err_inst = err_tmp[`LSU_MON_INST]; |
| 6244 | cam_data = `SPC2.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 6245 | err_priv = err_tmp[`ST_PRIV]; |
| 6246 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 6247 | if (err_inst[`CASA]) |
| 6248 | begin //{ |
| 6249 | err_inj_cnt = err_inj_cnt + 1; |
| 6250 | if (err_inj_cnt == 10) |
| 6251 | begin //{ |
| 6252 | case (err_bit) |
| 6253 | 11, 12: err_bit = err_bit + 1; |
| 6254 | 13: err_bit = 44; |
| 6255 | 44: err_bit = 11; |
| 6256 | endcase |
| 6257 | err_inj_cnt = 0; |
| 6258 | stb_err_inj = 1'b1; |
| 6259 | |
| 6260 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 6261 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 6262 | #1; |
| 6263 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 6264 | end //} |
| 6265 | end //} |
| 6266 | end //} |
| 6267 | if (stb_err_inj_d2) |
| 6268 | begin |
| 6269 | if (~`SPC2.lsu_sbapp_err_g) |
| 6270 | begin |
| 6271 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 6272 | end |
| 6273 | else |
| 6274 | begin |
| 6275 | if ((`SPC2.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 6276 | (`SPC2.lsu_stberr_index_g != stb_err_index_d2) || |
| 6277 | (`SPC2.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 6278 | begin |
| 6279 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 6280 | end |
| 6281 | end |
| 6282 | end |
| 6283 | else |
| 6284 | begin |
| 6285 | if (`SPC2.lsu_sbapp_err_g) |
| 6286 | begin |
| 6287 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC2.lsu_stberr_tid_g); |
| 6288 | end |
| 6289 | end |
| 6290 | |
| 6291 | end //} |
| 6292 | |
| 6293 | |
| 6294 | always @ (posedge (`SPC2.l2clk & enabled & cmp_stb_err_inj)) |
| 6295 | begin |
| 6296 | stb_err_inj_d1 <= stb_err_inj; |
| 6297 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 6298 | stb_err_tid_d1 <= err_tid; |
| 6299 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 6300 | stb_err_index_d1 <= err_index; |
| 6301 | stb_err_index_d2 <= stb_err_index_d1; |
| 6302 | stb_err_priv_d1 <= err_priv; |
| 6303 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 6304 | end |
| 6305 | |
| 6306 | `endif |
| 6307 | `endif |
| 6308 | `endif |
| 6309 | endmodule |
| 6310 | |
| 6311 | `endif |
| 6312 | `ifdef CORE_3 |
| 6313 | |
| 6314 | module lsu_mon_c3; |
| 6315 | `ifndef GATESIM |
| 6316 | |
| 6317 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 6318 | `ifndef NO_MONITORS |
| 6319 | |
| 6320 | reg imm_asi_vld_e; |
| 6321 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 6322 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 6323 | reg [1:0] exu_ecc_b; |
| 6324 | reg [1:0] exu_lsu_va_error_b; |
| 6325 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 6326 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 6327 | reg [31:0] inst_e, inst_m, inst_b; |
| 6328 | reg [47:0] vaddr_m, vaddr_b; |
| 6329 | reg [63:0] int_st_data_m, int_st_data_b; |
| 6330 | reg [63:0] fp_st_sata_fx2; |
| 6331 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 6332 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 6333 | |
| 6334 | reg [7:0] ld_valid; |
| 6335 | reg [7:0] tlb_valid; |
| 6336 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 6337 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 6338 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 6339 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 6340 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 6341 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 6342 | //the L2c. |
| 6343 | reg [63:0] stb_valid; |
| 6344 | reg [`STB_Pend_Width] stb[63:0]; |
| 6345 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 6346 | |
| 6347 | reg [7:0] pf_cnt[7:0]; |
| 6348 | reg [7:0] dcache_inv_cnt[7:0]; |
| 6349 | reg [7:0] st_rmo_cnt[7:0]; |
| 6350 | |
| 6351 | reg [55:0] print_inst; |
| 6352 | |
| 6353 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 6354 | |
| 6355 | reg [7:0] lsu_bst_active; |
| 6356 | reg store_alloc; |
| 6357 | reg [3:0] bst_cnt; |
| 6358 | reg [195:0] stb_alloc_data; |
| 6359 | reg [195:0] bst_data, bst_inst_data; |
| 6360 | reg [2:0] bst_active_thid; |
| 6361 | reg bst_fgu_err; |
| 6362 | |
| 6363 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 6364 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 6365 | //different types of err occur on blk ld helper returns |
| 6366 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 6367 | //stored in DFESR |
| 6368 | |
| 6369 | wire [2:0] core_id = 3; |
| 6370 | |
| 6371 | integer i; |
| 6372 | integer err_cnt; |
| 6373 | |
| 6374 | reg enabled; |
| 6375 | reg reset_in_middle; |
| 6376 | reg [7:0] finish_mask; |
| 6377 | |
| 6378 | initial |
| 6379 | begin |
| 6380 | enabled = 0; |
| 6381 | reset_in_middle = 0; |
| 6382 | ld_valid = 8'b0; |
| 6383 | lsu_inst_e = 0; |
| 6384 | tlb_valid = 8'b0; |
| 6385 | for (i = 0; i < 8; i = i+1) |
| 6386 | begin |
| 6387 | pf_cnt[i] = 0; |
| 6388 | dcache_inv_cnt[i] = 0; |
| 6389 | wrptr[i] = 0; |
| 6390 | rdptr[i] = 0; |
| 6391 | iss_ptr[i] = 0; |
| 6392 | ret_ptr[i] = 0; |
| 6393 | st_rmo_cnt[i] = 0; |
| 6394 | is_blkld[i] = 1'b0; |
| 6395 | st_priv[i] = 2'b0; |
| 6396 | l2_blk_ld_errtype[i] = 2'b0; |
| 6397 | end |
| 6398 | lsu_bst_active = 8'b0; |
| 6399 | store_alloc = 1'b0; |
| 6400 | bst_cnt = 4'b0; |
| 6401 | stb_valid = 64'b0; |
| 6402 | |
| 6403 | // avoid time zero ugliness. jp |
| 6404 | //@(posedge `SPC0.l2clk); |
| 6405 | //@(negedge `SPC0.l2clk); |
| 6406 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 6407 | |
| 6408 | case (core_id) |
| 6409 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 6410 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 6411 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 6412 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 6413 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 6414 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 6415 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 6416 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 6417 | endcase |
| 6418 | end |
| 6419 | |
| 6420 | always @ (`TOP.in_reset) |
| 6421 | begin |
| 6422 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 6423 | begin |
| 6424 | enabled = 1'b1; |
| 6425 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 6426 | end |
| 6427 | |
| 6428 | |
| 6429 | if (`TOP.in_reset & enabled) |
| 6430 | begin |
| 6431 | reset_in_middle = 1'b1; |
| 6432 | enabled = 1'b0; |
| 6433 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 6434 | end |
| 6435 | end |
| 6436 | |
| 6437 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 6438 | begin //{ |
| 6439 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 6440 | begin //{ |
| 6441 | for (i = 0; i < 8; i=i+1) |
| 6442 | begin |
| 6443 | if (ld_valid[i]) |
| 6444 | begin |
| 6445 | DispPendReq(i); |
| 6446 | end |
| 6447 | end |
| 6448 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 6449 | end //} |
| 6450 | if (|stb_valid[63:0]) |
| 6451 | begin //{ |
| 6452 | err_cnt = 0; |
| 6453 | for (i = 0; i < 64; i=i+1) |
| 6454 | begin |
| 6455 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 6456 | begin |
| 6457 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 6458 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 6459 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 6460 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 6461 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 6462 | //of simualation. |
| 6463 | if (~is_squash_bit_set(i[5:0])) |
| 6464 | begin |
| 6465 | err_cnt = err_cnt + 1; |
| 6466 | Disp_STB_entry(i[5:3],i[2:0]); |
| 6467 | end |
| 6468 | end |
| 6469 | end |
| 6470 | if (err_cnt) |
| 6471 | begin |
| 6472 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 6473 | end |
| 6474 | end //} |
| 6475 | err_cnt = 0; |
| 6476 | for (i = 0; i < 8; i=i+1) |
| 6477 | begin //{ |
| 6478 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 6479 | begin |
| 6480 | err_cnt = 1; |
| 6481 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 6482 | end |
| 6483 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 6484 | begin |
| 6485 | err_cnt = 1; |
| 6486 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 6487 | end |
| 6488 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 6489 | begin |
| 6490 | err_cnt = 1; |
| 6491 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 6492 | end |
| 6493 | end //} |
| 6494 | if (err_cnt) |
| 6495 | begin |
| 6496 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 6497 | end |
| 6498 | end //} |
| 6499 | |
| 6500 | function is_squash_bit_set; |
| 6501 | input [5:0] index; |
| 6502 | reg [204:0] tmp; |
| 6503 | begin |
| 6504 | tmp = stb[index]; |
| 6505 | if (tmp[`ST_SQUASH]) |
| 6506 | is_squash_bit_set = 1'b1; |
| 6507 | else |
| 6508 | is_squash_bit_set = 1'b0; |
| 6509 | end |
| 6510 | endfunction |
| 6511 | |
| 6512 | |
| 6513 | always @ (negedge (`SPC3.l2clk & enabled)) |
| 6514 | begin //{ |
| 6515 | |
| 6516 | asi_e = `SPC3.lsu.dcc.dcc_asi_e[7:0]; |
| 6517 | |
| 6518 | lsu_inst_e[`LD] <= `SPC3.dec_ld_inst_e; |
| 6519 | lsu_inst_e[`ST] <= `SPC3.dec_st_inst_e; |
| 6520 | lsu_inst_e[`FP] <= `SPC3.dec_fpldst_inst_e; |
| 6521 | lsu_inst_e[`PREF] <= `SPC3.dec_pref_inst_e; |
| 6522 | lsu_inst_e[`SWAP] <= `SPC3.dec_swap_inst_e; |
| 6523 | lsu_inst_e[`CASA] <= `SPC3.dec_casa_inst_e; |
| 6524 | lsu_inst_e[`LDSTUB] <= `SPC3.dec_ldstub_inst_e; |
| 6525 | lsu_inst_e[`FLUSH] <= `SPC3.dec_flush_inst_e; |
| 6526 | lsu_inst_e[`MEMBAR] <= `SPC3.dec_memstbar_inst_e; |
| 6527 | lsu_inst_e[`LDD] <= `SPC3.dec_ld_inst_e & `SPC3.dec_ldst_dbl_e & ~`SPC3.dec_fpldst_inst_e; |
| 6528 | lsu_inst_e[`STD] <= `SPC3.dec_st_inst_e & `SPC3.dec_ldst_dbl_e & ~`SPC3.lsu.dec_fpldst_inst_e; |
| 6529 | |
| 6530 | lsu_inst_e[`BLKLD] <= `SPC3.dec_ld_inst_e & `SPC3.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 6531 | lsu_inst_e[`BLKST] <= `SPC3.dec_st_inst_e & `SPC3.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 6532 | lsu_inst_e[`QLD] <= `SPC3.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 6533 | lsu_inst_e[`ASR_RD_WR] <= `SPC3.dec_sr_inst_e & (`SPC3.dec_ld_inst_e | `SPC3.dec_st_inst_e); |
| 6534 | lsu_inst_e[`PR_RD_WR] <= `SPC3.dec_pr_inst_e & (`SPC3.dec_ld_inst_e | `SPC3.dec_st_inst_e); |
| 6535 | lsu_inst_e[`HPR_RD_WR] <= `SPC3.dec_hpr_inst_e & (`SPC3.dec_ld_inst_e | `SPC3.dec_st_inst_e); |
| 6536 | lsu_inst_e[`FSR_RD_WR] <= `SPC3.dec_fsr_ldst_e & (`SPC3.dec_ld_inst_e | `SPC3.dec_st_inst_e); |
| 6537 | end //} |
| 6538 | |
| 6539 | always @ (posedge (`SPC3.l2clk & enabled)) |
| 6540 | begin //{ |
| 6541 | dec_tg0_inst_d <= `SPC3.dec.ded0.decode_mux[31:0]; |
| 6542 | dec_tg1_inst_d <= `SPC3.dec.ded1.decode_mux[31:0]; |
| 6543 | imm_asi_vld_e <= `SPC3.lsu.dec_imm_asi_vld_d; |
| 6544 | |
| 6545 | imm_asi_e <= `SPC3.lsu.dec_imm_asi_d; |
| 6546 | dec_altspace_e <= `SPC3.dec_altspace_d; |
| 6547 | dec_altspace_m <= dec_altspace_e; |
| 6548 | dec_altspace_b <= dec_altspace_m; |
| 6549 | |
| 6550 | exu_ecc_b <= `SPC3.exu_ecc_m; |
| 6551 | exu_lsu_va_error_b <= `SPC3.exu_lsu_va_error_m; |
| 6552 | |
| 6553 | dec_lsu_tid_e <= `SPC3.dec_lsu_tg_d ? {1'b1, `SPC3.dec_lsu_tid1_d} : {1'b0, `SPC3.dec_lsu_tid0_d}; |
| 6554 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 6555 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 6556 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 6557 | |
| 6558 | inst_pc_e <= `SPC3.dec_lsu_tg_d ? {`SPC3.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC3.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 6559 | inst_pc_m <= inst_pc_e; |
| 6560 | inst_pc_b <= inst_pc_m; |
| 6561 | inst_pc_w <= inst_pc_b; |
| 6562 | |
| 6563 | inst_e <= `SPC3.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 6564 | inst_m <= inst_e; |
| 6565 | inst_b <= inst_m; |
| 6566 | |
| 6567 | vaddr_m <= `SPC3.exu_lsu_address_e; |
| 6568 | vaddr_b <= vaddr_m; |
| 6569 | |
| 6570 | int_st_data_m <= `SPC3.exu_lsu_store_data_e; |
| 6571 | int_st_data_b <= int_st_data_m; |
| 6572 | fp_st_sata_fx2 <= `SPC3.fgu_lsu_fst_data_fx1; |
| 6573 | |
| 6574 | mmu_dtlb_reload_d1 <= `SPC3.mmu_dtlb_reload; |
| 6575 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 6576 | |
| 6577 | //pcx_thid_d1 <= `SPC3.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 6578 | lsu_inst_m <= lsu_inst_e; |
| 6579 | lsu_inst_b <= lsu_inst_m; |
| 6580 | |
| 6581 | asi_m <= asi_e; |
| 6582 | asi_b <= asi_m; |
| 6583 | end //} |
| 6584 | |
| 6585 | function Is_blk_asi; |
| 6586 | input [7:0] asi; |
| 6587 | begin |
| 6588 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 6589 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 6590 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 6591 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 6592 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 6593 | end |
| 6594 | endfunction |
| 6595 | |
| 6596 | function Is_qld_asi; |
| 6597 | input [7:0] asi; |
| 6598 | begin |
| 6599 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 6600 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 6601 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 6602 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 6603 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 6604 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 6605 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 6606 | end |
| 6607 | endfunction |
| 6608 | |
| 6609 | function Is_bis_asi; |
| 6610 | input [7:0] asi; |
| 6611 | begin |
| 6612 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 6613 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 6614 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 6615 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 6616 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 6617 | end |
| 6618 | endfunction |
| 6619 | |
| 6620 | always @ (negedge (`SPC3.l2clk & enabled)) |
| 6621 | begin //{ |
| 6622 | Chk_store; |
| 6623 | store_alloc = 1'b0; |
| 6624 | if (lsu_inst_m != 0) |
| 6625 | begin |
| 6626 | if (`SPC3.dec_flush_lm) |
| 6627 | begin |
| 6628 | lsu_inst_m <= 0; |
| 6629 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 6630 | end |
| 6631 | end |
| 6632 | |
| 6633 | if (lsu_inst_b != 0) |
| 6634 | begin //{ |
| 6635 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 6636 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 6637 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 6638 | else print_inst = ""; |
| 6639 | |
| 6640 | if (`SPC3.dec_flush_lb) |
| 6641 | begin |
| 6642 | lsu_inst_b <= 0; |
| 6643 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 6644 | end |
| 6645 | else if (`SPC3.tlu_flush_lsu_b) |
| 6646 | begin |
| 6647 | lsu_inst_b <= 0; |
| 6648 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 6649 | end |
| 6650 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 6651 | //casa shd be killed. |
| 6652 | //This function will also chk for errors on 2nd cycle. |
| 6653 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 6654 | begin |
| 6655 | lsu_inst_b <= 0; |
| 6656 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 6657 | end |
| 6658 | else if ((`SPC3.fgu_cecc_fx2 || `SPC3.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 6659 | begin |
| 6660 | lsu_inst_b <= 0; |
| 6661 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 6662 | end |
| 6663 | else if (IsExc(core_id)) |
| 6664 | lsu_inst_b <= 0; |
| 6665 | else if (!`SPC3.lsu_tlb_miss_b_) |
| 6666 | begin |
| 6667 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 6668 | //Insert_tlb_miss_info; |
| 6669 | end |
| 6670 | else |
| 6671 | begin //{ |
| 6672 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 6673 | //an exception tlu anyway tells the front end to flush itself there is |
| 6674 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 6675 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 6676 | //handles it when it is reissued by the front end. |
| 6677 | |
| 6678 | if (`SPC3.lsu_tlb_bypass_b) |
| 6679 | begin |
| 6680 | if (`SPC3.lsu_sync != 8'b0) |
| 6681 | begin |
| 6682 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 6683 | end |
| 6684 | else |
| 6685 | begin |
| 6686 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 6687 | end |
| 6688 | end |
| 6689 | else |
| 6690 | begin |
| 6691 | if (`SPC3.lsu_sync != 8'b0) |
| 6692 | begin |
| 6693 | if (lsu_inst_b[`ST]) |
| 6694 | begin |
| 6695 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 6696 | end |
| 6697 | else |
| 6698 | begin |
| 6699 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 6700 | end |
| 6701 | end |
| 6702 | else |
| 6703 | begin |
| 6704 | if (lsu_inst_b[`ST]) |
| 6705 | begin |
| 6706 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 6707 | end |
| 6708 | else |
| 6709 | begin |
| 6710 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 6711 | end |
| 6712 | end |
| 6713 | end |
| 6714 | |
| 6715 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 6716 | begin //{ |
| 6717 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC3.lsu.stb_cam_hit) |
| 6718 | begin |
| 6719 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 6720 | end |
| 6721 | end //} |
| 6722 | |
| 6723 | if (lsu_inst_b[`LD]) |
| 6724 | Insert_ld_miss_info; |
| 6725 | |
| 6726 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 6727 | begin |
| 6728 | Make_STB_data; |
| 6729 | store_alloc = 1'b1; |
| 6730 | end |
| 6731 | Insert_in_last_inst_array; |
| 6732 | |
| 6733 | if (`SPC3.lsu_trap_flush[7:0]) |
| 6734 | begin |
| 6735 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC3.lsu_trap_flush[7:0])); |
| 6736 | end |
| 6737 | end //} |
| 6738 | end //} |
| 6739 | end //} |
| 6740 | |
| 6741 | //STB ue testing: |
| 6742 | //This is how we test squashing of stores by LSU_mon: |
| 6743 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 6744 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 6745 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 6746 | //The squashed stores are deallocated when either a block_store_kill is |
| 6747 | //asserted or dealloc signals are asserted by the LSU. |
| 6748 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 6749 | //all the pending stores in the IFU. It means the when block_store_kill |
| 6750 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 6751 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 6752 | //the sbdiou signal to TLU. |
| 6753 | |
| 6754 | |
| 6755 | always @ (negedge (`SPC3.l2clk & enabled)) |
| 6756 | begin |
| 6757 | if (`SPC3.lsu_l15_valid & `SPC3.lsu.spc_pcx_data_pa[129]) |
| 6758 | Chk_pcx_req_pkt(`SPC3.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 6759 | if ((`SPC3.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC3.lsu_rngl_cdbus[59]) |
| 6760 | Chk_st_on_ASI_ring(`LOCAL); |
| 6761 | |
| 6762 | if ((`SPC3.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC3.lsu_rngf_cdbus[59]) |
| 6763 | Chk_st_on_ASI_ring(`FAST); |
| 6764 | |
| 6765 | //if (`SPC3.l15_lsu_valid) |
| 6766 | //Chk_cpx_response_pkt({`SPC3.l15_lsu_valid, `SPC3.l15_lsu_cpkt[17:13],`SPC3.l15_lsu_cpkt[11:0],`SPC3.l15_spc_data1[127:0]}); |
| 6767 | |
| 6768 | if (`SPC3.cpx_spc_data_cx[145]) |
| 6769 | Chk_cpx_response_pkt(`SPC3.cpx_spc_data_cx); |
| 6770 | |
| 6771 | if (`SPC3.lsu_complete[7:0] != 8'b0) |
| 6772 | begin |
| 6773 | if (`SPC3.lsu_complete[0]) Chk_ld_complete(0); |
| 6774 | if (`SPC3.lsu_complete[1]) Chk_ld_complete(1); |
| 6775 | if (`SPC3.lsu_complete[2]) Chk_ld_complete(2); |
| 6776 | if (`SPC3.lsu_complete[3]) Chk_ld_complete(3); |
| 6777 | if (`SPC3.lsu_complete[4]) Chk_ld_complete(4); |
| 6778 | if (`SPC3.lsu_complete[5]) Chk_ld_complete(5); |
| 6779 | if (`SPC3.lsu_complete[6]) Chk_ld_complete(6); |
| 6780 | if (`SPC3.lsu_complete[7]) Chk_ld_complete(7); |
| 6781 | end |
| 6782 | |
| 6783 | if (`SPC3.lsu_block_store_kill[7:0] != 8'b0) |
| 6784 | begin |
| 6785 | if (`SPC3.lsu_block_store_kill[0]) Squash_STB(0); |
| 6786 | if (`SPC3.lsu_block_store_kill[1]) Squash_STB(1); |
| 6787 | if (`SPC3.lsu_block_store_kill[2]) Squash_STB(2); |
| 6788 | if (`SPC3.lsu_block_store_kill[3]) Squash_STB(3); |
| 6789 | if (`SPC3.lsu_block_store_kill[4]) Squash_STB(4); |
| 6790 | if (`SPC3.lsu_block_store_kill[5]) Squash_STB(5); |
| 6791 | if (`SPC3.lsu_block_store_kill[6]) Squash_STB(6); |
| 6792 | if (`SPC3.lsu_block_store_kill[7]) Squash_STB(7); |
| 6793 | end |
| 6794 | |
| 6795 | if (`SPC3.lsu_stb_dealloc[7:0] != 8'b0) |
| 6796 | begin |
| 6797 | if (`SPC3.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 6798 | if (`SPC3.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 6799 | if (`SPC3.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 6800 | if (`SPC3.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 6801 | if (`SPC3.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 6802 | if (`SPC3.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 6803 | if (`SPC3.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 6804 | if (`SPC3.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 6805 | end |
| 6806 | |
| 6807 | if (`SPC3.lsu_block_store_stall) |
| 6808 | Chk_block_store; |
| 6809 | |
| 6810 | if (`SPC3.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 6811 | Set_block_store_parameters; |
| 6812 | |
| 6813 | if (`SPC3.lsu_sbdiou_err_g || `SPC3.lsu_sbapp_err_g) |
| 6814 | Squash_store; |
| 6815 | |
| 6816 | if (`SPC3.lsu_stb_flush_g) |
| 6817 | st_priv[`SPC3.lsu_stberr_tid_g] = get_priv_on_flush(`SPC3.lsu_stberr_tid_g); |
| 6818 | end |
| 6819 | |
| 6820 | function [1:0] get_priv_on_flush; |
| 6821 | input [2:0] tid; |
| 6822 | reg [2:0] sq_index; |
| 6823 | reg [204:0] tmp; |
| 6824 | |
| 6825 | begin |
| 6826 | sq_index = `SPC3.lsu_stberr_index_g; |
| 6827 | tmp = stb[{tid, sq_index}]; |
| 6828 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 6829 | end |
| 6830 | endfunction |
| 6831 | |
| 6832 | task Chk_block_store; |
| 6833 | reg [20:0] inst; |
| 6834 | reg [2:0] thid; |
| 6835 | begin |
| 6836 | thid = `SPC3.lsu_block_store_tid; |
| 6837 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 6838 | inst = bst_inst_data[`LSU_MON_INST]; |
| 6839 | |
| 6840 | if (~inst[`BLKST]) |
| 6841 | begin |
| 6842 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 6843 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 6844 | end |
| 6845 | end |
| 6846 | endtask |
| 6847 | |
| 6848 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 6849 | //the 8 stb entries from the previous blk store. |
| 6850 | |
| 6851 | task Set_block_store_parameters; |
| 6852 | reg [2:0] thid; |
| 6853 | begin |
| 6854 | |
| 6855 | thid = decode_tid(`SPC3.lsu.lsu_block_store_alloc[7:0]); |
| 6856 | if (lsu_bst_active[thid]) |
| 6857 | begin |
| 6858 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 6859 | end |
| 6860 | else |
| 6861 | begin |
| 6862 | lsu_bst_active[thid] = 1'b1; |
| 6863 | bst_active_thid = thid; |
| 6864 | if (`SPC3.lsu.fgu_fst_ecc_error_fx2) |
| 6865 | bst_fgu_err = 1'b1; |
| 6866 | else |
| 6867 | bst_fgu_err = 1'b0; |
| 6868 | end |
| 6869 | end |
| 6870 | endtask |
| 6871 | |
| 6872 | task Squash_store; |
| 6873 | reg [2:0] thid; |
| 6874 | reg [2:0] sq_index; |
| 6875 | reg [2:0] i; |
| 6876 | reg [204:0] tmp; |
| 6877 | reg [3:0] squash_cnt; |
| 6878 | reg [1:0] priv; |
| 6879 | |
| 6880 | begin |
| 6881 | thid = `SPC3.lsu_stberr_tid_g; |
| 6882 | sq_index = `SPC3.lsu_stberr_index_g; |
| 6883 | priv = `SPC3.lsu_stberr_priv_g; |
| 6884 | tmp = stb[{thid, sq_index}]; |
| 6885 | squash_cnt = 0; |
| 6886 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 6887 | |
| 6888 | st_priv[thid] = tmp[`ST_PRIV]; |
| 6889 | |
| 6890 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 6891 | //In that case iss_ptr won't be equal to sbdiou index. |
| 6892 | //if (sq_index != iss_ptr[thid]) |
| 6893 | //begin |
| 6894 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 6895 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 6896 | //end |
| 6897 | |
| 6898 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 6899 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 6900 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 6901 | //removing this chk. |
| 6902 | |
| 6903 | //if (tmp[`L2_ST_ISS]) |
| 6904 | //begin |
| 6905 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 6906 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 6907 | //end |
| 6908 | |
| 6909 | if (iss_ptr[thid] == wrptr[thid]) |
| 6910 | begin |
| 6911 | if (stb_valid[{thid, wrptr[thid]}]) |
| 6912 | squash_cnt = 8; |
| 6913 | else |
| 6914 | begin |
| 6915 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 6916 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 6917 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 6918 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 6919 | end |
| 6920 | end |
| 6921 | else |
| 6922 | begin |
| 6923 | if (iss_ptr[thid] < wrptr[thid]) |
| 6924 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 6925 | else if (iss_ptr[thid] > wrptr[thid]) |
| 6926 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 6927 | end |
| 6928 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 6929 | |
| 6930 | i = iss_ptr[thid]; |
| 6931 | |
| 6932 | while (squash_cnt) |
| 6933 | begin |
| 6934 | tmp = stb[{thid, i}]; |
| 6935 | tmp[`ST_SQUASH] = 1'b1; |
| 6936 | if (priv < tmp[`ST_PRIV]) |
| 6937 | begin |
| 6938 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 6939 | priv = tmp[`ST_PRIV]; |
| 6940 | end |
| 6941 | |
| 6942 | stb[{thid, i}] = tmp; |
| 6943 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 6944 | |
| 6945 | i = i + 1; |
| 6946 | squash_cnt = squash_cnt - 1'b1; |
| 6947 | end |
| 6948 | end |
| 6949 | endtask |
| 6950 | |
| 6951 | function [2:0] decode_tid; |
| 6952 | input [7:0] thid_encode; |
| 6953 | begin |
| 6954 | case (thid_encode) |
| 6955 | 8'h1: decode_tid = 3'b0; |
| 6956 | 8'h2: decode_tid = 3'h1; |
| 6957 | 8'h4: decode_tid = 3'h2; |
| 6958 | 8'h8: decode_tid = 3'h3; |
| 6959 | 8'h10: decode_tid = 3'h4; |
| 6960 | 8'h20: decode_tid = 3'h5; |
| 6961 | 8'h40: decode_tid = 3'h6; |
| 6962 | 8'h80: decode_tid = 3'h7; |
| 6963 | default: |
| 6964 | begin |
| 6965 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 6966 | end |
| 6967 | endcase |
| 6968 | end |
| 6969 | endfunction |
| 6970 | |
| 6971 | task Chk_ld_complete; |
| 6972 | input [2:0] thid; |
| 6973 | reg [`LD_Pend_Width] tmp; |
| 6974 | begin |
| 6975 | tmp = ld_pend_array[thid]; |
| 6976 | |
| 6977 | if (ld_valid[thid]) |
| 6978 | begin |
| 6979 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 6980 | begin |
| 6981 | DispPendReq(thid); |
| 6982 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 6983 | end |
| 6984 | ld_valid[thid] = 1'b0; |
| 6985 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 6986 | end |
| 6987 | |
| 6988 | tmp = last_inst_array[thid]; |
| 6989 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 6990 | end |
| 6991 | endtask |
| 6992 | |
| 6993 | task Chk_pcx_req_pkt; |
| 6994 | input [129:0] pcx_pkt; |
| 6995 | reg [2:0] thid; |
| 6996 | reg [`LD_Pend_Width] tmp, tmp1; |
| 6997 | reg [15:0] inst; |
| 6998 | reg [11*8:0] req; |
| 6999 | reg [39:0] addr; |
| 7000 | begin |
| 7001 | thid = pcx_pkt[`PCX_THR_ID]; |
| 7002 | tmp = ld_pend_array[thid]; |
| 7003 | inst = tmp[`LSU_MON_INST]; |
| 7004 | req = DispPCXReq(pcx_pkt); |
| 7005 | addr = pcx_pkt[`PCX_ADDR]; |
| 7006 | |
| 7007 | |
| 7008 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 7009 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 7010 | |
| 7011 | |
| 7012 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 7013 | begin |
| 7014 | if (~ld_valid[thid]) |
| 7015 | begin |
| 7016 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 7017 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 7018 | end |
| 7019 | if (~inst[`BLKLD]) |
| 7020 | begin |
| 7021 | if (tmp[`MEMOP_PA] != addr) |
| 7022 | begin |
| 7023 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 7024 | begin |
| 7025 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 7026 | end |
| 7027 | else |
| 7028 | begin |
| 7029 | DispPendReq(thid); |
| 7030 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 7031 | end |
| 7032 | end |
| 7033 | end |
| 7034 | end |
| 7035 | |
| 7036 | case (pcx_pkt[`PCX_RQTYP]) |
| 7037 | `PCX_LOAD: |
| 7038 | begin |
| 7039 | if (pcx_pkt[`PCX_PF]) |
| 7040 | begin |
| 7041 | if (~inst[`PREF]) |
| 7042 | begin |
| 7043 | DispPendReq(thid); |
| 7044 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 7045 | end |
| 7046 | if (pcx_pkt[`PCX_INV]) |
| 7047 | begin |
| 7048 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 7049 | end |
| 7050 | else |
| 7051 | begin |
| 7052 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 7053 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 7054 | end |
| 7055 | tmp[`L2_ISS] = 4'hF; |
| 7056 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 7057 | ld_pend_array[thid] = tmp; |
| 7058 | end |
| 7059 | else |
| 7060 | begin |
| 7061 | if (pcx_pkt[`PCX_INV]) |
| 7062 | begin |
| 7063 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7064 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 7065 | end |
| 7066 | else |
| 7067 | begin |
| 7068 | Chk_req_load(pcx_pkt); |
| 7069 | end |
| 7070 | end |
| 7071 | end |
| 7072 | `PCX_CAS1, `PCX_CAS2: |
| 7073 | begin |
| 7074 | if (~inst[`CASA]) |
| 7075 | begin |
| 7076 | DispPendReq(thid); |
| 7077 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 7078 | end |
| 7079 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 7080 | begin |
| 7081 | tmp[`L2_ISS] = 4'hE; |
| 7082 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7083 | ld_pend_array[thid] = tmp; |
| 7084 | end |
| 7085 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 7086 | begin |
| 7087 | tmp[`L2_ISS] = 4'hF; |
| 7088 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7089 | ld_pend_array[thid] = tmp; |
| 7090 | chk_store_issue_to_pcx(pcx_pkt); |
| 7091 | end |
| 7092 | |
| 7093 | end |
| 7094 | `PCX_SWAP_LDSTUB: |
| 7095 | begin |
| 7096 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 7097 | begin |
| 7098 | DispPendReq(thid); |
| 7099 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 7100 | end |
| 7101 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 7102 | tmp[`L2_ISS] = 4'hF; |
| 7103 | ld_pend_array[thid] = tmp; |
| 7104 | |
| 7105 | chk_store_issue_to_pcx(pcx_pkt); |
| 7106 | end |
| 7107 | |
| 7108 | `PCX_STORE: |
| 7109 | begin |
| 7110 | chk_store_issue_to_pcx(pcx_pkt); |
| 7111 | end |
| 7112 | |
| 7113 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 7114 | endcase |
| 7115 | end |
| 7116 | endtask |
| 7117 | |
| 7118 | task Chk_cpx_response_pkt; |
| 7119 | input [145:0] cpx_pkt; |
| 7120 | reg [2:0] thid; |
| 7121 | begin |
| 7122 | thid = cpx_pkt[`CPX_THR_ID]; |
| 7123 | |
| 7124 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 7125 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 7126 | begin |
| 7127 | chk_ccx_ld_response(cpx_pkt); |
| 7128 | end |
| 7129 | |
| 7130 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 7131 | begin |
| 7132 | if (pf_cnt[thid] == 8'b0) |
| 7133 | begin |
| 7134 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 7135 | end |
| 7136 | else |
| 7137 | begin |
| 7138 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 7139 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 7140 | end |
| 7141 | end |
| 7142 | |
| 7143 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 7144 | chk_ccx_ld_response(cpx_pkt); |
| 7145 | |
| 7146 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 7147 | begin |
| 7148 | if (cpx_pkt[123]) //D pkt |
| 7149 | begin //{ |
| 7150 | if (cpx_pkt[120:118] != core_id) |
| 7151 | begin |
| 7152 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 7153 | end |
| 7154 | if (dcache_inv_cnt[thid] == 8'b0) |
| 7155 | begin |
| 7156 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 7157 | end |
| 7158 | else |
| 7159 | begin |
| 7160 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 7161 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 7162 | end |
| 7163 | end //} |
| 7164 | else if (cpx_pkt[124]) //I pkt |
| 7165 | begin |
| 7166 | if (cpx_pkt[120:118] != core_id) |
| 7167 | begin |
| 7168 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 7169 | end |
| 7170 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 7171 | end |
| 7172 | else if (cpx_pkt[124:123] == 2'b0) |
| 7173 | begin |
| 7174 | if (cpx_pkt[120:118] == core_id) |
| 7175 | begin |
| 7176 | chk_ccx_st_response(cpx_pkt); |
| 7177 | end |
| 7178 | else |
| 7179 | begin |
| 7180 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 7181 | end |
| 7182 | end |
| 7183 | end |
| 7184 | |
| 7185 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 7186 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 7187 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 7188 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 7189 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 7190 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 7191 | |
| 7192 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 7193 | begin |
| 7194 | chk_ccx_atm_response(cpx_pkt); |
| 7195 | end |
| 7196 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 7197 | begin |
| 7198 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 7199 | begin |
| 7200 | chk_ccx_atm_response(cpx_pkt); |
| 7201 | chk_ccx_st_response(cpx_pkt); |
| 7202 | end |
| 7203 | end |
| 7204 | |
| 7205 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 7206 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 7207 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 7208 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 7209 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 7210 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 7211 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 7212 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 7213 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 7214 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 7215 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 7216 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 7217 | |
| 7218 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 7219 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 7220 | |
| 7221 | default: |
| 7222 | begin |
| 7223 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 7224 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 7225 | |
| 7226 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 7227 | end |
| 7228 | |
| 7229 | endcase |
| 7230 | end |
| 7231 | endtask |
| 7232 | |
| 7233 | task chk_ccx_ld_response; |
| 7234 | input [145:0] cpx_pkt; |
| 7235 | reg [2:0] thid; |
| 7236 | reg [20:0] inst; |
| 7237 | reg [39:0] cpx_pa, inst_pa; |
| 7238 | reg [`LD_Pend_Width] tmp; |
| 7239 | reg [3:0] pkt_type; |
| 7240 | begin |
| 7241 | thid = cpx_pkt[`CPX_THR_ID]; |
| 7242 | tmp = ld_pend_array[thid]; |
| 7243 | inst = tmp[`LSU_MON_INST]; |
| 7244 | inst_pa = tmp[`MEMOP_PA]; |
| 7245 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 7246 | |
| 7247 | if (ld_valid[thid]) |
| 7248 | begin |
| 7249 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 7250 | /* |
| 7251 | if (inst_pa[39] != pkt_type[3]) |
| 7252 | begin |
| 7253 | DispPendReq(thid); |
| 7254 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 7255 | end |
| 7256 | */ |
| 7257 | |
| 7258 | if (inst[`BLKLD]) |
| 7259 | begin |
| 7260 | if (tmp[`L2_RESP] == 4'h0) |
| 7261 | begin |
| 7262 | tmp[`L2_RESP] = 4'h1; |
| 7263 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 7264 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 7265 | begin |
| 7266 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 7267 | end |
| 7268 | |
| 7269 | end |
| 7270 | else if (tmp[`L2_RESP] == 4'h1) |
| 7271 | begin |
| 7272 | tmp[`L2_RESP] = 4'h3; |
| 7273 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 7274 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 7275 | begin |
| 7276 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 7277 | end |
| 7278 | end |
| 7279 | else if (tmp[`L2_RESP] == 4'h3) |
| 7280 | begin |
| 7281 | tmp[`L2_RESP] = 4'h7; |
| 7282 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 7283 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 7284 | begin |
| 7285 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 7286 | end |
| 7287 | end |
| 7288 | else if (tmp[`L2_RESP] == 4'h7) |
| 7289 | begin |
| 7290 | tmp[`L2_RESP] = 4'hF; |
| 7291 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 7292 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 7293 | begin |
| 7294 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 7295 | end |
| 7296 | |
| 7297 | //is_blkld[thid] = 1'b1; |
| 7298 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 7299 | l2_blk_ld_errtype[thid] = `ND; |
| 7300 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 7301 | l2_blk_ld_errtype[thid] = `UE; |
| 7302 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 7303 | l2_blk_ld_errtype[thid] = `CE; |
| 7304 | else |
| 7305 | l2_blk_ld_errtype[thid] = `NE; |
| 7306 | end |
| 7307 | else |
| 7308 | begin |
| 7309 | DispPendReq(thid); |
| 7310 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 7311 | end |
| 7312 | end |
| 7313 | else if (Is_single_pcx_req_ld(inst)) |
| 7314 | begin |
| 7315 | //is_blkld[thid] = 1'b0; |
| 7316 | if (tmp[`L2_RESP] != 4'hE) |
| 7317 | begin |
| 7318 | DispPendReq(thid); |
| 7319 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 7320 | end |
| 7321 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 7322 | tmp[`L2_RESP] = 4'hF; |
| 7323 | end |
| 7324 | else |
| 7325 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 7326 | end |
| 7327 | else |
| 7328 | begin |
| 7329 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 7330 | end |
| 7331 | |
| 7332 | ld_pend_array[thid] = tmp; |
| 7333 | end |
| 7334 | endtask |
| 7335 | |
| 7336 | task chk_ccx_atm_response; |
| 7337 | input [145:0] cpx_pkt; |
| 7338 | reg [2:0] thid; |
| 7339 | reg [20:0] inst; |
| 7340 | reg [39:0] inst_pa; |
| 7341 | reg [`LD_Pend_Width] tmp; |
| 7342 | begin |
| 7343 | thid = cpx_pkt[`CPX_THR_ID]; |
| 7344 | tmp = ld_pend_array[thid]; |
| 7345 | inst = tmp[`LSU_MON_INST]; |
| 7346 | inst_pa = tmp[`MEMOP_PA]; |
| 7347 | |
| 7348 | if (~ld_valid[thid]) |
| 7349 | begin |
| 7350 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 7351 | begin |
| 7352 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 7353 | end |
| 7354 | else |
| 7355 | begin |
| 7356 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 7357 | end |
| 7358 | end |
| 7359 | else |
| 7360 | begin |
| 7361 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 7362 | begin |
| 7363 | DispPendReq(thid); |
| 7364 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 7365 | begin |
| 7366 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 7367 | end |
| 7368 | else |
| 7369 | begin |
| 7370 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 7371 | end |
| 7372 | end |
| 7373 | else |
| 7374 | begin |
| 7375 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 7376 | begin |
| 7377 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 7378 | end |
| 7379 | else |
| 7380 | begin |
| 7381 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 7382 | end |
| 7383 | |
| 7384 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 7385 | begin |
| 7386 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 7387 | else |
| 7388 | begin |
| 7389 | DispPendReq(thid); |
| 7390 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 7391 | end |
| 7392 | end |
| 7393 | else |
| 7394 | begin |
| 7395 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 7396 | else |
| 7397 | begin |
| 7398 | DispPendReq(thid); |
| 7399 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 7400 | end |
| 7401 | end |
| 7402 | end |
| 7403 | end |
| 7404 | ld_pend_array[thid] = tmp; |
| 7405 | end |
| 7406 | endtask |
| 7407 | |
| 7408 | task chk_ccx_st_response; |
| 7409 | input [145:0] cpx_pkt; |
| 7410 | reg [2:0] thid; |
| 7411 | reg [20:0] inst; |
| 7412 | reg [39:0] cpx_pa, inst_pa; |
| 7413 | reg [204:0] tmp; |
| 7414 | reg [3:0] pkt_type; |
| 7415 | begin |
| 7416 | thid = cpx_pkt[`CPX_THR_ID]; |
| 7417 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 7418 | inst = tmp[`LSU_MON_INST]; |
| 7419 | inst_pa = tmp[`MEMOP_PA]; |
| 7420 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 7421 | |
| 7422 | |
| 7423 | //is received. There could be some other store sitting in the STB at that time. |
| 7424 | |
| 7425 | //Chk for squash bit only for non-bis responses. |
| 7426 | |
| 7427 | |
| 7428 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 7429 | begin |
| 7430 | if (st_rmo_cnt[thid] == 0) |
| 7431 | begin |
| 7432 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 7433 | end |
| 7434 | else |
| 7435 | begin |
| 7436 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 7437 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 7438 | end |
| 7439 | end |
| 7440 | else |
| 7441 | begin |
| 7442 | if (tmp[`ST_SQUASH]) |
| 7443 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 7444 | |
| 7445 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 7446 | begin |
| 7447 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 7448 | end |
| 7449 | else |
| 7450 | begin |
| 7451 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 7452 | begin |
| 7453 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 7454 | end |
| 7455 | tmp[`L2_ACK] = 1'b1; |
| 7456 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 7457 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 7458 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 7459 | end |
| 7460 | end |
| 7461 | end |
| 7462 | endtask |
| 7463 | |
| 7464 | task Chk_req_load; |
| 7465 | input [129:0] pcx_pkt; |
| 7466 | reg [2:0] thid; |
| 7467 | reg [`LD_Pend_Width] tmp; |
| 7468 | reg [39:0] pcx_pa, inst_pa; |
| 7469 | reg [20:0] inst; |
| 7470 | reg [11*8:0] req; |
| 7471 | begin |
| 7472 | |
| 7473 | thid = pcx_pkt[`PCX_THR_ID]; |
| 7474 | tmp = ld_pend_array[thid]; |
| 7475 | inst = tmp[`LSU_MON_INST]; |
| 7476 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 7477 | inst_pa = tmp[`MEMOP_PA]; |
| 7478 | req = DispPCXReq(pcx_pkt); |
| 7479 | |
| 7480 | if (inst[`BLKLD]) |
| 7481 | begin |
| 7482 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 7483 | begin |
| 7484 | DispPendReq(thid); |
| 7485 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 7486 | end |
| 7487 | if (pcx_pa[5:0] == 6'b0) |
| 7488 | begin |
| 7489 | if (tmp[`L2_ISS] != 4'h0 ) |
| 7490 | begin |
| 7491 | DispPendReq(thid); |
| 7492 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 7493 | end |
| 7494 | else |
| 7495 | begin |
| 7496 | tmp[`L2_ISS] = 4'h1; |
| 7497 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7498 | end |
| 7499 | |
| 7500 | end |
| 7501 | if (pcx_pa[5:0] == 6'h10) |
| 7502 | begin |
| 7503 | if (tmp[`L2_ISS] != 4'h1) |
| 7504 | begin |
| 7505 | DispPendReq(thid); |
| 7506 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 7507 | end |
| 7508 | else |
| 7509 | begin |
| 7510 | tmp[`L2_ISS] = 4'h3; |
| 7511 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7512 | end |
| 7513 | end |
| 7514 | if (pcx_pa[5:0] == 6'h20) |
| 7515 | begin |
| 7516 | if (tmp[`L2_ISS] != 4'h3) |
| 7517 | begin |
| 7518 | DispPendReq(thid); |
| 7519 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 7520 | end |
| 7521 | else |
| 7522 | begin |
| 7523 | tmp[`L2_ISS] = 4'h7; |
| 7524 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7525 | end |
| 7526 | end |
| 7527 | if (pcx_pa[5:0] == 6'h30) |
| 7528 | begin |
| 7529 | if (tmp[`L2_ISS] != 4'h7) |
| 7530 | begin |
| 7531 | DispPendReq(thid); |
| 7532 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 7533 | end |
| 7534 | else |
| 7535 | begin |
| 7536 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7537 | tmp[`L2_ISS] = 4'hF; |
| 7538 | end |
| 7539 | end |
| 7540 | ld_pend_array[thid] = tmp; |
| 7541 | end |
| 7542 | else if (Is_single_pcx_req_ld(inst)) |
| 7543 | begin |
| 7544 | if (tmp[`L2_ISS] == 4'hF) |
| 7545 | begin |
| 7546 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 7547 | end |
| 7548 | else |
| 7549 | begin |
| 7550 | tmp[`L2_ISS] = 4'hF; |
| 7551 | ld_pend_array[thid] = tmp; |
| 7552 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 7553 | end |
| 7554 | end |
| 7555 | else |
| 7556 | begin |
| 7557 | DispPendReq(thid); |
| 7558 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 7559 | end |
| 7560 | end |
| 7561 | endtask |
| 7562 | |
| 7563 | |
| 7564 | function Is_single_pcx_req_ld; |
| 7565 | input [20:0] inst; |
| 7566 | begin |
| 7567 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 7568 | Is_single_pcx_req_ld = 1'b1; |
| 7569 | else |
| 7570 | Is_single_pcx_req_ld = 1'b0; |
| 7571 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 7572 | end |
| 7573 | endfunction |
| 7574 | |
| 7575 | |
| 7576 | function Is_trap; |
| 7577 | input [2:0]tid; |
| 7578 | |
| 7579 | begin |
| 7580 | Is_trap = 1'b0; |
| 7581 | case (`SPC3.lsu_trap_flush[7:0]) |
| 7582 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 7583 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 7584 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 7585 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 7586 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 7587 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 7588 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 7589 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 7590 | endcase |
| 7591 | end |
| 7592 | endfunction |
| 7593 | |
| 7594 | function [8*11:0] DispPCXReq; |
| 7595 | input [129:0] pcx_pkt; |
| 7596 | begin |
| 7597 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 7598 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 7599 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 7600 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 7601 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 7602 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 7603 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 7604 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 7605 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 7606 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 7607 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 7608 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 7609 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 7610 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 7611 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 7612 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 7613 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 7614 | default: |
| 7615 | begin |
| 7616 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 7617 | DispPCXReq = " "; |
| 7618 | end |
| 7619 | endcase |
| 7620 | end |
| 7621 | endfunction |
| 7622 | |
| 7623 | function IsExc; |
| 7624 | input [2:0] core_id; |
| 7625 | reg [21*8:0] DispExc; |
| 7626 | |
| 7627 | begin |
| 7628 | DispExc = 170'b0; |
| 7629 | IsExc = 1'b0; |
| 7630 | |
| 7631 | if (`SPC3.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 7632 | if (`SPC3.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 7633 | if (`SPC3.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 7634 | if (`SPC3.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 7635 | if (`SPC3.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 7636 | if (`SPC3.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 7637 | //if (`SPC3.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 7638 | if (`SPC3.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 7639 | if (`SPC3.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 7640 | if (`SPC3.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 7641 | if (`SPC3.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 7642 | if (`SPC3.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 7643 | if (`SPC3.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 7644 | if (`SPC3.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 7645 | //if (`SPC3.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 7646 | if (`SPC3.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 7647 | if (`SPC3.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 7648 | if (`SPC3.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 7649 | |
| 7650 | |
| 7651 | if (DispExc != 0) |
| 7652 | begin |
| 7653 | IsExc = 1'b1; |
| 7654 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 7655 | end |
| 7656 | |
| 7657 | end |
| 7658 | endfunction |
| 7659 | |
| 7660 | function Is_exu_error; |
| 7661 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 7662 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 7663 | reg err_b; |
| 7664 | reg err_m; |
| 7665 | |
| 7666 | begin |
| 7667 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC3.lsu_tlb_bypass_b)): |
| 7668 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC3.lsu_tlb_bypass_b)); |
| 7669 | |
| 7670 | err_m = (dec_lsu_tid_b[2] ? `SPC3.exu_ecc_m[1] : `SPC3.exu_ecc_m[0]) & `SPC3.lsu.dcc.twocycle_b; |
| 7671 | |
| 7672 | Is_exu_error = err_b | err_m; |
| 7673 | end |
| 7674 | endfunction |
| 7675 | |
| 7676 | /* |
| 7677 | task Insert_tlb_miss_info; |
| 7678 | reg [127:0] tmp; |
| 7679 | begin |
| 7680 | tmp = 128'b0; |
| 7681 | if (tlb_valid[dec_lsu_tid_b]) |
| 7682 | begin |
| 7683 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 7684 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 7685 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 7686 | end |
| 7687 | else |
| 7688 | begin |
| 7689 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 7690 | tmp[`INST_VA] = inst_pc_b; |
| 7691 | tmp[`MEMOP_VA] = vaddr_b; |
| 7692 | tmp[`INST] = inst_b; |
| 7693 | end |
| 7694 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 7695 | end |
| 7696 | endtask |
| 7697 | |
| 7698 | */ |
| 7699 | |
| 7700 | //problem with the signal. |
| 7701 | /* |
| 7702 | always @ (negedge `SPC3.l2clk) |
| 7703 | begin |
| 7704 | if (mmu_dtlb_reload_d2) |
| 7705 | Chk_dtlb_reload; |
| 7706 | end |
| 7707 | |
| 7708 | task Chk_dtlb_reload; |
| 7709 | reg [2:0] thid; |
| 7710 | reg [127:0] tmp; |
| 7711 | begin |
| 7712 | if (`SPC3.tlu_trap_pc_0_valid) |
| 7713 | thid = {1'b0, `SPC3.tlu_trap_0_tid}; |
| 7714 | else if (`SPC3.tlu_trap_pc_1_valid) |
| 7715 | thid = {1'b0, `SPC3.tlu_trap_1_tid}; |
| 7716 | else |
| 7717 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 7718 | |
| 7719 | if (~tlb_valid[thid]) |
| 7720 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 7721 | else |
| 7722 | begin |
| 7723 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 7724 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 7725 | tlb_valid[thid] = 1'b0; |
| 7726 | end |
| 7727 | end |
| 7728 | endtask |
| 7729 | */ |
| 7730 | |
| 7731 | task Insert_ld_miss_info; |
| 7732 | reg [`LD_Pend_Width] tmp; |
| 7733 | begin |
| 7734 | tmp = 213'b0; |
| 7735 | if (ld_valid[dec_lsu_tid_b]) |
| 7736 | begin |
| 7737 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 7738 | DispPendReq(dec_lsu_tid_b); |
| 7739 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 7740 | end |
| 7741 | else |
| 7742 | begin |
| 7743 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 7744 | tmp[`INST_VA] = inst_pc_b; |
| 7745 | tmp[`MEMOP_VA] = vaddr_b; |
| 7746 | tmp[`MEMOP_PA] = {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 7747 | tmp[`INST_ASI] = asi_b; |
| 7748 | |
| 7749 | if (lsu_inst_b[`BLKLD]) |
| 7750 | begin |
| 7751 | tmp[`L2_ISS] = 4'h0; |
| 7752 | tmp[`L2_RESP] = 4'h0; |
| 7753 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 7754 | end |
| 7755 | else |
| 7756 | begin |
| 7757 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 7758 | if (lsu_inst_b[`CASA]) |
| 7759 | tmp[`L2_ISS] = 4'hC; |
| 7760 | else |
| 7761 | tmp[`L2_ISS] = 4'hE; |
| 7762 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 7763 | tmp[`L2_RESP] = 4'hC; |
| 7764 | else |
| 7765 | tmp[`L2_RESP] = 4'hE; |
| 7766 | |
| 7767 | end |
| 7768 | |
| 7769 | tmp[`INST] = inst_b; |
| 7770 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 7771 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 7772 | end |
| 7773 | end |
| 7774 | endtask |
| 7775 | |
| 7776 | |
| 7777 | task Insert_in_last_inst_array; |
| 7778 | reg [135:0] tmp; |
| 7779 | begin |
| 7780 | tmp = 128'b0; |
| 7781 | tmp[`INST_VA] = inst_pc_b; |
| 7782 | tmp[`MEMOP_VA] = vaddr_b; |
| 7783 | tmp[`INST] = inst_b; |
| 7784 | tmp[135:128] = asi_b; |
| 7785 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 7786 | end |
| 7787 | endtask |
| 7788 | |
| 7789 | |
| 7790 | task DispPendReq; |
| 7791 | input [2:0] thid; |
| 7792 | reg [`LD_Pend_Width] tmp; |
| 7793 | begin |
| 7794 | |
| 7795 | tmp = ld_pend_array[thid]; |
| 7796 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 7797 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 7798 | end |
| 7799 | endtask |
| 7800 | |
| 7801 | task Disp_STB_entry; |
| 7802 | input [2:0] thid; |
| 7803 | input [2:0] ptr; |
| 7804 | reg [204:0] tmp; |
| 7805 | begin |
| 7806 | |
| 7807 | tmp = stb[{thid, ptr}]; |
| 7808 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 7809 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 7810 | end |
| 7811 | endtask |
| 7812 | |
| 7813 | /* |
| 7814 | |
| 7815 | task Disp_tlbmiss_pend_array_entry; |
| 7816 | input [2:0] thid; |
| 7817 | reg [127:0] tmp; |
| 7818 | begin |
| 7819 | tmp = tlbmiss_pend_array[thid]; |
| 7820 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 7821 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 7822 | |
| 7823 | end |
| 7824 | endtask |
| 7825 | |
| 7826 | */ |
| 7827 | task Disp_CPX_pkt; |
| 7828 | input [145:0] cpx_pkt; |
| 7829 | begin |
| 7830 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 7831 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 7832 | end |
| 7833 | endtask |
| 7834 | |
| 7835 | |
| 7836 | task Make_STB_data; |
| 7837 | reg [204:0] tmp; |
| 7838 | begin |
| 7839 | tmp = 0; |
| 7840 | tmp[`INST_VA] = inst_pc_b; |
| 7841 | tmp[`MEMOP_VA] = vaddr_b; |
| 7842 | tmp[`MEMOP_PA] = {`SPC3.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 7843 | tmp[`L2_ST_ISS] = 1'b0; |
| 7844 | tmp[`ASI_ST_ISS] = 1'b0; |
| 7845 | tmp[`L2_ACK] = 1'b0; |
| 7846 | tmp[`INST] = inst_b; |
| 7847 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 7848 | tmp[`ST_SQUASH] = 1'b0; |
| 7849 | tmp[`INST_ASI] = asi_b; |
| 7850 | if (`SPC3.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 7851 | tmp[`ST_PRIV] = `HPRIV; |
| 7852 | else if (`SPC3.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 7853 | tmp[`ST_PRIV] = `PRIV; |
| 7854 | else |
| 7855 | tmp[`ST_PRIV] = `USER; |
| 7856 | //bis_asi to io space is not rmo |
| 7857 | |
| 7858 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC3.lsu.tlb_pgnum[39]); |
| 7859 | stb_alloc_data <= tmp; |
| 7860 | end |
| 7861 | endtask |
| 7862 | |
| 7863 | task Insert_in_STB; |
| 7864 | input [195:0] store_data; |
| 7865 | input [2:0] thid; |
| 7866 | begin |
| 7867 | if (stb_full(thid)) |
| 7868 | begin |
| 7869 | //DispSTB(thid); |
| 7870 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 7871 | end |
| 7872 | else |
| 7873 | begin |
| 7874 | stb[{thid, wrptr[thid]}] = store_data; |
| 7875 | //Disp_STB_entry(thid, wrptr[thid]); |
| 7876 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 7877 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 7878 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 7879 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 7880 | end |
| 7881 | end |
| 7882 | endtask |
| 7883 | |
| 7884 | function stb_full; |
| 7885 | input [2:0] thid; |
| 7886 | begin |
| 7887 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 7888 | stb_full = 1'b1; |
| 7889 | else |
| 7890 | stb_full = 1'b0; |
| 7891 | end |
| 7892 | endfunction |
| 7893 | |
| 7894 | |
| 7895 | task Dealloc_STB; |
| 7896 | input [2:0] thid; |
| 7897 | reg [204:0] tmp; |
| 7898 | reg [20:0] lsu_inst; |
| 7899 | begin |
| 7900 | //thid = decode_tid(`SPC3.lsu_stb_dealloc); |
| 7901 | tmp = stb[{thid, rdptr[thid]}]; |
| 7902 | lsu_inst = tmp[`LSU_MON_INST]; |
| 7903 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 7904 | begin |
| 7905 | //DispSTB(thid); |
| 7906 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC3.lsu_stb_dealloc); |
| 7907 | end |
| 7908 | if (tmp[`L2_ST_ISS]) |
| 7909 | begin |
| 7910 | if (~tmp[`L2_ACK]) |
| 7911 | begin |
| 7912 | Disp_STB_entry(thid, rdptr[thid]); |
| 7913 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC3.lsu_stb_dealloc); |
| 7914 | end |
| 7915 | end |
| 7916 | else if (tmp[`ASI_ST_ISS]) |
| 7917 | begin |
| 7918 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 7919 | end |
| 7920 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 7921 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 7922 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 7923 | // and deallocated. |
| 7924 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 7925 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 7926 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 7927 | begin |
| 7928 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 7929 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 7930 | end |
| 7931 | else |
| 7932 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC3.lsu_stb_dealloc); |
| 7933 | |
| 7934 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 7935 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 7936 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 7937 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 7938 | /* |
| 7939 | if (tmp[`RMO]) |
| 7940 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 7941 | */ |
| 7942 | end |
| 7943 | endtask |
| 7944 | |
| 7945 | task Squash_STB; |
| 7946 | input [2:0] thid; |
| 7947 | reg [204:0] tmp; |
| 7948 | reg [3:0] squash_cnt; |
| 7949 | reg [2:0] i; |
| 7950 | begin |
| 7951 | squash_cnt = 4'b0; |
| 7952 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 7953 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 7954 | if (rdptr[thid] != iss_ptr[thid]) |
| 7955 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 7956 | |
| 7957 | if (iss_ptr[thid] == wrptr[thid]) |
| 7958 | begin |
| 7959 | if (stb_valid[{thid, wrptr[thid]}]) |
| 7960 | squash_cnt = 8; |
| 7961 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 7962 | * |
| 7963 | else |
| 7964 | begin |
| 7965 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 7966 | end |
| 7967 | */ |
| 7968 | end |
| 7969 | else |
| 7970 | begin |
| 7971 | if (iss_ptr[thid] < wrptr[thid]) |
| 7972 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 7973 | else if (iss_ptr[thid] > wrptr[thid]) |
| 7974 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 7975 | end |
| 7976 | |
| 7977 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 7978 | |
| 7979 | i = iss_ptr[thid]; |
| 7980 | |
| 7981 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 7982 | |
| 7983 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 7984 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 7985 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 7986 | |
| 7987 | while (squash_cnt) |
| 7988 | begin |
| 7989 | tmp = stb[{thid, i}]; |
| 7990 | if (~stb_valid[{thid, i}]) |
| 7991 | begin |
| 7992 | //DispSTB(thid); |
| 7993 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 7994 | end |
| 7995 | if (tmp[`L2_ST_ISS]) |
| 7996 | begin |
| 7997 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 7998 | end |
| 7999 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 8000 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 8001 | //set in the chkr which was causin it to fire. |
| 8002 | //if (~tmp[`ST_SQUASH]) |
| 8003 | //begin |
| 8004 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 8005 | //end |
| 8006 | stb_valid[{thid, i}] = 1'b0; |
| 8007 | |
| 8008 | i = i + 1; |
| 8009 | squash_cnt = squash_cnt - 1'b1; |
| 8010 | end |
| 8011 | |
| 8012 | end |
| 8013 | endtask |
| 8014 | |
| 8015 | task Chk_store; |
| 8016 | reg [2:0] thid; |
| 8017 | reg [47:0] addr; |
| 8018 | reg [3:0] i; |
| 8019 | reg [204:0] tmp; |
| 8020 | begin |
| 8021 | if ((bst_cnt > 0) && (`SPC3.lsu_stb_alloc == 8'b0)) |
| 8022 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 8023 | |
| 8024 | //For bst the stb is still written even though we have errors. |
| 8025 | //Stb is written in W stage. Howvere for first blk store helper |
| 8026 | //the err will be flagged by FGU in b stage. We can miss the |
| 8027 | // err signal if we don't sample in B. |
| 8028 | //for the last helper err will be signalled in B stage of last helper and at |
| 8029 | |
| 8030 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 8031 | bst_fgu_err = 1'b1; |
| 8032 | |
| 8033 | if (`SPC3.lsu_stb_alloc[7:0] != 8'b0) |
| 8034 | begin |
| 8035 | thid = decode_tid(`SPC3.lsu_stb_alloc[7:0]); |
| 8036 | if (store_alloc) |
| 8037 | begin |
| 8038 | if (thid != dec_lsu_tid_w) |
| 8039 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC3.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 8040 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 8041 | end |
| 8042 | else |
| 8043 | begin |
| 8044 | if (lsu_bst_active[thid]) |
| 8045 | begin |
| 8046 | if (bst_cnt == 0) |
| 8047 | begin |
| 8048 | bst_data = bst_inst_data; |
| 8049 | end |
| 8050 | else |
| 8051 | begin |
| 8052 | if (thid != bst_active_thid) |
| 8053 | begin |
| 8054 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC3.lsu_stb_alloc[7:0], bst_active_thid); |
| 8055 | end |
| 8056 | |
| 8057 | addr = bst_data[`MEMOP_VA]; |
| 8058 | |
| 8059 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 8060 | addr = bst_data[`MEMOP_PA]; |
| 8061 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 8062 | end |
| 8063 | bst_cnt = bst_cnt + 1; |
| 8064 | Insert_in_STB(bst_data, bst_active_thid); |
| 8065 | if (bst_cnt == 8) |
| 8066 | begin |
| 8067 | bst_cnt = 0; |
| 8068 | lsu_bst_active[thid] = 1'b0; |
| 8069 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 8070 | begin |
| 8071 | for (i = 0; i < 8; i=i+1) |
| 8072 | begin |
| 8073 | tmp = stb[{thid, i[2:0]}]; |
| 8074 | if (tmp[`ST_SQUASH]) |
| 8075 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 8076 | tmp[`ST_SQUASH] = 1'b1; |
| 8077 | stb[{thid, i[2:0]}] = tmp; |
| 8078 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 8079 | end |
| 8080 | end |
| 8081 | bst_fgu_err = 1'b0; |
| 8082 | end |
| 8083 | end |
| 8084 | else |
| 8085 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC3.lsu_stb_alloc[7:0]); |
| 8086 | |
| 8087 | end |
| 8088 | end |
| 8089 | else |
| 8090 | begin |
| 8091 | if (store_alloc) |
| 8092 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 8093 | end |
| 8094 | end |
| 8095 | endtask |
| 8096 | |
| 8097 | task Chk_st_on_ASI_ring; |
| 8098 | input ring; |
| 8099 | reg [2:0] thid; |
| 8100 | reg [7:0] asi; |
| 8101 | reg [47:0] addr, act_addr; |
| 8102 | reg [1:0] req_type; |
| 8103 | reg [204:0] tmp; |
| 8104 | |
| 8105 | begin |
| 8106 | if (ring == `LOCAL) |
| 8107 | thid =`SPC3.lsu_rngl_cdbus[58:56]; |
| 8108 | else |
| 8109 | thid =`SPC3.lsu_rngf_cdbus[58:56]; |
| 8110 | |
| 8111 | if (ring == `LOCAL) |
| 8112 | asi =`SPC3.lsu_rngl_cdbus[55:48]; |
| 8113 | else |
| 8114 | asi =`SPC3.lsu_rngf_cdbus[55:48]; |
| 8115 | |
| 8116 | if (ring == `LOCAL) |
| 8117 | addr =`SPC3.lsu_rngl_cdbus[47:0]; |
| 8118 | else |
| 8119 | addr =`SPC3.lsu_rngf_cdbus[47:0]; |
| 8120 | |
| 8121 | if (ring == `LOCAL) |
| 8122 | req_type =`SPC3.lsu_rngl_cdbus[61:60]; |
| 8123 | else |
| 8124 | req_type =`SPC3.lsu_rngf_cdbus[61:60]; |
| 8125 | |
| 8126 | |
| 8127 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 8128 | if (tmp[`ASI_ST_ISS]) |
| 8129 | begin |
| 8130 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8131 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 8132 | end |
| 8133 | |
| 8134 | if (tmp[`ST_SQUASH]) |
| 8135 | begin |
| 8136 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8137 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 8138 | end |
| 8139 | |
| 8140 | act_addr = tmp[`MEMOP_PA]; |
| 8141 | act_addr = {act_addr[39:3], 3'b0}; |
| 8142 | |
| 8143 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 8144 | //the address. |
| 8145 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 8146 | begin |
| 8147 | tmp[`ASI_ST_ISS] = 1'b1; |
| 8148 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 8149 | if (ring == `LOCAL) |
| 8150 | begin |
| 8151 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 8152 | end |
| 8153 | else |
| 8154 | begin |
| 8155 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 8156 | end |
| 8157 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 8158 | end |
| 8159 | else |
| 8160 | begin |
| 8161 | if (ring == `LOCAL) |
| 8162 | begin |
| 8163 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 8164 | end |
| 8165 | else |
| 8166 | begin |
| 8167 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 8168 | end |
| 8169 | end |
| 8170 | |
| 8171 | end |
| 8172 | endtask |
| 8173 | |
| 8174 | |
| 8175 | task chk_store_issue_to_pcx; |
| 8176 | input [129:0] pcx_pkt; |
| 8177 | reg [2:0] thid; |
| 8178 | reg [204:0] tmp; |
| 8179 | reg [20:0] inst; |
| 8180 | reg [39:0] pcx_pa, inst_pa; |
| 8181 | begin |
| 8182 | thid = pcx_pkt[`PCX_THR_ID]; |
| 8183 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 8184 | inst = tmp[`LSU_MON_INST]; |
| 8185 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 8186 | inst_pa = tmp[`MEMOP_PA]; |
| 8187 | |
| 8188 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 8189 | begin |
| 8190 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 8191 | end |
| 8192 | if (pcx_pkt[`PCX_INV]) |
| 8193 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 8194 | |
| 8195 | |
| 8196 | if (~inst[`ST]) |
| 8197 | begin |
| 8198 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8199 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8200 | end |
| 8201 | |
| 8202 | /* CONFIRM WITH MARK |
| 8203 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 8204 | begin |
| 8205 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8206 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 8207 | end |
| 8208 | */ |
| 8209 | //enhancement req 100146 |
| 8210 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 8211 | begin |
| 8212 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8213 | end |
| 8214 | |
| 8215 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 8216 | begin |
| 8217 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8218 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8219 | end |
| 8220 | |
| 8221 | if (tmp[`L2_ST_ISS]) |
| 8222 | begin |
| 8223 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8224 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8225 | end |
| 8226 | else |
| 8227 | tmp[`L2_ST_ISS] = 1'b1; |
| 8228 | |
| 8229 | if (tmp[`ST_SQUASH]) |
| 8230 | begin |
| 8231 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8232 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8233 | end |
| 8234 | |
| 8235 | if (tmp[`RMO]) |
| 8236 | begin |
| 8237 | if (~pcx_pkt[`PCX_BIS]) |
| 8238 | begin |
| 8239 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8240 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8241 | end |
| 8242 | if (tmp[`L2_ACK]) |
| 8243 | begin |
| 8244 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8245 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 8246 | end |
| 8247 | else |
| 8248 | begin |
| 8249 | tmp[`L2_ACK] = 1'b1; |
| 8250 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 8251 | //response seen from stub |
| 8252 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 8253 | end |
| 8254 | end |
| 8255 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 8256 | |
| 8257 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 8258 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 8259 | end |
| 8260 | endtask |
| 8261 | |
| 8262 | `ifdef INJ_STB_ERR_IN_CMP |
| 8263 | |
| 8264 | |
| 8265 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 8266 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 8267 | reg [204:0] err_tmp ; |
| 8268 | reg [20:0] err_inst; |
| 8269 | reg [44:0] cam_data; |
| 8270 | reg [5:0] err_bit; |
| 8271 | integer err_inj_cnt; |
| 8272 | reg cmp_stb_err_inj; |
| 8273 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 8274 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 8275 | |
| 8276 | initial |
| 8277 | begin |
| 8278 | cmp_stb_err_inj = 1'b0; |
| 8279 | |
| 8280 | cam_data = 45'b0; |
| 8281 | err_bit = 11; |
| 8282 | err_inj_cnt = 0; |
| 8283 | stb_err_inj = 0; |
| 8284 | if (("cmp_stb_err_inj_on")) |
| 8285 | cmp_stb_err_inj = 1'b1; |
| 8286 | else |
| 8287 | cmp_stb_err_inj = 1'b0; |
| 8288 | end |
| 8289 | |
| 8290 | always @ (negedge (`SPC3.l2clk & enabled & cmp_stb_err_inj)) |
| 8291 | begin //{ |
| 8292 | //valid stb ram rd for issue to pcx |
| 8293 | stb_err_inj = 1'b0; |
| 8294 | if (`SPC3.lsu.sbc.ram_rptr_vld_2 & `SPC3.lsu.sbc.st_pcx_rq_p3 & `SPC3.lsu.pic.pic_st_sel_p3) |
| 8295 | begin //{ |
| 8296 | err_tid = decode_tid(`SPC3.lsu.sbc.st_rq_sel_p3[7:0]); |
| 8297 | err_index = `SPC3.lsu.sbc.ram_rptr_d1; |
| 8298 | err_tmp = stb[{err_tid, err_index}]; |
| 8299 | err_inst = err_tmp[`LSU_MON_INST]; |
| 8300 | cam_data = `SPC3.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 8301 | err_priv = err_tmp[`ST_PRIV]; |
| 8302 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 8303 | if (err_inst[`CASA]) |
| 8304 | begin //{ |
| 8305 | err_inj_cnt = err_inj_cnt + 1; |
| 8306 | if (err_inj_cnt == 10) |
| 8307 | begin //{ |
| 8308 | case (err_bit) |
| 8309 | 11, 12: err_bit = err_bit + 1; |
| 8310 | 13: err_bit = 44; |
| 8311 | 44: err_bit = 11; |
| 8312 | endcase |
| 8313 | err_inj_cnt = 0; |
| 8314 | stb_err_inj = 1'b1; |
| 8315 | |
| 8316 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 8317 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 8318 | #1; |
| 8319 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 8320 | end //} |
| 8321 | end //} |
| 8322 | end //} |
| 8323 | if (stb_err_inj_d2) |
| 8324 | begin |
| 8325 | if (~`SPC3.lsu_sbapp_err_g) |
| 8326 | begin |
| 8327 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 8328 | end |
| 8329 | else |
| 8330 | begin |
| 8331 | if ((`SPC3.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 8332 | (`SPC3.lsu_stberr_index_g != stb_err_index_d2) || |
| 8333 | (`SPC3.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 8334 | begin |
| 8335 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 8336 | end |
| 8337 | end |
| 8338 | end |
| 8339 | else |
| 8340 | begin |
| 8341 | if (`SPC3.lsu_sbapp_err_g) |
| 8342 | begin |
| 8343 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC3.lsu_stberr_tid_g); |
| 8344 | end |
| 8345 | end |
| 8346 | |
| 8347 | end //} |
| 8348 | |
| 8349 | |
| 8350 | always @ (posedge (`SPC3.l2clk & enabled & cmp_stb_err_inj)) |
| 8351 | begin |
| 8352 | stb_err_inj_d1 <= stb_err_inj; |
| 8353 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 8354 | stb_err_tid_d1 <= err_tid; |
| 8355 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 8356 | stb_err_index_d1 <= err_index; |
| 8357 | stb_err_index_d2 <= stb_err_index_d1; |
| 8358 | stb_err_priv_d1 <= err_priv; |
| 8359 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 8360 | end |
| 8361 | |
| 8362 | `endif |
| 8363 | `endif |
| 8364 | `endif |
| 8365 | endmodule |
| 8366 | |
| 8367 | `endif |
| 8368 | `ifdef CORE_4 |
| 8369 | |
| 8370 | module lsu_mon_c4; |
| 8371 | `ifndef GATESIM |
| 8372 | |
| 8373 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 8374 | `ifndef NO_MONITORS |
| 8375 | |
| 8376 | reg imm_asi_vld_e; |
| 8377 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 8378 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 8379 | reg [1:0] exu_ecc_b; |
| 8380 | reg [1:0] exu_lsu_va_error_b; |
| 8381 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 8382 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 8383 | reg [31:0] inst_e, inst_m, inst_b; |
| 8384 | reg [47:0] vaddr_m, vaddr_b; |
| 8385 | reg [63:0] int_st_data_m, int_st_data_b; |
| 8386 | reg [63:0] fp_st_sata_fx2; |
| 8387 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 8388 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 8389 | |
| 8390 | reg [7:0] ld_valid; |
| 8391 | reg [7:0] tlb_valid; |
| 8392 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 8393 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 8394 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 8395 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 8396 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 8397 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 8398 | //the L2c. |
| 8399 | reg [63:0] stb_valid; |
| 8400 | reg [`STB_Pend_Width] stb[63:0]; |
| 8401 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 8402 | |
| 8403 | reg [7:0] pf_cnt[7:0]; |
| 8404 | reg [7:0] dcache_inv_cnt[7:0]; |
| 8405 | reg [7:0] st_rmo_cnt[7:0]; |
| 8406 | |
| 8407 | reg [55:0] print_inst; |
| 8408 | |
| 8409 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 8410 | |
| 8411 | reg [7:0] lsu_bst_active; |
| 8412 | reg store_alloc; |
| 8413 | reg [3:0] bst_cnt; |
| 8414 | reg [195:0] stb_alloc_data; |
| 8415 | reg [195:0] bst_data, bst_inst_data; |
| 8416 | reg [2:0] bst_active_thid; |
| 8417 | reg bst_fgu_err; |
| 8418 | |
| 8419 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 8420 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 8421 | //different types of err occur on blk ld helper returns |
| 8422 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 8423 | //stored in DFESR |
| 8424 | |
| 8425 | wire [2:0] core_id = 4; |
| 8426 | |
| 8427 | integer i; |
| 8428 | integer err_cnt; |
| 8429 | |
| 8430 | reg enabled; |
| 8431 | reg reset_in_middle; |
| 8432 | reg [7:0] finish_mask; |
| 8433 | |
| 8434 | initial |
| 8435 | begin |
| 8436 | enabled = 0; |
| 8437 | reset_in_middle = 0; |
| 8438 | ld_valid = 8'b0; |
| 8439 | lsu_inst_e = 0; |
| 8440 | tlb_valid = 8'b0; |
| 8441 | for (i = 0; i < 8; i = i+1) |
| 8442 | begin |
| 8443 | pf_cnt[i] = 0; |
| 8444 | dcache_inv_cnt[i] = 0; |
| 8445 | wrptr[i] = 0; |
| 8446 | rdptr[i] = 0; |
| 8447 | iss_ptr[i] = 0; |
| 8448 | ret_ptr[i] = 0; |
| 8449 | st_rmo_cnt[i] = 0; |
| 8450 | is_blkld[i] = 1'b0; |
| 8451 | st_priv[i] = 2'b0; |
| 8452 | l2_blk_ld_errtype[i] = 2'b0; |
| 8453 | end |
| 8454 | lsu_bst_active = 8'b0; |
| 8455 | store_alloc = 1'b0; |
| 8456 | bst_cnt = 4'b0; |
| 8457 | stb_valid = 64'b0; |
| 8458 | |
| 8459 | // avoid time zero ugliness. jp |
| 8460 | //@(posedge `SPC0.l2clk); |
| 8461 | //@(negedge `SPC0.l2clk); |
| 8462 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 8463 | |
| 8464 | case (core_id) |
| 8465 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 8466 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 8467 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 8468 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 8469 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 8470 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 8471 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 8472 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 8473 | endcase |
| 8474 | end |
| 8475 | |
| 8476 | always @ (`TOP.in_reset) |
| 8477 | begin |
| 8478 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 8479 | begin |
| 8480 | enabled = 1'b1; |
| 8481 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 8482 | end |
| 8483 | |
| 8484 | |
| 8485 | if (`TOP.in_reset & enabled) |
| 8486 | begin |
| 8487 | reset_in_middle = 1'b1; |
| 8488 | enabled = 1'b0; |
| 8489 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 8490 | end |
| 8491 | end |
| 8492 | |
| 8493 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 8494 | begin //{ |
| 8495 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 8496 | begin //{ |
| 8497 | for (i = 0; i < 8; i=i+1) |
| 8498 | begin |
| 8499 | if (ld_valid[i]) |
| 8500 | begin |
| 8501 | DispPendReq(i); |
| 8502 | end |
| 8503 | end |
| 8504 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 8505 | end //} |
| 8506 | if (|stb_valid[63:0]) |
| 8507 | begin //{ |
| 8508 | err_cnt = 0; |
| 8509 | for (i = 0; i < 64; i=i+1) |
| 8510 | begin |
| 8511 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 8512 | begin |
| 8513 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 8514 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 8515 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 8516 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 8517 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 8518 | //of simualation. |
| 8519 | if (~is_squash_bit_set(i[5:0])) |
| 8520 | begin |
| 8521 | err_cnt = err_cnt + 1; |
| 8522 | Disp_STB_entry(i[5:3],i[2:0]); |
| 8523 | end |
| 8524 | end |
| 8525 | end |
| 8526 | if (err_cnt) |
| 8527 | begin |
| 8528 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 8529 | end |
| 8530 | end //} |
| 8531 | err_cnt = 0; |
| 8532 | for (i = 0; i < 8; i=i+1) |
| 8533 | begin //{ |
| 8534 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 8535 | begin |
| 8536 | err_cnt = 1; |
| 8537 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 8538 | end |
| 8539 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 8540 | begin |
| 8541 | err_cnt = 1; |
| 8542 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 8543 | end |
| 8544 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 8545 | begin |
| 8546 | err_cnt = 1; |
| 8547 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 8548 | end |
| 8549 | end //} |
| 8550 | if (err_cnt) |
| 8551 | begin |
| 8552 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 8553 | end |
| 8554 | end //} |
| 8555 | |
| 8556 | function is_squash_bit_set; |
| 8557 | input [5:0] index; |
| 8558 | reg [204:0] tmp; |
| 8559 | begin |
| 8560 | tmp = stb[index]; |
| 8561 | if (tmp[`ST_SQUASH]) |
| 8562 | is_squash_bit_set = 1'b1; |
| 8563 | else |
| 8564 | is_squash_bit_set = 1'b0; |
| 8565 | end |
| 8566 | endfunction |
| 8567 | |
| 8568 | |
| 8569 | always @ (negedge (`SPC4.l2clk & enabled)) |
| 8570 | begin //{ |
| 8571 | |
| 8572 | asi_e = `SPC4.lsu.dcc.dcc_asi_e[7:0]; |
| 8573 | |
| 8574 | lsu_inst_e[`LD] <= `SPC4.dec_ld_inst_e; |
| 8575 | lsu_inst_e[`ST] <= `SPC4.dec_st_inst_e; |
| 8576 | lsu_inst_e[`FP] <= `SPC4.dec_fpldst_inst_e; |
| 8577 | lsu_inst_e[`PREF] <= `SPC4.dec_pref_inst_e; |
| 8578 | lsu_inst_e[`SWAP] <= `SPC4.dec_swap_inst_e; |
| 8579 | lsu_inst_e[`CASA] <= `SPC4.dec_casa_inst_e; |
| 8580 | lsu_inst_e[`LDSTUB] <= `SPC4.dec_ldstub_inst_e; |
| 8581 | lsu_inst_e[`FLUSH] <= `SPC4.dec_flush_inst_e; |
| 8582 | lsu_inst_e[`MEMBAR] <= `SPC4.dec_memstbar_inst_e; |
| 8583 | lsu_inst_e[`LDD] <= `SPC4.dec_ld_inst_e & `SPC4.dec_ldst_dbl_e & ~`SPC4.dec_fpldst_inst_e; |
| 8584 | lsu_inst_e[`STD] <= `SPC4.dec_st_inst_e & `SPC4.dec_ldst_dbl_e & ~`SPC4.lsu.dec_fpldst_inst_e; |
| 8585 | |
| 8586 | lsu_inst_e[`BLKLD] <= `SPC4.dec_ld_inst_e & `SPC4.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 8587 | lsu_inst_e[`BLKST] <= `SPC4.dec_st_inst_e & `SPC4.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 8588 | lsu_inst_e[`QLD] <= `SPC4.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 8589 | lsu_inst_e[`ASR_RD_WR] <= `SPC4.dec_sr_inst_e & (`SPC4.dec_ld_inst_e | `SPC4.dec_st_inst_e); |
| 8590 | lsu_inst_e[`PR_RD_WR] <= `SPC4.dec_pr_inst_e & (`SPC4.dec_ld_inst_e | `SPC4.dec_st_inst_e); |
| 8591 | lsu_inst_e[`HPR_RD_WR] <= `SPC4.dec_hpr_inst_e & (`SPC4.dec_ld_inst_e | `SPC4.dec_st_inst_e); |
| 8592 | lsu_inst_e[`FSR_RD_WR] <= `SPC4.dec_fsr_ldst_e & (`SPC4.dec_ld_inst_e | `SPC4.dec_st_inst_e); |
| 8593 | end //} |
| 8594 | |
| 8595 | always @ (posedge (`SPC4.l2clk & enabled)) |
| 8596 | begin //{ |
| 8597 | dec_tg0_inst_d <= `SPC4.dec.ded0.decode_mux[31:0]; |
| 8598 | dec_tg1_inst_d <= `SPC4.dec.ded1.decode_mux[31:0]; |
| 8599 | imm_asi_vld_e <= `SPC4.lsu.dec_imm_asi_vld_d; |
| 8600 | |
| 8601 | imm_asi_e <= `SPC4.lsu.dec_imm_asi_d; |
| 8602 | dec_altspace_e <= `SPC4.dec_altspace_d; |
| 8603 | dec_altspace_m <= dec_altspace_e; |
| 8604 | dec_altspace_b <= dec_altspace_m; |
| 8605 | |
| 8606 | exu_ecc_b <= `SPC4.exu_ecc_m; |
| 8607 | exu_lsu_va_error_b <= `SPC4.exu_lsu_va_error_m; |
| 8608 | |
| 8609 | dec_lsu_tid_e <= `SPC4.dec_lsu_tg_d ? {1'b1, `SPC4.dec_lsu_tid1_d} : {1'b0, `SPC4.dec_lsu_tid0_d}; |
| 8610 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 8611 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 8612 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 8613 | |
| 8614 | inst_pc_e <= `SPC4.dec_lsu_tg_d ? {`SPC4.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC4.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 8615 | inst_pc_m <= inst_pc_e; |
| 8616 | inst_pc_b <= inst_pc_m; |
| 8617 | inst_pc_w <= inst_pc_b; |
| 8618 | |
| 8619 | inst_e <= `SPC4.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 8620 | inst_m <= inst_e; |
| 8621 | inst_b <= inst_m; |
| 8622 | |
| 8623 | vaddr_m <= `SPC4.exu_lsu_address_e; |
| 8624 | vaddr_b <= vaddr_m; |
| 8625 | |
| 8626 | int_st_data_m <= `SPC4.exu_lsu_store_data_e; |
| 8627 | int_st_data_b <= int_st_data_m; |
| 8628 | fp_st_sata_fx2 <= `SPC4.fgu_lsu_fst_data_fx1; |
| 8629 | |
| 8630 | mmu_dtlb_reload_d1 <= `SPC4.mmu_dtlb_reload; |
| 8631 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 8632 | |
| 8633 | //pcx_thid_d1 <= `SPC4.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 8634 | lsu_inst_m <= lsu_inst_e; |
| 8635 | lsu_inst_b <= lsu_inst_m; |
| 8636 | |
| 8637 | asi_m <= asi_e; |
| 8638 | asi_b <= asi_m; |
| 8639 | end //} |
| 8640 | |
| 8641 | function Is_blk_asi; |
| 8642 | input [7:0] asi; |
| 8643 | begin |
| 8644 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 8645 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 8646 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 8647 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 8648 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 8649 | end |
| 8650 | endfunction |
| 8651 | |
| 8652 | function Is_qld_asi; |
| 8653 | input [7:0] asi; |
| 8654 | begin |
| 8655 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 8656 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 8657 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 8658 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 8659 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 8660 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 8661 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 8662 | end |
| 8663 | endfunction |
| 8664 | |
| 8665 | function Is_bis_asi; |
| 8666 | input [7:0] asi; |
| 8667 | begin |
| 8668 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 8669 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 8670 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 8671 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 8672 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 8673 | end |
| 8674 | endfunction |
| 8675 | |
| 8676 | always @ (negedge (`SPC4.l2clk & enabled)) |
| 8677 | begin //{ |
| 8678 | Chk_store; |
| 8679 | store_alloc = 1'b0; |
| 8680 | if (lsu_inst_m != 0) |
| 8681 | begin |
| 8682 | if (`SPC4.dec_flush_lm) |
| 8683 | begin |
| 8684 | lsu_inst_m <= 0; |
| 8685 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 8686 | end |
| 8687 | end |
| 8688 | |
| 8689 | if (lsu_inst_b != 0) |
| 8690 | begin //{ |
| 8691 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 8692 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 8693 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 8694 | else print_inst = ""; |
| 8695 | |
| 8696 | if (`SPC4.dec_flush_lb) |
| 8697 | begin |
| 8698 | lsu_inst_b <= 0; |
| 8699 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 8700 | end |
| 8701 | else if (`SPC4.tlu_flush_lsu_b) |
| 8702 | begin |
| 8703 | lsu_inst_b <= 0; |
| 8704 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 8705 | end |
| 8706 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 8707 | //casa shd be killed. |
| 8708 | //This function will also chk for errors on 2nd cycle. |
| 8709 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 8710 | begin |
| 8711 | lsu_inst_b <= 0; |
| 8712 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 8713 | end |
| 8714 | else if ((`SPC4.fgu_cecc_fx2 || `SPC4.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 8715 | begin |
| 8716 | lsu_inst_b <= 0; |
| 8717 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 8718 | end |
| 8719 | else if (IsExc(core_id)) |
| 8720 | lsu_inst_b <= 0; |
| 8721 | else if (!`SPC4.lsu_tlb_miss_b_) |
| 8722 | begin |
| 8723 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 8724 | //Insert_tlb_miss_info; |
| 8725 | end |
| 8726 | else |
| 8727 | begin //{ |
| 8728 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 8729 | //an exception tlu anyway tells the front end to flush itself there is |
| 8730 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 8731 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 8732 | //handles it when it is reissued by the front end. |
| 8733 | |
| 8734 | if (`SPC4.lsu_tlb_bypass_b) |
| 8735 | begin |
| 8736 | if (`SPC4.lsu_sync != 8'b0) |
| 8737 | begin |
| 8738 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 8739 | end |
| 8740 | else |
| 8741 | begin |
| 8742 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 8743 | end |
| 8744 | end |
| 8745 | else |
| 8746 | begin |
| 8747 | if (`SPC4.lsu_sync != 8'b0) |
| 8748 | begin |
| 8749 | if (lsu_inst_b[`ST]) |
| 8750 | begin |
| 8751 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 8752 | end |
| 8753 | else |
| 8754 | begin |
| 8755 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 8756 | end |
| 8757 | end |
| 8758 | else |
| 8759 | begin |
| 8760 | if (lsu_inst_b[`ST]) |
| 8761 | begin |
| 8762 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 8763 | end |
| 8764 | else |
| 8765 | begin |
| 8766 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 8767 | end |
| 8768 | end |
| 8769 | end |
| 8770 | |
| 8771 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 8772 | begin //{ |
| 8773 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC4.lsu.stb_cam_hit) |
| 8774 | begin |
| 8775 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 8776 | end |
| 8777 | end //} |
| 8778 | |
| 8779 | if (lsu_inst_b[`LD]) |
| 8780 | Insert_ld_miss_info; |
| 8781 | |
| 8782 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 8783 | begin |
| 8784 | Make_STB_data; |
| 8785 | store_alloc = 1'b1; |
| 8786 | end |
| 8787 | Insert_in_last_inst_array; |
| 8788 | |
| 8789 | if (`SPC4.lsu_trap_flush[7:0]) |
| 8790 | begin |
| 8791 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC4.lsu_trap_flush[7:0])); |
| 8792 | end |
| 8793 | end //} |
| 8794 | end //} |
| 8795 | end //} |
| 8796 | |
| 8797 | //STB ue testing: |
| 8798 | //This is how we test squashing of stores by LSU_mon: |
| 8799 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 8800 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 8801 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 8802 | //The squashed stores are deallocated when either a block_store_kill is |
| 8803 | //asserted or dealloc signals are asserted by the LSU. |
| 8804 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 8805 | //all the pending stores in the IFU. It means the when block_store_kill |
| 8806 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 8807 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 8808 | //the sbdiou signal to TLU. |
| 8809 | |
| 8810 | |
| 8811 | always @ (negedge (`SPC4.l2clk & enabled)) |
| 8812 | begin |
| 8813 | if (`SPC4.lsu_l15_valid & `SPC4.lsu.spc_pcx_data_pa[129]) |
| 8814 | Chk_pcx_req_pkt(`SPC4.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 8815 | if ((`SPC4.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC4.lsu_rngl_cdbus[59]) |
| 8816 | Chk_st_on_ASI_ring(`LOCAL); |
| 8817 | |
| 8818 | if ((`SPC4.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC4.lsu_rngf_cdbus[59]) |
| 8819 | Chk_st_on_ASI_ring(`FAST); |
| 8820 | |
| 8821 | //if (`SPC4.l15_lsu_valid) |
| 8822 | //Chk_cpx_response_pkt({`SPC4.l15_lsu_valid, `SPC4.l15_lsu_cpkt[17:13],`SPC4.l15_lsu_cpkt[11:0],`SPC4.l15_spc_data1[127:0]}); |
| 8823 | |
| 8824 | if (`SPC4.cpx_spc_data_cx[145]) |
| 8825 | Chk_cpx_response_pkt(`SPC4.cpx_spc_data_cx); |
| 8826 | |
| 8827 | if (`SPC4.lsu_complete[7:0] != 8'b0) |
| 8828 | begin |
| 8829 | if (`SPC4.lsu_complete[0]) Chk_ld_complete(0); |
| 8830 | if (`SPC4.lsu_complete[1]) Chk_ld_complete(1); |
| 8831 | if (`SPC4.lsu_complete[2]) Chk_ld_complete(2); |
| 8832 | if (`SPC4.lsu_complete[3]) Chk_ld_complete(3); |
| 8833 | if (`SPC4.lsu_complete[4]) Chk_ld_complete(4); |
| 8834 | if (`SPC4.lsu_complete[5]) Chk_ld_complete(5); |
| 8835 | if (`SPC4.lsu_complete[6]) Chk_ld_complete(6); |
| 8836 | if (`SPC4.lsu_complete[7]) Chk_ld_complete(7); |
| 8837 | end |
| 8838 | |
| 8839 | if (`SPC4.lsu_block_store_kill[7:0] != 8'b0) |
| 8840 | begin |
| 8841 | if (`SPC4.lsu_block_store_kill[0]) Squash_STB(0); |
| 8842 | if (`SPC4.lsu_block_store_kill[1]) Squash_STB(1); |
| 8843 | if (`SPC4.lsu_block_store_kill[2]) Squash_STB(2); |
| 8844 | if (`SPC4.lsu_block_store_kill[3]) Squash_STB(3); |
| 8845 | if (`SPC4.lsu_block_store_kill[4]) Squash_STB(4); |
| 8846 | if (`SPC4.lsu_block_store_kill[5]) Squash_STB(5); |
| 8847 | if (`SPC4.lsu_block_store_kill[6]) Squash_STB(6); |
| 8848 | if (`SPC4.lsu_block_store_kill[7]) Squash_STB(7); |
| 8849 | end |
| 8850 | |
| 8851 | if (`SPC4.lsu_stb_dealloc[7:0] != 8'b0) |
| 8852 | begin |
| 8853 | if (`SPC4.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 8854 | if (`SPC4.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 8855 | if (`SPC4.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 8856 | if (`SPC4.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 8857 | if (`SPC4.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 8858 | if (`SPC4.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 8859 | if (`SPC4.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 8860 | if (`SPC4.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 8861 | end |
| 8862 | |
| 8863 | if (`SPC4.lsu_block_store_stall) |
| 8864 | Chk_block_store; |
| 8865 | |
| 8866 | if (`SPC4.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 8867 | Set_block_store_parameters; |
| 8868 | |
| 8869 | if (`SPC4.lsu_sbdiou_err_g || `SPC4.lsu_sbapp_err_g) |
| 8870 | Squash_store; |
| 8871 | |
| 8872 | if (`SPC4.lsu_stb_flush_g) |
| 8873 | st_priv[`SPC4.lsu_stberr_tid_g] = get_priv_on_flush(`SPC4.lsu_stberr_tid_g); |
| 8874 | end |
| 8875 | |
| 8876 | function [1:0] get_priv_on_flush; |
| 8877 | input [2:0] tid; |
| 8878 | reg [2:0] sq_index; |
| 8879 | reg [204:0] tmp; |
| 8880 | |
| 8881 | begin |
| 8882 | sq_index = `SPC4.lsu_stberr_index_g; |
| 8883 | tmp = stb[{tid, sq_index}]; |
| 8884 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 8885 | end |
| 8886 | endfunction |
| 8887 | |
| 8888 | task Chk_block_store; |
| 8889 | reg [20:0] inst; |
| 8890 | reg [2:0] thid; |
| 8891 | begin |
| 8892 | thid = `SPC4.lsu_block_store_tid; |
| 8893 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 8894 | inst = bst_inst_data[`LSU_MON_INST]; |
| 8895 | |
| 8896 | if (~inst[`BLKST]) |
| 8897 | begin |
| 8898 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 8899 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 8900 | end |
| 8901 | end |
| 8902 | endtask |
| 8903 | |
| 8904 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 8905 | //the 8 stb entries from the previous blk store. |
| 8906 | |
| 8907 | task Set_block_store_parameters; |
| 8908 | reg [2:0] thid; |
| 8909 | begin |
| 8910 | |
| 8911 | thid = decode_tid(`SPC4.lsu.lsu_block_store_alloc[7:0]); |
| 8912 | if (lsu_bst_active[thid]) |
| 8913 | begin |
| 8914 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 8915 | end |
| 8916 | else |
| 8917 | begin |
| 8918 | lsu_bst_active[thid] = 1'b1; |
| 8919 | bst_active_thid = thid; |
| 8920 | if (`SPC4.lsu.fgu_fst_ecc_error_fx2) |
| 8921 | bst_fgu_err = 1'b1; |
| 8922 | else |
| 8923 | bst_fgu_err = 1'b0; |
| 8924 | end |
| 8925 | end |
| 8926 | endtask |
| 8927 | |
| 8928 | task Squash_store; |
| 8929 | reg [2:0] thid; |
| 8930 | reg [2:0] sq_index; |
| 8931 | reg [2:0] i; |
| 8932 | reg [204:0] tmp; |
| 8933 | reg [3:0] squash_cnt; |
| 8934 | reg [1:0] priv; |
| 8935 | |
| 8936 | begin |
| 8937 | thid = `SPC4.lsu_stberr_tid_g; |
| 8938 | sq_index = `SPC4.lsu_stberr_index_g; |
| 8939 | priv = `SPC4.lsu_stberr_priv_g; |
| 8940 | tmp = stb[{thid, sq_index}]; |
| 8941 | squash_cnt = 0; |
| 8942 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 8943 | |
| 8944 | st_priv[thid] = tmp[`ST_PRIV]; |
| 8945 | |
| 8946 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 8947 | //In that case iss_ptr won't be equal to sbdiou index. |
| 8948 | //if (sq_index != iss_ptr[thid]) |
| 8949 | //begin |
| 8950 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 8951 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 8952 | //end |
| 8953 | |
| 8954 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 8955 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 8956 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 8957 | //removing this chk. |
| 8958 | |
| 8959 | //if (tmp[`L2_ST_ISS]) |
| 8960 | //begin |
| 8961 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 8962 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 8963 | //end |
| 8964 | |
| 8965 | if (iss_ptr[thid] == wrptr[thid]) |
| 8966 | begin |
| 8967 | if (stb_valid[{thid, wrptr[thid]}]) |
| 8968 | squash_cnt = 8; |
| 8969 | else |
| 8970 | begin |
| 8971 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 8972 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 8973 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 8974 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 8975 | end |
| 8976 | end |
| 8977 | else |
| 8978 | begin |
| 8979 | if (iss_ptr[thid] < wrptr[thid]) |
| 8980 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 8981 | else if (iss_ptr[thid] > wrptr[thid]) |
| 8982 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 8983 | end |
| 8984 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 8985 | |
| 8986 | i = iss_ptr[thid]; |
| 8987 | |
| 8988 | while (squash_cnt) |
| 8989 | begin |
| 8990 | tmp = stb[{thid, i}]; |
| 8991 | tmp[`ST_SQUASH] = 1'b1; |
| 8992 | if (priv < tmp[`ST_PRIV]) |
| 8993 | begin |
| 8994 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 8995 | priv = tmp[`ST_PRIV]; |
| 8996 | end |
| 8997 | |
| 8998 | stb[{thid, i}] = tmp; |
| 8999 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 9000 | |
| 9001 | i = i + 1; |
| 9002 | squash_cnt = squash_cnt - 1'b1; |
| 9003 | end |
| 9004 | end |
| 9005 | endtask |
| 9006 | |
| 9007 | function [2:0] decode_tid; |
| 9008 | input [7:0] thid_encode; |
| 9009 | begin |
| 9010 | case (thid_encode) |
| 9011 | 8'h1: decode_tid = 3'b0; |
| 9012 | 8'h2: decode_tid = 3'h1; |
| 9013 | 8'h4: decode_tid = 3'h2; |
| 9014 | 8'h8: decode_tid = 3'h3; |
| 9015 | 8'h10: decode_tid = 3'h4; |
| 9016 | 8'h20: decode_tid = 3'h5; |
| 9017 | 8'h40: decode_tid = 3'h6; |
| 9018 | 8'h80: decode_tid = 3'h7; |
| 9019 | default: |
| 9020 | begin |
| 9021 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 9022 | end |
| 9023 | endcase |
| 9024 | end |
| 9025 | endfunction |
| 9026 | |
| 9027 | task Chk_ld_complete; |
| 9028 | input [2:0] thid; |
| 9029 | reg [`LD_Pend_Width] tmp; |
| 9030 | begin |
| 9031 | tmp = ld_pend_array[thid]; |
| 9032 | |
| 9033 | if (ld_valid[thid]) |
| 9034 | begin |
| 9035 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 9036 | begin |
| 9037 | DispPendReq(thid); |
| 9038 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 9039 | end |
| 9040 | ld_valid[thid] = 1'b0; |
| 9041 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 9042 | end |
| 9043 | |
| 9044 | tmp = last_inst_array[thid]; |
| 9045 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 9046 | end |
| 9047 | endtask |
| 9048 | |
| 9049 | task Chk_pcx_req_pkt; |
| 9050 | input [129:0] pcx_pkt; |
| 9051 | reg [2:0] thid; |
| 9052 | reg [`LD_Pend_Width] tmp, tmp1; |
| 9053 | reg [15:0] inst; |
| 9054 | reg [11*8:0] req; |
| 9055 | reg [39:0] addr; |
| 9056 | begin |
| 9057 | thid = pcx_pkt[`PCX_THR_ID]; |
| 9058 | tmp = ld_pend_array[thid]; |
| 9059 | inst = tmp[`LSU_MON_INST]; |
| 9060 | req = DispPCXReq(pcx_pkt); |
| 9061 | addr = pcx_pkt[`PCX_ADDR]; |
| 9062 | |
| 9063 | |
| 9064 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 9065 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 9066 | |
| 9067 | |
| 9068 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 9069 | begin |
| 9070 | if (~ld_valid[thid]) |
| 9071 | begin |
| 9072 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 9073 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 9074 | end |
| 9075 | if (~inst[`BLKLD]) |
| 9076 | begin |
| 9077 | if (tmp[`MEMOP_PA] != addr) |
| 9078 | begin |
| 9079 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 9080 | begin |
| 9081 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 9082 | end |
| 9083 | else |
| 9084 | begin |
| 9085 | DispPendReq(thid); |
| 9086 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 9087 | end |
| 9088 | end |
| 9089 | end |
| 9090 | end |
| 9091 | |
| 9092 | case (pcx_pkt[`PCX_RQTYP]) |
| 9093 | `PCX_LOAD: |
| 9094 | begin |
| 9095 | if (pcx_pkt[`PCX_PF]) |
| 9096 | begin |
| 9097 | if (~inst[`PREF]) |
| 9098 | begin |
| 9099 | DispPendReq(thid); |
| 9100 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 9101 | end |
| 9102 | if (pcx_pkt[`PCX_INV]) |
| 9103 | begin |
| 9104 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 9105 | end |
| 9106 | else |
| 9107 | begin |
| 9108 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 9109 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 9110 | end |
| 9111 | tmp[`L2_ISS] = 4'hF; |
| 9112 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 9113 | ld_pend_array[thid] = tmp; |
| 9114 | end |
| 9115 | else |
| 9116 | begin |
| 9117 | if (pcx_pkt[`PCX_INV]) |
| 9118 | begin |
| 9119 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9120 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 9121 | end |
| 9122 | else |
| 9123 | begin |
| 9124 | Chk_req_load(pcx_pkt); |
| 9125 | end |
| 9126 | end |
| 9127 | end |
| 9128 | `PCX_CAS1, `PCX_CAS2: |
| 9129 | begin |
| 9130 | if (~inst[`CASA]) |
| 9131 | begin |
| 9132 | DispPendReq(thid); |
| 9133 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 9134 | end |
| 9135 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 9136 | begin |
| 9137 | tmp[`L2_ISS] = 4'hE; |
| 9138 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9139 | ld_pend_array[thid] = tmp; |
| 9140 | end |
| 9141 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 9142 | begin |
| 9143 | tmp[`L2_ISS] = 4'hF; |
| 9144 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9145 | ld_pend_array[thid] = tmp; |
| 9146 | chk_store_issue_to_pcx(pcx_pkt); |
| 9147 | end |
| 9148 | |
| 9149 | end |
| 9150 | `PCX_SWAP_LDSTUB: |
| 9151 | begin |
| 9152 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 9153 | begin |
| 9154 | DispPendReq(thid); |
| 9155 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 9156 | end |
| 9157 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 9158 | tmp[`L2_ISS] = 4'hF; |
| 9159 | ld_pend_array[thid] = tmp; |
| 9160 | |
| 9161 | chk_store_issue_to_pcx(pcx_pkt); |
| 9162 | end |
| 9163 | |
| 9164 | `PCX_STORE: |
| 9165 | begin |
| 9166 | chk_store_issue_to_pcx(pcx_pkt); |
| 9167 | end |
| 9168 | |
| 9169 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 9170 | endcase |
| 9171 | end |
| 9172 | endtask |
| 9173 | |
| 9174 | task Chk_cpx_response_pkt; |
| 9175 | input [145:0] cpx_pkt; |
| 9176 | reg [2:0] thid; |
| 9177 | begin |
| 9178 | thid = cpx_pkt[`CPX_THR_ID]; |
| 9179 | |
| 9180 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 9181 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 9182 | begin |
| 9183 | chk_ccx_ld_response(cpx_pkt); |
| 9184 | end |
| 9185 | |
| 9186 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 9187 | begin |
| 9188 | if (pf_cnt[thid] == 8'b0) |
| 9189 | begin |
| 9190 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 9191 | end |
| 9192 | else |
| 9193 | begin |
| 9194 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 9195 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 9196 | end |
| 9197 | end |
| 9198 | |
| 9199 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 9200 | chk_ccx_ld_response(cpx_pkt); |
| 9201 | |
| 9202 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 9203 | begin |
| 9204 | if (cpx_pkt[123]) //D pkt |
| 9205 | begin //{ |
| 9206 | if (cpx_pkt[120:118] != core_id) |
| 9207 | begin |
| 9208 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 9209 | end |
| 9210 | if (dcache_inv_cnt[thid] == 8'b0) |
| 9211 | begin |
| 9212 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 9213 | end |
| 9214 | else |
| 9215 | begin |
| 9216 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 9217 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 9218 | end |
| 9219 | end //} |
| 9220 | else if (cpx_pkt[124]) //I pkt |
| 9221 | begin |
| 9222 | if (cpx_pkt[120:118] != core_id) |
| 9223 | begin |
| 9224 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 9225 | end |
| 9226 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 9227 | end |
| 9228 | else if (cpx_pkt[124:123] == 2'b0) |
| 9229 | begin |
| 9230 | if (cpx_pkt[120:118] == core_id) |
| 9231 | begin |
| 9232 | chk_ccx_st_response(cpx_pkt); |
| 9233 | end |
| 9234 | else |
| 9235 | begin |
| 9236 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 9237 | end |
| 9238 | end |
| 9239 | end |
| 9240 | |
| 9241 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 9242 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 9243 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 9244 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 9245 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 9246 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 9247 | |
| 9248 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 9249 | begin |
| 9250 | chk_ccx_atm_response(cpx_pkt); |
| 9251 | end |
| 9252 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 9253 | begin |
| 9254 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 9255 | begin |
| 9256 | chk_ccx_atm_response(cpx_pkt); |
| 9257 | chk_ccx_st_response(cpx_pkt); |
| 9258 | end |
| 9259 | end |
| 9260 | |
| 9261 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 9262 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 9263 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 9264 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 9265 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 9266 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 9267 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 9268 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 9269 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 9270 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 9271 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 9272 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 9273 | |
| 9274 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 9275 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 9276 | |
| 9277 | default: |
| 9278 | begin |
| 9279 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 9280 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 9281 | |
| 9282 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 9283 | end |
| 9284 | |
| 9285 | endcase |
| 9286 | end |
| 9287 | endtask |
| 9288 | |
| 9289 | task chk_ccx_ld_response; |
| 9290 | input [145:0] cpx_pkt; |
| 9291 | reg [2:0] thid; |
| 9292 | reg [20:0] inst; |
| 9293 | reg [39:0] cpx_pa, inst_pa; |
| 9294 | reg [`LD_Pend_Width] tmp; |
| 9295 | reg [3:0] pkt_type; |
| 9296 | begin |
| 9297 | thid = cpx_pkt[`CPX_THR_ID]; |
| 9298 | tmp = ld_pend_array[thid]; |
| 9299 | inst = tmp[`LSU_MON_INST]; |
| 9300 | inst_pa = tmp[`MEMOP_PA]; |
| 9301 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 9302 | |
| 9303 | if (ld_valid[thid]) |
| 9304 | begin |
| 9305 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 9306 | /* |
| 9307 | if (inst_pa[39] != pkt_type[3]) |
| 9308 | begin |
| 9309 | DispPendReq(thid); |
| 9310 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 9311 | end |
| 9312 | */ |
| 9313 | |
| 9314 | if (inst[`BLKLD]) |
| 9315 | begin |
| 9316 | if (tmp[`L2_RESP] == 4'h0) |
| 9317 | begin |
| 9318 | tmp[`L2_RESP] = 4'h1; |
| 9319 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 9320 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 9321 | begin |
| 9322 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 9323 | end |
| 9324 | |
| 9325 | end |
| 9326 | else if (tmp[`L2_RESP] == 4'h1) |
| 9327 | begin |
| 9328 | tmp[`L2_RESP] = 4'h3; |
| 9329 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 9330 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 9331 | begin |
| 9332 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 9333 | end |
| 9334 | end |
| 9335 | else if (tmp[`L2_RESP] == 4'h3) |
| 9336 | begin |
| 9337 | tmp[`L2_RESP] = 4'h7; |
| 9338 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 9339 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 9340 | begin |
| 9341 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 9342 | end |
| 9343 | end |
| 9344 | else if (tmp[`L2_RESP] == 4'h7) |
| 9345 | begin |
| 9346 | tmp[`L2_RESP] = 4'hF; |
| 9347 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 9348 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 9349 | begin |
| 9350 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 9351 | end |
| 9352 | |
| 9353 | //is_blkld[thid] = 1'b1; |
| 9354 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 9355 | l2_blk_ld_errtype[thid] = `ND; |
| 9356 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 9357 | l2_blk_ld_errtype[thid] = `UE; |
| 9358 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 9359 | l2_blk_ld_errtype[thid] = `CE; |
| 9360 | else |
| 9361 | l2_blk_ld_errtype[thid] = `NE; |
| 9362 | end |
| 9363 | else |
| 9364 | begin |
| 9365 | DispPendReq(thid); |
| 9366 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 9367 | end |
| 9368 | end |
| 9369 | else if (Is_single_pcx_req_ld(inst)) |
| 9370 | begin |
| 9371 | //is_blkld[thid] = 1'b0; |
| 9372 | if (tmp[`L2_RESP] != 4'hE) |
| 9373 | begin |
| 9374 | DispPendReq(thid); |
| 9375 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 9376 | end |
| 9377 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 9378 | tmp[`L2_RESP] = 4'hF; |
| 9379 | end |
| 9380 | else |
| 9381 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 9382 | end |
| 9383 | else |
| 9384 | begin |
| 9385 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 9386 | end |
| 9387 | |
| 9388 | ld_pend_array[thid] = tmp; |
| 9389 | end |
| 9390 | endtask |
| 9391 | |
| 9392 | task chk_ccx_atm_response; |
| 9393 | input [145:0] cpx_pkt; |
| 9394 | reg [2:0] thid; |
| 9395 | reg [20:0] inst; |
| 9396 | reg [39:0] inst_pa; |
| 9397 | reg [`LD_Pend_Width] tmp; |
| 9398 | begin |
| 9399 | thid = cpx_pkt[`CPX_THR_ID]; |
| 9400 | tmp = ld_pend_array[thid]; |
| 9401 | inst = tmp[`LSU_MON_INST]; |
| 9402 | inst_pa = tmp[`MEMOP_PA]; |
| 9403 | |
| 9404 | if (~ld_valid[thid]) |
| 9405 | begin |
| 9406 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 9407 | begin |
| 9408 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 9409 | end |
| 9410 | else |
| 9411 | begin |
| 9412 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 9413 | end |
| 9414 | end |
| 9415 | else |
| 9416 | begin |
| 9417 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 9418 | begin |
| 9419 | DispPendReq(thid); |
| 9420 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 9421 | begin |
| 9422 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 9423 | end |
| 9424 | else |
| 9425 | begin |
| 9426 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 9427 | end |
| 9428 | end |
| 9429 | else |
| 9430 | begin |
| 9431 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 9432 | begin |
| 9433 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 9434 | end |
| 9435 | else |
| 9436 | begin |
| 9437 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 9438 | end |
| 9439 | |
| 9440 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 9441 | begin |
| 9442 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 9443 | else |
| 9444 | begin |
| 9445 | DispPendReq(thid); |
| 9446 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 9447 | end |
| 9448 | end |
| 9449 | else |
| 9450 | begin |
| 9451 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 9452 | else |
| 9453 | begin |
| 9454 | DispPendReq(thid); |
| 9455 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 9456 | end |
| 9457 | end |
| 9458 | end |
| 9459 | end |
| 9460 | ld_pend_array[thid] = tmp; |
| 9461 | end |
| 9462 | endtask |
| 9463 | |
| 9464 | task chk_ccx_st_response; |
| 9465 | input [145:0] cpx_pkt; |
| 9466 | reg [2:0] thid; |
| 9467 | reg [20:0] inst; |
| 9468 | reg [39:0] cpx_pa, inst_pa; |
| 9469 | reg [204:0] tmp; |
| 9470 | reg [3:0] pkt_type; |
| 9471 | begin |
| 9472 | thid = cpx_pkt[`CPX_THR_ID]; |
| 9473 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 9474 | inst = tmp[`LSU_MON_INST]; |
| 9475 | inst_pa = tmp[`MEMOP_PA]; |
| 9476 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 9477 | |
| 9478 | |
| 9479 | //is received. There could be some other store sitting in the STB at that time. |
| 9480 | |
| 9481 | //Chk for squash bit only for non-bis responses. |
| 9482 | |
| 9483 | |
| 9484 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 9485 | begin |
| 9486 | if (st_rmo_cnt[thid] == 0) |
| 9487 | begin |
| 9488 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 9489 | end |
| 9490 | else |
| 9491 | begin |
| 9492 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 9493 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 9494 | end |
| 9495 | end |
| 9496 | else |
| 9497 | begin |
| 9498 | if (tmp[`ST_SQUASH]) |
| 9499 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 9500 | |
| 9501 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 9502 | begin |
| 9503 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 9504 | end |
| 9505 | else |
| 9506 | begin |
| 9507 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 9508 | begin |
| 9509 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 9510 | end |
| 9511 | tmp[`L2_ACK] = 1'b1; |
| 9512 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 9513 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 9514 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 9515 | end |
| 9516 | end |
| 9517 | end |
| 9518 | endtask |
| 9519 | |
| 9520 | task Chk_req_load; |
| 9521 | input [129:0] pcx_pkt; |
| 9522 | reg [2:0] thid; |
| 9523 | reg [`LD_Pend_Width] tmp; |
| 9524 | reg [39:0] pcx_pa, inst_pa; |
| 9525 | reg [20:0] inst; |
| 9526 | reg [11*8:0] req; |
| 9527 | begin |
| 9528 | |
| 9529 | thid = pcx_pkt[`PCX_THR_ID]; |
| 9530 | tmp = ld_pend_array[thid]; |
| 9531 | inst = tmp[`LSU_MON_INST]; |
| 9532 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 9533 | inst_pa = tmp[`MEMOP_PA]; |
| 9534 | req = DispPCXReq(pcx_pkt); |
| 9535 | |
| 9536 | if (inst[`BLKLD]) |
| 9537 | begin |
| 9538 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 9539 | begin |
| 9540 | DispPendReq(thid); |
| 9541 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 9542 | end |
| 9543 | if (pcx_pa[5:0] == 6'b0) |
| 9544 | begin |
| 9545 | if (tmp[`L2_ISS] != 4'h0 ) |
| 9546 | begin |
| 9547 | DispPendReq(thid); |
| 9548 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 9549 | end |
| 9550 | else |
| 9551 | begin |
| 9552 | tmp[`L2_ISS] = 4'h1; |
| 9553 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9554 | end |
| 9555 | |
| 9556 | end |
| 9557 | if (pcx_pa[5:0] == 6'h10) |
| 9558 | begin |
| 9559 | if (tmp[`L2_ISS] != 4'h1) |
| 9560 | begin |
| 9561 | DispPendReq(thid); |
| 9562 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 9563 | end |
| 9564 | else |
| 9565 | begin |
| 9566 | tmp[`L2_ISS] = 4'h3; |
| 9567 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9568 | end |
| 9569 | end |
| 9570 | if (pcx_pa[5:0] == 6'h20) |
| 9571 | begin |
| 9572 | if (tmp[`L2_ISS] != 4'h3) |
| 9573 | begin |
| 9574 | DispPendReq(thid); |
| 9575 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 9576 | end |
| 9577 | else |
| 9578 | begin |
| 9579 | tmp[`L2_ISS] = 4'h7; |
| 9580 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9581 | end |
| 9582 | end |
| 9583 | if (pcx_pa[5:0] == 6'h30) |
| 9584 | begin |
| 9585 | if (tmp[`L2_ISS] != 4'h7) |
| 9586 | begin |
| 9587 | DispPendReq(thid); |
| 9588 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 9589 | end |
| 9590 | else |
| 9591 | begin |
| 9592 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9593 | tmp[`L2_ISS] = 4'hF; |
| 9594 | end |
| 9595 | end |
| 9596 | ld_pend_array[thid] = tmp; |
| 9597 | end |
| 9598 | else if (Is_single_pcx_req_ld(inst)) |
| 9599 | begin |
| 9600 | if (tmp[`L2_ISS] == 4'hF) |
| 9601 | begin |
| 9602 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 9603 | end |
| 9604 | else |
| 9605 | begin |
| 9606 | tmp[`L2_ISS] = 4'hF; |
| 9607 | ld_pend_array[thid] = tmp; |
| 9608 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 9609 | end |
| 9610 | end |
| 9611 | else |
| 9612 | begin |
| 9613 | DispPendReq(thid); |
| 9614 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 9615 | end |
| 9616 | end |
| 9617 | endtask |
| 9618 | |
| 9619 | |
| 9620 | function Is_single_pcx_req_ld; |
| 9621 | input [20:0] inst; |
| 9622 | begin |
| 9623 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 9624 | Is_single_pcx_req_ld = 1'b1; |
| 9625 | else |
| 9626 | Is_single_pcx_req_ld = 1'b0; |
| 9627 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 9628 | end |
| 9629 | endfunction |
| 9630 | |
| 9631 | |
| 9632 | function Is_trap; |
| 9633 | input [2:0]tid; |
| 9634 | |
| 9635 | begin |
| 9636 | Is_trap = 1'b0; |
| 9637 | case (`SPC4.lsu_trap_flush[7:0]) |
| 9638 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 9639 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 9640 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 9641 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 9642 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 9643 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 9644 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 9645 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 9646 | endcase |
| 9647 | end |
| 9648 | endfunction |
| 9649 | |
| 9650 | function [8*11:0] DispPCXReq; |
| 9651 | input [129:0] pcx_pkt; |
| 9652 | begin |
| 9653 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 9654 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 9655 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 9656 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 9657 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 9658 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 9659 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 9660 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 9661 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 9662 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 9663 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 9664 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 9665 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 9666 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 9667 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 9668 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 9669 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 9670 | default: |
| 9671 | begin |
| 9672 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 9673 | DispPCXReq = " "; |
| 9674 | end |
| 9675 | endcase |
| 9676 | end |
| 9677 | endfunction |
| 9678 | |
| 9679 | function IsExc; |
| 9680 | input [2:0] core_id; |
| 9681 | reg [21*8:0] DispExc; |
| 9682 | |
| 9683 | begin |
| 9684 | DispExc = 170'b0; |
| 9685 | IsExc = 1'b0; |
| 9686 | |
| 9687 | if (`SPC4.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 9688 | if (`SPC4.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 9689 | if (`SPC4.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 9690 | if (`SPC4.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 9691 | if (`SPC4.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 9692 | if (`SPC4.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 9693 | //if (`SPC4.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 9694 | if (`SPC4.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 9695 | if (`SPC4.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 9696 | if (`SPC4.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 9697 | if (`SPC4.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 9698 | if (`SPC4.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 9699 | if (`SPC4.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 9700 | if (`SPC4.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 9701 | //if (`SPC4.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 9702 | if (`SPC4.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 9703 | if (`SPC4.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 9704 | if (`SPC4.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 9705 | |
| 9706 | |
| 9707 | if (DispExc != 0) |
| 9708 | begin |
| 9709 | IsExc = 1'b1; |
| 9710 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 9711 | end |
| 9712 | |
| 9713 | end |
| 9714 | endfunction |
| 9715 | |
| 9716 | function Is_exu_error; |
| 9717 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 9718 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 9719 | reg err_b; |
| 9720 | reg err_m; |
| 9721 | |
| 9722 | begin |
| 9723 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC4.lsu_tlb_bypass_b)): |
| 9724 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC4.lsu_tlb_bypass_b)); |
| 9725 | |
| 9726 | err_m = (dec_lsu_tid_b[2] ? `SPC4.exu_ecc_m[1] : `SPC4.exu_ecc_m[0]) & `SPC4.lsu.dcc.twocycle_b; |
| 9727 | |
| 9728 | Is_exu_error = err_b | err_m; |
| 9729 | end |
| 9730 | endfunction |
| 9731 | |
| 9732 | /* |
| 9733 | task Insert_tlb_miss_info; |
| 9734 | reg [127:0] tmp; |
| 9735 | begin |
| 9736 | tmp = 128'b0; |
| 9737 | if (tlb_valid[dec_lsu_tid_b]) |
| 9738 | begin |
| 9739 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 9740 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 9741 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 9742 | end |
| 9743 | else |
| 9744 | begin |
| 9745 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 9746 | tmp[`INST_VA] = inst_pc_b; |
| 9747 | tmp[`MEMOP_VA] = vaddr_b; |
| 9748 | tmp[`INST] = inst_b; |
| 9749 | end |
| 9750 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 9751 | end |
| 9752 | endtask |
| 9753 | |
| 9754 | */ |
| 9755 | |
| 9756 | //problem with the signal. |
| 9757 | /* |
| 9758 | always @ (negedge `SPC4.l2clk) |
| 9759 | begin |
| 9760 | if (mmu_dtlb_reload_d2) |
| 9761 | Chk_dtlb_reload; |
| 9762 | end |
| 9763 | |
| 9764 | task Chk_dtlb_reload; |
| 9765 | reg [2:0] thid; |
| 9766 | reg [127:0] tmp; |
| 9767 | begin |
| 9768 | if (`SPC4.tlu_trap_pc_0_valid) |
| 9769 | thid = {1'b0, `SPC4.tlu_trap_0_tid}; |
| 9770 | else if (`SPC4.tlu_trap_pc_1_valid) |
| 9771 | thid = {1'b0, `SPC4.tlu_trap_1_tid}; |
| 9772 | else |
| 9773 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 9774 | |
| 9775 | if (~tlb_valid[thid]) |
| 9776 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 9777 | else |
| 9778 | begin |
| 9779 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 9780 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 9781 | tlb_valid[thid] = 1'b0; |
| 9782 | end |
| 9783 | end |
| 9784 | endtask |
| 9785 | */ |
| 9786 | |
| 9787 | task Insert_ld_miss_info; |
| 9788 | reg [`LD_Pend_Width] tmp; |
| 9789 | begin |
| 9790 | tmp = 213'b0; |
| 9791 | if (ld_valid[dec_lsu_tid_b]) |
| 9792 | begin |
| 9793 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 9794 | DispPendReq(dec_lsu_tid_b); |
| 9795 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 9796 | end |
| 9797 | else |
| 9798 | begin |
| 9799 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 9800 | tmp[`INST_VA] = inst_pc_b; |
| 9801 | tmp[`MEMOP_VA] = vaddr_b; |
| 9802 | tmp[`MEMOP_PA] = {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 9803 | tmp[`INST_ASI] = asi_b; |
| 9804 | |
| 9805 | if (lsu_inst_b[`BLKLD]) |
| 9806 | begin |
| 9807 | tmp[`L2_ISS] = 4'h0; |
| 9808 | tmp[`L2_RESP] = 4'h0; |
| 9809 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 9810 | end |
| 9811 | else |
| 9812 | begin |
| 9813 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 9814 | if (lsu_inst_b[`CASA]) |
| 9815 | tmp[`L2_ISS] = 4'hC; |
| 9816 | else |
| 9817 | tmp[`L2_ISS] = 4'hE; |
| 9818 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 9819 | tmp[`L2_RESP] = 4'hC; |
| 9820 | else |
| 9821 | tmp[`L2_RESP] = 4'hE; |
| 9822 | |
| 9823 | end |
| 9824 | |
| 9825 | tmp[`INST] = inst_b; |
| 9826 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 9827 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 9828 | end |
| 9829 | end |
| 9830 | endtask |
| 9831 | |
| 9832 | |
| 9833 | task Insert_in_last_inst_array; |
| 9834 | reg [135:0] tmp; |
| 9835 | begin |
| 9836 | tmp = 128'b0; |
| 9837 | tmp[`INST_VA] = inst_pc_b; |
| 9838 | tmp[`MEMOP_VA] = vaddr_b; |
| 9839 | tmp[`INST] = inst_b; |
| 9840 | tmp[135:128] = asi_b; |
| 9841 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 9842 | end |
| 9843 | endtask |
| 9844 | |
| 9845 | |
| 9846 | task DispPendReq; |
| 9847 | input [2:0] thid; |
| 9848 | reg [`LD_Pend_Width] tmp; |
| 9849 | begin |
| 9850 | |
| 9851 | tmp = ld_pend_array[thid]; |
| 9852 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 9853 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 9854 | end |
| 9855 | endtask |
| 9856 | |
| 9857 | task Disp_STB_entry; |
| 9858 | input [2:0] thid; |
| 9859 | input [2:0] ptr; |
| 9860 | reg [204:0] tmp; |
| 9861 | begin |
| 9862 | |
| 9863 | tmp = stb[{thid, ptr}]; |
| 9864 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 9865 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 9866 | end |
| 9867 | endtask |
| 9868 | |
| 9869 | /* |
| 9870 | |
| 9871 | task Disp_tlbmiss_pend_array_entry; |
| 9872 | input [2:0] thid; |
| 9873 | reg [127:0] tmp; |
| 9874 | begin |
| 9875 | tmp = tlbmiss_pend_array[thid]; |
| 9876 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 9877 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 9878 | |
| 9879 | end |
| 9880 | endtask |
| 9881 | |
| 9882 | */ |
| 9883 | task Disp_CPX_pkt; |
| 9884 | input [145:0] cpx_pkt; |
| 9885 | begin |
| 9886 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 9887 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 9888 | end |
| 9889 | endtask |
| 9890 | |
| 9891 | |
| 9892 | task Make_STB_data; |
| 9893 | reg [204:0] tmp; |
| 9894 | begin |
| 9895 | tmp = 0; |
| 9896 | tmp[`INST_VA] = inst_pc_b; |
| 9897 | tmp[`MEMOP_VA] = vaddr_b; |
| 9898 | tmp[`MEMOP_PA] = {`SPC4.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 9899 | tmp[`L2_ST_ISS] = 1'b0; |
| 9900 | tmp[`ASI_ST_ISS] = 1'b0; |
| 9901 | tmp[`L2_ACK] = 1'b0; |
| 9902 | tmp[`INST] = inst_b; |
| 9903 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 9904 | tmp[`ST_SQUASH] = 1'b0; |
| 9905 | tmp[`INST_ASI] = asi_b; |
| 9906 | if (`SPC4.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 9907 | tmp[`ST_PRIV] = `HPRIV; |
| 9908 | else if (`SPC4.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 9909 | tmp[`ST_PRIV] = `PRIV; |
| 9910 | else |
| 9911 | tmp[`ST_PRIV] = `USER; |
| 9912 | //bis_asi to io space is not rmo |
| 9913 | |
| 9914 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC4.lsu.tlb_pgnum[39]); |
| 9915 | stb_alloc_data <= tmp; |
| 9916 | end |
| 9917 | endtask |
| 9918 | |
| 9919 | task Insert_in_STB; |
| 9920 | input [195:0] store_data; |
| 9921 | input [2:0] thid; |
| 9922 | begin |
| 9923 | if (stb_full(thid)) |
| 9924 | begin |
| 9925 | //DispSTB(thid); |
| 9926 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 9927 | end |
| 9928 | else |
| 9929 | begin |
| 9930 | stb[{thid, wrptr[thid]}] = store_data; |
| 9931 | //Disp_STB_entry(thid, wrptr[thid]); |
| 9932 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 9933 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 9934 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 9935 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 9936 | end |
| 9937 | end |
| 9938 | endtask |
| 9939 | |
| 9940 | function stb_full; |
| 9941 | input [2:0] thid; |
| 9942 | begin |
| 9943 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 9944 | stb_full = 1'b1; |
| 9945 | else |
| 9946 | stb_full = 1'b0; |
| 9947 | end |
| 9948 | endfunction |
| 9949 | |
| 9950 | |
| 9951 | task Dealloc_STB; |
| 9952 | input [2:0] thid; |
| 9953 | reg [204:0] tmp; |
| 9954 | reg [20:0] lsu_inst; |
| 9955 | begin |
| 9956 | //thid = decode_tid(`SPC4.lsu_stb_dealloc); |
| 9957 | tmp = stb[{thid, rdptr[thid]}]; |
| 9958 | lsu_inst = tmp[`LSU_MON_INST]; |
| 9959 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 9960 | begin |
| 9961 | //DispSTB(thid); |
| 9962 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC4.lsu_stb_dealloc); |
| 9963 | end |
| 9964 | if (tmp[`L2_ST_ISS]) |
| 9965 | begin |
| 9966 | if (~tmp[`L2_ACK]) |
| 9967 | begin |
| 9968 | Disp_STB_entry(thid, rdptr[thid]); |
| 9969 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC4.lsu_stb_dealloc); |
| 9970 | end |
| 9971 | end |
| 9972 | else if (tmp[`ASI_ST_ISS]) |
| 9973 | begin |
| 9974 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 9975 | end |
| 9976 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 9977 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 9978 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 9979 | // and deallocated. |
| 9980 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 9981 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 9982 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 9983 | begin |
| 9984 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 9985 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 9986 | end |
| 9987 | else |
| 9988 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC4.lsu_stb_dealloc); |
| 9989 | |
| 9990 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 9991 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 9992 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 9993 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 9994 | /* |
| 9995 | if (tmp[`RMO]) |
| 9996 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 9997 | */ |
| 9998 | end |
| 9999 | endtask |
| 10000 | |
| 10001 | task Squash_STB; |
| 10002 | input [2:0] thid; |
| 10003 | reg [204:0] tmp; |
| 10004 | reg [3:0] squash_cnt; |
| 10005 | reg [2:0] i; |
| 10006 | begin |
| 10007 | squash_cnt = 4'b0; |
| 10008 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 10009 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 10010 | if (rdptr[thid] != iss_ptr[thid]) |
| 10011 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 10012 | |
| 10013 | if (iss_ptr[thid] == wrptr[thid]) |
| 10014 | begin |
| 10015 | if (stb_valid[{thid, wrptr[thid]}]) |
| 10016 | squash_cnt = 8; |
| 10017 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 10018 | * |
| 10019 | else |
| 10020 | begin |
| 10021 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 10022 | end |
| 10023 | */ |
| 10024 | end |
| 10025 | else |
| 10026 | begin |
| 10027 | if (iss_ptr[thid] < wrptr[thid]) |
| 10028 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 10029 | else if (iss_ptr[thid] > wrptr[thid]) |
| 10030 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 10031 | end |
| 10032 | |
| 10033 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 10034 | |
| 10035 | i = iss_ptr[thid]; |
| 10036 | |
| 10037 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 10038 | |
| 10039 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 10040 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 10041 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 10042 | |
| 10043 | while (squash_cnt) |
| 10044 | begin |
| 10045 | tmp = stb[{thid, i}]; |
| 10046 | if (~stb_valid[{thid, i}]) |
| 10047 | begin |
| 10048 | //DispSTB(thid); |
| 10049 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 10050 | end |
| 10051 | if (tmp[`L2_ST_ISS]) |
| 10052 | begin |
| 10053 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 10054 | end |
| 10055 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 10056 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 10057 | //set in the chkr which was causin it to fire. |
| 10058 | //if (~tmp[`ST_SQUASH]) |
| 10059 | //begin |
| 10060 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 10061 | //end |
| 10062 | stb_valid[{thid, i}] = 1'b0; |
| 10063 | |
| 10064 | i = i + 1; |
| 10065 | squash_cnt = squash_cnt - 1'b1; |
| 10066 | end |
| 10067 | |
| 10068 | end |
| 10069 | endtask |
| 10070 | |
| 10071 | task Chk_store; |
| 10072 | reg [2:0] thid; |
| 10073 | reg [47:0] addr; |
| 10074 | reg [3:0] i; |
| 10075 | reg [204:0] tmp; |
| 10076 | begin |
| 10077 | if ((bst_cnt > 0) && (`SPC4.lsu_stb_alloc == 8'b0)) |
| 10078 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 10079 | |
| 10080 | //For bst the stb is still written even though we have errors. |
| 10081 | //Stb is written in W stage. Howvere for first blk store helper |
| 10082 | //the err will be flagged by FGU in b stage. We can miss the |
| 10083 | // err signal if we don't sample in B. |
| 10084 | //for the last helper err will be signalled in B stage of last helper and at |
| 10085 | |
| 10086 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 10087 | bst_fgu_err = 1'b1; |
| 10088 | |
| 10089 | if (`SPC4.lsu_stb_alloc[7:0] != 8'b0) |
| 10090 | begin |
| 10091 | thid = decode_tid(`SPC4.lsu_stb_alloc[7:0]); |
| 10092 | if (store_alloc) |
| 10093 | begin |
| 10094 | if (thid != dec_lsu_tid_w) |
| 10095 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC4.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 10096 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 10097 | end |
| 10098 | else |
| 10099 | begin |
| 10100 | if (lsu_bst_active[thid]) |
| 10101 | begin |
| 10102 | if (bst_cnt == 0) |
| 10103 | begin |
| 10104 | bst_data = bst_inst_data; |
| 10105 | end |
| 10106 | else |
| 10107 | begin |
| 10108 | if (thid != bst_active_thid) |
| 10109 | begin |
| 10110 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC4.lsu_stb_alloc[7:0], bst_active_thid); |
| 10111 | end |
| 10112 | |
| 10113 | addr = bst_data[`MEMOP_VA]; |
| 10114 | |
| 10115 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 10116 | addr = bst_data[`MEMOP_PA]; |
| 10117 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 10118 | end |
| 10119 | bst_cnt = bst_cnt + 1; |
| 10120 | Insert_in_STB(bst_data, bst_active_thid); |
| 10121 | if (bst_cnt == 8) |
| 10122 | begin |
| 10123 | bst_cnt = 0; |
| 10124 | lsu_bst_active[thid] = 1'b0; |
| 10125 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 10126 | begin |
| 10127 | for (i = 0; i < 8; i=i+1) |
| 10128 | begin |
| 10129 | tmp = stb[{thid, i[2:0]}]; |
| 10130 | if (tmp[`ST_SQUASH]) |
| 10131 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 10132 | tmp[`ST_SQUASH] = 1'b1; |
| 10133 | stb[{thid, i[2:0]}] = tmp; |
| 10134 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 10135 | end |
| 10136 | end |
| 10137 | bst_fgu_err = 1'b0; |
| 10138 | end |
| 10139 | end |
| 10140 | else |
| 10141 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC4.lsu_stb_alloc[7:0]); |
| 10142 | |
| 10143 | end |
| 10144 | end |
| 10145 | else |
| 10146 | begin |
| 10147 | if (store_alloc) |
| 10148 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 10149 | end |
| 10150 | end |
| 10151 | endtask |
| 10152 | |
| 10153 | task Chk_st_on_ASI_ring; |
| 10154 | input ring; |
| 10155 | reg [2:0] thid; |
| 10156 | reg [7:0] asi; |
| 10157 | reg [47:0] addr, act_addr; |
| 10158 | reg [1:0] req_type; |
| 10159 | reg [204:0] tmp; |
| 10160 | |
| 10161 | begin |
| 10162 | if (ring == `LOCAL) |
| 10163 | thid =`SPC4.lsu_rngl_cdbus[58:56]; |
| 10164 | else |
| 10165 | thid =`SPC4.lsu_rngf_cdbus[58:56]; |
| 10166 | |
| 10167 | if (ring == `LOCAL) |
| 10168 | asi =`SPC4.lsu_rngl_cdbus[55:48]; |
| 10169 | else |
| 10170 | asi =`SPC4.lsu_rngf_cdbus[55:48]; |
| 10171 | |
| 10172 | if (ring == `LOCAL) |
| 10173 | addr =`SPC4.lsu_rngl_cdbus[47:0]; |
| 10174 | else |
| 10175 | addr =`SPC4.lsu_rngf_cdbus[47:0]; |
| 10176 | |
| 10177 | if (ring == `LOCAL) |
| 10178 | req_type =`SPC4.lsu_rngl_cdbus[61:60]; |
| 10179 | else |
| 10180 | req_type =`SPC4.lsu_rngf_cdbus[61:60]; |
| 10181 | |
| 10182 | |
| 10183 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 10184 | if (tmp[`ASI_ST_ISS]) |
| 10185 | begin |
| 10186 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10187 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 10188 | end |
| 10189 | |
| 10190 | if (tmp[`ST_SQUASH]) |
| 10191 | begin |
| 10192 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10193 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 10194 | end |
| 10195 | |
| 10196 | act_addr = tmp[`MEMOP_PA]; |
| 10197 | act_addr = {act_addr[39:3], 3'b0}; |
| 10198 | |
| 10199 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 10200 | //the address. |
| 10201 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 10202 | begin |
| 10203 | tmp[`ASI_ST_ISS] = 1'b1; |
| 10204 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 10205 | if (ring == `LOCAL) |
| 10206 | begin |
| 10207 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 10208 | end |
| 10209 | else |
| 10210 | begin |
| 10211 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 10212 | end |
| 10213 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 10214 | end |
| 10215 | else |
| 10216 | begin |
| 10217 | if (ring == `LOCAL) |
| 10218 | begin |
| 10219 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 10220 | end |
| 10221 | else |
| 10222 | begin |
| 10223 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 10224 | end |
| 10225 | end |
| 10226 | |
| 10227 | end |
| 10228 | endtask |
| 10229 | |
| 10230 | |
| 10231 | task chk_store_issue_to_pcx; |
| 10232 | input [129:0] pcx_pkt; |
| 10233 | reg [2:0] thid; |
| 10234 | reg [204:0] tmp; |
| 10235 | reg [20:0] inst; |
| 10236 | reg [39:0] pcx_pa, inst_pa; |
| 10237 | begin |
| 10238 | thid = pcx_pkt[`PCX_THR_ID]; |
| 10239 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 10240 | inst = tmp[`LSU_MON_INST]; |
| 10241 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 10242 | inst_pa = tmp[`MEMOP_PA]; |
| 10243 | |
| 10244 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 10245 | begin |
| 10246 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 10247 | end |
| 10248 | if (pcx_pkt[`PCX_INV]) |
| 10249 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 10250 | |
| 10251 | |
| 10252 | if (~inst[`ST]) |
| 10253 | begin |
| 10254 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10255 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10256 | end |
| 10257 | |
| 10258 | /* CONFIRM WITH MARK |
| 10259 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 10260 | begin |
| 10261 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10262 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 10263 | end |
| 10264 | */ |
| 10265 | //enhancement req 100146 |
| 10266 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 10267 | begin |
| 10268 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10269 | end |
| 10270 | |
| 10271 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 10272 | begin |
| 10273 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10274 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10275 | end |
| 10276 | |
| 10277 | if (tmp[`L2_ST_ISS]) |
| 10278 | begin |
| 10279 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10280 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10281 | end |
| 10282 | else |
| 10283 | tmp[`L2_ST_ISS] = 1'b1; |
| 10284 | |
| 10285 | if (tmp[`ST_SQUASH]) |
| 10286 | begin |
| 10287 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10288 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10289 | end |
| 10290 | |
| 10291 | if (tmp[`RMO]) |
| 10292 | begin |
| 10293 | if (~pcx_pkt[`PCX_BIS]) |
| 10294 | begin |
| 10295 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10296 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10297 | end |
| 10298 | if (tmp[`L2_ACK]) |
| 10299 | begin |
| 10300 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10301 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 10302 | end |
| 10303 | else |
| 10304 | begin |
| 10305 | tmp[`L2_ACK] = 1'b1; |
| 10306 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 10307 | //response seen from stub |
| 10308 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 10309 | end |
| 10310 | end |
| 10311 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 10312 | |
| 10313 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 10314 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 10315 | end |
| 10316 | endtask |
| 10317 | |
| 10318 | `ifdef INJ_STB_ERR_IN_CMP |
| 10319 | |
| 10320 | |
| 10321 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 10322 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 10323 | reg [204:0] err_tmp ; |
| 10324 | reg [20:0] err_inst; |
| 10325 | reg [44:0] cam_data; |
| 10326 | reg [5:0] err_bit; |
| 10327 | integer err_inj_cnt; |
| 10328 | reg cmp_stb_err_inj; |
| 10329 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 10330 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 10331 | |
| 10332 | initial |
| 10333 | begin |
| 10334 | cmp_stb_err_inj = 1'b0; |
| 10335 | |
| 10336 | cam_data = 45'b0; |
| 10337 | err_bit = 11; |
| 10338 | err_inj_cnt = 0; |
| 10339 | stb_err_inj = 0; |
| 10340 | if (("cmp_stb_err_inj_on")) |
| 10341 | cmp_stb_err_inj = 1'b1; |
| 10342 | else |
| 10343 | cmp_stb_err_inj = 1'b0; |
| 10344 | end |
| 10345 | |
| 10346 | always @ (negedge (`SPC4.l2clk & enabled & cmp_stb_err_inj)) |
| 10347 | begin //{ |
| 10348 | //valid stb ram rd for issue to pcx |
| 10349 | stb_err_inj = 1'b0; |
| 10350 | if (`SPC4.lsu.sbc.ram_rptr_vld_2 & `SPC4.lsu.sbc.st_pcx_rq_p3 & `SPC4.lsu.pic.pic_st_sel_p3) |
| 10351 | begin //{ |
| 10352 | err_tid = decode_tid(`SPC4.lsu.sbc.st_rq_sel_p3[7:0]); |
| 10353 | err_index = `SPC4.lsu.sbc.ram_rptr_d1; |
| 10354 | err_tmp = stb[{err_tid, err_index}]; |
| 10355 | err_inst = err_tmp[`LSU_MON_INST]; |
| 10356 | cam_data = `SPC4.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 10357 | err_priv = err_tmp[`ST_PRIV]; |
| 10358 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 10359 | if (err_inst[`CASA]) |
| 10360 | begin //{ |
| 10361 | err_inj_cnt = err_inj_cnt + 1; |
| 10362 | if (err_inj_cnt == 10) |
| 10363 | begin //{ |
| 10364 | case (err_bit) |
| 10365 | 11, 12: err_bit = err_bit + 1; |
| 10366 | 13: err_bit = 44; |
| 10367 | 44: err_bit = 11; |
| 10368 | endcase |
| 10369 | err_inj_cnt = 0; |
| 10370 | stb_err_inj = 1'b1; |
| 10371 | |
| 10372 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 10373 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 10374 | #1; |
| 10375 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 10376 | end //} |
| 10377 | end //} |
| 10378 | end //} |
| 10379 | if (stb_err_inj_d2) |
| 10380 | begin |
| 10381 | if (~`SPC4.lsu_sbapp_err_g) |
| 10382 | begin |
| 10383 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 10384 | end |
| 10385 | else |
| 10386 | begin |
| 10387 | if ((`SPC4.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 10388 | (`SPC4.lsu_stberr_index_g != stb_err_index_d2) || |
| 10389 | (`SPC4.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 10390 | begin |
| 10391 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 10392 | end |
| 10393 | end |
| 10394 | end |
| 10395 | else |
| 10396 | begin |
| 10397 | if (`SPC4.lsu_sbapp_err_g) |
| 10398 | begin |
| 10399 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC4.lsu_stberr_tid_g); |
| 10400 | end |
| 10401 | end |
| 10402 | |
| 10403 | end //} |
| 10404 | |
| 10405 | |
| 10406 | always @ (posedge (`SPC4.l2clk & enabled & cmp_stb_err_inj)) |
| 10407 | begin |
| 10408 | stb_err_inj_d1 <= stb_err_inj; |
| 10409 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 10410 | stb_err_tid_d1 <= err_tid; |
| 10411 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 10412 | stb_err_index_d1 <= err_index; |
| 10413 | stb_err_index_d2 <= stb_err_index_d1; |
| 10414 | stb_err_priv_d1 <= err_priv; |
| 10415 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 10416 | end |
| 10417 | |
| 10418 | `endif |
| 10419 | `endif |
| 10420 | `endif |
| 10421 | endmodule |
| 10422 | |
| 10423 | `endif |
| 10424 | `ifdef CORE_5 |
| 10425 | |
| 10426 | module lsu_mon_c5; |
| 10427 | `ifndef GATESIM |
| 10428 | |
| 10429 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 10430 | `ifndef NO_MONITORS |
| 10431 | |
| 10432 | reg imm_asi_vld_e; |
| 10433 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 10434 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 10435 | reg [1:0] exu_ecc_b; |
| 10436 | reg [1:0] exu_lsu_va_error_b; |
| 10437 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 10438 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 10439 | reg [31:0] inst_e, inst_m, inst_b; |
| 10440 | reg [47:0] vaddr_m, vaddr_b; |
| 10441 | reg [63:0] int_st_data_m, int_st_data_b; |
| 10442 | reg [63:0] fp_st_sata_fx2; |
| 10443 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 10444 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 10445 | |
| 10446 | reg [7:0] ld_valid; |
| 10447 | reg [7:0] tlb_valid; |
| 10448 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 10449 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 10450 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 10451 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 10452 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 10453 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 10454 | //the L2c. |
| 10455 | reg [63:0] stb_valid; |
| 10456 | reg [`STB_Pend_Width] stb[63:0]; |
| 10457 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 10458 | |
| 10459 | reg [7:0] pf_cnt[7:0]; |
| 10460 | reg [7:0] dcache_inv_cnt[7:0]; |
| 10461 | reg [7:0] st_rmo_cnt[7:0]; |
| 10462 | |
| 10463 | reg [55:0] print_inst; |
| 10464 | |
| 10465 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 10466 | |
| 10467 | reg [7:0] lsu_bst_active; |
| 10468 | reg store_alloc; |
| 10469 | reg [3:0] bst_cnt; |
| 10470 | reg [195:0] stb_alloc_data; |
| 10471 | reg [195:0] bst_data, bst_inst_data; |
| 10472 | reg [2:0] bst_active_thid; |
| 10473 | reg bst_fgu_err; |
| 10474 | |
| 10475 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 10476 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 10477 | //different types of err occur on blk ld helper returns |
| 10478 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 10479 | //stored in DFESR |
| 10480 | |
| 10481 | wire [2:0] core_id = 5; |
| 10482 | |
| 10483 | integer i; |
| 10484 | integer err_cnt; |
| 10485 | |
| 10486 | reg enabled; |
| 10487 | reg reset_in_middle; |
| 10488 | reg [7:0] finish_mask; |
| 10489 | |
| 10490 | initial |
| 10491 | begin |
| 10492 | enabled = 0; |
| 10493 | reset_in_middle = 0; |
| 10494 | ld_valid = 8'b0; |
| 10495 | lsu_inst_e = 0; |
| 10496 | tlb_valid = 8'b0; |
| 10497 | for (i = 0; i < 8; i = i+1) |
| 10498 | begin |
| 10499 | pf_cnt[i] = 0; |
| 10500 | dcache_inv_cnt[i] = 0; |
| 10501 | wrptr[i] = 0; |
| 10502 | rdptr[i] = 0; |
| 10503 | iss_ptr[i] = 0; |
| 10504 | ret_ptr[i] = 0; |
| 10505 | st_rmo_cnt[i] = 0; |
| 10506 | is_blkld[i] = 1'b0; |
| 10507 | st_priv[i] = 2'b0; |
| 10508 | l2_blk_ld_errtype[i] = 2'b0; |
| 10509 | end |
| 10510 | lsu_bst_active = 8'b0; |
| 10511 | store_alloc = 1'b0; |
| 10512 | bst_cnt = 4'b0; |
| 10513 | stb_valid = 64'b0; |
| 10514 | |
| 10515 | // avoid time zero ugliness. jp |
| 10516 | //@(posedge `SPC0.l2clk); |
| 10517 | //@(negedge `SPC0.l2clk); |
| 10518 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 10519 | |
| 10520 | case (core_id) |
| 10521 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 10522 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 10523 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 10524 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 10525 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 10526 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 10527 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 10528 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 10529 | endcase |
| 10530 | end |
| 10531 | |
| 10532 | always @ (`TOP.in_reset) |
| 10533 | begin |
| 10534 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 10535 | begin |
| 10536 | enabled = 1'b1; |
| 10537 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 10538 | end |
| 10539 | |
| 10540 | |
| 10541 | if (`TOP.in_reset & enabled) |
| 10542 | begin |
| 10543 | reset_in_middle = 1'b1; |
| 10544 | enabled = 1'b0; |
| 10545 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 10546 | end |
| 10547 | end |
| 10548 | |
| 10549 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 10550 | begin //{ |
| 10551 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 10552 | begin //{ |
| 10553 | for (i = 0; i < 8; i=i+1) |
| 10554 | begin |
| 10555 | if (ld_valid[i]) |
| 10556 | begin |
| 10557 | DispPendReq(i); |
| 10558 | end |
| 10559 | end |
| 10560 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 10561 | end //} |
| 10562 | if (|stb_valid[63:0]) |
| 10563 | begin //{ |
| 10564 | err_cnt = 0; |
| 10565 | for (i = 0; i < 64; i=i+1) |
| 10566 | begin |
| 10567 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 10568 | begin |
| 10569 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 10570 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 10571 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 10572 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 10573 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 10574 | //of simualation. |
| 10575 | if (~is_squash_bit_set(i[5:0])) |
| 10576 | begin |
| 10577 | err_cnt = err_cnt + 1; |
| 10578 | Disp_STB_entry(i[5:3],i[2:0]); |
| 10579 | end |
| 10580 | end |
| 10581 | end |
| 10582 | if (err_cnt) |
| 10583 | begin |
| 10584 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 10585 | end |
| 10586 | end //} |
| 10587 | err_cnt = 0; |
| 10588 | for (i = 0; i < 8; i=i+1) |
| 10589 | begin //{ |
| 10590 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 10591 | begin |
| 10592 | err_cnt = 1; |
| 10593 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 10594 | end |
| 10595 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 10596 | begin |
| 10597 | err_cnt = 1; |
| 10598 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 10599 | end |
| 10600 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 10601 | begin |
| 10602 | err_cnt = 1; |
| 10603 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 10604 | end |
| 10605 | end //} |
| 10606 | if (err_cnt) |
| 10607 | begin |
| 10608 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 10609 | end |
| 10610 | end //} |
| 10611 | |
| 10612 | function is_squash_bit_set; |
| 10613 | input [5:0] index; |
| 10614 | reg [204:0] tmp; |
| 10615 | begin |
| 10616 | tmp = stb[index]; |
| 10617 | if (tmp[`ST_SQUASH]) |
| 10618 | is_squash_bit_set = 1'b1; |
| 10619 | else |
| 10620 | is_squash_bit_set = 1'b0; |
| 10621 | end |
| 10622 | endfunction |
| 10623 | |
| 10624 | |
| 10625 | always @ (negedge (`SPC5.l2clk & enabled)) |
| 10626 | begin //{ |
| 10627 | |
| 10628 | asi_e = `SPC5.lsu.dcc.dcc_asi_e[7:0]; |
| 10629 | |
| 10630 | lsu_inst_e[`LD] <= `SPC5.dec_ld_inst_e; |
| 10631 | lsu_inst_e[`ST] <= `SPC5.dec_st_inst_e; |
| 10632 | lsu_inst_e[`FP] <= `SPC5.dec_fpldst_inst_e; |
| 10633 | lsu_inst_e[`PREF] <= `SPC5.dec_pref_inst_e; |
| 10634 | lsu_inst_e[`SWAP] <= `SPC5.dec_swap_inst_e; |
| 10635 | lsu_inst_e[`CASA] <= `SPC5.dec_casa_inst_e; |
| 10636 | lsu_inst_e[`LDSTUB] <= `SPC5.dec_ldstub_inst_e; |
| 10637 | lsu_inst_e[`FLUSH] <= `SPC5.dec_flush_inst_e; |
| 10638 | lsu_inst_e[`MEMBAR] <= `SPC5.dec_memstbar_inst_e; |
| 10639 | lsu_inst_e[`LDD] <= `SPC5.dec_ld_inst_e & `SPC5.dec_ldst_dbl_e & ~`SPC5.dec_fpldst_inst_e; |
| 10640 | lsu_inst_e[`STD] <= `SPC5.dec_st_inst_e & `SPC5.dec_ldst_dbl_e & ~`SPC5.lsu.dec_fpldst_inst_e; |
| 10641 | |
| 10642 | lsu_inst_e[`BLKLD] <= `SPC5.dec_ld_inst_e & `SPC5.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 10643 | lsu_inst_e[`BLKST] <= `SPC5.dec_st_inst_e & `SPC5.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 10644 | lsu_inst_e[`QLD] <= `SPC5.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 10645 | lsu_inst_e[`ASR_RD_WR] <= `SPC5.dec_sr_inst_e & (`SPC5.dec_ld_inst_e | `SPC5.dec_st_inst_e); |
| 10646 | lsu_inst_e[`PR_RD_WR] <= `SPC5.dec_pr_inst_e & (`SPC5.dec_ld_inst_e | `SPC5.dec_st_inst_e); |
| 10647 | lsu_inst_e[`HPR_RD_WR] <= `SPC5.dec_hpr_inst_e & (`SPC5.dec_ld_inst_e | `SPC5.dec_st_inst_e); |
| 10648 | lsu_inst_e[`FSR_RD_WR] <= `SPC5.dec_fsr_ldst_e & (`SPC5.dec_ld_inst_e | `SPC5.dec_st_inst_e); |
| 10649 | end //} |
| 10650 | |
| 10651 | always @ (posedge (`SPC5.l2clk & enabled)) |
| 10652 | begin //{ |
| 10653 | dec_tg0_inst_d <= `SPC5.dec.ded0.decode_mux[31:0]; |
| 10654 | dec_tg1_inst_d <= `SPC5.dec.ded1.decode_mux[31:0]; |
| 10655 | imm_asi_vld_e <= `SPC5.lsu.dec_imm_asi_vld_d; |
| 10656 | |
| 10657 | imm_asi_e <= `SPC5.lsu.dec_imm_asi_d; |
| 10658 | dec_altspace_e <= `SPC5.dec_altspace_d; |
| 10659 | dec_altspace_m <= dec_altspace_e; |
| 10660 | dec_altspace_b <= dec_altspace_m; |
| 10661 | |
| 10662 | exu_ecc_b <= `SPC5.exu_ecc_m; |
| 10663 | exu_lsu_va_error_b <= `SPC5.exu_lsu_va_error_m; |
| 10664 | |
| 10665 | dec_lsu_tid_e <= `SPC5.dec_lsu_tg_d ? {1'b1, `SPC5.dec_lsu_tid1_d} : {1'b0, `SPC5.dec_lsu_tid0_d}; |
| 10666 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 10667 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 10668 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 10669 | |
| 10670 | inst_pc_e <= `SPC5.dec_lsu_tg_d ? {`SPC5.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC5.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 10671 | inst_pc_m <= inst_pc_e; |
| 10672 | inst_pc_b <= inst_pc_m; |
| 10673 | inst_pc_w <= inst_pc_b; |
| 10674 | |
| 10675 | inst_e <= `SPC5.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 10676 | inst_m <= inst_e; |
| 10677 | inst_b <= inst_m; |
| 10678 | |
| 10679 | vaddr_m <= `SPC5.exu_lsu_address_e; |
| 10680 | vaddr_b <= vaddr_m; |
| 10681 | |
| 10682 | int_st_data_m <= `SPC5.exu_lsu_store_data_e; |
| 10683 | int_st_data_b <= int_st_data_m; |
| 10684 | fp_st_sata_fx2 <= `SPC5.fgu_lsu_fst_data_fx1; |
| 10685 | |
| 10686 | mmu_dtlb_reload_d1 <= `SPC5.mmu_dtlb_reload; |
| 10687 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 10688 | |
| 10689 | //pcx_thid_d1 <= `SPC5.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 10690 | lsu_inst_m <= lsu_inst_e; |
| 10691 | lsu_inst_b <= lsu_inst_m; |
| 10692 | |
| 10693 | asi_m <= asi_e; |
| 10694 | asi_b <= asi_m; |
| 10695 | end //} |
| 10696 | |
| 10697 | function Is_blk_asi; |
| 10698 | input [7:0] asi; |
| 10699 | begin |
| 10700 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 10701 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 10702 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 10703 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 10704 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 10705 | end |
| 10706 | endfunction |
| 10707 | |
| 10708 | function Is_qld_asi; |
| 10709 | input [7:0] asi; |
| 10710 | begin |
| 10711 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 10712 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 10713 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 10714 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 10715 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 10716 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 10717 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 10718 | end |
| 10719 | endfunction |
| 10720 | |
| 10721 | function Is_bis_asi; |
| 10722 | input [7:0] asi; |
| 10723 | begin |
| 10724 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 10725 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 10726 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 10727 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 10728 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 10729 | end |
| 10730 | endfunction |
| 10731 | |
| 10732 | always @ (negedge (`SPC5.l2clk & enabled)) |
| 10733 | begin //{ |
| 10734 | Chk_store; |
| 10735 | store_alloc = 1'b0; |
| 10736 | if (lsu_inst_m != 0) |
| 10737 | begin |
| 10738 | if (`SPC5.dec_flush_lm) |
| 10739 | begin |
| 10740 | lsu_inst_m <= 0; |
| 10741 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 10742 | end |
| 10743 | end |
| 10744 | |
| 10745 | if (lsu_inst_b != 0) |
| 10746 | begin //{ |
| 10747 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 10748 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 10749 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 10750 | else print_inst = ""; |
| 10751 | |
| 10752 | if (`SPC5.dec_flush_lb) |
| 10753 | begin |
| 10754 | lsu_inst_b <= 0; |
| 10755 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 10756 | end |
| 10757 | else if (`SPC5.tlu_flush_lsu_b) |
| 10758 | begin |
| 10759 | lsu_inst_b <= 0; |
| 10760 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 10761 | end |
| 10762 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 10763 | //casa shd be killed. |
| 10764 | //This function will also chk for errors on 2nd cycle. |
| 10765 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 10766 | begin |
| 10767 | lsu_inst_b <= 0; |
| 10768 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 10769 | end |
| 10770 | else if ((`SPC5.fgu_cecc_fx2 || `SPC5.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 10771 | begin |
| 10772 | lsu_inst_b <= 0; |
| 10773 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 10774 | end |
| 10775 | else if (IsExc(core_id)) |
| 10776 | lsu_inst_b <= 0; |
| 10777 | else if (!`SPC5.lsu_tlb_miss_b_) |
| 10778 | begin |
| 10779 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 10780 | //Insert_tlb_miss_info; |
| 10781 | end |
| 10782 | else |
| 10783 | begin //{ |
| 10784 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 10785 | //an exception tlu anyway tells the front end to flush itself there is |
| 10786 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 10787 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 10788 | //handles it when it is reissued by the front end. |
| 10789 | |
| 10790 | if (`SPC5.lsu_tlb_bypass_b) |
| 10791 | begin |
| 10792 | if (`SPC5.lsu_sync != 8'b0) |
| 10793 | begin |
| 10794 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 10795 | end |
| 10796 | else |
| 10797 | begin |
| 10798 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 10799 | end |
| 10800 | end |
| 10801 | else |
| 10802 | begin |
| 10803 | if (`SPC5.lsu_sync != 8'b0) |
| 10804 | begin |
| 10805 | if (lsu_inst_b[`ST]) |
| 10806 | begin |
| 10807 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 10808 | end |
| 10809 | else |
| 10810 | begin |
| 10811 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 10812 | end |
| 10813 | end |
| 10814 | else |
| 10815 | begin |
| 10816 | if (lsu_inst_b[`ST]) |
| 10817 | begin |
| 10818 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 10819 | end |
| 10820 | else |
| 10821 | begin |
| 10822 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 10823 | end |
| 10824 | end |
| 10825 | end |
| 10826 | |
| 10827 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 10828 | begin //{ |
| 10829 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC5.lsu.stb_cam_hit) |
| 10830 | begin |
| 10831 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 10832 | end |
| 10833 | end //} |
| 10834 | |
| 10835 | if (lsu_inst_b[`LD]) |
| 10836 | Insert_ld_miss_info; |
| 10837 | |
| 10838 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 10839 | begin |
| 10840 | Make_STB_data; |
| 10841 | store_alloc = 1'b1; |
| 10842 | end |
| 10843 | Insert_in_last_inst_array; |
| 10844 | |
| 10845 | if (`SPC5.lsu_trap_flush[7:0]) |
| 10846 | begin |
| 10847 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC5.lsu_trap_flush[7:0])); |
| 10848 | end |
| 10849 | end //} |
| 10850 | end //} |
| 10851 | end //} |
| 10852 | |
| 10853 | //STB ue testing: |
| 10854 | //This is how we test squashing of stores by LSU_mon: |
| 10855 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 10856 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 10857 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 10858 | //The squashed stores are deallocated when either a block_store_kill is |
| 10859 | //asserted or dealloc signals are asserted by the LSU. |
| 10860 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 10861 | //all the pending stores in the IFU. It means the when block_store_kill |
| 10862 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 10863 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 10864 | //the sbdiou signal to TLU. |
| 10865 | |
| 10866 | |
| 10867 | always @ (negedge (`SPC5.l2clk & enabled)) |
| 10868 | begin |
| 10869 | if (`SPC5.lsu_l15_valid & `SPC5.lsu.spc_pcx_data_pa[129]) |
| 10870 | Chk_pcx_req_pkt(`SPC5.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 10871 | if ((`SPC5.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC5.lsu_rngl_cdbus[59]) |
| 10872 | Chk_st_on_ASI_ring(`LOCAL); |
| 10873 | |
| 10874 | if ((`SPC5.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC5.lsu_rngf_cdbus[59]) |
| 10875 | Chk_st_on_ASI_ring(`FAST); |
| 10876 | |
| 10877 | //if (`SPC5.l15_lsu_valid) |
| 10878 | //Chk_cpx_response_pkt({`SPC5.l15_lsu_valid, `SPC5.l15_lsu_cpkt[17:13],`SPC5.l15_lsu_cpkt[11:0],`SPC5.l15_spc_data1[127:0]}); |
| 10879 | |
| 10880 | if (`SPC5.cpx_spc_data_cx[145]) |
| 10881 | Chk_cpx_response_pkt(`SPC5.cpx_spc_data_cx); |
| 10882 | |
| 10883 | if (`SPC5.lsu_complete[7:0] != 8'b0) |
| 10884 | begin |
| 10885 | if (`SPC5.lsu_complete[0]) Chk_ld_complete(0); |
| 10886 | if (`SPC5.lsu_complete[1]) Chk_ld_complete(1); |
| 10887 | if (`SPC5.lsu_complete[2]) Chk_ld_complete(2); |
| 10888 | if (`SPC5.lsu_complete[3]) Chk_ld_complete(3); |
| 10889 | if (`SPC5.lsu_complete[4]) Chk_ld_complete(4); |
| 10890 | if (`SPC5.lsu_complete[5]) Chk_ld_complete(5); |
| 10891 | if (`SPC5.lsu_complete[6]) Chk_ld_complete(6); |
| 10892 | if (`SPC5.lsu_complete[7]) Chk_ld_complete(7); |
| 10893 | end |
| 10894 | |
| 10895 | if (`SPC5.lsu_block_store_kill[7:0] != 8'b0) |
| 10896 | begin |
| 10897 | if (`SPC5.lsu_block_store_kill[0]) Squash_STB(0); |
| 10898 | if (`SPC5.lsu_block_store_kill[1]) Squash_STB(1); |
| 10899 | if (`SPC5.lsu_block_store_kill[2]) Squash_STB(2); |
| 10900 | if (`SPC5.lsu_block_store_kill[3]) Squash_STB(3); |
| 10901 | if (`SPC5.lsu_block_store_kill[4]) Squash_STB(4); |
| 10902 | if (`SPC5.lsu_block_store_kill[5]) Squash_STB(5); |
| 10903 | if (`SPC5.lsu_block_store_kill[6]) Squash_STB(6); |
| 10904 | if (`SPC5.lsu_block_store_kill[7]) Squash_STB(7); |
| 10905 | end |
| 10906 | |
| 10907 | if (`SPC5.lsu_stb_dealloc[7:0] != 8'b0) |
| 10908 | begin |
| 10909 | if (`SPC5.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 10910 | if (`SPC5.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 10911 | if (`SPC5.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 10912 | if (`SPC5.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 10913 | if (`SPC5.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 10914 | if (`SPC5.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 10915 | if (`SPC5.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 10916 | if (`SPC5.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 10917 | end |
| 10918 | |
| 10919 | if (`SPC5.lsu_block_store_stall) |
| 10920 | Chk_block_store; |
| 10921 | |
| 10922 | if (`SPC5.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 10923 | Set_block_store_parameters; |
| 10924 | |
| 10925 | if (`SPC5.lsu_sbdiou_err_g || `SPC5.lsu_sbapp_err_g) |
| 10926 | Squash_store; |
| 10927 | |
| 10928 | if (`SPC5.lsu_stb_flush_g) |
| 10929 | st_priv[`SPC5.lsu_stberr_tid_g] = get_priv_on_flush(`SPC5.lsu_stberr_tid_g); |
| 10930 | end |
| 10931 | |
| 10932 | function [1:0] get_priv_on_flush; |
| 10933 | input [2:0] tid; |
| 10934 | reg [2:0] sq_index; |
| 10935 | reg [204:0] tmp; |
| 10936 | |
| 10937 | begin |
| 10938 | sq_index = `SPC5.lsu_stberr_index_g; |
| 10939 | tmp = stb[{tid, sq_index}]; |
| 10940 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 10941 | end |
| 10942 | endfunction |
| 10943 | |
| 10944 | task Chk_block_store; |
| 10945 | reg [20:0] inst; |
| 10946 | reg [2:0] thid; |
| 10947 | begin |
| 10948 | thid = `SPC5.lsu_block_store_tid; |
| 10949 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 10950 | inst = bst_inst_data[`LSU_MON_INST]; |
| 10951 | |
| 10952 | if (~inst[`BLKST]) |
| 10953 | begin |
| 10954 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 10955 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 10956 | end |
| 10957 | end |
| 10958 | endtask |
| 10959 | |
| 10960 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 10961 | //the 8 stb entries from the previous blk store. |
| 10962 | |
| 10963 | task Set_block_store_parameters; |
| 10964 | reg [2:0] thid; |
| 10965 | begin |
| 10966 | |
| 10967 | thid = decode_tid(`SPC5.lsu.lsu_block_store_alloc[7:0]); |
| 10968 | if (lsu_bst_active[thid]) |
| 10969 | begin |
| 10970 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 10971 | end |
| 10972 | else |
| 10973 | begin |
| 10974 | lsu_bst_active[thid] = 1'b1; |
| 10975 | bst_active_thid = thid; |
| 10976 | if (`SPC5.lsu.fgu_fst_ecc_error_fx2) |
| 10977 | bst_fgu_err = 1'b1; |
| 10978 | else |
| 10979 | bst_fgu_err = 1'b0; |
| 10980 | end |
| 10981 | end |
| 10982 | endtask |
| 10983 | |
| 10984 | task Squash_store; |
| 10985 | reg [2:0] thid; |
| 10986 | reg [2:0] sq_index; |
| 10987 | reg [2:0] i; |
| 10988 | reg [204:0] tmp; |
| 10989 | reg [3:0] squash_cnt; |
| 10990 | reg [1:0] priv; |
| 10991 | |
| 10992 | begin |
| 10993 | thid = `SPC5.lsu_stberr_tid_g; |
| 10994 | sq_index = `SPC5.lsu_stberr_index_g; |
| 10995 | priv = `SPC5.lsu_stberr_priv_g; |
| 10996 | tmp = stb[{thid, sq_index}]; |
| 10997 | squash_cnt = 0; |
| 10998 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 10999 | |
| 11000 | st_priv[thid] = tmp[`ST_PRIV]; |
| 11001 | |
| 11002 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 11003 | //In that case iss_ptr won't be equal to sbdiou index. |
| 11004 | //if (sq_index != iss_ptr[thid]) |
| 11005 | //begin |
| 11006 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 11007 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 11008 | //end |
| 11009 | |
| 11010 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 11011 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 11012 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 11013 | //removing this chk. |
| 11014 | |
| 11015 | //if (tmp[`L2_ST_ISS]) |
| 11016 | //begin |
| 11017 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 11018 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 11019 | //end |
| 11020 | |
| 11021 | if (iss_ptr[thid] == wrptr[thid]) |
| 11022 | begin |
| 11023 | if (stb_valid[{thid, wrptr[thid]}]) |
| 11024 | squash_cnt = 8; |
| 11025 | else |
| 11026 | begin |
| 11027 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 11028 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 11029 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 11030 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 11031 | end |
| 11032 | end |
| 11033 | else |
| 11034 | begin |
| 11035 | if (iss_ptr[thid] < wrptr[thid]) |
| 11036 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 11037 | else if (iss_ptr[thid] > wrptr[thid]) |
| 11038 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 11039 | end |
| 11040 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 11041 | |
| 11042 | i = iss_ptr[thid]; |
| 11043 | |
| 11044 | while (squash_cnt) |
| 11045 | begin |
| 11046 | tmp = stb[{thid, i}]; |
| 11047 | tmp[`ST_SQUASH] = 1'b1; |
| 11048 | if (priv < tmp[`ST_PRIV]) |
| 11049 | begin |
| 11050 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 11051 | priv = tmp[`ST_PRIV]; |
| 11052 | end |
| 11053 | |
| 11054 | stb[{thid, i}] = tmp; |
| 11055 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 11056 | |
| 11057 | i = i + 1; |
| 11058 | squash_cnt = squash_cnt - 1'b1; |
| 11059 | end |
| 11060 | end |
| 11061 | endtask |
| 11062 | |
| 11063 | function [2:0] decode_tid; |
| 11064 | input [7:0] thid_encode; |
| 11065 | begin |
| 11066 | case (thid_encode) |
| 11067 | 8'h1: decode_tid = 3'b0; |
| 11068 | 8'h2: decode_tid = 3'h1; |
| 11069 | 8'h4: decode_tid = 3'h2; |
| 11070 | 8'h8: decode_tid = 3'h3; |
| 11071 | 8'h10: decode_tid = 3'h4; |
| 11072 | 8'h20: decode_tid = 3'h5; |
| 11073 | 8'h40: decode_tid = 3'h6; |
| 11074 | 8'h80: decode_tid = 3'h7; |
| 11075 | default: |
| 11076 | begin |
| 11077 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 11078 | end |
| 11079 | endcase |
| 11080 | end |
| 11081 | endfunction |
| 11082 | |
| 11083 | task Chk_ld_complete; |
| 11084 | input [2:0] thid; |
| 11085 | reg [`LD_Pend_Width] tmp; |
| 11086 | begin |
| 11087 | tmp = ld_pend_array[thid]; |
| 11088 | |
| 11089 | if (ld_valid[thid]) |
| 11090 | begin |
| 11091 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 11092 | begin |
| 11093 | DispPendReq(thid); |
| 11094 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 11095 | end |
| 11096 | ld_valid[thid] = 1'b0; |
| 11097 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 11098 | end |
| 11099 | |
| 11100 | tmp = last_inst_array[thid]; |
| 11101 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 11102 | end |
| 11103 | endtask |
| 11104 | |
| 11105 | task Chk_pcx_req_pkt; |
| 11106 | input [129:0] pcx_pkt; |
| 11107 | reg [2:0] thid; |
| 11108 | reg [`LD_Pend_Width] tmp, tmp1; |
| 11109 | reg [15:0] inst; |
| 11110 | reg [11*8:0] req; |
| 11111 | reg [39:0] addr; |
| 11112 | begin |
| 11113 | thid = pcx_pkt[`PCX_THR_ID]; |
| 11114 | tmp = ld_pend_array[thid]; |
| 11115 | inst = tmp[`LSU_MON_INST]; |
| 11116 | req = DispPCXReq(pcx_pkt); |
| 11117 | addr = pcx_pkt[`PCX_ADDR]; |
| 11118 | |
| 11119 | |
| 11120 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 11121 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 11122 | |
| 11123 | |
| 11124 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 11125 | begin |
| 11126 | if (~ld_valid[thid]) |
| 11127 | begin |
| 11128 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 11129 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 11130 | end |
| 11131 | if (~inst[`BLKLD]) |
| 11132 | begin |
| 11133 | if (tmp[`MEMOP_PA] != addr) |
| 11134 | begin |
| 11135 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 11136 | begin |
| 11137 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 11138 | end |
| 11139 | else |
| 11140 | begin |
| 11141 | DispPendReq(thid); |
| 11142 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 11143 | end |
| 11144 | end |
| 11145 | end |
| 11146 | end |
| 11147 | |
| 11148 | case (pcx_pkt[`PCX_RQTYP]) |
| 11149 | `PCX_LOAD: |
| 11150 | begin |
| 11151 | if (pcx_pkt[`PCX_PF]) |
| 11152 | begin |
| 11153 | if (~inst[`PREF]) |
| 11154 | begin |
| 11155 | DispPendReq(thid); |
| 11156 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 11157 | end |
| 11158 | if (pcx_pkt[`PCX_INV]) |
| 11159 | begin |
| 11160 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 11161 | end |
| 11162 | else |
| 11163 | begin |
| 11164 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 11165 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 11166 | end |
| 11167 | tmp[`L2_ISS] = 4'hF; |
| 11168 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 11169 | ld_pend_array[thid] = tmp; |
| 11170 | end |
| 11171 | else |
| 11172 | begin |
| 11173 | if (pcx_pkt[`PCX_INV]) |
| 11174 | begin |
| 11175 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11176 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 11177 | end |
| 11178 | else |
| 11179 | begin |
| 11180 | Chk_req_load(pcx_pkt); |
| 11181 | end |
| 11182 | end |
| 11183 | end |
| 11184 | `PCX_CAS1, `PCX_CAS2: |
| 11185 | begin |
| 11186 | if (~inst[`CASA]) |
| 11187 | begin |
| 11188 | DispPendReq(thid); |
| 11189 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 11190 | end |
| 11191 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 11192 | begin |
| 11193 | tmp[`L2_ISS] = 4'hE; |
| 11194 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11195 | ld_pend_array[thid] = tmp; |
| 11196 | end |
| 11197 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 11198 | begin |
| 11199 | tmp[`L2_ISS] = 4'hF; |
| 11200 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11201 | ld_pend_array[thid] = tmp; |
| 11202 | chk_store_issue_to_pcx(pcx_pkt); |
| 11203 | end |
| 11204 | |
| 11205 | end |
| 11206 | `PCX_SWAP_LDSTUB: |
| 11207 | begin |
| 11208 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 11209 | begin |
| 11210 | DispPendReq(thid); |
| 11211 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 11212 | end |
| 11213 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 11214 | tmp[`L2_ISS] = 4'hF; |
| 11215 | ld_pend_array[thid] = tmp; |
| 11216 | |
| 11217 | chk_store_issue_to_pcx(pcx_pkt); |
| 11218 | end |
| 11219 | |
| 11220 | `PCX_STORE: |
| 11221 | begin |
| 11222 | chk_store_issue_to_pcx(pcx_pkt); |
| 11223 | end |
| 11224 | |
| 11225 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 11226 | endcase |
| 11227 | end |
| 11228 | endtask |
| 11229 | |
| 11230 | task Chk_cpx_response_pkt; |
| 11231 | input [145:0] cpx_pkt; |
| 11232 | reg [2:0] thid; |
| 11233 | begin |
| 11234 | thid = cpx_pkt[`CPX_THR_ID]; |
| 11235 | |
| 11236 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 11237 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 11238 | begin |
| 11239 | chk_ccx_ld_response(cpx_pkt); |
| 11240 | end |
| 11241 | |
| 11242 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 11243 | begin |
| 11244 | if (pf_cnt[thid] == 8'b0) |
| 11245 | begin |
| 11246 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 11247 | end |
| 11248 | else |
| 11249 | begin |
| 11250 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 11251 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 11252 | end |
| 11253 | end |
| 11254 | |
| 11255 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 11256 | chk_ccx_ld_response(cpx_pkt); |
| 11257 | |
| 11258 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 11259 | begin |
| 11260 | if (cpx_pkt[123]) //D pkt |
| 11261 | begin //{ |
| 11262 | if (cpx_pkt[120:118] != core_id) |
| 11263 | begin |
| 11264 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 11265 | end |
| 11266 | if (dcache_inv_cnt[thid] == 8'b0) |
| 11267 | begin |
| 11268 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 11269 | end |
| 11270 | else |
| 11271 | begin |
| 11272 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 11273 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 11274 | end |
| 11275 | end //} |
| 11276 | else if (cpx_pkt[124]) //I pkt |
| 11277 | begin |
| 11278 | if (cpx_pkt[120:118] != core_id) |
| 11279 | begin |
| 11280 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 11281 | end |
| 11282 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 11283 | end |
| 11284 | else if (cpx_pkt[124:123] == 2'b0) |
| 11285 | begin |
| 11286 | if (cpx_pkt[120:118] == core_id) |
| 11287 | begin |
| 11288 | chk_ccx_st_response(cpx_pkt); |
| 11289 | end |
| 11290 | else |
| 11291 | begin |
| 11292 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 11293 | end |
| 11294 | end |
| 11295 | end |
| 11296 | |
| 11297 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 11298 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 11299 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 11300 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 11301 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 11302 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 11303 | |
| 11304 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 11305 | begin |
| 11306 | chk_ccx_atm_response(cpx_pkt); |
| 11307 | end |
| 11308 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 11309 | begin |
| 11310 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 11311 | begin |
| 11312 | chk_ccx_atm_response(cpx_pkt); |
| 11313 | chk_ccx_st_response(cpx_pkt); |
| 11314 | end |
| 11315 | end |
| 11316 | |
| 11317 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 11318 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 11319 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 11320 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 11321 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 11322 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 11323 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 11324 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 11325 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 11326 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 11327 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 11328 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 11329 | |
| 11330 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 11331 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 11332 | |
| 11333 | default: |
| 11334 | begin |
| 11335 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 11336 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 11337 | |
| 11338 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 11339 | end |
| 11340 | |
| 11341 | endcase |
| 11342 | end |
| 11343 | endtask |
| 11344 | |
| 11345 | task chk_ccx_ld_response; |
| 11346 | input [145:0] cpx_pkt; |
| 11347 | reg [2:0] thid; |
| 11348 | reg [20:0] inst; |
| 11349 | reg [39:0] cpx_pa, inst_pa; |
| 11350 | reg [`LD_Pend_Width] tmp; |
| 11351 | reg [3:0] pkt_type; |
| 11352 | begin |
| 11353 | thid = cpx_pkt[`CPX_THR_ID]; |
| 11354 | tmp = ld_pend_array[thid]; |
| 11355 | inst = tmp[`LSU_MON_INST]; |
| 11356 | inst_pa = tmp[`MEMOP_PA]; |
| 11357 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 11358 | |
| 11359 | if (ld_valid[thid]) |
| 11360 | begin |
| 11361 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 11362 | /* |
| 11363 | if (inst_pa[39] != pkt_type[3]) |
| 11364 | begin |
| 11365 | DispPendReq(thid); |
| 11366 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 11367 | end |
| 11368 | */ |
| 11369 | |
| 11370 | if (inst[`BLKLD]) |
| 11371 | begin |
| 11372 | if (tmp[`L2_RESP] == 4'h0) |
| 11373 | begin |
| 11374 | tmp[`L2_RESP] = 4'h1; |
| 11375 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 11376 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 11377 | begin |
| 11378 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 11379 | end |
| 11380 | |
| 11381 | end |
| 11382 | else if (tmp[`L2_RESP] == 4'h1) |
| 11383 | begin |
| 11384 | tmp[`L2_RESP] = 4'h3; |
| 11385 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 11386 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 11387 | begin |
| 11388 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 11389 | end |
| 11390 | end |
| 11391 | else if (tmp[`L2_RESP] == 4'h3) |
| 11392 | begin |
| 11393 | tmp[`L2_RESP] = 4'h7; |
| 11394 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 11395 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 11396 | begin |
| 11397 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 11398 | end |
| 11399 | end |
| 11400 | else if (tmp[`L2_RESP] == 4'h7) |
| 11401 | begin |
| 11402 | tmp[`L2_RESP] = 4'hF; |
| 11403 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 11404 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 11405 | begin |
| 11406 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 11407 | end |
| 11408 | |
| 11409 | //is_blkld[thid] = 1'b1; |
| 11410 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 11411 | l2_blk_ld_errtype[thid] = `ND; |
| 11412 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 11413 | l2_blk_ld_errtype[thid] = `UE; |
| 11414 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 11415 | l2_blk_ld_errtype[thid] = `CE; |
| 11416 | else |
| 11417 | l2_blk_ld_errtype[thid] = `NE; |
| 11418 | end |
| 11419 | else |
| 11420 | begin |
| 11421 | DispPendReq(thid); |
| 11422 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 11423 | end |
| 11424 | end |
| 11425 | else if (Is_single_pcx_req_ld(inst)) |
| 11426 | begin |
| 11427 | //is_blkld[thid] = 1'b0; |
| 11428 | if (tmp[`L2_RESP] != 4'hE) |
| 11429 | begin |
| 11430 | DispPendReq(thid); |
| 11431 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 11432 | end |
| 11433 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 11434 | tmp[`L2_RESP] = 4'hF; |
| 11435 | end |
| 11436 | else |
| 11437 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 11438 | end |
| 11439 | else |
| 11440 | begin |
| 11441 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 11442 | end |
| 11443 | |
| 11444 | ld_pend_array[thid] = tmp; |
| 11445 | end |
| 11446 | endtask |
| 11447 | |
| 11448 | task chk_ccx_atm_response; |
| 11449 | input [145:0] cpx_pkt; |
| 11450 | reg [2:0] thid; |
| 11451 | reg [20:0] inst; |
| 11452 | reg [39:0] inst_pa; |
| 11453 | reg [`LD_Pend_Width] tmp; |
| 11454 | begin |
| 11455 | thid = cpx_pkt[`CPX_THR_ID]; |
| 11456 | tmp = ld_pend_array[thid]; |
| 11457 | inst = tmp[`LSU_MON_INST]; |
| 11458 | inst_pa = tmp[`MEMOP_PA]; |
| 11459 | |
| 11460 | if (~ld_valid[thid]) |
| 11461 | begin |
| 11462 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 11463 | begin |
| 11464 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 11465 | end |
| 11466 | else |
| 11467 | begin |
| 11468 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 11469 | end |
| 11470 | end |
| 11471 | else |
| 11472 | begin |
| 11473 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 11474 | begin |
| 11475 | DispPendReq(thid); |
| 11476 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 11477 | begin |
| 11478 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 11479 | end |
| 11480 | else |
| 11481 | begin |
| 11482 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 11483 | end |
| 11484 | end |
| 11485 | else |
| 11486 | begin |
| 11487 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 11488 | begin |
| 11489 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 11490 | end |
| 11491 | else |
| 11492 | begin |
| 11493 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 11494 | end |
| 11495 | |
| 11496 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 11497 | begin |
| 11498 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 11499 | else |
| 11500 | begin |
| 11501 | DispPendReq(thid); |
| 11502 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 11503 | end |
| 11504 | end |
| 11505 | else |
| 11506 | begin |
| 11507 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 11508 | else |
| 11509 | begin |
| 11510 | DispPendReq(thid); |
| 11511 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 11512 | end |
| 11513 | end |
| 11514 | end |
| 11515 | end |
| 11516 | ld_pend_array[thid] = tmp; |
| 11517 | end |
| 11518 | endtask |
| 11519 | |
| 11520 | task chk_ccx_st_response; |
| 11521 | input [145:0] cpx_pkt; |
| 11522 | reg [2:0] thid; |
| 11523 | reg [20:0] inst; |
| 11524 | reg [39:0] cpx_pa, inst_pa; |
| 11525 | reg [204:0] tmp; |
| 11526 | reg [3:0] pkt_type; |
| 11527 | begin |
| 11528 | thid = cpx_pkt[`CPX_THR_ID]; |
| 11529 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 11530 | inst = tmp[`LSU_MON_INST]; |
| 11531 | inst_pa = tmp[`MEMOP_PA]; |
| 11532 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 11533 | |
| 11534 | |
| 11535 | //is received. There could be some other store sitting in the STB at that time. |
| 11536 | |
| 11537 | //Chk for squash bit only for non-bis responses. |
| 11538 | |
| 11539 | |
| 11540 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 11541 | begin |
| 11542 | if (st_rmo_cnt[thid] == 0) |
| 11543 | begin |
| 11544 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 11545 | end |
| 11546 | else |
| 11547 | begin |
| 11548 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 11549 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 11550 | end |
| 11551 | end |
| 11552 | else |
| 11553 | begin |
| 11554 | if (tmp[`ST_SQUASH]) |
| 11555 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 11556 | |
| 11557 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 11558 | begin |
| 11559 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 11560 | end |
| 11561 | else |
| 11562 | begin |
| 11563 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 11564 | begin |
| 11565 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 11566 | end |
| 11567 | tmp[`L2_ACK] = 1'b1; |
| 11568 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 11569 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 11570 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 11571 | end |
| 11572 | end |
| 11573 | end |
| 11574 | endtask |
| 11575 | |
| 11576 | task Chk_req_load; |
| 11577 | input [129:0] pcx_pkt; |
| 11578 | reg [2:0] thid; |
| 11579 | reg [`LD_Pend_Width] tmp; |
| 11580 | reg [39:0] pcx_pa, inst_pa; |
| 11581 | reg [20:0] inst; |
| 11582 | reg [11*8:0] req; |
| 11583 | begin |
| 11584 | |
| 11585 | thid = pcx_pkt[`PCX_THR_ID]; |
| 11586 | tmp = ld_pend_array[thid]; |
| 11587 | inst = tmp[`LSU_MON_INST]; |
| 11588 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 11589 | inst_pa = tmp[`MEMOP_PA]; |
| 11590 | req = DispPCXReq(pcx_pkt); |
| 11591 | |
| 11592 | if (inst[`BLKLD]) |
| 11593 | begin |
| 11594 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 11595 | begin |
| 11596 | DispPendReq(thid); |
| 11597 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 11598 | end |
| 11599 | if (pcx_pa[5:0] == 6'b0) |
| 11600 | begin |
| 11601 | if (tmp[`L2_ISS] != 4'h0 ) |
| 11602 | begin |
| 11603 | DispPendReq(thid); |
| 11604 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 11605 | end |
| 11606 | else |
| 11607 | begin |
| 11608 | tmp[`L2_ISS] = 4'h1; |
| 11609 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11610 | end |
| 11611 | |
| 11612 | end |
| 11613 | if (pcx_pa[5:0] == 6'h10) |
| 11614 | begin |
| 11615 | if (tmp[`L2_ISS] != 4'h1) |
| 11616 | begin |
| 11617 | DispPendReq(thid); |
| 11618 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 11619 | end |
| 11620 | else |
| 11621 | begin |
| 11622 | tmp[`L2_ISS] = 4'h3; |
| 11623 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11624 | end |
| 11625 | end |
| 11626 | if (pcx_pa[5:0] == 6'h20) |
| 11627 | begin |
| 11628 | if (tmp[`L2_ISS] != 4'h3) |
| 11629 | begin |
| 11630 | DispPendReq(thid); |
| 11631 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 11632 | end |
| 11633 | else |
| 11634 | begin |
| 11635 | tmp[`L2_ISS] = 4'h7; |
| 11636 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11637 | end |
| 11638 | end |
| 11639 | if (pcx_pa[5:0] == 6'h30) |
| 11640 | begin |
| 11641 | if (tmp[`L2_ISS] != 4'h7) |
| 11642 | begin |
| 11643 | DispPendReq(thid); |
| 11644 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 11645 | end |
| 11646 | else |
| 11647 | begin |
| 11648 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11649 | tmp[`L2_ISS] = 4'hF; |
| 11650 | end |
| 11651 | end |
| 11652 | ld_pend_array[thid] = tmp; |
| 11653 | end |
| 11654 | else if (Is_single_pcx_req_ld(inst)) |
| 11655 | begin |
| 11656 | if (tmp[`L2_ISS] == 4'hF) |
| 11657 | begin |
| 11658 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 11659 | end |
| 11660 | else |
| 11661 | begin |
| 11662 | tmp[`L2_ISS] = 4'hF; |
| 11663 | ld_pend_array[thid] = tmp; |
| 11664 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 11665 | end |
| 11666 | end |
| 11667 | else |
| 11668 | begin |
| 11669 | DispPendReq(thid); |
| 11670 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 11671 | end |
| 11672 | end |
| 11673 | endtask |
| 11674 | |
| 11675 | |
| 11676 | function Is_single_pcx_req_ld; |
| 11677 | input [20:0] inst; |
| 11678 | begin |
| 11679 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 11680 | Is_single_pcx_req_ld = 1'b1; |
| 11681 | else |
| 11682 | Is_single_pcx_req_ld = 1'b0; |
| 11683 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 11684 | end |
| 11685 | endfunction |
| 11686 | |
| 11687 | |
| 11688 | function Is_trap; |
| 11689 | input [2:0]tid; |
| 11690 | |
| 11691 | begin |
| 11692 | Is_trap = 1'b0; |
| 11693 | case (`SPC5.lsu_trap_flush[7:0]) |
| 11694 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 11695 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 11696 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 11697 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 11698 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 11699 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 11700 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 11701 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 11702 | endcase |
| 11703 | end |
| 11704 | endfunction |
| 11705 | |
| 11706 | function [8*11:0] DispPCXReq; |
| 11707 | input [129:0] pcx_pkt; |
| 11708 | begin |
| 11709 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 11710 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 11711 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 11712 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 11713 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 11714 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 11715 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 11716 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 11717 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 11718 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 11719 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 11720 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 11721 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 11722 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 11723 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 11724 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 11725 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 11726 | default: |
| 11727 | begin |
| 11728 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 11729 | DispPCXReq = " "; |
| 11730 | end |
| 11731 | endcase |
| 11732 | end |
| 11733 | endfunction |
| 11734 | |
| 11735 | function IsExc; |
| 11736 | input [2:0] core_id; |
| 11737 | reg [21*8:0] DispExc; |
| 11738 | |
| 11739 | begin |
| 11740 | DispExc = 170'b0; |
| 11741 | IsExc = 1'b0; |
| 11742 | |
| 11743 | if (`SPC5.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 11744 | if (`SPC5.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 11745 | if (`SPC5.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 11746 | if (`SPC5.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 11747 | if (`SPC5.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 11748 | if (`SPC5.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 11749 | //if (`SPC5.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 11750 | if (`SPC5.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 11751 | if (`SPC5.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 11752 | if (`SPC5.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 11753 | if (`SPC5.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 11754 | if (`SPC5.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 11755 | if (`SPC5.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 11756 | if (`SPC5.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 11757 | //if (`SPC5.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 11758 | if (`SPC5.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 11759 | if (`SPC5.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 11760 | if (`SPC5.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 11761 | |
| 11762 | |
| 11763 | if (DispExc != 0) |
| 11764 | begin |
| 11765 | IsExc = 1'b1; |
| 11766 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 11767 | end |
| 11768 | |
| 11769 | end |
| 11770 | endfunction |
| 11771 | |
| 11772 | function Is_exu_error; |
| 11773 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 11774 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 11775 | reg err_b; |
| 11776 | reg err_m; |
| 11777 | |
| 11778 | begin |
| 11779 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC5.lsu_tlb_bypass_b)): |
| 11780 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC5.lsu_tlb_bypass_b)); |
| 11781 | |
| 11782 | err_m = (dec_lsu_tid_b[2] ? `SPC5.exu_ecc_m[1] : `SPC5.exu_ecc_m[0]) & `SPC5.lsu.dcc.twocycle_b; |
| 11783 | |
| 11784 | Is_exu_error = err_b | err_m; |
| 11785 | end |
| 11786 | endfunction |
| 11787 | |
| 11788 | /* |
| 11789 | task Insert_tlb_miss_info; |
| 11790 | reg [127:0] tmp; |
| 11791 | begin |
| 11792 | tmp = 128'b0; |
| 11793 | if (tlb_valid[dec_lsu_tid_b]) |
| 11794 | begin |
| 11795 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 11796 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 11797 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 11798 | end |
| 11799 | else |
| 11800 | begin |
| 11801 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 11802 | tmp[`INST_VA] = inst_pc_b; |
| 11803 | tmp[`MEMOP_VA] = vaddr_b; |
| 11804 | tmp[`INST] = inst_b; |
| 11805 | end |
| 11806 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 11807 | end |
| 11808 | endtask |
| 11809 | |
| 11810 | */ |
| 11811 | |
| 11812 | //problem with the signal. |
| 11813 | /* |
| 11814 | always @ (negedge `SPC5.l2clk) |
| 11815 | begin |
| 11816 | if (mmu_dtlb_reload_d2) |
| 11817 | Chk_dtlb_reload; |
| 11818 | end |
| 11819 | |
| 11820 | task Chk_dtlb_reload; |
| 11821 | reg [2:0] thid; |
| 11822 | reg [127:0] tmp; |
| 11823 | begin |
| 11824 | if (`SPC5.tlu_trap_pc_0_valid) |
| 11825 | thid = {1'b0, `SPC5.tlu_trap_0_tid}; |
| 11826 | else if (`SPC5.tlu_trap_pc_1_valid) |
| 11827 | thid = {1'b0, `SPC5.tlu_trap_1_tid}; |
| 11828 | else |
| 11829 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 11830 | |
| 11831 | if (~tlb_valid[thid]) |
| 11832 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 11833 | else |
| 11834 | begin |
| 11835 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 11836 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 11837 | tlb_valid[thid] = 1'b0; |
| 11838 | end |
| 11839 | end |
| 11840 | endtask |
| 11841 | */ |
| 11842 | |
| 11843 | task Insert_ld_miss_info; |
| 11844 | reg [`LD_Pend_Width] tmp; |
| 11845 | begin |
| 11846 | tmp = 213'b0; |
| 11847 | if (ld_valid[dec_lsu_tid_b]) |
| 11848 | begin |
| 11849 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 11850 | DispPendReq(dec_lsu_tid_b); |
| 11851 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 11852 | end |
| 11853 | else |
| 11854 | begin |
| 11855 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 11856 | tmp[`INST_VA] = inst_pc_b; |
| 11857 | tmp[`MEMOP_VA] = vaddr_b; |
| 11858 | tmp[`MEMOP_PA] = {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 11859 | tmp[`INST_ASI] = asi_b; |
| 11860 | |
| 11861 | if (lsu_inst_b[`BLKLD]) |
| 11862 | begin |
| 11863 | tmp[`L2_ISS] = 4'h0; |
| 11864 | tmp[`L2_RESP] = 4'h0; |
| 11865 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 11866 | end |
| 11867 | else |
| 11868 | begin |
| 11869 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 11870 | if (lsu_inst_b[`CASA]) |
| 11871 | tmp[`L2_ISS] = 4'hC; |
| 11872 | else |
| 11873 | tmp[`L2_ISS] = 4'hE; |
| 11874 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 11875 | tmp[`L2_RESP] = 4'hC; |
| 11876 | else |
| 11877 | tmp[`L2_RESP] = 4'hE; |
| 11878 | |
| 11879 | end |
| 11880 | |
| 11881 | tmp[`INST] = inst_b; |
| 11882 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 11883 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 11884 | end |
| 11885 | end |
| 11886 | endtask |
| 11887 | |
| 11888 | |
| 11889 | task Insert_in_last_inst_array; |
| 11890 | reg [135:0] tmp; |
| 11891 | begin |
| 11892 | tmp = 128'b0; |
| 11893 | tmp[`INST_VA] = inst_pc_b; |
| 11894 | tmp[`MEMOP_VA] = vaddr_b; |
| 11895 | tmp[`INST] = inst_b; |
| 11896 | tmp[135:128] = asi_b; |
| 11897 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 11898 | end |
| 11899 | endtask |
| 11900 | |
| 11901 | |
| 11902 | task DispPendReq; |
| 11903 | input [2:0] thid; |
| 11904 | reg [`LD_Pend_Width] tmp; |
| 11905 | begin |
| 11906 | |
| 11907 | tmp = ld_pend_array[thid]; |
| 11908 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 11909 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 11910 | end |
| 11911 | endtask |
| 11912 | |
| 11913 | task Disp_STB_entry; |
| 11914 | input [2:0] thid; |
| 11915 | input [2:0] ptr; |
| 11916 | reg [204:0] tmp; |
| 11917 | begin |
| 11918 | |
| 11919 | tmp = stb[{thid, ptr}]; |
| 11920 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 11921 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 11922 | end |
| 11923 | endtask |
| 11924 | |
| 11925 | /* |
| 11926 | |
| 11927 | task Disp_tlbmiss_pend_array_entry; |
| 11928 | input [2:0] thid; |
| 11929 | reg [127:0] tmp; |
| 11930 | begin |
| 11931 | tmp = tlbmiss_pend_array[thid]; |
| 11932 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 11933 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 11934 | |
| 11935 | end |
| 11936 | endtask |
| 11937 | |
| 11938 | */ |
| 11939 | task Disp_CPX_pkt; |
| 11940 | input [145:0] cpx_pkt; |
| 11941 | begin |
| 11942 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 11943 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 11944 | end |
| 11945 | endtask |
| 11946 | |
| 11947 | |
| 11948 | task Make_STB_data; |
| 11949 | reg [204:0] tmp; |
| 11950 | begin |
| 11951 | tmp = 0; |
| 11952 | tmp[`INST_VA] = inst_pc_b; |
| 11953 | tmp[`MEMOP_VA] = vaddr_b; |
| 11954 | tmp[`MEMOP_PA] = {`SPC5.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 11955 | tmp[`L2_ST_ISS] = 1'b0; |
| 11956 | tmp[`ASI_ST_ISS] = 1'b0; |
| 11957 | tmp[`L2_ACK] = 1'b0; |
| 11958 | tmp[`INST] = inst_b; |
| 11959 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 11960 | tmp[`ST_SQUASH] = 1'b0; |
| 11961 | tmp[`INST_ASI] = asi_b; |
| 11962 | if (`SPC5.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 11963 | tmp[`ST_PRIV] = `HPRIV; |
| 11964 | else if (`SPC5.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 11965 | tmp[`ST_PRIV] = `PRIV; |
| 11966 | else |
| 11967 | tmp[`ST_PRIV] = `USER; |
| 11968 | //bis_asi to io space is not rmo |
| 11969 | |
| 11970 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC5.lsu.tlb_pgnum[39]); |
| 11971 | stb_alloc_data <= tmp; |
| 11972 | end |
| 11973 | endtask |
| 11974 | |
| 11975 | task Insert_in_STB; |
| 11976 | input [195:0] store_data; |
| 11977 | input [2:0] thid; |
| 11978 | begin |
| 11979 | if (stb_full(thid)) |
| 11980 | begin |
| 11981 | //DispSTB(thid); |
| 11982 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 11983 | end |
| 11984 | else |
| 11985 | begin |
| 11986 | stb[{thid, wrptr[thid]}] = store_data; |
| 11987 | //Disp_STB_entry(thid, wrptr[thid]); |
| 11988 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 11989 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 11990 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 11991 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 11992 | end |
| 11993 | end |
| 11994 | endtask |
| 11995 | |
| 11996 | function stb_full; |
| 11997 | input [2:0] thid; |
| 11998 | begin |
| 11999 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 12000 | stb_full = 1'b1; |
| 12001 | else |
| 12002 | stb_full = 1'b0; |
| 12003 | end |
| 12004 | endfunction |
| 12005 | |
| 12006 | |
| 12007 | task Dealloc_STB; |
| 12008 | input [2:0] thid; |
| 12009 | reg [204:0] tmp; |
| 12010 | reg [20:0] lsu_inst; |
| 12011 | begin |
| 12012 | //thid = decode_tid(`SPC5.lsu_stb_dealloc); |
| 12013 | tmp = stb[{thid, rdptr[thid]}]; |
| 12014 | lsu_inst = tmp[`LSU_MON_INST]; |
| 12015 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 12016 | begin |
| 12017 | //DispSTB(thid); |
| 12018 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC5.lsu_stb_dealloc); |
| 12019 | end |
| 12020 | if (tmp[`L2_ST_ISS]) |
| 12021 | begin |
| 12022 | if (~tmp[`L2_ACK]) |
| 12023 | begin |
| 12024 | Disp_STB_entry(thid, rdptr[thid]); |
| 12025 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC5.lsu_stb_dealloc); |
| 12026 | end |
| 12027 | end |
| 12028 | else if (tmp[`ASI_ST_ISS]) |
| 12029 | begin |
| 12030 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 12031 | end |
| 12032 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 12033 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 12034 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 12035 | // and deallocated. |
| 12036 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 12037 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 12038 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 12039 | begin |
| 12040 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 12041 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 12042 | end |
| 12043 | else |
| 12044 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC5.lsu_stb_dealloc); |
| 12045 | |
| 12046 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 12047 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 12048 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 12049 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 12050 | /* |
| 12051 | if (tmp[`RMO]) |
| 12052 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 12053 | */ |
| 12054 | end |
| 12055 | endtask |
| 12056 | |
| 12057 | task Squash_STB; |
| 12058 | input [2:0] thid; |
| 12059 | reg [204:0] tmp; |
| 12060 | reg [3:0] squash_cnt; |
| 12061 | reg [2:0] i; |
| 12062 | begin |
| 12063 | squash_cnt = 4'b0; |
| 12064 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 12065 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 12066 | if (rdptr[thid] != iss_ptr[thid]) |
| 12067 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 12068 | |
| 12069 | if (iss_ptr[thid] == wrptr[thid]) |
| 12070 | begin |
| 12071 | if (stb_valid[{thid, wrptr[thid]}]) |
| 12072 | squash_cnt = 8; |
| 12073 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 12074 | * |
| 12075 | else |
| 12076 | begin |
| 12077 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 12078 | end |
| 12079 | */ |
| 12080 | end |
| 12081 | else |
| 12082 | begin |
| 12083 | if (iss_ptr[thid] < wrptr[thid]) |
| 12084 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 12085 | else if (iss_ptr[thid] > wrptr[thid]) |
| 12086 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 12087 | end |
| 12088 | |
| 12089 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 12090 | |
| 12091 | i = iss_ptr[thid]; |
| 12092 | |
| 12093 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 12094 | |
| 12095 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 12096 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 12097 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 12098 | |
| 12099 | while (squash_cnt) |
| 12100 | begin |
| 12101 | tmp = stb[{thid, i}]; |
| 12102 | if (~stb_valid[{thid, i}]) |
| 12103 | begin |
| 12104 | //DispSTB(thid); |
| 12105 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 12106 | end |
| 12107 | if (tmp[`L2_ST_ISS]) |
| 12108 | begin |
| 12109 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 12110 | end |
| 12111 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 12112 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 12113 | //set in the chkr which was causin it to fire. |
| 12114 | //if (~tmp[`ST_SQUASH]) |
| 12115 | //begin |
| 12116 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 12117 | //end |
| 12118 | stb_valid[{thid, i}] = 1'b0; |
| 12119 | |
| 12120 | i = i + 1; |
| 12121 | squash_cnt = squash_cnt - 1'b1; |
| 12122 | end |
| 12123 | |
| 12124 | end |
| 12125 | endtask |
| 12126 | |
| 12127 | task Chk_store; |
| 12128 | reg [2:0] thid; |
| 12129 | reg [47:0] addr; |
| 12130 | reg [3:0] i; |
| 12131 | reg [204:0] tmp; |
| 12132 | begin |
| 12133 | if ((bst_cnt > 0) && (`SPC5.lsu_stb_alloc == 8'b0)) |
| 12134 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 12135 | |
| 12136 | //For bst the stb is still written even though we have errors. |
| 12137 | //Stb is written in W stage. Howvere for first blk store helper |
| 12138 | //the err will be flagged by FGU in b stage. We can miss the |
| 12139 | // err signal if we don't sample in B. |
| 12140 | //for the last helper err will be signalled in B stage of last helper and at |
| 12141 | |
| 12142 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 12143 | bst_fgu_err = 1'b1; |
| 12144 | |
| 12145 | if (`SPC5.lsu_stb_alloc[7:0] != 8'b0) |
| 12146 | begin |
| 12147 | thid = decode_tid(`SPC5.lsu_stb_alloc[7:0]); |
| 12148 | if (store_alloc) |
| 12149 | begin |
| 12150 | if (thid != dec_lsu_tid_w) |
| 12151 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC5.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 12152 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 12153 | end |
| 12154 | else |
| 12155 | begin |
| 12156 | if (lsu_bst_active[thid]) |
| 12157 | begin |
| 12158 | if (bst_cnt == 0) |
| 12159 | begin |
| 12160 | bst_data = bst_inst_data; |
| 12161 | end |
| 12162 | else |
| 12163 | begin |
| 12164 | if (thid != bst_active_thid) |
| 12165 | begin |
| 12166 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC5.lsu_stb_alloc[7:0], bst_active_thid); |
| 12167 | end |
| 12168 | |
| 12169 | addr = bst_data[`MEMOP_VA]; |
| 12170 | |
| 12171 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 12172 | addr = bst_data[`MEMOP_PA]; |
| 12173 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 12174 | end |
| 12175 | bst_cnt = bst_cnt + 1; |
| 12176 | Insert_in_STB(bst_data, bst_active_thid); |
| 12177 | if (bst_cnt == 8) |
| 12178 | begin |
| 12179 | bst_cnt = 0; |
| 12180 | lsu_bst_active[thid] = 1'b0; |
| 12181 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 12182 | begin |
| 12183 | for (i = 0; i < 8; i=i+1) |
| 12184 | begin |
| 12185 | tmp = stb[{thid, i[2:0]}]; |
| 12186 | if (tmp[`ST_SQUASH]) |
| 12187 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 12188 | tmp[`ST_SQUASH] = 1'b1; |
| 12189 | stb[{thid, i[2:0]}] = tmp; |
| 12190 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 12191 | end |
| 12192 | end |
| 12193 | bst_fgu_err = 1'b0; |
| 12194 | end |
| 12195 | end |
| 12196 | else |
| 12197 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC5.lsu_stb_alloc[7:0]); |
| 12198 | |
| 12199 | end |
| 12200 | end |
| 12201 | else |
| 12202 | begin |
| 12203 | if (store_alloc) |
| 12204 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 12205 | end |
| 12206 | end |
| 12207 | endtask |
| 12208 | |
| 12209 | task Chk_st_on_ASI_ring; |
| 12210 | input ring; |
| 12211 | reg [2:0] thid; |
| 12212 | reg [7:0] asi; |
| 12213 | reg [47:0] addr, act_addr; |
| 12214 | reg [1:0] req_type; |
| 12215 | reg [204:0] tmp; |
| 12216 | |
| 12217 | begin |
| 12218 | if (ring == `LOCAL) |
| 12219 | thid =`SPC5.lsu_rngl_cdbus[58:56]; |
| 12220 | else |
| 12221 | thid =`SPC5.lsu_rngf_cdbus[58:56]; |
| 12222 | |
| 12223 | if (ring == `LOCAL) |
| 12224 | asi =`SPC5.lsu_rngl_cdbus[55:48]; |
| 12225 | else |
| 12226 | asi =`SPC5.lsu_rngf_cdbus[55:48]; |
| 12227 | |
| 12228 | if (ring == `LOCAL) |
| 12229 | addr =`SPC5.lsu_rngl_cdbus[47:0]; |
| 12230 | else |
| 12231 | addr =`SPC5.lsu_rngf_cdbus[47:0]; |
| 12232 | |
| 12233 | if (ring == `LOCAL) |
| 12234 | req_type =`SPC5.lsu_rngl_cdbus[61:60]; |
| 12235 | else |
| 12236 | req_type =`SPC5.lsu_rngf_cdbus[61:60]; |
| 12237 | |
| 12238 | |
| 12239 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 12240 | if (tmp[`ASI_ST_ISS]) |
| 12241 | begin |
| 12242 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12243 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 12244 | end |
| 12245 | |
| 12246 | if (tmp[`ST_SQUASH]) |
| 12247 | begin |
| 12248 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12249 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 12250 | end |
| 12251 | |
| 12252 | act_addr = tmp[`MEMOP_PA]; |
| 12253 | act_addr = {act_addr[39:3], 3'b0}; |
| 12254 | |
| 12255 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 12256 | //the address. |
| 12257 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 12258 | begin |
| 12259 | tmp[`ASI_ST_ISS] = 1'b1; |
| 12260 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 12261 | if (ring == `LOCAL) |
| 12262 | begin |
| 12263 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 12264 | end |
| 12265 | else |
| 12266 | begin |
| 12267 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 12268 | end |
| 12269 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 12270 | end |
| 12271 | else |
| 12272 | begin |
| 12273 | if (ring == `LOCAL) |
| 12274 | begin |
| 12275 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 12276 | end |
| 12277 | else |
| 12278 | begin |
| 12279 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 12280 | end |
| 12281 | end |
| 12282 | |
| 12283 | end |
| 12284 | endtask |
| 12285 | |
| 12286 | |
| 12287 | task chk_store_issue_to_pcx; |
| 12288 | input [129:0] pcx_pkt; |
| 12289 | reg [2:0] thid; |
| 12290 | reg [204:0] tmp; |
| 12291 | reg [20:0] inst; |
| 12292 | reg [39:0] pcx_pa, inst_pa; |
| 12293 | begin |
| 12294 | thid = pcx_pkt[`PCX_THR_ID]; |
| 12295 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 12296 | inst = tmp[`LSU_MON_INST]; |
| 12297 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 12298 | inst_pa = tmp[`MEMOP_PA]; |
| 12299 | |
| 12300 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 12301 | begin |
| 12302 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 12303 | end |
| 12304 | if (pcx_pkt[`PCX_INV]) |
| 12305 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 12306 | |
| 12307 | |
| 12308 | if (~inst[`ST]) |
| 12309 | begin |
| 12310 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12311 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12312 | end |
| 12313 | |
| 12314 | /* CONFIRM WITH MARK |
| 12315 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 12316 | begin |
| 12317 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12318 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 12319 | end |
| 12320 | */ |
| 12321 | //enhancement req 100146 |
| 12322 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 12323 | begin |
| 12324 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12325 | end |
| 12326 | |
| 12327 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 12328 | begin |
| 12329 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12330 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12331 | end |
| 12332 | |
| 12333 | if (tmp[`L2_ST_ISS]) |
| 12334 | begin |
| 12335 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12336 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12337 | end |
| 12338 | else |
| 12339 | tmp[`L2_ST_ISS] = 1'b1; |
| 12340 | |
| 12341 | if (tmp[`ST_SQUASH]) |
| 12342 | begin |
| 12343 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12344 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12345 | end |
| 12346 | |
| 12347 | if (tmp[`RMO]) |
| 12348 | begin |
| 12349 | if (~pcx_pkt[`PCX_BIS]) |
| 12350 | begin |
| 12351 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12352 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12353 | end |
| 12354 | if (tmp[`L2_ACK]) |
| 12355 | begin |
| 12356 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 12357 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 12358 | end |
| 12359 | else |
| 12360 | begin |
| 12361 | tmp[`L2_ACK] = 1'b1; |
| 12362 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 12363 | //response seen from stub |
| 12364 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 12365 | end |
| 12366 | end |
| 12367 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 12368 | |
| 12369 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 12370 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 12371 | end |
| 12372 | endtask |
| 12373 | |
| 12374 | `ifdef INJ_STB_ERR_IN_CMP |
| 12375 | |
| 12376 | |
| 12377 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 12378 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 12379 | reg [204:0] err_tmp ; |
| 12380 | reg [20:0] err_inst; |
| 12381 | reg [44:0] cam_data; |
| 12382 | reg [5:0] err_bit; |
| 12383 | integer err_inj_cnt; |
| 12384 | reg cmp_stb_err_inj; |
| 12385 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 12386 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 12387 | |
| 12388 | initial |
| 12389 | begin |
| 12390 | cmp_stb_err_inj = 1'b0; |
| 12391 | |
| 12392 | cam_data = 45'b0; |
| 12393 | err_bit = 11; |
| 12394 | err_inj_cnt = 0; |
| 12395 | stb_err_inj = 0; |
| 12396 | if (("cmp_stb_err_inj_on")) |
| 12397 | cmp_stb_err_inj = 1'b1; |
| 12398 | else |
| 12399 | cmp_stb_err_inj = 1'b0; |
| 12400 | end |
| 12401 | |
| 12402 | always @ (negedge (`SPC5.l2clk & enabled & cmp_stb_err_inj)) |
| 12403 | begin //{ |
| 12404 | //valid stb ram rd for issue to pcx |
| 12405 | stb_err_inj = 1'b0; |
| 12406 | if (`SPC5.lsu.sbc.ram_rptr_vld_2 & `SPC5.lsu.sbc.st_pcx_rq_p3 & `SPC5.lsu.pic.pic_st_sel_p3) |
| 12407 | begin //{ |
| 12408 | err_tid = decode_tid(`SPC5.lsu.sbc.st_rq_sel_p3[7:0]); |
| 12409 | err_index = `SPC5.lsu.sbc.ram_rptr_d1; |
| 12410 | err_tmp = stb[{err_tid, err_index}]; |
| 12411 | err_inst = err_tmp[`LSU_MON_INST]; |
| 12412 | cam_data = `SPC5.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 12413 | err_priv = err_tmp[`ST_PRIV]; |
| 12414 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 12415 | if (err_inst[`CASA]) |
| 12416 | begin //{ |
| 12417 | err_inj_cnt = err_inj_cnt + 1; |
| 12418 | if (err_inj_cnt == 10) |
| 12419 | begin //{ |
| 12420 | case (err_bit) |
| 12421 | 11, 12: err_bit = err_bit + 1; |
| 12422 | 13: err_bit = 44; |
| 12423 | 44: err_bit = 11; |
| 12424 | endcase |
| 12425 | err_inj_cnt = 0; |
| 12426 | stb_err_inj = 1'b1; |
| 12427 | |
| 12428 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 12429 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 12430 | #1; |
| 12431 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 12432 | end //} |
| 12433 | end //} |
| 12434 | end //} |
| 12435 | if (stb_err_inj_d2) |
| 12436 | begin |
| 12437 | if (~`SPC5.lsu_sbapp_err_g) |
| 12438 | begin |
| 12439 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 12440 | end |
| 12441 | else |
| 12442 | begin |
| 12443 | if ((`SPC5.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 12444 | (`SPC5.lsu_stberr_index_g != stb_err_index_d2) || |
| 12445 | (`SPC5.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 12446 | begin |
| 12447 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 12448 | end |
| 12449 | end |
| 12450 | end |
| 12451 | else |
| 12452 | begin |
| 12453 | if (`SPC5.lsu_sbapp_err_g) |
| 12454 | begin |
| 12455 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC5.lsu_stberr_tid_g); |
| 12456 | end |
| 12457 | end |
| 12458 | |
| 12459 | end //} |
| 12460 | |
| 12461 | |
| 12462 | always @ (posedge (`SPC5.l2clk & enabled & cmp_stb_err_inj)) |
| 12463 | begin |
| 12464 | stb_err_inj_d1 <= stb_err_inj; |
| 12465 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 12466 | stb_err_tid_d1 <= err_tid; |
| 12467 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 12468 | stb_err_index_d1 <= err_index; |
| 12469 | stb_err_index_d2 <= stb_err_index_d1; |
| 12470 | stb_err_priv_d1 <= err_priv; |
| 12471 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 12472 | end |
| 12473 | |
| 12474 | `endif |
| 12475 | `endif |
| 12476 | `endif |
| 12477 | endmodule |
| 12478 | |
| 12479 | `endif |
| 12480 | `ifdef CORE_6 |
| 12481 | |
| 12482 | module lsu_mon_c6; |
| 12483 | `ifndef GATESIM |
| 12484 | |
| 12485 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 12486 | `ifndef NO_MONITORS |
| 12487 | |
| 12488 | reg imm_asi_vld_e; |
| 12489 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 12490 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 12491 | reg [1:0] exu_ecc_b; |
| 12492 | reg [1:0] exu_lsu_va_error_b; |
| 12493 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 12494 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 12495 | reg [31:0] inst_e, inst_m, inst_b; |
| 12496 | reg [47:0] vaddr_m, vaddr_b; |
| 12497 | reg [63:0] int_st_data_m, int_st_data_b; |
| 12498 | reg [63:0] fp_st_sata_fx2; |
| 12499 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 12500 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 12501 | |
| 12502 | reg [7:0] ld_valid; |
| 12503 | reg [7:0] tlb_valid; |
| 12504 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 12505 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 12506 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 12507 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 12508 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 12509 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 12510 | //the L2c. |
| 12511 | reg [63:0] stb_valid; |
| 12512 | reg [`STB_Pend_Width] stb[63:0]; |
| 12513 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 12514 | |
| 12515 | reg [7:0] pf_cnt[7:0]; |
| 12516 | reg [7:0] dcache_inv_cnt[7:0]; |
| 12517 | reg [7:0] st_rmo_cnt[7:0]; |
| 12518 | |
| 12519 | reg [55:0] print_inst; |
| 12520 | |
| 12521 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 12522 | |
| 12523 | reg [7:0] lsu_bst_active; |
| 12524 | reg store_alloc; |
| 12525 | reg [3:0] bst_cnt; |
| 12526 | reg [195:0] stb_alloc_data; |
| 12527 | reg [195:0] bst_data, bst_inst_data; |
| 12528 | reg [2:0] bst_active_thid; |
| 12529 | reg bst_fgu_err; |
| 12530 | |
| 12531 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 12532 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 12533 | //different types of err occur on blk ld helper returns |
| 12534 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 12535 | //stored in DFESR |
| 12536 | |
| 12537 | wire [2:0] core_id = 6; |
| 12538 | |
| 12539 | integer i; |
| 12540 | integer err_cnt; |
| 12541 | |
| 12542 | reg enabled; |
| 12543 | reg reset_in_middle; |
| 12544 | reg [7:0] finish_mask; |
| 12545 | |
| 12546 | initial |
| 12547 | begin |
| 12548 | enabled = 0; |
| 12549 | reset_in_middle = 0; |
| 12550 | ld_valid = 8'b0; |
| 12551 | lsu_inst_e = 0; |
| 12552 | tlb_valid = 8'b0; |
| 12553 | for (i = 0; i < 8; i = i+1) |
| 12554 | begin |
| 12555 | pf_cnt[i] = 0; |
| 12556 | dcache_inv_cnt[i] = 0; |
| 12557 | wrptr[i] = 0; |
| 12558 | rdptr[i] = 0; |
| 12559 | iss_ptr[i] = 0; |
| 12560 | ret_ptr[i] = 0; |
| 12561 | st_rmo_cnt[i] = 0; |
| 12562 | is_blkld[i] = 1'b0; |
| 12563 | st_priv[i] = 2'b0; |
| 12564 | l2_blk_ld_errtype[i] = 2'b0; |
| 12565 | end |
| 12566 | lsu_bst_active = 8'b0; |
| 12567 | store_alloc = 1'b0; |
| 12568 | bst_cnt = 4'b0; |
| 12569 | stb_valid = 64'b0; |
| 12570 | |
| 12571 | // avoid time zero ugliness. jp |
| 12572 | //@(posedge `SPC0.l2clk); |
| 12573 | //@(negedge `SPC0.l2clk); |
| 12574 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 12575 | |
| 12576 | case (core_id) |
| 12577 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 12578 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 12579 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 12580 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 12581 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 12582 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 12583 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 12584 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 12585 | endcase |
| 12586 | end |
| 12587 | |
| 12588 | always @ (`TOP.in_reset) |
| 12589 | begin |
| 12590 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 12591 | begin |
| 12592 | enabled = 1'b1; |
| 12593 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 12594 | end |
| 12595 | |
| 12596 | |
| 12597 | if (`TOP.in_reset & enabled) |
| 12598 | begin |
| 12599 | reset_in_middle = 1'b1; |
| 12600 | enabled = 1'b0; |
| 12601 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 12602 | end |
| 12603 | end |
| 12604 | |
| 12605 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 12606 | begin //{ |
| 12607 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 12608 | begin //{ |
| 12609 | for (i = 0; i < 8; i=i+1) |
| 12610 | begin |
| 12611 | if (ld_valid[i]) |
| 12612 | begin |
| 12613 | DispPendReq(i); |
| 12614 | end |
| 12615 | end |
| 12616 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 12617 | end //} |
| 12618 | if (|stb_valid[63:0]) |
| 12619 | begin //{ |
| 12620 | err_cnt = 0; |
| 12621 | for (i = 0; i < 64; i=i+1) |
| 12622 | begin |
| 12623 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 12624 | begin |
| 12625 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 12626 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 12627 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 12628 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 12629 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 12630 | //of simualation. |
| 12631 | if (~is_squash_bit_set(i[5:0])) |
| 12632 | begin |
| 12633 | err_cnt = err_cnt + 1; |
| 12634 | Disp_STB_entry(i[5:3],i[2:0]); |
| 12635 | end |
| 12636 | end |
| 12637 | end |
| 12638 | if (err_cnt) |
| 12639 | begin |
| 12640 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 12641 | end |
| 12642 | end //} |
| 12643 | err_cnt = 0; |
| 12644 | for (i = 0; i < 8; i=i+1) |
| 12645 | begin //{ |
| 12646 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 12647 | begin |
| 12648 | err_cnt = 1; |
| 12649 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 12650 | end |
| 12651 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 12652 | begin |
| 12653 | err_cnt = 1; |
| 12654 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 12655 | end |
| 12656 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 12657 | begin |
| 12658 | err_cnt = 1; |
| 12659 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 12660 | end |
| 12661 | end //} |
| 12662 | if (err_cnt) |
| 12663 | begin |
| 12664 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 12665 | end |
| 12666 | end //} |
| 12667 | |
| 12668 | function is_squash_bit_set; |
| 12669 | input [5:0] index; |
| 12670 | reg [204:0] tmp; |
| 12671 | begin |
| 12672 | tmp = stb[index]; |
| 12673 | if (tmp[`ST_SQUASH]) |
| 12674 | is_squash_bit_set = 1'b1; |
| 12675 | else |
| 12676 | is_squash_bit_set = 1'b0; |
| 12677 | end |
| 12678 | endfunction |
| 12679 | |
| 12680 | |
| 12681 | always @ (negedge (`SPC6.l2clk & enabled)) |
| 12682 | begin //{ |
| 12683 | |
| 12684 | asi_e = `SPC6.lsu.dcc.dcc_asi_e[7:0]; |
| 12685 | |
| 12686 | lsu_inst_e[`LD] <= `SPC6.dec_ld_inst_e; |
| 12687 | lsu_inst_e[`ST] <= `SPC6.dec_st_inst_e; |
| 12688 | lsu_inst_e[`FP] <= `SPC6.dec_fpldst_inst_e; |
| 12689 | lsu_inst_e[`PREF] <= `SPC6.dec_pref_inst_e; |
| 12690 | lsu_inst_e[`SWAP] <= `SPC6.dec_swap_inst_e; |
| 12691 | lsu_inst_e[`CASA] <= `SPC6.dec_casa_inst_e; |
| 12692 | lsu_inst_e[`LDSTUB] <= `SPC6.dec_ldstub_inst_e; |
| 12693 | lsu_inst_e[`FLUSH] <= `SPC6.dec_flush_inst_e; |
| 12694 | lsu_inst_e[`MEMBAR] <= `SPC6.dec_memstbar_inst_e; |
| 12695 | lsu_inst_e[`LDD] <= `SPC6.dec_ld_inst_e & `SPC6.dec_ldst_dbl_e & ~`SPC6.dec_fpldst_inst_e; |
| 12696 | lsu_inst_e[`STD] <= `SPC6.dec_st_inst_e & `SPC6.dec_ldst_dbl_e & ~`SPC6.lsu.dec_fpldst_inst_e; |
| 12697 | |
| 12698 | lsu_inst_e[`BLKLD] <= `SPC6.dec_ld_inst_e & `SPC6.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 12699 | lsu_inst_e[`BLKST] <= `SPC6.dec_st_inst_e & `SPC6.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 12700 | lsu_inst_e[`QLD] <= `SPC6.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 12701 | lsu_inst_e[`ASR_RD_WR] <= `SPC6.dec_sr_inst_e & (`SPC6.dec_ld_inst_e | `SPC6.dec_st_inst_e); |
| 12702 | lsu_inst_e[`PR_RD_WR] <= `SPC6.dec_pr_inst_e & (`SPC6.dec_ld_inst_e | `SPC6.dec_st_inst_e); |
| 12703 | lsu_inst_e[`HPR_RD_WR] <= `SPC6.dec_hpr_inst_e & (`SPC6.dec_ld_inst_e | `SPC6.dec_st_inst_e); |
| 12704 | lsu_inst_e[`FSR_RD_WR] <= `SPC6.dec_fsr_ldst_e & (`SPC6.dec_ld_inst_e | `SPC6.dec_st_inst_e); |
| 12705 | end //} |
| 12706 | |
| 12707 | always @ (posedge (`SPC6.l2clk & enabled)) |
| 12708 | begin //{ |
| 12709 | dec_tg0_inst_d <= `SPC6.dec.ded0.decode_mux[31:0]; |
| 12710 | dec_tg1_inst_d <= `SPC6.dec.ded1.decode_mux[31:0]; |
| 12711 | imm_asi_vld_e <= `SPC6.lsu.dec_imm_asi_vld_d; |
| 12712 | |
| 12713 | imm_asi_e <= `SPC6.lsu.dec_imm_asi_d; |
| 12714 | dec_altspace_e <= `SPC6.dec_altspace_d; |
| 12715 | dec_altspace_m <= dec_altspace_e; |
| 12716 | dec_altspace_b <= dec_altspace_m; |
| 12717 | |
| 12718 | exu_ecc_b <= `SPC6.exu_ecc_m; |
| 12719 | exu_lsu_va_error_b <= `SPC6.exu_lsu_va_error_m; |
| 12720 | |
| 12721 | dec_lsu_tid_e <= `SPC6.dec_lsu_tg_d ? {1'b1, `SPC6.dec_lsu_tid1_d} : {1'b0, `SPC6.dec_lsu_tid0_d}; |
| 12722 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 12723 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 12724 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 12725 | |
| 12726 | inst_pc_e <= `SPC6.dec_lsu_tg_d ? {`SPC6.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC6.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 12727 | inst_pc_m <= inst_pc_e; |
| 12728 | inst_pc_b <= inst_pc_m; |
| 12729 | inst_pc_w <= inst_pc_b; |
| 12730 | |
| 12731 | inst_e <= `SPC6.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 12732 | inst_m <= inst_e; |
| 12733 | inst_b <= inst_m; |
| 12734 | |
| 12735 | vaddr_m <= `SPC6.exu_lsu_address_e; |
| 12736 | vaddr_b <= vaddr_m; |
| 12737 | |
| 12738 | int_st_data_m <= `SPC6.exu_lsu_store_data_e; |
| 12739 | int_st_data_b <= int_st_data_m; |
| 12740 | fp_st_sata_fx2 <= `SPC6.fgu_lsu_fst_data_fx1; |
| 12741 | |
| 12742 | mmu_dtlb_reload_d1 <= `SPC6.mmu_dtlb_reload; |
| 12743 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 12744 | |
| 12745 | //pcx_thid_d1 <= `SPC6.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 12746 | lsu_inst_m <= lsu_inst_e; |
| 12747 | lsu_inst_b <= lsu_inst_m; |
| 12748 | |
| 12749 | asi_m <= asi_e; |
| 12750 | asi_b <= asi_m; |
| 12751 | end //} |
| 12752 | |
| 12753 | function Is_blk_asi; |
| 12754 | input [7:0] asi; |
| 12755 | begin |
| 12756 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 12757 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 12758 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 12759 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 12760 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 12761 | end |
| 12762 | endfunction |
| 12763 | |
| 12764 | function Is_qld_asi; |
| 12765 | input [7:0] asi; |
| 12766 | begin |
| 12767 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 12768 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 12769 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 12770 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 12771 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 12772 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 12773 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 12774 | end |
| 12775 | endfunction |
| 12776 | |
| 12777 | function Is_bis_asi; |
| 12778 | input [7:0] asi; |
| 12779 | begin |
| 12780 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 12781 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 12782 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 12783 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 12784 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 12785 | end |
| 12786 | endfunction |
| 12787 | |
| 12788 | always @ (negedge (`SPC6.l2clk & enabled)) |
| 12789 | begin //{ |
| 12790 | Chk_store; |
| 12791 | store_alloc = 1'b0; |
| 12792 | if (lsu_inst_m != 0) |
| 12793 | begin |
| 12794 | if (`SPC6.dec_flush_lm) |
| 12795 | begin |
| 12796 | lsu_inst_m <= 0; |
| 12797 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 12798 | end |
| 12799 | end |
| 12800 | |
| 12801 | if (lsu_inst_b != 0) |
| 12802 | begin //{ |
| 12803 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 12804 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 12805 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 12806 | else print_inst = ""; |
| 12807 | |
| 12808 | if (`SPC6.dec_flush_lb) |
| 12809 | begin |
| 12810 | lsu_inst_b <= 0; |
| 12811 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 12812 | end |
| 12813 | else if (`SPC6.tlu_flush_lsu_b) |
| 12814 | begin |
| 12815 | lsu_inst_b <= 0; |
| 12816 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 12817 | end |
| 12818 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 12819 | //casa shd be killed. |
| 12820 | //This function will also chk for errors on 2nd cycle. |
| 12821 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 12822 | begin |
| 12823 | lsu_inst_b <= 0; |
| 12824 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 12825 | end |
| 12826 | else if ((`SPC6.fgu_cecc_fx2 || `SPC6.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 12827 | begin |
| 12828 | lsu_inst_b <= 0; |
| 12829 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 12830 | end |
| 12831 | else if (IsExc(core_id)) |
| 12832 | lsu_inst_b <= 0; |
| 12833 | else if (!`SPC6.lsu_tlb_miss_b_) |
| 12834 | begin |
| 12835 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 12836 | //Insert_tlb_miss_info; |
| 12837 | end |
| 12838 | else |
| 12839 | begin //{ |
| 12840 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 12841 | //an exception tlu anyway tells the front end to flush itself there is |
| 12842 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 12843 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 12844 | //handles it when it is reissued by the front end. |
| 12845 | |
| 12846 | if (`SPC6.lsu_tlb_bypass_b) |
| 12847 | begin |
| 12848 | if (`SPC6.lsu_sync != 8'b0) |
| 12849 | begin |
| 12850 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 12851 | end |
| 12852 | else |
| 12853 | begin |
| 12854 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 12855 | end |
| 12856 | end |
| 12857 | else |
| 12858 | begin |
| 12859 | if (`SPC6.lsu_sync != 8'b0) |
| 12860 | begin |
| 12861 | if (lsu_inst_b[`ST]) |
| 12862 | begin |
| 12863 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 12864 | end |
| 12865 | else |
| 12866 | begin |
| 12867 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 12868 | end |
| 12869 | end |
| 12870 | else |
| 12871 | begin |
| 12872 | if (lsu_inst_b[`ST]) |
| 12873 | begin |
| 12874 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 12875 | end |
| 12876 | else |
| 12877 | begin |
| 12878 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 12879 | end |
| 12880 | end |
| 12881 | end |
| 12882 | |
| 12883 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 12884 | begin //{ |
| 12885 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC6.lsu.stb_cam_hit) |
| 12886 | begin |
| 12887 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 12888 | end |
| 12889 | end //} |
| 12890 | |
| 12891 | if (lsu_inst_b[`LD]) |
| 12892 | Insert_ld_miss_info; |
| 12893 | |
| 12894 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 12895 | begin |
| 12896 | Make_STB_data; |
| 12897 | store_alloc = 1'b1; |
| 12898 | end |
| 12899 | Insert_in_last_inst_array; |
| 12900 | |
| 12901 | if (`SPC6.lsu_trap_flush[7:0]) |
| 12902 | begin |
| 12903 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC6.lsu_trap_flush[7:0])); |
| 12904 | end |
| 12905 | end //} |
| 12906 | end //} |
| 12907 | end //} |
| 12908 | |
| 12909 | //STB ue testing: |
| 12910 | //This is how we test squashing of stores by LSU_mon: |
| 12911 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 12912 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 12913 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 12914 | //The squashed stores are deallocated when either a block_store_kill is |
| 12915 | //asserted or dealloc signals are asserted by the LSU. |
| 12916 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 12917 | //all the pending stores in the IFU. It means the when block_store_kill |
| 12918 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 12919 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 12920 | //the sbdiou signal to TLU. |
| 12921 | |
| 12922 | |
| 12923 | always @ (negedge (`SPC6.l2clk & enabled)) |
| 12924 | begin |
| 12925 | if (`SPC6.lsu_l15_valid & `SPC6.lsu.spc_pcx_data_pa[129]) |
| 12926 | Chk_pcx_req_pkt(`SPC6.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 12927 | if ((`SPC6.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC6.lsu_rngl_cdbus[59]) |
| 12928 | Chk_st_on_ASI_ring(`LOCAL); |
| 12929 | |
| 12930 | if ((`SPC6.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC6.lsu_rngf_cdbus[59]) |
| 12931 | Chk_st_on_ASI_ring(`FAST); |
| 12932 | |
| 12933 | //if (`SPC6.l15_lsu_valid) |
| 12934 | //Chk_cpx_response_pkt({`SPC6.l15_lsu_valid, `SPC6.l15_lsu_cpkt[17:13],`SPC6.l15_lsu_cpkt[11:0],`SPC6.l15_spc_data1[127:0]}); |
| 12935 | |
| 12936 | if (`SPC6.cpx_spc_data_cx[145]) |
| 12937 | Chk_cpx_response_pkt(`SPC6.cpx_spc_data_cx); |
| 12938 | |
| 12939 | if (`SPC6.lsu_complete[7:0] != 8'b0) |
| 12940 | begin |
| 12941 | if (`SPC6.lsu_complete[0]) Chk_ld_complete(0); |
| 12942 | if (`SPC6.lsu_complete[1]) Chk_ld_complete(1); |
| 12943 | if (`SPC6.lsu_complete[2]) Chk_ld_complete(2); |
| 12944 | if (`SPC6.lsu_complete[3]) Chk_ld_complete(3); |
| 12945 | if (`SPC6.lsu_complete[4]) Chk_ld_complete(4); |
| 12946 | if (`SPC6.lsu_complete[5]) Chk_ld_complete(5); |
| 12947 | if (`SPC6.lsu_complete[6]) Chk_ld_complete(6); |
| 12948 | if (`SPC6.lsu_complete[7]) Chk_ld_complete(7); |
| 12949 | end |
| 12950 | |
| 12951 | if (`SPC6.lsu_block_store_kill[7:0] != 8'b0) |
| 12952 | begin |
| 12953 | if (`SPC6.lsu_block_store_kill[0]) Squash_STB(0); |
| 12954 | if (`SPC6.lsu_block_store_kill[1]) Squash_STB(1); |
| 12955 | if (`SPC6.lsu_block_store_kill[2]) Squash_STB(2); |
| 12956 | if (`SPC6.lsu_block_store_kill[3]) Squash_STB(3); |
| 12957 | if (`SPC6.lsu_block_store_kill[4]) Squash_STB(4); |
| 12958 | if (`SPC6.lsu_block_store_kill[5]) Squash_STB(5); |
| 12959 | if (`SPC6.lsu_block_store_kill[6]) Squash_STB(6); |
| 12960 | if (`SPC6.lsu_block_store_kill[7]) Squash_STB(7); |
| 12961 | end |
| 12962 | |
| 12963 | if (`SPC6.lsu_stb_dealloc[7:0] != 8'b0) |
| 12964 | begin |
| 12965 | if (`SPC6.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 12966 | if (`SPC6.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 12967 | if (`SPC6.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 12968 | if (`SPC6.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 12969 | if (`SPC6.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 12970 | if (`SPC6.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 12971 | if (`SPC6.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 12972 | if (`SPC6.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 12973 | end |
| 12974 | |
| 12975 | if (`SPC6.lsu_block_store_stall) |
| 12976 | Chk_block_store; |
| 12977 | |
| 12978 | if (`SPC6.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 12979 | Set_block_store_parameters; |
| 12980 | |
| 12981 | if (`SPC6.lsu_sbdiou_err_g || `SPC6.lsu_sbapp_err_g) |
| 12982 | Squash_store; |
| 12983 | |
| 12984 | if (`SPC6.lsu_stb_flush_g) |
| 12985 | st_priv[`SPC6.lsu_stberr_tid_g] = get_priv_on_flush(`SPC6.lsu_stberr_tid_g); |
| 12986 | end |
| 12987 | |
| 12988 | function [1:0] get_priv_on_flush; |
| 12989 | input [2:0] tid; |
| 12990 | reg [2:0] sq_index; |
| 12991 | reg [204:0] tmp; |
| 12992 | |
| 12993 | begin |
| 12994 | sq_index = `SPC6.lsu_stberr_index_g; |
| 12995 | tmp = stb[{tid, sq_index}]; |
| 12996 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 12997 | end |
| 12998 | endfunction |
| 12999 | |
| 13000 | task Chk_block_store; |
| 13001 | reg [20:0] inst; |
| 13002 | reg [2:0] thid; |
| 13003 | begin |
| 13004 | thid = `SPC6.lsu_block_store_tid; |
| 13005 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 13006 | inst = bst_inst_data[`LSU_MON_INST]; |
| 13007 | |
| 13008 | if (~inst[`BLKST]) |
| 13009 | begin |
| 13010 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 13011 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 13012 | end |
| 13013 | end |
| 13014 | endtask |
| 13015 | |
| 13016 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 13017 | //the 8 stb entries from the previous blk store. |
| 13018 | |
| 13019 | task Set_block_store_parameters; |
| 13020 | reg [2:0] thid; |
| 13021 | begin |
| 13022 | |
| 13023 | thid = decode_tid(`SPC6.lsu.lsu_block_store_alloc[7:0]); |
| 13024 | if (lsu_bst_active[thid]) |
| 13025 | begin |
| 13026 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 13027 | end |
| 13028 | else |
| 13029 | begin |
| 13030 | lsu_bst_active[thid] = 1'b1; |
| 13031 | bst_active_thid = thid; |
| 13032 | if (`SPC6.lsu.fgu_fst_ecc_error_fx2) |
| 13033 | bst_fgu_err = 1'b1; |
| 13034 | else |
| 13035 | bst_fgu_err = 1'b0; |
| 13036 | end |
| 13037 | end |
| 13038 | endtask |
| 13039 | |
| 13040 | task Squash_store; |
| 13041 | reg [2:0] thid; |
| 13042 | reg [2:0] sq_index; |
| 13043 | reg [2:0] i; |
| 13044 | reg [204:0] tmp; |
| 13045 | reg [3:0] squash_cnt; |
| 13046 | reg [1:0] priv; |
| 13047 | |
| 13048 | begin |
| 13049 | thid = `SPC6.lsu_stberr_tid_g; |
| 13050 | sq_index = `SPC6.lsu_stberr_index_g; |
| 13051 | priv = `SPC6.lsu_stberr_priv_g; |
| 13052 | tmp = stb[{thid, sq_index}]; |
| 13053 | squash_cnt = 0; |
| 13054 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 13055 | |
| 13056 | st_priv[thid] = tmp[`ST_PRIV]; |
| 13057 | |
| 13058 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 13059 | //In that case iss_ptr won't be equal to sbdiou index. |
| 13060 | //if (sq_index != iss_ptr[thid]) |
| 13061 | //begin |
| 13062 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 13063 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 13064 | //end |
| 13065 | |
| 13066 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 13067 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 13068 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 13069 | //removing this chk. |
| 13070 | |
| 13071 | //if (tmp[`L2_ST_ISS]) |
| 13072 | //begin |
| 13073 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 13074 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 13075 | //end |
| 13076 | |
| 13077 | if (iss_ptr[thid] == wrptr[thid]) |
| 13078 | begin |
| 13079 | if (stb_valid[{thid, wrptr[thid]}]) |
| 13080 | squash_cnt = 8; |
| 13081 | else |
| 13082 | begin |
| 13083 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 13084 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 13085 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 13086 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 13087 | end |
| 13088 | end |
| 13089 | else |
| 13090 | begin |
| 13091 | if (iss_ptr[thid] < wrptr[thid]) |
| 13092 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 13093 | else if (iss_ptr[thid] > wrptr[thid]) |
| 13094 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 13095 | end |
| 13096 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 13097 | |
| 13098 | i = iss_ptr[thid]; |
| 13099 | |
| 13100 | while (squash_cnt) |
| 13101 | begin |
| 13102 | tmp = stb[{thid, i}]; |
| 13103 | tmp[`ST_SQUASH] = 1'b1; |
| 13104 | if (priv < tmp[`ST_PRIV]) |
| 13105 | begin |
| 13106 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 13107 | priv = tmp[`ST_PRIV]; |
| 13108 | end |
| 13109 | |
| 13110 | stb[{thid, i}] = tmp; |
| 13111 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 13112 | |
| 13113 | i = i + 1; |
| 13114 | squash_cnt = squash_cnt - 1'b1; |
| 13115 | end |
| 13116 | end |
| 13117 | endtask |
| 13118 | |
| 13119 | function [2:0] decode_tid; |
| 13120 | input [7:0] thid_encode; |
| 13121 | begin |
| 13122 | case (thid_encode) |
| 13123 | 8'h1: decode_tid = 3'b0; |
| 13124 | 8'h2: decode_tid = 3'h1; |
| 13125 | 8'h4: decode_tid = 3'h2; |
| 13126 | 8'h8: decode_tid = 3'h3; |
| 13127 | 8'h10: decode_tid = 3'h4; |
| 13128 | 8'h20: decode_tid = 3'h5; |
| 13129 | 8'h40: decode_tid = 3'h6; |
| 13130 | 8'h80: decode_tid = 3'h7; |
| 13131 | default: |
| 13132 | begin |
| 13133 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 13134 | end |
| 13135 | endcase |
| 13136 | end |
| 13137 | endfunction |
| 13138 | |
| 13139 | task Chk_ld_complete; |
| 13140 | input [2:0] thid; |
| 13141 | reg [`LD_Pend_Width] tmp; |
| 13142 | begin |
| 13143 | tmp = ld_pend_array[thid]; |
| 13144 | |
| 13145 | if (ld_valid[thid]) |
| 13146 | begin |
| 13147 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 13148 | begin |
| 13149 | DispPendReq(thid); |
| 13150 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 13151 | end |
| 13152 | ld_valid[thid] = 1'b0; |
| 13153 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 13154 | end |
| 13155 | |
| 13156 | tmp = last_inst_array[thid]; |
| 13157 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 13158 | end |
| 13159 | endtask |
| 13160 | |
| 13161 | task Chk_pcx_req_pkt; |
| 13162 | input [129:0] pcx_pkt; |
| 13163 | reg [2:0] thid; |
| 13164 | reg [`LD_Pend_Width] tmp, tmp1; |
| 13165 | reg [15:0] inst; |
| 13166 | reg [11*8:0] req; |
| 13167 | reg [39:0] addr; |
| 13168 | begin |
| 13169 | thid = pcx_pkt[`PCX_THR_ID]; |
| 13170 | tmp = ld_pend_array[thid]; |
| 13171 | inst = tmp[`LSU_MON_INST]; |
| 13172 | req = DispPCXReq(pcx_pkt); |
| 13173 | addr = pcx_pkt[`PCX_ADDR]; |
| 13174 | |
| 13175 | |
| 13176 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 13177 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 13178 | |
| 13179 | |
| 13180 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 13181 | begin |
| 13182 | if (~ld_valid[thid]) |
| 13183 | begin |
| 13184 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 13185 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 13186 | end |
| 13187 | if (~inst[`BLKLD]) |
| 13188 | begin |
| 13189 | if (tmp[`MEMOP_PA] != addr) |
| 13190 | begin |
| 13191 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 13192 | begin |
| 13193 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 13194 | end |
| 13195 | else |
| 13196 | begin |
| 13197 | DispPendReq(thid); |
| 13198 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 13199 | end |
| 13200 | end |
| 13201 | end |
| 13202 | end |
| 13203 | |
| 13204 | case (pcx_pkt[`PCX_RQTYP]) |
| 13205 | `PCX_LOAD: |
| 13206 | begin |
| 13207 | if (pcx_pkt[`PCX_PF]) |
| 13208 | begin |
| 13209 | if (~inst[`PREF]) |
| 13210 | begin |
| 13211 | DispPendReq(thid); |
| 13212 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 13213 | end |
| 13214 | if (pcx_pkt[`PCX_INV]) |
| 13215 | begin |
| 13216 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 13217 | end |
| 13218 | else |
| 13219 | begin |
| 13220 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 13221 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 13222 | end |
| 13223 | tmp[`L2_ISS] = 4'hF; |
| 13224 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 13225 | ld_pend_array[thid] = tmp; |
| 13226 | end |
| 13227 | else |
| 13228 | begin |
| 13229 | if (pcx_pkt[`PCX_INV]) |
| 13230 | begin |
| 13231 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13232 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 13233 | end |
| 13234 | else |
| 13235 | begin |
| 13236 | Chk_req_load(pcx_pkt); |
| 13237 | end |
| 13238 | end |
| 13239 | end |
| 13240 | `PCX_CAS1, `PCX_CAS2: |
| 13241 | begin |
| 13242 | if (~inst[`CASA]) |
| 13243 | begin |
| 13244 | DispPendReq(thid); |
| 13245 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 13246 | end |
| 13247 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 13248 | begin |
| 13249 | tmp[`L2_ISS] = 4'hE; |
| 13250 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13251 | ld_pend_array[thid] = tmp; |
| 13252 | end |
| 13253 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 13254 | begin |
| 13255 | tmp[`L2_ISS] = 4'hF; |
| 13256 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13257 | ld_pend_array[thid] = tmp; |
| 13258 | chk_store_issue_to_pcx(pcx_pkt); |
| 13259 | end |
| 13260 | |
| 13261 | end |
| 13262 | `PCX_SWAP_LDSTUB: |
| 13263 | begin |
| 13264 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 13265 | begin |
| 13266 | DispPendReq(thid); |
| 13267 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 13268 | end |
| 13269 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 13270 | tmp[`L2_ISS] = 4'hF; |
| 13271 | ld_pend_array[thid] = tmp; |
| 13272 | |
| 13273 | chk_store_issue_to_pcx(pcx_pkt); |
| 13274 | end |
| 13275 | |
| 13276 | `PCX_STORE: |
| 13277 | begin |
| 13278 | chk_store_issue_to_pcx(pcx_pkt); |
| 13279 | end |
| 13280 | |
| 13281 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 13282 | endcase |
| 13283 | end |
| 13284 | endtask |
| 13285 | |
| 13286 | task Chk_cpx_response_pkt; |
| 13287 | input [145:0] cpx_pkt; |
| 13288 | reg [2:0] thid; |
| 13289 | begin |
| 13290 | thid = cpx_pkt[`CPX_THR_ID]; |
| 13291 | |
| 13292 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 13293 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 13294 | begin |
| 13295 | chk_ccx_ld_response(cpx_pkt); |
| 13296 | end |
| 13297 | |
| 13298 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 13299 | begin |
| 13300 | if (pf_cnt[thid] == 8'b0) |
| 13301 | begin |
| 13302 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 13303 | end |
| 13304 | else |
| 13305 | begin |
| 13306 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 13307 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 13308 | end |
| 13309 | end |
| 13310 | |
| 13311 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 13312 | chk_ccx_ld_response(cpx_pkt); |
| 13313 | |
| 13314 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 13315 | begin |
| 13316 | if (cpx_pkt[123]) //D pkt |
| 13317 | begin //{ |
| 13318 | if (cpx_pkt[120:118] != core_id) |
| 13319 | begin |
| 13320 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 13321 | end |
| 13322 | if (dcache_inv_cnt[thid] == 8'b0) |
| 13323 | begin |
| 13324 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 13325 | end |
| 13326 | else |
| 13327 | begin |
| 13328 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 13329 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 13330 | end |
| 13331 | end //} |
| 13332 | else if (cpx_pkt[124]) //I pkt |
| 13333 | begin |
| 13334 | if (cpx_pkt[120:118] != core_id) |
| 13335 | begin |
| 13336 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 13337 | end |
| 13338 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 13339 | end |
| 13340 | else if (cpx_pkt[124:123] == 2'b0) |
| 13341 | begin |
| 13342 | if (cpx_pkt[120:118] == core_id) |
| 13343 | begin |
| 13344 | chk_ccx_st_response(cpx_pkt); |
| 13345 | end |
| 13346 | else |
| 13347 | begin |
| 13348 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 13349 | end |
| 13350 | end |
| 13351 | end |
| 13352 | |
| 13353 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 13354 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 13355 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 13356 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 13357 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 13358 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 13359 | |
| 13360 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 13361 | begin |
| 13362 | chk_ccx_atm_response(cpx_pkt); |
| 13363 | end |
| 13364 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 13365 | begin |
| 13366 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 13367 | begin |
| 13368 | chk_ccx_atm_response(cpx_pkt); |
| 13369 | chk_ccx_st_response(cpx_pkt); |
| 13370 | end |
| 13371 | end |
| 13372 | |
| 13373 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 13374 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 13375 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 13376 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 13377 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 13378 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 13379 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 13380 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 13381 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 13382 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 13383 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 13384 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 13385 | |
| 13386 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 13387 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 13388 | |
| 13389 | default: |
| 13390 | begin |
| 13391 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 13392 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 13393 | |
| 13394 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 13395 | end |
| 13396 | |
| 13397 | endcase |
| 13398 | end |
| 13399 | endtask |
| 13400 | |
| 13401 | task chk_ccx_ld_response; |
| 13402 | input [145:0] cpx_pkt; |
| 13403 | reg [2:0] thid; |
| 13404 | reg [20:0] inst; |
| 13405 | reg [39:0] cpx_pa, inst_pa; |
| 13406 | reg [`LD_Pend_Width] tmp; |
| 13407 | reg [3:0] pkt_type; |
| 13408 | begin |
| 13409 | thid = cpx_pkt[`CPX_THR_ID]; |
| 13410 | tmp = ld_pend_array[thid]; |
| 13411 | inst = tmp[`LSU_MON_INST]; |
| 13412 | inst_pa = tmp[`MEMOP_PA]; |
| 13413 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 13414 | |
| 13415 | if (ld_valid[thid]) |
| 13416 | begin |
| 13417 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 13418 | /* |
| 13419 | if (inst_pa[39] != pkt_type[3]) |
| 13420 | begin |
| 13421 | DispPendReq(thid); |
| 13422 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 13423 | end |
| 13424 | */ |
| 13425 | |
| 13426 | if (inst[`BLKLD]) |
| 13427 | begin |
| 13428 | if (tmp[`L2_RESP] == 4'h0) |
| 13429 | begin |
| 13430 | tmp[`L2_RESP] = 4'h1; |
| 13431 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 13432 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 13433 | begin |
| 13434 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 13435 | end |
| 13436 | |
| 13437 | end |
| 13438 | else if (tmp[`L2_RESP] == 4'h1) |
| 13439 | begin |
| 13440 | tmp[`L2_RESP] = 4'h3; |
| 13441 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 13442 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 13443 | begin |
| 13444 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 13445 | end |
| 13446 | end |
| 13447 | else if (tmp[`L2_RESP] == 4'h3) |
| 13448 | begin |
| 13449 | tmp[`L2_RESP] = 4'h7; |
| 13450 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 13451 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 13452 | begin |
| 13453 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 13454 | end |
| 13455 | end |
| 13456 | else if (tmp[`L2_RESP] == 4'h7) |
| 13457 | begin |
| 13458 | tmp[`L2_RESP] = 4'hF; |
| 13459 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 13460 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 13461 | begin |
| 13462 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 13463 | end |
| 13464 | |
| 13465 | //is_blkld[thid] = 1'b1; |
| 13466 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 13467 | l2_blk_ld_errtype[thid] = `ND; |
| 13468 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 13469 | l2_blk_ld_errtype[thid] = `UE; |
| 13470 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 13471 | l2_blk_ld_errtype[thid] = `CE; |
| 13472 | else |
| 13473 | l2_blk_ld_errtype[thid] = `NE; |
| 13474 | end |
| 13475 | else |
| 13476 | begin |
| 13477 | DispPendReq(thid); |
| 13478 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 13479 | end |
| 13480 | end |
| 13481 | else if (Is_single_pcx_req_ld(inst)) |
| 13482 | begin |
| 13483 | //is_blkld[thid] = 1'b0; |
| 13484 | if (tmp[`L2_RESP] != 4'hE) |
| 13485 | begin |
| 13486 | DispPendReq(thid); |
| 13487 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 13488 | end |
| 13489 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 13490 | tmp[`L2_RESP] = 4'hF; |
| 13491 | end |
| 13492 | else |
| 13493 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 13494 | end |
| 13495 | else |
| 13496 | begin |
| 13497 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 13498 | end |
| 13499 | |
| 13500 | ld_pend_array[thid] = tmp; |
| 13501 | end |
| 13502 | endtask |
| 13503 | |
| 13504 | task chk_ccx_atm_response; |
| 13505 | input [145:0] cpx_pkt; |
| 13506 | reg [2:0] thid; |
| 13507 | reg [20:0] inst; |
| 13508 | reg [39:0] inst_pa; |
| 13509 | reg [`LD_Pend_Width] tmp; |
| 13510 | begin |
| 13511 | thid = cpx_pkt[`CPX_THR_ID]; |
| 13512 | tmp = ld_pend_array[thid]; |
| 13513 | inst = tmp[`LSU_MON_INST]; |
| 13514 | inst_pa = tmp[`MEMOP_PA]; |
| 13515 | |
| 13516 | if (~ld_valid[thid]) |
| 13517 | begin |
| 13518 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 13519 | begin |
| 13520 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 13521 | end |
| 13522 | else |
| 13523 | begin |
| 13524 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 13525 | end |
| 13526 | end |
| 13527 | else |
| 13528 | begin |
| 13529 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 13530 | begin |
| 13531 | DispPendReq(thid); |
| 13532 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 13533 | begin |
| 13534 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 13535 | end |
| 13536 | else |
| 13537 | begin |
| 13538 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 13539 | end |
| 13540 | end |
| 13541 | else |
| 13542 | begin |
| 13543 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 13544 | begin |
| 13545 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 13546 | end |
| 13547 | else |
| 13548 | begin |
| 13549 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 13550 | end |
| 13551 | |
| 13552 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 13553 | begin |
| 13554 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 13555 | else |
| 13556 | begin |
| 13557 | DispPendReq(thid); |
| 13558 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 13559 | end |
| 13560 | end |
| 13561 | else |
| 13562 | begin |
| 13563 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 13564 | else |
| 13565 | begin |
| 13566 | DispPendReq(thid); |
| 13567 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 13568 | end |
| 13569 | end |
| 13570 | end |
| 13571 | end |
| 13572 | ld_pend_array[thid] = tmp; |
| 13573 | end |
| 13574 | endtask |
| 13575 | |
| 13576 | task chk_ccx_st_response; |
| 13577 | input [145:0] cpx_pkt; |
| 13578 | reg [2:0] thid; |
| 13579 | reg [20:0] inst; |
| 13580 | reg [39:0] cpx_pa, inst_pa; |
| 13581 | reg [204:0] tmp; |
| 13582 | reg [3:0] pkt_type; |
| 13583 | begin |
| 13584 | thid = cpx_pkt[`CPX_THR_ID]; |
| 13585 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 13586 | inst = tmp[`LSU_MON_INST]; |
| 13587 | inst_pa = tmp[`MEMOP_PA]; |
| 13588 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 13589 | |
| 13590 | |
| 13591 | //is received. There could be some other store sitting in the STB at that time. |
| 13592 | |
| 13593 | //Chk for squash bit only for non-bis responses. |
| 13594 | |
| 13595 | |
| 13596 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 13597 | begin |
| 13598 | if (st_rmo_cnt[thid] == 0) |
| 13599 | begin |
| 13600 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 13601 | end |
| 13602 | else |
| 13603 | begin |
| 13604 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 13605 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 13606 | end |
| 13607 | end |
| 13608 | else |
| 13609 | begin |
| 13610 | if (tmp[`ST_SQUASH]) |
| 13611 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 13612 | |
| 13613 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 13614 | begin |
| 13615 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 13616 | end |
| 13617 | else |
| 13618 | begin |
| 13619 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 13620 | begin |
| 13621 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 13622 | end |
| 13623 | tmp[`L2_ACK] = 1'b1; |
| 13624 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 13625 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 13626 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 13627 | end |
| 13628 | end |
| 13629 | end |
| 13630 | endtask |
| 13631 | |
| 13632 | task Chk_req_load; |
| 13633 | input [129:0] pcx_pkt; |
| 13634 | reg [2:0] thid; |
| 13635 | reg [`LD_Pend_Width] tmp; |
| 13636 | reg [39:0] pcx_pa, inst_pa; |
| 13637 | reg [20:0] inst; |
| 13638 | reg [11*8:0] req; |
| 13639 | begin |
| 13640 | |
| 13641 | thid = pcx_pkt[`PCX_THR_ID]; |
| 13642 | tmp = ld_pend_array[thid]; |
| 13643 | inst = tmp[`LSU_MON_INST]; |
| 13644 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 13645 | inst_pa = tmp[`MEMOP_PA]; |
| 13646 | req = DispPCXReq(pcx_pkt); |
| 13647 | |
| 13648 | if (inst[`BLKLD]) |
| 13649 | begin |
| 13650 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 13651 | begin |
| 13652 | DispPendReq(thid); |
| 13653 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 13654 | end |
| 13655 | if (pcx_pa[5:0] == 6'b0) |
| 13656 | begin |
| 13657 | if (tmp[`L2_ISS] != 4'h0 ) |
| 13658 | begin |
| 13659 | DispPendReq(thid); |
| 13660 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 13661 | end |
| 13662 | else |
| 13663 | begin |
| 13664 | tmp[`L2_ISS] = 4'h1; |
| 13665 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13666 | end |
| 13667 | |
| 13668 | end |
| 13669 | if (pcx_pa[5:0] == 6'h10) |
| 13670 | begin |
| 13671 | if (tmp[`L2_ISS] != 4'h1) |
| 13672 | begin |
| 13673 | DispPendReq(thid); |
| 13674 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 13675 | end |
| 13676 | else |
| 13677 | begin |
| 13678 | tmp[`L2_ISS] = 4'h3; |
| 13679 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13680 | end |
| 13681 | end |
| 13682 | if (pcx_pa[5:0] == 6'h20) |
| 13683 | begin |
| 13684 | if (tmp[`L2_ISS] != 4'h3) |
| 13685 | begin |
| 13686 | DispPendReq(thid); |
| 13687 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 13688 | end |
| 13689 | else |
| 13690 | begin |
| 13691 | tmp[`L2_ISS] = 4'h7; |
| 13692 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13693 | end |
| 13694 | end |
| 13695 | if (pcx_pa[5:0] == 6'h30) |
| 13696 | begin |
| 13697 | if (tmp[`L2_ISS] != 4'h7) |
| 13698 | begin |
| 13699 | DispPendReq(thid); |
| 13700 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 13701 | end |
| 13702 | else |
| 13703 | begin |
| 13704 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13705 | tmp[`L2_ISS] = 4'hF; |
| 13706 | end |
| 13707 | end |
| 13708 | ld_pend_array[thid] = tmp; |
| 13709 | end |
| 13710 | else if (Is_single_pcx_req_ld(inst)) |
| 13711 | begin |
| 13712 | if (tmp[`L2_ISS] == 4'hF) |
| 13713 | begin |
| 13714 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 13715 | end |
| 13716 | else |
| 13717 | begin |
| 13718 | tmp[`L2_ISS] = 4'hF; |
| 13719 | ld_pend_array[thid] = tmp; |
| 13720 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 13721 | end |
| 13722 | end |
| 13723 | else |
| 13724 | begin |
| 13725 | DispPendReq(thid); |
| 13726 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 13727 | end |
| 13728 | end |
| 13729 | endtask |
| 13730 | |
| 13731 | |
| 13732 | function Is_single_pcx_req_ld; |
| 13733 | input [20:0] inst; |
| 13734 | begin |
| 13735 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 13736 | Is_single_pcx_req_ld = 1'b1; |
| 13737 | else |
| 13738 | Is_single_pcx_req_ld = 1'b0; |
| 13739 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 13740 | end |
| 13741 | endfunction |
| 13742 | |
| 13743 | |
| 13744 | function Is_trap; |
| 13745 | input [2:0]tid; |
| 13746 | |
| 13747 | begin |
| 13748 | Is_trap = 1'b0; |
| 13749 | case (`SPC6.lsu_trap_flush[7:0]) |
| 13750 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 13751 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 13752 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 13753 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 13754 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 13755 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 13756 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 13757 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 13758 | endcase |
| 13759 | end |
| 13760 | endfunction |
| 13761 | |
| 13762 | function [8*11:0] DispPCXReq; |
| 13763 | input [129:0] pcx_pkt; |
| 13764 | begin |
| 13765 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 13766 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 13767 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 13768 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 13769 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 13770 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 13771 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 13772 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 13773 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 13774 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 13775 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 13776 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 13777 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 13778 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 13779 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 13780 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 13781 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 13782 | default: |
| 13783 | begin |
| 13784 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 13785 | DispPCXReq = " "; |
| 13786 | end |
| 13787 | endcase |
| 13788 | end |
| 13789 | endfunction |
| 13790 | |
| 13791 | function IsExc; |
| 13792 | input [2:0] core_id; |
| 13793 | reg [21*8:0] DispExc; |
| 13794 | |
| 13795 | begin |
| 13796 | DispExc = 170'b0; |
| 13797 | IsExc = 1'b0; |
| 13798 | |
| 13799 | if (`SPC6.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 13800 | if (`SPC6.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 13801 | if (`SPC6.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 13802 | if (`SPC6.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 13803 | if (`SPC6.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 13804 | if (`SPC6.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 13805 | //if (`SPC6.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 13806 | if (`SPC6.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 13807 | if (`SPC6.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 13808 | if (`SPC6.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 13809 | if (`SPC6.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 13810 | if (`SPC6.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 13811 | if (`SPC6.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 13812 | if (`SPC6.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 13813 | //if (`SPC6.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 13814 | if (`SPC6.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 13815 | if (`SPC6.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 13816 | if (`SPC6.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 13817 | |
| 13818 | |
| 13819 | if (DispExc != 0) |
| 13820 | begin |
| 13821 | IsExc = 1'b1; |
| 13822 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 13823 | end |
| 13824 | |
| 13825 | end |
| 13826 | endfunction |
| 13827 | |
| 13828 | function Is_exu_error; |
| 13829 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 13830 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 13831 | reg err_b; |
| 13832 | reg err_m; |
| 13833 | |
| 13834 | begin |
| 13835 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC6.lsu_tlb_bypass_b)): |
| 13836 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC6.lsu_tlb_bypass_b)); |
| 13837 | |
| 13838 | err_m = (dec_lsu_tid_b[2] ? `SPC6.exu_ecc_m[1] : `SPC6.exu_ecc_m[0]) & `SPC6.lsu.dcc.twocycle_b; |
| 13839 | |
| 13840 | Is_exu_error = err_b | err_m; |
| 13841 | end |
| 13842 | endfunction |
| 13843 | |
| 13844 | /* |
| 13845 | task Insert_tlb_miss_info; |
| 13846 | reg [127:0] tmp; |
| 13847 | begin |
| 13848 | tmp = 128'b0; |
| 13849 | if (tlb_valid[dec_lsu_tid_b]) |
| 13850 | begin |
| 13851 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 13852 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 13853 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 13854 | end |
| 13855 | else |
| 13856 | begin |
| 13857 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 13858 | tmp[`INST_VA] = inst_pc_b; |
| 13859 | tmp[`MEMOP_VA] = vaddr_b; |
| 13860 | tmp[`INST] = inst_b; |
| 13861 | end |
| 13862 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 13863 | end |
| 13864 | endtask |
| 13865 | |
| 13866 | */ |
| 13867 | |
| 13868 | //problem with the signal. |
| 13869 | /* |
| 13870 | always @ (negedge `SPC6.l2clk) |
| 13871 | begin |
| 13872 | if (mmu_dtlb_reload_d2) |
| 13873 | Chk_dtlb_reload; |
| 13874 | end |
| 13875 | |
| 13876 | task Chk_dtlb_reload; |
| 13877 | reg [2:0] thid; |
| 13878 | reg [127:0] tmp; |
| 13879 | begin |
| 13880 | if (`SPC6.tlu_trap_pc_0_valid) |
| 13881 | thid = {1'b0, `SPC6.tlu_trap_0_tid}; |
| 13882 | else if (`SPC6.tlu_trap_pc_1_valid) |
| 13883 | thid = {1'b0, `SPC6.tlu_trap_1_tid}; |
| 13884 | else |
| 13885 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 13886 | |
| 13887 | if (~tlb_valid[thid]) |
| 13888 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 13889 | else |
| 13890 | begin |
| 13891 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 13892 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 13893 | tlb_valid[thid] = 1'b0; |
| 13894 | end |
| 13895 | end |
| 13896 | endtask |
| 13897 | */ |
| 13898 | |
| 13899 | task Insert_ld_miss_info; |
| 13900 | reg [`LD_Pend_Width] tmp; |
| 13901 | begin |
| 13902 | tmp = 213'b0; |
| 13903 | if (ld_valid[dec_lsu_tid_b]) |
| 13904 | begin |
| 13905 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 13906 | DispPendReq(dec_lsu_tid_b); |
| 13907 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 13908 | end |
| 13909 | else |
| 13910 | begin |
| 13911 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 13912 | tmp[`INST_VA] = inst_pc_b; |
| 13913 | tmp[`MEMOP_VA] = vaddr_b; |
| 13914 | tmp[`MEMOP_PA] = {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 13915 | tmp[`INST_ASI] = asi_b; |
| 13916 | |
| 13917 | if (lsu_inst_b[`BLKLD]) |
| 13918 | begin |
| 13919 | tmp[`L2_ISS] = 4'h0; |
| 13920 | tmp[`L2_RESP] = 4'h0; |
| 13921 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 13922 | end |
| 13923 | else |
| 13924 | begin |
| 13925 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 13926 | if (lsu_inst_b[`CASA]) |
| 13927 | tmp[`L2_ISS] = 4'hC; |
| 13928 | else |
| 13929 | tmp[`L2_ISS] = 4'hE; |
| 13930 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 13931 | tmp[`L2_RESP] = 4'hC; |
| 13932 | else |
| 13933 | tmp[`L2_RESP] = 4'hE; |
| 13934 | |
| 13935 | end |
| 13936 | |
| 13937 | tmp[`INST] = inst_b; |
| 13938 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 13939 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 13940 | end |
| 13941 | end |
| 13942 | endtask |
| 13943 | |
| 13944 | |
| 13945 | task Insert_in_last_inst_array; |
| 13946 | reg [135:0] tmp; |
| 13947 | begin |
| 13948 | tmp = 128'b0; |
| 13949 | tmp[`INST_VA] = inst_pc_b; |
| 13950 | tmp[`MEMOP_VA] = vaddr_b; |
| 13951 | tmp[`INST] = inst_b; |
| 13952 | tmp[135:128] = asi_b; |
| 13953 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 13954 | end |
| 13955 | endtask |
| 13956 | |
| 13957 | |
| 13958 | task DispPendReq; |
| 13959 | input [2:0] thid; |
| 13960 | reg [`LD_Pend_Width] tmp; |
| 13961 | begin |
| 13962 | |
| 13963 | tmp = ld_pend_array[thid]; |
| 13964 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 13965 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 13966 | end |
| 13967 | endtask |
| 13968 | |
| 13969 | task Disp_STB_entry; |
| 13970 | input [2:0] thid; |
| 13971 | input [2:0] ptr; |
| 13972 | reg [204:0] tmp; |
| 13973 | begin |
| 13974 | |
| 13975 | tmp = stb[{thid, ptr}]; |
| 13976 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 13977 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 13978 | end |
| 13979 | endtask |
| 13980 | |
| 13981 | /* |
| 13982 | |
| 13983 | task Disp_tlbmiss_pend_array_entry; |
| 13984 | input [2:0] thid; |
| 13985 | reg [127:0] tmp; |
| 13986 | begin |
| 13987 | tmp = tlbmiss_pend_array[thid]; |
| 13988 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 13989 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 13990 | |
| 13991 | end |
| 13992 | endtask |
| 13993 | |
| 13994 | */ |
| 13995 | task Disp_CPX_pkt; |
| 13996 | input [145:0] cpx_pkt; |
| 13997 | begin |
| 13998 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 13999 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 14000 | end |
| 14001 | endtask |
| 14002 | |
| 14003 | |
| 14004 | task Make_STB_data; |
| 14005 | reg [204:0] tmp; |
| 14006 | begin |
| 14007 | tmp = 0; |
| 14008 | tmp[`INST_VA] = inst_pc_b; |
| 14009 | tmp[`MEMOP_VA] = vaddr_b; |
| 14010 | tmp[`MEMOP_PA] = {`SPC6.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 14011 | tmp[`L2_ST_ISS] = 1'b0; |
| 14012 | tmp[`ASI_ST_ISS] = 1'b0; |
| 14013 | tmp[`L2_ACK] = 1'b0; |
| 14014 | tmp[`INST] = inst_b; |
| 14015 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 14016 | tmp[`ST_SQUASH] = 1'b0; |
| 14017 | tmp[`INST_ASI] = asi_b; |
| 14018 | if (`SPC6.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 14019 | tmp[`ST_PRIV] = `HPRIV; |
| 14020 | else if (`SPC6.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 14021 | tmp[`ST_PRIV] = `PRIV; |
| 14022 | else |
| 14023 | tmp[`ST_PRIV] = `USER; |
| 14024 | //bis_asi to io space is not rmo |
| 14025 | |
| 14026 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC6.lsu.tlb_pgnum[39]); |
| 14027 | stb_alloc_data <= tmp; |
| 14028 | end |
| 14029 | endtask |
| 14030 | |
| 14031 | task Insert_in_STB; |
| 14032 | input [195:0] store_data; |
| 14033 | input [2:0] thid; |
| 14034 | begin |
| 14035 | if (stb_full(thid)) |
| 14036 | begin |
| 14037 | //DispSTB(thid); |
| 14038 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 14039 | end |
| 14040 | else |
| 14041 | begin |
| 14042 | stb[{thid, wrptr[thid]}] = store_data; |
| 14043 | //Disp_STB_entry(thid, wrptr[thid]); |
| 14044 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 14045 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 14046 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 14047 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 14048 | end |
| 14049 | end |
| 14050 | endtask |
| 14051 | |
| 14052 | function stb_full; |
| 14053 | input [2:0] thid; |
| 14054 | begin |
| 14055 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 14056 | stb_full = 1'b1; |
| 14057 | else |
| 14058 | stb_full = 1'b0; |
| 14059 | end |
| 14060 | endfunction |
| 14061 | |
| 14062 | |
| 14063 | task Dealloc_STB; |
| 14064 | input [2:0] thid; |
| 14065 | reg [204:0] tmp; |
| 14066 | reg [20:0] lsu_inst; |
| 14067 | begin |
| 14068 | //thid = decode_tid(`SPC6.lsu_stb_dealloc); |
| 14069 | tmp = stb[{thid, rdptr[thid]}]; |
| 14070 | lsu_inst = tmp[`LSU_MON_INST]; |
| 14071 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 14072 | begin |
| 14073 | //DispSTB(thid); |
| 14074 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC6.lsu_stb_dealloc); |
| 14075 | end |
| 14076 | if (tmp[`L2_ST_ISS]) |
| 14077 | begin |
| 14078 | if (~tmp[`L2_ACK]) |
| 14079 | begin |
| 14080 | Disp_STB_entry(thid, rdptr[thid]); |
| 14081 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC6.lsu_stb_dealloc); |
| 14082 | end |
| 14083 | end |
| 14084 | else if (tmp[`ASI_ST_ISS]) |
| 14085 | begin |
| 14086 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 14087 | end |
| 14088 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 14089 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 14090 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 14091 | // and deallocated. |
| 14092 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 14093 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 14094 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 14095 | begin |
| 14096 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 14097 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 14098 | end |
| 14099 | else |
| 14100 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC6.lsu_stb_dealloc); |
| 14101 | |
| 14102 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 14103 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 14104 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 14105 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 14106 | /* |
| 14107 | if (tmp[`RMO]) |
| 14108 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 14109 | */ |
| 14110 | end |
| 14111 | endtask |
| 14112 | |
| 14113 | task Squash_STB; |
| 14114 | input [2:0] thid; |
| 14115 | reg [204:0] tmp; |
| 14116 | reg [3:0] squash_cnt; |
| 14117 | reg [2:0] i; |
| 14118 | begin |
| 14119 | squash_cnt = 4'b0; |
| 14120 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 14121 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 14122 | if (rdptr[thid] != iss_ptr[thid]) |
| 14123 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 14124 | |
| 14125 | if (iss_ptr[thid] == wrptr[thid]) |
| 14126 | begin |
| 14127 | if (stb_valid[{thid, wrptr[thid]}]) |
| 14128 | squash_cnt = 8; |
| 14129 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 14130 | * |
| 14131 | else |
| 14132 | begin |
| 14133 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 14134 | end |
| 14135 | */ |
| 14136 | end |
| 14137 | else |
| 14138 | begin |
| 14139 | if (iss_ptr[thid] < wrptr[thid]) |
| 14140 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 14141 | else if (iss_ptr[thid] > wrptr[thid]) |
| 14142 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 14143 | end |
| 14144 | |
| 14145 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 14146 | |
| 14147 | i = iss_ptr[thid]; |
| 14148 | |
| 14149 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 14150 | |
| 14151 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 14152 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 14153 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 14154 | |
| 14155 | while (squash_cnt) |
| 14156 | begin |
| 14157 | tmp = stb[{thid, i}]; |
| 14158 | if (~stb_valid[{thid, i}]) |
| 14159 | begin |
| 14160 | //DispSTB(thid); |
| 14161 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 14162 | end |
| 14163 | if (tmp[`L2_ST_ISS]) |
| 14164 | begin |
| 14165 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 14166 | end |
| 14167 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 14168 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 14169 | //set in the chkr which was causin it to fire. |
| 14170 | //if (~tmp[`ST_SQUASH]) |
| 14171 | //begin |
| 14172 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 14173 | //end |
| 14174 | stb_valid[{thid, i}] = 1'b0; |
| 14175 | |
| 14176 | i = i + 1; |
| 14177 | squash_cnt = squash_cnt - 1'b1; |
| 14178 | end |
| 14179 | |
| 14180 | end |
| 14181 | endtask |
| 14182 | |
| 14183 | task Chk_store; |
| 14184 | reg [2:0] thid; |
| 14185 | reg [47:0] addr; |
| 14186 | reg [3:0] i; |
| 14187 | reg [204:0] tmp; |
| 14188 | begin |
| 14189 | if ((bst_cnt > 0) && (`SPC6.lsu_stb_alloc == 8'b0)) |
| 14190 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 14191 | |
| 14192 | //For bst the stb is still written even though we have errors. |
| 14193 | //Stb is written in W stage. Howvere for first blk store helper |
| 14194 | //the err will be flagged by FGU in b stage. We can miss the |
| 14195 | // err signal if we don't sample in B. |
| 14196 | //for the last helper err will be signalled in B stage of last helper and at |
| 14197 | |
| 14198 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 14199 | bst_fgu_err = 1'b1; |
| 14200 | |
| 14201 | if (`SPC6.lsu_stb_alloc[7:0] != 8'b0) |
| 14202 | begin |
| 14203 | thid = decode_tid(`SPC6.lsu_stb_alloc[7:0]); |
| 14204 | if (store_alloc) |
| 14205 | begin |
| 14206 | if (thid != dec_lsu_tid_w) |
| 14207 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC6.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 14208 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 14209 | end |
| 14210 | else |
| 14211 | begin |
| 14212 | if (lsu_bst_active[thid]) |
| 14213 | begin |
| 14214 | if (bst_cnt == 0) |
| 14215 | begin |
| 14216 | bst_data = bst_inst_data; |
| 14217 | end |
| 14218 | else |
| 14219 | begin |
| 14220 | if (thid != bst_active_thid) |
| 14221 | begin |
| 14222 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC6.lsu_stb_alloc[7:0], bst_active_thid); |
| 14223 | end |
| 14224 | |
| 14225 | addr = bst_data[`MEMOP_VA]; |
| 14226 | |
| 14227 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 14228 | addr = bst_data[`MEMOP_PA]; |
| 14229 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 14230 | end |
| 14231 | bst_cnt = bst_cnt + 1; |
| 14232 | Insert_in_STB(bst_data, bst_active_thid); |
| 14233 | if (bst_cnt == 8) |
| 14234 | begin |
| 14235 | bst_cnt = 0; |
| 14236 | lsu_bst_active[thid] = 1'b0; |
| 14237 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 14238 | begin |
| 14239 | for (i = 0; i < 8; i=i+1) |
| 14240 | begin |
| 14241 | tmp = stb[{thid, i[2:0]}]; |
| 14242 | if (tmp[`ST_SQUASH]) |
| 14243 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 14244 | tmp[`ST_SQUASH] = 1'b1; |
| 14245 | stb[{thid, i[2:0]}] = tmp; |
| 14246 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 14247 | end |
| 14248 | end |
| 14249 | bst_fgu_err = 1'b0; |
| 14250 | end |
| 14251 | end |
| 14252 | else |
| 14253 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC6.lsu_stb_alloc[7:0]); |
| 14254 | |
| 14255 | end |
| 14256 | end |
| 14257 | else |
| 14258 | begin |
| 14259 | if (store_alloc) |
| 14260 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 14261 | end |
| 14262 | end |
| 14263 | endtask |
| 14264 | |
| 14265 | task Chk_st_on_ASI_ring; |
| 14266 | input ring; |
| 14267 | reg [2:0] thid; |
| 14268 | reg [7:0] asi; |
| 14269 | reg [47:0] addr, act_addr; |
| 14270 | reg [1:0] req_type; |
| 14271 | reg [204:0] tmp; |
| 14272 | |
| 14273 | begin |
| 14274 | if (ring == `LOCAL) |
| 14275 | thid =`SPC6.lsu_rngl_cdbus[58:56]; |
| 14276 | else |
| 14277 | thid =`SPC6.lsu_rngf_cdbus[58:56]; |
| 14278 | |
| 14279 | if (ring == `LOCAL) |
| 14280 | asi =`SPC6.lsu_rngl_cdbus[55:48]; |
| 14281 | else |
| 14282 | asi =`SPC6.lsu_rngf_cdbus[55:48]; |
| 14283 | |
| 14284 | if (ring == `LOCAL) |
| 14285 | addr =`SPC6.lsu_rngl_cdbus[47:0]; |
| 14286 | else |
| 14287 | addr =`SPC6.lsu_rngf_cdbus[47:0]; |
| 14288 | |
| 14289 | if (ring == `LOCAL) |
| 14290 | req_type =`SPC6.lsu_rngl_cdbus[61:60]; |
| 14291 | else |
| 14292 | req_type =`SPC6.lsu_rngf_cdbus[61:60]; |
| 14293 | |
| 14294 | |
| 14295 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 14296 | if (tmp[`ASI_ST_ISS]) |
| 14297 | begin |
| 14298 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14299 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 14300 | end |
| 14301 | |
| 14302 | if (tmp[`ST_SQUASH]) |
| 14303 | begin |
| 14304 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14305 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 14306 | end |
| 14307 | |
| 14308 | act_addr = tmp[`MEMOP_PA]; |
| 14309 | act_addr = {act_addr[39:3], 3'b0}; |
| 14310 | |
| 14311 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 14312 | //the address. |
| 14313 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 14314 | begin |
| 14315 | tmp[`ASI_ST_ISS] = 1'b1; |
| 14316 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 14317 | if (ring == `LOCAL) |
| 14318 | begin |
| 14319 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 14320 | end |
| 14321 | else |
| 14322 | begin |
| 14323 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 14324 | end |
| 14325 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 14326 | end |
| 14327 | else |
| 14328 | begin |
| 14329 | if (ring == `LOCAL) |
| 14330 | begin |
| 14331 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 14332 | end |
| 14333 | else |
| 14334 | begin |
| 14335 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 14336 | end |
| 14337 | end |
| 14338 | |
| 14339 | end |
| 14340 | endtask |
| 14341 | |
| 14342 | |
| 14343 | task chk_store_issue_to_pcx; |
| 14344 | input [129:0] pcx_pkt; |
| 14345 | reg [2:0] thid; |
| 14346 | reg [204:0] tmp; |
| 14347 | reg [20:0] inst; |
| 14348 | reg [39:0] pcx_pa, inst_pa; |
| 14349 | begin |
| 14350 | thid = pcx_pkt[`PCX_THR_ID]; |
| 14351 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 14352 | inst = tmp[`LSU_MON_INST]; |
| 14353 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 14354 | inst_pa = tmp[`MEMOP_PA]; |
| 14355 | |
| 14356 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 14357 | begin |
| 14358 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 14359 | end |
| 14360 | if (pcx_pkt[`PCX_INV]) |
| 14361 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 14362 | |
| 14363 | |
| 14364 | if (~inst[`ST]) |
| 14365 | begin |
| 14366 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14367 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14368 | end |
| 14369 | |
| 14370 | /* CONFIRM WITH MARK |
| 14371 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 14372 | begin |
| 14373 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14374 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 14375 | end |
| 14376 | */ |
| 14377 | //enhancement req 100146 |
| 14378 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 14379 | begin |
| 14380 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14381 | end |
| 14382 | |
| 14383 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 14384 | begin |
| 14385 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14386 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14387 | end |
| 14388 | |
| 14389 | if (tmp[`L2_ST_ISS]) |
| 14390 | begin |
| 14391 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14392 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14393 | end |
| 14394 | else |
| 14395 | tmp[`L2_ST_ISS] = 1'b1; |
| 14396 | |
| 14397 | if (tmp[`ST_SQUASH]) |
| 14398 | begin |
| 14399 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14400 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14401 | end |
| 14402 | |
| 14403 | if (tmp[`RMO]) |
| 14404 | begin |
| 14405 | if (~pcx_pkt[`PCX_BIS]) |
| 14406 | begin |
| 14407 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14408 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14409 | end |
| 14410 | if (tmp[`L2_ACK]) |
| 14411 | begin |
| 14412 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 14413 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 14414 | end |
| 14415 | else |
| 14416 | begin |
| 14417 | tmp[`L2_ACK] = 1'b1; |
| 14418 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 14419 | //response seen from stub |
| 14420 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 14421 | end |
| 14422 | end |
| 14423 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 14424 | |
| 14425 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 14426 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 14427 | end |
| 14428 | endtask |
| 14429 | |
| 14430 | `ifdef INJ_STB_ERR_IN_CMP |
| 14431 | |
| 14432 | |
| 14433 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 14434 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 14435 | reg [204:0] err_tmp ; |
| 14436 | reg [20:0] err_inst; |
| 14437 | reg [44:0] cam_data; |
| 14438 | reg [5:0] err_bit; |
| 14439 | integer err_inj_cnt; |
| 14440 | reg cmp_stb_err_inj; |
| 14441 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 14442 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 14443 | |
| 14444 | initial |
| 14445 | begin |
| 14446 | cmp_stb_err_inj = 1'b0; |
| 14447 | |
| 14448 | cam_data = 45'b0; |
| 14449 | err_bit = 11; |
| 14450 | err_inj_cnt = 0; |
| 14451 | stb_err_inj = 0; |
| 14452 | if (("cmp_stb_err_inj_on")) |
| 14453 | cmp_stb_err_inj = 1'b1; |
| 14454 | else |
| 14455 | cmp_stb_err_inj = 1'b0; |
| 14456 | end |
| 14457 | |
| 14458 | always @ (negedge (`SPC6.l2clk & enabled & cmp_stb_err_inj)) |
| 14459 | begin //{ |
| 14460 | //valid stb ram rd for issue to pcx |
| 14461 | stb_err_inj = 1'b0; |
| 14462 | if (`SPC6.lsu.sbc.ram_rptr_vld_2 & `SPC6.lsu.sbc.st_pcx_rq_p3 & `SPC6.lsu.pic.pic_st_sel_p3) |
| 14463 | begin //{ |
| 14464 | err_tid = decode_tid(`SPC6.lsu.sbc.st_rq_sel_p3[7:0]); |
| 14465 | err_index = `SPC6.lsu.sbc.ram_rptr_d1; |
| 14466 | err_tmp = stb[{err_tid, err_index}]; |
| 14467 | err_inst = err_tmp[`LSU_MON_INST]; |
| 14468 | cam_data = `SPC6.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 14469 | err_priv = err_tmp[`ST_PRIV]; |
| 14470 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 14471 | if (err_inst[`CASA]) |
| 14472 | begin //{ |
| 14473 | err_inj_cnt = err_inj_cnt + 1; |
| 14474 | if (err_inj_cnt == 10) |
| 14475 | begin //{ |
| 14476 | case (err_bit) |
| 14477 | 11, 12: err_bit = err_bit + 1; |
| 14478 | 13: err_bit = 44; |
| 14479 | 44: err_bit = 11; |
| 14480 | endcase |
| 14481 | err_inj_cnt = 0; |
| 14482 | stb_err_inj = 1'b1; |
| 14483 | |
| 14484 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 14485 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 14486 | #1; |
| 14487 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 14488 | end //} |
| 14489 | end //} |
| 14490 | end //} |
| 14491 | if (stb_err_inj_d2) |
| 14492 | begin |
| 14493 | if (~`SPC6.lsu_sbapp_err_g) |
| 14494 | begin |
| 14495 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 14496 | end |
| 14497 | else |
| 14498 | begin |
| 14499 | if ((`SPC6.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 14500 | (`SPC6.lsu_stberr_index_g != stb_err_index_d2) || |
| 14501 | (`SPC6.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 14502 | begin |
| 14503 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 14504 | end |
| 14505 | end |
| 14506 | end |
| 14507 | else |
| 14508 | begin |
| 14509 | if (`SPC6.lsu_sbapp_err_g) |
| 14510 | begin |
| 14511 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC6.lsu_stberr_tid_g); |
| 14512 | end |
| 14513 | end |
| 14514 | |
| 14515 | end //} |
| 14516 | |
| 14517 | |
| 14518 | always @ (posedge (`SPC6.l2clk & enabled & cmp_stb_err_inj)) |
| 14519 | begin |
| 14520 | stb_err_inj_d1 <= stb_err_inj; |
| 14521 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 14522 | stb_err_tid_d1 <= err_tid; |
| 14523 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 14524 | stb_err_index_d1 <= err_index; |
| 14525 | stb_err_index_d2 <= stb_err_index_d1; |
| 14526 | stb_err_priv_d1 <= err_priv; |
| 14527 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 14528 | end |
| 14529 | |
| 14530 | `endif |
| 14531 | `endif |
| 14532 | `endif |
| 14533 | endmodule |
| 14534 | |
| 14535 | `endif |
| 14536 | `ifdef CORE_7 |
| 14537 | |
| 14538 | module lsu_mon_c7; |
| 14539 | `ifndef GATESIM |
| 14540 | |
| 14541 | // If vcs_build_args NO_MONITORS, then module will be empty |
| 14542 | `ifndef NO_MONITORS |
| 14543 | |
| 14544 | reg imm_asi_vld_e; |
| 14545 | reg [7:0] asi_e, imm_asi_e, asi_m, asi_b; |
| 14546 | reg dec_altspace_e, dec_altspace_b, dec_altspace_m; |
| 14547 | reg [1:0] exu_ecc_b; |
| 14548 | reg [1:0] exu_lsu_va_error_b; |
| 14549 | reg [2:0] dec_lsu_tid_e, dec_lsu_tid_m, dec_lsu_tid_b, dec_lsu_tid_w; |
| 14550 | reg [47:0] inst_pc_e, inst_pc_m, inst_pc_b, inst_pc_w; |
| 14551 | reg [31:0] inst_e, inst_m, inst_b; |
| 14552 | reg [47:0] vaddr_m, vaddr_b; |
| 14553 | reg [63:0] int_st_data_m, int_st_data_b; |
| 14554 | reg [63:0] fp_st_sata_fx2; |
| 14555 | reg [20:0] lsu_inst_e, lsu_inst_m, lsu_inst_b; |
| 14556 | reg mmu_dtlb_reload_d1, mmu_dtlb_reload_d2; |
| 14557 | |
| 14558 | reg [7:0] ld_valid; |
| 14559 | reg [7:0] tlb_valid; |
| 14560 | reg [`LD_Pend_Width] ld_pend_array[7:0]; |
| 14561 | reg [`LAST_INST_Pend_Width] last_inst_array[7:0]; |
| 14562 | reg [2:0] wrptr[7:0]; //Pts. to the STB entry into which data will be written next |
| 14563 | reg [2:0] rdptr[7:0]; //Tracks the dealloc signal from STB |
| 14564 | reg [2:0] iss_ptr[7:0]; //keeps track of when a store is issued from the STB to PCX |
| 14565 | reg [2:0] ret_ptr[7:0]; //keeps track of when the response is received from |
| 14566 | //the L2c. |
| 14567 | reg [63:0] stb_valid; |
| 14568 | reg [`STB_Pend_Width] stb[63:0]; |
| 14569 | //reg [`TLB_MISS_Pend_Width] tlbmiss_pend_array[7:0]; |
| 14570 | |
| 14571 | reg [7:0] pf_cnt[7:0]; |
| 14572 | reg [7:0] dcache_inv_cnt[7:0]; |
| 14573 | reg [7:0] st_rmo_cnt[7:0]; |
| 14574 | |
| 14575 | reg [55:0] print_inst; |
| 14576 | |
| 14577 | reg [31:0] dec_tg0_inst_d, dec_tg1_inst_d; |
| 14578 | |
| 14579 | reg [7:0] lsu_bst_active; |
| 14580 | reg store_alloc; |
| 14581 | reg [3:0] bst_cnt; |
| 14582 | reg [195:0] stb_alloc_data; |
| 14583 | reg [195:0] bst_data, bst_inst_data; |
| 14584 | reg [2:0] bst_active_thid; |
| 14585 | reg bst_fgu_err; |
| 14586 | |
| 14587 | reg [7:0] is_blkld; //reqd by lsu_ras_chkr to chk errors on blk ld. |
| 14588 | reg [1:0] l2_blk_ld_errtype[7:0]; //Gives the type of err the ahd be reported by LSU if |
| 14589 | //different types of err occur on blk ld helper returns |
| 14590 | reg [1:0] st_priv[7:0]; //Gives the final priv level for an sbdiou/sbapp err that shd be |
| 14591 | //stored in DFESR |
| 14592 | |
| 14593 | wire [2:0] core_id = 7; |
| 14594 | |
| 14595 | integer i; |
| 14596 | integer err_cnt; |
| 14597 | |
| 14598 | reg enabled; |
| 14599 | reg reset_in_middle; |
| 14600 | reg [7:0] finish_mask; |
| 14601 | |
| 14602 | initial |
| 14603 | begin |
| 14604 | enabled = 0; |
| 14605 | reset_in_middle = 0; |
| 14606 | ld_valid = 8'b0; |
| 14607 | lsu_inst_e = 0; |
| 14608 | tlb_valid = 8'b0; |
| 14609 | for (i = 0; i < 8; i = i+1) |
| 14610 | begin |
| 14611 | pf_cnt[i] = 0; |
| 14612 | dcache_inv_cnt[i] = 0; |
| 14613 | wrptr[i] = 0; |
| 14614 | rdptr[i] = 0; |
| 14615 | iss_ptr[i] = 0; |
| 14616 | ret_ptr[i] = 0; |
| 14617 | st_rmo_cnt[i] = 0; |
| 14618 | is_blkld[i] = 1'b0; |
| 14619 | st_priv[i] = 2'b0; |
| 14620 | l2_blk_ld_errtype[i] = 2'b0; |
| 14621 | end |
| 14622 | lsu_bst_active = 8'b0; |
| 14623 | store_alloc = 1'b0; |
| 14624 | bst_cnt = 4'b0; |
| 14625 | stb_valid = 64'b0; |
| 14626 | |
| 14627 | // avoid time zero ugliness. jp |
| 14628 | //@(posedge `SPC0.l2clk); |
| 14629 | //@(negedge `SPC0.l2clk); |
| 14630 | //if (`PARGS.lsu_mon_on) enabled = 1; |
| 14631 | |
| 14632 | case (core_id) |
| 14633 | 3'h0: finish_mask = `PARGS.finish_mask[7:0]; |
| 14634 | 3'h1: finish_mask = `PARGS.finish_mask[15:8]; |
| 14635 | 3'h2: finish_mask = `PARGS.finish_mask[23:16]; |
| 14636 | 3'h3: finish_mask = `PARGS.finish_mask[31:24]; |
| 14637 | 3'h4: finish_mask = `PARGS.finish_mask[39:32]; |
| 14638 | 3'h5: finish_mask = `PARGS.finish_mask[47:40]; |
| 14639 | 3'h6: finish_mask = `PARGS.finish_mask[55:48]; |
| 14640 | 3'h7: finish_mask = `PARGS.finish_mask[63:56]; |
| 14641 | endcase |
| 14642 | end |
| 14643 | |
| 14644 | always @ (`TOP.in_reset) |
| 14645 | begin |
| 14646 | if (~`TOP.in_reset & `PARGS.lsu_mon_on & ~reset_in_middle) |
| 14647 | begin |
| 14648 | enabled = 1'b1; |
| 14649 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Lsu_mon on, in_reset = 0."); |
| 14650 | end |
| 14651 | |
| 14652 | |
| 14653 | if (`TOP.in_reset & enabled) |
| 14654 | begin |
| 14655 | reset_in_middle = 1'b1; |
| 14656 | enabled = 1'b0; |
| 14657 | `PR_ALWAYS("lsu_mon", `ALWAYS, "Reset asserted in the middle of the diag. Turned off Lsu_mon."); |
| 14658 | end |
| 14659 | end |
| 14660 | |
| 14661 | always @ (posedge (tb_top.sim_status[0] & enabled)) |
| 14662 | begin //{ |
| 14663 | if (|(ld_valid[7:0] & finish_mask[7:0])) |
| 14664 | begin //{ |
| 14665 | for (i = 0; i < 8; i=i+1) |
| 14666 | begin |
| 14667 | if (ld_valid[i]) |
| 14668 | begin |
| 14669 | DispPendReq(i); |
| 14670 | end |
| 14671 | end |
| 14672 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Ld requests pending at the end of simulation. ld_valid = %0h", core_id, ld_valid); |
| 14673 | end //} |
| 14674 | if (|stb_valid[63:0]) |
| 14675 | begin //{ |
| 14676 | err_cnt = 0; |
| 14677 | for (i = 0; i < 64; i=i+1) |
| 14678 | begin |
| 14679 | if (stb_valid[i] & finish_mask[i[5:3]]) |
| 14680 | begin |
| 14681 | //chkr resets the stb valid bits when block_store_kill is asserted. |
| 14682 | //in couple of failures block_store_kill was sampled asserted two cycles after |
| 14683 | //lsu asserted stb_empty. The simulation ended the cycle stb_empty was sampled high |
| 14684 | //causing moniotr firings with valid entries in stb at end of simulation. Now |
| 14685 | //don't flag an error if squash bit is set and stb_valid is asserted at end |
| 14686 | //of simualation. |
| 14687 | if (~is_squash_bit_set(i[5:0])) |
| 14688 | begin |
| 14689 | err_cnt = err_cnt + 1; |
| 14690 | Disp_STB_entry(i[5:3],i[2:0]); |
| 14691 | end |
| 14692 | end |
| 14693 | end |
| 14694 | if (err_cnt) |
| 14695 | begin |
| 14696 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Store requests pending at the end of simulation. stb_valid = %0h", core_id, stb_valid); |
| 14697 | end |
| 14698 | end //} |
| 14699 | err_cnt = 0; |
| 14700 | for (i = 0; i < 8; i=i+1) |
| 14701 | begin //{ |
| 14702 | if (finish_mask[i] & (pf_cnt[i] != 0)) |
| 14703 | begin |
| 14704 | err_cnt = 1; |
| 14705 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> Prefetches not finished. Pf_cnt = %0d", core_id, i, pf_cnt[i]); |
| 14706 | end |
| 14707 | if (finish_mask[i] & (dcache_inv_cnt[i] != 0)) |
| 14708 | begin |
| 14709 | err_cnt = 1; |
| 14710 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> D pkt not received for all invalidate reqs. issued by the thread. dcache_inv_cnt = %0d", core_id, i, dcache_inv_cnt[i]); |
| 14711 | end |
| 14712 | if (finish_mask[i] & (st_rmo_cnt[i] != 0)) |
| 14713 | begin |
| 14714 | err_cnt = 1; |
| 14715 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> rmo_cnt not zero. rmo_cnt = %0d", core_id, i, st_rmo_cnt[i]); |
| 14716 | end |
| 14717 | end //} |
| 14718 | if (err_cnt) |
| 14719 | begin |
| 14720 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> Prefetch/D/RMO_stores requests pending at the end of simulation.", core_id); |
| 14721 | end |
| 14722 | end //} |
| 14723 | |
| 14724 | function is_squash_bit_set; |
| 14725 | input [5:0] index; |
| 14726 | reg [204:0] tmp; |
| 14727 | begin |
| 14728 | tmp = stb[index]; |
| 14729 | if (tmp[`ST_SQUASH]) |
| 14730 | is_squash_bit_set = 1'b1; |
| 14731 | else |
| 14732 | is_squash_bit_set = 1'b0; |
| 14733 | end |
| 14734 | endfunction |
| 14735 | |
| 14736 | |
| 14737 | always @ (negedge (`SPC7.l2clk & enabled)) |
| 14738 | begin //{ |
| 14739 | |
| 14740 | asi_e = `SPC7.lsu.dcc.dcc_asi_e[7:0]; |
| 14741 | |
| 14742 | lsu_inst_e[`LD] <= `SPC7.dec_ld_inst_e; |
| 14743 | lsu_inst_e[`ST] <= `SPC7.dec_st_inst_e; |
| 14744 | lsu_inst_e[`FP] <= `SPC7.dec_fpldst_inst_e; |
| 14745 | lsu_inst_e[`PREF] <= `SPC7.dec_pref_inst_e; |
| 14746 | lsu_inst_e[`SWAP] <= `SPC7.dec_swap_inst_e; |
| 14747 | lsu_inst_e[`CASA] <= `SPC7.dec_casa_inst_e; |
| 14748 | lsu_inst_e[`LDSTUB] <= `SPC7.dec_ldstub_inst_e; |
| 14749 | lsu_inst_e[`FLUSH] <= `SPC7.dec_flush_inst_e; |
| 14750 | lsu_inst_e[`MEMBAR] <= `SPC7.dec_memstbar_inst_e; |
| 14751 | lsu_inst_e[`LDD] <= `SPC7.dec_ld_inst_e & `SPC7.dec_ldst_dbl_e & ~`SPC7.dec_fpldst_inst_e; |
| 14752 | lsu_inst_e[`STD] <= `SPC7.dec_st_inst_e & `SPC7.dec_ldst_dbl_e & ~`SPC7.lsu.dec_fpldst_inst_e; |
| 14753 | |
| 14754 | lsu_inst_e[`BLKLD] <= `SPC7.dec_ld_inst_e & `SPC7.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 14755 | lsu_inst_e[`BLKST] <= `SPC7.dec_st_inst_e & `SPC7.dec_fpldst_inst_e & dec_altspace_e & Is_blk_asi(asi_e); |
| 14756 | lsu_inst_e[`QLD] <= `SPC7.dec_ld_inst_e & dec_altspace_e & Is_qld_asi(asi_e); |
| 14757 | lsu_inst_e[`ASR_RD_WR] <= `SPC7.dec_sr_inst_e & (`SPC7.dec_ld_inst_e | `SPC7.dec_st_inst_e); |
| 14758 | lsu_inst_e[`PR_RD_WR] <= `SPC7.dec_pr_inst_e & (`SPC7.dec_ld_inst_e | `SPC7.dec_st_inst_e); |
| 14759 | lsu_inst_e[`HPR_RD_WR] <= `SPC7.dec_hpr_inst_e & (`SPC7.dec_ld_inst_e | `SPC7.dec_st_inst_e); |
| 14760 | lsu_inst_e[`FSR_RD_WR] <= `SPC7.dec_fsr_ldst_e & (`SPC7.dec_ld_inst_e | `SPC7.dec_st_inst_e); |
| 14761 | end //} |
| 14762 | |
| 14763 | always @ (posedge (`SPC7.l2clk & enabled)) |
| 14764 | begin //{ |
| 14765 | dec_tg0_inst_d <= `SPC7.dec.ded0.decode_mux[31:0]; |
| 14766 | dec_tg1_inst_d <= `SPC7.dec.ded1.decode_mux[31:0]; |
| 14767 | imm_asi_vld_e <= `SPC7.lsu.dec_imm_asi_vld_d; |
| 14768 | |
| 14769 | imm_asi_e <= `SPC7.lsu.dec_imm_asi_d; |
| 14770 | dec_altspace_e <= `SPC7.dec_altspace_d; |
| 14771 | dec_altspace_m <= dec_altspace_e; |
| 14772 | dec_altspace_b <= dec_altspace_m; |
| 14773 | |
| 14774 | exu_ecc_b <= `SPC7.exu_ecc_m; |
| 14775 | exu_lsu_va_error_b <= `SPC7.exu_lsu_va_error_m; |
| 14776 | |
| 14777 | dec_lsu_tid_e <= `SPC7.dec_lsu_tg_d ? {1'b1, `SPC7.dec_lsu_tid1_d} : {1'b0, `SPC7.dec_lsu_tid0_d}; |
| 14778 | dec_lsu_tid_m <= dec_lsu_tid_e; |
| 14779 | dec_lsu_tid_b <= dec_lsu_tid_m; |
| 14780 | dec_lsu_tid_w <= dec_lsu_tid_b; |
| 14781 | |
| 14782 | inst_pc_e <= `SPC7.dec_lsu_tg_d ? {`SPC7.tlu.tlu_pc_1_d[47:2], 2'b0} : {`SPC7.tlu.tlu_pc_0_d[47:2], 2'b0}; |
| 14783 | inst_pc_m <= inst_pc_e; |
| 14784 | inst_pc_b <= inst_pc_m; |
| 14785 | inst_pc_w <= inst_pc_b; |
| 14786 | |
| 14787 | inst_e <= `SPC7.dec_lsu_tg_d ? dec_tg1_inst_d : dec_tg0_inst_d; |
| 14788 | inst_m <= inst_e; |
| 14789 | inst_b <= inst_m; |
| 14790 | |
| 14791 | vaddr_m <= `SPC7.exu_lsu_address_e; |
| 14792 | vaddr_b <= vaddr_m; |
| 14793 | |
| 14794 | int_st_data_m <= `SPC7.exu_lsu_store_data_e; |
| 14795 | int_st_data_b <= int_st_data_m; |
| 14796 | fp_st_sata_fx2 <= `SPC7.fgu_lsu_fst_data_fx1; |
| 14797 | |
| 14798 | mmu_dtlb_reload_d1 <= `SPC7.mmu_dtlb_reload; |
| 14799 | mmu_dtlb_reload_d2 <= mmu_dtlb_reload_d1; |
| 14800 | |
| 14801 | //pcx_thid_d1 <= `SPC7.lsu.spc_pcx_data_pa[`PCX_THR_ID]; |
| 14802 | lsu_inst_m <= lsu_inst_e; |
| 14803 | lsu_inst_b <= lsu_inst_m; |
| 14804 | |
| 14805 | asi_m <= asi_e; |
| 14806 | asi_b <= asi_m; |
| 14807 | end //} |
| 14808 | |
| 14809 | function Is_blk_asi; |
| 14810 | input [7:0] asi; |
| 14811 | begin |
| 14812 | Is_blk_asi = (asi == `ASI_BLK_AIUP) | (asi == `ASI_BLK_AIUS) | |
| 14813 | (asi == `ASI_BLK_AIUPL) | (asi == `ASI_BLK_AIUSL) | |
| 14814 | (asi == `ASI_BLK_P) | (asi == `ASI_BLK_S) | |
| 14815 | (asi == `ASI_BLK_PL) | (asi == `ASI_BLK_SL) | |
| 14816 | (asi == `ASI_BLK_COMMIT_P) | (asi == `ASI_BLK_COMMIT_S); |
| 14817 | end |
| 14818 | endfunction |
| 14819 | |
| 14820 | function Is_qld_asi; |
| 14821 | input [7:0] asi; |
| 14822 | begin |
| 14823 | Is_qld_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 14824 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 14825 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 14826 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 14827 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE) | |
| 14828 | (asi == `ASI_QUAD_LDD) | (asi == `ASI_QUAD_LDD_REAL) | |
| 14829 | (asi == `ASI_QUAD_LDD_L) | (asi == `ASI_QUAD_LDD_REAL_L); |
| 14830 | end |
| 14831 | endfunction |
| 14832 | |
| 14833 | function Is_bis_asi; |
| 14834 | input [7:0] asi; |
| 14835 | begin |
| 14836 | Is_bis_asi = (asi == `ASI_AIU_BIS_QUAD_LDD_P) | (asi == `ASI_AIU_BIS_QUAD_LDD_S) | |
| 14837 | (asi == `ASI_AIU_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_AIU_BIS_QUAD_LDD_S_LITTLE) | |
| 14838 | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD) | (asi == `ASI_NUCLEUS_BIS_QUAD_LDD_LITTLE) | |
| 14839 | (asi == `ASI_BIS_QUAD_LDD_P) | (asi == `ASI_BIS_QUAD_LDD_S) | |
| 14840 | (asi == `ASI_BIS_QUAD_LDD_P_LITTLE) | (asi == `ASI_BIS_QUAD_LDD_S_LITTLE); |
| 14841 | end |
| 14842 | endfunction |
| 14843 | |
| 14844 | always @ (negedge (`SPC7.l2clk & enabled)) |
| 14845 | begin //{ |
| 14846 | Chk_store; |
| 14847 | store_alloc = 1'b0; |
| 14848 | if (lsu_inst_m != 0) |
| 14849 | begin |
| 14850 | if (`SPC7.dec_flush_lm) |
| 14851 | begin |
| 14852 | lsu_inst_m <= 0; |
| 14853 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> M_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_m, inst_pc_m, tb_top.intf0.xlate(inst_m),vaddr_m); |
| 14854 | end |
| 14855 | end |
| 14856 | |
| 14857 | if (lsu_inst_b != 0) |
| 14858 | begin //{ |
| 14859 | if (lsu_inst_b[`BLKLD]) print_inst = " BLKLD,"; |
| 14860 | else if (lsu_inst_b[`BLKST]) print_inst = " BLKST,"; |
| 14861 | else if (lsu_inst_b[`QLD]) print_inst = " QLD,"; |
| 14862 | else print_inst = ""; |
| 14863 | |
| 14864 | if (`SPC7.dec_flush_lb) |
| 14865 | begin |
| 14866 | lsu_inst_b <= 0; |
| 14867 | `PR_INFO("lsu_mon", 21, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to IFU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 14868 | end |
| 14869 | else if (`SPC7.tlu_flush_lsu_b) |
| 14870 | begin |
| 14871 | lsu_inst_b <= 0; |
| 14872 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to TLU Flush.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 14873 | end |
| 14874 | //casa is a two cycle operation. If there is an err on the 2nd cycle of casa then also |
| 14875 | //casa shd be killed. |
| 14876 | //This function will also chk for errors on 2nd cycle. |
| 14877 | else if (Is_exu_error(exu_lsu_va_error_b, exu_ecc_b)) |
| 14878 | begin |
| 14879 | lsu_inst_b <= 0; |
| 14880 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h <%0h> B_stage: %s(VA=%0h) Flushed due to EXU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 14881 | end |
| 14882 | else if ((`SPC7.fgu_cecc_fx2 || `SPC7.fgu_uecc_fx2) && lsu_inst_b[`ST] && lsu_inst_b[`FP]) |
| 14883 | begin |
| 14884 | lsu_inst_b <= 0; |
| 14885 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h) Flushed due to FGU error.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 14886 | end |
| 14887 | else if (IsExc(core_id)) |
| 14888 | lsu_inst_b <= 0; |
| 14889 | else if (!`SPC7.lsu_tlb_miss_b_) |
| 14890 | begin |
| 14891 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h)%s ASI = %0h. DTLB miss.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, asi_b); |
| 14892 | //Insert_tlb_miss_info; |
| 14893 | end |
| 14894 | else |
| 14895 | begin //{ |
| 14896 | //Lsu doesn't assert lsu_sync for an exception or dtlb miss. Since for |
| 14897 | //an exception tlu anyway tells the front end to flush itself there is |
| 14898 | //no reason for LSU to flush the front end then TLU to flush it again. |
| 14899 | //Lsu treats the dtlbmiss as an exception that it flushes the inst and |
| 14900 | //handles it when it is reissued by the front end. |
| 14901 | |
| 14902 | if (`SPC7.lsu_tlb_bypass_b) |
| 14903 | begin |
| 14904 | if (`SPC7.lsu_sync != 8'b0) |
| 14905 | begin |
| 14906 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 14907 | end |
| 14908 | else |
| 14909 | begin |
| 14910 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB Bypass.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 14911 | end |
| 14912 | end |
| 14913 | else |
| 14914 | begin |
| 14915 | if (`SPC7.lsu_sync != 8'b0) |
| 14916 | begin |
| 14917 | if (lsu_inst_b[`ST]) |
| 14918 | begin |
| 14919 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b,int_st_data_b); |
| 14920 | end |
| 14921 | else |
| 14922 | begin |
| 14923 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. LSU_sync. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 14924 | end |
| 14925 | end |
| 14926 | else |
| 14927 | begin |
| 14928 | if (lsu_inst_b[`ST]) |
| 14929 | begin |
| 14930 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h, Store_data = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b, int_st_data_b); |
| 14931 | end |
| 14932 | else |
| 14933 | begin |
| 14934 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h>: %s(VA=%0h)%s PA = %0h, ASI = %0h. DTLB hit.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, print_inst, {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}, asi_b); |
| 14935 | end |
| 14936 | end |
| 14937 | end |
| 14938 | |
| 14939 | if (lsu_inst_b[`LD] || lsu_inst_b[`PREF] || lsu_inst_b[`SWAP] || lsu_inst_b[`CASA] || lsu_inst_b[`LDSTUB]) |
| 14940 | begin //{ |
| 14941 | if (((lsu_inst_b == 16'h1) || (lsu_inst_b == 16'h5)) & `SPC7.lsu.stb_cam_hit) |
| 14942 | begin |
| 14943 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: LSU_sync asserted due to STB RAW.", core_id, dec_lsu_tid_b, inst_pc_b); |
| 14944 | end |
| 14945 | end //} |
| 14946 | |
| 14947 | if (lsu_inst_b[`LD]) |
| 14948 | Insert_ld_miss_info; |
| 14949 | |
| 14950 | if (lsu_inst_b[`ST]) //for atomics both ld and store signals are asserted |
| 14951 | begin |
| 14952 | Make_STB_data; |
| 14953 | store_alloc = 1'b1; |
| 14954 | end |
| 14955 | Insert_in_last_inst_array; |
| 14956 | |
| 14957 | if (`SPC7.lsu_trap_flush[7:0]) |
| 14958 | begin |
| 14959 | `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> Trap Flush asserted.", core_id, decode_tid(`SPC7.lsu_trap_flush[7:0])); |
| 14960 | end |
| 14961 | end //} |
| 14962 | end //} |
| 14963 | end //} |
| 14964 | |
| 14965 | //STB ue testing: |
| 14966 | //This is how we test squashing of stores by LSU_mon: |
| 14967 | //Whenever lsu asserts err_sbdiou signal, the monitor sets the squash |
| 14968 | //bit in the STB for the rest of the stores. If any of these squashed stores |
| 14969 | //is issued on the asi ring or to the PCX interface the monitor complains. |
| 14970 | //The squashed stores are deallocated when either a block_store_kill is |
| 14971 | //asserted or dealloc signals are asserted by the LSU. |
| 14972 | //When the block_store_kill is asserted, it tells the IFU to dealloc |
| 14973 | //all the pending stores in the IFU. It means the when block_store_kill |
| 14974 | //is asserted we have deallocated all the non-squashed requests from STB. |
| 14975 | //The 0in_chkr ensures that LSU flags the correct index and priv with the |
| 14976 | //the sbdiou signal to TLU. |
| 14977 | |
| 14978 | |
| 14979 | always @ (negedge (`SPC7.l2clk & enabled)) |
| 14980 | begin |
| 14981 | if (`SPC7.lsu_l15_valid & `SPC7.lsu.spc_pcx_data_pa[129]) |
| 14982 | Chk_pcx_req_pkt(`SPC7.lsu.spc_pcx_data_pa[129:0]); //chk if we need .lsu here |
| 14983 | if ((`SPC7.lsu_rngl_cdbus[64:63] == 2'b11) & ~`SPC7.lsu_rngl_cdbus[59]) |
| 14984 | Chk_st_on_ASI_ring(`LOCAL); |
| 14985 | |
| 14986 | if ((`SPC7.lsu_rngf_cdbus[64:63] == 2'b11) & ~`SPC7.lsu_rngf_cdbus[59]) |
| 14987 | Chk_st_on_ASI_ring(`FAST); |
| 14988 | |
| 14989 | //if (`SPC7.l15_lsu_valid) |
| 14990 | //Chk_cpx_response_pkt({`SPC7.l15_lsu_valid, `SPC7.l15_lsu_cpkt[17:13],`SPC7.l15_lsu_cpkt[11:0],`SPC7.l15_spc_data1[127:0]}); |
| 14991 | |
| 14992 | if (`SPC7.cpx_spc_data_cx[145]) |
| 14993 | Chk_cpx_response_pkt(`SPC7.cpx_spc_data_cx); |
| 14994 | |
| 14995 | if (`SPC7.lsu_complete[7:0] != 8'b0) |
| 14996 | begin |
| 14997 | if (`SPC7.lsu_complete[0]) Chk_ld_complete(0); |
| 14998 | if (`SPC7.lsu_complete[1]) Chk_ld_complete(1); |
| 14999 | if (`SPC7.lsu_complete[2]) Chk_ld_complete(2); |
| 15000 | if (`SPC7.lsu_complete[3]) Chk_ld_complete(3); |
| 15001 | if (`SPC7.lsu_complete[4]) Chk_ld_complete(4); |
| 15002 | if (`SPC7.lsu_complete[5]) Chk_ld_complete(5); |
| 15003 | if (`SPC7.lsu_complete[6]) Chk_ld_complete(6); |
| 15004 | if (`SPC7.lsu_complete[7]) Chk_ld_complete(7); |
| 15005 | end |
| 15006 | |
| 15007 | if (`SPC7.lsu_block_store_kill[7:0] != 8'b0) |
| 15008 | begin |
| 15009 | if (`SPC7.lsu_block_store_kill[0]) Squash_STB(0); |
| 15010 | if (`SPC7.lsu_block_store_kill[1]) Squash_STB(1); |
| 15011 | if (`SPC7.lsu_block_store_kill[2]) Squash_STB(2); |
| 15012 | if (`SPC7.lsu_block_store_kill[3]) Squash_STB(3); |
| 15013 | if (`SPC7.lsu_block_store_kill[4]) Squash_STB(4); |
| 15014 | if (`SPC7.lsu_block_store_kill[5]) Squash_STB(5); |
| 15015 | if (`SPC7.lsu_block_store_kill[6]) Squash_STB(6); |
| 15016 | if (`SPC7.lsu_block_store_kill[7]) Squash_STB(7); |
| 15017 | end |
| 15018 | |
| 15019 | if (`SPC7.lsu_stb_dealloc[7:0] != 8'b0) |
| 15020 | begin |
| 15021 | if (`SPC7.lsu_stb_dealloc[0]) Dealloc_STB(0); |
| 15022 | if (`SPC7.lsu_stb_dealloc[1]) Dealloc_STB(1); |
| 15023 | if (`SPC7.lsu_stb_dealloc[2]) Dealloc_STB(2); |
| 15024 | if (`SPC7.lsu_stb_dealloc[3]) Dealloc_STB(3); |
| 15025 | if (`SPC7.lsu_stb_dealloc[4]) Dealloc_STB(4); |
| 15026 | if (`SPC7.lsu_stb_dealloc[5]) Dealloc_STB(5); |
| 15027 | if (`SPC7.lsu_stb_dealloc[6]) Dealloc_STB(6); |
| 15028 | if (`SPC7.lsu_stb_dealloc[7]) Dealloc_STB(7); |
| 15029 | end |
| 15030 | |
| 15031 | if (`SPC7.lsu_block_store_stall) |
| 15032 | Chk_block_store; |
| 15033 | |
| 15034 | if (`SPC7.lsu.lsu_block_store_alloc[7:0] != 8'b0) |
| 15035 | Set_block_store_parameters; |
| 15036 | |
| 15037 | if (`SPC7.lsu_sbdiou_err_g || `SPC7.lsu_sbapp_err_g) |
| 15038 | Squash_store; |
| 15039 | |
| 15040 | if (`SPC7.lsu_stb_flush_g) |
| 15041 | st_priv[`SPC7.lsu_stberr_tid_g] = get_priv_on_flush(`SPC7.lsu_stberr_tid_g); |
| 15042 | end |
| 15043 | |
| 15044 | function [1:0] get_priv_on_flush; |
| 15045 | input [2:0] tid; |
| 15046 | reg [2:0] sq_index; |
| 15047 | reg [204:0] tmp; |
| 15048 | |
| 15049 | begin |
| 15050 | sq_index = `SPC7.lsu_stberr_index_g; |
| 15051 | tmp = stb[{tid, sq_index}]; |
| 15052 | get_priv_on_flush = tmp[`ST_PRIV]; |
| 15053 | end |
| 15054 | endfunction |
| 15055 | |
| 15056 | task Chk_block_store; |
| 15057 | reg [20:0] inst; |
| 15058 | reg [2:0] thid; |
| 15059 | begin |
| 15060 | thid = `SPC7.lsu_block_store_tid; |
| 15061 | bst_inst_data = stb[{thid, rdptr[thid]}]; |
| 15062 | inst = bst_inst_data[`LSU_MON_INST]; |
| 15063 | |
| 15064 | if (~inst[`BLKST]) |
| 15065 | begin |
| 15066 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 15067 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_stall while the req at the top of STB is not blkst as shown above", core_id, thid); |
| 15068 | end |
| 15069 | end |
| 15070 | endtask |
| 15071 | |
| 15072 | //lsu can assert block_store_stall for a new block store while it has not yet written |
| 15073 | //the 8 stb entries from the previous blk store. |
| 15074 | |
| 15075 | task Set_block_store_parameters; |
| 15076 | reg [2:0] thid; |
| 15077 | begin |
| 15078 | |
| 15079 | thid = decode_tid(`SPC7.lsu.lsu_block_store_alloc[7:0]); |
| 15080 | if (lsu_bst_active[thid]) |
| 15081 | begin |
| 15082 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted blk_store_alloc while the bst_active is already set for this thread.", core_id, thid); |
| 15083 | end |
| 15084 | else |
| 15085 | begin |
| 15086 | lsu_bst_active[thid] = 1'b1; |
| 15087 | bst_active_thid = thid; |
| 15088 | if (`SPC7.lsu.fgu_fst_ecc_error_fx2) |
| 15089 | bst_fgu_err = 1'b1; |
| 15090 | else |
| 15091 | bst_fgu_err = 1'b0; |
| 15092 | end |
| 15093 | end |
| 15094 | endtask |
| 15095 | |
| 15096 | task Squash_store; |
| 15097 | reg [2:0] thid; |
| 15098 | reg [2:0] sq_index; |
| 15099 | reg [2:0] i; |
| 15100 | reg [204:0] tmp; |
| 15101 | reg [3:0] squash_cnt; |
| 15102 | reg [1:0] priv; |
| 15103 | |
| 15104 | begin |
| 15105 | thid = `SPC7.lsu_stberr_tid_g; |
| 15106 | sq_index = `SPC7.lsu_stberr_index_g; |
| 15107 | priv = `SPC7.lsu_stberr_priv_g; |
| 15108 | tmp = stb[{thid, sq_index}]; |
| 15109 | squash_cnt = 0; |
| 15110 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Sbdiou/sbapp seen for index = %h and priv = %h.", core_id, thid, sq_index, priv); |
| 15111 | |
| 15112 | st_priv[thid] = tmp[`ST_PRIV]; |
| 15113 | |
| 15114 | //lsu can assert deallocate before it asserts the sbdiou signal. |
| 15115 | //In that case iss_ptr won't be equal to sbdiou index. |
| 15116 | //if (sq_index != iss_ptr[thid]) |
| 15117 | //begin |
| 15118 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 15119 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted sbdiou/sbapp with index %0h while the next req to be issued is at index %0h.", core_id, thid, sq_index, iss_ptr[thid]); |
| 15120 | //end |
| 15121 | |
| 15122 | //If there is only one store in the store buffer which gets an sbdiou error, then LSU can deallocate |
| 15123 | //the store and then assert sbdiou. The deallocation will cause the stb issue_ptr to move |
| 15124 | //forward to an inst. that has already been issued and completed and this chk can fire. So |
| 15125 | //removing this chk. |
| 15126 | |
| 15127 | //if (tmp[`L2_ST_ISS]) |
| 15128 | //begin |
| 15129 | // Disp_STB_entry(thid, iss_ptr[thid]); |
| 15130 | // `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, tmp[`MEMOP_PA]); |
| 15131 | //end |
| 15132 | |
| 15133 | if (iss_ptr[thid] == wrptr[thid]) |
| 15134 | begin |
| 15135 | if (stb_valid[{thid, wrptr[thid]}]) |
| 15136 | squash_cnt = 8; |
| 15137 | else |
| 15138 | begin |
| 15139 | //changing it to an info message because if there is only one valid entry in store buffer that |
| 15140 | //gets an sbdiou then LSU can deallocate the entry and then issue sbdiou. |
| 15141 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted sbdiou/sbapp while there are no valid entries in STB to be issued.", core_id, thid); |
| 15142 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> sbdiou/sbapp squashed only one entry in STB.", core_id, thid); |
| 15143 | end |
| 15144 | end |
| 15145 | else |
| 15146 | begin |
| 15147 | if (iss_ptr[thid] < wrptr[thid]) |
| 15148 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 15149 | else if (iss_ptr[thid] > wrptr[thid]) |
| 15150 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 15151 | end |
| 15152 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STORE:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 15153 | |
| 15154 | i = iss_ptr[thid]; |
| 15155 | |
| 15156 | while (squash_cnt) |
| 15157 | begin |
| 15158 | tmp = stb[{thid, i}]; |
| 15159 | tmp[`ST_SQUASH] = 1'b1; |
| 15160 | if (priv < tmp[`ST_PRIV]) |
| 15161 | begin |
| 15162 | `PR_INFO("lsu_mon", `INFO, "<C%h> <T%0h> <PA = %0h> Sbdiou/sbapp signalled. Err in user/priv level store is squashing a higher priv level store.", core_id, thid, tmp[`MEMOP_PA]); |
| 15163 | priv = tmp[`ST_PRIV]; |
| 15164 | end |
| 15165 | |
| 15166 | stb[{thid, i}] = tmp; |
| 15167 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed.", core_id, thid, tmp[`MEMOP_PA], i); |
| 15168 | |
| 15169 | i = i + 1; |
| 15170 | squash_cnt = squash_cnt - 1'b1; |
| 15171 | end |
| 15172 | end |
| 15173 | endtask |
| 15174 | |
| 15175 | function [2:0] decode_tid; |
| 15176 | input [7:0] thid_encode; |
| 15177 | begin |
| 15178 | case (thid_encode) |
| 15179 | 8'h1: decode_tid = 3'b0; |
| 15180 | 8'h2: decode_tid = 3'h1; |
| 15181 | 8'h4: decode_tid = 3'h2; |
| 15182 | 8'h8: decode_tid = 3'h3; |
| 15183 | 8'h10: decode_tid = 3'h4; |
| 15184 | 8'h20: decode_tid = 3'h5; |
| 15185 | 8'h40: decode_tid = 3'h6; |
| 15186 | 8'h80: decode_tid = 3'h7; |
| 15187 | default: |
| 15188 | begin |
| 15189 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> decode_tid. Incorrect value of thid input = %0h.", core_id, thid_encode, thid_encode); |
| 15190 | end |
| 15191 | endcase |
| 15192 | end |
| 15193 | endfunction |
| 15194 | |
| 15195 | task Chk_ld_complete; |
| 15196 | input [2:0] thid; |
| 15197 | reg [`LD_Pend_Width] tmp; |
| 15198 | begin |
| 15199 | tmp = ld_pend_array[thid]; |
| 15200 | |
| 15201 | if (ld_valid[thid]) |
| 15202 | begin |
| 15203 | if ((tmp[`L2_ISS] != 4'hf) || (tmp[`L2_RESP] != 4'hf)) |
| 15204 | begin |
| 15205 | DispPendReq(thid); |
| 15206 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> LSU asserted lsu_complete while the l2_iss and l2_resp bits are not F.", core_id, thid); |
| 15207 | end |
| 15208 | ld_valid[thid] = 1'b0; |
| 15209 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete. Setting ld_valid to 0.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 15210 | end |
| 15211 | |
| 15212 | tmp = last_inst_array[thid]; |
| 15213 | `PR_INFO("lsu_mon", 24, "<C%h> <T%0h> <%0h> %s(VA=%0h) Complete.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 15214 | end |
| 15215 | endtask |
| 15216 | |
| 15217 | task Chk_pcx_req_pkt; |
| 15218 | input [129:0] pcx_pkt; |
| 15219 | reg [2:0] thid; |
| 15220 | reg [`LD_Pend_Width] tmp, tmp1; |
| 15221 | reg [15:0] inst; |
| 15222 | reg [11*8:0] req; |
| 15223 | reg [39:0] addr; |
| 15224 | begin |
| 15225 | thid = pcx_pkt[`PCX_THR_ID]; |
| 15226 | tmp = ld_pend_array[thid]; |
| 15227 | inst = tmp[`LSU_MON_INST]; |
| 15228 | req = DispPCXReq(pcx_pkt); |
| 15229 | addr = pcx_pkt[`PCX_ADDR]; |
| 15230 | |
| 15231 | |
| 15232 | if (pcx_pkt[`PCX_CPU_ID] != core_id) |
| 15233 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> cpu_id (spc_pcx_data_pa[122:120]) = %h is not = %0h when the lsu made a %s req to gasket.", core_id, pcx_pkt[`PCX_THR_ID], addr, pcx_pkt[122:120], core_id, req); |
| 15234 | |
| 15235 | |
| 15236 | if ((pcx_pkt[`PCX_RQTYP] == `PCX_LOAD) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) || (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) || (pcx_pkt[`PCX_RQTYP] == `PCX_SWAP_LDSTUB)) |
| 15237 | begin |
| 15238 | if (~ld_valid[thid]) |
| 15239 | begin |
| 15240 | ld_valid[thid] = 1'b1; //we have sent a req to gasket and are waiting for response |
| 15241 | `PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> Setting ld_valid[%0h].", core_id, thid, thid); |
| 15242 | end |
| 15243 | if (~inst[`BLKLD]) |
| 15244 | begin |
| 15245 | if (tmp[`MEMOP_PA] != addr) |
| 15246 | begin |
| 15247 | if ((tmp[`INST_ASI] == 8'h41) || (tmp[`INST_ASI] == 8'h73) || ((tmp[`INST_ASI] == 8'h45) && ((tmp[`MEMOP_PA] == 8'h10) || (tmp[`MEMOP_PA] == 8'h18)))) |
| 15248 | begin |
| 15249 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <PA = %0h> PA mismatch on gasket for %s request. Ignoring the mismatch as inst. is issued with asi 41, 73 or 45 (with VA 0x10 or 18).", core_id, thid, addr, req); |
| 15250 | end |
| 15251 | else |
| 15252 | begin |
| 15253 | DispPendReq(thid); |
| 15254 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A %s request made to gasket by LSU while the pending req is with PA %0h.", core_id, thid, addr, req, tmp[`MEMOP_PA]); |
| 15255 | end |
| 15256 | end |
| 15257 | end |
| 15258 | end |
| 15259 | |
| 15260 | case (pcx_pkt[`PCX_RQTYP]) |
| 15261 | `PCX_LOAD: |
| 15262 | begin |
| 15263 | if (pcx_pkt[`PCX_PF]) |
| 15264 | begin |
| 15265 | if (~inst[`PREF]) |
| 15266 | begin |
| 15267 | DispPendReq(thid); |
| 15268 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A prefetch request made to gasket by LSU which mismatches the pending request from the thread.", core_id, thid, addr); |
| 15269 | end |
| 15270 | if (pcx_pkt[`PCX_INV]) |
| 15271 | begin |
| 15272 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: PREF_ICE(VA=%0h) Issued. pf_cnt not updated.", core_id, thid, tmp[`INST_VA], tmp[`MEMOP_VA]); |
| 15273 | end |
| 15274 | else |
| 15275 | begin |
| 15276 | pf_cnt[thid] = pf_cnt[thid] + 1'b1; |
| 15277 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued. pf_cnt = %0d.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pf_cnt[thid]); |
| 15278 | end |
| 15279 | tmp[`L2_ISS] = 4'hF; |
| 15280 | tmp[`L2_RESP] = 4'hF; //we don't wait for a prefetch response from gasket |
| 15281 | ld_pend_array[thid] = tmp; |
| 15282 | end |
| 15283 | else |
| 15284 | begin |
| 15285 | if (pcx_pkt[`PCX_INV]) |
| 15286 | begin |
| 15287 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Dcache invalidate pkt issued to CCX.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15288 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] + 1'b1; |
| 15289 | end |
| 15290 | else |
| 15291 | begin |
| 15292 | Chk_req_load(pcx_pkt); |
| 15293 | end |
| 15294 | end |
| 15295 | end |
| 15296 | `PCX_CAS1, `PCX_CAS2: |
| 15297 | begin |
| 15298 | if (~inst[`CASA]) |
| 15299 | begin |
| 15300 | DispPendReq(thid); |
| 15301 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> CASA request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr); |
| 15302 | end |
| 15303 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS1) |
| 15304 | begin |
| 15305 | tmp[`L2_ISS] = 4'hE; |
| 15306 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS1) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15307 | ld_pend_array[thid] = tmp; |
| 15308 | end |
| 15309 | if (pcx_pkt[`PCX_RQTYP] == `PCX_CAS2) |
| 15310 | begin |
| 15311 | tmp[`L2_ISS] = 4'hF; |
| 15312 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) (CAS2) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15313 | ld_pend_array[thid] = tmp; |
| 15314 | chk_store_issue_to_pcx(pcx_pkt); |
| 15315 | end |
| 15316 | |
| 15317 | end |
| 15318 | `PCX_SWAP_LDSTUB: |
| 15319 | begin |
| 15320 | if (~inst[`SWAP] && ~inst[`LDSTUB]) |
| 15321 | begin |
| 15322 | DispPendReq(thid); |
| 15323 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> %s request made to gasket by LSU while no such request request is pending from this thread.", core_id, thid, addr, req); |
| 15324 | end |
| 15325 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket. store_data = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], pcx_pkt[`PCX_DATA]); |
| 15326 | tmp[`L2_ISS] = 4'hF; |
| 15327 | ld_pend_array[thid] = tmp; |
| 15328 | |
| 15329 | chk_store_issue_to_pcx(pcx_pkt); |
| 15330 | end |
| 15331 | |
| 15332 | `PCX_STORE: |
| 15333 | begin |
| 15334 | chk_store_issue_to_pcx(pcx_pkt); |
| 15335 | end |
| 15336 | |
| 15337 | default: `PR_INFO("lsu_mon", 21, "<C%h> <T%0h> <%0h>: %s Issued to gasket.", core_id, thid, addr, req); |
| 15338 | endcase |
| 15339 | end |
| 15340 | endtask |
| 15341 | |
| 15342 | task Chk_cpx_response_pkt; |
| 15343 | input [145:0] cpx_pkt; |
| 15344 | reg [2:0] thid; |
| 15345 | begin |
| 15346 | thid = cpx_pkt[`CPX_THR_ID]; |
| 15347 | |
| 15348 | casex ({cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]}) |
| 15349 | {4'b0, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 15350 | begin |
| 15351 | chk_ccx_ld_response(cpx_pkt); |
| 15352 | end |
| 15353 | |
| 15354 | {4'b0, 2'bxx, 1'b1, 1'b0, 1'b1}: |
| 15355 | begin |
| 15356 | if (pf_cnt[thid] == 8'b0) |
| 15357 | begin |
| 15358 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Prefetch response received from gasket while the pf_cnt is 0 for this thread.", core_id, thid); |
| 15359 | end |
| 15360 | else |
| 15361 | begin |
| 15362 | pf_cnt[thid] = pf_cnt[thid] - 1'b1; |
| 15363 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> Prefetch response received. pfcnt = %0d.", core_id, thid, pf_cnt[thid]); |
| 15364 | end |
| 15365 | end |
| 15366 | |
| 15367 | {4'h8, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 15368 | chk_ccx_ld_response(cpx_pkt); |
| 15369 | |
| 15370 | {4'h4, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 15371 | begin |
| 15372 | if (cpx_pkt[123]) //D pkt |
| 15373 | begin //{ |
| 15374 | if (cpx_pkt[120:118] != core_id) |
| 15375 | begin |
| 15376 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 15377 | end |
| 15378 | if (dcache_inv_cnt[thid] == 8'b0) |
| 15379 | begin |
| 15380 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> D response received from gasket while the Dcache_inv_cnt is 0 for this thread.", core_id, thid); |
| 15381 | end |
| 15382 | else |
| 15383 | begin |
| 15384 | dcache_inv_cnt[thid] = dcache_inv_cnt[thid] - 1'b1; |
| 15385 | `PR_INFO("lsu_mon", 26, "<C%h> <T%0h> D response received. Dcache_inv_cnt = %0d.", core_id, thid, dcache_inv_cnt[thid]); |
| 15386 | end |
| 15387 | end //} |
| 15388 | else if (cpx_pkt[124]) //I pkt |
| 15389 | begin |
| 15390 | if (cpx_pkt[120:118] != core_id) |
| 15391 | begin |
| 15392 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> I response received from gasket with core_id =%h.", core_id, thid, cpx_pkt[120:118]); |
| 15393 | end |
| 15394 | //`PR_INFO("lsu_mon", 25, "<C%h> <T%0h> I pkt.", core_id, thid); |
| 15395 | end |
| 15396 | else if (cpx_pkt[124:123] == 2'b0) |
| 15397 | begin |
| 15398 | if (cpx_pkt[120:118] == core_id) |
| 15399 | begin |
| 15400 | chk_ccx_st_response(cpx_pkt); |
| 15401 | end |
| 15402 | else |
| 15403 | begin |
| 15404 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Store Ack pkt received from core %0h.", core_id, thid, cpx_pkt[120:118]); |
| 15405 | end |
| 15406 | end |
| 15407 | end |
| 15408 | |
| 15409 | {4'h1, 2'bxx, 1'bx, 1'b0, 1'b0}: |
| 15410 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL1 return.", core_id, thid); |
| 15411 | {4'h1, 2'bxx, 1'bx, 1'b1, 1'b0}: |
| 15412 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> IFILL2 return.", core_id, thid); |
| 15413 | {4'h9, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 15414 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> NCU IFILL return.", core_id, thid); |
| 15415 | |
| 15416 | {4'b0, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 15417 | begin |
| 15418 | chk_ccx_atm_response(cpx_pkt); |
| 15419 | end |
| 15420 | {4'h4, 2'bxx, 1'b1, 1'b1, 1'b0}: |
| 15421 | begin |
| 15422 | if ((cpx_pkt[`CPX_RTNTYP] == 4'h4) & (cpx_pkt[120:118] == core_id)) |
| 15423 | begin |
| 15424 | chk_ccx_atm_response(cpx_pkt); |
| 15425 | chk_ccx_st_response(cpx_pkt); |
| 15426 | end |
| 15427 | end |
| 15428 | |
| 15429 | {4'h2, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 15430 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream Ld return.", core_id, thid); |
| 15431 | {4'h6, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 15432 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Stream store Ack.", core_id, thid); |
| 15433 | {4'h5, 2'bxx, 1'b1, 1'b0, 1'b0}: |
| 15434 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> MMU ld return.", core_id, thid); |
| 15435 | {4'h7, 2'b00, 1'b0, 1'bx, 1'b0}: |
| 15436 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Interrupt return.", core_id, thid); |
| 15437 | {4'h3, 2'b00, 1'bx, 1'bx, 1'b0}: |
| 15438 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Eviction Invalidation.", core_id, thid); |
| 15439 | {4'hc, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 15440 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> L2 Indication.", core_id, thid); |
| 15441 | |
| 15442 | {4'hd, 2'bxx, 1'bx, 1'bx, 1'b0}: |
| 15443 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> Soc Error Indication.", core_id, thid); |
| 15444 | |
| 15445 | default: |
| 15446 | begin |
| 15447 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 15448 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 15449 | |
| 15450 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> Can't recognise the CPX pkt.", core_id, thid); |
| 15451 | end |
| 15452 | |
| 15453 | endcase |
| 15454 | end |
| 15455 | endtask |
| 15456 | |
| 15457 | task chk_ccx_ld_response; |
| 15458 | input [145:0] cpx_pkt; |
| 15459 | reg [2:0] thid; |
| 15460 | reg [20:0] inst; |
| 15461 | reg [39:0] cpx_pa, inst_pa; |
| 15462 | reg [`LD_Pend_Width] tmp; |
| 15463 | reg [3:0] pkt_type; |
| 15464 | begin |
| 15465 | thid = cpx_pkt[`CPX_THR_ID]; |
| 15466 | tmp = ld_pend_array[thid]; |
| 15467 | inst = tmp[`LSU_MON_INST]; |
| 15468 | inst_pa = tmp[`MEMOP_PA]; |
| 15469 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 15470 | |
| 15471 | if (ld_valid[thid]) |
| 15472 | begin |
| 15473 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) L2 response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 15474 | /* |
| 15475 | if (inst_pa[39] != pkt_type[3]) |
| 15476 | begin |
| 15477 | DispPendReq(thid); |
| 15478 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> ccx pkt_type = %h mismatches the ld_pa bit 39. ld_pa = %0h.", core_id, thid, pkt_type, inst_pa); |
| 15479 | end |
| 15480 | */ |
| 15481 | |
| 15482 | if (inst[`BLKLD]) |
| 15483 | begin |
| 15484 | if (tmp[`L2_RESP] == 4'h0) |
| 15485 | begin |
| 15486 | tmp[`L2_RESP] = 4'h1; |
| 15487 | tmp[`L2_ERR0] = cpx_pkt[`CPX_ERR]; |
| 15488 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 15489 | begin |
| 15490 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 1.", core_id, thid); |
| 15491 | end |
| 15492 | |
| 15493 | end |
| 15494 | else if (tmp[`L2_RESP] == 4'h1) |
| 15495 | begin |
| 15496 | tmp[`L2_RESP] = 4'h3; |
| 15497 | tmp[`L2_ERR1] = cpx_pkt[`CPX_ERR]; |
| 15498 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 15499 | begin |
| 15500 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 2.", core_id, thid); |
| 15501 | end |
| 15502 | end |
| 15503 | else if (tmp[`L2_RESP] == 4'h3) |
| 15504 | begin |
| 15505 | tmp[`L2_RESP] = 4'h7; |
| 15506 | tmp[`L2_ERR2] = cpx_pkt[`CPX_ERR]; |
| 15507 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 15508 | begin |
| 15509 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 3.", core_id, thid); |
| 15510 | end |
| 15511 | end |
| 15512 | else if (tmp[`L2_RESP] == 4'h7) |
| 15513 | begin |
| 15514 | tmp[`L2_RESP] = 4'hF; |
| 15515 | tmp[`L2_ERR3] = cpx_pkt[`CPX_ERR]; |
| 15516 | if ((cpx_pkt[`CPX_ERR] == `ND) || (cpx_pkt[`CPX_ERR] == `UE)) |
| 15517 | begin |
| 15518 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> UE/ND err on blk ld helper 4.", core_id, thid); |
| 15519 | end |
| 15520 | |
| 15521 | //is_blkld[thid] = 1'b1; |
| 15522 | if ((tmp[`L2_ERR0] == `ND) || (tmp[`L2_ERR1] == `ND) || (tmp[`L2_ERR2] == `ND) || (tmp[`L2_ERR3] == `ND)) |
| 15523 | l2_blk_ld_errtype[thid] = `ND; |
| 15524 | else if ((tmp[`L2_ERR0] == `UE) || (tmp[`L2_ERR1] == `UE) || (tmp[`L2_ERR2] == `UE) || (tmp[`L2_ERR3] == `UE)) |
| 15525 | l2_blk_ld_errtype[thid] = `UE; |
| 15526 | else if ((tmp[`L2_ERR0] == `CE) || (tmp[`L2_ERR1] == `CE) || (tmp[`L2_ERR2] == `CE) || (tmp[`L2_ERR3] == `CE)) |
| 15527 | l2_blk_ld_errtype[thid] = `CE; |
| 15528 | else |
| 15529 | l2_blk_ld_errtype[thid] = `NE; |
| 15530 | end |
| 15531 | else |
| 15532 | begin |
| 15533 | DispPendReq(thid); |
| 15534 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 15535 | end |
| 15536 | end |
| 15537 | else if (Is_single_pcx_req_ld(inst)) |
| 15538 | begin |
| 15539 | //is_blkld[thid] = 1'b0; |
| 15540 | if (tmp[`L2_RESP] != 4'hE) |
| 15541 | begin |
| 15542 | DispPendReq(thid); |
| 15543 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when response pkt received from ccx.", core_id, thid); |
| 15544 | end |
| 15545 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Setting L2_resp bits to F.", core_id, thid); |
| 15546 | tmp[`L2_RESP] = 4'hF; |
| 15547 | end |
| 15548 | else |
| 15549 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket for thid %h while no load request pending from core for this thread.", core_id, thid, thid); |
| 15550 | end |
| 15551 | else |
| 15552 | begin |
| 15553 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Load response received from gasket while no load request pending from core for this thread.", core_id, thid); |
| 15554 | end |
| 15555 | |
| 15556 | ld_pend_array[thid] = tmp; |
| 15557 | end |
| 15558 | endtask |
| 15559 | |
| 15560 | task chk_ccx_atm_response; |
| 15561 | input [145:0] cpx_pkt; |
| 15562 | reg [2:0] thid; |
| 15563 | reg [20:0] inst; |
| 15564 | reg [39:0] inst_pa; |
| 15565 | reg [`LD_Pend_Width] tmp; |
| 15566 | begin |
| 15567 | thid = cpx_pkt[`CPX_THR_ID]; |
| 15568 | tmp = ld_pend_array[thid]; |
| 15569 | inst = tmp[`LSU_MON_INST]; |
| 15570 | inst_pa = tmp[`MEMOP_PA]; |
| 15571 | |
| 15572 | if (~ld_valid[thid]) |
| 15573 | begin |
| 15574 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 15575 | begin |
| 15576 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 15577 | end |
| 15578 | else |
| 15579 | begin |
| 15580 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket while no request pending from core for this thread.", core_id, thid); |
| 15581 | end |
| 15582 | end |
| 15583 | else |
| 15584 | begin |
| 15585 | if (~inst[`SWAP] && ~inst[`CASA] && ~inst[`LDSTUB]) |
| 15586 | begin |
| 15587 | DispPendReq(thid); |
| 15588 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 15589 | begin |
| 15590 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ld response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 15591 | end |
| 15592 | else |
| 15593 | begin |
| 15594 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Atomic ack response received from gasket which mismatches the request pending from this thread.", core_id, thid); |
| 15595 | end |
| 15596 | end |
| 15597 | else |
| 15598 | begin |
| 15599 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 15600 | begin |
| 15601 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ld response.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 15602 | end |
| 15603 | else |
| 15604 | begin |
| 15605 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) Atomic ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 15606 | end |
| 15607 | |
| 15608 | if (cpx_pkt[`CPX_RTNTYP] == 4'b0) |
| 15609 | begin |
| 15610 | if (tmp[`L2_RESP] == 4'hC) tmp[`L2_RESP] = 4'hD; |
| 15611 | else |
| 15612 | begin |
| 15613 | DispPendReq(thid); |
| 15614 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ld return pkt received from ccx.", core_id, thid); |
| 15615 | end |
| 15616 | end |
| 15617 | else |
| 15618 | begin |
| 15619 | if (tmp[`L2_RESP] == 4'hD) tmp[`L2_RESP] = 4'hF; |
| 15620 | else |
| 15621 | begin |
| 15622 | DispPendReq(thid); |
| 15623 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Illegal value of l2_resp cnt when atomic ack pkt received from ccx.", core_id, thid); |
| 15624 | end |
| 15625 | end |
| 15626 | end |
| 15627 | end |
| 15628 | ld_pend_array[thid] = tmp; |
| 15629 | end |
| 15630 | endtask |
| 15631 | |
| 15632 | task chk_ccx_st_response; |
| 15633 | input [145:0] cpx_pkt; |
| 15634 | reg [2:0] thid; |
| 15635 | reg [20:0] inst; |
| 15636 | reg [39:0] cpx_pa, inst_pa; |
| 15637 | reg [204:0] tmp; |
| 15638 | reg [3:0] pkt_type; |
| 15639 | begin |
| 15640 | thid = cpx_pkt[`CPX_THR_ID]; |
| 15641 | tmp = stb[{thid, ret_ptr[thid]}]; |
| 15642 | inst = tmp[`LSU_MON_INST]; |
| 15643 | inst_pa = tmp[`MEMOP_PA]; |
| 15644 | pkt_type = cpx_pkt[`CPX_RTNTYP]; |
| 15645 | |
| 15646 | |
| 15647 | //is received. There could be some other store sitting in the STB at that time. |
| 15648 | |
| 15649 | //Chk for squash bit only for non-bis responses. |
| 15650 | |
| 15651 | |
| 15652 | if (cpx_pkt[`CPX_BIS]) //response to rmo store |
| 15653 | begin |
| 15654 | if (st_rmo_cnt[thid] == 0) |
| 15655 | begin |
| 15656 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received for an rmo store while the st_rmo_cnt for this thread is 0.", core_id, thid); |
| 15657 | end |
| 15658 | else |
| 15659 | begin |
| 15660 | st_rmo_cnt[thid] = st_rmo_cnt[thid] - 1'b1; |
| 15661 | `PR_INFO("lsu_mon", 25, "<C%0h> <T%0h> Store ack received for RMO store. rmo_cnt = %0d", core_id, thid, st_rmo_cnt[thid]); |
| 15662 | end |
| 15663 | end |
| 15664 | else |
| 15665 | begin |
| 15666 | if (tmp[`ST_SQUASH]) |
| 15667 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> L2 response received while the SQUASH bit is set in the STB entry %0h.", core_id, thid, ret_ptr[thid]); |
| 15668 | |
| 15669 | if (~stb_valid[{thid, ret_ptr[thid]}]) |
| 15670 | begin |
| 15671 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Store ack received while that entry is invalid in STB.", core_id, thid); |
| 15672 | end |
| 15673 | else |
| 15674 | begin |
| 15675 | if (~cpx_pkt[`CPX_ATM]) //don't print this message for atomic return |
| 15676 | begin |
| 15677 | `PR_INFO("lsu_mon", 26, "<C%0h> <T%0h> <%0h> %s(VA=%0h) STB[%0d] Store ack.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], ret_ptr[thid]); |
| 15678 | end |
| 15679 | tmp[`L2_ACK] = 1'b1; |
| 15680 | stb[{thid, ret_ptr[thid]}] = tmp; |
| 15681 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 15682 | //`PR_INFO("lsu_mon", 22, "<C%0h> <T%0h> ret_ptr = %0d.", core_id, thid, ret_ptr[thid]); |
| 15683 | end |
| 15684 | end |
| 15685 | end |
| 15686 | endtask |
| 15687 | |
| 15688 | task Chk_req_load; |
| 15689 | input [129:0] pcx_pkt; |
| 15690 | reg [2:0] thid; |
| 15691 | reg [`LD_Pend_Width] tmp; |
| 15692 | reg [39:0] pcx_pa, inst_pa; |
| 15693 | reg [20:0] inst; |
| 15694 | reg [11*8:0] req; |
| 15695 | begin |
| 15696 | |
| 15697 | thid = pcx_pkt[`PCX_THR_ID]; |
| 15698 | tmp = ld_pend_array[thid]; |
| 15699 | inst = tmp[`LSU_MON_INST]; |
| 15700 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 15701 | inst_pa = tmp[`MEMOP_PA]; |
| 15702 | req = DispPCXReq(pcx_pkt); |
| 15703 | |
| 15704 | if (inst[`BLKLD]) |
| 15705 | begin |
| 15706 | if (pcx_pa[39:6] != inst_pa[39:6]) |
| 15707 | begin |
| 15708 | DispPendReq(thid); |
| 15709 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pa, tmp[`MEMOP_PA]); |
| 15710 | end |
| 15711 | if (pcx_pa[5:0] == 6'b0) |
| 15712 | begin |
| 15713 | if (tmp[`L2_ISS] != 4'h0 ) |
| 15714 | begin |
| 15715 | DispPendReq(thid); |
| 15716 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 1st load request (pa[5:0] = 6'b0) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 15717 | end |
| 15718 | else |
| 15719 | begin |
| 15720 | tmp[`L2_ISS] = 4'h1; |
| 15721 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 1st blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15722 | end |
| 15723 | |
| 15724 | end |
| 15725 | if (pcx_pa[5:0] == 6'h10) |
| 15726 | begin |
| 15727 | if (tmp[`L2_ISS] != 4'h1) |
| 15728 | begin |
| 15729 | DispPendReq(thid); |
| 15730 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 2nd load request (pa[5:0] = 6'h10) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 15731 | end |
| 15732 | else |
| 15733 | begin |
| 15734 | tmp[`L2_ISS] = 4'h3; |
| 15735 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 2nd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15736 | end |
| 15737 | end |
| 15738 | if (pcx_pa[5:0] == 6'h20) |
| 15739 | begin |
| 15740 | if (tmp[`L2_ISS] != 4'h3) |
| 15741 | begin |
| 15742 | DispPendReq(thid); |
| 15743 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 3rd load request (pa[5:0] = 6'h20) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 15744 | end |
| 15745 | else |
| 15746 | begin |
| 15747 | tmp[`L2_ISS] = 4'h7; |
| 15748 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 3rd blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15749 | end |
| 15750 | end |
| 15751 | if (pcx_pa[5:0] == 6'h30) |
| 15752 | begin |
| 15753 | if (tmp[`L2_ISS] != 4'h7) |
| 15754 | begin |
| 15755 | DispPendReq(thid); |
| 15756 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> 4th load request (pa[5:0] = 6'h30) made to gasket by LSU for blkld while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 15757 | end |
| 15758 | else |
| 15759 | begin |
| 15760 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) 4th blkld helper Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15761 | tmp[`L2_ISS] = 4'hF; |
| 15762 | end |
| 15763 | end |
| 15764 | ld_pend_array[thid] = tmp; |
| 15765 | end |
| 15766 | else if (Is_single_pcx_req_ld(inst)) |
| 15767 | begin |
| 15768 | if (tmp[`L2_ISS] == 4'hF) |
| 15769 | begin |
| 15770 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Load request made to gasket by LSU while this request has already been issued to gasket.", core_id, thid, pcx_pa); |
| 15771 | end |
| 15772 | else |
| 15773 | begin |
| 15774 | tmp[`L2_ISS] = 4'hF; |
| 15775 | ld_pend_array[thid] = tmp; |
| 15776 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA]); |
| 15777 | end |
| 15778 | end |
| 15779 | else |
| 15780 | begin |
| 15781 | DispPendReq(thid); |
| 15782 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A load request made to gasket by LSU while there is no such ld request pending from this thread.", core_id, thid, pcx_pa); |
| 15783 | end |
| 15784 | end |
| 15785 | endtask |
| 15786 | |
| 15787 | |
| 15788 | function Is_single_pcx_req_ld; |
| 15789 | input [20:0] inst; |
| 15790 | begin |
| 15791 | if (inst[`LDD] || inst[`QLD] || inst[`FSR_RD_WR] || (inst == 21'h1) || (inst == 21'h5)) |
| 15792 | Is_single_pcx_req_ld = 1'b1; |
| 15793 | else |
| 15794 | Is_single_pcx_req_ld = 1'b0; |
| 15795 | //`PR_INFO("lsu_mon", 22, "<C%0h> Is_single_pcx_req_ld = %b. ", core_id, Is_single_pcx_req_ld); |
| 15796 | end |
| 15797 | endfunction |
| 15798 | |
| 15799 | |
| 15800 | function Is_trap; |
| 15801 | input [2:0]tid; |
| 15802 | |
| 15803 | begin |
| 15804 | Is_trap = 1'b0; |
| 15805 | case (`SPC7.lsu_trap_flush[7:0]) |
| 15806 | 8'h01: if (tid == 3'h0) Is_trap = 1'b1; |
| 15807 | 8'h02: if (tid == 3'h1) Is_trap = 1'b1; |
| 15808 | 8'h04: if (tid == 3'h2) Is_trap = 1'b1; |
| 15809 | 8'h08: if (tid == 3'h3) Is_trap = 1'b1; |
| 15810 | 8'h10: if (tid == 3'h4) Is_trap = 1'b1; |
| 15811 | 8'h20: if (tid == 3'h5) Is_trap = 1'b1; |
| 15812 | 8'h40: if (tid == 3'h6) Is_trap = 1'b1; |
| 15813 | 8'h80: if (tid == 3'h7) Is_trap = 1'b1; |
| 15814 | endcase |
| 15815 | end |
| 15816 | endfunction |
| 15817 | |
| 15818 | function [8*11:0] DispPCXReq; |
| 15819 | input [129:0] pcx_pkt; |
| 15820 | begin |
| 15821 | casex ({pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS]}) |
| 15822 | {5'h0, 1'b1, 1'b0, 1'b1, 1'b0}: DispPCXReq = "PREF"; |
| 15823 | {5'h0, 1'b1, 1'b1, 1'b1, 1'b0}: DispPCXReq = "PREF_ICE"; |
| 15824 | {5'h0, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "LD"; |
| 15825 | {5'h0, 1'bx, 1'b1, 1'b0, 1'b0}: DispPCXReq = "D"; |
| 15826 | {5'h10, 1'bx, 1'b0, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 15827 | {5'h10, 1'b0, 1'b1, 1'b0, 1'b0}: DispPCXReq = "I"; |
| 15828 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b0}: DispPCXReq = "ST"; |
| 15829 | {5'h1, 1'bX, 1'bX, 1'b1, 1'b1}: DispPCXReq = "BLKST"; |
| 15830 | {5'h1, 1'bX, 1'bX, 1'b0, 1'b1}: DispPCXReq = "BIS"; |
| 15831 | {5'h2, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA1"; |
| 15832 | {5'h3, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "CASA2"; |
| 15833 | {5'h7, 1'b1, 1'bX, 1'b0, 1'b0}: DispPCXReq = "SWAP_LDSTUB"; |
| 15834 | {5'h4, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "STREAM_LD"; |
| 15835 | {5'h5, 1'b1, 1'b0, 1'b0, 1'bx}: DispPCXReq = "STREAM_ST"; |
| 15836 | {5'h8, 1'b1, 1'b0, 1'b0, 1'b0}: DispPCXReq = "MMU_LD"; |
| 15837 | //{5'h9, 1'b0, 1'b0, 1'b0, 1'b0}: DispPCXReq = "INT"; |
| 15838 | default: |
| 15839 | begin |
| 15840 | `PR_ERROR("lsu_mon", `ERROR, "<C%0h> <T%0h> <%0h> Can't recognise the PCX pkt type. rq_type = %h, nc_bit = %0b, inv_bit = %0b, pf_bit = %0b, bis_bit = %0b. pcx_pkt[129:0] = %h", core_id, pcx_pkt[`PCX_THR_ID], pcx_pkt[`PCX_ADDR], pcx_pkt[`PCX_RQTYP], pcx_pkt[`PCX_NC], pcx_pkt[`PCX_INV], pcx_pkt[`PCX_PF], pcx_pkt[`PCX_BIS], pcx_pkt); |
| 15841 | DispPCXReq = " "; |
| 15842 | end |
| 15843 | endcase |
| 15844 | end |
| 15845 | endfunction |
| 15846 | |
| 15847 | function IsExc; |
| 15848 | input [2:0] core_id; |
| 15849 | reg [21*8:0] DispExc; |
| 15850 | |
| 15851 | begin |
| 15852 | DispExc = 170'b0; |
| 15853 | IsExc = 1'b0; |
| 15854 | |
| 15855 | if (`SPC7.lsu_align_b) DispExc = "Addr_not_aligned"; |
| 15856 | if (`SPC7.lsu_lddf_align_b) DispExc = "LDDF_Addr_not_aligned"; |
| 15857 | if (`SPC7.lsu_stdf_align_b) DispExc = "STDF_Addr_not_aligned"; |
| 15858 | if (`SPC7.lsu_priv_action_b) DispExc = "Priv_actio"; |
| 15859 | if (`SPC7.lsu_va_watchpoint_b) DispExc = "VA_watchpoint"; |
| 15860 | if (`SPC7.lsu_pa_watchpoint_b) DispExc = "PA_watchpoint"; |
| 15861 | //if (`SPC7.lsu_tlb_miss_b_) DispExc = "Tlb_miss"; |
| 15862 | if (`SPC7.lsu_illegal_inst_b) DispExc = "Illegal_inst"; |
| 15863 | if (`SPC7.lsu_daccess_prot_b) DispExc = "Data_access_prot_exc"; |
| 15864 | if (`SPC7.lsu_dae_invalid_asi_b) DispExc = "Dae_Invalid_asi"; |
| 15865 | if (`SPC7.lsu_dae_nc_page_b) DispExc = "Dae_nc_page"; |
| 15866 | if (`SPC7.lsu_dae_nfo_page_b) DispExc = "Dae_NFO_page"; |
| 15867 | if (`SPC7.lsu_dae_priv_viol_b) DispExc = "Dae_Priv_viol"; |
| 15868 | if (`SPC7.lsu_dae_so_page) DispExc = "Dae_so_page"; |
| 15869 | //if (`SPC7.lsu_perfmon_trap_b) DispExc = "Perf_mon_trap"; |
| 15870 | if (`SPC7.lsu_dtmh_err_b) DispExc = "DTLB_data_par_err"; |
| 15871 | if (`SPC7.lsu_dttp_err_b) DispExc = "DTLB_tag_par_err"; |
| 15872 | if (`SPC7.lsu_dtdp_err_b) DispExc = "DTLB_data_par_err"; |
| 15873 | |
| 15874 | |
| 15875 | if (DispExc != 0) |
| 15876 | begin |
| 15877 | IsExc = 1'b1; |
| 15878 | `PR_INFO("lsu_mon", 23, "<C%0h> <T%0h> <%0h> B_stage: %s(VA=%0h) ASI = %0h. %s Exception.",core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b, asi_b, DispExc); |
| 15879 | end |
| 15880 | |
| 15881 | end |
| 15882 | endfunction |
| 15883 | |
| 15884 | function Is_exu_error; |
| 15885 | input [1:0] exu_lsu_va_error_b; // VA error requiring a flush |
| 15886 | input [1:0] exu_ecc_b; // ECC error requiring a flush |
| 15887 | reg err_b; |
| 15888 | reg err_m; |
| 15889 | |
| 15890 | begin |
| 15891 | err_b = dec_lsu_tid_b[2] ? (exu_ecc_b[1] | (exu_lsu_va_error_b[1] & ~`SPC7.lsu_tlb_bypass_b)): |
| 15892 | (exu_ecc_b[0] | (exu_lsu_va_error_b[0] & ~`SPC7.lsu_tlb_bypass_b)); |
| 15893 | |
| 15894 | err_m = (dec_lsu_tid_b[2] ? `SPC7.exu_ecc_m[1] : `SPC7.exu_ecc_m[0]) & `SPC7.lsu.dcc.twocycle_b; |
| 15895 | |
| 15896 | Is_exu_error = err_b | err_m; |
| 15897 | end |
| 15898 | endfunction |
| 15899 | |
| 15900 | /* |
| 15901 | task Insert_tlb_miss_info; |
| 15902 | reg [127:0] tmp; |
| 15903 | begin |
| 15904 | tmp = 128'b0; |
| 15905 | if (tlb_valid[dec_lsu_tid_b]) |
| 15906 | begin |
| 15907 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 15908 | Disp_tlbmiss_pend_array_entry(dec_lsu_tid_b); |
| 15909 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new tlb miss request received while there is already a Tlb miss request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 15910 | end |
| 15911 | else |
| 15912 | begin |
| 15913 | tlb_valid[dec_lsu_tid_b] <= 1'b1; |
| 15914 | tmp[`INST_VA] = inst_pc_b; |
| 15915 | tmp[`MEMOP_VA] = vaddr_b; |
| 15916 | tmp[`INST] = inst_b; |
| 15917 | end |
| 15918 | tlbmiss_pend_array[dec_lsu_tid_b] = tmp; |
| 15919 | end |
| 15920 | endtask |
| 15921 | |
| 15922 | */ |
| 15923 | |
| 15924 | //problem with the signal. |
| 15925 | /* |
| 15926 | always @ (negedge `SPC7.l2clk) |
| 15927 | begin |
| 15928 | if (mmu_dtlb_reload_d2) |
| 15929 | Chk_dtlb_reload; |
| 15930 | end |
| 15931 | |
| 15932 | task Chk_dtlb_reload; |
| 15933 | reg [2:0] thid; |
| 15934 | reg [127:0] tmp; |
| 15935 | begin |
| 15936 | if (`SPC7.tlu_trap_pc_0_valid) |
| 15937 | thid = {1'b0, `SPC7.tlu_trap_0_tid}; |
| 15938 | else if (`SPC7.tlu_trap_pc_1_valid) |
| 15939 | thid = {1'b0, `SPC7.tlu_trap_1_tid}; |
| 15940 | else |
| 15941 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> mmu_dtlb_reload asserted but trap_pc_0_valid and trap_pc_1_valid are both 0", core_id); |
| 15942 | |
| 15943 | if (~tlb_valid[thid]) |
| 15944 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> mmu_dtlb_reload asserted while tlb_valid is 0.", core_id, thid); |
| 15945 | else |
| 15946 | begin |
| 15947 | tmp = tlbmiss_pend_array[dec_lsu_tid_b]; |
| 15948 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> %s(VA=%0h> DTLB reloaded for VA = %0h.", core_id, thid, tb_top.intf0.xlate(tmp[`INST]), tmp[`INST_VA], tmp[`MEMOP_VA] ); |
| 15949 | tlb_valid[thid] = 1'b0; |
| 15950 | end |
| 15951 | end |
| 15952 | endtask |
| 15953 | */ |
| 15954 | |
| 15955 | task Insert_ld_miss_info; |
| 15956 | reg [`LD_Pend_Width] tmp; |
| 15957 | begin |
| 15958 | tmp = 213'b0; |
| 15959 | if (ld_valid[dec_lsu_tid_b]) |
| 15960 | begin |
| 15961 | tmp = ld_pend_array[dec_lsu_tid_b]; |
| 15962 | DispPendReq(dec_lsu_tid_b); |
| 15963 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> B_stage: %s(VA=%0h>) A new request received while there is already a request pending from this thread as shown above.", core_id, dec_lsu_tid_b, inst_pc_b, tb_top.intf0.xlate(inst_b),vaddr_b); |
| 15964 | end |
| 15965 | else |
| 15966 | begin |
| 15967 | //ld_valid[dec_lsu_tid_b] <= 1'b1; |
| 15968 | tmp[`INST_VA] = inst_pc_b; |
| 15969 | tmp[`MEMOP_VA] = vaddr_b; |
| 15970 | tmp[`MEMOP_PA] = {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 15971 | tmp[`INST_ASI] = asi_b; |
| 15972 | |
| 15973 | if (lsu_inst_b[`BLKLD]) |
| 15974 | begin |
| 15975 | tmp[`L2_ISS] = 4'h0; |
| 15976 | tmp[`L2_RESP] = 4'h0; |
| 15977 | is_blkld[dec_lsu_tid_b] = 1'b1; |
| 15978 | end |
| 15979 | else |
| 15980 | begin |
| 15981 | is_blkld[dec_lsu_tid_b] = 1'b0; |
| 15982 | if (lsu_inst_b[`CASA]) |
| 15983 | tmp[`L2_ISS] = 4'hC; |
| 15984 | else |
| 15985 | tmp[`L2_ISS] = 4'hE; |
| 15986 | if (lsu_inst_b[`SWAP] || lsu_inst_b[`LDSTUB] || lsu_inst_b[`CASA]) |
| 15987 | tmp[`L2_RESP] = 4'hC; |
| 15988 | else |
| 15989 | tmp[`L2_RESP] = 4'hE; |
| 15990 | |
| 15991 | end |
| 15992 | |
| 15993 | tmp[`INST] = inst_b; |
| 15994 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 15995 | ld_pend_array[dec_lsu_tid_b] = tmp; |
| 15996 | end |
| 15997 | end |
| 15998 | endtask |
| 15999 | |
| 16000 | |
| 16001 | task Insert_in_last_inst_array; |
| 16002 | reg [135:0] tmp; |
| 16003 | begin |
| 16004 | tmp = 128'b0; |
| 16005 | tmp[`INST_VA] = inst_pc_b; |
| 16006 | tmp[`MEMOP_VA] = vaddr_b; |
| 16007 | tmp[`INST] = inst_b; |
| 16008 | tmp[135:128] = asi_b; |
| 16009 | last_inst_array[dec_lsu_tid_b] = tmp; |
| 16010 | end |
| 16011 | endtask |
| 16012 | |
| 16013 | |
| 16014 | task DispPendReq; |
| 16015 | input [2:0] thid; |
| 16016 | reg [`LD_Pend_Width] tmp; |
| 16017 | begin |
| 16018 | |
| 16019 | tmp = ld_pend_array[thid]; |
| 16020 | `PR_ALWAYS("lsu_mon", `ALWAYS, "LD_PEND_ARRAY[%0h] Data.", thid); |
| 16021 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_RESP = %0h, LSU_MON_INST=%h.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ISS], tmp[`L2_RESP], tmp[`LSU_MON_INST]); |
| 16022 | end |
| 16023 | endtask |
| 16024 | |
| 16025 | task Disp_STB_entry; |
| 16026 | input [2:0] thid; |
| 16027 | input [2:0] ptr; |
| 16028 | reg [204:0] tmp; |
| 16029 | begin |
| 16030 | |
| 16031 | tmp = stb[{thid, ptr}]; |
| 16032 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> STB[%0h] data.", core_id, thid, ptr); |
| 16033 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%h> <T%0h> <%0h> %s(VA=%0h). PA = %0h. L2_ISS = %0h. L2_ACK = %0h, LSU_MON_INST=%h. RMO = %0b", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA], tmp[`MEMOP_PA], tmp[`L2_ST_ISS], tmp[`L2_ACK], tmp[`LSU_MON_INST], tmp[`RMO]); |
| 16034 | end |
| 16035 | endtask |
| 16036 | |
| 16037 | /* |
| 16038 | |
| 16039 | task Disp_tlbmiss_pend_array_entry; |
| 16040 | input [2:0] thid; |
| 16041 | reg [127:0] tmp; |
| 16042 | begin |
| 16043 | tmp = tlbmiss_pend_array[thid]; |
| 16044 | `PR_INFO("lsu_mon", 23, "TLB_MISS_PEND_ARRAY[%0h] Data.", thid); |
| 16045 | `PR_INFO("lsu_mon", 23, "<C%h> <T%0h> <%0h> %s(VA=%0h).", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]), tmp[`MEMOP_VA]); |
| 16046 | |
| 16047 | end |
| 16048 | endtask |
| 16049 | |
| 16050 | */ |
| 16051 | task Disp_CPX_pkt; |
| 16052 | input [145:0] cpx_pkt; |
| 16053 | begin |
| 16054 | `PR_ALWAYS("lsu_mon", `ALWAYS, "CPX_PKT data."); |
| 16055 | `PR_ALWAYS("lsu_mon", `ALWAYS, "<C%0h> <T%0h> rtn_typ = %0h, err_bits = %0h, nc=%0b, atm = %0b, pf = %0b", core_id, cpx_pkt[`CPX_THR_ID], cpx_pkt[`CPX_RTNTYP], cpx_pkt[`CPX_ERR], cpx_pkt[`CPX_NC], cpx_pkt[`CPX_ATM], cpx_pkt[`CPX_PF]); |
| 16056 | end |
| 16057 | endtask |
| 16058 | |
| 16059 | |
| 16060 | task Make_STB_data; |
| 16061 | reg [204:0] tmp; |
| 16062 | begin |
| 16063 | tmp = 0; |
| 16064 | tmp[`INST_VA] = inst_pc_b; |
| 16065 | tmp[`MEMOP_VA] = vaddr_b; |
| 16066 | tmp[`MEMOP_PA] = {`SPC7.lsu.tlb_pgnum[39:13], vaddr_b[12:0]}; |
| 16067 | tmp[`L2_ST_ISS] = 1'b0; |
| 16068 | tmp[`ASI_ST_ISS] = 1'b0; |
| 16069 | tmp[`L2_ACK] = 1'b0; |
| 16070 | tmp[`INST] = inst_b; |
| 16071 | tmp[`LSU_MON_INST] = lsu_inst_b; |
| 16072 | tmp[`ST_SQUASH] = 1'b0; |
| 16073 | tmp[`INST_ASI] = asi_b; |
| 16074 | if (`SPC7.lsu.tlu_lsu_hpstate_hpriv[dec_lsu_tid_b]) |
| 16075 | tmp[`ST_PRIV] = `HPRIV; |
| 16076 | else if (`SPC7.lsu.tlu_lsu_pstate_priv[dec_lsu_tid_b]) |
| 16077 | tmp[`ST_PRIV] = `PRIV; |
| 16078 | else |
| 16079 | tmp[`ST_PRIV] = `USER; |
| 16080 | //bis_asi to io space is not rmo |
| 16081 | |
| 16082 | tmp[`RMO] = lsu_inst_b[`BLKST] | (dec_altspace_b & Is_bis_asi(asi_b) & ~`SPC7.lsu.tlb_pgnum[39]); |
| 16083 | stb_alloc_data <= tmp; |
| 16084 | end |
| 16085 | endtask |
| 16086 | |
| 16087 | task Insert_in_STB; |
| 16088 | input [195:0] store_data; |
| 16089 | input [2:0] thid; |
| 16090 | begin |
| 16091 | if (stb_full(thid)) |
| 16092 | begin |
| 16093 | //DispSTB(thid); |
| 16094 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> STB full and a new store received for insertion in STB.", core_id, thid); |
| 16095 | end |
| 16096 | else |
| 16097 | begin |
| 16098 | stb[{thid, wrptr[thid]}] = store_data; |
| 16099 | //Disp_STB_entry(thid, wrptr[thid]); |
| 16100 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h> %s(VA=%0h). STB[%0h] Inserted.", core_id, thid, store_data[`INST_VA], tb_top.intf0.xlate(store_data[`INST]), store_data[`MEMOP_VA], wrptr[thid]); |
| 16101 | stb_valid[{thid, wrptr[thid]}] = 1'b1; |
| 16102 | wrptr[thid] = wrptr[thid] + 1'b1; |
| 16103 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> wrptr = %0d.", core_id, thid, wrptr[thid]); |
| 16104 | end |
| 16105 | end |
| 16106 | endtask |
| 16107 | |
| 16108 | function stb_full; |
| 16109 | input [2:0] thid; |
| 16110 | begin |
| 16111 | if ((wrptr[thid] == rdptr[thid]) && stb_valid[{thid, wrptr[thid]}]) |
| 16112 | stb_full = 1'b1; |
| 16113 | else |
| 16114 | stb_full = 1'b0; |
| 16115 | end |
| 16116 | endfunction |
| 16117 | |
| 16118 | |
| 16119 | task Dealloc_STB; |
| 16120 | input [2:0] thid; |
| 16121 | reg [204:0] tmp; |
| 16122 | reg [20:0] lsu_inst; |
| 16123 | begin |
| 16124 | //thid = decode_tid(`SPC7.lsu_stb_dealloc); |
| 16125 | tmp = stb[{thid, rdptr[thid]}]; |
| 16126 | lsu_inst = tmp[`LSU_MON_INST]; |
| 16127 | if (~stb_valid[{thid, rdptr[thid]}]) |
| 16128 | begin |
| 16129 | //DispSTB(thid); |
| 16130 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted while the stb entry is invalid for that thid.", core_id, thid, `SPC7.lsu_stb_dealloc); |
| 16131 | end |
| 16132 | if (tmp[`L2_ST_ISS]) |
| 16133 | begin |
| 16134 | if (~tmp[`L2_ACK]) |
| 16135 | begin |
| 16136 | Disp_STB_entry(thid, rdptr[thid]); |
| 16137 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted when we haven't received the response from the gasket.", core_id, thid, `SPC7.lsu_stb_dealloc); |
| 16138 | end |
| 16139 | end |
| 16140 | else if (tmp[`ASI_ST_ISS]) |
| 16141 | begin |
| 16142 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 16143 | end |
| 16144 | //blkst inst. is not issued anywhere, blkst helpers are issued. |
| 16145 | //in case of bis stores, lsu issues the dealloc in P3, i.e when the req is issued to PCX. |
| 16146 | //IF it is bis to cp sapce and there is an err then the store is issued to PCX with nd set |
| 16147 | // and deallocated. |
| 16148 | //However for ue onbis to IO space, dealloc is sent to IFU, issued on PCX with valid bit 0. |
| 16149 | //The sbdiou signal is sent in next cycle. We need to take bis io stores in this equation. |
| 16150 | else if (tmp[`ST_SQUASH] || lsu_inst[`BLKST] || (tmp[`RMO] & ~lsu_inst[`BLKST] & ~`SPC0.lsu.sbc.kill_store_p4_)) |
| 16151 | begin |
| 16152 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 16153 | ret_ptr[thid] = ret_ptr[thid] + 1'b1; |
| 16154 | end |
| 16155 | else |
| 16156 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_dealloc = %0h asserted which is not issued to asi ring, or PCX or is not squashed.", core_id, thid, `SPC7.lsu_stb_dealloc); |
| 16157 | |
| 16158 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <%0h>: %s(VA=%0h) PA = %0h. STB[%0d] Deallocated.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], tmp[`MEMOP_PA], rdptr[thid]); |
| 16159 | stb_valid[{thid, rdptr[thid]}] = 1'b0; |
| 16160 | rdptr[thid] = rdptr[thid] + 1'b1; |
| 16161 | //`PR_INFO("lsu_mon", 22, "<C%h> <T%0h> rd_ptr = %0d.", core_id, thid, rdptr[thid]); |
| 16162 | /* |
| 16163 | if (tmp[`RMO]) |
| 16164 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 16165 | */ |
| 16166 | end |
| 16167 | endtask |
| 16168 | |
| 16169 | task Squash_STB; |
| 16170 | input [2:0] thid; |
| 16171 | reg [204:0] tmp; |
| 16172 | reg [3:0] squash_cnt; |
| 16173 | reg [2:0] i; |
| 16174 | begin |
| 16175 | squash_cnt = 4'b0; |
| 16176 | if (ret_ptr[thid] != iss_ptr[thid]) |
| 16177 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the ret_ptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], ret_ptr[thid], iss_ptr[thid]); |
| 16178 | if (rdptr[thid] != iss_ptr[thid]) |
| 16179 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the rdptr = %0h != iss_ptr = %0h.", core_id, thid, tmp[`MEMOP_PA], rdptr[thid], iss_ptr[thid]); |
| 16180 | |
| 16181 | if (iss_ptr[thid] == wrptr[thid]) |
| 16182 | begin |
| 16183 | if (stb_valid[{thid, wrptr[thid]}]) |
| 16184 | squash_cnt = 8; |
| 16185 | /* Lsu can assert both dealloc and block_store_kill for a request. |
| 16186 | * |
| 16187 | else |
| 16188 | begin |
| 16189 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Lsu asserted block_store_kill while there are no valid entries in STB to be deallocated.", core_id, thid); |
| 16190 | end |
| 16191 | */ |
| 16192 | end |
| 16193 | else |
| 16194 | begin |
| 16195 | if (iss_ptr[thid] < wrptr[thid]) |
| 16196 | squash_cnt = wrptr[thid] - iss_ptr[thid]; |
| 16197 | else if (iss_ptr[thid] > wrptr[thid]) |
| 16198 | squash_cnt = wrptr[thid] + (8 - iss_ptr[thid]); |
| 16199 | end |
| 16200 | |
| 16201 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> SQUASH_STB:iss_ptr = %0h, wrptr = %0h, squash_cnt = %0h.", core_id, thid, iss_ptr[thid], wrptr[thid], squash_cnt); |
| 16202 | |
| 16203 | i = iss_ptr[thid]; |
| 16204 | |
| 16205 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> Block store kill changed issue_ptr:%0h->%0h. ret_ptr: %0h->%0h. rdptr:%0h->%0h.", core_id, thid, iss_ptr[thid], iss_ptr[thid]+squash_cnt, ret_ptr[thid], ret_ptr[thid]+squash_cnt, rdptr[thid], rdptr[thid]+squash_cnt); |
| 16206 | |
| 16207 | ret_ptr[thid] = ret_ptr[thid] + squash_cnt; |
| 16208 | rdptr[thid] = rdptr[thid] + squash_cnt; |
| 16209 | iss_ptr[thid] = iss_ptr[thid] + squash_cnt; |
| 16210 | |
| 16211 | while (squash_cnt) |
| 16212 | begin |
| 16213 | tmp = stb[{thid, i}]; |
| 16214 | if (~stb_valid[{thid, i}]) |
| 16215 | begin |
| 16216 | //DispSTB(thid); |
| 16217 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h><PA = %0h> lsu_block_store_kill asserted while the stb entry %0h is invalid.", core_id, thid, tmp[`MEMOP_PA], i); |
| 16218 | end |
| 16219 | if (tmp[`L2_ST_ISS]) |
| 16220 | begin |
| 16221 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h>st_issue bit is set when the block_store_kill is asserted for stb entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 16222 | end |
| 16223 | //commenting out the chk below. Lsu can assert sbdiou and then in the next cycle insert a new entry into |
| 16224 | //stb. LSU will squash this new entry and won't issue it to PCX/asi but its squash bit won't be |
| 16225 | //set in the chkr which was causin it to fire. |
| 16226 | //if (~tmp[`ST_SQUASH]) |
| 16227 | //begin |
| 16228 | //`PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> lsu_block_store_kill asserted while the squash bit is 0 in the STB entry %0h.", core_id, thid, tmp[`MEMOP_PA], i); |
| 16229 | //end |
| 16230 | stb_valid[{thid, i}] = 1'b0; |
| 16231 | |
| 16232 | i = i + 1; |
| 16233 | squash_cnt = squash_cnt - 1'b1; |
| 16234 | end |
| 16235 | |
| 16236 | end |
| 16237 | endtask |
| 16238 | |
| 16239 | task Chk_store; |
| 16240 | reg [2:0] thid; |
| 16241 | reg [47:0] addr; |
| 16242 | reg [3:0] i; |
| 16243 | reg [204:0] tmp; |
| 16244 | begin |
| 16245 | if ((bst_cnt > 0) && (`SPC7.lsu_stb_alloc == 8'b0)) |
| 16246 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> Blk store entries are not allocated back to back in STB.", core_id, bst_active_thid); |
| 16247 | |
| 16248 | //For bst the stb is still written even though we have errors. |
| 16249 | //Stb is written in W stage. Howvere for first blk store helper |
| 16250 | //the err will be flagged by FGU in b stage. We can miss the |
| 16251 | // err signal if we don't sample in B. |
| 16252 | //for the last helper err will be signalled in B stage of last helper and at |
| 16253 | |
| 16254 | if (lsu_bst_active[bst_active_thid] & `SPC0.fgu_fst_ecc_error_fx2 & (bst_cnt < 7)) |
| 16255 | bst_fgu_err = 1'b1; |
| 16256 | |
| 16257 | if (`SPC7.lsu_stb_alloc[7:0] != 8'b0) |
| 16258 | begin |
| 16259 | thid = decode_tid(`SPC7.lsu_stb_alloc[7:0]); |
| 16260 | if (store_alloc) |
| 16261 | begin |
| 16262 | if (thid != dec_lsu_tid_w) |
| 16263 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the thid %0h.", core_id, dec_lsu_tid_w, `SPC7.lsu_stb_alloc[7:0], dec_lsu_tid_w); |
| 16264 | Insert_in_STB(stb_alloc_data, dec_lsu_tid_w); |
| 16265 | end |
| 16266 | else |
| 16267 | begin |
| 16268 | if (lsu_bst_active[thid]) |
| 16269 | begin |
| 16270 | if (bst_cnt == 0) |
| 16271 | begin |
| 16272 | bst_data = bst_inst_data; |
| 16273 | end |
| 16274 | else |
| 16275 | begin |
| 16276 | if (thid != bst_active_thid) |
| 16277 | begin |
| 16278 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> lsu_stb_alloc = %0h mismatches the active blkstore thid = %0h.", core_id, bst_active_thid, `SPC7.lsu_stb_alloc[7:0], bst_active_thid); |
| 16279 | end |
| 16280 | |
| 16281 | addr = bst_data[`MEMOP_VA]; |
| 16282 | |
| 16283 | bst_data[`MEMOP_VA] = {addr[47:6], bst_cnt[2:0], 3'b0}; |
| 16284 | addr = bst_data[`MEMOP_PA]; |
| 16285 | bst_data[`MEMOP_PA] = {addr[39:6], bst_cnt[2:0], 3'b0}; |
| 16286 | end |
| 16287 | bst_cnt = bst_cnt + 1; |
| 16288 | Insert_in_STB(bst_data, bst_active_thid); |
| 16289 | if (bst_cnt == 8) |
| 16290 | begin |
| 16291 | bst_cnt = 0; |
| 16292 | lsu_bst_active[thid] = 1'b0; |
| 16293 | if (bst_fgu_err) //set the squash bit to 0 for all the stb entries |
| 16294 | begin |
| 16295 | for (i = 0; i < 8; i=i+1) |
| 16296 | begin |
| 16297 | tmp = stb[{thid, i[2:0]}]; |
| 16298 | if (tmp[`ST_SQUASH]) |
| 16299 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Squash bit already set when trying to set it for a bst fgu errerr.", core_id, thid, tmp[`MEMOP_PA]); |
| 16300 | tmp[`ST_SQUASH] = 1'b1; |
| 16301 | stb[{thid, i[2:0]}] = tmp; |
| 16302 | `PR_INFO("lsu_mon", 22, "<C%h> <T%0h> <PA = %0h> STB_entry[%0h] squashed due to FGU err.", core_id, thid, tmp[`MEMOP_PA], i); |
| 16303 | end |
| 16304 | end |
| 16305 | bst_fgu_err = 1'b0; |
| 16306 | end |
| 16307 | end |
| 16308 | else |
| 16309 | `PR_ERROR("lsu_mon", `ERROR, "<C%h>: LSU asserted lsu_stb_alloc = %0h while no store pending to be written in STB.", core_id, `SPC7.lsu_stb_alloc[7:0]); |
| 16310 | |
| 16311 | end |
| 16312 | end |
| 16313 | else |
| 16314 | begin |
| 16315 | if (store_alloc) |
| 16316 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h> W_stage: LSU did not assert lsu_stb_alloc for the store.", core_id, dec_lsu_tid_w, inst_pc_w); |
| 16317 | end |
| 16318 | end |
| 16319 | endtask |
| 16320 | |
| 16321 | task Chk_st_on_ASI_ring; |
| 16322 | input ring; |
| 16323 | reg [2:0] thid; |
| 16324 | reg [7:0] asi; |
| 16325 | reg [47:0] addr, act_addr; |
| 16326 | reg [1:0] req_type; |
| 16327 | reg [204:0] tmp; |
| 16328 | |
| 16329 | begin |
| 16330 | if (ring == `LOCAL) |
| 16331 | thid =`SPC7.lsu_rngl_cdbus[58:56]; |
| 16332 | else |
| 16333 | thid =`SPC7.lsu_rngf_cdbus[58:56]; |
| 16334 | |
| 16335 | if (ring == `LOCAL) |
| 16336 | asi =`SPC7.lsu_rngl_cdbus[55:48]; |
| 16337 | else |
| 16338 | asi =`SPC7.lsu_rngf_cdbus[55:48]; |
| 16339 | |
| 16340 | if (ring == `LOCAL) |
| 16341 | addr =`SPC7.lsu_rngl_cdbus[47:0]; |
| 16342 | else |
| 16343 | addr =`SPC7.lsu_rngf_cdbus[47:0]; |
| 16344 | |
| 16345 | if (ring == `LOCAL) |
| 16346 | req_type =`SPC7.lsu_rngl_cdbus[61:60]; |
| 16347 | else |
| 16348 | req_type =`SPC7.lsu_rngf_cdbus[61:60]; |
| 16349 | |
| 16350 | |
| 16351 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 16352 | if (tmp[`ASI_ST_ISS]) |
| 16353 | begin |
| 16354 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16355 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the ASI interface.", core_id, thid, addr); |
| 16356 | end |
| 16357 | |
| 16358 | if (tmp[`ST_SQUASH]) |
| 16359 | begin |
| 16360 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16361 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the ASI interface that has been squashed.", core_id, thid, addr); |
| 16362 | end |
| 16363 | |
| 16364 | act_addr = tmp[`MEMOP_PA]; |
| 16365 | act_addr = {act_addr[39:3], 3'b0}; |
| 16366 | |
| 16367 | //47 is D tag rd asi. LSU issues that on the ring but changes |
| 16368 | //the address. |
| 16369 | if ((addr == act_addr) || (asi == 8'h47) || (asi == 8'h46)) |
| 16370 | begin |
| 16371 | tmp[`ASI_ST_ISS] = 1'b1; |
| 16372 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 16373 | if (ring == `LOCAL) |
| 16374 | begin |
| 16375 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on local ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 16376 | end |
| 16377 | else |
| 16378 | begin |
| 16379 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued on fast ring.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 16380 | end |
| 16381 | iss_ptr[thid] = iss_ptr[thid] + 1'b1; |
| 16382 | end |
| 16383 | else |
| 16384 | begin |
| 16385 | if (ring == `LOCAL) |
| 16386 | begin |
| 16387 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on local ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 16388 | end |
| 16389 | else |
| 16390 | begin |
| 16391 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] PA mismatch for asi req on fast ring. Expected PA = %0h, actual PA = %0h", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid], tmp[`MEMOP_PA], addr); |
| 16392 | end |
| 16393 | end |
| 16394 | |
| 16395 | end |
| 16396 | endtask |
| 16397 | |
| 16398 | |
| 16399 | task chk_store_issue_to_pcx; |
| 16400 | input [129:0] pcx_pkt; |
| 16401 | reg [2:0] thid; |
| 16402 | reg [204:0] tmp; |
| 16403 | reg [20:0] inst; |
| 16404 | reg [39:0] pcx_pa, inst_pa; |
| 16405 | begin |
| 16406 | thid = pcx_pkt[`PCX_THR_ID]; |
| 16407 | tmp = stb[{thid, iss_ptr[thid]}]; |
| 16408 | inst = tmp[`LSU_MON_INST]; |
| 16409 | pcx_pa = pcx_pkt[`PCX_ADDR]; |
| 16410 | inst_pa = tmp[`MEMOP_PA]; |
| 16411 | |
| 16412 | if (pcx_pkt[`PCX_RQTYP] == `PCX_STORE) |
| 16413 | begin |
| 16414 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 16415 | end |
| 16416 | if (pcx_pkt[`PCX_INV]) |
| 16417 | `PR_INFO("lsu_mon", 25, "<C%h> <T%0h> <%0h>: %s(VA=%0h) STB[%0d] Issued to gasket with ND set.", core_id, thid, tmp[`INST_VA], tb_top.intf0.xlate(tmp[`INST]),tmp[`MEMOP_VA], iss_ptr[thid]); |
| 16418 | |
| 16419 | |
| 16420 | if (~inst[`ST]) |
| 16421 | begin |
| 16422 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16423 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req is not store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16424 | end |
| 16425 | |
| 16426 | /* CONFIRM WITH MARK |
| 16427 | if (pcx_pa[39:0] != inst_pa[39:0]) |
| 16428 | begin |
| 16429 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16430 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> A store request made to gasket by LSU while the pending req has PA %0h.", core_id, thid, pcx_pkt[`PCX_ADDR], tmp[`MEMOP_PA]); |
| 16431 | end |
| 16432 | */ |
| 16433 | //enhancement req 100146 |
| 16434 | if ((tmp[`INST_ASI] == 8'h73) & (pcx_pa[39:0] != {8'h90, core_id, thid, tmp[`INST_ASI], 18'h0})) |
| 16435 | begin |
| 16436 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> pcx_pa is not correct for asi write to interrupt vector dispatch register.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16437 | end |
| 16438 | |
| 16439 | if (inst[`BLKST] && ~pcx_pkt[`PCX_BST]) |
| 16440 | begin |
| 16441 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16442 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Bst bit is not set in the PCX pkt by LSU for a blk st request.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16443 | end |
| 16444 | |
| 16445 | if (tmp[`L2_ST_ISS]) |
| 16446 | begin |
| 16447 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16448 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store reissued on the PCX interface.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16449 | end |
| 16450 | else |
| 16451 | tmp[`L2_ST_ISS] = 1'b1; |
| 16452 | |
| 16453 | if (tmp[`ST_SQUASH]) |
| 16454 | begin |
| 16455 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16456 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> Store issued on the PCX interface that has been squashed.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16457 | end |
| 16458 | |
| 16459 | if (tmp[`RMO]) |
| 16460 | begin |
| 16461 | if (~pcx_pkt[`PCX_BIS]) |
| 16462 | begin |
| 16463 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16464 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> BIS bit is not set in the PCX pkt by LSU for an RMO store.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16465 | end |
| 16466 | if (tmp[`L2_ACK]) |
| 16467 | begin |
| 16468 | Disp_STB_entry(thid, iss_ptr[thid]); |
| 16469 | `PR_ERROR("lsu_mon", `ERROR, "<C%h> <T%0h> <PA = %0h> L2ack bit is set when the RMO store is issued to PCX.", core_id, thid, pcx_pkt[`PCX_ADDR]); |
| 16470 | end |
| 16471 | else |
| 16472 | begin |
| 16473 | tmp[`L2_ACK] = 1'b1; |
| 16474 | ret_ptr[thid] = ret_ptr[thid] + 1; //this will be deallocated before |
| 16475 | //response seen from stub |
| 16476 | st_rmo_cnt[thid] = st_rmo_cnt[thid] + 1'b1; |
| 16477 | end |
| 16478 | end |
| 16479 | stb[{thid, iss_ptr[thid]}] = tmp; |
| 16480 | |
| 16481 | iss_ptr[thid] = iss_ptr[thid] + 1; |
| 16482 | `PR_INFO("lsu_mon", 20, "<C%h> <T%0h> iss_ptr = %0d. ret_ptr = %0d, st_rmo_cnt = %0d", core_id, thid, iss_ptr[thid], ret_ptr[thid], st_rmo_cnt[thid]); |
| 16483 | end |
| 16484 | endtask |
| 16485 | |
| 16486 | `ifdef INJ_STB_ERR_IN_CMP |
| 16487 | |
| 16488 | |
| 16489 | reg [2:0] err_tid, stb_err_tid_d1, stb_err_tid_d2; |
| 16490 | reg [2:0] err_index, stb_err_index_d1, stb_err_index_d2; |
| 16491 | reg [204:0] err_tmp ; |
| 16492 | reg [20:0] err_inst; |
| 16493 | reg [44:0] cam_data; |
| 16494 | reg [5:0] err_bit; |
| 16495 | integer err_inj_cnt; |
| 16496 | reg cmp_stb_err_inj; |
| 16497 | reg stb_err_inj, stb_err_inj_d1, stb_err_inj_d2; |
| 16498 | reg [1:0] err_priv, stb_err_priv_d1, stb_err_priv_d2; |
| 16499 | |
| 16500 | initial |
| 16501 | begin |
| 16502 | cmp_stb_err_inj = 1'b0; |
| 16503 | |
| 16504 | cam_data = 45'b0; |
| 16505 | err_bit = 11; |
| 16506 | err_inj_cnt = 0; |
| 16507 | stb_err_inj = 0; |
| 16508 | if (("cmp_stb_err_inj_on")) |
| 16509 | cmp_stb_err_inj = 1'b1; |
| 16510 | else |
| 16511 | cmp_stb_err_inj = 1'b0; |
| 16512 | end |
| 16513 | |
| 16514 | always @ (negedge (`SPC7.l2clk & enabled & cmp_stb_err_inj)) |
| 16515 | begin //{ |
| 16516 | //valid stb ram rd for issue to pcx |
| 16517 | stb_err_inj = 1'b0; |
| 16518 | if (`SPC7.lsu.sbc.ram_rptr_vld_2 & `SPC7.lsu.sbc.st_pcx_rq_p3 & `SPC7.lsu.pic.pic_st_sel_p3) |
| 16519 | begin //{ |
| 16520 | err_tid = decode_tid(`SPC7.lsu.sbc.st_rq_sel_p3[7:0]); |
| 16521 | err_index = `SPC7.lsu.sbc.ram_rptr_d1; |
| 16522 | err_tmp = stb[{err_tid, err_index}]; |
| 16523 | err_inst = err_tmp[`LSU_MON_INST]; |
| 16524 | cam_data = `SPC7.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 16525 | err_priv = err_tmp[`ST_PRIV]; |
| 16526 | //if (err_inst[`SWAP] || err_inst[`CASA] || err_inst[`LDSTUB]) |
| 16527 | if (err_inst[`CASA]) |
| 16528 | begin //{ |
| 16529 | err_inj_cnt = err_inj_cnt + 1; |
| 16530 | if (err_inj_cnt == 10) |
| 16531 | begin //{ |
| 16532 | case (err_bit) |
| 16533 | 11, 12: err_bit = err_bit + 1; |
| 16534 | 13: err_bit = 44; |
| 16535 | 44: err_bit = 11; |
| 16536 | endcase |
| 16537 | err_inj_cnt = 0; |
| 16538 | stb_err_inj = 1'b1; |
| 16539 | |
| 16540 | force `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0] = cam_data ^ (1 << err_bit); |
| 16541 | `PR_INFO("stb_err", 22, "<T%0h> <%0h> STB[%0h]: SBAPP forced for CASA. err_bit = %0h", err_tid, {cam_data[44:8], 3'b0}, err_index, err_bit); |
| 16542 | #1; |
| 16543 | release `SPC0.lsu.stb_cam.cam_array.stb_rdata[44:0]; |
| 16544 | end //} |
| 16545 | end //} |
| 16546 | end //} |
| 16547 | if (stb_err_inj_d2) |
| 16548 | begin |
| 16549 | if (~`SPC7.lsu_sbapp_err_g) |
| 16550 | begin |
| 16551 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err not asserted when err is injected for atomic.", stb_err_tid_d2); |
| 16552 | end |
| 16553 | else |
| 16554 | begin |
| 16555 | if ((`SPC7.lsu_stberr_tid_g != stb_err_tid_d2) || |
| 16556 | (`SPC7.lsu_stberr_index_g != stb_err_index_d2) || |
| 16557 | (`SPC7.lsu_stberr_priv_g != stb_err_priv_d2)) |
| 16558 | begin |
| 16559 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err parameters mismatch.", stb_err_tid_d2); |
| 16560 | end |
| 16561 | end |
| 16562 | end |
| 16563 | else |
| 16564 | begin |
| 16565 | if (`SPC7.lsu_sbapp_err_g) |
| 16566 | begin |
| 16567 | `PR_ERROR("lsu_mon", `ERROR, "<T%0h> sbapp err asserted when none expected.", `SPC7.lsu_stberr_tid_g); |
| 16568 | end |
| 16569 | end |
| 16570 | |
| 16571 | end //} |
| 16572 | |
| 16573 | |
| 16574 | always @ (posedge (`SPC7.l2clk & enabled & cmp_stb_err_inj)) |
| 16575 | begin |
| 16576 | stb_err_inj_d1 <= stb_err_inj; |
| 16577 | stb_err_inj_d2 <= stb_err_inj_d1; |
| 16578 | stb_err_tid_d1 <= err_tid; |
| 16579 | stb_err_tid_d2 <= stb_err_tid_d1; |
| 16580 | stb_err_index_d1 <= err_index; |
| 16581 | stb_err_index_d2 <= stb_err_index_d1; |
| 16582 | stb_err_priv_d1 <= err_priv; |
| 16583 | stb_err_priv_d2 <= stb_err_priv_d1; |
| 16584 | end |
| 16585 | |
| 16586 | `endif |
| 16587 | `endif |
| 16588 | `endif |
| 16589 | endmodule |
| 16590 | |
| 16591 | `endif |
| 16592 | //---------------------------------------------------------- |
| 16593 | //---------------------------------------------------------- |
| 16594 | |
| 16595 | |
| 16596 | |
| 16597 | |
| 16598 | |
| 16599 | |
| 16600 | |