| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: axis_tlb_mon.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifdef CORE_0 |
| 36 | |
| 37 | module itlb_wr_c0 (dbg_in); |
| 38 | `ifndef GATESIM |
| 39 | |
| 40 | parameter NUM_TLB=64; |
| 41 | |
| 42 | wire [7:0] data_in; |
| 43 | wire [7:0] tlb_wr; |
| 44 | wire wr_en; |
| 45 | wire [7:0] entry; |
| 46 | wire [3:0] demap; |
| 47 | reg [3:0] demap_1; |
| 48 | wire demap_page; |
| 49 | wire demap_context; |
| 50 | wire demap_real; |
| 51 | wire demap_all; |
| 52 | wire skip_demap; |
| 53 | wire demap_active; |
| 54 | wire auto_demap; |
| 55 | wire [2:0] demap_tid; |
| 56 | reg [2:0] demap_tid_1; |
| 57 | reg [5:0] demap_tnum_1; |
| 58 | wire [7:0] asi_wr_itlb; |
| 59 | wire [7:0] asi_wr_itlb_demap; |
| 60 | wire [7:0] asi_wr_itlb_data_in; |
| 61 | wire [7:0] asi_wr_itlb_data_access; |
| 62 | input dbg_in; |
| 63 | |
| 64 | reg [(`TS_WIDTH-1):0] tstamp; |
| 65 | reg [7:0] data_in_ready; |
| 66 | reg hwtw; |
| 67 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 68 | reg dbg_en; |
| 69 | |
| 70 | reg [2:0] mytid; |
| 71 | reg [5:0] mytnum; |
| 72 | wire [2:0] mycid; |
| 73 | integer junk; |
| 74 | integer i; |
| 75 | reg [7:0] cnt; |
| 76 | |
| 77 | assign mycid = 0; |
| 78 | |
| 79 | //---------------------------------------------------------- |
| 80 | // Instantiate fifo - 1 entry per thread |
| 81 | //fifo fifo (); |
| 82 | // Define fifo parameters |
| 83 | `ifndef PALLADIUM |
| 84 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 85 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 86 | defparam fifo.PTR_BITS = 4; |
| 87 | `endif |
| 88 | |
| 89 | //---------------------------------------------------------- |
| 90 | // DUT probes |
| 91 | |
| 92 | assign data_in = `SPC0.mmu.asi.htc_wr_itlb_data_in; |
| 93 | assign wr_en = `SPC0.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 94 | |
| 95 | assign entry = `SPC0.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 96 | |
| 97 | assign demap_page = `SPC0.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 98 | assign demap_context = `SPC0.ifu_ftu.itc_demap_context; |
| 99 | assign demap_real = `SPC0.ifu_ftu.itc_demap_real; |
| 100 | assign demap_all = `SPC0.ifu_ftu.itc_demap_all; |
| 101 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 102 | assign skip_demap = `SPC0.ifu_ftu.itc_wr_u_en; |
| 103 | assign demap_tid = `SPC0.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 104 | |
| 105 | |
| 106 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 107 | assign demap_active = |demap_1 && !skip_demap; |
| 108 | assign auto_demap = |demap_1 && skip_demap; |
| 109 | wire [7:0] itlb_wr = {(`SPC0.tlu.trl1.take_itw & `SPC0.tlu.trl1.trap[3]), |
| 110 | (`SPC0.tlu.trl1.take_itw & `SPC0.tlu.trl1.trap[2]), |
| 111 | (`SPC0.tlu.trl1.take_itw & `SPC0.tlu.trl1.trap[1]), |
| 112 | (`SPC0.tlu.trl1.take_itw & `SPC0.tlu.trl1.trap[0]), |
| 113 | (`SPC0.tlu.trl0.take_itw & `SPC0.tlu.trl0.trap[3]), |
| 114 | (`SPC0.tlu.trl0.take_itw & `SPC0.tlu.trl0.trap[2]), |
| 115 | (`SPC0.tlu.trl0.take_itw & `SPC0.tlu.trl0.trap[1]), |
| 116 | (`SPC0.tlu.trl0.take_itw & `SPC0.tlu.trl0.trap[0]) |
| 117 | }; |
| 118 | |
| 119 | assign tlb_wr = itlb_wr; |
| 120 | |
| 121 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 122 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 123 | // These signals assert before the MMU reorders the TLB writes. |
| 124 | // Use these to suppress SSTEP in nas_pipe. |
| 125 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 126 | assign asi_wr_itlb_demap = `SPC0.mmu.asi_wr_immu_demap; |
| 127 | assign asi_wr_itlb_data_in = `SPC0.mmu.asi_wr_itlb_data_in; |
| 128 | assign asi_wr_itlb_data_access = {`SPC0.mmu.asd1.asi_wr_itlb_data_access, |
| 129 | `SPC0.mmu.asd0.asi_wr_itlb_data_access}; |
| 130 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 131 | |
| 132 | //--------------------- |
| 133 | // Probes for debugging |
| 134 | |
| 135 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 136 | |
| 137 | // n2_tlb_tl_64x59_cam.sv |
| 138 | |
| 139 | `define CNTX1_HI 65 |
| 140 | `define CNTX1_LO 53 |
| 141 | `define PID_HI 52 |
| 142 | `define PID_LO 50 |
| 143 | `define REAL_BIT 49 |
| 144 | `define VA_47 48 |
| 145 | `define VA_28 29 |
| 146 | `define VA_27 28 |
| 147 | `define VA_22 23 |
| 148 | `define TTE_VALID 22 |
| 149 | `define VA_21 21 |
| 150 | `define VA_16 16 |
| 151 | `define VA_15 15 |
| 152 | `define VA_13 13 |
| 153 | `define CNTX0_HI 12 |
| 154 | `define CNTX0_LO 0 |
| 155 | |
| 156 | // n2_tlb_tl_64x59_ram.sv |
| 157 | |
| 158 | `define DATA_PARITY 36 |
| 159 | `define DATA_PA_39_28_HI 35 |
| 160 | `define DATA_PA_39_28_LO 24 |
| 161 | `define DATA_PA_27_22_HI 23 |
| 162 | `define DATA_PA_27_22_LO 18 |
| 163 | `define DATA_VA_27_22_V 17 |
| 164 | `define DATA_PA_21_16_HI 16 |
| 165 | `define DATA_PA_21_16_LO 11 |
| 166 | `define DATA_VA_21_16_V 10 |
| 167 | `define DATA_PA_15_13_HI 9 |
| 168 | `define DATA_PA_15_13_LO 7 |
| 169 | `define DATA_VA_15_13_V 6 |
| 170 | `define DATA_NFO 5 |
| 171 | `define DATA_IE 4 |
| 172 | `define DATA_CP 3 |
| 173 | `define DATA_X 2 |
| 174 | `define DATA_P 1 |
| 175 | `define DATA_W 0 |
| 176 | |
| 177 | wire [(NUM_TLB-1):0] tlb_valid; |
| 178 | wire [(NUM_TLB-1):0] tlb_match; |
| 179 | wire tte_valid; |
| 180 | wire [47:0] tte_va; |
| 181 | wire [12:0] tte_context; |
| 182 | wire tte_real; |
| 183 | wire [2:0] tte_pid; |
| 184 | wire [2:0] tte_page_mask; |
| 185 | wire [39:0] tte_pa; |
| 186 | wire tte_nfo; |
| 187 | wire tte_ie; |
| 188 | wire tte_cp; |
| 189 | wire tte_e; |
| 190 | wire tte_p; |
| 191 | wire tte_w; |
| 192 | wire tte_ep; |
| 193 | |
| 194 | assign tlb_valid = `SPC0.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 195 | assign tlb_match = `SPC0.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 196 | |
| 197 | assign tte_va = {`SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 198 | `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 199 | `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 200 | `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 201 | 13'b0 |
| 202 | }; |
| 203 | assign tte_context = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 204 | assign tte_pid = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 205 | assign tte_real = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 206 | assign tte_valid = `SPC0.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 207 | |
| 208 | assign tte_page_mask = `SPC0.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 209 | |
| 210 | assign tte_pa = {`SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 211 | `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 212 | `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 213 | `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 214 | 13'b0 |
| 215 | }; |
| 216 | assign tte_nfo = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 217 | assign tte_ie = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 218 | assign tte_cp = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 219 | assign tte_e = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 220 | assign tte_p = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 221 | assign tte_w = `SPC0.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 222 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 223 | |
| 224 | //---------------------------------------------------------- |
| 225 | initial begin // { |
| 226 | `ifndef PALLADIUM |
| 227 | #1; |
| 228 | `endif |
| 229 | hwtw = 1'b0; |
| 230 | data_in_ready = 8'b0; |
| 231 | end // } |
| 232 | |
| 233 | //---------------------------------------------------------- |
| 234 | // Must use negedge to avoid race condition |
| 235 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 236 | |
| 237 | always @ (negedge `CPU.l2clk) begin // { |
| 238 | |
| 239 | tstamp = `TOP.cycle; |
| 240 | demap_tstamp = `TOP.cycle; |
| 241 | |
| 242 | // Delay by 1 cycle to align with skip_demap |
| 243 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 244 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 245 | demap_1 <= demap; |
| 246 | |
| 247 | |
| 248 | //---------------------------------------------------------- |
| 249 | // Send I/DTLBWRITE due to demap |
| 250 | // |
| 251 | |
| 252 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 253 | $display("tlb_sync", `ERROR, |
| 254 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 255 | mycid,demap_tid_1); |
| 256 | end // } |
| 257 | |
| 258 | //if (demap_active) begin // { |
| 259 | // fifo.pop_fifo ({hwtw,mytid}); |
| 260 | //end |
| 261 | //-------------------- |
| 262 | if (dbg_in & (|demap_1)) begin // { |
| 263 | begin // axis tbcall_region |
| 264 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 265 | end |
| 266 | |
| 267 | if (demap_active) begin |
| 268 | begin // axis tbcall_region |
| 269 | case (demap_1) |
| 270 | 4'b0001: $write ("type=real "); |
| 271 | 4'b0010: $write ("type=cntx "); |
| 272 | 4'b0100: $write ("type=page "); |
| 273 | 4'b1000: $write ("type=all "); |
| 274 | default: |
| 275 | $display ("tlb_sync", `ERROR, |
| 276 | "Bench Problem - demap_1() should be one-hot."); |
| 277 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 278 | endcase |
| 279 | end |
| 280 | end |
| 281 | else begin |
| 282 | begin // axis tbcall_region |
| 283 | $write("type=autodemap "); |
| 284 | end |
| 285 | end |
| 286 | |
| 287 | begin // axis tbcall_region |
| 288 | $display ("match=%h ts=%0d", |
| 289 | tlb_match,demap_tstamp*`TOP.core_period); |
| 290 | end |
| 291 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 292 | if (tlb_match[cnt]==1'b1) begin // { |
| 293 | begin // axis tbcall_region |
| 294 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 295 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 296 | end |
| 297 | end // } |
| 298 | end // } |
| 299 | |
| 300 | end // } |
| 301 | |
| 302 | //---------------------------------------------------------- |
| 303 | // Send I/DHWTW due to HWTW |
| 304 | // Send I/DTLBWRITE due to ASI write |
| 305 | |
| 306 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 307 | // These signals will be interleaved between the threads. |
| 308 | // Need to queue up the signals over time so they can be processed in order. |
| 309 | // Each thread will only be doing 1 thing at a time. |
| 310 | |
| 311 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 312 | |
| 313 | for (i=0;i<=7;i=i+1) begin // { |
| 314 | |
| 315 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 316 | $display ("tlb_sync", `ERROR, |
| 317 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 318 | end // } |
| 319 | else begin // { |
| 320 | |
| 321 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 322 | if (data_in[i]) begin // { |
| 323 | data_in_ready[i] <= 1'b1; |
| 324 | end // } |
| 325 | |
| 326 | // tlb_wr[tid] determines which thread will write next |
| 327 | // Use fifo to save the tids of the tlb_wr signals in order |
| 328 | if (tlb_wr[i]) begin // { |
| 329 | if (data_in_ready[i]) begin // { |
| 330 | hwtw <= 1'b1; |
| 331 | mytid[2:0] <= i[2:0]; |
| 332 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 333 | data_in_ready[i] <= 1'b0; |
| 334 | end // } |
| 335 | else begin // { |
| 336 | hwtw <= 1'b0; |
| 337 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 338 | mytid[2:0] <= i[2:0]; |
| 339 | end // } |
| 340 | end // } |
| 341 | |
| 342 | end // if} |
| 343 | end // for} |
| 344 | |
| 345 | end // if} |
| 346 | |
| 347 | //---------------------------------------------------------- |
| 348 | // wr_en means that the write is occurring |
| 349 | if (wr_en) begin // { |
| 350 | //fifo.pop_fifo ({hwtw,mytid}); |
| 351 | mytnum = (mycid * 8) + mytid; |
| 352 | |
| 353 | //-------------------- |
| 354 | if (dbg_in) begin // { |
| 355 | begin // axis tbcall_region |
| 356 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 357 | end |
| 358 | |
| 359 | begin // axis tbcall_region |
| 360 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 361 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 362 | end |
| 363 | |
| 364 | begin // axis tbcall_region |
| 365 | case (tte_page_mask) |
| 366 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 367 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 368 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 369 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 370 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 371 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 372 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 373 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 374 | endcase |
| 375 | |
| 376 | if (hwtw) $display (" (hwtw)"); |
| 377 | else $display (""); |
| 378 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 379 | |
| 380 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 381 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 382 | end |
| 383 | end // } |
| 384 | //-------------------- |
| 385 | |
| 386 | end // } |
| 387 | |
| 388 | end // always} |
| 389 | |
| 390 | `endif |
| 391 | //---------------------------------------------------------- |
| 392 | endmodule |
| 393 | |
| 394 | module dtlb_wr_c0 (dbg_in); |
| 395 | `ifndef GATESIM |
| 396 | |
| 397 | parameter NUM_TLB=128; |
| 398 | |
| 399 | wire [7:0] data_in; |
| 400 | wire [7:0] tlb_wr; |
| 401 | wire wr_en; |
| 402 | wire [7:0] entry; |
| 403 | wire [7:0] asi_num; |
| 404 | wire asi_enable0; // 1 per thread group |
| 405 | wire asi_enable1; |
| 406 | // wire [7:0] store_asi; // 1 per thread |
| 407 | wire [3:0] demap; |
| 408 | reg [3:0] demap_1; |
| 409 | wire demap_page; |
| 410 | wire demap_context; |
| 411 | wire demap_real; |
| 412 | wire demap_all; |
| 413 | wire skip_demap; |
| 414 | wire demap_active; |
| 415 | wire auto_demap; |
| 416 | wire [2:0] demap_tid; |
| 417 | reg [2:0] demap_tid_1; |
| 418 | reg [5:0] demap_tnum_1; |
| 419 | input dbg_in; |
| 420 | |
| 421 | reg [(`TS_WIDTH-1):0] tstamp; |
| 422 | reg hwtw; |
| 423 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 424 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 425 | |
| 426 | reg [2:0] mytid; |
| 427 | reg [5:0] mytnum; |
| 428 | wire [2:0] mycid; |
| 429 | integer junk; |
| 430 | integer i; |
| 431 | reg [7:0] cnt; |
| 432 | |
| 433 | assign mycid = 0; |
| 434 | |
| 435 | //---------------------------------------------------------- |
| 436 | // Instantiate fifo - 1 entry per thread |
| 437 | //fifo fifo (); |
| 438 | // Define fifo parameters |
| 439 | `ifndef PALLADIUM |
| 440 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 441 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 442 | defparam fifo.PTR_BITS = 4; |
| 443 | `endif |
| 444 | |
| 445 | //---------------------------------------------------------- |
| 446 | // DUT probes |
| 447 | |
| 448 | assign data_in = `SPC0.mmu.asi.wrote_dtlb; |
| 449 | assign tlb_wr = `SPC0.mmu_reload_done; |
| 450 | assign wr_en = `SPC0.lsu.tlb.tlb_wr_1_in_dout; |
| 451 | |
| 452 | assign entry = `SPC0.lsu.tlb.rw_index_1[6:0]; |
| 453 | |
| 454 | // assign asi_num = `PROBES0.asi_num; |
| 455 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 456 | // !`PROBES0.tlb_bypass_b & |
| 457 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 458 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 459 | // !`PROBES0.tlb_bypass_b & |
| 460 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 461 | |
| 462 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 463 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 464 | |
| 465 | |
| 466 | assign demap_page = `SPC0.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 467 | assign demap_context = `SPC0.lsu.tlc_demap_context; |
| 468 | assign demap_real = `SPC0.lsu.tlc_demap_real; |
| 469 | assign demap_all = `SPC0.lsu.tlc_demap_all; |
| 470 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 471 | assign skip_demap =`SPC0.lsu.tlc_wr_u_en; |
| 472 | assign demap_tid = `SPC0.lsu.tld.tte1[37:35]; |
| 473 | |
| 474 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 475 | assign demap_active = |demap_1 && !skip_demap; |
| 476 | assign auto_demap = |demap_1 && skip_demap; |
| 477 | |
| 478 | //--------------------- |
| 479 | // Probes for debugging |
| 480 | |
| 481 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 482 | |
| 483 | // n2_tlb_tl_128x59_cam.sv |
| 484 | |
| 485 | `define CNTX1_HI 65 |
| 486 | `define CNTX1_LO 53 |
| 487 | `define PID_HI 52 |
| 488 | `define PID_LO 50 |
| 489 | `define REAL_BIT 49 |
| 490 | `define VA_47 48 |
| 491 | `define VA_28 29 |
| 492 | `define VA_27 28 |
| 493 | `define VA_22 23 |
| 494 | `define TTE_VALID 22 |
| 495 | `define VA_21 21 |
| 496 | `define VA_16 16 |
| 497 | `define VA_15 15 |
| 498 | `define VA_13 13 |
| 499 | `define CNTX0_HI 12 |
| 500 | `define CNTX0_LO 0 |
| 501 | |
| 502 | // n2_tlb_tl_128x59_ram.sv |
| 503 | |
| 504 | `define DATA_PARITY 36 |
| 505 | `define DATA_PA_39_28_HI 35 |
| 506 | `define DATA_PA_39_28_LO 24 |
| 507 | `define DATA_PA_27_22_HI 23 |
| 508 | `define DATA_PA_27_22_LO 18 |
| 509 | `define DATA_VA_27_22_V 17 |
| 510 | `define DATA_PA_21_16_HI 16 |
| 511 | `define DATA_PA_21_16_LO 11 |
| 512 | `define DATA_VA_21_16_V 10 |
| 513 | `define DATA_PA_15_13_HI 9 |
| 514 | `define DATA_PA_15_13_LO 7 |
| 515 | `define DATA_VA_15_13_V 6 |
| 516 | `define DATA_NFO 5 |
| 517 | `define DATA_IE 4 |
| 518 | `define DATA_CP 3 |
| 519 | `define DATA_X 2 |
| 520 | `define DATA_P 1 |
| 521 | `define DATA_W 0 |
| 522 | |
| 523 | wire [(NUM_TLB-1):0] tlb_valid; |
| 524 | wire [(NUM_TLB-1):0] tlb_match; |
| 525 | wire tte_valid; |
| 526 | wire [47:0] tte_va; |
| 527 | wire [12:0] tte_context; |
| 528 | wire tte_real; |
| 529 | wire [2:0] tte_pid; |
| 530 | wire [2:0] tte_page_mask; |
| 531 | wire [39:0] tte_pa; |
| 532 | wire tte_nfo; |
| 533 | wire tte_ie; |
| 534 | wire tte_cp; |
| 535 | wire tte_e; |
| 536 | wire tte_p; |
| 537 | wire tte_w; |
| 538 | wire tte_ep; |
| 539 | |
| 540 | |
| 541 | assign tlb_valid = `SPC0.lsu.tlb.array.cam.valid; |
| 542 | assign tlb_match = `SPC0.lsu.tlb.array.cam.match; |
| 543 | |
| 544 | assign tte_va = {`SPC0.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 545 | `SPC0.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 546 | `SPC0.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 547 | `SPC0.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 548 | 13'b0 |
| 549 | }; |
| 550 | assign tte_context = `SPC0.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 551 | assign tte_pid = `SPC0.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 552 | assign tte_real = `SPC0.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 553 | assign tte_valid = `SPC0.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 554 | |
| 555 | assign tte_page_mask = `SPC0.lsu.tlb.tte_page_size_mask_1; |
| 556 | |
| 557 | assign tte_pa = {`SPC0.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 558 | `SPC0.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 559 | `SPC0.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 560 | `SPC0.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 561 | 13'b0 |
| 562 | }; |
| 563 | assign tte_nfo = `SPC0.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 564 | assign tte_ie = `SPC0.lsu.tlb.tte_data_1[`DATA_IE]; |
| 565 | assign tte_cp = `SPC0.lsu.tlb.tte_data_1[`DATA_CP]; |
| 566 | assign tte_e = `SPC0.lsu.tlb.tte_data_1[`DATA_X]; |
| 567 | assign tte_p = `SPC0.lsu.tlb.tte_data_1[`DATA_P]; |
| 568 | assign tte_w = `SPC0.lsu.tlb.tte_data_1[`DATA_W]; |
| 569 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 570 | |
| 571 | //---------------------------------------------------------- |
| 572 | // Initialize state machine to idle state |
| 573 | initial begin // { |
| 574 | `ifndef PALLADIUM |
| 575 | #1; |
| 576 | `endif |
| 577 | hwtw = 1'b0; |
| 578 | //for (i=0; i<=7; i=i+1) begin |
| 579 | // my_asi[i] = 8'b0; |
| 580 | //end |
| 581 | |
| 582 | end // } |
| 583 | |
| 584 | //---------------------------------------------------------- |
| 585 | // Must use negedge to avoid race condition |
| 586 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 587 | |
| 588 | always @ (negedge `CPU.l2clk) begin // { |
| 589 | |
| 590 | tstamp = `TOP.cycle; |
| 591 | demap_tstamp = `TOP.cycle; |
| 592 | |
| 593 | // Delay by 1 cycle to align with skip_demap |
| 594 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 595 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 596 | demap_1 <= demap; |
| 597 | |
| 598 | //---------------------------------------------------------- |
| 599 | // Send I/DTLBWRITE due to demap |
| 600 | // |
| 601 | |
| 602 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 603 | $display("tlb_sync", `ERROR, |
| 604 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 605 | mycid,demap_tid_1); |
| 606 | end // } |
| 607 | |
| 608 | //if (demap_active) begin // { |
| 609 | // fifo.pop_fifo ({hwtw,mytid}); |
| 610 | //end //} |
| 611 | |
| 612 | //-------------------- |
| 613 | if (dbg_in & (|demap_1)) begin // { |
| 614 | begin // axis tbcall_region |
| 615 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 616 | end |
| 617 | |
| 618 | if (demap_active) begin |
| 619 | begin // axis tbcall_region |
| 620 | case (demap_1) |
| 621 | 4'b0001: $write ("type=real "); |
| 622 | 4'b0010: $write ("type=cntx "); |
| 623 | 4'b0100: $write ("type=page "); |
| 624 | 4'b1000: $write ("type=all "); |
| 625 | default: |
| 626 | $display ("tlb_sync", `ERROR, |
| 627 | "Bench Problem - demap_1 should be one-hot."); |
| 628 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 629 | endcase |
| 630 | end |
| 631 | end |
| 632 | else begin |
| 633 | begin // axis tbcall_region |
| 634 | $write ("type=autodemap "); |
| 635 | end |
| 636 | end |
| 637 | |
| 638 | begin // axis tbcall_region |
| 639 | $display ("match=%h ts=%0d", |
| 640 | tlb_match,demap_tstamp*`TOP.core_period); |
| 641 | end |
| 642 | |
| 643 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 644 | if (tlb_match[cnt]==1'b1) begin // { |
| 645 | begin // axis tbcall_region |
| 646 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 647 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 648 | end |
| 649 | end // } |
| 650 | end // } |
| 651 | //-------------------- |
| 652 | end // } |
| 653 | |
| 654 | //---------------------------------------------------------- |
| 655 | // Send I/DHWTW due to HWTW |
| 656 | // Send I/DTLBWRITE due to ASI write |
| 657 | |
| 658 | // Save asi num when DTLBREAD happens. |
| 659 | // Otherwise, hold state. |
| 660 | // Send asi num later with DHWTW |
| 661 | // for (i=0;i<=7;i=i+1) begin // { |
| 662 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 663 | // end // } |
| 664 | |
| 665 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 666 | // These signals will be interleaved between the threads. |
| 667 | // Need to queue up the signals over time so they can be processed in order. |
| 668 | // Each thread will only be doing 1 thing at a time. |
| 669 | |
| 670 | for (i=0;i<=7;i=i+1) begin // { |
| 671 | |
| 672 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 673 | |
| 674 | // data_in[tid] determines which thread will write next |
| 675 | // Use fifo to save the tids of the data_in signals in order |
| 676 | |
| 677 | if (data_in[i]) begin // { |
| 678 | mytid[2:0] <= i[2:0]; |
| 679 | if (tlb_wr[i]) begin // { |
| 680 | hwtw <= 1'b1; |
| 681 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 682 | end // } |
| 683 | else begin // { |
| 684 | hwtw <= 1'b0; |
| 685 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 686 | end // } |
| 687 | end // } |
| 688 | |
| 689 | end // } |
| 690 | |
| 691 | //---------------------------------------------------------- |
| 692 | // wr_en means that the write is occurring |
| 693 | if (wr_en) begin // { |
| 694 | //fifo.pop_fifo ({hwtw,mytid}); |
| 695 | mytnum = (mycid * 8) + mytid; |
| 696 | |
| 697 | //-------------------- |
| 698 | if (dbg_in) begin // { |
| 699 | begin // axis tbcall_region |
| 700 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 701 | |
| 702 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 703 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 704 | |
| 705 | case (tte_page_mask) |
| 706 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 707 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 708 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 709 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 710 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 711 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 712 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 713 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 714 | endcase |
| 715 | |
| 716 | if (hwtw) $display (" (hwtw)"); |
| 717 | else $display (""); |
| 718 | |
| 719 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 720 | |
| 721 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 722 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 723 | end // } |
| 724 | //-------------------- |
| 725 | |
| 726 | end // } |
| 727 | end // } |
| 728 | |
| 729 | end // always} |
| 730 | |
| 731 | //---------------------------------------------------------- |
| 732 | `endif |
| 733 | |
| 734 | endmodule |
| 735 | `endif |
| 736 | |
| 737 | //---------------------------------------------------------- |
| 738 | //---------------------------------------------------------- |
| 739 | |
| 740 | |
| 741 | `ifdef CORE_1 |
| 742 | |
| 743 | module itlb_wr_c1 (dbg_in); |
| 744 | `ifndef GATESIM |
| 745 | |
| 746 | parameter NUM_TLB=64; |
| 747 | |
| 748 | wire [7:0] data_in; |
| 749 | wire [7:0] tlb_wr; |
| 750 | wire wr_en; |
| 751 | wire [7:0] entry; |
| 752 | wire [3:0] demap; |
| 753 | reg [3:0] demap_1; |
| 754 | wire demap_page; |
| 755 | wire demap_context; |
| 756 | wire demap_real; |
| 757 | wire demap_all; |
| 758 | wire skip_demap; |
| 759 | wire demap_active; |
| 760 | wire auto_demap; |
| 761 | wire [2:0] demap_tid; |
| 762 | reg [2:0] demap_tid_1; |
| 763 | reg [5:0] demap_tnum_1; |
| 764 | wire [7:0] asi_wr_itlb; |
| 765 | wire [7:0] asi_wr_itlb_demap; |
| 766 | wire [7:0] asi_wr_itlb_data_in; |
| 767 | wire [7:0] asi_wr_itlb_data_access; |
| 768 | input dbg_in; |
| 769 | |
| 770 | reg [(`TS_WIDTH-1):0] tstamp; |
| 771 | reg [7:0] data_in_ready; |
| 772 | reg hwtw; |
| 773 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 774 | reg dbg_en; |
| 775 | |
| 776 | reg [2:0] mytid; |
| 777 | reg [5:0] mytnum; |
| 778 | wire [2:0] mycid; |
| 779 | integer junk; |
| 780 | integer i; |
| 781 | reg [7:0] cnt; |
| 782 | |
| 783 | assign mycid = 1; |
| 784 | |
| 785 | //---------------------------------------------------------- |
| 786 | // Instantiate fifo - 1 entry per thread |
| 787 | //fifo fifo (); |
| 788 | // Define fifo parameters |
| 789 | `ifndef PALLADIUM |
| 790 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 791 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 792 | defparam fifo.PTR_BITS = 4; |
| 793 | `endif |
| 794 | |
| 795 | //---------------------------------------------------------- |
| 796 | // DUT probes |
| 797 | |
| 798 | assign data_in = `SPC1.mmu.asi.htc_wr_itlb_data_in; |
| 799 | assign wr_en = `SPC1.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 800 | |
| 801 | assign entry = `SPC1.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 802 | |
| 803 | assign demap_page = `SPC1.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 804 | assign demap_context = `SPC1.ifu_ftu.itc_demap_context; |
| 805 | assign demap_real = `SPC1.ifu_ftu.itc_demap_real; |
| 806 | assign demap_all = `SPC1.ifu_ftu.itc_demap_all; |
| 807 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 808 | assign skip_demap = `SPC1.ifu_ftu.itc_wr_u_en; |
| 809 | assign demap_tid = `SPC1.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 810 | |
| 811 | |
| 812 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 813 | assign demap_active = |demap_1 && !skip_demap; |
| 814 | assign auto_demap = |demap_1 && skip_demap; |
| 815 | wire [7:0] itlb_wr = {(`SPC1.tlu.trl1.take_itw & `SPC1.tlu.trl1.trap[3]), |
| 816 | (`SPC1.tlu.trl1.take_itw & `SPC1.tlu.trl1.trap[2]), |
| 817 | (`SPC1.tlu.trl1.take_itw & `SPC1.tlu.trl1.trap[1]), |
| 818 | (`SPC1.tlu.trl1.take_itw & `SPC1.tlu.trl1.trap[0]), |
| 819 | (`SPC1.tlu.trl0.take_itw & `SPC1.tlu.trl0.trap[3]), |
| 820 | (`SPC1.tlu.trl0.take_itw & `SPC1.tlu.trl0.trap[2]), |
| 821 | (`SPC1.tlu.trl0.take_itw & `SPC1.tlu.trl0.trap[1]), |
| 822 | (`SPC1.tlu.trl0.take_itw & `SPC1.tlu.trl0.trap[0]) |
| 823 | }; |
| 824 | |
| 825 | assign tlb_wr = itlb_wr; |
| 826 | |
| 827 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 828 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 829 | // These signals assert before the MMU reorders the TLB writes. |
| 830 | // Use these to suppress SSTEP in nas_pipe. |
| 831 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 832 | assign asi_wr_itlb_demap = `SPC1.mmu.asi_wr_immu_demap; |
| 833 | assign asi_wr_itlb_data_in = `SPC1.mmu.asi_wr_itlb_data_in; |
| 834 | assign asi_wr_itlb_data_access = {`SPC1.mmu.asd1.asi_wr_itlb_data_access, |
| 835 | `SPC1.mmu.asd0.asi_wr_itlb_data_access}; |
| 836 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 837 | |
| 838 | //--------------------- |
| 839 | // Probes for debugging |
| 840 | |
| 841 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 842 | |
| 843 | // n2_tlb_tl_64x59_cam.sv |
| 844 | |
| 845 | `define CNTX1_HI 65 |
| 846 | `define CNTX1_LO 53 |
| 847 | `define PID_HI 52 |
| 848 | `define PID_LO 50 |
| 849 | `define REAL_BIT 49 |
| 850 | `define VA_47 48 |
| 851 | `define VA_28 29 |
| 852 | `define VA_27 28 |
| 853 | `define VA_22 23 |
| 854 | `define TTE_VALID 22 |
| 855 | `define VA_21 21 |
| 856 | `define VA_16 16 |
| 857 | `define VA_15 15 |
| 858 | `define VA_13 13 |
| 859 | `define CNTX0_HI 12 |
| 860 | `define CNTX0_LO 0 |
| 861 | |
| 862 | // n2_tlb_tl_64x59_ram.sv |
| 863 | |
| 864 | `define DATA_PARITY 36 |
| 865 | `define DATA_PA_39_28_HI 35 |
| 866 | `define DATA_PA_39_28_LO 24 |
| 867 | `define DATA_PA_27_22_HI 23 |
| 868 | `define DATA_PA_27_22_LO 18 |
| 869 | `define DATA_VA_27_22_V 17 |
| 870 | `define DATA_PA_21_16_HI 16 |
| 871 | `define DATA_PA_21_16_LO 11 |
| 872 | `define DATA_VA_21_16_V 10 |
| 873 | `define DATA_PA_15_13_HI 9 |
| 874 | `define DATA_PA_15_13_LO 7 |
| 875 | `define DATA_VA_15_13_V 6 |
| 876 | `define DATA_NFO 5 |
| 877 | `define DATA_IE 4 |
| 878 | `define DATA_CP 3 |
| 879 | `define DATA_X 2 |
| 880 | `define DATA_P 1 |
| 881 | `define DATA_W 0 |
| 882 | |
| 883 | wire [(NUM_TLB-1):0] tlb_valid; |
| 884 | wire [(NUM_TLB-1):0] tlb_match; |
| 885 | wire tte_valid; |
| 886 | wire [47:0] tte_va; |
| 887 | wire [12:0] tte_context; |
| 888 | wire tte_real; |
| 889 | wire [2:0] tte_pid; |
| 890 | wire [2:0] tte_page_mask; |
| 891 | wire [39:0] tte_pa; |
| 892 | wire tte_nfo; |
| 893 | wire tte_ie; |
| 894 | wire tte_cp; |
| 895 | wire tte_e; |
| 896 | wire tte_p; |
| 897 | wire tte_w; |
| 898 | wire tte_ep; |
| 899 | |
| 900 | assign tlb_valid = `SPC1.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 901 | assign tlb_match = `SPC1.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 902 | |
| 903 | assign tte_va = {`SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 904 | `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 905 | `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 906 | `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 907 | 13'b0 |
| 908 | }; |
| 909 | assign tte_context = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 910 | assign tte_pid = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 911 | assign tte_real = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 912 | assign tte_valid = `SPC1.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 913 | |
| 914 | assign tte_page_mask = `SPC1.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 915 | |
| 916 | assign tte_pa = {`SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 917 | `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 918 | `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 919 | `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 920 | 13'b0 |
| 921 | }; |
| 922 | assign tte_nfo = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 923 | assign tte_ie = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 924 | assign tte_cp = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 925 | assign tte_e = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 926 | assign tte_p = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 927 | assign tte_w = `SPC1.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 928 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 929 | |
| 930 | //---------------------------------------------------------- |
| 931 | initial begin // { |
| 932 | `ifndef PALLADIUM |
| 933 | #1; |
| 934 | `endif |
| 935 | hwtw = 1'b0; |
| 936 | data_in_ready = 8'b0; |
| 937 | end // } |
| 938 | |
| 939 | //---------------------------------------------------------- |
| 940 | // Must use negedge to avoid race condition |
| 941 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 942 | |
| 943 | always @ (negedge `CPU.l2clk) begin // { |
| 944 | |
| 945 | tstamp = `TOP.cycle; |
| 946 | demap_tstamp = `TOP.cycle; |
| 947 | |
| 948 | // Delay by 1 cycle to align with skip_demap |
| 949 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 950 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 951 | demap_1 <= demap; |
| 952 | |
| 953 | |
| 954 | //---------------------------------------------------------- |
| 955 | // Send I/DTLBWRITE due to demap |
| 956 | // |
| 957 | |
| 958 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 959 | $display("tlb_sync", `ERROR, |
| 960 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 961 | mycid,demap_tid_1); |
| 962 | end // } |
| 963 | |
| 964 | //if (demap_active) begin // { |
| 965 | // fifo.pop_fifo ({hwtw,mytid}); |
| 966 | //end |
| 967 | //-------------------- |
| 968 | if (dbg_in & (|demap_1)) begin // { |
| 969 | begin // axis tbcall_region |
| 970 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 971 | end |
| 972 | |
| 973 | if (demap_active) begin |
| 974 | begin // axis tbcall_region |
| 975 | case (demap_1) |
| 976 | 4'b0001: $write ("type=real "); |
| 977 | 4'b0010: $write ("type=cntx "); |
| 978 | 4'b0100: $write ("type=page "); |
| 979 | 4'b1000: $write ("type=all "); |
| 980 | default: |
| 981 | $display ("tlb_sync", `ERROR, |
| 982 | "Bench Problem - demap_1() should be one-hot."); |
| 983 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 984 | endcase |
| 985 | end |
| 986 | end |
| 987 | else begin |
| 988 | begin // axis tbcall_region |
| 989 | $write("type=autodemap "); |
| 990 | end |
| 991 | end |
| 992 | |
| 993 | begin // axis tbcall_region |
| 994 | $display ("match=%h ts=%0d", |
| 995 | tlb_match,demap_tstamp*`TOP.core_period); |
| 996 | end |
| 997 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 998 | if (tlb_match[cnt]==1'b1) begin // { |
| 999 | begin // axis tbcall_region |
| 1000 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 1001 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 1002 | end |
| 1003 | end // } |
| 1004 | end // } |
| 1005 | |
| 1006 | end // } |
| 1007 | |
| 1008 | //---------------------------------------------------------- |
| 1009 | // Send I/DHWTW due to HWTW |
| 1010 | // Send I/DTLBWRITE due to ASI write |
| 1011 | |
| 1012 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 1013 | // These signals will be interleaved between the threads. |
| 1014 | // Need to queue up the signals over time so they can be processed in order. |
| 1015 | // Each thread will only be doing 1 thing at a time. |
| 1016 | |
| 1017 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 1018 | |
| 1019 | for (i=0;i<=7;i=i+1) begin // { |
| 1020 | |
| 1021 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 1022 | $display ("tlb_sync", `ERROR, |
| 1023 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 1024 | end // } |
| 1025 | else begin // { |
| 1026 | |
| 1027 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 1028 | if (data_in[i]) begin // { |
| 1029 | data_in_ready[i] <= 1'b1; |
| 1030 | end // } |
| 1031 | |
| 1032 | // tlb_wr[tid] determines which thread will write next |
| 1033 | // Use fifo to save the tids of the tlb_wr signals in order |
| 1034 | if (tlb_wr[i]) begin // { |
| 1035 | if (data_in_ready[i]) begin // { |
| 1036 | hwtw <= 1'b1; |
| 1037 | mytid[2:0] <= i[2:0]; |
| 1038 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 1039 | data_in_ready[i] <= 1'b0; |
| 1040 | end // } |
| 1041 | else begin // { |
| 1042 | hwtw <= 1'b0; |
| 1043 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 1044 | mytid[2:0] <= i[2:0]; |
| 1045 | end // } |
| 1046 | end // } |
| 1047 | |
| 1048 | end // if} |
| 1049 | end // for} |
| 1050 | |
| 1051 | end // if} |
| 1052 | |
| 1053 | //---------------------------------------------------------- |
| 1054 | // wr_en means that the write is occurring |
| 1055 | if (wr_en) begin // { |
| 1056 | //fifo.pop_fifo ({hwtw,mytid}); |
| 1057 | mytnum = (mycid * 8) + mytid; |
| 1058 | |
| 1059 | //-------------------- |
| 1060 | if (dbg_in) begin // { |
| 1061 | begin // axis tbcall_region |
| 1062 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 1063 | end |
| 1064 | |
| 1065 | begin // axis tbcall_region |
| 1066 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 1067 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 1068 | end |
| 1069 | |
| 1070 | begin // axis tbcall_region |
| 1071 | case (tte_page_mask) |
| 1072 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 1073 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1074 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 1075 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1076 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 1077 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1078 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 1079 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1080 | endcase |
| 1081 | |
| 1082 | if (hwtw) $display (" (hwtw)"); |
| 1083 | else $display (""); |
| 1084 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 1085 | |
| 1086 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 1087 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 1088 | end |
| 1089 | end // } |
| 1090 | //-------------------- |
| 1091 | |
| 1092 | end // } |
| 1093 | |
| 1094 | end // always} |
| 1095 | |
| 1096 | `endif |
| 1097 | //---------------------------------------------------------- |
| 1098 | endmodule |
| 1099 | |
| 1100 | module dtlb_wr_c1 (dbg_in); |
| 1101 | `ifndef GATESIM |
| 1102 | |
| 1103 | parameter NUM_TLB=128; |
| 1104 | |
| 1105 | wire [7:0] data_in; |
| 1106 | wire [7:0] tlb_wr; |
| 1107 | wire wr_en; |
| 1108 | wire [7:0] entry; |
| 1109 | wire [7:0] asi_num; |
| 1110 | wire asi_enable0; // 1 per thread group |
| 1111 | wire asi_enable1; |
| 1112 | // wire [7:0] store_asi; // 1 per thread |
| 1113 | wire [3:0] demap; |
| 1114 | reg [3:0] demap_1; |
| 1115 | wire demap_page; |
| 1116 | wire demap_context; |
| 1117 | wire demap_real; |
| 1118 | wire demap_all; |
| 1119 | wire skip_demap; |
| 1120 | wire demap_active; |
| 1121 | wire auto_demap; |
| 1122 | wire [2:0] demap_tid; |
| 1123 | reg [2:0] demap_tid_1; |
| 1124 | reg [5:0] demap_tnum_1; |
| 1125 | input dbg_in; |
| 1126 | |
| 1127 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1128 | reg hwtw; |
| 1129 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 1130 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 1131 | |
| 1132 | reg [2:0] mytid; |
| 1133 | reg [5:0] mytnum; |
| 1134 | wire [2:0] mycid; |
| 1135 | integer junk; |
| 1136 | integer i; |
| 1137 | reg [7:0] cnt; |
| 1138 | |
| 1139 | assign mycid = 1; |
| 1140 | |
| 1141 | //---------------------------------------------------------- |
| 1142 | // Instantiate fifo - 1 entry per thread |
| 1143 | //fifo fifo (); |
| 1144 | // Define fifo parameters |
| 1145 | `ifndef PALLADIUM |
| 1146 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 1147 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 1148 | defparam fifo.PTR_BITS = 4; |
| 1149 | `endif |
| 1150 | |
| 1151 | //---------------------------------------------------------- |
| 1152 | // DUT probes |
| 1153 | |
| 1154 | assign data_in = `SPC1.mmu.asi.wrote_dtlb; |
| 1155 | assign tlb_wr = `SPC1.mmu_reload_done; |
| 1156 | assign wr_en = `SPC1.lsu.tlb.tlb_wr_1_in_dout; |
| 1157 | |
| 1158 | assign entry = `SPC1.lsu.tlb.rw_index_1[6:0]; |
| 1159 | |
| 1160 | // assign asi_num = `PROBES0.asi_num; |
| 1161 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 1162 | // !`PROBES0.tlb_bypass_b & |
| 1163 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 1164 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 1165 | // !`PROBES0.tlb_bypass_b & |
| 1166 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 1167 | |
| 1168 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 1169 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 1170 | |
| 1171 | |
| 1172 | assign demap_page = `SPC1.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 1173 | assign demap_context = `SPC1.lsu.tlc_demap_context; |
| 1174 | assign demap_real = `SPC1.lsu.tlc_demap_real; |
| 1175 | assign demap_all = `SPC1.lsu.tlc_demap_all; |
| 1176 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 1177 | assign skip_demap =`SPC1.lsu.tlc_wr_u_en; |
| 1178 | assign demap_tid = `SPC1.lsu.tld.tte1[37:35]; |
| 1179 | |
| 1180 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 1181 | assign demap_active = |demap_1 && !skip_demap; |
| 1182 | assign auto_demap = |demap_1 && skip_demap; |
| 1183 | |
| 1184 | //--------------------- |
| 1185 | // Probes for debugging |
| 1186 | |
| 1187 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 1188 | |
| 1189 | // n2_tlb_tl_128x59_cam.sv |
| 1190 | |
| 1191 | `define CNTX1_HI 65 |
| 1192 | `define CNTX1_LO 53 |
| 1193 | `define PID_HI 52 |
| 1194 | `define PID_LO 50 |
| 1195 | `define REAL_BIT 49 |
| 1196 | `define VA_47 48 |
| 1197 | `define VA_28 29 |
| 1198 | `define VA_27 28 |
| 1199 | `define VA_22 23 |
| 1200 | `define TTE_VALID 22 |
| 1201 | `define VA_21 21 |
| 1202 | `define VA_16 16 |
| 1203 | `define VA_15 15 |
| 1204 | `define VA_13 13 |
| 1205 | `define CNTX0_HI 12 |
| 1206 | `define CNTX0_LO 0 |
| 1207 | |
| 1208 | // n2_tlb_tl_128x59_ram.sv |
| 1209 | |
| 1210 | `define DATA_PARITY 36 |
| 1211 | `define DATA_PA_39_28_HI 35 |
| 1212 | `define DATA_PA_39_28_LO 24 |
| 1213 | `define DATA_PA_27_22_HI 23 |
| 1214 | `define DATA_PA_27_22_LO 18 |
| 1215 | `define DATA_VA_27_22_V 17 |
| 1216 | `define DATA_PA_21_16_HI 16 |
| 1217 | `define DATA_PA_21_16_LO 11 |
| 1218 | `define DATA_VA_21_16_V 10 |
| 1219 | `define DATA_PA_15_13_HI 9 |
| 1220 | `define DATA_PA_15_13_LO 7 |
| 1221 | `define DATA_VA_15_13_V 6 |
| 1222 | `define DATA_NFO 5 |
| 1223 | `define DATA_IE 4 |
| 1224 | `define DATA_CP 3 |
| 1225 | `define DATA_X 2 |
| 1226 | `define DATA_P 1 |
| 1227 | `define DATA_W 0 |
| 1228 | |
| 1229 | wire [(NUM_TLB-1):0] tlb_valid; |
| 1230 | wire [(NUM_TLB-1):0] tlb_match; |
| 1231 | wire tte_valid; |
| 1232 | wire [47:0] tte_va; |
| 1233 | wire [12:0] tte_context; |
| 1234 | wire tte_real; |
| 1235 | wire [2:0] tte_pid; |
| 1236 | wire [2:0] tte_page_mask; |
| 1237 | wire [39:0] tte_pa; |
| 1238 | wire tte_nfo; |
| 1239 | wire tte_ie; |
| 1240 | wire tte_cp; |
| 1241 | wire tte_e; |
| 1242 | wire tte_p; |
| 1243 | wire tte_w; |
| 1244 | wire tte_ep; |
| 1245 | |
| 1246 | |
| 1247 | assign tlb_valid = `SPC1.lsu.tlb.array.cam.valid; |
| 1248 | assign tlb_match = `SPC1.lsu.tlb.array.cam.match; |
| 1249 | |
| 1250 | assign tte_va = {`SPC1.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 1251 | `SPC1.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 1252 | `SPC1.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 1253 | `SPC1.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 1254 | 13'b0 |
| 1255 | }; |
| 1256 | assign tte_context = `SPC1.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 1257 | assign tte_pid = `SPC1.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 1258 | assign tte_real = `SPC1.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 1259 | assign tte_valid = `SPC1.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 1260 | |
| 1261 | assign tte_page_mask = `SPC1.lsu.tlb.tte_page_size_mask_1; |
| 1262 | |
| 1263 | assign tte_pa = {`SPC1.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 1264 | `SPC1.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 1265 | `SPC1.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 1266 | `SPC1.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 1267 | 13'b0 |
| 1268 | }; |
| 1269 | assign tte_nfo = `SPC1.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 1270 | assign tte_ie = `SPC1.lsu.tlb.tte_data_1[`DATA_IE]; |
| 1271 | assign tte_cp = `SPC1.lsu.tlb.tte_data_1[`DATA_CP]; |
| 1272 | assign tte_e = `SPC1.lsu.tlb.tte_data_1[`DATA_X]; |
| 1273 | assign tte_p = `SPC1.lsu.tlb.tte_data_1[`DATA_P]; |
| 1274 | assign tte_w = `SPC1.lsu.tlb.tte_data_1[`DATA_W]; |
| 1275 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 1276 | |
| 1277 | //---------------------------------------------------------- |
| 1278 | // Initialize state machine to idle state |
| 1279 | initial begin // { |
| 1280 | `ifndef PALLADIUM |
| 1281 | #1; |
| 1282 | `endif |
| 1283 | hwtw = 1'b0; |
| 1284 | //for (i=0; i<=7; i=i+1) begin |
| 1285 | // my_asi[i] = 8'b0; |
| 1286 | //end |
| 1287 | |
| 1288 | end // } |
| 1289 | |
| 1290 | //---------------------------------------------------------- |
| 1291 | // Must use negedge to avoid race condition |
| 1292 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 1293 | |
| 1294 | always @ (negedge `CPU.l2clk) begin // { |
| 1295 | |
| 1296 | tstamp = `TOP.cycle; |
| 1297 | demap_tstamp = `TOP.cycle; |
| 1298 | |
| 1299 | // Delay by 1 cycle to align with skip_demap |
| 1300 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 1301 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 1302 | demap_1 <= demap; |
| 1303 | |
| 1304 | //---------------------------------------------------------- |
| 1305 | // Send I/DTLBWRITE due to demap |
| 1306 | // |
| 1307 | |
| 1308 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 1309 | $display("tlb_sync", `ERROR, |
| 1310 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 1311 | mycid,demap_tid_1); |
| 1312 | end // } |
| 1313 | |
| 1314 | //if (demap_active) begin // { |
| 1315 | // fifo.pop_fifo ({hwtw,mytid}); |
| 1316 | //end //} |
| 1317 | |
| 1318 | //-------------------- |
| 1319 | if (dbg_in & (|demap_1)) begin // { |
| 1320 | begin // axis tbcall_region |
| 1321 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 1322 | end |
| 1323 | |
| 1324 | if (demap_active) begin |
| 1325 | begin // axis tbcall_region |
| 1326 | case (demap_1) |
| 1327 | 4'b0001: $write ("type=real "); |
| 1328 | 4'b0010: $write ("type=cntx "); |
| 1329 | 4'b0100: $write ("type=page "); |
| 1330 | 4'b1000: $write ("type=all "); |
| 1331 | default: |
| 1332 | $display ("tlb_sync", `ERROR, |
| 1333 | "Bench Problem - demap_1 should be one-hot."); |
| 1334 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 1335 | endcase |
| 1336 | end |
| 1337 | end |
| 1338 | else begin |
| 1339 | begin // axis tbcall_region |
| 1340 | $write ("type=autodemap "); |
| 1341 | end |
| 1342 | end |
| 1343 | |
| 1344 | begin // axis tbcall_region |
| 1345 | $display ("match=%h ts=%0d", |
| 1346 | tlb_match,demap_tstamp*`TOP.core_period); |
| 1347 | end |
| 1348 | |
| 1349 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 1350 | if (tlb_match[cnt]==1'b1) begin // { |
| 1351 | begin // axis tbcall_region |
| 1352 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 1353 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 1354 | end |
| 1355 | end // } |
| 1356 | end // } |
| 1357 | //-------------------- |
| 1358 | end // } |
| 1359 | |
| 1360 | //---------------------------------------------------------- |
| 1361 | // Send I/DHWTW due to HWTW |
| 1362 | // Send I/DTLBWRITE due to ASI write |
| 1363 | |
| 1364 | // Save asi num when DTLBREAD happens. |
| 1365 | // Otherwise, hold state. |
| 1366 | // Send asi num later with DHWTW |
| 1367 | // for (i=0;i<=7;i=i+1) begin // { |
| 1368 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 1369 | // end // } |
| 1370 | |
| 1371 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 1372 | // These signals will be interleaved between the threads. |
| 1373 | // Need to queue up the signals over time so they can be processed in order. |
| 1374 | // Each thread will only be doing 1 thing at a time. |
| 1375 | |
| 1376 | for (i=0;i<=7;i=i+1) begin // { |
| 1377 | |
| 1378 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 1379 | |
| 1380 | // data_in[tid] determines which thread will write next |
| 1381 | // Use fifo to save the tids of the data_in signals in order |
| 1382 | |
| 1383 | if (data_in[i]) begin // { |
| 1384 | mytid[2:0] <= i[2:0]; |
| 1385 | if (tlb_wr[i]) begin // { |
| 1386 | hwtw <= 1'b1; |
| 1387 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 1388 | end // } |
| 1389 | else begin // { |
| 1390 | hwtw <= 1'b0; |
| 1391 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 1392 | end // } |
| 1393 | end // } |
| 1394 | |
| 1395 | end // } |
| 1396 | |
| 1397 | //---------------------------------------------------------- |
| 1398 | // wr_en means that the write is occurring |
| 1399 | if (wr_en) begin // { |
| 1400 | //fifo.pop_fifo ({hwtw,mytid}); |
| 1401 | mytnum = (mycid * 8) + mytid; |
| 1402 | |
| 1403 | //-------------------- |
| 1404 | if (dbg_in) begin // { |
| 1405 | begin // axis tbcall_region |
| 1406 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 1407 | |
| 1408 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 1409 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 1410 | |
| 1411 | case (tte_page_mask) |
| 1412 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 1413 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1414 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 1415 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1416 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 1417 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1418 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 1419 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1420 | endcase |
| 1421 | |
| 1422 | if (hwtw) $display (" (hwtw)"); |
| 1423 | else $display (""); |
| 1424 | |
| 1425 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 1426 | |
| 1427 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 1428 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 1429 | end // } |
| 1430 | //-------------------- |
| 1431 | |
| 1432 | end // } |
| 1433 | end // } |
| 1434 | |
| 1435 | end // always} |
| 1436 | |
| 1437 | //---------------------------------------------------------- |
| 1438 | `endif |
| 1439 | |
| 1440 | endmodule |
| 1441 | `endif |
| 1442 | |
| 1443 | //---------------------------------------------------------- |
| 1444 | //---------------------------------------------------------- |
| 1445 | |
| 1446 | |
| 1447 | `ifdef CORE_2 |
| 1448 | |
| 1449 | module itlb_wr_c2 (dbg_in); |
| 1450 | `ifndef GATESIM |
| 1451 | |
| 1452 | parameter NUM_TLB=64; |
| 1453 | |
| 1454 | wire [7:0] data_in; |
| 1455 | wire [7:0] tlb_wr; |
| 1456 | wire wr_en; |
| 1457 | wire [7:0] entry; |
| 1458 | wire [3:0] demap; |
| 1459 | reg [3:0] demap_1; |
| 1460 | wire demap_page; |
| 1461 | wire demap_context; |
| 1462 | wire demap_real; |
| 1463 | wire demap_all; |
| 1464 | wire skip_demap; |
| 1465 | wire demap_active; |
| 1466 | wire auto_demap; |
| 1467 | wire [2:0] demap_tid; |
| 1468 | reg [2:0] demap_tid_1; |
| 1469 | reg [5:0] demap_tnum_1; |
| 1470 | wire [7:0] asi_wr_itlb; |
| 1471 | wire [7:0] asi_wr_itlb_demap; |
| 1472 | wire [7:0] asi_wr_itlb_data_in; |
| 1473 | wire [7:0] asi_wr_itlb_data_access; |
| 1474 | input dbg_in; |
| 1475 | |
| 1476 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1477 | reg [7:0] data_in_ready; |
| 1478 | reg hwtw; |
| 1479 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 1480 | reg dbg_en; |
| 1481 | |
| 1482 | reg [2:0] mytid; |
| 1483 | reg [5:0] mytnum; |
| 1484 | wire [2:0] mycid; |
| 1485 | integer junk; |
| 1486 | integer i; |
| 1487 | reg [7:0] cnt; |
| 1488 | |
| 1489 | assign mycid = 2; |
| 1490 | |
| 1491 | //---------------------------------------------------------- |
| 1492 | // Instantiate fifo - 1 entry per thread |
| 1493 | //fifo fifo (); |
| 1494 | // Define fifo parameters |
| 1495 | `ifndef PALLADIUM |
| 1496 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 1497 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 1498 | defparam fifo.PTR_BITS = 4; |
| 1499 | `endif |
| 1500 | |
| 1501 | //---------------------------------------------------------- |
| 1502 | // DUT probes |
| 1503 | |
| 1504 | assign data_in = `SPC2.mmu.asi.htc_wr_itlb_data_in; |
| 1505 | assign wr_en = `SPC2.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 1506 | |
| 1507 | assign entry = `SPC2.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 1508 | |
| 1509 | assign demap_page = `SPC2.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 1510 | assign demap_context = `SPC2.ifu_ftu.itc_demap_context; |
| 1511 | assign demap_real = `SPC2.ifu_ftu.itc_demap_real; |
| 1512 | assign demap_all = `SPC2.ifu_ftu.itc_demap_all; |
| 1513 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 1514 | assign skip_demap = `SPC2.ifu_ftu.itc_wr_u_en; |
| 1515 | assign demap_tid = `SPC2.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 1516 | |
| 1517 | |
| 1518 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 1519 | assign demap_active = |demap_1 && !skip_demap; |
| 1520 | assign auto_demap = |demap_1 && skip_demap; |
| 1521 | wire [7:0] itlb_wr = {(`SPC2.tlu.trl1.take_itw & `SPC2.tlu.trl1.trap[3]), |
| 1522 | (`SPC2.tlu.trl1.take_itw & `SPC2.tlu.trl1.trap[2]), |
| 1523 | (`SPC2.tlu.trl1.take_itw & `SPC2.tlu.trl1.trap[1]), |
| 1524 | (`SPC2.tlu.trl1.take_itw & `SPC2.tlu.trl1.trap[0]), |
| 1525 | (`SPC2.tlu.trl0.take_itw & `SPC2.tlu.trl0.trap[3]), |
| 1526 | (`SPC2.tlu.trl0.take_itw & `SPC2.tlu.trl0.trap[2]), |
| 1527 | (`SPC2.tlu.trl0.take_itw & `SPC2.tlu.trl0.trap[1]), |
| 1528 | (`SPC2.tlu.trl0.take_itw & `SPC2.tlu.trl0.trap[0]) |
| 1529 | }; |
| 1530 | |
| 1531 | assign tlb_wr = itlb_wr; |
| 1532 | |
| 1533 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 1534 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 1535 | // These signals assert before the MMU reorders the TLB writes. |
| 1536 | // Use these to suppress SSTEP in nas_pipe. |
| 1537 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 1538 | assign asi_wr_itlb_demap = `SPC2.mmu.asi_wr_immu_demap; |
| 1539 | assign asi_wr_itlb_data_in = `SPC2.mmu.asi_wr_itlb_data_in; |
| 1540 | assign asi_wr_itlb_data_access = {`SPC2.mmu.asd1.asi_wr_itlb_data_access, |
| 1541 | `SPC2.mmu.asd0.asi_wr_itlb_data_access}; |
| 1542 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 1543 | |
| 1544 | //--------------------- |
| 1545 | // Probes for debugging |
| 1546 | |
| 1547 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 1548 | |
| 1549 | // n2_tlb_tl_64x59_cam.sv |
| 1550 | |
| 1551 | `define CNTX1_HI 65 |
| 1552 | `define CNTX1_LO 53 |
| 1553 | `define PID_HI 52 |
| 1554 | `define PID_LO 50 |
| 1555 | `define REAL_BIT 49 |
| 1556 | `define VA_47 48 |
| 1557 | `define VA_28 29 |
| 1558 | `define VA_27 28 |
| 1559 | `define VA_22 23 |
| 1560 | `define TTE_VALID 22 |
| 1561 | `define VA_21 21 |
| 1562 | `define VA_16 16 |
| 1563 | `define VA_15 15 |
| 1564 | `define VA_13 13 |
| 1565 | `define CNTX0_HI 12 |
| 1566 | `define CNTX0_LO 0 |
| 1567 | |
| 1568 | // n2_tlb_tl_64x59_ram.sv |
| 1569 | |
| 1570 | `define DATA_PARITY 36 |
| 1571 | `define DATA_PA_39_28_HI 35 |
| 1572 | `define DATA_PA_39_28_LO 24 |
| 1573 | `define DATA_PA_27_22_HI 23 |
| 1574 | `define DATA_PA_27_22_LO 18 |
| 1575 | `define DATA_VA_27_22_V 17 |
| 1576 | `define DATA_PA_21_16_HI 16 |
| 1577 | `define DATA_PA_21_16_LO 11 |
| 1578 | `define DATA_VA_21_16_V 10 |
| 1579 | `define DATA_PA_15_13_HI 9 |
| 1580 | `define DATA_PA_15_13_LO 7 |
| 1581 | `define DATA_VA_15_13_V 6 |
| 1582 | `define DATA_NFO 5 |
| 1583 | `define DATA_IE 4 |
| 1584 | `define DATA_CP 3 |
| 1585 | `define DATA_X 2 |
| 1586 | `define DATA_P 1 |
| 1587 | `define DATA_W 0 |
| 1588 | |
| 1589 | wire [(NUM_TLB-1):0] tlb_valid; |
| 1590 | wire [(NUM_TLB-1):0] tlb_match; |
| 1591 | wire tte_valid; |
| 1592 | wire [47:0] tte_va; |
| 1593 | wire [12:0] tte_context; |
| 1594 | wire tte_real; |
| 1595 | wire [2:0] tte_pid; |
| 1596 | wire [2:0] tte_page_mask; |
| 1597 | wire [39:0] tte_pa; |
| 1598 | wire tte_nfo; |
| 1599 | wire tte_ie; |
| 1600 | wire tte_cp; |
| 1601 | wire tte_e; |
| 1602 | wire tte_p; |
| 1603 | wire tte_w; |
| 1604 | wire tte_ep; |
| 1605 | |
| 1606 | assign tlb_valid = `SPC2.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 1607 | assign tlb_match = `SPC2.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 1608 | |
| 1609 | assign tte_va = {`SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 1610 | `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 1611 | `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 1612 | `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 1613 | 13'b0 |
| 1614 | }; |
| 1615 | assign tte_context = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 1616 | assign tte_pid = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 1617 | assign tte_real = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 1618 | assign tte_valid = `SPC2.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 1619 | |
| 1620 | assign tte_page_mask = `SPC2.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 1621 | |
| 1622 | assign tte_pa = {`SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 1623 | `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 1624 | `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 1625 | `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 1626 | 13'b0 |
| 1627 | }; |
| 1628 | assign tte_nfo = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 1629 | assign tte_ie = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 1630 | assign tte_cp = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 1631 | assign tte_e = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 1632 | assign tte_p = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 1633 | assign tte_w = `SPC2.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 1634 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 1635 | |
| 1636 | //---------------------------------------------------------- |
| 1637 | initial begin // { |
| 1638 | `ifndef PALLADIUM |
| 1639 | #1; |
| 1640 | `endif |
| 1641 | hwtw = 1'b0; |
| 1642 | data_in_ready = 8'b0; |
| 1643 | end // } |
| 1644 | |
| 1645 | //---------------------------------------------------------- |
| 1646 | // Must use negedge to avoid race condition |
| 1647 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 1648 | |
| 1649 | always @ (negedge `CPU.l2clk) begin // { |
| 1650 | |
| 1651 | tstamp = `TOP.cycle; |
| 1652 | demap_tstamp = `TOP.cycle; |
| 1653 | |
| 1654 | // Delay by 1 cycle to align with skip_demap |
| 1655 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 1656 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 1657 | demap_1 <= demap; |
| 1658 | |
| 1659 | |
| 1660 | //---------------------------------------------------------- |
| 1661 | // Send I/DTLBWRITE due to demap |
| 1662 | // |
| 1663 | |
| 1664 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 1665 | $display("tlb_sync", `ERROR, |
| 1666 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 1667 | mycid,demap_tid_1); |
| 1668 | end // } |
| 1669 | |
| 1670 | //if (demap_active) begin // { |
| 1671 | // fifo.pop_fifo ({hwtw,mytid}); |
| 1672 | //end |
| 1673 | //-------------------- |
| 1674 | if (dbg_in & (|demap_1)) begin // { |
| 1675 | begin // axis tbcall_region |
| 1676 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 1677 | end |
| 1678 | |
| 1679 | if (demap_active) begin |
| 1680 | begin // axis tbcall_region |
| 1681 | case (demap_1) |
| 1682 | 4'b0001: $write ("type=real "); |
| 1683 | 4'b0010: $write ("type=cntx "); |
| 1684 | 4'b0100: $write ("type=page "); |
| 1685 | 4'b1000: $write ("type=all "); |
| 1686 | default: |
| 1687 | $display ("tlb_sync", `ERROR, |
| 1688 | "Bench Problem - demap_1() should be one-hot."); |
| 1689 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 1690 | endcase |
| 1691 | end |
| 1692 | end |
| 1693 | else begin |
| 1694 | begin // axis tbcall_region |
| 1695 | $write("type=autodemap "); |
| 1696 | end |
| 1697 | end |
| 1698 | |
| 1699 | begin // axis tbcall_region |
| 1700 | $display ("match=%h ts=%0d", |
| 1701 | tlb_match,demap_tstamp*`TOP.core_period); |
| 1702 | end |
| 1703 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 1704 | if (tlb_match[cnt]==1'b1) begin // { |
| 1705 | begin // axis tbcall_region |
| 1706 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 1707 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 1708 | end |
| 1709 | end // } |
| 1710 | end // } |
| 1711 | |
| 1712 | end // } |
| 1713 | |
| 1714 | //---------------------------------------------------------- |
| 1715 | // Send I/DHWTW due to HWTW |
| 1716 | // Send I/DTLBWRITE due to ASI write |
| 1717 | |
| 1718 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 1719 | // These signals will be interleaved between the threads. |
| 1720 | // Need to queue up the signals over time so they can be processed in order. |
| 1721 | // Each thread will only be doing 1 thing at a time. |
| 1722 | |
| 1723 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 1724 | |
| 1725 | for (i=0;i<=7;i=i+1) begin // { |
| 1726 | |
| 1727 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 1728 | $display ("tlb_sync", `ERROR, |
| 1729 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 1730 | end // } |
| 1731 | else begin // { |
| 1732 | |
| 1733 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 1734 | if (data_in[i]) begin // { |
| 1735 | data_in_ready[i] <= 1'b1; |
| 1736 | end // } |
| 1737 | |
| 1738 | // tlb_wr[tid] determines which thread will write next |
| 1739 | // Use fifo to save the tids of the tlb_wr signals in order |
| 1740 | if (tlb_wr[i]) begin // { |
| 1741 | if (data_in_ready[i]) begin // { |
| 1742 | hwtw <= 1'b1; |
| 1743 | mytid[2:0] <= i[2:0]; |
| 1744 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 1745 | data_in_ready[i] <= 1'b0; |
| 1746 | end // } |
| 1747 | else begin // { |
| 1748 | hwtw <= 1'b0; |
| 1749 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 1750 | mytid[2:0] <= i[2:0]; |
| 1751 | end // } |
| 1752 | end // } |
| 1753 | |
| 1754 | end // if} |
| 1755 | end // for} |
| 1756 | |
| 1757 | end // if} |
| 1758 | |
| 1759 | //---------------------------------------------------------- |
| 1760 | // wr_en means that the write is occurring |
| 1761 | if (wr_en) begin // { |
| 1762 | //fifo.pop_fifo ({hwtw,mytid}); |
| 1763 | mytnum = (mycid * 8) + mytid; |
| 1764 | |
| 1765 | //-------------------- |
| 1766 | if (dbg_in) begin // { |
| 1767 | begin // axis tbcall_region |
| 1768 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 1769 | end |
| 1770 | |
| 1771 | begin // axis tbcall_region |
| 1772 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 1773 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 1774 | end |
| 1775 | |
| 1776 | begin // axis tbcall_region |
| 1777 | case (tte_page_mask) |
| 1778 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 1779 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1780 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 1781 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1782 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 1783 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1784 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 1785 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 1786 | endcase |
| 1787 | |
| 1788 | if (hwtw) $display (" (hwtw)"); |
| 1789 | else $display (""); |
| 1790 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 1791 | |
| 1792 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 1793 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 1794 | end |
| 1795 | end // } |
| 1796 | //-------------------- |
| 1797 | |
| 1798 | end // } |
| 1799 | |
| 1800 | end // always} |
| 1801 | |
| 1802 | `endif |
| 1803 | //---------------------------------------------------------- |
| 1804 | endmodule |
| 1805 | |
| 1806 | module dtlb_wr_c2 (dbg_in); |
| 1807 | `ifndef GATESIM |
| 1808 | |
| 1809 | parameter NUM_TLB=128; |
| 1810 | |
| 1811 | wire [7:0] data_in; |
| 1812 | wire [7:0] tlb_wr; |
| 1813 | wire wr_en; |
| 1814 | wire [7:0] entry; |
| 1815 | wire [7:0] asi_num; |
| 1816 | wire asi_enable0; // 1 per thread group |
| 1817 | wire asi_enable1; |
| 1818 | // wire [7:0] store_asi; // 1 per thread |
| 1819 | wire [3:0] demap; |
| 1820 | reg [3:0] demap_1; |
| 1821 | wire demap_page; |
| 1822 | wire demap_context; |
| 1823 | wire demap_real; |
| 1824 | wire demap_all; |
| 1825 | wire skip_demap; |
| 1826 | wire demap_active; |
| 1827 | wire auto_demap; |
| 1828 | wire [2:0] demap_tid; |
| 1829 | reg [2:0] demap_tid_1; |
| 1830 | reg [5:0] demap_tnum_1; |
| 1831 | input dbg_in; |
| 1832 | |
| 1833 | reg [(`TS_WIDTH-1):0] tstamp; |
| 1834 | reg hwtw; |
| 1835 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 1836 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 1837 | |
| 1838 | reg [2:0] mytid; |
| 1839 | reg [5:0] mytnum; |
| 1840 | wire [2:0] mycid; |
| 1841 | integer junk; |
| 1842 | integer i; |
| 1843 | reg [7:0] cnt; |
| 1844 | |
| 1845 | assign mycid = 2; |
| 1846 | |
| 1847 | //---------------------------------------------------------- |
| 1848 | // Instantiate fifo - 1 entry per thread |
| 1849 | //fifo fifo (); |
| 1850 | // Define fifo parameters |
| 1851 | `ifndef PALLADIUM |
| 1852 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 1853 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 1854 | defparam fifo.PTR_BITS = 4; |
| 1855 | `endif |
| 1856 | |
| 1857 | //---------------------------------------------------------- |
| 1858 | // DUT probes |
| 1859 | |
| 1860 | assign data_in = `SPC2.mmu.asi.wrote_dtlb; |
| 1861 | assign tlb_wr = `SPC2.mmu_reload_done; |
| 1862 | assign wr_en = `SPC2.lsu.tlb.tlb_wr_1_in_dout; |
| 1863 | |
| 1864 | assign entry = `SPC2.lsu.tlb.rw_index_1[6:0]; |
| 1865 | |
| 1866 | // assign asi_num = `PROBES0.asi_num; |
| 1867 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 1868 | // !`PROBES0.tlb_bypass_b & |
| 1869 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 1870 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 1871 | // !`PROBES0.tlb_bypass_b & |
| 1872 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 1873 | |
| 1874 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 1875 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 1876 | |
| 1877 | |
| 1878 | assign demap_page = `SPC2.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 1879 | assign demap_context = `SPC2.lsu.tlc_demap_context; |
| 1880 | assign demap_real = `SPC2.lsu.tlc_demap_real; |
| 1881 | assign demap_all = `SPC2.lsu.tlc_demap_all; |
| 1882 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 1883 | assign skip_demap =`SPC2.lsu.tlc_wr_u_en; |
| 1884 | assign demap_tid = `SPC2.lsu.tld.tte1[37:35]; |
| 1885 | |
| 1886 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 1887 | assign demap_active = |demap_1 && !skip_demap; |
| 1888 | assign auto_demap = |demap_1 && skip_demap; |
| 1889 | |
| 1890 | //--------------------- |
| 1891 | // Probes for debugging |
| 1892 | |
| 1893 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 1894 | |
| 1895 | // n2_tlb_tl_128x59_cam.sv |
| 1896 | |
| 1897 | `define CNTX1_HI 65 |
| 1898 | `define CNTX1_LO 53 |
| 1899 | `define PID_HI 52 |
| 1900 | `define PID_LO 50 |
| 1901 | `define REAL_BIT 49 |
| 1902 | `define VA_47 48 |
| 1903 | `define VA_28 29 |
| 1904 | `define VA_27 28 |
| 1905 | `define VA_22 23 |
| 1906 | `define TTE_VALID 22 |
| 1907 | `define VA_21 21 |
| 1908 | `define VA_16 16 |
| 1909 | `define VA_15 15 |
| 1910 | `define VA_13 13 |
| 1911 | `define CNTX0_HI 12 |
| 1912 | `define CNTX0_LO 0 |
| 1913 | |
| 1914 | // n2_tlb_tl_128x59_ram.sv |
| 1915 | |
| 1916 | `define DATA_PARITY 36 |
| 1917 | `define DATA_PA_39_28_HI 35 |
| 1918 | `define DATA_PA_39_28_LO 24 |
| 1919 | `define DATA_PA_27_22_HI 23 |
| 1920 | `define DATA_PA_27_22_LO 18 |
| 1921 | `define DATA_VA_27_22_V 17 |
| 1922 | `define DATA_PA_21_16_HI 16 |
| 1923 | `define DATA_PA_21_16_LO 11 |
| 1924 | `define DATA_VA_21_16_V 10 |
| 1925 | `define DATA_PA_15_13_HI 9 |
| 1926 | `define DATA_PA_15_13_LO 7 |
| 1927 | `define DATA_VA_15_13_V 6 |
| 1928 | `define DATA_NFO 5 |
| 1929 | `define DATA_IE 4 |
| 1930 | `define DATA_CP 3 |
| 1931 | `define DATA_X 2 |
| 1932 | `define DATA_P 1 |
| 1933 | `define DATA_W 0 |
| 1934 | |
| 1935 | wire [(NUM_TLB-1):0] tlb_valid; |
| 1936 | wire [(NUM_TLB-1):0] tlb_match; |
| 1937 | wire tte_valid; |
| 1938 | wire [47:0] tte_va; |
| 1939 | wire [12:0] tte_context; |
| 1940 | wire tte_real; |
| 1941 | wire [2:0] tte_pid; |
| 1942 | wire [2:0] tte_page_mask; |
| 1943 | wire [39:0] tte_pa; |
| 1944 | wire tte_nfo; |
| 1945 | wire tte_ie; |
| 1946 | wire tte_cp; |
| 1947 | wire tte_e; |
| 1948 | wire tte_p; |
| 1949 | wire tte_w; |
| 1950 | wire tte_ep; |
| 1951 | |
| 1952 | |
| 1953 | assign tlb_valid = `SPC2.lsu.tlb.array.cam.valid; |
| 1954 | assign tlb_match = `SPC2.lsu.tlb.array.cam.match; |
| 1955 | |
| 1956 | assign tte_va = {`SPC2.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 1957 | `SPC2.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 1958 | `SPC2.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 1959 | `SPC2.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 1960 | 13'b0 |
| 1961 | }; |
| 1962 | assign tte_context = `SPC2.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 1963 | assign tte_pid = `SPC2.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 1964 | assign tte_real = `SPC2.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 1965 | assign tte_valid = `SPC2.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 1966 | |
| 1967 | assign tte_page_mask = `SPC2.lsu.tlb.tte_page_size_mask_1; |
| 1968 | |
| 1969 | assign tte_pa = {`SPC2.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 1970 | `SPC2.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 1971 | `SPC2.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 1972 | `SPC2.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 1973 | 13'b0 |
| 1974 | }; |
| 1975 | assign tte_nfo = `SPC2.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 1976 | assign tte_ie = `SPC2.lsu.tlb.tte_data_1[`DATA_IE]; |
| 1977 | assign tte_cp = `SPC2.lsu.tlb.tte_data_1[`DATA_CP]; |
| 1978 | assign tte_e = `SPC2.lsu.tlb.tte_data_1[`DATA_X]; |
| 1979 | assign tte_p = `SPC2.lsu.tlb.tte_data_1[`DATA_P]; |
| 1980 | assign tte_w = `SPC2.lsu.tlb.tte_data_1[`DATA_W]; |
| 1981 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 1982 | |
| 1983 | //---------------------------------------------------------- |
| 1984 | // Initialize state machine to idle state |
| 1985 | initial begin // { |
| 1986 | `ifndef PALLADIUM |
| 1987 | #1; |
| 1988 | `endif |
| 1989 | hwtw = 1'b0; |
| 1990 | //for (i=0; i<=7; i=i+1) begin |
| 1991 | // my_asi[i] = 8'b0; |
| 1992 | //end |
| 1993 | |
| 1994 | end // } |
| 1995 | |
| 1996 | //---------------------------------------------------------- |
| 1997 | // Must use negedge to avoid race condition |
| 1998 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 1999 | |
| 2000 | always @ (negedge `CPU.l2clk) begin // { |
| 2001 | |
| 2002 | tstamp = `TOP.cycle; |
| 2003 | demap_tstamp = `TOP.cycle; |
| 2004 | |
| 2005 | // Delay by 1 cycle to align with skip_demap |
| 2006 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 2007 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 2008 | demap_1 <= demap; |
| 2009 | |
| 2010 | //---------------------------------------------------------- |
| 2011 | // Send I/DTLBWRITE due to demap |
| 2012 | // |
| 2013 | |
| 2014 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 2015 | $display("tlb_sync", `ERROR, |
| 2016 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 2017 | mycid,demap_tid_1); |
| 2018 | end // } |
| 2019 | |
| 2020 | //if (demap_active) begin // { |
| 2021 | // fifo.pop_fifo ({hwtw,mytid}); |
| 2022 | //end //} |
| 2023 | |
| 2024 | //-------------------- |
| 2025 | if (dbg_in & (|demap_1)) begin // { |
| 2026 | begin // axis tbcall_region |
| 2027 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 2028 | end |
| 2029 | |
| 2030 | if (demap_active) begin |
| 2031 | begin // axis tbcall_region |
| 2032 | case (demap_1) |
| 2033 | 4'b0001: $write ("type=real "); |
| 2034 | 4'b0010: $write ("type=cntx "); |
| 2035 | 4'b0100: $write ("type=page "); |
| 2036 | 4'b1000: $write ("type=all "); |
| 2037 | default: |
| 2038 | $display ("tlb_sync", `ERROR, |
| 2039 | "Bench Problem - demap_1 should be one-hot."); |
| 2040 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 2041 | endcase |
| 2042 | end |
| 2043 | end |
| 2044 | else begin |
| 2045 | begin // axis tbcall_region |
| 2046 | $write ("type=autodemap "); |
| 2047 | end |
| 2048 | end |
| 2049 | |
| 2050 | begin // axis tbcall_region |
| 2051 | $display ("match=%h ts=%0d", |
| 2052 | tlb_match,demap_tstamp*`TOP.core_period); |
| 2053 | end |
| 2054 | |
| 2055 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 2056 | if (tlb_match[cnt]==1'b1) begin // { |
| 2057 | begin // axis tbcall_region |
| 2058 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 2059 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 2060 | end |
| 2061 | end // } |
| 2062 | end // } |
| 2063 | //-------------------- |
| 2064 | end // } |
| 2065 | |
| 2066 | //---------------------------------------------------------- |
| 2067 | // Send I/DHWTW due to HWTW |
| 2068 | // Send I/DTLBWRITE due to ASI write |
| 2069 | |
| 2070 | // Save asi num when DTLBREAD happens. |
| 2071 | // Otherwise, hold state. |
| 2072 | // Send asi num later with DHWTW |
| 2073 | // for (i=0;i<=7;i=i+1) begin // { |
| 2074 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 2075 | // end // } |
| 2076 | |
| 2077 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 2078 | // These signals will be interleaved between the threads. |
| 2079 | // Need to queue up the signals over time so they can be processed in order. |
| 2080 | // Each thread will only be doing 1 thing at a time. |
| 2081 | |
| 2082 | for (i=0;i<=7;i=i+1) begin // { |
| 2083 | |
| 2084 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 2085 | |
| 2086 | // data_in[tid] determines which thread will write next |
| 2087 | // Use fifo to save the tids of the data_in signals in order |
| 2088 | |
| 2089 | if (data_in[i]) begin // { |
| 2090 | mytid[2:0] <= i[2:0]; |
| 2091 | if (tlb_wr[i]) begin // { |
| 2092 | hwtw <= 1'b1; |
| 2093 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 2094 | end // } |
| 2095 | else begin // { |
| 2096 | hwtw <= 1'b0; |
| 2097 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 2098 | end // } |
| 2099 | end // } |
| 2100 | |
| 2101 | end // } |
| 2102 | |
| 2103 | //---------------------------------------------------------- |
| 2104 | // wr_en means that the write is occurring |
| 2105 | if (wr_en) begin // { |
| 2106 | //fifo.pop_fifo ({hwtw,mytid}); |
| 2107 | mytnum = (mycid * 8) + mytid; |
| 2108 | |
| 2109 | //-------------------- |
| 2110 | if (dbg_in) begin // { |
| 2111 | begin // axis tbcall_region |
| 2112 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 2113 | |
| 2114 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 2115 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 2116 | |
| 2117 | case (tte_page_mask) |
| 2118 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 2119 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2120 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 2121 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2122 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 2123 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2124 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 2125 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2126 | endcase |
| 2127 | |
| 2128 | if (hwtw) $display (" (hwtw)"); |
| 2129 | else $display (""); |
| 2130 | |
| 2131 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 2132 | |
| 2133 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 2134 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 2135 | end // } |
| 2136 | //-------------------- |
| 2137 | |
| 2138 | end // } |
| 2139 | end // } |
| 2140 | |
| 2141 | end // always} |
| 2142 | |
| 2143 | //---------------------------------------------------------- |
| 2144 | `endif |
| 2145 | |
| 2146 | endmodule |
| 2147 | `endif |
| 2148 | |
| 2149 | //---------------------------------------------------------- |
| 2150 | //---------------------------------------------------------- |
| 2151 | |
| 2152 | |
| 2153 | `ifdef CORE_3 |
| 2154 | |
| 2155 | module itlb_wr_c3 (dbg_in); |
| 2156 | `ifndef GATESIM |
| 2157 | |
| 2158 | parameter NUM_TLB=64; |
| 2159 | |
| 2160 | wire [7:0] data_in; |
| 2161 | wire [7:0] tlb_wr; |
| 2162 | wire wr_en; |
| 2163 | wire [7:0] entry; |
| 2164 | wire [3:0] demap; |
| 2165 | reg [3:0] demap_1; |
| 2166 | wire demap_page; |
| 2167 | wire demap_context; |
| 2168 | wire demap_real; |
| 2169 | wire demap_all; |
| 2170 | wire skip_demap; |
| 2171 | wire demap_active; |
| 2172 | wire auto_demap; |
| 2173 | wire [2:0] demap_tid; |
| 2174 | reg [2:0] demap_tid_1; |
| 2175 | reg [5:0] demap_tnum_1; |
| 2176 | wire [7:0] asi_wr_itlb; |
| 2177 | wire [7:0] asi_wr_itlb_demap; |
| 2178 | wire [7:0] asi_wr_itlb_data_in; |
| 2179 | wire [7:0] asi_wr_itlb_data_access; |
| 2180 | input dbg_in; |
| 2181 | |
| 2182 | reg [(`TS_WIDTH-1):0] tstamp; |
| 2183 | reg [7:0] data_in_ready; |
| 2184 | reg hwtw; |
| 2185 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 2186 | reg dbg_en; |
| 2187 | |
| 2188 | reg [2:0] mytid; |
| 2189 | reg [5:0] mytnum; |
| 2190 | wire [2:0] mycid; |
| 2191 | integer junk; |
| 2192 | integer i; |
| 2193 | reg [7:0] cnt; |
| 2194 | |
| 2195 | assign mycid = 3; |
| 2196 | |
| 2197 | //---------------------------------------------------------- |
| 2198 | // Instantiate fifo - 1 entry per thread |
| 2199 | //fifo fifo (); |
| 2200 | // Define fifo parameters |
| 2201 | `ifndef PALLADIUM |
| 2202 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 2203 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 2204 | defparam fifo.PTR_BITS = 4; |
| 2205 | `endif |
| 2206 | |
| 2207 | //---------------------------------------------------------- |
| 2208 | // DUT probes |
| 2209 | |
| 2210 | assign data_in = `SPC3.mmu.asi.htc_wr_itlb_data_in; |
| 2211 | assign wr_en = `SPC3.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 2212 | |
| 2213 | assign entry = `SPC3.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 2214 | |
| 2215 | assign demap_page = `SPC3.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 2216 | assign demap_context = `SPC3.ifu_ftu.itc_demap_context; |
| 2217 | assign demap_real = `SPC3.ifu_ftu.itc_demap_real; |
| 2218 | assign demap_all = `SPC3.ifu_ftu.itc_demap_all; |
| 2219 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 2220 | assign skip_demap = `SPC3.ifu_ftu.itc_wr_u_en; |
| 2221 | assign demap_tid = `SPC3.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 2222 | |
| 2223 | |
| 2224 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 2225 | assign demap_active = |demap_1 && !skip_demap; |
| 2226 | assign auto_demap = |demap_1 && skip_demap; |
| 2227 | wire [7:0] itlb_wr = {(`SPC3.tlu.trl1.take_itw & `SPC3.tlu.trl1.trap[3]), |
| 2228 | (`SPC3.tlu.trl1.take_itw & `SPC3.tlu.trl1.trap[2]), |
| 2229 | (`SPC3.tlu.trl1.take_itw & `SPC3.tlu.trl1.trap[1]), |
| 2230 | (`SPC3.tlu.trl1.take_itw & `SPC3.tlu.trl1.trap[0]), |
| 2231 | (`SPC3.tlu.trl0.take_itw & `SPC3.tlu.trl0.trap[3]), |
| 2232 | (`SPC3.tlu.trl0.take_itw & `SPC3.tlu.trl0.trap[2]), |
| 2233 | (`SPC3.tlu.trl0.take_itw & `SPC3.tlu.trl0.trap[1]), |
| 2234 | (`SPC3.tlu.trl0.take_itw & `SPC3.tlu.trl0.trap[0]) |
| 2235 | }; |
| 2236 | |
| 2237 | assign tlb_wr = itlb_wr; |
| 2238 | |
| 2239 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 2240 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 2241 | // These signals assert before the MMU reorders the TLB writes. |
| 2242 | // Use these to suppress SSTEP in nas_pipe. |
| 2243 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 2244 | assign asi_wr_itlb_demap = `SPC3.mmu.asi_wr_immu_demap; |
| 2245 | assign asi_wr_itlb_data_in = `SPC3.mmu.asi_wr_itlb_data_in; |
| 2246 | assign asi_wr_itlb_data_access = {`SPC3.mmu.asd1.asi_wr_itlb_data_access, |
| 2247 | `SPC3.mmu.asd0.asi_wr_itlb_data_access}; |
| 2248 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 2249 | |
| 2250 | //--------------------- |
| 2251 | // Probes for debugging |
| 2252 | |
| 2253 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 2254 | |
| 2255 | // n2_tlb_tl_64x59_cam.sv |
| 2256 | |
| 2257 | `define CNTX1_HI 65 |
| 2258 | `define CNTX1_LO 53 |
| 2259 | `define PID_HI 52 |
| 2260 | `define PID_LO 50 |
| 2261 | `define REAL_BIT 49 |
| 2262 | `define VA_47 48 |
| 2263 | `define VA_28 29 |
| 2264 | `define VA_27 28 |
| 2265 | `define VA_22 23 |
| 2266 | `define TTE_VALID 22 |
| 2267 | `define VA_21 21 |
| 2268 | `define VA_16 16 |
| 2269 | `define VA_15 15 |
| 2270 | `define VA_13 13 |
| 2271 | `define CNTX0_HI 12 |
| 2272 | `define CNTX0_LO 0 |
| 2273 | |
| 2274 | // n2_tlb_tl_64x59_ram.sv |
| 2275 | |
| 2276 | `define DATA_PARITY 36 |
| 2277 | `define DATA_PA_39_28_HI 35 |
| 2278 | `define DATA_PA_39_28_LO 24 |
| 2279 | `define DATA_PA_27_22_HI 23 |
| 2280 | `define DATA_PA_27_22_LO 18 |
| 2281 | `define DATA_VA_27_22_V 17 |
| 2282 | `define DATA_PA_21_16_HI 16 |
| 2283 | `define DATA_PA_21_16_LO 11 |
| 2284 | `define DATA_VA_21_16_V 10 |
| 2285 | `define DATA_PA_15_13_HI 9 |
| 2286 | `define DATA_PA_15_13_LO 7 |
| 2287 | `define DATA_VA_15_13_V 6 |
| 2288 | `define DATA_NFO 5 |
| 2289 | `define DATA_IE 4 |
| 2290 | `define DATA_CP 3 |
| 2291 | `define DATA_X 2 |
| 2292 | `define DATA_P 1 |
| 2293 | `define DATA_W 0 |
| 2294 | |
| 2295 | wire [(NUM_TLB-1):0] tlb_valid; |
| 2296 | wire [(NUM_TLB-1):0] tlb_match; |
| 2297 | wire tte_valid; |
| 2298 | wire [47:0] tte_va; |
| 2299 | wire [12:0] tte_context; |
| 2300 | wire tte_real; |
| 2301 | wire [2:0] tte_pid; |
| 2302 | wire [2:0] tte_page_mask; |
| 2303 | wire [39:0] tte_pa; |
| 2304 | wire tte_nfo; |
| 2305 | wire tte_ie; |
| 2306 | wire tte_cp; |
| 2307 | wire tte_e; |
| 2308 | wire tte_p; |
| 2309 | wire tte_w; |
| 2310 | wire tte_ep; |
| 2311 | |
| 2312 | assign tlb_valid = `SPC3.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 2313 | assign tlb_match = `SPC3.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 2314 | |
| 2315 | assign tte_va = {`SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 2316 | `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 2317 | `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 2318 | `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 2319 | 13'b0 |
| 2320 | }; |
| 2321 | assign tte_context = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 2322 | assign tte_pid = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 2323 | assign tte_real = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 2324 | assign tte_valid = `SPC3.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 2325 | |
| 2326 | assign tte_page_mask = `SPC3.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 2327 | |
| 2328 | assign tte_pa = {`SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 2329 | `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 2330 | `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 2331 | `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 2332 | 13'b0 |
| 2333 | }; |
| 2334 | assign tte_nfo = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 2335 | assign tte_ie = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 2336 | assign tte_cp = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 2337 | assign tte_e = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 2338 | assign tte_p = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 2339 | assign tte_w = `SPC3.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 2340 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 2341 | |
| 2342 | //---------------------------------------------------------- |
| 2343 | initial begin // { |
| 2344 | `ifndef PALLADIUM |
| 2345 | #1; |
| 2346 | `endif |
| 2347 | hwtw = 1'b0; |
| 2348 | data_in_ready = 8'b0; |
| 2349 | end // } |
| 2350 | |
| 2351 | //---------------------------------------------------------- |
| 2352 | // Must use negedge to avoid race condition |
| 2353 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 2354 | |
| 2355 | always @ (negedge `CPU.l2clk) begin // { |
| 2356 | |
| 2357 | tstamp = `TOP.cycle; |
| 2358 | demap_tstamp = `TOP.cycle; |
| 2359 | |
| 2360 | // Delay by 1 cycle to align with skip_demap |
| 2361 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 2362 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 2363 | demap_1 <= demap; |
| 2364 | |
| 2365 | |
| 2366 | //---------------------------------------------------------- |
| 2367 | // Send I/DTLBWRITE due to demap |
| 2368 | // |
| 2369 | |
| 2370 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 2371 | $display("tlb_sync", `ERROR, |
| 2372 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 2373 | mycid,demap_tid_1); |
| 2374 | end // } |
| 2375 | |
| 2376 | //if (demap_active) begin // { |
| 2377 | // fifo.pop_fifo ({hwtw,mytid}); |
| 2378 | //end |
| 2379 | //-------------------- |
| 2380 | if (dbg_in & (|demap_1)) begin // { |
| 2381 | begin // axis tbcall_region |
| 2382 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 2383 | end |
| 2384 | |
| 2385 | if (demap_active) begin |
| 2386 | begin // axis tbcall_region |
| 2387 | case (demap_1) |
| 2388 | 4'b0001: $write ("type=real "); |
| 2389 | 4'b0010: $write ("type=cntx "); |
| 2390 | 4'b0100: $write ("type=page "); |
| 2391 | 4'b1000: $write ("type=all "); |
| 2392 | default: |
| 2393 | $display ("tlb_sync", `ERROR, |
| 2394 | "Bench Problem - demap_1() should be one-hot."); |
| 2395 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 2396 | endcase |
| 2397 | end |
| 2398 | end |
| 2399 | else begin |
| 2400 | begin // axis tbcall_region |
| 2401 | $write("type=autodemap "); |
| 2402 | end |
| 2403 | end |
| 2404 | |
| 2405 | begin // axis tbcall_region |
| 2406 | $display ("match=%h ts=%0d", |
| 2407 | tlb_match,demap_tstamp*`TOP.core_period); |
| 2408 | end |
| 2409 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 2410 | if (tlb_match[cnt]==1'b1) begin // { |
| 2411 | begin // axis tbcall_region |
| 2412 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 2413 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 2414 | end |
| 2415 | end // } |
| 2416 | end // } |
| 2417 | |
| 2418 | end // } |
| 2419 | |
| 2420 | //---------------------------------------------------------- |
| 2421 | // Send I/DHWTW due to HWTW |
| 2422 | // Send I/DTLBWRITE due to ASI write |
| 2423 | |
| 2424 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 2425 | // These signals will be interleaved between the threads. |
| 2426 | // Need to queue up the signals over time so they can be processed in order. |
| 2427 | // Each thread will only be doing 1 thing at a time. |
| 2428 | |
| 2429 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 2430 | |
| 2431 | for (i=0;i<=7;i=i+1) begin // { |
| 2432 | |
| 2433 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 2434 | $display ("tlb_sync", `ERROR, |
| 2435 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 2436 | end // } |
| 2437 | else begin // { |
| 2438 | |
| 2439 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 2440 | if (data_in[i]) begin // { |
| 2441 | data_in_ready[i] <= 1'b1; |
| 2442 | end // } |
| 2443 | |
| 2444 | // tlb_wr[tid] determines which thread will write next |
| 2445 | // Use fifo to save the tids of the tlb_wr signals in order |
| 2446 | if (tlb_wr[i]) begin // { |
| 2447 | if (data_in_ready[i]) begin // { |
| 2448 | hwtw <= 1'b1; |
| 2449 | mytid[2:0] <= i[2:0]; |
| 2450 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 2451 | data_in_ready[i] <= 1'b0; |
| 2452 | end // } |
| 2453 | else begin // { |
| 2454 | hwtw <= 1'b0; |
| 2455 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 2456 | mytid[2:0] <= i[2:0]; |
| 2457 | end // } |
| 2458 | end // } |
| 2459 | |
| 2460 | end // if} |
| 2461 | end // for} |
| 2462 | |
| 2463 | end // if} |
| 2464 | |
| 2465 | //---------------------------------------------------------- |
| 2466 | // wr_en means that the write is occurring |
| 2467 | if (wr_en) begin // { |
| 2468 | //fifo.pop_fifo ({hwtw,mytid}); |
| 2469 | mytnum = (mycid * 8) + mytid; |
| 2470 | |
| 2471 | //-------------------- |
| 2472 | if (dbg_in) begin // { |
| 2473 | begin // axis tbcall_region |
| 2474 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 2475 | end |
| 2476 | |
| 2477 | begin // axis tbcall_region |
| 2478 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 2479 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 2480 | end |
| 2481 | |
| 2482 | begin // axis tbcall_region |
| 2483 | case (tte_page_mask) |
| 2484 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 2485 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2486 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 2487 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2488 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 2489 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2490 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 2491 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2492 | endcase |
| 2493 | |
| 2494 | if (hwtw) $display (" (hwtw)"); |
| 2495 | else $display (""); |
| 2496 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 2497 | |
| 2498 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 2499 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 2500 | end |
| 2501 | end // } |
| 2502 | //-------------------- |
| 2503 | |
| 2504 | end // } |
| 2505 | |
| 2506 | end // always} |
| 2507 | |
| 2508 | `endif |
| 2509 | //---------------------------------------------------------- |
| 2510 | endmodule |
| 2511 | |
| 2512 | module dtlb_wr_c3 (dbg_in); |
| 2513 | `ifndef GATESIM |
| 2514 | |
| 2515 | parameter NUM_TLB=128; |
| 2516 | |
| 2517 | wire [7:0] data_in; |
| 2518 | wire [7:0] tlb_wr; |
| 2519 | wire wr_en; |
| 2520 | wire [7:0] entry; |
| 2521 | wire [7:0] asi_num; |
| 2522 | wire asi_enable0; // 1 per thread group |
| 2523 | wire asi_enable1; |
| 2524 | // wire [7:0] store_asi; // 1 per thread |
| 2525 | wire [3:0] demap; |
| 2526 | reg [3:0] demap_1; |
| 2527 | wire demap_page; |
| 2528 | wire demap_context; |
| 2529 | wire demap_real; |
| 2530 | wire demap_all; |
| 2531 | wire skip_demap; |
| 2532 | wire demap_active; |
| 2533 | wire auto_demap; |
| 2534 | wire [2:0] demap_tid; |
| 2535 | reg [2:0] demap_tid_1; |
| 2536 | reg [5:0] demap_tnum_1; |
| 2537 | input dbg_in; |
| 2538 | |
| 2539 | reg [(`TS_WIDTH-1):0] tstamp; |
| 2540 | reg hwtw; |
| 2541 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 2542 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 2543 | |
| 2544 | reg [2:0] mytid; |
| 2545 | reg [5:0] mytnum; |
| 2546 | wire [2:0] mycid; |
| 2547 | integer junk; |
| 2548 | integer i; |
| 2549 | reg [7:0] cnt; |
| 2550 | |
| 2551 | assign mycid = 3; |
| 2552 | |
| 2553 | //---------------------------------------------------------- |
| 2554 | // Instantiate fifo - 1 entry per thread |
| 2555 | //fifo fifo (); |
| 2556 | // Define fifo parameters |
| 2557 | `ifndef PALLADIUM |
| 2558 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 2559 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 2560 | defparam fifo.PTR_BITS = 4; |
| 2561 | `endif |
| 2562 | |
| 2563 | //---------------------------------------------------------- |
| 2564 | // DUT probes |
| 2565 | |
| 2566 | assign data_in = `SPC3.mmu.asi.wrote_dtlb; |
| 2567 | assign tlb_wr = `SPC3.mmu_reload_done; |
| 2568 | assign wr_en = `SPC3.lsu.tlb.tlb_wr_1_in_dout; |
| 2569 | |
| 2570 | assign entry = `SPC3.lsu.tlb.rw_index_1[6:0]; |
| 2571 | |
| 2572 | // assign asi_num = `PROBES0.asi_num; |
| 2573 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 2574 | // !`PROBES0.tlb_bypass_b & |
| 2575 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 2576 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 2577 | // !`PROBES0.tlb_bypass_b & |
| 2578 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 2579 | |
| 2580 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 2581 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 2582 | |
| 2583 | |
| 2584 | assign demap_page = `SPC3.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 2585 | assign demap_context = `SPC3.lsu.tlc_demap_context; |
| 2586 | assign demap_real = `SPC3.lsu.tlc_demap_real; |
| 2587 | assign demap_all = `SPC3.lsu.tlc_demap_all; |
| 2588 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 2589 | assign skip_demap =`SPC3.lsu.tlc_wr_u_en; |
| 2590 | assign demap_tid = `SPC3.lsu.tld.tte1[37:35]; |
| 2591 | |
| 2592 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 2593 | assign demap_active = |demap_1 && !skip_demap; |
| 2594 | assign auto_demap = |demap_1 && skip_demap; |
| 2595 | |
| 2596 | //--------------------- |
| 2597 | // Probes for debugging |
| 2598 | |
| 2599 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 2600 | |
| 2601 | // n2_tlb_tl_128x59_cam.sv |
| 2602 | |
| 2603 | `define CNTX1_HI 65 |
| 2604 | `define CNTX1_LO 53 |
| 2605 | `define PID_HI 52 |
| 2606 | `define PID_LO 50 |
| 2607 | `define REAL_BIT 49 |
| 2608 | `define VA_47 48 |
| 2609 | `define VA_28 29 |
| 2610 | `define VA_27 28 |
| 2611 | `define VA_22 23 |
| 2612 | `define TTE_VALID 22 |
| 2613 | `define VA_21 21 |
| 2614 | `define VA_16 16 |
| 2615 | `define VA_15 15 |
| 2616 | `define VA_13 13 |
| 2617 | `define CNTX0_HI 12 |
| 2618 | `define CNTX0_LO 0 |
| 2619 | |
| 2620 | // n2_tlb_tl_128x59_ram.sv |
| 2621 | |
| 2622 | `define DATA_PARITY 36 |
| 2623 | `define DATA_PA_39_28_HI 35 |
| 2624 | `define DATA_PA_39_28_LO 24 |
| 2625 | `define DATA_PA_27_22_HI 23 |
| 2626 | `define DATA_PA_27_22_LO 18 |
| 2627 | `define DATA_VA_27_22_V 17 |
| 2628 | `define DATA_PA_21_16_HI 16 |
| 2629 | `define DATA_PA_21_16_LO 11 |
| 2630 | `define DATA_VA_21_16_V 10 |
| 2631 | `define DATA_PA_15_13_HI 9 |
| 2632 | `define DATA_PA_15_13_LO 7 |
| 2633 | `define DATA_VA_15_13_V 6 |
| 2634 | `define DATA_NFO 5 |
| 2635 | `define DATA_IE 4 |
| 2636 | `define DATA_CP 3 |
| 2637 | `define DATA_X 2 |
| 2638 | `define DATA_P 1 |
| 2639 | `define DATA_W 0 |
| 2640 | |
| 2641 | wire [(NUM_TLB-1):0] tlb_valid; |
| 2642 | wire [(NUM_TLB-1):0] tlb_match; |
| 2643 | wire tte_valid; |
| 2644 | wire [47:0] tte_va; |
| 2645 | wire [12:0] tte_context; |
| 2646 | wire tte_real; |
| 2647 | wire [2:0] tte_pid; |
| 2648 | wire [2:0] tte_page_mask; |
| 2649 | wire [39:0] tte_pa; |
| 2650 | wire tte_nfo; |
| 2651 | wire tte_ie; |
| 2652 | wire tte_cp; |
| 2653 | wire tte_e; |
| 2654 | wire tte_p; |
| 2655 | wire tte_w; |
| 2656 | wire tte_ep; |
| 2657 | |
| 2658 | |
| 2659 | assign tlb_valid = `SPC3.lsu.tlb.array.cam.valid; |
| 2660 | assign tlb_match = `SPC3.lsu.tlb.array.cam.match; |
| 2661 | |
| 2662 | assign tte_va = {`SPC3.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 2663 | `SPC3.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 2664 | `SPC3.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 2665 | `SPC3.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 2666 | 13'b0 |
| 2667 | }; |
| 2668 | assign tte_context = `SPC3.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 2669 | assign tte_pid = `SPC3.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 2670 | assign tte_real = `SPC3.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 2671 | assign tte_valid = `SPC3.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 2672 | |
| 2673 | assign tte_page_mask = `SPC3.lsu.tlb.tte_page_size_mask_1; |
| 2674 | |
| 2675 | assign tte_pa = {`SPC3.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 2676 | `SPC3.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 2677 | `SPC3.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 2678 | `SPC3.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 2679 | 13'b0 |
| 2680 | }; |
| 2681 | assign tte_nfo = `SPC3.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 2682 | assign tte_ie = `SPC3.lsu.tlb.tte_data_1[`DATA_IE]; |
| 2683 | assign tte_cp = `SPC3.lsu.tlb.tte_data_1[`DATA_CP]; |
| 2684 | assign tte_e = `SPC3.lsu.tlb.tte_data_1[`DATA_X]; |
| 2685 | assign tte_p = `SPC3.lsu.tlb.tte_data_1[`DATA_P]; |
| 2686 | assign tte_w = `SPC3.lsu.tlb.tte_data_1[`DATA_W]; |
| 2687 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 2688 | |
| 2689 | //---------------------------------------------------------- |
| 2690 | // Initialize state machine to idle state |
| 2691 | initial begin // { |
| 2692 | `ifndef PALLADIUM |
| 2693 | #1; |
| 2694 | `endif |
| 2695 | hwtw = 1'b0; |
| 2696 | //for (i=0; i<=7; i=i+1) begin |
| 2697 | // my_asi[i] = 8'b0; |
| 2698 | //end |
| 2699 | |
| 2700 | end // } |
| 2701 | |
| 2702 | //---------------------------------------------------------- |
| 2703 | // Must use negedge to avoid race condition |
| 2704 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 2705 | |
| 2706 | always @ (negedge `CPU.l2clk) begin // { |
| 2707 | |
| 2708 | tstamp = `TOP.cycle; |
| 2709 | demap_tstamp = `TOP.cycle; |
| 2710 | |
| 2711 | // Delay by 1 cycle to align with skip_demap |
| 2712 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 2713 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 2714 | demap_1 <= demap; |
| 2715 | |
| 2716 | //---------------------------------------------------------- |
| 2717 | // Send I/DTLBWRITE due to demap |
| 2718 | // |
| 2719 | |
| 2720 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 2721 | $display("tlb_sync", `ERROR, |
| 2722 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 2723 | mycid,demap_tid_1); |
| 2724 | end // } |
| 2725 | |
| 2726 | //if (demap_active) begin // { |
| 2727 | // fifo.pop_fifo ({hwtw,mytid}); |
| 2728 | //end //} |
| 2729 | |
| 2730 | //-------------------- |
| 2731 | if (dbg_in & (|demap_1)) begin // { |
| 2732 | begin // axis tbcall_region |
| 2733 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 2734 | end |
| 2735 | |
| 2736 | if (demap_active) begin |
| 2737 | begin // axis tbcall_region |
| 2738 | case (demap_1) |
| 2739 | 4'b0001: $write ("type=real "); |
| 2740 | 4'b0010: $write ("type=cntx "); |
| 2741 | 4'b0100: $write ("type=page "); |
| 2742 | 4'b1000: $write ("type=all "); |
| 2743 | default: |
| 2744 | $display ("tlb_sync", `ERROR, |
| 2745 | "Bench Problem - demap_1 should be one-hot."); |
| 2746 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 2747 | endcase |
| 2748 | end |
| 2749 | end |
| 2750 | else begin |
| 2751 | begin // axis tbcall_region |
| 2752 | $write ("type=autodemap "); |
| 2753 | end |
| 2754 | end |
| 2755 | |
| 2756 | begin // axis tbcall_region |
| 2757 | $display ("match=%h ts=%0d", |
| 2758 | tlb_match,demap_tstamp*`TOP.core_period); |
| 2759 | end |
| 2760 | |
| 2761 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 2762 | if (tlb_match[cnt]==1'b1) begin // { |
| 2763 | begin // axis tbcall_region |
| 2764 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 2765 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 2766 | end |
| 2767 | end // } |
| 2768 | end // } |
| 2769 | //-------------------- |
| 2770 | end // } |
| 2771 | |
| 2772 | //---------------------------------------------------------- |
| 2773 | // Send I/DHWTW due to HWTW |
| 2774 | // Send I/DTLBWRITE due to ASI write |
| 2775 | |
| 2776 | // Save asi num when DTLBREAD happens. |
| 2777 | // Otherwise, hold state. |
| 2778 | // Send asi num later with DHWTW |
| 2779 | // for (i=0;i<=7;i=i+1) begin // { |
| 2780 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 2781 | // end // } |
| 2782 | |
| 2783 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 2784 | // These signals will be interleaved between the threads. |
| 2785 | // Need to queue up the signals over time so they can be processed in order. |
| 2786 | // Each thread will only be doing 1 thing at a time. |
| 2787 | |
| 2788 | for (i=0;i<=7;i=i+1) begin // { |
| 2789 | |
| 2790 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 2791 | |
| 2792 | // data_in[tid] determines which thread will write next |
| 2793 | // Use fifo to save the tids of the data_in signals in order |
| 2794 | |
| 2795 | if (data_in[i]) begin // { |
| 2796 | mytid[2:0] <= i[2:0]; |
| 2797 | if (tlb_wr[i]) begin // { |
| 2798 | hwtw <= 1'b1; |
| 2799 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 2800 | end // } |
| 2801 | else begin // { |
| 2802 | hwtw <= 1'b0; |
| 2803 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 2804 | end // } |
| 2805 | end // } |
| 2806 | |
| 2807 | end // } |
| 2808 | |
| 2809 | //---------------------------------------------------------- |
| 2810 | // wr_en means that the write is occurring |
| 2811 | if (wr_en) begin // { |
| 2812 | //fifo.pop_fifo ({hwtw,mytid}); |
| 2813 | mytnum = (mycid * 8) + mytid; |
| 2814 | |
| 2815 | //-------------------- |
| 2816 | if (dbg_in) begin // { |
| 2817 | begin // axis tbcall_region |
| 2818 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 2819 | |
| 2820 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 2821 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 2822 | |
| 2823 | case (tte_page_mask) |
| 2824 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 2825 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2826 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 2827 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2828 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 2829 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2830 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 2831 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 2832 | endcase |
| 2833 | |
| 2834 | if (hwtw) $display (" (hwtw)"); |
| 2835 | else $display (""); |
| 2836 | |
| 2837 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 2838 | |
| 2839 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 2840 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 2841 | end // } |
| 2842 | //-------------------- |
| 2843 | |
| 2844 | end // } |
| 2845 | end // } |
| 2846 | |
| 2847 | end // always} |
| 2848 | |
| 2849 | //---------------------------------------------------------- |
| 2850 | `endif |
| 2851 | |
| 2852 | endmodule |
| 2853 | `endif |
| 2854 | |
| 2855 | //---------------------------------------------------------- |
| 2856 | //---------------------------------------------------------- |
| 2857 | |
| 2858 | |
| 2859 | `ifdef CORE_4 |
| 2860 | |
| 2861 | module itlb_wr_c4 (dbg_in); |
| 2862 | `ifndef GATESIM |
| 2863 | |
| 2864 | parameter NUM_TLB=64; |
| 2865 | |
| 2866 | wire [7:0] data_in; |
| 2867 | wire [7:0] tlb_wr; |
| 2868 | wire wr_en; |
| 2869 | wire [7:0] entry; |
| 2870 | wire [3:0] demap; |
| 2871 | reg [3:0] demap_1; |
| 2872 | wire demap_page; |
| 2873 | wire demap_context; |
| 2874 | wire demap_real; |
| 2875 | wire demap_all; |
| 2876 | wire skip_demap; |
| 2877 | wire demap_active; |
| 2878 | wire auto_demap; |
| 2879 | wire [2:0] demap_tid; |
| 2880 | reg [2:0] demap_tid_1; |
| 2881 | reg [5:0] demap_tnum_1; |
| 2882 | wire [7:0] asi_wr_itlb; |
| 2883 | wire [7:0] asi_wr_itlb_demap; |
| 2884 | wire [7:0] asi_wr_itlb_data_in; |
| 2885 | wire [7:0] asi_wr_itlb_data_access; |
| 2886 | input dbg_in; |
| 2887 | |
| 2888 | reg [(`TS_WIDTH-1):0] tstamp; |
| 2889 | reg [7:0] data_in_ready; |
| 2890 | reg hwtw; |
| 2891 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 2892 | reg dbg_en; |
| 2893 | |
| 2894 | reg [2:0] mytid; |
| 2895 | reg [5:0] mytnum; |
| 2896 | wire [2:0] mycid; |
| 2897 | integer junk; |
| 2898 | integer i; |
| 2899 | reg [7:0] cnt; |
| 2900 | |
| 2901 | assign mycid = 4; |
| 2902 | |
| 2903 | //---------------------------------------------------------- |
| 2904 | // Instantiate fifo - 1 entry per thread |
| 2905 | //fifo fifo (); |
| 2906 | // Define fifo parameters |
| 2907 | `ifndef PALLADIUM |
| 2908 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 2909 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 2910 | defparam fifo.PTR_BITS = 4; |
| 2911 | `endif |
| 2912 | |
| 2913 | //---------------------------------------------------------- |
| 2914 | // DUT probes |
| 2915 | |
| 2916 | assign data_in = `SPC4.mmu.asi.htc_wr_itlb_data_in; |
| 2917 | assign wr_en = `SPC4.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 2918 | |
| 2919 | assign entry = `SPC4.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 2920 | |
| 2921 | assign demap_page = `SPC4.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 2922 | assign demap_context = `SPC4.ifu_ftu.itc_demap_context; |
| 2923 | assign demap_real = `SPC4.ifu_ftu.itc_demap_real; |
| 2924 | assign demap_all = `SPC4.ifu_ftu.itc_demap_all; |
| 2925 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 2926 | assign skip_demap = `SPC4.ifu_ftu.itc_wr_u_en; |
| 2927 | assign demap_tid = `SPC4.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 2928 | |
| 2929 | |
| 2930 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 2931 | assign demap_active = |demap_1 && !skip_demap; |
| 2932 | assign auto_demap = |demap_1 && skip_demap; |
| 2933 | wire [7:0] itlb_wr = {(`SPC4.tlu.trl1.take_itw & `SPC4.tlu.trl1.trap[3]), |
| 2934 | (`SPC4.tlu.trl1.take_itw & `SPC4.tlu.trl1.trap[2]), |
| 2935 | (`SPC4.tlu.trl1.take_itw & `SPC4.tlu.trl1.trap[1]), |
| 2936 | (`SPC4.tlu.trl1.take_itw & `SPC4.tlu.trl1.trap[0]), |
| 2937 | (`SPC4.tlu.trl0.take_itw & `SPC4.tlu.trl0.trap[3]), |
| 2938 | (`SPC4.tlu.trl0.take_itw & `SPC4.tlu.trl0.trap[2]), |
| 2939 | (`SPC4.tlu.trl0.take_itw & `SPC4.tlu.trl0.trap[1]), |
| 2940 | (`SPC4.tlu.trl0.take_itw & `SPC4.tlu.trl0.trap[0]) |
| 2941 | }; |
| 2942 | |
| 2943 | assign tlb_wr = itlb_wr; |
| 2944 | |
| 2945 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 2946 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 2947 | // These signals assert before the MMU reorders the TLB writes. |
| 2948 | // Use these to suppress SSTEP in nas_pipe. |
| 2949 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 2950 | assign asi_wr_itlb_demap = `SPC4.mmu.asi_wr_immu_demap; |
| 2951 | assign asi_wr_itlb_data_in = `SPC4.mmu.asi_wr_itlb_data_in; |
| 2952 | assign asi_wr_itlb_data_access = {`SPC4.mmu.asd1.asi_wr_itlb_data_access, |
| 2953 | `SPC4.mmu.asd0.asi_wr_itlb_data_access}; |
| 2954 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 2955 | |
| 2956 | //--------------------- |
| 2957 | // Probes for debugging |
| 2958 | |
| 2959 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 2960 | |
| 2961 | // n2_tlb_tl_64x59_cam.sv |
| 2962 | |
| 2963 | `define CNTX1_HI 65 |
| 2964 | `define CNTX1_LO 53 |
| 2965 | `define PID_HI 52 |
| 2966 | `define PID_LO 50 |
| 2967 | `define REAL_BIT 49 |
| 2968 | `define VA_47 48 |
| 2969 | `define VA_28 29 |
| 2970 | `define VA_27 28 |
| 2971 | `define VA_22 23 |
| 2972 | `define TTE_VALID 22 |
| 2973 | `define VA_21 21 |
| 2974 | `define VA_16 16 |
| 2975 | `define VA_15 15 |
| 2976 | `define VA_13 13 |
| 2977 | `define CNTX0_HI 12 |
| 2978 | `define CNTX0_LO 0 |
| 2979 | |
| 2980 | // n2_tlb_tl_64x59_ram.sv |
| 2981 | |
| 2982 | `define DATA_PARITY 36 |
| 2983 | `define DATA_PA_39_28_HI 35 |
| 2984 | `define DATA_PA_39_28_LO 24 |
| 2985 | `define DATA_PA_27_22_HI 23 |
| 2986 | `define DATA_PA_27_22_LO 18 |
| 2987 | `define DATA_VA_27_22_V 17 |
| 2988 | `define DATA_PA_21_16_HI 16 |
| 2989 | `define DATA_PA_21_16_LO 11 |
| 2990 | `define DATA_VA_21_16_V 10 |
| 2991 | `define DATA_PA_15_13_HI 9 |
| 2992 | `define DATA_PA_15_13_LO 7 |
| 2993 | `define DATA_VA_15_13_V 6 |
| 2994 | `define DATA_NFO 5 |
| 2995 | `define DATA_IE 4 |
| 2996 | `define DATA_CP 3 |
| 2997 | `define DATA_X 2 |
| 2998 | `define DATA_P 1 |
| 2999 | `define DATA_W 0 |
| 3000 | |
| 3001 | wire [(NUM_TLB-1):0] tlb_valid; |
| 3002 | wire [(NUM_TLB-1):0] tlb_match; |
| 3003 | wire tte_valid; |
| 3004 | wire [47:0] tte_va; |
| 3005 | wire [12:0] tte_context; |
| 3006 | wire tte_real; |
| 3007 | wire [2:0] tte_pid; |
| 3008 | wire [2:0] tte_page_mask; |
| 3009 | wire [39:0] tte_pa; |
| 3010 | wire tte_nfo; |
| 3011 | wire tte_ie; |
| 3012 | wire tte_cp; |
| 3013 | wire tte_e; |
| 3014 | wire tte_p; |
| 3015 | wire tte_w; |
| 3016 | wire tte_ep; |
| 3017 | |
| 3018 | assign tlb_valid = `SPC4.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 3019 | assign tlb_match = `SPC4.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 3020 | |
| 3021 | assign tte_va = {`SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 3022 | `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 3023 | `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 3024 | `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 3025 | 13'b0 |
| 3026 | }; |
| 3027 | assign tte_context = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 3028 | assign tte_pid = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 3029 | assign tte_real = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 3030 | assign tte_valid = `SPC4.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 3031 | |
| 3032 | assign tte_page_mask = `SPC4.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 3033 | |
| 3034 | assign tte_pa = {`SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 3035 | `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 3036 | `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 3037 | `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 3038 | 13'b0 |
| 3039 | }; |
| 3040 | assign tte_nfo = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 3041 | assign tte_ie = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 3042 | assign tte_cp = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 3043 | assign tte_e = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 3044 | assign tte_p = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 3045 | assign tte_w = `SPC4.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 3046 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 3047 | |
| 3048 | //---------------------------------------------------------- |
| 3049 | initial begin // { |
| 3050 | `ifndef PALLADIUM |
| 3051 | #1; |
| 3052 | `endif |
| 3053 | hwtw = 1'b0; |
| 3054 | data_in_ready = 8'b0; |
| 3055 | end // } |
| 3056 | |
| 3057 | //---------------------------------------------------------- |
| 3058 | // Must use negedge to avoid race condition |
| 3059 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 3060 | |
| 3061 | always @ (negedge `CPU.l2clk) begin // { |
| 3062 | |
| 3063 | tstamp = `TOP.cycle; |
| 3064 | demap_tstamp = `TOP.cycle; |
| 3065 | |
| 3066 | // Delay by 1 cycle to align with skip_demap |
| 3067 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 3068 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 3069 | demap_1 <= demap; |
| 3070 | |
| 3071 | |
| 3072 | //---------------------------------------------------------- |
| 3073 | // Send I/DTLBWRITE due to demap |
| 3074 | // |
| 3075 | |
| 3076 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 3077 | $display("tlb_sync", `ERROR, |
| 3078 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 3079 | mycid,demap_tid_1); |
| 3080 | end // } |
| 3081 | |
| 3082 | //if (demap_active) begin // { |
| 3083 | // fifo.pop_fifo ({hwtw,mytid}); |
| 3084 | //end |
| 3085 | //-------------------- |
| 3086 | if (dbg_in & (|demap_1)) begin // { |
| 3087 | begin // axis tbcall_region |
| 3088 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 3089 | end |
| 3090 | |
| 3091 | if (demap_active) begin |
| 3092 | begin // axis tbcall_region |
| 3093 | case (demap_1) |
| 3094 | 4'b0001: $write ("type=real "); |
| 3095 | 4'b0010: $write ("type=cntx "); |
| 3096 | 4'b0100: $write ("type=page "); |
| 3097 | 4'b1000: $write ("type=all "); |
| 3098 | default: |
| 3099 | $display ("tlb_sync", `ERROR, |
| 3100 | "Bench Problem - demap_1() should be one-hot."); |
| 3101 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 3102 | endcase |
| 3103 | end |
| 3104 | end |
| 3105 | else begin |
| 3106 | begin // axis tbcall_region |
| 3107 | $write("type=autodemap "); |
| 3108 | end |
| 3109 | end |
| 3110 | |
| 3111 | begin // axis tbcall_region |
| 3112 | $display ("match=%h ts=%0d", |
| 3113 | tlb_match,demap_tstamp*`TOP.core_period); |
| 3114 | end |
| 3115 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 3116 | if (tlb_match[cnt]==1'b1) begin // { |
| 3117 | begin // axis tbcall_region |
| 3118 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 3119 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 3120 | end |
| 3121 | end // } |
| 3122 | end // } |
| 3123 | |
| 3124 | end // } |
| 3125 | |
| 3126 | //---------------------------------------------------------- |
| 3127 | // Send I/DHWTW due to HWTW |
| 3128 | // Send I/DTLBWRITE due to ASI write |
| 3129 | |
| 3130 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 3131 | // These signals will be interleaved between the threads. |
| 3132 | // Need to queue up the signals over time so they can be processed in order. |
| 3133 | // Each thread will only be doing 1 thing at a time. |
| 3134 | |
| 3135 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 3136 | |
| 3137 | for (i=0;i<=7;i=i+1) begin // { |
| 3138 | |
| 3139 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 3140 | $display ("tlb_sync", `ERROR, |
| 3141 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 3142 | end // } |
| 3143 | else begin // { |
| 3144 | |
| 3145 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 3146 | if (data_in[i]) begin // { |
| 3147 | data_in_ready[i] <= 1'b1; |
| 3148 | end // } |
| 3149 | |
| 3150 | // tlb_wr[tid] determines which thread will write next |
| 3151 | // Use fifo to save the tids of the tlb_wr signals in order |
| 3152 | if (tlb_wr[i]) begin // { |
| 3153 | if (data_in_ready[i]) begin // { |
| 3154 | hwtw <= 1'b1; |
| 3155 | mytid[2:0] <= i[2:0]; |
| 3156 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 3157 | data_in_ready[i] <= 1'b0; |
| 3158 | end // } |
| 3159 | else begin // { |
| 3160 | hwtw <= 1'b0; |
| 3161 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 3162 | mytid[2:0] <= i[2:0]; |
| 3163 | end // } |
| 3164 | end // } |
| 3165 | |
| 3166 | end // if} |
| 3167 | end // for} |
| 3168 | |
| 3169 | end // if} |
| 3170 | |
| 3171 | //---------------------------------------------------------- |
| 3172 | // wr_en means that the write is occurring |
| 3173 | if (wr_en) begin // { |
| 3174 | //fifo.pop_fifo ({hwtw,mytid}); |
| 3175 | mytnum = (mycid * 8) + mytid; |
| 3176 | |
| 3177 | //-------------------- |
| 3178 | if (dbg_in) begin // { |
| 3179 | begin // axis tbcall_region |
| 3180 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 3181 | end |
| 3182 | |
| 3183 | begin // axis tbcall_region |
| 3184 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 3185 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 3186 | end |
| 3187 | |
| 3188 | begin // axis tbcall_region |
| 3189 | case (tte_page_mask) |
| 3190 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 3191 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3192 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 3193 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3194 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 3195 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3196 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 3197 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3198 | endcase |
| 3199 | |
| 3200 | if (hwtw) $display (" (hwtw)"); |
| 3201 | else $display (""); |
| 3202 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 3203 | |
| 3204 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 3205 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 3206 | end |
| 3207 | end // } |
| 3208 | //-------------------- |
| 3209 | |
| 3210 | end // } |
| 3211 | |
| 3212 | end // always} |
| 3213 | |
| 3214 | `endif |
| 3215 | //---------------------------------------------------------- |
| 3216 | endmodule |
| 3217 | |
| 3218 | module dtlb_wr_c4 (dbg_in); |
| 3219 | `ifndef GATESIM |
| 3220 | |
| 3221 | parameter NUM_TLB=128; |
| 3222 | |
| 3223 | wire [7:0] data_in; |
| 3224 | wire [7:0] tlb_wr; |
| 3225 | wire wr_en; |
| 3226 | wire [7:0] entry; |
| 3227 | wire [7:0] asi_num; |
| 3228 | wire asi_enable0; // 1 per thread group |
| 3229 | wire asi_enable1; |
| 3230 | // wire [7:0] store_asi; // 1 per thread |
| 3231 | wire [3:0] demap; |
| 3232 | reg [3:0] demap_1; |
| 3233 | wire demap_page; |
| 3234 | wire demap_context; |
| 3235 | wire demap_real; |
| 3236 | wire demap_all; |
| 3237 | wire skip_demap; |
| 3238 | wire demap_active; |
| 3239 | wire auto_demap; |
| 3240 | wire [2:0] demap_tid; |
| 3241 | reg [2:0] demap_tid_1; |
| 3242 | reg [5:0] demap_tnum_1; |
| 3243 | input dbg_in; |
| 3244 | |
| 3245 | reg [(`TS_WIDTH-1):0] tstamp; |
| 3246 | reg hwtw; |
| 3247 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 3248 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 3249 | |
| 3250 | reg [2:0] mytid; |
| 3251 | reg [5:0] mytnum; |
| 3252 | wire [2:0] mycid; |
| 3253 | integer junk; |
| 3254 | integer i; |
| 3255 | reg [7:0] cnt; |
| 3256 | |
| 3257 | assign mycid = 4; |
| 3258 | |
| 3259 | //---------------------------------------------------------- |
| 3260 | // Instantiate fifo - 1 entry per thread |
| 3261 | //fifo fifo (); |
| 3262 | // Define fifo parameters |
| 3263 | `ifndef PALLADIUM |
| 3264 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 3265 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 3266 | defparam fifo.PTR_BITS = 4; |
| 3267 | `endif |
| 3268 | |
| 3269 | //---------------------------------------------------------- |
| 3270 | // DUT probes |
| 3271 | |
| 3272 | assign data_in = `SPC4.mmu.asi.wrote_dtlb; |
| 3273 | assign tlb_wr = `SPC4.mmu_reload_done; |
| 3274 | assign wr_en = `SPC4.lsu.tlb.tlb_wr_1_in_dout; |
| 3275 | |
| 3276 | assign entry = `SPC4.lsu.tlb.rw_index_1[6:0]; |
| 3277 | |
| 3278 | // assign asi_num = `PROBES0.asi_num; |
| 3279 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 3280 | // !`PROBES0.tlb_bypass_b & |
| 3281 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 3282 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 3283 | // !`PROBES0.tlb_bypass_b & |
| 3284 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 3285 | |
| 3286 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 3287 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 3288 | |
| 3289 | |
| 3290 | assign demap_page = `SPC4.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 3291 | assign demap_context = `SPC4.lsu.tlc_demap_context; |
| 3292 | assign demap_real = `SPC4.lsu.tlc_demap_real; |
| 3293 | assign demap_all = `SPC4.lsu.tlc_demap_all; |
| 3294 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 3295 | assign skip_demap =`SPC4.lsu.tlc_wr_u_en; |
| 3296 | assign demap_tid = `SPC4.lsu.tld.tte1[37:35]; |
| 3297 | |
| 3298 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 3299 | assign demap_active = |demap_1 && !skip_demap; |
| 3300 | assign auto_demap = |demap_1 && skip_demap; |
| 3301 | |
| 3302 | //--------------------- |
| 3303 | // Probes for debugging |
| 3304 | |
| 3305 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 3306 | |
| 3307 | // n2_tlb_tl_128x59_cam.sv |
| 3308 | |
| 3309 | `define CNTX1_HI 65 |
| 3310 | `define CNTX1_LO 53 |
| 3311 | `define PID_HI 52 |
| 3312 | `define PID_LO 50 |
| 3313 | `define REAL_BIT 49 |
| 3314 | `define VA_47 48 |
| 3315 | `define VA_28 29 |
| 3316 | `define VA_27 28 |
| 3317 | `define VA_22 23 |
| 3318 | `define TTE_VALID 22 |
| 3319 | `define VA_21 21 |
| 3320 | `define VA_16 16 |
| 3321 | `define VA_15 15 |
| 3322 | `define VA_13 13 |
| 3323 | `define CNTX0_HI 12 |
| 3324 | `define CNTX0_LO 0 |
| 3325 | |
| 3326 | // n2_tlb_tl_128x59_ram.sv |
| 3327 | |
| 3328 | `define DATA_PARITY 36 |
| 3329 | `define DATA_PA_39_28_HI 35 |
| 3330 | `define DATA_PA_39_28_LO 24 |
| 3331 | `define DATA_PA_27_22_HI 23 |
| 3332 | `define DATA_PA_27_22_LO 18 |
| 3333 | `define DATA_VA_27_22_V 17 |
| 3334 | `define DATA_PA_21_16_HI 16 |
| 3335 | `define DATA_PA_21_16_LO 11 |
| 3336 | `define DATA_VA_21_16_V 10 |
| 3337 | `define DATA_PA_15_13_HI 9 |
| 3338 | `define DATA_PA_15_13_LO 7 |
| 3339 | `define DATA_VA_15_13_V 6 |
| 3340 | `define DATA_NFO 5 |
| 3341 | `define DATA_IE 4 |
| 3342 | `define DATA_CP 3 |
| 3343 | `define DATA_X 2 |
| 3344 | `define DATA_P 1 |
| 3345 | `define DATA_W 0 |
| 3346 | |
| 3347 | wire [(NUM_TLB-1):0] tlb_valid; |
| 3348 | wire [(NUM_TLB-1):0] tlb_match; |
| 3349 | wire tte_valid; |
| 3350 | wire [47:0] tte_va; |
| 3351 | wire [12:0] tte_context; |
| 3352 | wire tte_real; |
| 3353 | wire [2:0] tte_pid; |
| 3354 | wire [2:0] tte_page_mask; |
| 3355 | wire [39:0] tte_pa; |
| 3356 | wire tte_nfo; |
| 3357 | wire tte_ie; |
| 3358 | wire tte_cp; |
| 3359 | wire tte_e; |
| 3360 | wire tte_p; |
| 3361 | wire tte_w; |
| 3362 | wire tte_ep; |
| 3363 | |
| 3364 | |
| 3365 | assign tlb_valid = `SPC4.lsu.tlb.array.cam.valid; |
| 3366 | assign tlb_match = `SPC4.lsu.tlb.array.cam.match; |
| 3367 | |
| 3368 | assign tte_va = {`SPC4.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 3369 | `SPC4.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 3370 | `SPC4.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 3371 | `SPC4.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 3372 | 13'b0 |
| 3373 | }; |
| 3374 | assign tte_context = `SPC4.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 3375 | assign tte_pid = `SPC4.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 3376 | assign tte_real = `SPC4.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 3377 | assign tte_valid = `SPC4.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 3378 | |
| 3379 | assign tte_page_mask = `SPC4.lsu.tlb.tte_page_size_mask_1; |
| 3380 | |
| 3381 | assign tte_pa = {`SPC4.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 3382 | `SPC4.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 3383 | `SPC4.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 3384 | `SPC4.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 3385 | 13'b0 |
| 3386 | }; |
| 3387 | assign tte_nfo = `SPC4.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 3388 | assign tte_ie = `SPC4.lsu.tlb.tte_data_1[`DATA_IE]; |
| 3389 | assign tte_cp = `SPC4.lsu.tlb.tte_data_1[`DATA_CP]; |
| 3390 | assign tte_e = `SPC4.lsu.tlb.tte_data_1[`DATA_X]; |
| 3391 | assign tte_p = `SPC4.lsu.tlb.tte_data_1[`DATA_P]; |
| 3392 | assign tte_w = `SPC4.lsu.tlb.tte_data_1[`DATA_W]; |
| 3393 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 3394 | |
| 3395 | //---------------------------------------------------------- |
| 3396 | // Initialize state machine to idle state |
| 3397 | initial begin // { |
| 3398 | `ifndef PALLADIUM |
| 3399 | #1; |
| 3400 | `endif |
| 3401 | hwtw = 1'b0; |
| 3402 | //for (i=0; i<=7; i=i+1) begin |
| 3403 | // my_asi[i] = 8'b0; |
| 3404 | //end |
| 3405 | |
| 3406 | end // } |
| 3407 | |
| 3408 | //---------------------------------------------------------- |
| 3409 | // Must use negedge to avoid race condition |
| 3410 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 3411 | |
| 3412 | always @ (negedge `CPU.l2clk) begin // { |
| 3413 | |
| 3414 | tstamp = `TOP.cycle; |
| 3415 | demap_tstamp = `TOP.cycle; |
| 3416 | |
| 3417 | // Delay by 1 cycle to align with skip_demap |
| 3418 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 3419 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 3420 | demap_1 <= demap; |
| 3421 | |
| 3422 | //---------------------------------------------------------- |
| 3423 | // Send I/DTLBWRITE due to demap |
| 3424 | // |
| 3425 | |
| 3426 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 3427 | $display("tlb_sync", `ERROR, |
| 3428 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 3429 | mycid,demap_tid_1); |
| 3430 | end // } |
| 3431 | |
| 3432 | //if (demap_active) begin // { |
| 3433 | // fifo.pop_fifo ({hwtw,mytid}); |
| 3434 | //end //} |
| 3435 | |
| 3436 | //-------------------- |
| 3437 | if (dbg_in & (|demap_1)) begin // { |
| 3438 | begin // axis tbcall_region |
| 3439 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 3440 | end |
| 3441 | |
| 3442 | if (demap_active) begin |
| 3443 | begin // axis tbcall_region |
| 3444 | case (demap_1) |
| 3445 | 4'b0001: $write ("type=real "); |
| 3446 | 4'b0010: $write ("type=cntx "); |
| 3447 | 4'b0100: $write ("type=page "); |
| 3448 | 4'b1000: $write ("type=all "); |
| 3449 | default: |
| 3450 | $display ("tlb_sync", `ERROR, |
| 3451 | "Bench Problem - demap_1 should be one-hot."); |
| 3452 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 3453 | endcase |
| 3454 | end |
| 3455 | end |
| 3456 | else begin |
| 3457 | begin // axis tbcall_region |
| 3458 | $write ("type=autodemap "); |
| 3459 | end |
| 3460 | end |
| 3461 | |
| 3462 | begin // axis tbcall_region |
| 3463 | $display ("match=%h ts=%0d", |
| 3464 | tlb_match,demap_tstamp*`TOP.core_period); |
| 3465 | end |
| 3466 | |
| 3467 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 3468 | if (tlb_match[cnt]==1'b1) begin // { |
| 3469 | begin // axis tbcall_region |
| 3470 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 3471 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 3472 | end |
| 3473 | end // } |
| 3474 | end // } |
| 3475 | //-------------------- |
| 3476 | end // } |
| 3477 | |
| 3478 | //---------------------------------------------------------- |
| 3479 | // Send I/DHWTW due to HWTW |
| 3480 | // Send I/DTLBWRITE due to ASI write |
| 3481 | |
| 3482 | // Save asi num when DTLBREAD happens. |
| 3483 | // Otherwise, hold state. |
| 3484 | // Send asi num later with DHWTW |
| 3485 | // for (i=0;i<=7;i=i+1) begin // { |
| 3486 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 3487 | // end // } |
| 3488 | |
| 3489 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 3490 | // These signals will be interleaved between the threads. |
| 3491 | // Need to queue up the signals over time so they can be processed in order. |
| 3492 | // Each thread will only be doing 1 thing at a time. |
| 3493 | |
| 3494 | for (i=0;i<=7;i=i+1) begin // { |
| 3495 | |
| 3496 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 3497 | |
| 3498 | // data_in[tid] determines which thread will write next |
| 3499 | // Use fifo to save the tids of the data_in signals in order |
| 3500 | |
| 3501 | if (data_in[i]) begin // { |
| 3502 | mytid[2:0] <= i[2:0]; |
| 3503 | if (tlb_wr[i]) begin // { |
| 3504 | hwtw <= 1'b1; |
| 3505 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 3506 | end // } |
| 3507 | else begin // { |
| 3508 | hwtw <= 1'b0; |
| 3509 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 3510 | end // } |
| 3511 | end // } |
| 3512 | |
| 3513 | end // } |
| 3514 | |
| 3515 | //---------------------------------------------------------- |
| 3516 | // wr_en means that the write is occurring |
| 3517 | if (wr_en) begin // { |
| 3518 | //fifo.pop_fifo ({hwtw,mytid}); |
| 3519 | mytnum = (mycid * 8) + mytid; |
| 3520 | |
| 3521 | //-------------------- |
| 3522 | if (dbg_in) begin // { |
| 3523 | begin // axis tbcall_region |
| 3524 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 3525 | |
| 3526 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 3527 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 3528 | |
| 3529 | case (tte_page_mask) |
| 3530 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 3531 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3532 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 3533 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3534 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 3535 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3536 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 3537 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3538 | endcase |
| 3539 | |
| 3540 | if (hwtw) $display (" (hwtw)"); |
| 3541 | else $display (""); |
| 3542 | |
| 3543 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 3544 | |
| 3545 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 3546 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 3547 | end // } |
| 3548 | //-------------------- |
| 3549 | |
| 3550 | end // } |
| 3551 | end // } |
| 3552 | |
| 3553 | end // always} |
| 3554 | |
| 3555 | //---------------------------------------------------------- |
| 3556 | `endif |
| 3557 | |
| 3558 | endmodule |
| 3559 | `endif |
| 3560 | |
| 3561 | //---------------------------------------------------------- |
| 3562 | //---------------------------------------------------------- |
| 3563 | |
| 3564 | |
| 3565 | `ifdef CORE_5 |
| 3566 | |
| 3567 | module itlb_wr_c5 (dbg_in); |
| 3568 | `ifndef GATESIM |
| 3569 | |
| 3570 | parameter NUM_TLB=64; |
| 3571 | |
| 3572 | wire [7:0] data_in; |
| 3573 | wire [7:0] tlb_wr; |
| 3574 | wire wr_en; |
| 3575 | wire [7:0] entry; |
| 3576 | wire [3:0] demap; |
| 3577 | reg [3:0] demap_1; |
| 3578 | wire demap_page; |
| 3579 | wire demap_context; |
| 3580 | wire demap_real; |
| 3581 | wire demap_all; |
| 3582 | wire skip_demap; |
| 3583 | wire demap_active; |
| 3584 | wire auto_demap; |
| 3585 | wire [2:0] demap_tid; |
| 3586 | reg [2:0] demap_tid_1; |
| 3587 | reg [5:0] demap_tnum_1; |
| 3588 | wire [7:0] asi_wr_itlb; |
| 3589 | wire [7:0] asi_wr_itlb_demap; |
| 3590 | wire [7:0] asi_wr_itlb_data_in; |
| 3591 | wire [7:0] asi_wr_itlb_data_access; |
| 3592 | input dbg_in; |
| 3593 | |
| 3594 | reg [(`TS_WIDTH-1):0] tstamp; |
| 3595 | reg [7:0] data_in_ready; |
| 3596 | reg hwtw; |
| 3597 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 3598 | reg dbg_en; |
| 3599 | |
| 3600 | reg [2:0] mytid; |
| 3601 | reg [5:0] mytnum; |
| 3602 | wire [2:0] mycid; |
| 3603 | integer junk; |
| 3604 | integer i; |
| 3605 | reg [7:0] cnt; |
| 3606 | |
| 3607 | assign mycid = 5; |
| 3608 | |
| 3609 | //---------------------------------------------------------- |
| 3610 | // Instantiate fifo - 1 entry per thread |
| 3611 | //fifo fifo (); |
| 3612 | // Define fifo parameters |
| 3613 | `ifndef PALLADIUM |
| 3614 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 3615 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 3616 | defparam fifo.PTR_BITS = 4; |
| 3617 | `endif |
| 3618 | |
| 3619 | //---------------------------------------------------------- |
| 3620 | // DUT probes |
| 3621 | |
| 3622 | assign data_in = `SPC5.mmu.asi.htc_wr_itlb_data_in; |
| 3623 | assign wr_en = `SPC5.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 3624 | |
| 3625 | assign entry = `SPC5.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 3626 | |
| 3627 | assign demap_page = `SPC5.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 3628 | assign demap_context = `SPC5.ifu_ftu.itc_demap_context; |
| 3629 | assign demap_real = `SPC5.ifu_ftu.itc_demap_real; |
| 3630 | assign demap_all = `SPC5.ifu_ftu.itc_demap_all; |
| 3631 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 3632 | assign skip_demap = `SPC5.ifu_ftu.itc_wr_u_en; |
| 3633 | assign demap_tid = `SPC5.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 3634 | |
| 3635 | |
| 3636 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 3637 | assign demap_active = |demap_1 && !skip_demap; |
| 3638 | assign auto_demap = |demap_1 && skip_demap; |
| 3639 | wire [7:0] itlb_wr = {(`SPC5.tlu.trl1.take_itw & `SPC5.tlu.trl1.trap[3]), |
| 3640 | (`SPC5.tlu.trl1.take_itw & `SPC5.tlu.trl1.trap[2]), |
| 3641 | (`SPC5.tlu.trl1.take_itw & `SPC5.tlu.trl1.trap[1]), |
| 3642 | (`SPC5.tlu.trl1.take_itw & `SPC5.tlu.trl1.trap[0]), |
| 3643 | (`SPC5.tlu.trl0.take_itw & `SPC5.tlu.trl0.trap[3]), |
| 3644 | (`SPC5.tlu.trl0.take_itw & `SPC5.tlu.trl0.trap[2]), |
| 3645 | (`SPC5.tlu.trl0.take_itw & `SPC5.tlu.trl0.trap[1]), |
| 3646 | (`SPC5.tlu.trl0.take_itw & `SPC5.tlu.trl0.trap[0]) |
| 3647 | }; |
| 3648 | |
| 3649 | assign tlb_wr = itlb_wr; |
| 3650 | |
| 3651 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 3652 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 3653 | // These signals assert before the MMU reorders the TLB writes. |
| 3654 | // Use these to suppress SSTEP in nas_pipe. |
| 3655 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 3656 | assign asi_wr_itlb_demap = `SPC5.mmu.asi_wr_immu_demap; |
| 3657 | assign asi_wr_itlb_data_in = `SPC5.mmu.asi_wr_itlb_data_in; |
| 3658 | assign asi_wr_itlb_data_access = {`SPC5.mmu.asd1.asi_wr_itlb_data_access, |
| 3659 | `SPC5.mmu.asd0.asi_wr_itlb_data_access}; |
| 3660 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 3661 | |
| 3662 | //--------------------- |
| 3663 | // Probes for debugging |
| 3664 | |
| 3665 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 3666 | |
| 3667 | // n2_tlb_tl_64x59_cam.sv |
| 3668 | |
| 3669 | `define CNTX1_HI 65 |
| 3670 | `define CNTX1_LO 53 |
| 3671 | `define PID_HI 52 |
| 3672 | `define PID_LO 50 |
| 3673 | `define REAL_BIT 49 |
| 3674 | `define VA_47 48 |
| 3675 | `define VA_28 29 |
| 3676 | `define VA_27 28 |
| 3677 | `define VA_22 23 |
| 3678 | `define TTE_VALID 22 |
| 3679 | `define VA_21 21 |
| 3680 | `define VA_16 16 |
| 3681 | `define VA_15 15 |
| 3682 | `define VA_13 13 |
| 3683 | `define CNTX0_HI 12 |
| 3684 | `define CNTX0_LO 0 |
| 3685 | |
| 3686 | // n2_tlb_tl_64x59_ram.sv |
| 3687 | |
| 3688 | `define DATA_PARITY 36 |
| 3689 | `define DATA_PA_39_28_HI 35 |
| 3690 | `define DATA_PA_39_28_LO 24 |
| 3691 | `define DATA_PA_27_22_HI 23 |
| 3692 | `define DATA_PA_27_22_LO 18 |
| 3693 | `define DATA_VA_27_22_V 17 |
| 3694 | `define DATA_PA_21_16_HI 16 |
| 3695 | `define DATA_PA_21_16_LO 11 |
| 3696 | `define DATA_VA_21_16_V 10 |
| 3697 | `define DATA_PA_15_13_HI 9 |
| 3698 | `define DATA_PA_15_13_LO 7 |
| 3699 | `define DATA_VA_15_13_V 6 |
| 3700 | `define DATA_NFO 5 |
| 3701 | `define DATA_IE 4 |
| 3702 | `define DATA_CP 3 |
| 3703 | `define DATA_X 2 |
| 3704 | `define DATA_P 1 |
| 3705 | `define DATA_W 0 |
| 3706 | |
| 3707 | wire [(NUM_TLB-1):0] tlb_valid; |
| 3708 | wire [(NUM_TLB-1):0] tlb_match; |
| 3709 | wire tte_valid; |
| 3710 | wire [47:0] tte_va; |
| 3711 | wire [12:0] tte_context; |
| 3712 | wire tte_real; |
| 3713 | wire [2:0] tte_pid; |
| 3714 | wire [2:0] tte_page_mask; |
| 3715 | wire [39:0] tte_pa; |
| 3716 | wire tte_nfo; |
| 3717 | wire tte_ie; |
| 3718 | wire tte_cp; |
| 3719 | wire tte_e; |
| 3720 | wire tte_p; |
| 3721 | wire tte_w; |
| 3722 | wire tte_ep; |
| 3723 | |
| 3724 | assign tlb_valid = `SPC5.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 3725 | assign tlb_match = `SPC5.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 3726 | |
| 3727 | assign tte_va = {`SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 3728 | `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 3729 | `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 3730 | `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 3731 | 13'b0 |
| 3732 | }; |
| 3733 | assign tte_context = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 3734 | assign tte_pid = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 3735 | assign tte_real = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 3736 | assign tte_valid = `SPC5.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 3737 | |
| 3738 | assign tte_page_mask = `SPC5.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 3739 | |
| 3740 | assign tte_pa = {`SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 3741 | `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 3742 | `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 3743 | `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 3744 | 13'b0 |
| 3745 | }; |
| 3746 | assign tte_nfo = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 3747 | assign tte_ie = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 3748 | assign tte_cp = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 3749 | assign tte_e = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 3750 | assign tte_p = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 3751 | assign tte_w = `SPC5.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 3752 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 3753 | |
| 3754 | //---------------------------------------------------------- |
| 3755 | initial begin // { |
| 3756 | `ifndef PALLADIUM |
| 3757 | #1; |
| 3758 | `endif |
| 3759 | hwtw = 1'b0; |
| 3760 | data_in_ready = 8'b0; |
| 3761 | end // } |
| 3762 | |
| 3763 | //---------------------------------------------------------- |
| 3764 | // Must use negedge to avoid race condition |
| 3765 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 3766 | |
| 3767 | always @ (negedge `CPU.l2clk) begin // { |
| 3768 | |
| 3769 | tstamp = `TOP.cycle; |
| 3770 | demap_tstamp = `TOP.cycle; |
| 3771 | |
| 3772 | // Delay by 1 cycle to align with skip_demap |
| 3773 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 3774 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 3775 | demap_1 <= demap; |
| 3776 | |
| 3777 | |
| 3778 | //---------------------------------------------------------- |
| 3779 | // Send I/DTLBWRITE due to demap |
| 3780 | // |
| 3781 | |
| 3782 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 3783 | $display("tlb_sync", `ERROR, |
| 3784 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 3785 | mycid,demap_tid_1); |
| 3786 | end // } |
| 3787 | |
| 3788 | //if (demap_active) begin // { |
| 3789 | // fifo.pop_fifo ({hwtw,mytid}); |
| 3790 | //end |
| 3791 | //-------------------- |
| 3792 | if (dbg_in & (|demap_1)) begin // { |
| 3793 | begin // axis tbcall_region |
| 3794 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 3795 | end |
| 3796 | |
| 3797 | if (demap_active) begin |
| 3798 | begin // axis tbcall_region |
| 3799 | case (demap_1) |
| 3800 | 4'b0001: $write ("type=real "); |
| 3801 | 4'b0010: $write ("type=cntx "); |
| 3802 | 4'b0100: $write ("type=page "); |
| 3803 | 4'b1000: $write ("type=all "); |
| 3804 | default: |
| 3805 | $display ("tlb_sync", `ERROR, |
| 3806 | "Bench Problem - demap_1() should be one-hot."); |
| 3807 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 3808 | endcase |
| 3809 | end |
| 3810 | end |
| 3811 | else begin |
| 3812 | begin // axis tbcall_region |
| 3813 | $write("type=autodemap "); |
| 3814 | end |
| 3815 | end |
| 3816 | |
| 3817 | begin // axis tbcall_region |
| 3818 | $display ("match=%h ts=%0d", |
| 3819 | tlb_match,demap_tstamp*`TOP.core_period); |
| 3820 | end |
| 3821 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 3822 | if (tlb_match[cnt]==1'b1) begin // { |
| 3823 | begin // axis tbcall_region |
| 3824 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 3825 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 3826 | end |
| 3827 | end // } |
| 3828 | end // } |
| 3829 | |
| 3830 | end // } |
| 3831 | |
| 3832 | //---------------------------------------------------------- |
| 3833 | // Send I/DHWTW due to HWTW |
| 3834 | // Send I/DTLBWRITE due to ASI write |
| 3835 | |
| 3836 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 3837 | // These signals will be interleaved between the threads. |
| 3838 | // Need to queue up the signals over time so they can be processed in order. |
| 3839 | // Each thread will only be doing 1 thing at a time. |
| 3840 | |
| 3841 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 3842 | |
| 3843 | for (i=0;i<=7;i=i+1) begin // { |
| 3844 | |
| 3845 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 3846 | $display ("tlb_sync", `ERROR, |
| 3847 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 3848 | end // } |
| 3849 | else begin // { |
| 3850 | |
| 3851 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 3852 | if (data_in[i]) begin // { |
| 3853 | data_in_ready[i] <= 1'b1; |
| 3854 | end // } |
| 3855 | |
| 3856 | // tlb_wr[tid] determines which thread will write next |
| 3857 | // Use fifo to save the tids of the tlb_wr signals in order |
| 3858 | if (tlb_wr[i]) begin // { |
| 3859 | if (data_in_ready[i]) begin // { |
| 3860 | hwtw <= 1'b1; |
| 3861 | mytid[2:0] <= i[2:0]; |
| 3862 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 3863 | data_in_ready[i] <= 1'b0; |
| 3864 | end // } |
| 3865 | else begin // { |
| 3866 | hwtw <= 1'b0; |
| 3867 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 3868 | mytid[2:0] <= i[2:0]; |
| 3869 | end // } |
| 3870 | end // } |
| 3871 | |
| 3872 | end // if} |
| 3873 | end // for} |
| 3874 | |
| 3875 | end // if} |
| 3876 | |
| 3877 | //---------------------------------------------------------- |
| 3878 | // wr_en means that the write is occurring |
| 3879 | if (wr_en) begin // { |
| 3880 | //fifo.pop_fifo ({hwtw,mytid}); |
| 3881 | mytnum = (mycid * 8) + mytid; |
| 3882 | |
| 3883 | //-------------------- |
| 3884 | if (dbg_in) begin // { |
| 3885 | begin // axis tbcall_region |
| 3886 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 3887 | end |
| 3888 | |
| 3889 | begin // axis tbcall_region |
| 3890 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 3891 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 3892 | end |
| 3893 | |
| 3894 | begin // axis tbcall_region |
| 3895 | case (tte_page_mask) |
| 3896 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 3897 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3898 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 3899 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3900 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 3901 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3902 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 3903 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 3904 | endcase |
| 3905 | |
| 3906 | if (hwtw) $display (" (hwtw)"); |
| 3907 | else $display (""); |
| 3908 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 3909 | |
| 3910 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 3911 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 3912 | end |
| 3913 | end // } |
| 3914 | //-------------------- |
| 3915 | |
| 3916 | end // } |
| 3917 | |
| 3918 | end // always} |
| 3919 | |
| 3920 | `endif |
| 3921 | //---------------------------------------------------------- |
| 3922 | endmodule |
| 3923 | |
| 3924 | module dtlb_wr_c5 (dbg_in); |
| 3925 | `ifndef GATESIM |
| 3926 | |
| 3927 | parameter NUM_TLB=128; |
| 3928 | |
| 3929 | wire [7:0] data_in; |
| 3930 | wire [7:0] tlb_wr; |
| 3931 | wire wr_en; |
| 3932 | wire [7:0] entry; |
| 3933 | wire [7:0] asi_num; |
| 3934 | wire asi_enable0; // 1 per thread group |
| 3935 | wire asi_enable1; |
| 3936 | // wire [7:0] store_asi; // 1 per thread |
| 3937 | wire [3:0] demap; |
| 3938 | reg [3:0] demap_1; |
| 3939 | wire demap_page; |
| 3940 | wire demap_context; |
| 3941 | wire demap_real; |
| 3942 | wire demap_all; |
| 3943 | wire skip_demap; |
| 3944 | wire demap_active; |
| 3945 | wire auto_demap; |
| 3946 | wire [2:0] demap_tid; |
| 3947 | reg [2:0] demap_tid_1; |
| 3948 | reg [5:0] demap_tnum_1; |
| 3949 | input dbg_in; |
| 3950 | |
| 3951 | reg [(`TS_WIDTH-1):0] tstamp; |
| 3952 | reg hwtw; |
| 3953 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 3954 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 3955 | |
| 3956 | reg [2:0] mytid; |
| 3957 | reg [5:0] mytnum; |
| 3958 | wire [2:0] mycid; |
| 3959 | integer junk; |
| 3960 | integer i; |
| 3961 | reg [7:0] cnt; |
| 3962 | |
| 3963 | assign mycid = 5; |
| 3964 | |
| 3965 | //---------------------------------------------------------- |
| 3966 | // Instantiate fifo - 1 entry per thread |
| 3967 | //fifo fifo (); |
| 3968 | // Define fifo parameters |
| 3969 | `ifndef PALLADIUM |
| 3970 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 3971 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 3972 | defparam fifo.PTR_BITS = 4; |
| 3973 | `endif |
| 3974 | |
| 3975 | //---------------------------------------------------------- |
| 3976 | // DUT probes |
| 3977 | |
| 3978 | assign data_in = `SPC5.mmu.asi.wrote_dtlb; |
| 3979 | assign tlb_wr = `SPC5.mmu_reload_done; |
| 3980 | assign wr_en = `SPC5.lsu.tlb.tlb_wr_1_in_dout; |
| 3981 | |
| 3982 | assign entry = `SPC5.lsu.tlb.rw_index_1[6:0]; |
| 3983 | |
| 3984 | // assign asi_num = `PROBES0.asi_num; |
| 3985 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 3986 | // !`PROBES0.tlb_bypass_b & |
| 3987 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 3988 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 3989 | // !`PROBES0.tlb_bypass_b & |
| 3990 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 3991 | |
| 3992 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 3993 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 3994 | |
| 3995 | |
| 3996 | assign demap_page = `SPC5.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 3997 | assign demap_context = `SPC5.lsu.tlc_demap_context; |
| 3998 | assign demap_real = `SPC5.lsu.tlc_demap_real; |
| 3999 | assign demap_all = `SPC5.lsu.tlc_demap_all; |
| 4000 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 4001 | assign skip_demap =`SPC5.lsu.tlc_wr_u_en; |
| 4002 | assign demap_tid = `SPC5.lsu.tld.tte1[37:35]; |
| 4003 | |
| 4004 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 4005 | assign demap_active = |demap_1 && !skip_demap; |
| 4006 | assign auto_demap = |demap_1 && skip_demap; |
| 4007 | |
| 4008 | //--------------------- |
| 4009 | // Probes for debugging |
| 4010 | |
| 4011 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 4012 | |
| 4013 | // n2_tlb_tl_128x59_cam.sv |
| 4014 | |
| 4015 | `define CNTX1_HI 65 |
| 4016 | `define CNTX1_LO 53 |
| 4017 | `define PID_HI 52 |
| 4018 | `define PID_LO 50 |
| 4019 | `define REAL_BIT 49 |
| 4020 | `define VA_47 48 |
| 4021 | `define VA_28 29 |
| 4022 | `define VA_27 28 |
| 4023 | `define VA_22 23 |
| 4024 | `define TTE_VALID 22 |
| 4025 | `define VA_21 21 |
| 4026 | `define VA_16 16 |
| 4027 | `define VA_15 15 |
| 4028 | `define VA_13 13 |
| 4029 | `define CNTX0_HI 12 |
| 4030 | `define CNTX0_LO 0 |
| 4031 | |
| 4032 | // n2_tlb_tl_128x59_ram.sv |
| 4033 | |
| 4034 | `define DATA_PARITY 36 |
| 4035 | `define DATA_PA_39_28_HI 35 |
| 4036 | `define DATA_PA_39_28_LO 24 |
| 4037 | `define DATA_PA_27_22_HI 23 |
| 4038 | `define DATA_PA_27_22_LO 18 |
| 4039 | `define DATA_VA_27_22_V 17 |
| 4040 | `define DATA_PA_21_16_HI 16 |
| 4041 | `define DATA_PA_21_16_LO 11 |
| 4042 | `define DATA_VA_21_16_V 10 |
| 4043 | `define DATA_PA_15_13_HI 9 |
| 4044 | `define DATA_PA_15_13_LO 7 |
| 4045 | `define DATA_VA_15_13_V 6 |
| 4046 | `define DATA_NFO 5 |
| 4047 | `define DATA_IE 4 |
| 4048 | `define DATA_CP 3 |
| 4049 | `define DATA_X 2 |
| 4050 | `define DATA_P 1 |
| 4051 | `define DATA_W 0 |
| 4052 | |
| 4053 | wire [(NUM_TLB-1):0] tlb_valid; |
| 4054 | wire [(NUM_TLB-1):0] tlb_match; |
| 4055 | wire tte_valid; |
| 4056 | wire [47:0] tte_va; |
| 4057 | wire [12:0] tte_context; |
| 4058 | wire tte_real; |
| 4059 | wire [2:0] tte_pid; |
| 4060 | wire [2:0] tte_page_mask; |
| 4061 | wire [39:0] tte_pa; |
| 4062 | wire tte_nfo; |
| 4063 | wire tte_ie; |
| 4064 | wire tte_cp; |
| 4065 | wire tte_e; |
| 4066 | wire tte_p; |
| 4067 | wire tte_w; |
| 4068 | wire tte_ep; |
| 4069 | |
| 4070 | |
| 4071 | assign tlb_valid = `SPC5.lsu.tlb.array.cam.valid; |
| 4072 | assign tlb_match = `SPC5.lsu.tlb.array.cam.match; |
| 4073 | |
| 4074 | assign tte_va = {`SPC5.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 4075 | `SPC5.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 4076 | `SPC5.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 4077 | `SPC5.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 4078 | 13'b0 |
| 4079 | }; |
| 4080 | assign tte_context = `SPC5.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 4081 | assign tte_pid = `SPC5.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 4082 | assign tte_real = `SPC5.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 4083 | assign tte_valid = `SPC5.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 4084 | |
| 4085 | assign tte_page_mask = `SPC5.lsu.tlb.tte_page_size_mask_1; |
| 4086 | |
| 4087 | assign tte_pa = {`SPC5.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 4088 | `SPC5.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 4089 | `SPC5.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 4090 | `SPC5.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 4091 | 13'b0 |
| 4092 | }; |
| 4093 | assign tte_nfo = `SPC5.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 4094 | assign tte_ie = `SPC5.lsu.tlb.tte_data_1[`DATA_IE]; |
| 4095 | assign tte_cp = `SPC5.lsu.tlb.tte_data_1[`DATA_CP]; |
| 4096 | assign tte_e = `SPC5.lsu.tlb.tte_data_1[`DATA_X]; |
| 4097 | assign tte_p = `SPC5.lsu.tlb.tte_data_1[`DATA_P]; |
| 4098 | assign tte_w = `SPC5.lsu.tlb.tte_data_1[`DATA_W]; |
| 4099 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 4100 | |
| 4101 | //---------------------------------------------------------- |
| 4102 | // Initialize state machine to idle state |
| 4103 | initial begin // { |
| 4104 | `ifndef PALLADIUM |
| 4105 | #1; |
| 4106 | `endif |
| 4107 | hwtw = 1'b0; |
| 4108 | //for (i=0; i<=7; i=i+1) begin |
| 4109 | // my_asi[i] = 8'b0; |
| 4110 | //end |
| 4111 | |
| 4112 | end // } |
| 4113 | |
| 4114 | //---------------------------------------------------------- |
| 4115 | // Must use negedge to avoid race condition |
| 4116 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 4117 | |
| 4118 | always @ (negedge `CPU.l2clk) begin // { |
| 4119 | |
| 4120 | tstamp = `TOP.cycle; |
| 4121 | demap_tstamp = `TOP.cycle; |
| 4122 | |
| 4123 | // Delay by 1 cycle to align with skip_demap |
| 4124 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 4125 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 4126 | demap_1 <= demap; |
| 4127 | |
| 4128 | //---------------------------------------------------------- |
| 4129 | // Send I/DTLBWRITE due to demap |
| 4130 | // |
| 4131 | |
| 4132 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 4133 | $display("tlb_sync", `ERROR, |
| 4134 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 4135 | mycid,demap_tid_1); |
| 4136 | end // } |
| 4137 | |
| 4138 | //if (demap_active) begin // { |
| 4139 | // fifo.pop_fifo ({hwtw,mytid}); |
| 4140 | //end //} |
| 4141 | |
| 4142 | //-------------------- |
| 4143 | if (dbg_in & (|demap_1)) begin // { |
| 4144 | begin // axis tbcall_region |
| 4145 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 4146 | end |
| 4147 | |
| 4148 | if (demap_active) begin |
| 4149 | begin // axis tbcall_region |
| 4150 | case (demap_1) |
| 4151 | 4'b0001: $write ("type=real "); |
| 4152 | 4'b0010: $write ("type=cntx "); |
| 4153 | 4'b0100: $write ("type=page "); |
| 4154 | 4'b1000: $write ("type=all "); |
| 4155 | default: |
| 4156 | $display ("tlb_sync", `ERROR, |
| 4157 | "Bench Problem - demap_1 should be one-hot."); |
| 4158 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 4159 | endcase |
| 4160 | end |
| 4161 | end |
| 4162 | else begin |
| 4163 | begin // axis tbcall_region |
| 4164 | $write ("type=autodemap "); |
| 4165 | end |
| 4166 | end |
| 4167 | |
| 4168 | begin // axis tbcall_region |
| 4169 | $display ("match=%h ts=%0d", |
| 4170 | tlb_match,demap_tstamp*`TOP.core_period); |
| 4171 | end |
| 4172 | |
| 4173 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 4174 | if (tlb_match[cnt]==1'b1) begin // { |
| 4175 | begin // axis tbcall_region |
| 4176 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 4177 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 4178 | end |
| 4179 | end // } |
| 4180 | end // } |
| 4181 | //-------------------- |
| 4182 | end // } |
| 4183 | |
| 4184 | //---------------------------------------------------------- |
| 4185 | // Send I/DHWTW due to HWTW |
| 4186 | // Send I/DTLBWRITE due to ASI write |
| 4187 | |
| 4188 | // Save asi num when DTLBREAD happens. |
| 4189 | // Otherwise, hold state. |
| 4190 | // Send asi num later with DHWTW |
| 4191 | // for (i=0;i<=7;i=i+1) begin // { |
| 4192 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 4193 | // end // } |
| 4194 | |
| 4195 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 4196 | // These signals will be interleaved between the threads. |
| 4197 | // Need to queue up the signals over time so they can be processed in order. |
| 4198 | // Each thread will only be doing 1 thing at a time. |
| 4199 | |
| 4200 | for (i=0;i<=7;i=i+1) begin // { |
| 4201 | |
| 4202 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 4203 | |
| 4204 | // data_in[tid] determines which thread will write next |
| 4205 | // Use fifo to save the tids of the data_in signals in order |
| 4206 | |
| 4207 | if (data_in[i]) begin // { |
| 4208 | mytid[2:0] <= i[2:0]; |
| 4209 | if (tlb_wr[i]) begin // { |
| 4210 | hwtw <= 1'b1; |
| 4211 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 4212 | end // } |
| 4213 | else begin // { |
| 4214 | hwtw <= 1'b0; |
| 4215 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 4216 | end // } |
| 4217 | end // } |
| 4218 | |
| 4219 | end // } |
| 4220 | |
| 4221 | //---------------------------------------------------------- |
| 4222 | // wr_en means that the write is occurring |
| 4223 | if (wr_en) begin // { |
| 4224 | //fifo.pop_fifo ({hwtw,mytid}); |
| 4225 | mytnum = (mycid * 8) + mytid; |
| 4226 | |
| 4227 | //-------------------- |
| 4228 | if (dbg_in) begin // { |
| 4229 | begin // axis tbcall_region |
| 4230 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 4231 | |
| 4232 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 4233 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 4234 | |
| 4235 | case (tte_page_mask) |
| 4236 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 4237 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4238 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 4239 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4240 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 4241 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4242 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 4243 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4244 | endcase |
| 4245 | |
| 4246 | if (hwtw) $display (" (hwtw)"); |
| 4247 | else $display (""); |
| 4248 | |
| 4249 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 4250 | |
| 4251 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 4252 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 4253 | end // } |
| 4254 | //-------------------- |
| 4255 | |
| 4256 | end // } |
| 4257 | end // } |
| 4258 | |
| 4259 | end // always} |
| 4260 | |
| 4261 | //---------------------------------------------------------- |
| 4262 | `endif |
| 4263 | |
| 4264 | endmodule |
| 4265 | `endif |
| 4266 | |
| 4267 | //---------------------------------------------------------- |
| 4268 | //---------------------------------------------------------- |
| 4269 | |
| 4270 | |
| 4271 | `ifdef CORE_6 |
| 4272 | |
| 4273 | module itlb_wr_c6 (dbg_in); |
| 4274 | `ifndef GATESIM |
| 4275 | |
| 4276 | parameter NUM_TLB=64; |
| 4277 | |
| 4278 | wire [7:0] data_in; |
| 4279 | wire [7:0] tlb_wr; |
| 4280 | wire wr_en; |
| 4281 | wire [7:0] entry; |
| 4282 | wire [3:0] demap; |
| 4283 | reg [3:0] demap_1; |
| 4284 | wire demap_page; |
| 4285 | wire demap_context; |
| 4286 | wire demap_real; |
| 4287 | wire demap_all; |
| 4288 | wire skip_demap; |
| 4289 | wire demap_active; |
| 4290 | wire auto_demap; |
| 4291 | wire [2:0] demap_tid; |
| 4292 | reg [2:0] demap_tid_1; |
| 4293 | reg [5:0] demap_tnum_1; |
| 4294 | wire [7:0] asi_wr_itlb; |
| 4295 | wire [7:0] asi_wr_itlb_demap; |
| 4296 | wire [7:0] asi_wr_itlb_data_in; |
| 4297 | wire [7:0] asi_wr_itlb_data_access; |
| 4298 | input dbg_in; |
| 4299 | |
| 4300 | reg [(`TS_WIDTH-1):0] tstamp; |
| 4301 | reg [7:0] data_in_ready; |
| 4302 | reg hwtw; |
| 4303 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 4304 | reg dbg_en; |
| 4305 | |
| 4306 | reg [2:0] mytid; |
| 4307 | reg [5:0] mytnum; |
| 4308 | wire [2:0] mycid; |
| 4309 | integer junk; |
| 4310 | integer i; |
| 4311 | reg [7:0] cnt; |
| 4312 | |
| 4313 | assign mycid = 6; |
| 4314 | |
| 4315 | //---------------------------------------------------------- |
| 4316 | // Instantiate fifo - 1 entry per thread |
| 4317 | //fifo fifo (); |
| 4318 | // Define fifo parameters |
| 4319 | `ifndef PALLADIUM |
| 4320 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 4321 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 4322 | defparam fifo.PTR_BITS = 4; |
| 4323 | `endif |
| 4324 | |
| 4325 | //---------------------------------------------------------- |
| 4326 | // DUT probes |
| 4327 | |
| 4328 | assign data_in = `SPC6.mmu.asi.htc_wr_itlb_data_in; |
| 4329 | assign wr_en = `SPC6.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 4330 | |
| 4331 | assign entry = `SPC6.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 4332 | |
| 4333 | assign demap_page = `SPC6.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 4334 | assign demap_context = `SPC6.ifu_ftu.itc_demap_context; |
| 4335 | assign demap_real = `SPC6.ifu_ftu.itc_demap_real; |
| 4336 | assign demap_all = `SPC6.ifu_ftu.itc_demap_all; |
| 4337 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 4338 | assign skip_demap = `SPC6.ifu_ftu.itc_wr_u_en; |
| 4339 | assign demap_tid = `SPC6.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 4340 | |
| 4341 | |
| 4342 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 4343 | assign demap_active = |demap_1 && !skip_demap; |
| 4344 | assign auto_demap = |demap_1 && skip_demap; |
| 4345 | wire [7:0] itlb_wr = {(`SPC6.tlu.trl1.take_itw & `SPC6.tlu.trl1.trap[3]), |
| 4346 | (`SPC6.tlu.trl1.take_itw & `SPC6.tlu.trl1.trap[2]), |
| 4347 | (`SPC6.tlu.trl1.take_itw & `SPC6.tlu.trl1.trap[1]), |
| 4348 | (`SPC6.tlu.trl1.take_itw & `SPC6.tlu.trl1.trap[0]), |
| 4349 | (`SPC6.tlu.trl0.take_itw & `SPC6.tlu.trl0.trap[3]), |
| 4350 | (`SPC6.tlu.trl0.take_itw & `SPC6.tlu.trl0.trap[2]), |
| 4351 | (`SPC6.tlu.trl0.take_itw & `SPC6.tlu.trl0.trap[1]), |
| 4352 | (`SPC6.tlu.trl0.take_itw & `SPC6.tlu.trl0.trap[0]) |
| 4353 | }; |
| 4354 | |
| 4355 | assign tlb_wr = itlb_wr; |
| 4356 | |
| 4357 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 4358 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 4359 | // These signals assert before the MMU reorders the TLB writes. |
| 4360 | // Use these to suppress SSTEP in nas_pipe. |
| 4361 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 4362 | assign asi_wr_itlb_demap = `SPC6.mmu.asi_wr_immu_demap; |
| 4363 | assign asi_wr_itlb_data_in = `SPC6.mmu.asi_wr_itlb_data_in; |
| 4364 | assign asi_wr_itlb_data_access = {`SPC6.mmu.asd1.asi_wr_itlb_data_access, |
| 4365 | `SPC6.mmu.asd0.asi_wr_itlb_data_access}; |
| 4366 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 4367 | |
| 4368 | //--------------------- |
| 4369 | // Probes for debugging |
| 4370 | |
| 4371 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 4372 | |
| 4373 | // n2_tlb_tl_64x59_cam.sv |
| 4374 | |
| 4375 | `define CNTX1_HI 65 |
| 4376 | `define CNTX1_LO 53 |
| 4377 | `define PID_HI 52 |
| 4378 | `define PID_LO 50 |
| 4379 | `define REAL_BIT 49 |
| 4380 | `define VA_47 48 |
| 4381 | `define VA_28 29 |
| 4382 | `define VA_27 28 |
| 4383 | `define VA_22 23 |
| 4384 | `define TTE_VALID 22 |
| 4385 | `define VA_21 21 |
| 4386 | `define VA_16 16 |
| 4387 | `define VA_15 15 |
| 4388 | `define VA_13 13 |
| 4389 | `define CNTX0_HI 12 |
| 4390 | `define CNTX0_LO 0 |
| 4391 | |
| 4392 | // n2_tlb_tl_64x59_ram.sv |
| 4393 | |
| 4394 | `define DATA_PARITY 36 |
| 4395 | `define DATA_PA_39_28_HI 35 |
| 4396 | `define DATA_PA_39_28_LO 24 |
| 4397 | `define DATA_PA_27_22_HI 23 |
| 4398 | `define DATA_PA_27_22_LO 18 |
| 4399 | `define DATA_VA_27_22_V 17 |
| 4400 | `define DATA_PA_21_16_HI 16 |
| 4401 | `define DATA_PA_21_16_LO 11 |
| 4402 | `define DATA_VA_21_16_V 10 |
| 4403 | `define DATA_PA_15_13_HI 9 |
| 4404 | `define DATA_PA_15_13_LO 7 |
| 4405 | `define DATA_VA_15_13_V 6 |
| 4406 | `define DATA_NFO 5 |
| 4407 | `define DATA_IE 4 |
| 4408 | `define DATA_CP 3 |
| 4409 | `define DATA_X 2 |
| 4410 | `define DATA_P 1 |
| 4411 | `define DATA_W 0 |
| 4412 | |
| 4413 | wire [(NUM_TLB-1):0] tlb_valid; |
| 4414 | wire [(NUM_TLB-1):0] tlb_match; |
| 4415 | wire tte_valid; |
| 4416 | wire [47:0] tte_va; |
| 4417 | wire [12:0] tte_context; |
| 4418 | wire tte_real; |
| 4419 | wire [2:0] tte_pid; |
| 4420 | wire [2:0] tte_page_mask; |
| 4421 | wire [39:0] tte_pa; |
| 4422 | wire tte_nfo; |
| 4423 | wire tte_ie; |
| 4424 | wire tte_cp; |
| 4425 | wire tte_e; |
| 4426 | wire tte_p; |
| 4427 | wire tte_w; |
| 4428 | wire tte_ep; |
| 4429 | |
| 4430 | assign tlb_valid = `SPC6.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 4431 | assign tlb_match = `SPC6.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 4432 | |
| 4433 | assign tte_va = {`SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 4434 | `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 4435 | `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 4436 | `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 4437 | 13'b0 |
| 4438 | }; |
| 4439 | assign tte_context = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 4440 | assign tte_pid = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 4441 | assign tte_real = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 4442 | assign tte_valid = `SPC6.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 4443 | |
| 4444 | assign tte_page_mask = `SPC6.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 4445 | |
| 4446 | assign tte_pa = {`SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 4447 | `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 4448 | `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 4449 | `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 4450 | 13'b0 |
| 4451 | }; |
| 4452 | assign tte_nfo = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 4453 | assign tte_ie = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 4454 | assign tte_cp = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 4455 | assign tte_e = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 4456 | assign tte_p = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 4457 | assign tte_w = `SPC6.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 4458 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 4459 | |
| 4460 | //---------------------------------------------------------- |
| 4461 | initial begin // { |
| 4462 | `ifndef PALLADIUM |
| 4463 | #1; |
| 4464 | `endif |
| 4465 | hwtw = 1'b0; |
| 4466 | data_in_ready = 8'b0; |
| 4467 | end // } |
| 4468 | |
| 4469 | //---------------------------------------------------------- |
| 4470 | // Must use negedge to avoid race condition |
| 4471 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 4472 | |
| 4473 | always @ (negedge `CPU.l2clk) begin // { |
| 4474 | |
| 4475 | tstamp = `TOP.cycle; |
| 4476 | demap_tstamp = `TOP.cycle; |
| 4477 | |
| 4478 | // Delay by 1 cycle to align with skip_demap |
| 4479 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 4480 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 4481 | demap_1 <= demap; |
| 4482 | |
| 4483 | |
| 4484 | //---------------------------------------------------------- |
| 4485 | // Send I/DTLBWRITE due to demap |
| 4486 | // |
| 4487 | |
| 4488 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 4489 | $display("tlb_sync", `ERROR, |
| 4490 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 4491 | mycid,demap_tid_1); |
| 4492 | end // } |
| 4493 | |
| 4494 | //if (demap_active) begin // { |
| 4495 | // fifo.pop_fifo ({hwtw,mytid}); |
| 4496 | //end |
| 4497 | //-------------------- |
| 4498 | if (dbg_in & (|demap_1)) begin // { |
| 4499 | begin // axis tbcall_region |
| 4500 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 4501 | end |
| 4502 | |
| 4503 | if (demap_active) begin |
| 4504 | begin // axis tbcall_region |
| 4505 | case (demap_1) |
| 4506 | 4'b0001: $write ("type=real "); |
| 4507 | 4'b0010: $write ("type=cntx "); |
| 4508 | 4'b0100: $write ("type=page "); |
| 4509 | 4'b1000: $write ("type=all "); |
| 4510 | default: |
| 4511 | $display ("tlb_sync", `ERROR, |
| 4512 | "Bench Problem - demap_1() should be one-hot."); |
| 4513 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 4514 | endcase |
| 4515 | end |
| 4516 | end |
| 4517 | else begin |
| 4518 | begin // axis tbcall_region |
| 4519 | $write("type=autodemap "); |
| 4520 | end |
| 4521 | end |
| 4522 | |
| 4523 | begin // axis tbcall_region |
| 4524 | $display ("match=%h ts=%0d", |
| 4525 | tlb_match,demap_tstamp*`TOP.core_period); |
| 4526 | end |
| 4527 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 4528 | if (tlb_match[cnt]==1'b1) begin // { |
| 4529 | begin // axis tbcall_region |
| 4530 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 4531 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 4532 | end |
| 4533 | end // } |
| 4534 | end // } |
| 4535 | |
| 4536 | end // } |
| 4537 | |
| 4538 | //---------------------------------------------------------- |
| 4539 | // Send I/DHWTW due to HWTW |
| 4540 | // Send I/DTLBWRITE due to ASI write |
| 4541 | |
| 4542 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 4543 | // These signals will be interleaved between the threads. |
| 4544 | // Need to queue up the signals over time so they can be processed in order. |
| 4545 | // Each thread will only be doing 1 thing at a time. |
| 4546 | |
| 4547 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 4548 | |
| 4549 | for (i=0;i<=7;i=i+1) begin // { |
| 4550 | |
| 4551 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 4552 | $display ("tlb_sync", `ERROR, |
| 4553 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 4554 | end // } |
| 4555 | else begin // { |
| 4556 | |
| 4557 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 4558 | if (data_in[i]) begin // { |
| 4559 | data_in_ready[i] <= 1'b1; |
| 4560 | end // } |
| 4561 | |
| 4562 | // tlb_wr[tid] determines which thread will write next |
| 4563 | // Use fifo to save the tids of the tlb_wr signals in order |
| 4564 | if (tlb_wr[i]) begin // { |
| 4565 | if (data_in_ready[i]) begin // { |
| 4566 | hwtw <= 1'b1; |
| 4567 | mytid[2:0] <= i[2:0]; |
| 4568 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 4569 | data_in_ready[i] <= 1'b0; |
| 4570 | end // } |
| 4571 | else begin // { |
| 4572 | hwtw <= 1'b0; |
| 4573 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 4574 | mytid[2:0] <= i[2:0]; |
| 4575 | end // } |
| 4576 | end // } |
| 4577 | |
| 4578 | end // if} |
| 4579 | end // for} |
| 4580 | |
| 4581 | end // if} |
| 4582 | |
| 4583 | //---------------------------------------------------------- |
| 4584 | // wr_en means that the write is occurring |
| 4585 | if (wr_en) begin // { |
| 4586 | //fifo.pop_fifo ({hwtw,mytid}); |
| 4587 | mytnum = (mycid * 8) + mytid; |
| 4588 | |
| 4589 | //-------------------- |
| 4590 | if (dbg_in) begin // { |
| 4591 | begin // axis tbcall_region |
| 4592 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 4593 | end |
| 4594 | |
| 4595 | begin // axis tbcall_region |
| 4596 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 4597 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 4598 | end |
| 4599 | |
| 4600 | begin // axis tbcall_region |
| 4601 | case (tte_page_mask) |
| 4602 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 4603 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4604 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 4605 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4606 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 4607 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4608 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 4609 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4610 | endcase |
| 4611 | |
| 4612 | if (hwtw) $display (" (hwtw)"); |
| 4613 | else $display (""); |
| 4614 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 4615 | |
| 4616 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 4617 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 4618 | end |
| 4619 | end // } |
| 4620 | //-------------------- |
| 4621 | |
| 4622 | end // } |
| 4623 | |
| 4624 | end // always} |
| 4625 | |
| 4626 | `endif |
| 4627 | //---------------------------------------------------------- |
| 4628 | endmodule |
| 4629 | |
| 4630 | module dtlb_wr_c6 (dbg_in); |
| 4631 | `ifndef GATESIM |
| 4632 | |
| 4633 | parameter NUM_TLB=128; |
| 4634 | |
| 4635 | wire [7:0] data_in; |
| 4636 | wire [7:0] tlb_wr; |
| 4637 | wire wr_en; |
| 4638 | wire [7:0] entry; |
| 4639 | wire [7:0] asi_num; |
| 4640 | wire asi_enable0; // 1 per thread group |
| 4641 | wire asi_enable1; |
| 4642 | // wire [7:0] store_asi; // 1 per thread |
| 4643 | wire [3:0] demap; |
| 4644 | reg [3:0] demap_1; |
| 4645 | wire demap_page; |
| 4646 | wire demap_context; |
| 4647 | wire demap_real; |
| 4648 | wire demap_all; |
| 4649 | wire skip_demap; |
| 4650 | wire demap_active; |
| 4651 | wire auto_demap; |
| 4652 | wire [2:0] demap_tid; |
| 4653 | reg [2:0] demap_tid_1; |
| 4654 | reg [5:0] demap_tnum_1; |
| 4655 | input dbg_in; |
| 4656 | |
| 4657 | reg [(`TS_WIDTH-1):0] tstamp; |
| 4658 | reg hwtw; |
| 4659 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 4660 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 4661 | |
| 4662 | reg [2:0] mytid; |
| 4663 | reg [5:0] mytnum; |
| 4664 | wire [2:0] mycid; |
| 4665 | integer junk; |
| 4666 | integer i; |
| 4667 | reg [7:0] cnt; |
| 4668 | |
| 4669 | assign mycid = 6; |
| 4670 | |
| 4671 | //---------------------------------------------------------- |
| 4672 | // Instantiate fifo - 1 entry per thread |
| 4673 | //fifo fifo (); |
| 4674 | // Define fifo parameters |
| 4675 | `ifndef PALLADIUM |
| 4676 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 4677 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 4678 | defparam fifo.PTR_BITS = 4; |
| 4679 | `endif |
| 4680 | |
| 4681 | //---------------------------------------------------------- |
| 4682 | // DUT probes |
| 4683 | |
| 4684 | assign data_in = `SPC6.mmu.asi.wrote_dtlb; |
| 4685 | assign tlb_wr = `SPC6.mmu_reload_done; |
| 4686 | assign wr_en = `SPC6.lsu.tlb.tlb_wr_1_in_dout; |
| 4687 | |
| 4688 | assign entry = `SPC6.lsu.tlb.rw_index_1[6:0]; |
| 4689 | |
| 4690 | // assign asi_num = `PROBES0.asi_num; |
| 4691 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 4692 | // !`PROBES0.tlb_bypass_b & |
| 4693 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 4694 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 4695 | // !`PROBES0.tlb_bypass_b & |
| 4696 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 4697 | |
| 4698 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 4699 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 4700 | |
| 4701 | |
| 4702 | assign demap_page = `SPC6.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 4703 | assign demap_context = `SPC6.lsu.tlc_demap_context; |
| 4704 | assign demap_real = `SPC6.lsu.tlc_demap_real; |
| 4705 | assign demap_all = `SPC6.lsu.tlc_demap_all; |
| 4706 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 4707 | assign skip_demap =`SPC6.lsu.tlc_wr_u_en; |
| 4708 | assign demap_tid = `SPC6.lsu.tld.tte1[37:35]; |
| 4709 | |
| 4710 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 4711 | assign demap_active = |demap_1 && !skip_demap; |
| 4712 | assign auto_demap = |demap_1 && skip_demap; |
| 4713 | |
| 4714 | //--------------------- |
| 4715 | // Probes for debugging |
| 4716 | |
| 4717 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 4718 | |
| 4719 | // n2_tlb_tl_128x59_cam.sv |
| 4720 | |
| 4721 | `define CNTX1_HI 65 |
| 4722 | `define CNTX1_LO 53 |
| 4723 | `define PID_HI 52 |
| 4724 | `define PID_LO 50 |
| 4725 | `define REAL_BIT 49 |
| 4726 | `define VA_47 48 |
| 4727 | `define VA_28 29 |
| 4728 | `define VA_27 28 |
| 4729 | `define VA_22 23 |
| 4730 | `define TTE_VALID 22 |
| 4731 | `define VA_21 21 |
| 4732 | `define VA_16 16 |
| 4733 | `define VA_15 15 |
| 4734 | `define VA_13 13 |
| 4735 | `define CNTX0_HI 12 |
| 4736 | `define CNTX0_LO 0 |
| 4737 | |
| 4738 | // n2_tlb_tl_128x59_ram.sv |
| 4739 | |
| 4740 | `define DATA_PARITY 36 |
| 4741 | `define DATA_PA_39_28_HI 35 |
| 4742 | `define DATA_PA_39_28_LO 24 |
| 4743 | `define DATA_PA_27_22_HI 23 |
| 4744 | `define DATA_PA_27_22_LO 18 |
| 4745 | `define DATA_VA_27_22_V 17 |
| 4746 | `define DATA_PA_21_16_HI 16 |
| 4747 | `define DATA_PA_21_16_LO 11 |
| 4748 | `define DATA_VA_21_16_V 10 |
| 4749 | `define DATA_PA_15_13_HI 9 |
| 4750 | `define DATA_PA_15_13_LO 7 |
| 4751 | `define DATA_VA_15_13_V 6 |
| 4752 | `define DATA_NFO 5 |
| 4753 | `define DATA_IE 4 |
| 4754 | `define DATA_CP 3 |
| 4755 | `define DATA_X 2 |
| 4756 | `define DATA_P 1 |
| 4757 | `define DATA_W 0 |
| 4758 | |
| 4759 | wire [(NUM_TLB-1):0] tlb_valid; |
| 4760 | wire [(NUM_TLB-1):0] tlb_match; |
| 4761 | wire tte_valid; |
| 4762 | wire [47:0] tte_va; |
| 4763 | wire [12:0] tte_context; |
| 4764 | wire tte_real; |
| 4765 | wire [2:0] tte_pid; |
| 4766 | wire [2:0] tte_page_mask; |
| 4767 | wire [39:0] tte_pa; |
| 4768 | wire tte_nfo; |
| 4769 | wire tte_ie; |
| 4770 | wire tte_cp; |
| 4771 | wire tte_e; |
| 4772 | wire tte_p; |
| 4773 | wire tte_w; |
| 4774 | wire tte_ep; |
| 4775 | |
| 4776 | |
| 4777 | assign tlb_valid = `SPC6.lsu.tlb.array.cam.valid; |
| 4778 | assign tlb_match = `SPC6.lsu.tlb.array.cam.match; |
| 4779 | |
| 4780 | assign tte_va = {`SPC6.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 4781 | `SPC6.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 4782 | `SPC6.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 4783 | `SPC6.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 4784 | 13'b0 |
| 4785 | }; |
| 4786 | assign tte_context = `SPC6.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 4787 | assign tte_pid = `SPC6.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 4788 | assign tte_real = `SPC6.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 4789 | assign tte_valid = `SPC6.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 4790 | |
| 4791 | assign tte_page_mask = `SPC6.lsu.tlb.tte_page_size_mask_1; |
| 4792 | |
| 4793 | assign tte_pa = {`SPC6.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 4794 | `SPC6.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 4795 | `SPC6.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 4796 | `SPC6.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 4797 | 13'b0 |
| 4798 | }; |
| 4799 | assign tte_nfo = `SPC6.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 4800 | assign tte_ie = `SPC6.lsu.tlb.tte_data_1[`DATA_IE]; |
| 4801 | assign tte_cp = `SPC6.lsu.tlb.tte_data_1[`DATA_CP]; |
| 4802 | assign tte_e = `SPC6.lsu.tlb.tte_data_1[`DATA_X]; |
| 4803 | assign tte_p = `SPC6.lsu.tlb.tte_data_1[`DATA_P]; |
| 4804 | assign tte_w = `SPC6.lsu.tlb.tte_data_1[`DATA_W]; |
| 4805 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 4806 | |
| 4807 | //---------------------------------------------------------- |
| 4808 | // Initialize state machine to idle state |
| 4809 | initial begin // { |
| 4810 | `ifndef PALLADIUM |
| 4811 | #1; |
| 4812 | `endif |
| 4813 | hwtw = 1'b0; |
| 4814 | //for (i=0; i<=7; i=i+1) begin |
| 4815 | // my_asi[i] = 8'b0; |
| 4816 | //end |
| 4817 | |
| 4818 | end // } |
| 4819 | |
| 4820 | //---------------------------------------------------------- |
| 4821 | // Must use negedge to avoid race condition |
| 4822 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 4823 | |
| 4824 | always @ (negedge `CPU.l2clk) begin // { |
| 4825 | |
| 4826 | tstamp = `TOP.cycle; |
| 4827 | demap_tstamp = `TOP.cycle; |
| 4828 | |
| 4829 | // Delay by 1 cycle to align with skip_demap |
| 4830 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 4831 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 4832 | demap_1 <= demap; |
| 4833 | |
| 4834 | //---------------------------------------------------------- |
| 4835 | // Send I/DTLBWRITE due to demap |
| 4836 | // |
| 4837 | |
| 4838 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 4839 | $display("tlb_sync", `ERROR, |
| 4840 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 4841 | mycid,demap_tid_1); |
| 4842 | end // } |
| 4843 | |
| 4844 | //if (demap_active) begin // { |
| 4845 | // fifo.pop_fifo ({hwtw,mytid}); |
| 4846 | //end //} |
| 4847 | |
| 4848 | //-------------------- |
| 4849 | if (dbg_in & (|demap_1)) begin // { |
| 4850 | begin // axis tbcall_region |
| 4851 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 4852 | end |
| 4853 | |
| 4854 | if (demap_active) begin |
| 4855 | begin // axis tbcall_region |
| 4856 | case (demap_1) |
| 4857 | 4'b0001: $write ("type=real "); |
| 4858 | 4'b0010: $write ("type=cntx "); |
| 4859 | 4'b0100: $write ("type=page "); |
| 4860 | 4'b1000: $write ("type=all "); |
| 4861 | default: |
| 4862 | $display ("tlb_sync", `ERROR, |
| 4863 | "Bench Problem - demap_1 should be one-hot."); |
| 4864 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 4865 | endcase |
| 4866 | end |
| 4867 | end |
| 4868 | else begin |
| 4869 | begin // axis tbcall_region |
| 4870 | $write ("type=autodemap "); |
| 4871 | end |
| 4872 | end |
| 4873 | |
| 4874 | begin // axis tbcall_region |
| 4875 | $display ("match=%h ts=%0d", |
| 4876 | tlb_match,demap_tstamp*`TOP.core_period); |
| 4877 | end |
| 4878 | |
| 4879 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 4880 | if (tlb_match[cnt]==1'b1) begin // { |
| 4881 | begin // axis tbcall_region |
| 4882 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 4883 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 4884 | end |
| 4885 | end // } |
| 4886 | end // } |
| 4887 | //-------------------- |
| 4888 | end // } |
| 4889 | |
| 4890 | //---------------------------------------------------------- |
| 4891 | // Send I/DHWTW due to HWTW |
| 4892 | // Send I/DTLBWRITE due to ASI write |
| 4893 | |
| 4894 | // Save asi num when DTLBREAD happens. |
| 4895 | // Otherwise, hold state. |
| 4896 | // Send asi num later with DHWTW |
| 4897 | // for (i=0;i<=7;i=i+1) begin // { |
| 4898 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 4899 | // end // } |
| 4900 | |
| 4901 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 4902 | // These signals will be interleaved between the threads. |
| 4903 | // Need to queue up the signals over time so they can be processed in order. |
| 4904 | // Each thread will only be doing 1 thing at a time. |
| 4905 | |
| 4906 | for (i=0;i<=7;i=i+1) begin // { |
| 4907 | |
| 4908 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 4909 | |
| 4910 | // data_in[tid] determines which thread will write next |
| 4911 | // Use fifo to save the tids of the data_in signals in order |
| 4912 | |
| 4913 | if (data_in[i]) begin // { |
| 4914 | mytid[2:0] <= i[2:0]; |
| 4915 | if (tlb_wr[i]) begin // { |
| 4916 | hwtw <= 1'b1; |
| 4917 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 4918 | end // } |
| 4919 | else begin // { |
| 4920 | hwtw <= 1'b0; |
| 4921 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 4922 | end // } |
| 4923 | end // } |
| 4924 | |
| 4925 | end // } |
| 4926 | |
| 4927 | //---------------------------------------------------------- |
| 4928 | // wr_en means that the write is occurring |
| 4929 | if (wr_en) begin // { |
| 4930 | //fifo.pop_fifo ({hwtw,mytid}); |
| 4931 | mytnum = (mycid * 8) + mytid; |
| 4932 | |
| 4933 | //-------------------- |
| 4934 | if (dbg_in) begin // { |
| 4935 | begin // axis tbcall_region |
| 4936 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 4937 | |
| 4938 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 4939 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 4940 | |
| 4941 | case (tte_page_mask) |
| 4942 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 4943 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4944 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 4945 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4946 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 4947 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4948 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 4949 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 4950 | endcase |
| 4951 | |
| 4952 | if (hwtw) $display (" (hwtw)"); |
| 4953 | else $display (""); |
| 4954 | |
| 4955 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 4956 | |
| 4957 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 4958 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 4959 | end // } |
| 4960 | //-------------------- |
| 4961 | |
| 4962 | end // } |
| 4963 | end // } |
| 4964 | |
| 4965 | end // always} |
| 4966 | |
| 4967 | //---------------------------------------------------------- |
| 4968 | `endif |
| 4969 | |
| 4970 | endmodule |
| 4971 | `endif |
| 4972 | |
| 4973 | //---------------------------------------------------------- |
| 4974 | //---------------------------------------------------------- |
| 4975 | |
| 4976 | |
| 4977 | `ifdef CORE_7 |
| 4978 | |
| 4979 | module itlb_wr_c7 (dbg_in); |
| 4980 | `ifndef GATESIM |
| 4981 | |
| 4982 | parameter NUM_TLB=64; |
| 4983 | |
| 4984 | wire [7:0] data_in; |
| 4985 | wire [7:0] tlb_wr; |
| 4986 | wire wr_en; |
| 4987 | wire [7:0] entry; |
| 4988 | wire [3:0] demap; |
| 4989 | reg [3:0] demap_1; |
| 4990 | wire demap_page; |
| 4991 | wire demap_context; |
| 4992 | wire demap_real; |
| 4993 | wire demap_all; |
| 4994 | wire skip_demap; |
| 4995 | wire demap_active; |
| 4996 | wire auto_demap; |
| 4997 | wire [2:0] demap_tid; |
| 4998 | reg [2:0] demap_tid_1; |
| 4999 | reg [5:0] demap_tnum_1; |
| 5000 | wire [7:0] asi_wr_itlb; |
| 5001 | wire [7:0] asi_wr_itlb_demap; |
| 5002 | wire [7:0] asi_wr_itlb_data_in; |
| 5003 | wire [7:0] asi_wr_itlb_data_access; |
| 5004 | input dbg_in; |
| 5005 | |
| 5006 | reg [(`TS_WIDTH-1):0] tstamp; |
| 5007 | reg [7:0] data_in_ready; |
| 5008 | reg hwtw; |
| 5009 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 5010 | reg dbg_en; |
| 5011 | |
| 5012 | reg [2:0] mytid; |
| 5013 | reg [5:0] mytnum; |
| 5014 | wire [2:0] mycid; |
| 5015 | integer junk; |
| 5016 | integer i; |
| 5017 | reg [7:0] cnt; |
| 5018 | |
| 5019 | assign mycid = 7; |
| 5020 | |
| 5021 | //---------------------------------------------------------- |
| 5022 | // Instantiate fifo - 1 entry per thread |
| 5023 | //fifo fifo (); |
| 5024 | // Define fifo parameters |
| 5025 | `ifndef PALLADIUM |
| 5026 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 5027 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 5028 | defparam fifo.PTR_BITS = 4; |
| 5029 | `endif |
| 5030 | |
| 5031 | //---------------------------------------------------------- |
| 5032 | // DUT probes |
| 5033 | |
| 5034 | assign data_in = `SPC7.mmu.asi.htc_wr_itlb_data_in; |
| 5035 | assign wr_en = `SPC7.ifu_ftu.ftu_itb_cust.tlb_wr_1_in_dout; |
| 5036 | |
| 5037 | assign entry = `SPC7.ifu_ftu.ftu_itb_cust.rw_index_1[5:0]; |
| 5038 | |
| 5039 | assign demap_page = `SPC7.ifu_ftu.ftu_itc_ctl.itc_demap_page; |
| 5040 | assign demap_context = `SPC7.ifu_ftu.itc_demap_context; |
| 5041 | assign demap_real = `SPC7.ifu_ftu.itc_demap_real; |
| 5042 | assign demap_all = `SPC7.ifu_ftu.itc_demap_all; |
| 5043 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 5044 | assign skip_demap = `SPC7.ifu_ftu.itc_wr_u_en; |
| 5045 | assign demap_tid = `SPC7.ifu_ftu.ftu_itd_dp.tte1[37:35]; |
| 5046 | |
| 5047 | |
| 5048 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 5049 | assign demap_active = |demap_1 && !skip_demap; |
| 5050 | assign auto_demap = |demap_1 && skip_demap; |
| 5051 | wire [7:0] itlb_wr = {(`SPC7.tlu.trl1.take_itw & `SPC7.tlu.trl1.trap[3]), |
| 5052 | (`SPC7.tlu.trl1.take_itw & `SPC7.tlu.trl1.trap[2]), |
| 5053 | (`SPC7.tlu.trl1.take_itw & `SPC7.tlu.trl1.trap[1]), |
| 5054 | (`SPC7.tlu.trl1.take_itw & `SPC7.tlu.trl1.trap[0]), |
| 5055 | (`SPC7.tlu.trl0.take_itw & `SPC7.tlu.trl0.trap[3]), |
| 5056 | (`SPC7.tlu.trl0.take_itw & `SPC7.tlu.trl0.trap[2]), |
| 5057 | (`SPC7.tlu.trl0.take_itw & `SPC7.tlu.trl0.trap[1]), |
| 5058 | (`SPC7.tlu.trl0.take_itw & `SPC7.tlu.trl0.trap[0]) |
| 5059 | }; |
| 5060 | |
| 5061 | assign tlb_wr = itlb_wr; |
| 5062 | |
| 5063 | // Signals that are early indication that TLBWRITE or TLBWRITE(demap) will happen. |
| 5064 | // Once these signals assert, the write to the TLB cannot be cancelled. |
| 5065 | // These signals assert before the MMU reorders the TLB writes. |
| 5066 | // Use these to suppress SSTEP in nas_pipe. |
| 5067 | // Best case, these signals assert 1 cycle after the previous SSTEP. |
| 5068 | assign asi_wr_itlb_demap = `SPC7.mmu.asi_wr_immu_demap; |
| 5069 | assign asi_wr_itlb_data_in = `SPC7.mmu.asi_wr_itlb_data_in; |
| 5070 | assign asi_wr_itlb_data_access = {`SPC7.mmu.asd1.asi_wr_itlb_data_access, |
| 5071 | `SPC7.mmu.asd0.asi_wr_itlb_data_access}; |
| 5072 | assign asi_wr_itlb = asi_wr_itlb_demap | asi_wr_itlb_data_in | asi_wr_itlb_data_access; |
| 5073 | |
| 5074 | //--------------------- |
| 5075 | // Probes for debugging |
| 5076 | |
| 5077 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl |
| 5078 | |
| 5079 | // n2_tlb_tl_64x59_cam.sv |
| 5080 | |
| 5081 | `define CNTX1_HI 65 |
| 5082 | `define CNTX1_LO 53 |
| 5083 | `define PID_HI 52 |
| 5084 | `define PID_LO 50 |
| 5085 | `define REAL_BIT 49 |
| 5086 | `define VA_47 48 |
| 5087 | `define VA_28 29 |
| 5088 | `define VA_27 28 |
| 5089 | `define VA_22 23 |
| 5090 | `define TTE_VALID 22 |
| 5091 | `define VA_21 21 |
| 5092 | `define VA_16 16 |
| 5093 | `define VA_15 15 |
| 5094 | `define VA_13 13 |
| 5095 | `define CNTX0_HI 12 |
| 5096 | `define CNTX0_LO 0 |
| 5097 | |
| 5098 | // n2_tlb_tl_64x59_ram.sv |
| 5099 | |
| 5100 | `define DATA_PARITY 36 |
| 5101 | `define DATA_PA_39_28_HI 35 |
| 5102 | `define DATA_PA_39_28_LO 24 |
| 5103 | `define DATA_PA_27_22_HI 23 |
| 5104 | `define DATA_PA_27_22_LO 18 |
| 5105 | `define DATA_VA_27_22_V 17 |
| 5106 | `define DATA_PA_21_16_HI 16 |
| 5107 | `define DATA_PA_21_16_LO 11 |
| 5108 | `define DATA_VA_21_16_V 10 |
| 5109 | `define DATA_PA_15_13_HI 9 |
| 5110 | `define DATA_PA_15_13_LO 7 |
| 5111 | `define DATA_VA_15_13_V 6 |
| 5112 | `define DATA_NFO 5 |
| 5113 | `define DATA_IE 4 |
| 5114 | `define DATA_CP 3 |
| 5115 | `define DATA_X 2 |
| 5116 | `define DATA_P 1 |
| 5117 | `define DATA_W 0 |
| 5118 | |
| 5119 | wire [(NUM_TLB-1):0] tlb_valid; |
| 5120 | wire [(NUM_TLB-1):0] tlb_match; |
| 5121 | wire tte_valid; |
| 5122 | wire [47:0] tte_va; |
| 5123 | wire [12:0] tte_context; |
| 5124 | wire tte_real; |
| 5125 | wire [2:0] tte_pid; |
| 5126 | wire [2:0] tte_page_mask; |
| 5127 | wire [39:0] tte_pa; |
| 5128 | wire tte_nfo; |
| 5129 | wire tte_ie; |
| 5130 | wire tte_cp; |
| 5131 | wire tte_e; |
| 5132 | wire tte_p; |
| 5133 | wire tte_w; |
| 5134 | wire tte_ep; |
| 5135 | |
| 5136 | assign tlb_valid = `SPC7.ifu_ftu.ftu_itb_cust.array.cam.valid; |
| 5137 | assign tlb_match = `SPC7.ifu_ftu.ftu_itb_cust.array.cam.match; |
| 5138 | |
| 5139 | assign tte_va = {`SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_47:`VA_28], |
| 5140 | `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_27:`VA_22], |
| 5141 | `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_21:`VA_16], |
| 5142 | `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`VA_15:`VA_13], |
| 5143 | 13'b0 |
| 5144 | }; |
| 5145 | assign tte_context = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 5146 | assign tte_pid = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 5147 | assign tte_real = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`REAL_BIT]; |
| 5148 | assign tte_valid = `SPC7.ifu_ftu.ftu_itb_cust.tte_tag_1_dout[`TTE_VALID]; |
| 5149 | |
| 5150 | assign tte_page_mask = `SPC7.ifu_ftu.ftu_itb_cust.tte_page_size_mask_1; |
| 5151 | |
| 5152 | assign tte_pa = {`SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 5153 | `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 5154 | `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 5155 | `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 5156 | 13'b0 |
| 5157 | }; |
| 5158 | assign tte_nfo = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_NFO]; |
| 5159 | assign tte_ie = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_IE]; |
| 5160 | assign tte_cp = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_CP]; |
| 5161 | assign tte_e = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_X]; |
| 5162 | assign tte_p = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_P]; |
| 5163 | assign tte_w = `SPC7.ifu_ftu.ftu_itb_cust.tte_data_1[`DATA_W]; |
| 5164 | assign tte_ep = 1'b1; // not stored in array, but implied as 1 |
| 5165 | |
| 5166 | //---------------------------------------------------------- |
| 5167 | initial begin // { |
| 5168 | `ifndef PALLADIUM |
| 5169 | #1; |
| 5170 | `endif |
| 5171 | hwtw = 1'b0; |
| 5172 | data_in_ready = 8'b0; |
| 5173 | end // } |
| 5174 | |
| 5175 | //---------------------------------------------------------- |
| 5176 | // Must use negedge to avoid race condition |
| 5177 | // tlb_replacement_index (aka entry) is created in always block using blocking assignments |
| 5178 | |
| 5179 | always @ (negedge `CPU.l2clk) begin // { |
| 5180 | |
| 5181 | tstamp = `TOP.cycle; |
| 5182 | demap_tstamp = `TOP.cycle; |
| 5183 | |
| 5184 | // Delay by 1 cycle to align with skip_demap |
| 5185 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 5186 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 5187 | demap_1 <= demap; |
| 5188 | |
| 5189 | |
| 5190 | //---------------------------------------------------------- |
| 5191 | // Send I/DTLBWRITE due to demap |
| 5192 | // |
| 5193 | |
| 5194 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 5195 | $display("tlb_sync", `ERROR, |
| 5196 | "C%0d T%0d Illegal Back to Back ITLB demap", |
| 5197 | mycid,demap_tid_1); |
| 5198 | end // } |
| 5199 | |
| 5200 | //if (demap_active) begin // { |
| 5201 | // fifo.pop_fifo ({hwtw,mytid}); |
| 5202 | //end |
| 5203 | //-------------------- |
| 5204 | if (dbg_in & (|demap_1)) begin // { |
| 5205 | begin // axis tbcall_region |
| 5206 | $write ("SHOW_TLB: ITLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 5207 | end |
| 5208 | |
| 5209 | if (demap_active) begin |
| 5210 | begin // axis tbcall_region |
| 5211 | case (demap_1) |
| 5212 | 4'b0001: $write ("type=real "); |
| 5213 | 4'b0010: $write ("type=cntx "); |
| 5214 | 4'b0100: $write ("type=page "); |
| 5215 | 4'b1000: $write ("type=all "); |
| 5216 | default: |
| 5217 | $display ("tlb_sync", `ERROR, |
| 5218 | "Bench Problem - demap_1() should be one-hot."); |
| 5219 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 5220 | endcase |
| 5221 | end |
| 5222 | end |
| 5223 | else begin |
| 5224 | begin // axis tbcall_region |
| 5225 | $write("type=autodemap "); |
| 5226 | end |
| 5227 | end |
| 5228 | |
| 5229 | begin // axis tbcall_region |
| 5230 | $display ("match=%h ts=%0d", |
| 5231 | tlb_match,demap_tstamp*`TOP.core_period); |
| 5232 | end |
| 5233 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 5234 | if (tlb_match[cnt]==1'b1) begin // { |
| 5235 | begin // axis tbcall_region |
| 5236 | $display ("SHOW_TLB: ITLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 5237 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 5238 | end |
| 5239 | end // } |
| 5240 | end // } |
| 5241 | |
| 5242 | end // } |
| 5243 | |
| 5244 | //---------------------------------------------------------- |
| 5245 | // Send I/DHWTW due to HWTW |
| 5246 | // Send I/DTLBWRITE due to ASI write |
| 5247 | |
| 5248 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 5249 | // These signals will be interleaved between the threads. |
| 5250 | // Need to queue up the signals over time so they can be processed in order. |
| 5251 | // Each thread will only be doing 1 thing at a time. |
| 5252 | |
| 5253 | if ((tlb_wr!=8'b0) || (data_in!=8'b0)) begin // { |
| 5254 | |
| 5255 | for (i=0;i<=7;i=i+1) begin // { |
| 5256 | |
| 5257 | if ((data_in[i])&&(tlb_wr[i])) begin // { |
| 5258 | $display ("tlb_sync", `ERROR, |
| 5259 | "Bad Inputs - iwr_data_in & iwr_tlb_wr should not be asserted at same time"); |
| 5260 | end // } |
| 5261 | else begin // { |
| 5262 | |
| 5263 | // data_in[tid] determines if the write is HWTW or TLBWRITE |
| 5264 | if (data_in[i]) begin // { |
| 5265 | data_in_ready[i] <= 1'b1; |
| 5266 | end // } |
| 5267 | |
| 5268 | // tlb_wr[tid] determines which thread will write next |
| 5269 | // Use fifo to save the tids of the tlb_wr signals in order |
| 5270 | if (tlb_wr[i]) begin // { |
| 5271 | if (data_in_ready[i]) begin // { |
| 5272 | hwtw <= 1'b1; |
| 5273 | mytid[2:0] <= i[2:0]; |
| 5274 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 5275 | data_in_ready[i] <= 1'b0; |
| 5276 | end // } |
| 5277 | else begin // { |
| 5278 | hwtw <= 1'b0; |
| 5279 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 5280 | mytid[2:0] <= i[2:0]; |
| 5281 | end // } |
| 5282 | end // } |
| 5283 | |
| 5284 | end // if} |
| 5285 | end // for} |
| 5286 | |
| 5287 | end // if} |
| 5288 | |
| 5289 | //---------------------------------------------------------- |
| 5290 | // wr_en means that the write is occurring |
| 5291 | if (wr_en) begin // { |
| 5292 | //fifo.pop_fifo ({hwtw,mytid}); |
| 5293 | mytnum = (mycid * 8) + mytid; |
| 5294 | |
| 5295 | //-------------------- |
| 5296 | if (dbg_in) begin // { |
| 5297 | begin // axis tbcall_region |
| 5298 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 5299 | end |
| 5300 | |
| 5301 | begin // axis tbcall_region |
| 5302 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 5303 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 5304 | end |
| 5305 | |
| 5306 | begin // axis tbcall_region |
| 5307 | case (tte_page_mask) |
| 5308 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 5309 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5310 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 5311 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5312 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 5313 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5314 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 5315 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5316 | endcase |
| 5317 | |
| 5318 | if (hwtw) $display (" (hwtw)"); |
| 5319 | else $display (""); |
| 5320 | $write ("SHOW_TLB: ITLB_WRITE C%0d T%0d ",mycid,mytid); |
| 5321 | |
| 5322 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=%b W=%b ts=%0d", |
| 5323 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_ep,tte_w,tstamp*`TOP.core_period); |
| 5324 | end |
| 5325 | end // } |
| 5326 | //-------------------- |
| 5327 | |
| 5328 | end // } |
| 5329 | |
| 5330 | end // always} |
| 5331 | |
| 5332 | `endif |
| 5333 | //---------------------------------------------------------- |
| 5334 | endmodule |
| 5335 | |
| 5336 | module dtlb_wr_c7 (dbg_in); |
| 5337 | `ifndef GATESIM |
| 5338 | |
| 5339 | parameter NUM_TLB=128; |
| 5340 | |
| 5341 | wire [7:0] data_in; |
| 5342 | wire [7:0] tlb_wr; |
| 5343 | wire wr_en; |
| 5344 | wire [7:0] entry; |
| 5345 | wire [7:0] asi_num; |
| 5346 | wire asi_enable0; // 1 per thread group |
| 5347 | wire asi_enable1; |
| 5348 | // wire [7:0] store_asi; // 1 per thread |
| 5349 | wire [3:0] demap; |
| 5350 | reg [3:0] demap_1; |
| 5351 | wire demap_page; |
| 5352 | wire demap_context; |
| 5353 | wire demap_real; |
| 5354 | wire demap_all; |
| 5355 | wire skip_demap; |
| 5356 | wire demap_active; |
| 5357 | wire auto_demap; |
| 5358 | wire [2:0] demap_tid; |
| 5359 | reg [2:0] demap_tid_1; |
| 5360 | reg [5:0] demap_tnum_1; |
| 5361 | input dbg_in; |
| 5362 | |
| 5363 | reg [(`TS_WIDTH-1):0] tstamp; |
| 5364 | reg hwtw; |
| 5365 | // reg [7:0] my_asi [0:7]; // 1 asi number stored per thread |
| 5366 | reg [(`TS_WIDTH-1):0] demap_tstamp; |
| 5367 | |
| 5368 | reg [2:0] mytid; |
| 5369 | reg [5:0] mytnum; |
| 5370 | wire [2:0] mycid; |
| 5371 | integer junk; |
| 5372 | integer i; |
| 5373 | reg [7:0] cnt; |
| 5374 | |
| 5375 | assign mycid = 7; |
| 5376 | |
| 5377 | //---------------------------------------------------------- |
| 5378 | // Instantiate fifo - 1 entry per thread |
| 5379 | //fifo fifo (); |
| 5380 | // Define fifo parameters |
| 5381 | `ifndef PALLADIUM |
| 5382 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} |
| 5383 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection |
| 5384 | defparam fifo.PTR_BITS = 4; |
| 5385 | `endif |
| 5386 | |
| 5387 | //---------------------------------------------------------- |
| 5388 | // DUT probes |
| 5389 | |
| 5390 | assign data_in = `SPC7.mmu.asi.wrote_dtlb; |
| 5391 | assign tlb_wr = `SPC7.mmu_reload_done; |
| 5392 | assign wr_en = `SPC7.lsu.tlb.tlb_wr_1_in_dout; |
| 5393 | |
| 5394 | assign entry = `SPC7.lsu.tlb.rw_index_1[6:0]; |
| 5395 | |
| 5396 | // assign asi_num = `PROBES0.asi_num; |
| 5397 | // assign asi_enable0 = `PROBES0.tlb_rd_vld_b & |
| 5398 | // !`PROBES0.tlb_bypass_b & |
| 5399 | // `SPC0.tlu.fls0.lsu_inst_b; |
| 5400 | //assign asi_enable1 = `PROBES0.tlb_rd_vld_b & |
| 5401 | // !`PROBES0.tlb_bypass_b & |
| 5402 | // `SPC0.tlu.fls1.lsu_inst_b; |
| 5403 | |
| 5404 | // assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; |
| 5405 | // assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; |
| 5406 | |
| 5407 | |
| 5408 | assign demap_page = `SPC7.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); |
| 5409 | assign demap_context = `SPC7.lsu.tlc_demap_context; |
| 5410 | assign demap_real = `SPC7.lsu.tlc_demap_real; |
| 5411 | assign demap_all = `SPC7.lsu.tlc_demap_all; |
| 5412 | assign demap = {demap_all,demap_page,demap_context,demap_real}; |
| 5413 | assign skip_demap =`SPC7.lsu.tlc_wr_u_en; |
| 5414 | assign demap_tid = `SPC7.lsu.tld.tte1[37:35]; |
| 5415 | |
| 5416 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS |
| 5417 | assign demap_active = |demap_1 && !skip_demap; |
| 5418 | assign auto_demap = |demap_1 && skip_demap; |
| 5419 | |
| 5420 | //--------------------- |
| 5421 | // Probes for debugging |
| 5422 | |
| 5423 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl |
| 5424 | |
| 5425 | // n2_tlb_tl_128x59_cam.sv |
| 5426 | |
| 5427 | `define CNTX1_HI 65 |
| 5428 | `define CNTX1_LO 53 |
| 5429 | `define PID_HI 52 |
| 5430 | `define PID_LO 50 |
| 5431 | `define REAL_BIT 49 |
| 5432 | `define VA_47 48 |
| 5433 | `define VA_28 29 |
| 5434 | `define VA_27 28 |
| 5435 | `define VA_22 23 |
| 5436 | `define TTE_VALID 22 |
| 5437 | `define VA_21 21 |
| 5438 | `define VA_16 16 |
| 5439 | `define VA_15 15 |
| 5440 | `define VA_13 13 |
| 5441 | `define CNTX0_HI 12 |
| 5442 | `define CNTX0_LO 0 |
| 5443 | |
| 5444 | // n2_tlb_tl_128x59_ram.sv |
| 5445 | |
| 5446 | `define DATA_PARITY 36 |
| 5447 | `define DATA_PA_39_28_HI 35 |
| 5448 | `define DATA_PA_39_28_LO 24 |
| 5449 | `define DATA_PA_27_22_HI 23 |
| 5450 | `define DATA_PA_27_22_LO 18 |
| 5451 | `define DATA_VA_27_22_V 17 |
| 5452 | `define DATA_PA_21_16_HI 16 |
| 5453 | `define DATA_PA_21_16_LO 11 |
| 5454 | `define DATA_VA_21_16_V 10 |
| 5455 | `define DATA_PA_15_13_HI 9 |
| 5456 | `define DATA_PA_15_13_LO 7 |
| 5457 | `define DATA_VA_15_13_V 6 |
| 5458 | `define DATA_NFO 5 |
| 5459 | `define DATA_IE 4 |
| 5460 | `define DATA_CP 3 |
| 5461 | `define DATA_X 2 |
| 5462 | `define DATA_P 1 |
| 5463 | `define DATA_W 0 |
| 5464 | |
| 5465 | wire [(NUM_TLB-1):0] tlb_valid; |
| 5466 | wire [(NUM_TLB-1):0] tlb_match; |
| 5467 | wire tte_valid; |
| 5468 | wire [47:0] tte_va; |
| 5469 | wire [12:0] tte_context; |
| 5470 | wire tte_real; |
| 5471 | wire [2:0] tte_pid; |
| 5472 | wire [2:0] tte_page_mask; |
| 5473 | wire [39:0] tte_pa; |
| 5474 | wire tte_nfo; |
| 5475 | wire tte_ie; |
| 5476 | wire tte_cp; |
| 5477 | wire tte_e; |
| 5478 | wire tte_p; |
| 5479 | wire tte_w; |
| 5480 | wire tte_ep; |
| 5481 | |
| 5482 | |
| 5483 | assign tlb_valid = `SPC7.lsu.tlb.array.cam.valid; |
| 5484 | assign tlb_match = `SPC7.lsu.tlb.array.cam.match; |
| 5485 | |
| 5486 | assign tte_va = {`SPC7.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], |
| 5487 | `SPC7.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], |
| 5488 | `SPC7.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], |
| 5489 | `SPC7.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], |
| 5490 | 13'b0 |
| 5491 | }; |
| 5492 | assign tte_context = `SPC7.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; |
| 5493 | assign tte_pid = `SPC7.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; |
| 5494 | assign tte_real = `SPC7.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; |
| 5495 | assign tte_valid = `SPC7.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; |
| 5496 | |
| 5497 | assign tte_page_mask = `SPC7.lsu.tlb.tte_page_size_mask_1; |
| 5498 | |
| 5499 | assign tte_pa = {`SPC7.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 5500 | `SPC7.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 5501 | `SPC7.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 5502 | `SPC7.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], |
| 5503 | 13'b0 |
| 5504 | }; |
| 5505 | assign tte_nfo = `SPC7.lsu.tlb.tte_data_1[`DATA_NFO]; |
| 5506 | assign tte_ie = `SPC7.lsu.tlb.tte_data_1[`DATA_IE]; |
| 5507 | assign tte_cp = `SPC7.lsu.tlb.tte_data_1[`DATA_CP]; |
| 5508 | assign tte_e = `SPC7.lsu.tlb.tte_data_1[`DATA_X]; |
| 5509 | assign tte_p = `SPC7.lsu.tlb.tte_data_1[`DATA_P]; |
| 5510 | assign tte_w = `SPC7.lsu.tlb.tte_data_1[`DATA_W]; |
| 5511 | assign tte_ep = 1'b1; // Does not apply for DTLB |
| 5512 | |
| 5513 | //---------------------------------------------------------- |
| 5514 | // Initialize state machine to idle state |
| 5515 | initial begin // { |
| 5516 | `ifndef PALLADIUM |
| 5517 | #1; |
| 5518 | `endif |
| 5519 | hwtw = 1'b0; |
| 5520 | //for (i=0; i<=7; i=i+1) begin |
| 5521 | // my_asi[i] = 8'b0; |
| 5522 | //end |
| 5523 | |
| 5524 | end // } |
| 5525 | |
| 5526 | //---------------------------------------------------------- |
| 5527 | // Must use negedge to avoid race condition |
| 5528 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments |
| 5529 | |
| 5530 | always @ (negedge `CPU.l2clk) begin // { |
| 5531 | |
| 5532 | tstamp = `TOP.cycle; |
| 5533 | demap_tstamp = `TOP.cycle; |
| 5534 | |
| 5535 | // Delay by 1 cycle to align with skip_demap |
| 5536 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted |
| 5537 | demap_tnum_1 <= (mycid * 8) + demap_tid; |
| 5538 | demap_1 <= demap; |
| 5539 | |
| 5540 | //---------------------------------------------------------- |
| 5541 | // Send I/DTLBWRITE due to demap |
| 5542 | // |
| 5543 | |
| 5544 | if ((demap!=0) && (demap_1!=0)) begin // { |
| 5545 | $display("tlb_sync", `ERROR, |
| 5546 | "C%0d T%0d Illegal Back to Back DTLB demap", |
| 5547 | mycid,demap_tid_1); |
| 5548 | end // } |
| 5549 | |
| 5550 | //if (demap_active) begin // { |
| 5551 | // fifo.pop_fifo ({hwtw,mytid}); |
| 5552 | //end //} |
| 5553 | |
| 5554 | //-------------------- |
| 5555 | if (dbg_in & (|demap_1)) begin // { |
| 5556 | begin // axis tbcall_region |
| 5557 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); |
| 5558 | end |
| 5559 | |
| 5560 | if (demap_active) begin |
| 5561 | begin // axis tbcall_region |
| 5562 | case (demap_1) |
| 5563 | 4'b0001: $write ("type=real "); |
| 5564 | 4'b0010: $write ("type=cntx "); |
| 5565 | 4'b0100: $write ("type=page "); |
| 5566 | 4'b1000: $write ("type=all "); |
| 5567 | default: |
| 5568 | $display ("tlb_sync", `ERROR, |
| 5569 | "Bench Problem - demap_1 should be one-hot."); |
| 5570 | // "Bench Problem - demap_1(%b) should be one-hot.",demap_1); |
| 5571 | endcase |
| 5572 | end |
| 5573 | end |
| 5574 | else begin |
| 5575 | begin // axis tbcall_region |
| 5576 | $write ("type=autodemap "); |
| 5577 | end |
| 5578 | end |
| 5579 | |
| 5580 | begin // axis tbcall_region |
| 5581 | $display ("match=%h ts=%0d", |
| 5582 | tlb_match,demap_tstamp*`TOP.core_period); |
| 5583 | end |
| 5584 | |
| 5585 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { |
| 5586 | if (tlb_match[cnt]==1'b1) begin // { |
| 5587 | begin // axis tbcall_region |
| 5588 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", |
| 5589 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); |
| 5590 | end |
| 5591 | end // } |
| 5592 | end // } |
| 5593 | //-------------------- |
| 5594 | end // } |
| 5595 | |
| 5596 | //---------------------------------------------------------- |
| 5597 | // Send I/DHWTW due to HWTW |
| 5598 | // Send I/DTLBWRITE due to ASI write |
| 5599 | |
| 5600 | // Save asi num when DTLBREAD happens. |
| 5601 | // Otherwise, hold state. |
| 5602 | // Send asi num later with DHWTW |
| 5603 | // for (i=0;i<=7;i=i+1) begin // { |
| 5604 | // my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; |
| 5605 | // end // } |
| 5606 | |
| 5607 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) |
| 5608 | // These signals will be interleaved between the threads. |
| 5609 | // Need to queue up the signals over time so they can be processed in order. |
| 5610 | // Each thread will only be doing 1 thing at a time. |
| 5611 | |
| 5612 | for (i=0;i<=7;i=i+1) begin // { |
| 5613 | |
| 5614 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE |
| 5615 | |
| 5616 | // data_in[tid] determines which thread will write next |
| 5617 | // Use fifo to save the tids of the data_in signals in order |
| 5618 | |
| 5619 | if (data_in[i]) begin // { |
| 5620 | mytid[2:0] <= i[2:0]; |
| 5621 | if (tlb_wr[i]) begin // { |
| 5622 | hwtw <= 1'b1; |
| 5623 | //fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} |
| 5624 | end // } |
| 5625 | else begin // { |
| 5626 | hwtw <= 1'b0; |
| 5627 | //fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} |
| 5628 | end // } |
| 5629 | end // } |
| 5630 | |
| 5631 | end // } |
| 5632 | |
| 5633 | //---------------------------------------------------------- |
| 5634 | // wr_en means that the write is occurring |
| 5635 | if (wr_en) begin // { |
| 5636 | //fifo.pop_fifo ({hwtw,mytid}); |
| 5637 | mytnum = (mycid * 8) + mytid; |
| 5638 | |
| 5639 | //-------------------- |
| 5640 | if (dbg_in) begin // { |
| 5641 | begin // axis tbcall_region |
| 5642 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 5643 | |
| 5644 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); |
| 5645 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); |
| 5646 | |
| 5647 | case (tte_page_mask) |
| 5648 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", |
| 5649 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5650 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", |
| 5651 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5652 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", |
| 5653 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5654 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", |
| 5655 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); |
| 5656 | endcase |
| 5657 | |
| 5658 | if (hwtw) $display (" (hwtw)"); |
| 5659 | else $display (""); |
| 5660 | |
| 5661 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); |
| 5662 | |
| 5663 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", |
| 5664 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); |
| 5665 | end // } |
| 5666 | //-------------------- |
| 5667 | |
| 5668 | end // } |
| 5669 | end // } |
| 5670 | |
| 5671 | end // always} |
| 5672 | |
| 5673 | //---------------------------------------------------------- |
| 5674 | `endif |
| 5675 | |
| 5676 | endmodule |
| 5677 | `endif |
| 5678 | |
| 5679 | //---------------------------------------------------------- |
| 5680 | //---------------------------------------------------------- |
| 5681 | |
| 5682 | |