| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fc_noreset_force.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | initial |
| 36 | begin |
| 37 | force `CPU.tcu_ncu_vld = 1'b0; |
| 38 | force `CPU.tcu_ncu_stall = 1'b0; |
| 39 | force `CPU.rst_ncu_vld = 1'b0; |
| 40 | force `CPU.rst_ncu_stall = 1'b0; |
| 41 | force `CPU.rst_ncu_xir_ =1'b1; |
| 42 | |
| 43 | force `CPU.ccu_ncu_vld = 1'b0; |
| 44 | force `CPU.ccu_ncu_stall = 1'b0; |
| 45 | |
| 46 | force TRST_L = 1'b0; |
| 47 | force PWRON_RST_L = 1'b1; |
| 48 | force `TCU.ncu_tcu_bank_avail[7:0] = 8'b11111111; |
| 49 | force `CPU.sio.niu_sio_dq = 1'b0; |
| 50 | force `CPU.niu_ncu_vld = 1'b0; |
| 51 | force `CPU.niu_ncu_stall = 1'b0; |
| 52 | force `CPU.ncu.iol2clk = 0; |
| 53 | force `CPU.ncu.cmp_io_sync_en = 0; |
| 54 | force `CPU.ncu.io_cmp_sync_en = 0; |
| 55 | |
| 56 | force `CPU.ncu.aclk_cmp = 0; |
| 57 | force `CPU.ncu.aclk_io = 0; |
| 58 | force `CPU.ncu.bclk_cmp = 0; |
| 59 | force `CPU.ncu.bclk_io = 0; |
| 60 | |
| 61 | force `CPU.tcu_spc0_scan_en = 1'b0; |
| 62 | force `CPU.tcu_spc1_scan_en = 1'b0; |
| 63 | force `CPU.tcu_spc2_scan_en = 1'b0; |
| 64 | force `CPU.tcu_spc3_scan_en = 1'b0; |
| 65 | force `CPU.tcu_spc4_scan_en = 1'b0; |
| 66 | force `CPU.tcu_spc5_scan_en = 1'b0; |
| 67 | force `CPU.tcu_spc6_scan_en = 1'b0; |
| 68 | force `CPU.tcu_spc7_scan_en = 1'b0; |
| 69 | |
| 70 | force `CPU.tcu_spc0_aclk = 1'b0; |
| 71 | force `CPU.tcu_spc1_aclk = 1'b0; |
| 72 | force `CPU.tcu_spc2_aclk = 1'b0; |
| 73 | force `CPU.tcu_spc3_aclk = 1'b0; |
| 74 | force `CPU.tcu_spc4_aclk = 1'b0; |
| 75 | force `CPU.tcu_spc5_aclk = 1'b0; |
| 76 | force `CPU.tcu_spc6_aclk = 1'b0; |
| 77 | force `CPU.tcu_spc7_aclk = 1'b0; |
| 78 | force `CPU.tcu_spc0_bclk = 1'b0; |
| 79 | force `CPU.tcu_spc1_bclk = 1'b0; |
| 80 | force `CPU.tcu_spc2_bclk = 1'b0; |
| 81 | force `CPU.tcu_spc3_bclk = 1'b0; |
| 82 | force `CPU.tcu_spc4_bclk = 1'b0; |
| 83 | force `CPU.tcu_spc5_bclk = 1'b0; |
| 84 | force `CPU.tcu_spc6_bclk = 1'b0; |
| 85 | force `CPU.tcu_spc7_bclk = 1'b0; |
| 86 | |
| 87 | force `CPU.tcu_spc0_clk_stop = 1'b0; |
| 88 | force `CPU.tcu_spc1_clk_stop = 1'b0; |
| 89 | force `CPU.tcu_spc2_clk_stop = 1'b0; |
| 90 | force `CPU.tcu_spc3_clk_stop = 1'b0; |
| 91 | force `CPU.tcu_spc4_clk_stop = 1'b0; |
| 92 | force `CPU.tcu_spc5_clk_stop = 1'b0; |
| 93 | force `CPU.tcu_spc6_clk_stop = 1'b0; |
| 94 | force `CPU.tcu_spc7_clk_stop = 1'b0; |
| 95 | |
| 96 | force `CPU.ccx.gl_ccx_clk_stop_left = 0; |
| 97 | force `CPU.ccx.gl_ccx_clk_stop_right = 0; |
| 98 | |
| 99 | force `CPU.tcu_spc0_se_scancollar_in = 1'b0; |
| 100 | force `CPU.tcu_spc1_se_scancollar_in = 1'b0; |
| 101 | force `CPU.tcu_spc2_se_scancollar_in = 1'b0; |
| 102 | force `CPU.tcu_spc3_se_scancollar_in = 1'b0; |
| 103 | force `CPU.tcu_spc4_se_scancollar_in = 1'b0; |
| 104 | force `CPU.tcu_spc5_se_scancollar_in = 1'b0; |
| 105 | force `CPU.tcu_spc6_se_scancollar_in = 1'b0; |
| 106 | force `CPU.tcu_spc7_se_scancollar_in = 1'b0; |
| 107 | |
| 108 | force `CPU.tcu_spc0_se_scancollar_out = 1'b0; |
| 109 | force `CPU.tcu_spc1_se_scancollar_out = 1'b0; |
| 110 | force `CPU.tcu_spc2_se_scancollar_out = 1'b0; |
| 111 | force `CPU.tcu_spc3_se_scancollar_out = 1'b0; |
| 112 | force `CPU.tcu_spc4_se_scancollar_out = 1'b0; |
| 113 | force `CPU.tcu_spc5_se_scancollar_out = 1'b0; |
| 114 | force `CPU.tcu_spc6_se_scancollar_out = 1'b0; |
| 115 | force `CPU.tcu_spc7_se_scancollar_out = 1'b0; |
| 116 | |
| 117 | force `CPU.tcu_spc0_array_wr_inhibit = 1'b0; |
| 118 | force `CPU.tcu_spc1_array_wr_inhibit = 1'b0; |
| 119 | force `CPU.tcu_spc2_array_wr_inhibit = 1'b0; |
| 120 | force `CPU.tcu_spc3_array_wr_inhibit = 1'b0; |
| 121 | force `CPU.tcu_spc4_array_wr_inhibit = 1'b0; |
| 122 | force `CPU.tcu_spc5_array_wr_inhibit = 1'b0; |
| 123 | force `CPU.tcu_spc6_array_wr_inhibit = 1'b0; |
| 124 | force `CPU.tcu_spc7_array_wr_inhibit = 1'b0; |
| 125 | |
| 126 | force `CPU.tcu_spc0_shscan_clk_stop = 1'b0; |
| 127 | force `CPU.tcu_spc1_shscan_clk_stop = 1'b0; |
| 128 | force `CPU.tcu_spc2_shscan_clk_stop = 1'b0; |
| 129 | force `CPU.tcu_spc3_shscan_clk_stop = 1'b0; |
| 130 | force `CPU.tcu_spc4_shscan_clk_stop = 1'b0; |
| 131 | force `CPU.tcu_spc5_shscan_clk_stop = 1'b0; |
| 132 | force `CPU.tcu_spc6_shscan_clk_stop = 1'b0; |
| 133 | force `CPU.tcu_spc7_shscan_clk_stop = 1'b0; |
| 134 | |
| 135 | force `CPU.tcu_spc0_mbist_scan_in = 1'b0; |
| 136 | force `CPU.tcu_spc1_mbist_scan_in = 1'b0; |
| 137 | force `CPU.tcu_spc2_mbist_scan_in = 1'b0; |
| 138 | force `CPU.tcu_spc3_mbist_scan_in = 1'b0; |
| 139 | force `CPU.tcu_spc4_mbist_scan_in = 1'b0; |
| 140 | force `CPU.tcu_spc5_mbist_scan_in = 1'b0; |
| 141 | force `CPU.tcu_spc6_mbist_scan_in = 1'b0; |
| 142 | force `CPU.tcu_spc7_mbist_scan_in = 1'b0; |
| 143 | |
| 144 | force `CPU.tcu_l2t0_shscan_clk_stop = 1'b0; |
| 145 | force `CPU.tcu_l2t1_shscan_clk_stop = 1'b0; |
| 146 | force `CPU.tcu_l2t2_shscan_clk_stop = 1'b0; |
| 147 | force `CPU.tcu_l2t3_shscan_clk_stop = 1'b0; |
| 148 | force `CPU.tcu_l2t4_shscan_clk_stop = 1'b0; |
| 149 | force `CPU.tcu_l2t5_shscan_clk_stop = 1'b0; |
| 150 | force `CPU.tcu_l2t6_shscan_clk_stop = 1'b0; |
| 151 | force `CPU.tcu_l2t7_shscan_clk_stop = 1'b0; |
| 152 | |
| 153 | |
| 154 | force `CPU.tcu_spc_mbist_start = 24'b0; |
| 155 | force `CPU.tcu_spc_lbist_start = 8'b0; |
| 156 | force `CPU.tcu_sio_mbist_start = 2'b0; |
| 157 | force `CPU.tcu_sii_mbist_start = 2'b0; |
| 158 | force `CPU.tcu_ncu_mbist_start = 2'b0; |
| 159 | force `CPU.tcu_mcu0_mbist_start = 1'b0; |
| 160 | force `CPU.tcu_mcu1_mbist_start = 1'b0; |
| 161 | force `CPU.tcu_mcu2_mbist_start = 1'b0; |
| 162 | force `CPU.tcu_mcu3_mbist_start = 1'b0; |
| 163 | force `CPU.tcu_l2b0_mbist_start = 1'b0; |
| 164 | force `CPU.tcu_l2b1_mbist_start = 1'b0; |
| 165 | force `CPU.tcu_l2b2_mbist_start = 1'b0; |
| 166 | force `CPU.tcu_l2b3_mbist_start = 1'b0; |
| 167 | force `CPU.tcu_l2b4_mbist_start = 1'b0; |
| 168 | force `CPU.tcu_l2b5_mbist_start = 1'b0; |
| 169 | force `CPU.tcu_l2b6_mbist_start = 1'b0; |
| 170 | force `CPU.tcu_l2b7_mbist_start = 1'b0; |
| 171 | force `CPU.tcu_l2t0_mbist_start = 3'b0; |
| 172 | force `CPU.tcu_l2t1_mbist_start = 3'b0; |
| 173 | force `CPU.tcu_l2t2_mbist_start = 3'b0; |
| 174 | force `CPU.tcu_l2t3_mbist_start = 3'b0; |
| 175 | force `CPU.tcu_l2t4_mbist_start = 3'b0; |
| 176 | force `CPU.tcu_l2t5_mbist_start = 3'b0; |
| 177 | force `CPU.tcu_l2t6_mbist_start = 3'b0; |
| 178 | force `CPU.tcu_l2t7_mbist_start = 3'b0; |
| 179 | force `CPU.tcu_dmu_mbist_start = 2'b0; |
| 180 | force `CPU.tcu_peu_mbist_start = 1'b0; |
| 181 | |
| 182 | force `CPU.tcu_l2d0_clk_stop = 1'b0; |
| 183 | force `CPU.tcu_l2d1_clk_stop = 1'b0; |
| 184 | force `CPU.tcu_l2d2_clk_stop = 1'b0; |
| 185 | force `CPU.tcu_l2d3_clk_stop = 1'b0; |
| 186 | force `CPU.tcu_l2d4_clk_stop = 1'b0; |
| 187 | force `CPU.tcu_l2d5_clk_stop = 1'b0; |
| 188 | force `CPU.tcu_l2d6_clk_stop = 1'b0; |
| 189 | force `CPU.tcu_l2d7_clk_stop = 1'b0; |
| 190 | |
| 191 | force `CPU.tcu_l2t0_clk_stop = 1'b0; |
| 192 | force `CPU.tcu_l2t1_clk_stop = 1'b0; |
| 193 | force `CPU.tcu_l2t2_clk_stop = 1'b0; |
| 194 | force `CPU.tcu_l2t3_clk_stop = 1'b0; |
| 195 | force `CPU.tcu_l2t4_clk_stop = 1'b0; |
| 196 | force `CPU.tcu_l2t5_clk_stop = 1'b0; |
| 197 | force `CPU.tcu_l2t6_clk_stop = 1'b0; |
| 198 | force `CPU.tcu_l2t7_clk_stop = 1'b0; |
| 199 | |
| 200 | force `CPU.tcu_l2b0_clk_stop = 1'b0; |
| 201 | force `CPU.tcu_l2b1_clk_stop = 1'b0; |
| 202 | force `CPU.tcu_l2b2_clk_stop = 1'b0; |
| 203 | force `CPU.tcu_l2b3_clk_stop = 1'b0; |
| 204 | force `CPU.tcu_l2b4_clk_stop = 1'b0; |
| 205 | force `CPU.tcu_l2b5_clk_stop = 1'b0; |
| 206 | force `CPU.tcu_l2b6_clk_stop = 1'b0; |
| 207 | force `CPU.tcu_l2b7_clk_stop = 1'b0; |
| 208 | |
| 209 | force `CPU.tcu_mbist_user_mode = 1'b0; |
| 210 | |
| 211 | force `CPU.tcu_mcu0_clk_stop = 1'b0; |
| 212 | force `CPU.tcu_mcu1_clk_stop = 1'b0; |
| 213 | force `CPU.tcu_mcu2_clk_stop = 1'b0; |
| 214 | force `CPU.tcu_mcu3_clk_stop = 1'b0; |
| 215 | |
| 216 | |
| 217 | force `CPU.tcu_mcu0_dr_clk_stop = 1'b0; |
| 218 | force `CPU.tcu_mcu1_dr_clk_stop = 1'b0; |
| 219 | force `CPU.tcu_mcu2_dr_clk_stop = 1'b0; |
| 220 | force `CPU.tcu_mcu3_dr_clk_stop = 1'b0; |
| 221 | |
| 222 | force `CPU.tcu_mcu0_io_clk_stop = 1'b0; |
| 223 | force `CPU.tcu_mcu1_io_clk_stop = 1'b0; |
| 224 | force `CPU.tcu_mcu2_io_clk_stop = 1'b0; |
| 225 | force `CPU.tcu_mcu3_io_clk_stop = 1'b0; |
| 226 | |
| 227 | force `CPU.tcu_ccx_clk_stop = 1'b0; |
| 228 | force `CPU.tcu_sii_clk_stop = 1'b0; |
| 229 | force `CPU.tcu_sii_io_clk_stop = 1'b0; |
| 230 | force `CPU.tcu_sio_io_clk_stop = 1'b0; |
| 231 | force `CPU.tcu_sio_clk_stop = 1'b0; |
| 232 | force `CPU.tcu_ncu_clk_stop = 1'b0; |
| 233 | force `CPU.tcu_ncu_io_clk_stop = 1'b0; |
| 234 | force `CPU.tcu_efu_io_clk_stop = 1'b0; |
| 235 | force `CPU.tcu_rst_clk_stop = 1'b0; |
| 236 | force `CPU.tcu_rst_io_clk_stop = 1'b0; |
| 237 | force `CPU.tcu_rst_dr_clk_stop = 1'b0; |
| 238 | force `CPU.tcu_dmu_io_clk_stop = 1'b0; |
| 239 | force `CPU.tcu_rdp_io_clk_stop = 1'b0; |
| 240 | force `CPU.tcu_mac_io_clk_stop = 1'b0; |
| 241 | `ifndef FC_NO_NIU_T2 |
| 242 | force `RTX.tcu_rtx_io_clk_stop = 1'b0; |
| 243 | `endif |
| 244 | force `CPU.tcu_tds_io_clk_stop = 1'b0; |
| 245 | force `CPU.tcu_peu_io_clk_stop = 1'b0; |
| 246 | force `CPU.tcu_mio_clk_stop = 1'b0; |
| 247 | force `CPU.tcu_db0_clk_stop = 1'b0; |
| 248 | force `CPU.tcu_db1_clk_stop = 1'b0; |
| 249 | force `CPU.tcu_spc_lbist_scan_in = 8'b0; |
| 250 | |
| 251 | force `CPU.tcu_spc_lbist_pgm = 1'b0; |
| 252 | force `CPU.tcu_spc_test_mode = 1'b0; |
| 253 | force `CPU.tcu.io_test_mode = 1'b0; |
| 254 | force `CPU.tcu_ss_mode = 8'b0; |
| 255 | force `CPU.tcu_do_mode = 8'b0; |
| 256 | force `CPU.tcu_ss_request = 8'b0; |
| 257 | force `CPU.tcu_div_bypass = 1'b0; |
| 258 | |
| 259 | force `CPU.tcu_dectest = 1'b1; |
| 260 | force `CPU.tcu_muxtest = 1'b1; |
| 261 | force `CPU.rst_wmr_protect = 1'b0; |
| 262 | force `CPU.tcu_pce_ov = 1'b0; |
| 263 | force `CPU.tcu_mbist_bisi_en = 1'b0; |
| 264 | force `CPU.tcu_mbist_user_mode = 1'b0; |
| 265 | force `CPU.tcu_spc_shscan_pce_ov = 1'b0; |
| 266 | force `CPU.tcu_spc_shscan_aclk = 1'b0; |
| 267 | force `CPU.tcu_spc_shscan_bclk = 1'b0; |
| 268 | force `CPU.tcu_spc_shscan_scan_en = 1'b0; |
| 269 | force `CPU.tcu_array_wr_inhibit = 1'b0; |
| 270 | force `CPU.tcu_array_bypass = 1'b0; |
| 271 | force `CPU.tcu_scan_en = 1'b0; |
| 272 | force `CPU.tcu_aclk = 1'b0; |
| 273 | force `CPU.tcu_bclk = 1'b0; |
| 274 | force `CPU.tcu_se_scancollar_in = 1'b0; |
| 275 | force `CPU.tcu_se_scancollar_out = 1'b0; |
| 276 | force `CPU.tcu_sii_vld = 1'b0; |
| 277 | |
| 278 | force `CPU.mio.niu_mio_debug_data = 32'b0; |
| 279 | |
| 280 | force `CPU.tcu_dmu_io_clk_stop = 1'b0; |
| 281 | force `CPU.tcu_peu_io_clk_stop = 1'b0; |
| 282 | force `CPU.tcu_peu_pc_clk_stop = 1'b0; |
| 283 | |
| 284 | force `CPU.rst_dmu_peu_por_ = 1'b0; |
| 285 | force `CPU.rst_dmu_peu_wmr_ = 1'b0; |
| 286 | `ifdef AXIS #1 `endif force `CPU.rst_ccu_pll_ = 1'b0; |
| 287 | force `CPU.rst_mio_pex_reset_l = 1'b0; |
| 288 | |
| 289 | force `CPU.ccx.scan_in = 0; |
| 290 | force `CPU.tcu_ccu_clk_stop = 0; |
| 291 | force `CPU.tcu_ccu_io_clk_stop = 0; |
| 292 | |
| 293 | `ifdef GATESIM |
| 294 | force `CPU.ccx.cpx__bfg5_scanout = 1'b0; |
| 295 | `else |
| 296 | force `CPU.ccx.cpx.cpx_dpa_scanin = 1'b0; |
| 297 | `endif |
| 298 | force `CPU.ccx.tcu_pce_ov = 0; |
| 299 | force `CPU.ccx.tcu_aclk = 0; |
| 300 | force `CPU.ccx.tcu_bclk = 0; |
| 301 | |
| 302 | force `CPU.ncu.mio_ncu_ext_int_l = 1'b1; |
| 303 | |
| 304 | force `CPU.ncu_spc_ba01 = 1'b1; |
| 305 | force `CPU.ncu_spc_ba23 = 1'b1; |
| 306 | force `CPU.ncu_spc_ba45 = 1'b1; |
| 307 | force `CPU.ncu_spc_ba67 = 1'b1; |
| 308 | force `CPU.ncu_spc_pm = 1'b0; |
| 309 | force `CPU.ncu_l2t_ba01 = 1'b1; |
| 310 | force `CPU.ncu_l2t_ba23 = 1'b1; |
| 311 | force `CPU.ncu_l2t_ba45 = 1'b1; |
| 312 | force `CPU.ncu_l2t_ba67 = 1'b1; |
| 313 | force `CPU.ncu_l2t_pm = 1'b0; |
| 314 | force `CPU.ncu_sii_ba01 = 1'b1; |
| 315 | force `CPU.ncu_sii_ba23 = 1'b1; |
| 316 | force `CPU.ncu_sii_ba45 = 1'b1; |
| 317 | force `CPU.ncu_sii_ba67 = 1'b1; |
| 318 | force `CPU.ncu_sii_pm = 1'b0; |
| 319 | force `CPU.ncu_mcu_ba01 = 1'b1; |
| 320 | force `CPU.ncu_mcu_ba23 = 1'b1; |
| 321 | force `CPU.ncu_mcu_ba45 = 1'b1; |
| 322 | force `CPU.ncu_mcu_ba67 = 1'b1; |
| 323 | force `CPU.ncu_mcu_pm = 1'b0; |
| 324 | force `CPU.ncu_sii_ba01 = 1'b1; |
| 325 | force `CPU.ncu_sii_ba23 = 1'b1; |
| 326 | force `CPU.ncu_sii_ba45 = 1'b1; |
| 327 | force `CPU.ncu_sii_ba67 = 1'b1; |
| 328 | force `CPU.ncu_sii_pm = 1'b0; |
| 329 | force `CPU.ncu_mcu_ba01 = 1'b1; |
| 330 | force `CPU.ncu_mcu_ba23 = 1'b1; |
| 331 | force `CPU.ncu_mcu_ba45 = 1'b1; |
| 332 | force `CPU.ncu_mcu_ba67 = 1'b1; |
| 333 | force `CPU.ncu_mcu_pm = 1'b0; |
| 334 | |
| 335 | force `CPU.rst_ccu_ = 1; // changed from rst_por_ Mar31'05. |
| 336 | |
| 337 | force `TCU.io_test_mode = 0; |
| 338 | |
| 339 | `ifdef GATESIM |
| 340 | force `CPU.ccx.cpx__bfg5_scanout = 1'b0; |
| 341 | `else |
| 342 | force `CPU.ccx.cpx.cpx_dpa_scanin = 1'b0; |
| 343 | `endif |
| 344 | force `CPU.tcu.tcu_soc0_scan_out = 0; |
| 345 | force `CPU.tcu.tcu_soc1_scan_out = 0; |
| 346 | force `CPU.tcu.tcu_soc2_scan_out = 0; |
| 347 | force `CPU.tcu.tcu_soc3_scan_out = 0; |
| 348 | force `CPU.tcu.tcu_soc4_scan_out = 0; |
| 349 | force `CPU.tcu.tcu_soc5_scan_out = 0; |
| 350 | force `CPU.tcu.tcu_soc6_scan_out = 0; |
| 351 | |
| 352 | |
| 353 | force `CPU.rst_mcu_selfrsh = 0; |
| 354 | |
| 355 | force `CPU.mcu0.scan_in = 1'b0 ; |
| 356 | force `CPU.mcu1.scan_in = 1'b0 ; |
| 357 | force `CPU.mcu2.scan_in = 1'b0 ; |
| 358 | force `CPU.mcu3.scan_in = 1'b0 ; |
| 359 | |
| 360 | `ifndef FC_NO_NIU_T2 |
| 361 | force `TDS.rst_por_ = ~niu_reset; |
| 362 | force `RTX.rst_por_ = ~niu_reset; |
| 363 | force `MAC.gl_mac_ = ~niu_reset; |
| 364 | force `RDP.rst_por_ = ~niu_reset; |
| 365 | |
| 366 | |
| 367 | force `RDP.cluster_arst_l = 1'b1; |
| 368 | force `RTX.cluster_arst_l = 1'b1; |
| 369 | force `TDS.cluster_arst_l = 1'b1; |
| 370 | force `MAC.cluster_arst_l = 1'b1; |
| 371 | `endif |
| 372 | |
| 373 | repeat (20) @(posedge core_clk); |
| 374 | force `CPU.rst_l2_por_ = 1'b1; |
| 375 | release `CPU.ncu.iol2clk ; |
| 376 | release `CPU.ncu.cmp_io_sync_en ; |
| 377 | release `CPU.ncu.io_cmp_sync_en ; |
| 378 | release `CPU.sio.niu_sio_dq; |
| 379 | release `CPU.niu_ncu_vld; |
| 380 | release `CPU.niu_ncu_stall; |
| 381 | |
| 382 | |
| 383 | repeat (20) @(posedge core_clk); |
| 384 | force `CPU.rst_l2_wmr_ = 1'b1; |
| 385 | |
| 386 | force `CPU.rst_ccu_pll_ = 1'b1; |
| 387 | force `CPU.rst_mio_pex_reset_l = 1'b1; |
| 388 | |
| 389 | `ifdef GATESIM |
| 390 | repeat (88) @(posedge `PEU.ca0_l1clkhdr__pcl2clk__col_0__vdd__tcu_scan_en__grp_2_3__l1clk); |
| 391 | `else |
| 392 | repeat (88) @ (posedge `PEU.pcl1clk); |
| 393 | `endif |
| 394 | force `CPU.rst_dmu_peu_wmr_ = 1'b1; |
| 395 | |
| 396 | end |
| 397 | |
| 398 | |
| 399 | |